* [PATCH 078/102] arm64: dts: renesas: r8a7796: Correct whitespace
From: Simon Horman @ 2018-05-18 11:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1526637994.git.horms+renesas@verge.net.au>
From: Geert Uytterhoeven <geert+renesas@glider.be>
Add missing spaces after commas.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index 3fbd86590fb0..6ffab2da07cb 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -143,7 +143,7 @@
};
a57_1: cpu at 1 {
- compatible = "arm,cortex-a57","arm,armv8";
+ compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x1>;
device_type = "cpu";
power-domains = <&sysc R8A7796_PD_CA57_CPU1>;
@@ -166,7 +166,7 @@
};
a53_1: cpu at 101 {
- compatible = "arm,cortex-a53","arm,armv8";
+ compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x101>;
device_type = "cpu";
power-domains = <&sysc R8A7796_PD_CA53_CPU1>;
@@ -177,7 +177,7 @@
};
a53_2: cpu at 102 {
- compatible = "arm,cortex-a53","arm,armv8";
+ compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x102>;
device_type = "cpu";
power-domains = <&sysc R8A7796_PD_CA53_CPU2>;
@@ -188,7 +188,7 @@
};
a53_3: cpu at 103 {
- compatible = "arm,cortex-a53","arm,armv8";
+ compatible = "arm,cortex-a53", "arm,armv8";
reg = <0x103>;
device_type = "cpu";
power-domains = <&sysc R8A7796_PD_CA53_CPU3>;
--
2.11.0
^ permalink raw reply related
* [PATCH 079/102] arm64: dts: renesas: r8a77965: Correct whitespace
From: Simon Horman @ 2018-05-18 11:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1526637994.git.horms+renesas@verge.net.au>
From: Geert Uytterhoeven <geert+renesas@glider.be>
Add missing space after comma.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a77965.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index b93281affd63..ba0edda431a5 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -67,7 +67,7 @@
};
a57_1: cpu at 1 {
- compatible = "arm,cortex-a57","arm,armv8";
+ compatible = "arm,cortex-a57", "arm,armv8";
reg = <0x1>;
device_type = "cpu";
power-domains = <&sysc R8A77965_PD_CA57_CPU1>;
--
2.11.0
^ permalink raw reply related
* [PATCH 080/102] arm64: dts: renesas: ulcb: Add BD9571 PMIC
From: Simon Horman @ 2018-05-18 11:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1526637994.git.horms+renesas@verge.net.au>
From: Geert Uytterhoeven <geert+renesas@glider.be>
Add a device node for the ROHM BD9571MWV PMIC.
This was based on the example in the DT binding documentation, but using
IRQ0 instead of a GPIO interrupt, as that matches the schematics, and
because INTC-EX is a simpler block.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/ulcb.dtsi | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi
index 93402783d52f..ee4249287fbd 100644
--- a/arch/arm64/boot/dts/renesas/ulcb.dtsi
+++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi
@@ -243,6 +243,30 @@
&i2c_dvfs {
status = "okay";
+
+ pmic: pmic at 30 {
+ pinctrl-0 = <&irq0_pins>;
+ pinctrl-names = "default";
+
+ compatible = "rohm,bd9571mwv";
+ reg = <0x30>;
+ interrupt-parent = <&intc_ex>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ regulators {
+ dvfs: dvfs {
+ regulator-name = "dvfs";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1030000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
};
&ohci1 {
@@ -276,6 +300,11 @@
function = "i2c2";
};
+ irq0_pins: irq0 {
+ groups = "intc_ex_irq0";
+ function = "intc_ex";
+ };
+
scif2_pins: scif2 {
groups = "scif2_data_a";
function = "scif2";
--
2.11.0
^ permalink raw reply related
* [PATCH 081/102] arm64: dts: renesas: salvator-common: Add PMIC DDR Backup Power config
From: Simon Horman @ 2018-05-18 11:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1526637994.git.horms+renesas@verge.net.au>
From: Geert Uytterhoeven <geert+renesas@glider.be>
On Salvator-X(S), all of the DDR0, DDR1, DDR0C, and DDR1C power rails
need to be kept powered when backup mode is enabled. Reflect this in
the "rohm,ddr-backup-power" property for the BD9571MWV PMIC node.
The accessory power switch (SW23) is a toggle switch, hence specify
"rohm,rstbmode-level".
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/salvator-common.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
index 803220a02f50..96b51e572666 100644
--- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
@@ -374,6 +374,8 @@
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
+ rohm,ddr-backup-power = <0xf>;
+ rohm,rstbmode-level;
regulators {
dvfs: dvfs {
--
2.11.0
^ permalink raw reply related
* [PATCH 082/102] arm64: dts: renesas: ulcb: Add PMIC DDR Backup Power config
From: Simon Horman @ 2018-05-18 11:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1526637994.git.horms+renesas@verge.net.au>
From: Geert Uytterhoeven <geert+renesas@glider.be>
On the R-Car Starter Kit Premier/Pro, all of the DDR0, DDR1, DDR0C, and
DDR1C power rails need to be kept powered when backup mode is enabled.
Reflect this in the "rohm,ddr-backup-power" property for the BD9571MWV
PMIC node.
The accessory power switch (SW8) is a momentary switch, hense specify
"rohm,rstbmode-pulse".
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/ulcb.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi
index ee4249287fbd..0edb16e6b372 100644
--- a/arch/arm64/boot/dts/renesas/ulcb.dtsi
+++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi
@@ -256,6 +256,8 @@
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
+ rohm,ddr-backup-power = <0xf>;
+ rohm,rstbmode-pulse;
regulators {
dvfs: dvfs {
--
2.11.0
^ permalink raw reply related
* [PATCH 083/102] arm64: dts: renesas: r8a77965: Add SDHI device nodes
From: Simon Horman @ 2018-05-18 11:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1526637994.git.horms+renesas@verge.net.au>
From: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Add SDHI nodes to the DT of the r8a77965 SoC.
Based on several similar patches of the R8A7796 device tree
by Simon Horman <horms+renesas@verge.net.au>.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a77965.dtsi | 36 +++++++++++++++++++++++++++----
1 file changed, 32 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index ba0edda431a5..f51c1b2cbae4 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -978,23 +978,51 @@
};
sdhi0: sd at ee100000 {
+ compatible = "renesas,sdhi-r8a77965",
+ "renesas,rcar-gen3-sdhi";
reg = <0 0xee100000 0 0x2000>;
- /* placeholder */
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 314>;
+ max-frequency = <200000000>;
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 314>;
+ status = "disabled";
};
sdhi1: sd at ee120000 {
+ compatible = "renesas,sdhi-r8a77965",
+ "renesas,rcar-gen3-sdhi";
reg = <0 0xee120000 0 0x2000>;
- /* placeholder */
+ interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 313>;
+ max-frequency = <200000000>;
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 313>;
+ status = "disabled";
};
sdhi2: sd at ee140000 {
+ compatible = "renesas,sdhi-r8a77965",
+ "renesas,rcar-gen3-sdhi";
reg = <0 0xee140000 0 0x2000>;
- /* placeholder */
+ interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 312>;
+ max-frequency = <200000000>;
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 312>;
+ status = "disabled";
};
sdhi3: sd at ee160000 {
+ compatible = "renesas,sdhi-r8a77965",
+ "renesas,rcar-gen3-sdhi";
reg = <0 0xee160000 0 0x2000>;
- /* placeholder */
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 311>;
+ max-frequency = <200000000>;
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 311>;
+ status = "disabled";
};
gic: interrupt-controller at f1010000 {
--
2.11.0
^ permalink raw reply related
* [PATCH 084/102] arm64: dts: renesas: r8a77970: Add secondary CA53 CPU core
From: Simon Horman @ 2018-05-18 11:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1526637994.git.horms+renesas@verge.net.au>
From: Geert Uytterhoeven <geert+renesas@glider.be>
Add a device node for the second Cortex-A53 CPU core on the Renesas
R-Car V3M (r8a77970) SoC, and adjust the interrupt delivery masks for
ARM Generic Interrupt Controller and Architectured Timer.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a77970.dtsi | 20 +++++++++++++++-----
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
index 37b843c0677a..1efaad71804d 100644
--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
@@ -41,6 +41,16 @@
enable-method = "psci";
};
+ a53_1: cpu at 1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <1>;
+ clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>;
+ power-domains = <&sysc R8A77970_PD_CA53_CPU1>;
+ next-level-cache = <&L2_CA53>;
+ enable-method = "psci";
+ };
+
L2_CA53: cache-controller {
compatible = "cache";
power-domains = <&sysc R8A77970_PD_CA53_SCU>;
@@ -635,7 +645,7 @@
<0 0xf1020000 0 0x20000>,
<0 0xf1040000 0 0x20000>,
<0 0xf1060000 0 0x20000>;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD 408>;
clock-names = "clk";
@@ -726,9 +736,9 @@
timer {
compatible = "arm,armv8-timer";
- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
};
--
2.11.0
^ permalink raw reply related
* [PATCH 085/102] arm64: dts: renesas: r8a77970: Add Cortex-A53 PMU node
From: Simon Horman @ 2018-05-18 11:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1526637994.git.horms+renesas@verge.net.au>
From: Geert Uytterhoeven <geert+renesas@glider.be>
Enable the performance monitor unit for the Cortex-A53 cores on the
R-Car V3M (r8a77970) SoC.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a77970.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
index 1efaad71804d..50046405d348 100644
--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
@@ -73,6 +73,13 @@
clock-frequency = <0>;
};
+ pmu_a53 {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&a53_0>, <&a53_1>;
+ };
+
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
--
2.11.0
^ permalink raw reply related
* [PATCH 086/102] arm64: dts: renesas: r8a77980: add resets property to CAN-FD node
From: Simon Horman @ 2018-05-18 11:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1526637994.git.horms+renesas@verge.net.au>
Add resets property to CAN-FD node to describe it in the reset topology of
on-SoC devices. This allows to reset the CAN-FD device using the Reset
Controller API.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
index 3a127643d1dc..32db26f2c8b5 100644
--- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -190,6 +190,7 @@
assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>;
assigned-clock-rates = <40000000>;
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 914>;
status = "disabled";
channel0 {
--
2.11.0
^ permalink raw reply related
* [PATCH 087/102] arm64: dts: renesas: r8a77995: Add VIN4
From: Simon Horman @ 2018-05-18 11:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1526637994.git.horms+renesas@verge.net.au>
From: Jacopo Mondi <jacopo+renesas@jmondi.org>
Describe VIN4 interface for R-Car D3 R8A77995 SoC.
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Acked-by: Niklas S?derlund <niklas.soderlund+renesas@ragnatech.se>
[simon: sorted node by bus address]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
---
arch/arm64/boot/dts/renesas/r8a77995.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77995.dtsi b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
index ba98865b0c9b..2506f46293e8 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77995.dtsi
@@ -610,6 +610,17 @@
status = "disabled";
};
+ vin4: video at e6ef4000 {
+ compatible = "renesas,vin-r8a77995";
+ reg = <0 0xe6ef4000 0 0x1000>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 807>;
+ power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
+ resets = <&cpg 807>;
+ renesas,id = <4>;
+ status = "disabled";
+ };
+
ohci0: usb at ee080000 {
compatible = "generic-ohci";
reg = <0 0xee080000 0 0x100>;
--
2.11.0
^ permalink raw reply related
* [PATCH 088/102] arm64: dts: renesas: r8a77970: disable EtherAVB
From: Simon Horman @ 2018-05-18 11:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1526637994.git.horms+renesas@verge.net.au>
From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
When adding the R8A77970 EtherAVB device I failed to notice that it does
not have the usual "status" property disabling the described devices in
anticipation that the board device trees enable the devices according to
their needs. This causes the EtherAVB driver to successfully probe despite
e.g. the needed pins not having been configured -- luckily, "eth<n>" device
can't be opened anyway...
Fixes: bea2ab136eaa ("arm64: dts: renesas: r8a77970: add EtherAVB support")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a77970.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
index 50046405d348..c8464d1ef1b2 100644
--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
@@ -473,6 +473,7 @@
iommus = <&ipmmu_rt 3>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
scif0: serial at e6e60000 {
--
2.11.0
^ permalink raw reply related
* [PATCH 089/102] arm64: dts: renesas: r8a77980: disable EtherAVB
From: Simon Horman @ 2018-05-18 11:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1526637994.git.horms+renesas@verge.net.au>
From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
When adding the R8A77980 EtherAVB device I failed to notice that it does
not have the usual "status" property disabling the described devices in
anticipation that the board device trees enable the devices according to
their needs. This causes the EtherAVB driver to successfully probe despite
e.g. the needed pins not having been configured -- luckily, "eth<n>" device
can't be opened anyway...
Fixes: bf6f90832f81 ("arm64: dts: renesas: r8a77980: add EtherAVB support")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
index 32db26f2c8b5..4c40f9f0ebc9 100644
--- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -244,6 +244,7 @@
phy-mode = "rgmii";
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
scif0: serial at e6e60000 {
--
2.11.0
^ permalink raw reply related
* [PATCH 090/102] arm64: dts: renesas: initial V3HSK board device tree
From: Simon Horman @ 2018-05-18 11:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1526637994.git.horms+renesas@verge.net.au>
From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Add the initial device tree for the V3H Starter Kit board.
The board has 1 debug serial port (SCIF0); include support for it,
so that the serial console can work.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/Makefile | 2 +-
arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts | 60 ++++++++++++++++++++++++++
2 files changed, 61 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index a235961c6532..9e2394bc3c62 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -9,6 +9,6 @@ dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-m3ulcb-kf.dtb
dtb-$(CONFIG_ARCH_R8A7796) += r8a7796-salvator-xs.dtb
dtb-$(CONFIG_ARCH_R8A77965) += r8a77965-salvator-x.dtb r8a77965-salvator-xs.dtb
dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-eagle.dtb r8a77970-v3msk.dtb
-dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb
+dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb r8a77980-v3hsk.dtb
dtb-$(CONFIG_ARCH_R8A77990) += r8a77990-ebisu.dtb
dtb-$(CONFIG_ARCH_R8A77995) += r8a77995-draak.dtb
diff --git a/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
new file mode 100644
index 000000000000..c9680994555d
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the V3H Starter Kit board
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ * Copyright (C) 2018 Cogent Embedded, Inc.
+ */
+
+/dts-v1/;
+#include "r8a77980.dtsi"
+
+/ {
+ model = "Renesas V3H Starter Kit board";
+ compatible = "renesas,v3hsk", "renesas,r8a77980";
+
+ aliases {
+ serial0 = &scif0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory at 48000000 {
+ device_type = "memory";
+ /* first 128MB is reserved for secure area. */
+ reg = <0 0x48000000 0 0x78000000>;
+ };
+};
+
+&extal_clk {
+ clock-frequency = <16666666>;
+};
+
+&extalr_clk {
+ clock-frequency = <32768>;
+};
+
+&pfc {
+ scif0_pins: scif0 {
+ groups = "scif0_data";
+ function = "scif0";
+ };
+
+ scif_clk_pins: scif_clk {
+ groups = "scif_clk_b";
+ function = "scif_clk";
+ };
+};
+
+&scif0 {
+ pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+};
+
+&scif_clk {
+ clock-frequency = <14745600>;
+};
--
2.11.0
^ permalink raw reply related
* [PATCH 091/102] arm64: dts: renesas: r8a77990: Add PFC device node
From: Simon Horman @ 2018-05-18 11:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1526637994.git.horms+renesas@verge.net.au>
From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
This patch adds PFC device node for r8a77990 (R-Car E3).
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a77990.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index 46580290b7fb..efc3c0ba36c2 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -60,6 +60,11 @@
#size-cells = <2>;
ranges;
+ pfc: pin-controller at e6060000 {
+ compatible = "renesas,pfc-r8a77990";
+ reg = <0 0xe6060000 0 0x508>;
+ };
+
cpg: clock-controller at e6150000 {
compatible = "renesas,r8a77990-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
--
2.11.0
^ permalink raw reply related
* [PATCH 092/102] arm64: dts: renesas: r8a77990: Add GPIO device nodes
From: Simon Horman @ 2018-05-18 11:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1526637994.git.horms+renesas@verge.net.au>
From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
This patch adds GPIO nodes for r8a77990 (R-Car E3).
Based on a patch from Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
[simon: dropped use of deprecated "renesas,gpio-rcar"]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a77990.dtsi | 105 ++++++++++++++++++++++++++++++
1 file changed, 105 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index efc3c0ba36c2..bbc3db50bc01 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -60,6 +60,111 @@
#size-cells = <2>;
ranges;
+ gpio0: gpio at e6050000 {
+ compatible = "renesas,gpio-r8a77990",
+ "renesas,rcar-gen3-gpio";
+ reg = <0 0xe6050000 0 0x50>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 0 18>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 912>;
+ power-domains = <&sysc 32>;
+ resets = <&cpg 912>;
+ };
+
+ gpio1: gpio at e6051000 {
+ compatible = "renesas,gpio-r8a77990",
+ "renesas,rcar-gen3-gpio";
+ reg = <0 0xe6051000 0 0x50>;
+ interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 32 23>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 911>;
+ power-domains = <&sysc 32>;
+ resets = <&cpg 911>;
+ };
+
+ gpio2: gpio at e6052000 {
+ compatible = "renesas,gpio-r8a77990",
+ "renesas,rcar-gen3-gpio";
+ reg = <0 0xe6052000 0 0x50>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 64 26>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 910>;
+ power-domains = <&sysc 32>;
+ resets = <&cpg 910>;
+ };
+
+ gpio3: gpio at e6053000 {
+ compatible = "renesas,gpio-r8a77990",
+ "renesas,rcar-gen3-gpio";
+ reg = <0 0xe6053000 0 0x50>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 96 16>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 909>;
+ power-domains = <&sysc 32>;
+ resets = <&cpg 909>;
+ };
+
+ gpio4: gpio at e6054000 {
+ compatible = "renesas,gpio-r8a77990",
+ "renesas,rcar-gen3-gpio";
+ reg = <0 0xe6054000 0 0x50>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 128 11>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 908>;
+ power-domains = <&sysc 32>;
+ resets = <&cpg 908>;
+ };
+
+ gpio5: gpio at e6055000 {
+ compatible = "renesas,gpio-r8a77990",
+ "renesas,rcar-gen3-gpio";
+ reg = <0 0xe6055000 0 0x50>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 160 20>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 907>;
+ power-domains = <&sysc 32>;
+ resets = <&cpg 907>;
+ };
+
+ gpio6: gpio at e6055400 {
+ compatible = "renesas,gpio-r8a77990",
+ "renesas,rcar-gen3-gpio";
+ reg = <0 0xe6055400 0 0x50>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pfc 0 192 18>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ clocks = <&cpg CPG_MOD 906>;
+ power-domains = <&sysc 32>;
+ resets = <&cpg 906>;
+ };
+
pfc: pin-controller at e6060000 {
compatible = "renesas,pfc-r8a77990";
reg = <0 0xe6060000 0 0x508>;
--
2.11.0
^ permalink raw reply related
* [PATCH 093/102] arm64: dts: renesas: r8a77990: Add EthernetAVB device nodes
From: Simon Horman @ 2018-05-18 11:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1526637994.git.horms+renesas@verge.net.au>
From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
This patch adds EthernetAVB node for r8a77990 (R-Car E3).
Based on a patch from Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a77990.dtsi | 45 +++++++++++++++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
index bbc3db50bc01..be4f519711a1 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi
@@ -191,6 +191,51 @@
#power-domain-cells = <1>;
};
+ avb: ethernet at e6800000 {
+ compatible = "renesas,etheravb-r8a77990",
+ "renesas,etheravb-rcar-gen3";
+ reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14", "ch15",
+ "ch16", "ch17", "ch18", "ch19",
+ "ch20", "ch21", "ch22", "ch23",
+ "ch24";
+ clocks = <&cpg CPG_MOD 812>;
+ power-domains = <&sysc 32>;
+ resets = <&cpg 812>;
+ phy-mode = "rgmii";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
scif2: serial at e6e88000 {
compatible = "renesas,scif-r8a77990",
"renesas,rcar-gen3-scif", "renesas,scif";
--
2.11.0
^ permalink raw reply related
* [PATCH 094/102] arm64: dts: renesas: r8a77990: ebisu: Enable EthernetAVB
From: Simon Horman @ 2018-05-18 11:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1526637994.git.horms+renesas@verge.net.au>
From: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
This patch enables EthernetAVB for r8a77990 Ebisu board.
Based on a patch from Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts | 28 ++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
index 63ee1347bb19..7a09d0524f9b 100644
--- a/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
@@ -7,6 +7,7 @@
/dts-v1/;
#include "r8a77990.dtsi"
+#include <dt-bindings/gpio/gpio.h>
/ {
model = "Renesas Ebisu board based on r8a77990";
@@ -14,6 +15,7 @@
aliases {
serial0 = &scif2;
+ ethernet0 = &avb;
};
chosen {
@@ -28,10 +30,36 @@
};
};
+&avb {
+ pinctrl-0 = <&avb_pins>;
+ pinctrl-names = "default";
+ renesas,no-ether-link;
+ phy-handle = <&phy0>;
+ phy-mode = "rgmii-txid";
+ status = "okay";
+
+ phy0: ethernet-phy at 0 {
+ rxc-skew-ps = <1500>;
+ reg = <0>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
+ reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
+ };
+};
+
&extal_clk {
clock-frequency = <48000000>;
};
+&pfc {
+ avb_pins: avb {
+ mux {
+ groups = "avb_link", "avb_mii";
+ function = "avb";
+ };
+ };
+};
+
&scif2 {
status = "okay";
};
--
2.11.0
^ permalink raw reply related
* [PATCH 095/102] arm64: dts: renesas: r8a77965: add I2C support
From: Simon Horman @ 2018-05-18 11:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1526637994.git.horms+renesas@verge.net.au>
From: Niklas S?derlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Niklas S?derlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a77965.dtsi | 99 ++++++++++++++++++++++++++++---
1 file changed, 90 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index f51c1b2cbae4..1f67aea49305 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -20,6 +20,13 @@
#size-cells = <2>;
aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
i2c7 = &i2c_dvfs;
};
@@ -314,44 +321,118 @@
};
i2c0: i2c at e6500000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a77965",
+ "renesas,rcar-gen3-i2c";
reg = <0 0xe6500000 0 0x40>;
- /* placeholder */
+ interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 931>;
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 931>;
+ dmas = <&dmac1 0x91>, <&dmac1 0x90>,
+ <&dmac2 0x91>, <&dmac2 0x90>;
+ dma-names = "tx", "rx", "tx", "rx";
+ i2c-scl-internal-delay-ns = <110>;
+ status = "disabled";
};
i2c1: i2c at e6508000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a77965",
+ "renesas,rcar-gen3-i2c";
reg = <0 0xe6508000 0 0x40>;
- /* placeholder */
+ interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 930>;
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 930>;
+ dmas = <&dmac1 0x93>, <&dmac1 0x92>,
+ <&dmac2 0x93>, <&dmac2 0x92>;
+ dma-names = "tx", "rx", "tx", "rx";
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
};
i2c2: i2c at e6510000 {
#address-cells = <1>;
#size-cells = <0>;
-
+ compatible = "renesas,i2c-r8a77965",
+ "renesas,rcar-gen3-i2c";
reg = <0 0xe6510000 0 0x40>;
- /* placeholder */
+ interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 929>;
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 929>;
+ dmas = <&dmac1 0x95>, <&dmac1 0x94>,
+ <&dmac2 0x95>, <&dmac2 0x94>;
+ dma-names = "tx", "rx", "tx", "rx";
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
};
i2c3: i2c at e66d0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a77965",
+ "renesas,rcar-gen3-i2c";
reg = <0 0xe66d0000 0 0x40>;
- /* placeholder */
+ interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 928>;
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 928>;
+ dmas = <&dmac0 0x97>, <&dmac0 0x96>;
+ dma-names = "tx", "rx";
+ i2c-scl-internal-delay-ns = <110>;
+ status = "disabled";
};
i2c4: i2c at e66d8000 {
#address-cells = <1>;
#size-cells = <0>;
-
+ compatible = "renesas,i2c-r8a77965",
+ "renesas,rcar-gen3-i2c";
reg = <0 0xe66d8000 0 0x40>;
- /* placeholder */
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 927>;
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 927>;
+ dmas = <&dmac0 0x99>, <&dmac0 0x98>;
+ dma-names = "tx", "rx";
+ i2c-scl-internal-delay-ns = <110>;
+ status = "disabled";
};
i2c5: i2c at e66e0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a77965",
+ "renesas,rcar-gen3-i2c";
reg = <0 0xe66e0000 0 0x40>;
- /* placeholder */
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 919>;
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 919>;
+ dmas = <&dmac0 0x9b>, <&dmac0 0x9a>;
+ dma-names = "tx", "rx";
+ i2c-scl-internal-delay-ns = <110>;
+ status = "disabled";
};
i2c6: i2c at e66e8000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "renesas,i2c-r8a77965",
+ "renesas,rcar-gen3-i2c";
reg = <0 0xe66e8000 0 0x40>;
- /* placeholder */
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 918>;
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 918>;
+ dmas = <&dmac0 0x9d>, <&dmac0 0x9c>;
+ dma-names = "tx", "rx";
+ i2c-scl-internal-delay-ns = <6>;
+ status = "disabled";
};
i2c_dvfs: i2c at e60b0000 {
--
2.11.0
^ permalink raw reply related
* [PATCH 096/102] arm64: dts: renesas: r8a7795: add VIN and CSI-2 nodes
From: Simon Horman @ 2018-05-18 11:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1526637994.git.horms+renesas@verge.net.au>
From: Niklas S?derlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Niklas S?derlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 389 +++++++++++++++++++++++++++++++
1 file changed, 389 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
index 91486b4910ce..d842940b2f43 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi
@@ -1397,6 +1397,262 @@
status = "disabled";
};
+ vin0: video at e6ef0000 {
+ compatible = "renesas,vin-r8a7795";
+ reg = <0 0xe6ef0000 0 0x1000>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 811>;
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 811>;
+ renesas,id = <0>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin0csi20: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint= <&csi20vin0>;
+ };
+ vin0csi40: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin0>;
+ };
+ };
+ };
+ };
+
+ vin1: video at e6ef1000 {
+ compatible = "renesas,vin-r8a7795";
+ reg = <0 0xe6ef1000 0 0x1000>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 810>;
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 810>;
+ renesas,id = <1>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin1csi20: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint= <&csi20vin1>;
+ };
+ vin1csi40: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin1>;
+ };
+ };
+ };
+ };
+
+ vin2: video at e6ef2000 {
+ compatible = "renesas,vin-r8a7795";
+ reg = <0 0xe6ef2000 0 0x1000>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 809>;
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 809>;
+ renesas,id = <2>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin2csi20: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint= <&csi20vin2>;
+ };
+ vin2csi40: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin2>;
+ };
+ };
+ };
+ };
+
+ vin3: video at e6ef3000 {
+ compatible = "renesas,vin-r8a7795";
+ reg = <0 0xe6ef3000 0 0x1000>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 808>;
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 808>;
+ renesas,id = <3>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin3csi20: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint= <&csi20vin3>;
+ };
+ vin3csi40: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin3>;
+ };
+ };
+ };
+ };
+
+ vin4: video at e6ef4000 {
+ compatible = "renesas,vin-r8a7795";
+ reg = <0 0xe6ef4000 0 0x1000>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 807>;
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 807>;
+ renesas,id = <4>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin4csi20: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint= <&csi20vin4>;
+ };
+ vin4csi41: endpoint at 3 {
+ reg = <3>;
+ remote-endpoint= <&csi41vin4>;
+ };
+ };
+ };
+ };
+
+ vin5: video at e6ef5000 {
+ compatible = "renesas,vin-r8a7795";
+ reg = <0 0xe6ef5000 0 0x1000>;
+ interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 806>;
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 806>;
+ renesas,id = <5>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin5csi20: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint= <&csi20vin5>;
+ };
+ vin5csi41: endpoint at 3 {
+ reg = <3>;
+ remote-endpoint= <&csi41vin5>;
+ };
+ };
+ };
+ };
+
+ vin6: video at e6ef6000 {
+ compatible = "renesas,vin-r8a7795";
+ reg = <0 0xe6ef6000 0 0x1000>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 805>;
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 805>;
+ renesas,id = <6>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin6csi20: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint= <&csi20vin6>;
+ };
+ vin6csi41: endpoint at 3 {
+ reg = <3>;
+ remote-endpoint= <&csi41vin6>;
+ };
+ };
+ };
+ };
+
+ vin7: video at e6ef7000 {
+ compatible = "renesas,vin-r8a7795";
+ reg = <0 0xe6ef7000 0 0x1000>;
+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 804>;
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 804>;
+ renesas,id = <7>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin7csi20: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint= <&csi20vin7>;
+ };
+ vin7csi41: endpoint at 3 {
+ reg = <3>;
+ remote-endpoint= <&csi41vin7>;
+ };
+ };
+ };
+ };
+
drif00: rif at e6f40000 {
compatible = "renesas,r8a7795-drif",
"renesas,rcar-gen3-drif";
@@ -2327,6 +2583,139 @@
renesas,fcp = <&fcpvi1>;
};
+ csi20: csi2 at fea80000 {
+ compatible = "renesas,r8a7795-csi2";
+ reg = <0 0xfea80000 0 0x10000>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 714>;
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 714>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ csi20vin0: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint = <&vin0csi20>;
+ };
+ csi20vin1: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint = <&vin1csi20>;
+ };
+ csi20vin2: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint = <&vin2csi20>;
+ };
+ csi20vin3: endpoint at 3 {
+ reg = <3>;
+ remote-endpoint = <&vin3csi20>;
+ };
+ csi20vin4: endpoint at 4 {
+ reg = <4>;
+ remote-endpoint = <&vin4csi20>;
+ };
+ csi20vin5: endpoint at 5 {
+ reg = <5>;
+ remote-endpoint = <&vin5csi20>;
+ };
+ csi20vin6: endpoint at 6 {
+ reg = <6>;
+ remote-endpoint = <&vin6csi20>;
+ };
+ csi20vin7: endpoint at 7 {
+ reg = <7>;
+ remote-endpoint = <&vin7csi20>;
+ };
+ };
+ };
+ };
+
+ csi40: csi2 at feaa0000 {
+ compatible = "renesas,r8a7795-csi2";
+ reg = <0 0xfeaa0000 0 0x10000>;
+ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 716>;
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 716>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ csi40vin0: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint = <&vin0csi40>;
+ };
+ csi40vin1: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint = <&vin1csi40>;
+ };
+ csi40vin2: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint = <&vin2csi40>;
+ };
+ csi40vin3: endpoint at 3 {
+ reg = <3>;
+ remote-endpoint = <&vin3csi40>;
+ };
+ };
+ };
+ };
+
+ csi41: csi2 at feab0000 {
+ compatible = "renesas,r8a7795-csi2";
+ reg = <0 0xfeab0000 0 0x10000>;
+ interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 715>;
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 715>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ csi41vin4: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint = <&vin4csi41>;
+ };
+ csi41vin5: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint = <&vin5csi41>;
+ };
+ csi41vin6: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint = <&vin6csi41>;
+ };
+ csi41vin7: endpoint at 3 {
+ reg = <3>;
+ remote-endpoint = <&vin7csi41>;
+ };
+ };
+ };
+ };
+
hdmi0: hdmi at fead0000 {
compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi";
reg = <0 0xfead0000 0 0x10000>;
--
2.11.0
^ permalink raw reply related
* [PATCH 097/102] arm64: dts: renesas: r8a7795-es1: add CSI-2 node
From: Simon Horman @ 2018-05-18 11:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1526637994.git.horms+renesas@verge.net.au>
From: Niklas S?derlund <niklas.soderlund+renesas@ragnatech.se>
Renesas H3 ES1.0 have one extra CSI-2 node, CSI21 which is not present
for later ES versions of H3.
Signed-off-by: Niklas S?derlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi | 143 +++++++++++++++++++++++++++
1 file changed, 143 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
index 0177f5e60e5a..e19dcd6cb767 100644
--- a/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi
@@ -107,6 +107,61 @@
resets = <&cpg 117>;
renesas,fcp = <&fcpf2>;
};
+
+ csi21: csi2 at fea90000 {
+ compatible = "renesas,r8a7795-csi2";
+ reg = <0 0xfea90000 0 0x10000>;
+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 713>;
+ power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
+ resets = <&cpg 713>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ csi21vin0: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint = <&vin0csi21>;
+ };
+ csi21vin1: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint = <&vin1csi21>;
+ };
+ csi21vin2: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint = <&vin2csi21>;
+ };
+ csi21vin3: endpoint at 3 {
+ reg = <3>;
+ remote-endpoint = <&vin3csi21>;
+ };
+ csi21vin4: endpoint at 4 {
+ reg = <4>;
+ remote-endpoint = <&vin4csi21>;
+ };
+ csi21vin5: endpoint at 5 {
+ reg = <5>;
+ remote-endpoint = <&vin5csi21>;
+ };
+ csi21vin6: endpoint at 6 {
+ reg = <6>;
+ remote-endpoint = <&vin6csi21>;
+ };
+ csi21vin7: endpoint at 7 {
+ reg = <7>;
+ remote-endpoint = <&vin7csi21>;
+ };
+ };
+ };
+ };
};
&gpio1 {
@@ -174,3 +229,91 @@
&du {
vsps = <&vspd0 &vspd1 &vspd2 &vspd3>;
};
+
+&vin0 {
+ ports {
+ port at 1 {
+ vin0csi21: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint= <&csi21vin0>;
+ };
+ };
+ };
+};
+
+&vin1 {
+ ports {
+ port at 1 {
+ vin1csi21: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint= <&csi21vin1>;
+ };
+ };
+ };
+};
+
+&vin2 {
+ ports {
+ port at 1 {
+ vin2csi21: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint= <&csi21vin2>;
+ };
+ };
+ };
+};
+
+&vin3 {
+ ports {
+ port at 1 {
+ vin3csi21: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint= <&csi21vin3>;
+ };
+ };
+ };
+};
+
+&vin4 {
+ ports {
+ port at 1 {
+ vin4csi21: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint= <&csi21vin4>;
+ };
+ };
+ };
+};
+
+&vin5 {
+ ports {
+ port at 1 {
+ vin5csi21: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint= <&csi21vin5>;
+ };
+ };
+ };
+};
+
+&vin6 {
+ ports {
+ port at 1 {
+ vin6csi21: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint= <&csi21vin6>;
+ };
+ };
+ };
+};
+
+&vin7 {
+ ports {
+ port at 1 {
+ vin7csi21: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint= <&csi21vin7>;
+ };
+ };
+ };
+};
--
2.11.0
^ permalink raw reply related
* [PATCH 098/102] arm64: dts: renesas: r8a7796: add VIN and CSI-2 nodes
From: Simon Horman @ 2018-05-18 11:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1526637994.git.horms+renesas@verge.net.au>
From: Niklas S?derlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Niklas S?derlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 367 +++++++++++++++++++++++++++++++
1 file changed, 367 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index 6ffab2da07cb..7c25be6b5af3 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -1280,6 +1280,262 @@
status = "disabled";
};
+ vin0: video at e6ef0000 {
+ compatible = "renesas,vin-r8a7796";
+ reg = <0 0xe6ef0000 0 0x1000>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 811>;
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 811>;
+ renesas,id = <0>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin0csi20: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint= <&csi20vin0>;
+ };
+ vin0csi40: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin0>;
+ };
+ };
+ };
+ };
+
+ vin1: video at e6ef1000 {
+ compatible = "renesas,vin-r8a7796";
+ reg = <0 0xe6ef1000 0 0x1000>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 810>;
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 810>;
+ renesas,id = <1>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin1csi20: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint= <&csi20vin1>;
+ };
+ vin1csi40: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin1>;
+ };
+ };
+ };
+ };
+
+ vin2: video at e6ef2000 {
+ compatible = "renesas,vin-r8a7796";
+ reg = <0 0xe6ef2000 0 0x1000>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 809>;
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 809>;
+ renesas,id = <2>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin2csi20: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint= <&csi20vin2>;
+ };
+ vin2csi40: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin2>;
+ };
+ };
+ };
+ };
+
+ vin3: video at e6ef3000 {
+ compatible = "renesas,vin-r8a7796";
+ reg = <0 0xe6ef3000 0 0x1000>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 808>;
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 808>;
+ renesas,id = <3>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin3csi20: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint= <&csi20vin3>;
+ };
+ vin3csi40: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin3>;
+ };
+ };
+ };
+ };
+
+ vin4: video at e6ef4000 {
+ compatible = "renesas,vin-r8a7796";
+ reg = <0 0xe6ef4000 0 0x1000>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 807>;
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 807>;
+ renesas,id = <4>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin4csi20: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint= <&csi20vin4>;
+ };
+ vin4csi40: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin4>;
+ };
+ };
+ };
+ };
+
+ vin5: video at e6ef5000 {
+ compatible = "renesas,vin-r8a7796";
+ reg = <0 0xe6ef5000 0 0x1000>;
+ interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 806>;
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 806>;
+ renesas,id = <5>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin5csi20: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint= <&csi20vin5>;
+ };
+ vin5csi40: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin5>;
+ };
+ };
+ };
+ };
+
+ vin6: video at e6ef6000 {
+ compatible = "renesas,vin-r8a7796";
+ reg = <0 0xe6ef6000 0 0x1000>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 805>;
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 805>;
+ renesas,id = <6>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin6csi20: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint= <&csi20vin6>;
+ };
+ vin6csi40: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin6>;
+ };
+ };
+ };
+ };
+
+ vin7: video at e6ef7000 {
+ compatible = "renesas,vin-r8a7796";
+ reg = <0 0xe6ef7000 0 0x1000>;
+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 804>;
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 804>;
+ renesas,id = <7>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin7csi20: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint= <&csi20vin7>;
+ };
+ vin7csi40: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin7>;
+ };
+ };
+ };
+ };
+
drif00: rif at e6f40000 {
compatible = "renesas,r8a7796-drif",
"renesas,rcar-gen3-drif";
@@ -1998,6 +2254,117 @@
renesas,fcp = <&fcpvi0>;
};
+ csi20: csi2 at fea80000 {
+ compatible = "renesas,r8a7796-csi2";
+ reg = <0 0xfea80000 0 0x10000>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 714>;
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 714>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ csi20vin0: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint = <&vin0csi20>;
+ };
+ csi20vin1: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint = <&vin1csi20>;
+ };
+ csi20vin2: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint = <&vin2csi20>;
+ };
+ csi20vin3: endpoint at 3 {
+ reg = <3>;
+ remote-endpoint = <&vin3csi20>;
+ };
+ csi20vin4: endpoint at 4 {
+ reg = <4>;
+ remote-endpoint = <&vin4csi20>;
+ };
+ csi20vin5: endpoint at 5 {
+ reg = <5>;
+ remote-endpoint = <&vin5csi20>;
+ };
+ csi20vin6: endpoint at 6 {
+ reg = <6>;
+ remote-endpoint = <&vin6csi20>;
+ };
+ csi20vin7: endpoint at 7 {
+ reg = <7>;
+ remote-endpoint = <&vin7csi20>;
+ };
+ };
+ };
+ };
+
+ csi40: csi2 at feaa0000 {
+ compatible = "renesas,r8a7796-csi2";
+ reg = <0 0xfeaa0000 0 0x10000>;
+ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 716>;
+ power-domains = <&sysc R8A7796_PD_ALWAYS_ON>;
+ resets = <&cpg 716>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ csi40vin0: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint = <&vin0csi40>;
+ };
+ csi40vin1: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint = <&vin1csi40>;
+ };
+ csi40vin2: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint = <&vin2csi40>;
+ };
+ csi40vin3: endpoint at 3 {
+ reg = <3>;
+ remote-endpoint = <&vin3csi40>;
+ };
+ csi40vin4: endpoint at 4 {
+ reg = <4>;
+ remote-endpoint = <&vin4csi40>;
+ };
+ csi40vin5: endpoint at 5 {
+ reg = <5>;
+ remote-endpoint = <&vin5csi40>;
+ };
+ csi40vin6: endpoint at 6 {
+ reg = <6>;
+ remote-endpoint = <&vin6csi40>;
+ };
+ csi40vin7: endpoint at 7 {
+ reg = <7>;
+ remote-endpoint = <&vin7csi40>;
+ };
+ };
+
+ };
+ };
+
hdmi0: hdmi at fead0000 {
compatible = "renesas,r8a7796-hdmi", "renesas,rcar-gen3-hdmi";
reg = <0 0xfead0000 0 0x10000>;
--
2.11.0
^ permalink raw reply related
* [GIT PULL] Renesas ARM64 Based SoC DT Updates for v4.18
From: Simon Horman @ 2018-05-18 11:16 UTC (permalink / raw)
To: linux-arm-kernel
Hi Olof, Hi Kevin, Hi Arnd,
Please consider these Renesas ARM64 based SoC DT updates for v4.18.
The following changes since commit 60cc43fc888428bb2f18f08997432d426a243338:
Linux 4.17-rc1 (2018-04-15 18:24:20 -0700)
are available in the git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-arm64-dt-for-v4.18
for you to fetch changes up to 908001d778eba06ee1d832863d4e9a1e2cfd4746:
arm64: dts: renesas: salvator-common: Add ADV7482 support (2018-05-18 11:52:03 +0200)
----------------------------------------------------------------
Renesas ARM64 Based SoC DT Updates for v4.18
* Cleanups:
- Corresct whitespace
- sort subnodes of the root and soc nodes
* R-Car M3-N (r8a77965) SoC
- Describe MSIOF SPI, PWM, SDHI and I2C devices in DT
- Add thermal support
* R-Car H3 (r8a7795) and R-Car M3-W (r8a7796) SoCs
- Decrease temperature hysteresis
Niklas S?derlund says "... decrease the hysteresis from 2C to 1C for
the two boards we have described upstream. They have no dependencies
and are ready to be accepted if the review is in favor of them."
* R-Car H3 (r8a7795), M3-W (r8a7796) and M3-N (r8a77965) SoCs
- Add address properties to rcar_sound port nodes
The rcar_sound port nodes have unit names and thus should have register
properties.
* R-Car H3 (r8a7795), M3-W (r8a7796) V3M (r8a77970) and D3 (r8a77995) SoCs
- Enable IPMMU devices
Magnus Damm says "Following the policy of using DT to describe the
hardware and not software support state, this series makes sure all
IPMMU devices are enabled in DT for SoCs such as r8a7795, r8a7796,
r8a77970 and r8a77995."
* R-Car M3-N (r8a77965) and V3H (r8a77980) SoCs
- Use sysc binding macros
These can be used now that they are present in Linus's tree.
This is a simple replacement of numeric values with symbolic ones.
- Describe USB2 and USB3 devices in DT
* R-Car V3M (r8a77970) SoC
- Add SMP Support
Geert Uytterhoeven says "This patch series enables SMP support on the
R-Car V3M SoC, by adding the second Cortex-A53 CPU core. It also adds
the performance monitor unit, and links it to both CPU cores."
- Correct IPMMU DS1 bit number
Magnus Damm says "Judging by "R-Car-Gen3-rev0.80" IPMMU IMSSTR register
documentation for [R-Car V3M] the DS1 bit field should be bit 0."
* R-Car V3H (r8a77980) SoC
- Use CPG clock binding macros
These can be used now that they are present in Linus's tree.
This is a simple replacement of numeric values with symbolic ones.
* R-Car V3H (r8a77980) and V3M (r8a77970) SoCs
- Disable EtherAVB
Sergei Shtylov says "I'm fixing the issue in the EtherAVB device nodes
in the R8A779{7|8}0 device trees that missed the "status" prop, usually
disabling the SoC devices in anticipation that the board device trees
enable the devices according to their needs. There should be no issues
with the current R8A779{7|8}0 board device trees, as all of them use
EtherAVB anyway, so I'm sending the patches generated against the
'devel' branch..."
* R-Car D3 (r8a77995) SoC
- Describe VIN4 in DT
* Ebisu board with R-Car E3 (r8a77990) SoC
- Initial support:
+ PSCI
+ CPU (single)
+ Cache controller
+ Main clocks and controller
+ Interrupt controller
+ Timer
+ PMU
+ Reset controller
+ Product register
+ System controller
+ UART for console
* Salvator-XS boards with R-Car H3 (r8a7795) SoC
- Enable USB2.0 channel 3
* Salvator-X and Salvator-XS boards with M3-N (r8a77965) SoC
- Enable DU
Kieran Bingham "This series enables the DU for the M3-N R8A77965 SoC,
and provides output on the VGA and HDMI connectors.
LVDS is not yet supported or tested."
* Salvator-X and Salvator-XS boards with
R-Car H3 (r8a7795), M3-W (r8a7796) and M3-N (r8a77965) SoCs
- Enable nable VIN, CSI-2 and ADV7482
Niklas S?derlund says "This series enable capture for H3, M3-W, M3-N
Salvator-X and Salvator-XS boards. It also adds the VIN and CSI-2 nodes
for V3M, but as the ADV7482 is on the V3M expansion boards I have
chosen not include that enablement in this series."
- Add PMIC DDR Backup Power config
Geert Uytterhoeven says " The ROHM BD9571MWV PMIC on the Renesas
Salvator-X(S) and ULCB development boards supports DDR Backup Power,
which means that the DDR power rails can be kept powered while the main
SoC is powered down.
For this to function correctly, the DDR Backup Power configuration
must be described in DT, which is the topic of this series:
- The first patch adds the missing device node for the BD9571 PMIC on
the ULCB boards,
- The last two patches add DDR Backup Mode configuration for
Salvator-X(S) and ULCB."
- Add EEPROM
Wolfram Sang says "Add the EEPROM found on Salvator-X and -XS boards
for H3, M3-W, and M3-N on the IIC_DVFS bus."
- Enable HDMI Sound
* Salvator-X and Salvator-XS boards with
R-Car H3 (r8a7795), M3-W (r8a7796) and M3-N (r8a77965) SoCs, and
Draak board with R-Car D3 (r8a77995) SoC
- Consistently name EtherAVB mdio pin group
Geert Uytterhoeven says "When initial support was added for R-Car H3,
the MDIO pin was forgotten, and the MDC pin got its own group named
"mdc". During the addition of support for R-Car M3-W, this mistake was
noticed. But as R-Car H3 and M3-W are pin compatible, and can be
mounted on the same boards, the decision was made to just add the MDIO
pin to the existing "mdc" group. Later this was extended to R-Car H3
ES2.0, and M3-N, because of pin compatibility, and to R-Car D3, in the
name of consistency among R-Car Gen3 SoCs.
However, this decision keeps on being questioned when adding new SoC
support. Hence bite the bullet and admit our mistake, and rename the
pin group from "mdc" to "mdio", like on R-Car Gen2 SoCs."
* Ebisu board with R-Car E3 (r8a77990) SoC
- Initial support: Memory, Main crystal, Serial console
- Enable Ethernet
- Revise PSCI node
Yoshihiro Shimoda says "The basic support patch 2d2dbadba421 ("arm64:
dts: renesas: Add Renesas R8A77990 SoC support") lacks the compatible
"arm,psci-1.0" in the psci node."
- Revise cache controller node
Yoshihiro Shimoda says "The cache controller node should not have
unit-addresses and reg properties."
* V3HSK board with R-Car V3H (r8a77980) SoC
- Initial board device tree
Sergei Shtylov says "Add the initial device tree for the V3H Starter
Kit board. The board has 1 debug serial port (SCIF0); include support
for it, so that the serial console can work."
- Enable PFC support and use for EtherAVB
* V3MSK board with R-Car V3M (r8a77970) SoC
- Add DU/LVDS/HDMI support
Sergei Shtylyov says "Define the V3M Starter Kit board dependent part
of the DU and LVDS device nodes. Also add the device nodes for Thine
THC63LVD1024 LVDS decoder and Analog Devices ADV7511W HDMI
transmitter..."
- Enable PFC for EtherAVB
* Condor board with R-Car V3H (r8a77980) SoC
- Enable eMMC
Sergei Shtylyov says "We're adding the R8A77980 MMC (SDHI)
device nodes and then enable eMMC support on the Condor board."
- Enable PFC support and use for EtherAVB and SCIF0
* Eagle board with R-Car V3M (r8a77970) SoC
- Enable HDMI output
* Eagle board with R-Car V3M (r8a77970) SoC and
Condor board with R-Car V3H (r8a77980) SoC
- Enable CAN-FD
Adds the CAN-FD device nodes so the DT SoC files and enables
single channel CAN-FD support in DT board files.
----------------------------------------------------------------
Geert Uytterhoeven (11):
arm64: dts: renesas: draak: Rename EtherAVB "mdc" pin group to "mdio"
arm64: dts: renesas: salvator-common: Rename EtherAVB "mdc" pin group to "mdio"
arm64: dts: renesas: ulcb: Rename EtherAVB "mdc" pin group to "mdio"
arm64: dts: renesas: r8a7795: Correct whitespace
arm64: dts: renesas: r8a7796: Correct whitespace
arm64: dts: renesas: r8a77965: Correct whitespace
arm64: dts: renesas: ulcb: Add BD9571 PMIC
arm64: dts: renesas: salvator-common: Add PMIC DDR Backup Power config
arm64: dts: renesas: ulcb: Add PMIC DDR Backup Power config
arm64: dts: renesas: r8a77970: Add secondary CA53 CPU core
arm64: dts: renesas: r8a77970: Add Cortex-A53 PMU node
Jacopo Mondi (2):
arm64: dts: renesas: eagle: Enable HDMI output
arm64: dts: renesas: r8a77995: Add VIN4
Kieran Bingham (7):
arm64: dts: renesas: r8a77965: Add FCPF and FCPV instances
arm64: dts: renesas: r8a77965: Add VSP instances
arm64: dts: renesas: r8a77965: Populate the DU instance placeholder
arm64: dts: renesas: r8a77965: Add HDMI encoder instance
arm64: dts: renesas: r8a77965-salvator-x: Enable DU external clocks and HDMI
arm64: dts: renesas: r8a77965-salvator-xs: Enable DU external clocks and HDMI
arm64: dts: renesas: salvator-common: Add ADV7482 support
Kuninori Morimoto (8):
arm64: dts: renesas: r8a7795: add HDMI sound support
arm64: dts: renesas: r8a7796: add HDMI sound support
arm64: dts: renesas: salvator-common: use audio-graph-card for Sound
arm64: dts: renesas: r8a7795-es1-salvator-x: enable HDMI sound
arm64: dts: renesas: r8a7795-salvator-xs: enable HDMI sound
arm64: dts: renesas: r8a7796-salvator-xs: enable HDMI sound
arm64: dts: renesas: r8a7795-salvator-x: enable HDMI sound
arm64: dts: renesas: r8a7796-salvator-x: enable HDMI sound
Magnus Damm (5):
arm64: dts: renesas: r8a77970: Update IPMMU DS1 bit number
arm64: dts: renesas: r8a7795: Enable IPMMU devices
arm64: dts: renesas: r8a7796: Enable IPMMU devices
arm64: dts: renesas: r8a77970: Enable IPMMU devices
arm64: dts: renesas: r8a77995: Enable IPMMU devices
Niklas S?derlund (11):
arm64: dts: renesas: r8a7795: decrease temperature hysteresis
arm64: dts: renesas: r8a7796: decrease temperature hysteresis
arm64: dts: renesas: r8a77965: use r8a77965-sysc binding definitions
arm64: dts: renesas: r8a77965: Add R-Car Gen3 thermal support
arm64: dts: renesas: r8a77965: add I2C support
arm64: dts: renesas: r8a7795: add VIN and CSI-2 nodes
arm64: dts: renesas: r8a7795-es1: add CSI-2 node
arm64: dts: renesas: r8a7796: add VIN and CSI-2 nodes
arm64: dts: renesas: r8a77965: add VIN and CSI-2 nodes
arm64: dts: renesas: r8a77970: add VIN and CSI-2 nodes
arm64: dts: renesas: salvator-common: enable VIN
Sergei Shtylyov (21):
arm64: dts: renesas: r8a77970: add FCPVD support
arm64: dts: renesas: r8a77970: add VSPD support
arm64: dts: renesas: r8a77970: add DU support
arm64: dts: renesas: r8a77970: add LVDS support
arm64: dts: renesas: eagle: add EtherAVB pins
arm64: dts: renesas: v3msk: add EtherAVB pins
arm64: dts: renesas: r8a77980: add PFC support
arm64: dts: renesas: condor: add SCIF0 pins
arm64: dts: renesas: condor: add EtherAVB pins
arm64: dts: renesas: r8a77980: add MMC support
arm64: dts: renesas: condor: add eMMC support
arm64: dts: renesas: v3msk: add DU/LVDS/HDMI support
arm64: dts: renesas: r8a77980: use CPG core clock macros
arm64: dts: renesas: r8a77980: use SYSC power domain macros
arm64: dts: renesas: r8a77970: add CAN-FD support
arm64: dts: renesas: eagle: add CAN-FD support
arm64: dts: renesas: r8a77980: add CAN-FD support
arm64: dts: renesas: condor: add CAN-FD support
arm64: dts: renesas: r8a77970: disable EtherAVB
arm64: dts: renesas: r8a77980: disable EtherAVB
arm64: dts: renesas: initial V3HSK board device tree
Simon Horman (9):
arm64: dts: renesas: r8a7796: sort subnodes of the root node
arm64: dts: renesas: r8a7796: sort subnodes of the soc node
arm64: dts: renesas: r8a7795: sort subnodes of the root node
arm64: dts: renesas: r8a7795: sort subnodes of the soc node
arm64: dts: renesas: r8a7795-es1: Enable IPMMU devices
arm64: dts: renesas: r8a7795: Add address properties to rcar_sound port nodes
arm64: dts: renesas: r8a7796: Add address properties to rcar_sound port nodes
arm64: dts: renesas: r8a77965: Add address properties to rcar_sound port nodes
arm64: dts: renesas: r8a77980: add resets property to CAN-FD node
Takeshi Kihara (3):
arm64: dts: renesas: r8a77965: Add all MSIOF device nodes
arm64: dts: renesas: Add Renesas Ebisu board support
arm64: dts: renesas: r8a77965: Add SDHI device nodes
Wolfram Sang (1):
arm64: dts: renesas: salvator-common: add eeprom
Yoshihiro Kaneko (5):
arm64: dts: renesas: r8a77995: sort subnodes of the root node
arm64: dts: renesas: r8a77995: sort subnodes of the soc node
arm64: dts: renesas: r8a77965: sort subnodes of the root node
arm64: dts: renesas: r8a77965: sort subnodes of the soc node
arm64: dts: renesas: r8a77970: sort subnodes of the soc node
Yoshihiro Shimoda (19):
arm64: dts: renesas: r8a77965: add usb2_phy nodes
arm64: dts: renesas: r8a77965: add usb3_phy node
arm64: dts: renesas: r8a77965: add USB 2.0 host nodes
arm64: dts: renesas: r8a77965: add usb_dmac nodes
arm64: dts: renesas: r8a77965: add HS-USB node
arm64: dts: renesas: r8a77965: add USB 3.0 host node
arm64: dts: renesas: r8a77965: add USB 3.0 peripheral node
arm64: dts: renesas: r8a77965: Add PWM device nodes
arm64: dts: renesas: Add Renesas R8A77990 Kconfig support
arm64: dts: renesas: Add Renesas R8A77990 SoC support
arm64: dts: renesas: r8a77990: Revise the psci node
arm64: dts: renesas: r8a77990: Revise the cache controller node
arm64: dts: renesas: r8a7795: salvator-xs: enable usb2_phy3 node
arm64: dts: renesas: r8a7795: salvator-xs: enable hsusb channel 3 node
arm64: dts: renesas: r8a7795: salvator-xs: enable USB2.0 host channel 3
arm64: dts: renesas: r8a77990: Add PFC device node
arm64: dts: renesas: r8a77990: Add GPIO device nodes
arm64: dts: renesas: r8a77990: Add EthernetAVB device nodes
arm64: dts: renesas: r8a77990: ebisu: Enable EthernetAVB
arch/arm64/Kconfig.platforms | 6 +
arch/arm64/boot/dts/renesas/Makefile | 3 +-
.../boot/dts/renesas/r8a7795-es1-salvator-x.dts | 46 +
arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi | 144 +-
arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 46 +
.../arm64/boot/dts/renesas/r8a7795-salvator-xs.dts | 85 +
arch/arm64/boot/dts/renesas/r8a7795.dtsi | 2499 +++++++++++---------
arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts | 28 +
.../arm64/boot/dts/renesas/r8a7796-salvator-xs.dts | 28 +
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 2395 +++++++++++--------
.../arm64/boot/dts/renesas/r8a77965-salvator-x.dts | 28 +
.../boot/dts/renesas/r8a77965-salvator-xs.dts | 28 +
arch/arm64/boot/dts/renesas/r8a77965.dtsi | 1601 +++++++++----
arch/arm64/boot/dts/renesas/r8a77970-eagle.dts | 116 +
arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts | 137 ++
arch/arm64/boot/dts/renesas/r8a77970.dtsi | 661 ++++--
arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 81 +
arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts | 60 +
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 99 +-
arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts | 65 +
arch/arm64/boot/dts/renesas/r8a77990.dtsi | 281 +++
arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 2 +-
arch/arm64/boot/dts/renesas/r8a77995.dtsi | 730 +++---
arch/arm64/boot/dts/renesas/salvator-common.dtsi | 187 +-
arch/arm64/boot/dts/renesas/ulcb.dtsi | 37 +-
25 files changed, 6324 insertions(+), 3069 deletions(-)
create mode 100644 arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
create mode 100644 arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
create mode 100644 arch/arm64/boot/dts/renesas/r8a77990.dtsi
^ permalink raw reply
* [PATCH 099/102] arm64: dts: renesas: r8a77965: add VIN and CSI-2 nodes
From: Simon Horman @ 2018-05-18 11:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1526637994.git.horms+renesas@verge.net.au>
From: Niklas S?derlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Niklas S?derlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a77965.dtsi | 326 +++++++++++++++++++++++++++++-
1 file changed, 316 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
index 1f67aea49305..486aecacb22a 100644
--- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi
@@ -886,43 +886,259 @@
};
vin0: video at e6ef0000 {
+ compatible = "renesas,vin-r8a77965";
reg = <0 0xe6ef0000 0 0x1000>;
- /* placeholder */
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 811>;
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 811>;
+ renesas,id = <0>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin0csi20: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint= <&csi20vin0>;
+ };
+ vin0csi40: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin0>;
+ };
+ };
+ };
};
vin1: video at e6ef1000 {
+ compatible = "renesas,vin-r8a77965";
reg = <0 0xe6ef1000 0 0x1000>;
- /* placeholder */
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 810>;
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 810>;
+ renesas,id = <1>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin1csi20: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint= <&csi20vin1>;
+ };
+ vin1csi40: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin1>;
+ };
+ };
+ };
};
vin2: video at e6ef2000 {
+ compatible = "renesas,vin-r8a77965";
reg = <0 0xe6ef2000 0 0x1000>;
- /* placeholder */
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 809>;
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 809>;
+ renesas,id = <2>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin2csi20: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint= <&csi20vin2>;
+ };
+ vin2csi40: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin2>;
+ };
+ };
+ };
};
vin3: video at e6ef3000 {
+ compatible = "renesas,vin-r8a77965";
reg = <0 0xe6ef3000 0 0x1000>;
- /* placeholder */
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 808>;
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 808>;
+ renesas,id = <3>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin3csi20: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint= <&csi20vin3>;
+ };
+ vin3csi40: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin3>;
+ };
+ };
+ };
};
vin4: video at e6ef4000 {
+ compatible = "renesas,vin-r8a77965";
reg = <0 0xe6ef4000 0 0x1000>;
- /* placeholder */
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 807>;
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 807>;
+ renesas,id = <4>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin4csi20: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint= <&csi20vin4>;
+ };
+ vin4csi40: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin4>;
+ };
+ };
+ };
};
vin5: video at e6ef5000 {
+ compatible = "renesas,vin-r8a77965";
reg = <0 0xe6ef5000 0 0x1000>;
- /* placeholder */
+ interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 806>;
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 806>;
+ renesas,id = <5>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin5csi20: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint= <&csi20vin5>;
+ };
+ vin5csi40: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin5>;
+ };
+ };
+ };
};
vin6: video at e6ef6000 {
+ compatible = "renesas,vin-r8a77965";
reg = <0 0xe6ef6000 0 0x1000>;
- /* placeholder */
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 805>;
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 805>;
+ renesas,id = <6>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin6csi20: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint= <&csi20vin6>;
+ };
+ vin6csi40: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin6>;
+ };
+ };
+ };
};
vin7: video at e6ef7000 {
+ compatible = "renesas,vin-r8a77965";
reg = <0 0xe6ef7000 0 0x1000>;
- /* placeholder */
+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 804>;
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 804>;
+ renesas,id = <7>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin7csi20: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint= <&csi20vin7>;
+ };
+ vin7csi40: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin7>;
+ };
+ };
+ };
};
rcar_sound: sound at ec500000 {
@@ -1218,22 +1434,112 @@
};
csi20: csi2 at fea80000 {
+ compatible = "renesas,r8a77965-csi2";
reg = <0 0xfea80000 0 0x10000>;
- /* placeholder */
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 714>;
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 714>;
+ status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ csi20vin0: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint = <&vin0csi20>;
+ };
+ csi20vin1: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint = <&vin1csi20>;
+ };
+ csi20vin2: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint = <&vin2csi20>;
+ };
+ csi20vin3: endpoint at 3 {
+ reg = <3>;
+ remote-endpoint = <&vin3csi20>;
+ };
+ csi20vin4: endpoint at 4 {
+ reg = <4>;
+ remote-endpoint = <&vin4csi20>;
+ };
+ csi20vin5: endpoint at 5 {
+ reg = <5>;
+ remote-endpoint = <&vin5csi20>;
+ };
+ csi20vin6: endpoint at 6 {
+ reg = <6>;
+ remote-endpoint = <&vin6csi20>;
+ };
+ csi20vin7: endpoint at 7 {
+ reg = <7>;
+ remote-endpoint = <&vin7csi20>;
+ };
+ };
};
};
csi40: csi2 at feaa0000 {
+ compatible = "renesas,r8a77965-csi2";
reg = <0 0xfeaa0000 0 0x10000>;
- /* placeholder */
+ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 716>;
+ power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
+ resets = <&cpg 716>;
+ status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ csi40vin0: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint = <&vin0csi40>;
+ };
+ csi40vin1: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint = <&vin1csi40>;
+ };
+ csi40vin2: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint = <&vin2csi40>;
+ };
+ csi40vin3: endpoint at 3 {
+ reg = <3>;
+ remote-endpoint = <&vin3csi40>;
+ };
+ csi40vin4: endpoint at 4 {
+ reg = <4>;
+ remote-endpoint = <&vin4csi40>;
+ };
+ csi40vin5: endpoint at 5 {
+ reg = <5>;
+ remote-endpoint = <&vin5csi40>;
+ };
+ csi40vin6: endpoint at 6 {
+ reg = <6>;
+ remote-endpoint = <&vin6csi40>;
+ };
+ csi40vin7: endpoint at 7 {
+ reg = <7>;
+ remote-endpoint = <&vin7csi40>;
+ };
+ };
};
};
--
2.11.0
^ permalink raw reply related
* [PATCH 100/102] arm64: dts: renesas: r8a77970: add VIN and CSI-2 nodes
From: Simon Horman @ 2018-05-18 11:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1526637994.git.horms+renesas@verge.net.au>
From: Niklas S?derlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Niklas S?derlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a77970.dtsi | 152 ++++++++++++++++++++++++++++++
1 file changed, 152 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
index c8464d1ef1b2..98a2317a16c4 100644
--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
@@ -547,6 +547,119 @@
status = "disabled";
};
+
+ vin0: video at e6ef0000 {
+ compatible = "renesas,vin-r8a77970";
+ reg = <0 0xe6ef0000 0 0x1000>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 811>;
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 811>;
+ renesas,id = <0>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin0csi40: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin0>;
+ };
+ };
+ };
+ };
+
+ vin1: video at e6ef1000 {
+ compatible = "renesas,vin-r8a77970";
+ reg = <0 0xe6ef1000 0 0x1000>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 810>;
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 810>;
+ renesas,id = <1>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin1csi40: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin1>;
+ };
+ };
+ };
+ };
+
+ vin2: video at e6ef2000 {
+ compatible = "renesas,vin-r8a77970";
+ reg = <0 0xe6ef2000 0 0x1000>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 809>;
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 809>;
+ renesas,id = <2>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin2csi40: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin2>;
+ };
+ };
+ };
+ };
+
+ vin3: video at e6ef3000 {
+ compatible = "renesas,vin-r8a77970";
+ reg = <0 0xe6ef3000 0 0x1000>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 808>;
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 808>;
+ renesas,id = <3>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin3csi40: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin3>;
+ };
+ };
+ };
+ };
+
dmac1: dma-controller at e7300000 {
compatible = "renesas,dmac-r8a77970",
"renesas,rcar-dmac";
@@ -679,6 +792,45 @@
resets = <&cpg 603>;
};
+ csi40: csi2 at feaa0000 {
+ compatible = "renesas,r8a77970-csi2";
+ reg = <0 0xfeaa0000 0 0x10000>;
+ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 716>;
+ power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
+ resets = <&cpg 716>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ csi40vin0: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint = <&vin0csi40>;
+ };
+ csi40vin1: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint = <&vin1csi40>;
+ };
+ csi40vin2: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint = <&vin2csi40>;
+ };
+ csi40vin3: endpoint at 3 {
+ reg = <3>;
+ remote-endpoint = <&vin3csi40>;
+ };
+ };
+ };
+ };
+
du: display at feb00000 {
compatible = "renesas,du-r8a77970";
reg = <0 0xfeb00000 0 0x80000>;
--
2.11.0
^ permalink raw reply related
* [PATCH 101/102] arm64: dts: renesas: salvator-common: enable VIN
From: Simon Horman @ 2018-05-18 11:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1526637994.git.horms+renesas@verge.net.au>
From: Niklas S?derlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Niklas S?derlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/salvator-common.dtsi | 32 ++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
index 96b51e572666..263e5787270e 100644
--- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
@@ -703,6 +703,38 @@
clock-frequency = <100000000>;
};
+&vin0 {
+ status = "okay";
+};
+
+&vin1 {
+ status = "okay";
+};
+
+&vin2 {
+ status = "okay";
+};
+
+&vin3 {
+ status = "okay";
+};
+
+&vin4 {
+ status = "okay";
+};
+
+&vin5 {
+ status = "okay";
+};
+
+&vin6 {
+ status = "okay";
+};
+
+&vin7 {
+ status = "okay";
+};
+
&wdt0 {
timeout-sec = <60>;
status = "okay";
--
2.11.0
^ permalink raw reply related
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