* [PATCH v3 2/8] drm/mediatek: support maximum 64 mutex mod
From: stu.hsieh at mediatek.com @ 2018-05-25 2:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527215665-11937-1-git-send-email-stu.hsieh@mediatek.com>
From: Stu Hsieh <stu.hsieh@mediatek.com>
This patch support that if modules more than 32,
add index more than 31 when using DISP_REG_MUTEX_MOD2 bit
Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 75 +++++++++++++++++++++-------------
1 file changed, 47 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 8130f3dab661..47ffa240bd25 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -41,31 +41,32 @@
#define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n))
#define DISP_REG_MUTEX_MOD(n) (0x2c + 0x20 * (n))
#define DISP_REG_MUTEX_SOF(n) (0x30 + 0x20 * (n))
+#define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 * (n))
#define INT_MUTEX BIT(1)
-#define MT8173_MUTEX_MOD_DISP_OVL0 BIT(11)
-#define MT8173_MUTEX_MOD_DISP_OVL1 BIT(12)
-#define MT8173_MUTEX_MOD_DISP_RDMA0 BIT(13)
-#define MT8173_MUTEX_MOD_DISP_RDMA1 BIT(14)
-#define MT8173_MUTEX_MOD_DISP_RDMA2 BIT(15)
-#define MT8173_MUTEX_MOD_DISP_WDMA0 BIT(16)
-#define MT8173_MUTEX_MOD_DISP_WDMA1 BIT(17)
-#define MT8173_MUTEX_MOD_DISP_COLOR0 BIT(18)
-#define MT8173_MUTEX_MOD_DISP_COLOR1 BIT(19)
-#define MT8173_MUTEX_MOD_DISP_AAL BIT(20)
-#define MT8173_MUTEX_MOD_DISP_GAMMA BIT(21)
-#define MT8173_MUTEX_MOD_DISP_UFOE BIT(22)
-#define MT8173_MUTEX_MOD_DISP_PWM0 BIT(23)
-#define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24)
-#define MT8173_MUTEX_MOD_DISP_OD BIT(25)
-
-#define MT2701_MUTEX_MOD_DISP_OVL BIT(3)
-#define MT2701_MUTEX_MOD_DISP_WDMA BIT(6)
-#define MT2701_MUTEX_MOD_DISP_COLOR BIT(7)
-#define MT2701_MUTEX_MOD_DISP_BLS BIT(9)
-#define MT2701_MUTEX_MOD_DISP_RDMA0 BIT(10)
-#define MT2701_MUTEX_MOD_DISP_RDMA1 BIT(12)
+#define MT8173_MUTEX_MOD_DISP_OVL0 11
+#define MT8173_MUTEX_MOD_DISP_OVL1 12
+#define MT8173_MUTEX_MOD_DISP_RDMA0 13
+#define MT8173_MUTEX_MOD_DISP_RDMA1 14
+#define MT8173_MUTEX_MOD_DISP_RDMA2 15
+#define MT8173_MUTEX_MOD_DISP_WDMA0 16
+#define MT8173_MUTEX_MOD_DISP_WDMA1 17
+#define MT8173_MUTEX_MOD_DISP_COLOR0 18
+#define MT8173_MUTEX_MOD_DISP_COLOR1 19
+#define MT8173_MUTEX_MOD_DISP_AAL 20
+#define MT8173_MUTEX_MOD_DISP_GAMMA 21
+#define MT8173_MUTEX_MOD_DISP_UFOE 22
+#define MT8173_MUTEX_MOD_DISP_PWM0 23
+#define MT8173_MUTEX_MOD_DISP_PWM1 24
+#define MT8173_MUTEX_MOD_DISP_OD 25
+
+#define MT2701_MUTEX_MOD_DISP_OVL 3
+#define MT2701_MUTEX_MOD_DISP_WDMA 6
+#define MT2701_MUTEX_MOD_DISP_COLOR 7
+#define MT2701_MUTEX_MOD_DISP_BLS 9
+#define MT2701_MUTEX_MOD_DISP_RDMA0 10
+#define MT2701_MUTEX_MOD_DISP_RDMA1 12
#define MUTEX_SOF_SINGLE_MODE 0
#define MUTEX_SOF_DSI0 1
@@ -278,6 +279,7 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex,
struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp,
mutex[mutex->id]);
unsigned int reg;
+ unsigned int offset;
WARN_ON(&ddp->mutex[mutex->id] != mutex);
@@ -292,9 +294,17 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex,
reg = MUTEX_SOF_DPI0;
break;
default:
- reg = readl_relaxed(ddp->regs + DISP_REG_MUTEX_MOD(mutex->id));
- reg |= ddp->mutex_mod[id];
- writel_relaxed(reg, ddp->regs + DISP_REG_MUTEX_MOD(mutex->id));
+ if (ddp->mutex_mod[id] < 32) {
+ offset = DISP_REG_MUTEX_MOD(mutex->id);
+ reg = readl_relaxed(ddp->regs + offset);
+ reg |= 1 << ddp->mutex_mod[id];
+ writel_relaxed(reg, ddp->regs + offset);
+ } else {
+ offset = DISP_REG_MUTEX_MOD2(mutex->id);
+ reg = readl_relaxed(ddp->regs + offset);
+ reg |= 1 << (ddp->mutex_mod[id] - 32);
+ writel_relaxed(reg, ddp->regs + offset);
+ }
return;
}
@@ -307,6 +317,7 @@ void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex,
struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp,
mutex[mutex->id]);
unsigned int reg;
+ unsigned int offset;
WARN_ON(&ddp->mutex[mutex->id] != mutex);
@@ -318,9 +329,17 @@ void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex,
ddp->regs + DISP_REG_MUTEX_SOF(mutex->id));
break;
default:
- reg = readl_relaxed(ddp->regs + DISP_REG_MUTEX_MOD(mutex->id));
- reg &= ~(ddp->mutex_mod[id]);
- writel_relaxed(reg, ddp->regs + DISP_REG_MUTEX_MOD(mutex->id));
+ if (ddp->mutex_mod[id] < 32) {
+ offset = DISP_REG_MUTEX_MOD(mutex->id);
+ reg = readl_relaxed(ddp->regs + offset);
+ reg &= ~(1 << ddp->mutex_mod[id]);
+ writel_relaxed(reg, ddp->regs + offset);
+ } else {
+ offset = DISP_REG_MUTEX_MOD2(mutex->id);
+ reg = readl_relaxed(ddp->regs + offset);
+ reg &= ~(1 << (ddp->mutex_mod[id] - 32));
+ writel_relaxed(reg, ddp->regs + offset);
+ }
break;
}
}
--
2.12.5
^ permalink raw reply related
* [PATCH v3 3/8] drm/mediatek: add connection from OD1 to RDMA1
From: stu.hsieh at mediatek.com @ 2018-05-25 2:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527215665-11937-1-git-send-email-stu.hsieh@mediatek.com>
From: Stu Hsieh <stu.hsieh@mediatek.com>
This patch add the connection from OD1 to RDMA1 for ext path.
Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 47ffa240bd25..0f568dd853d8 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -151,6 +151,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur,
} else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
*addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
value = GAMMA_MOUT_EN_RDMA1;
+ } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
+ *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
+ value = OD1_MOUT_EN_RDMA1;
} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
*addr = DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN;
value = RDMA1_MOUT_DPI0;
--
2.12.5
^ permalink raw reply related
* [PATCH v3 4/8] drm/mediatek: add ddp component AAL1
From: stu.hsieh at mediatek.com @ 2018-05-25 2:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527215665-11937-1-git-send-email-stu.hsieh@mediatek.com>
From: Stu Hsieh <stu.hsieh@mediatek.com>
This patch add component AAL1 and
rename AAL to AAL0
Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 0828cf8bf85c..eee3c0cc2632 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -41,7 +41,8 @@ enum mtk_ddp_comp_type {
};
enum mtk_ddp_comp_id {
- DDP_COMPONENT_AAL,
+ DDP_COMPONENT_AAL0,
+ DDP_COMPONENT_AAL1,
DDP_COMPONENT_BLS,
DDP_COMPONENT_COLOR0,
DDP_COMPONENT_COLOR1,
--
2.12.5
^ permalink raw reply related
* [PATCH v3 5/8] drm/mediatek: add ddp component OD1
From: stu.hsieh at mediatek.com @ 2018-05-25 2:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527215665-11937-1-git-send-email-stu.hsieh@mediatek.com>
From: Stu Hsieh <stu.hsieh@mediatek.com>
This patch add the component OD1 and
rename the OD to OD1
Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index eee3c0cc2632..9b19fc4423f1 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -50,7 +50,8 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_DSI0,
DDP_COMPONENT_DSI1,
DDP_COMPONENT_GAMMA,
- DDP_COMPONENT_OD,
+ DDP_COMPONENT_OD0,
+ DDP_COMPONENT_OD1,
DDP_COMPONENT_OVL0,
DDP_COMPONENT_OVL1,
DDP_COMPONENT_PWM0,
--
2.12.5
^ permalink raw reply related
* [PATCH v3 6/8] drm/mediatek: add ddp component PWM2
From: stu.hsieh at mediatek.com @ 2018-05-25 2:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527215665-11937-1-git-send-email-stu.hsieh@mediatek.com>
From: Stu Hsieh <stu.hsieh@mediatek.com>
This patch add component PWM2
Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 9b19fc4423f1..e00c2e798abd 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -56,6 +56,7 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_OVL1,
DDP_COMPONENT_PWM0,
DDP_COMPONENT_PWM1,
+ DDP_COMPONENT_PWM2,
DDP_COMPONENT_RDMA0,
DDP_COMPONENT_RDMA1,
DDP_COMPONENT_RDMA2,
--
2.12.5
^ permalink raw reply related
* [PATCH v3 7/8] drm/mediatek: Add support for mediatek SOC MT2712
From: stu.hsieh at mediatek.com @ 2018-05-25 2:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527215665-11937-1-git-send-email-stu.hsieh@mediatek.com>
From: Stu Hsieh <stu.hsieh@mediatek.com>
This patch add support for the Mediatek MT2712 DISP subsystem.
There are two OVL engine and three disp output in MT2712.
Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 46 +++++++++++++++++++++++++++--
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 8 +++--
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 42 ++++++++++++++++++++++++--
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 7 +++--
4 files changed, 94 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 0f568dd853d8..676726249ae0 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -61,6 +61,24 @@
#define MT8173_MUTEX_MOD_DISP_PWM1 24
#define MT8173_MUTEX_MOD_DISP_OD 25
+#define MT2712_MUTEX_MOD_DISP_OVL0 11
+#define MT2712_MUTEX_MOD_DISP_OVL1 12
+#define MT2712_MUTEX_MOD_DISP_RDMA0 13
+#define MT2712_MUTEX_MOD_DISP_RDMA1 14
+#define MT2712_MUTEX_MOD_DISP_RDMA2 15
+#define MT2712_MUTEX_MOD_DISP_WDMA0 16
+#define MT2712_MUTEX_MOD_DISP_WDMA1 17
+#define MT2712_MUTEX_MOD_DISP_COLOR0 18
+#define MT2712_MUTEX_MOD_DISP_COLOR1 19
+#define MT2712_MUTEX_MOD_DISP_AAL0 20
+#define MT2712_MUTEX_MOD_DISP_UFOE 22
+#define MT2712_MUTEX_MOD_DISP_PWM0 23
+#define MT2712_MUTEX_MOD_DISP_PWM1 24
+#define MT2712_MUTEX_MOD_DISP_PWM2 10
+#define MT2712_MUTEX_MOD_DISP_OD0 25
+#define MT2712_MUTEX_MOD2_DISP_AAL1 33
+#define MT2712_MUTEX_MOD2_DISP_OD1 34
+
#define MT2701_MUTEX_MOD_DISP_OVL 3
#define MT2701_MUTEX_MOD_DISP_WDMA 6
#define MT2701_MUTEX_MOD_DISP_COLOR 7
@@ -75,6 +93,7 @@
#define OVL0_MOUT_EN_COLOR0 0x1
#define OD_MOUT_EN_RDMA0 0x1
+#define OD1_MOUT_EN_RDMA1 BIT(16)
#define UFOE_MOUT_EN_DSI0 0x1
#define COLOR0_SEL_IN_OVL0 0x1
#define OVL1_MOUT_EN_COLOR1 0x1
@@ -109,12 +128,32 @@ static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA,
};
+static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+ [DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0,
+ [DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1,
+ [DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0,
+ [DDP_COMPONENT_COLOR1] = MT2712_MUTEX_MOD_DISP_COLOR1,
+ [DDP_COMPONENT_OD0] = MT2712_MUTEX_MOD_DISP_OD0,
+ [DDP_COMPONENT_OD1] = MT2712_MUTEX_MOD2_DISP_OD1,
+ [DDP_COMPONENT_OVL0] = MT2712_MUTEX_MOD_DISP_OVL0,
+ [DDP_COMPONENT_OVL1] = MT2712_MUTEX_MOD_DISP_OVL1,
+ [DDP_COMPONENT_PWM0] = MT2712_MUTEX_MOD_DISP_PWM0,
+ [DDP_COMPONENT_PWM1] = MT2712_MUTEX_MOD_DISP_PWM1,
+ [DDP_COMPONENT_PWM2] = MT2712_MUTEX_MOD_DISP_PWM2,
+ [DDP_COMPONENT_RDMA0] = MT2712_MUTEX_MOD_DISP_RDMA0,
+ [DDP_COMPONENT_RDMA1] = MT2712_MUTEX_MOD_DISP_RDMA1,
+ [DDP_COMPONENT_RDMA2] = MT2712_MUTEX_MOD_DISP_RDMA2,
+ [DDP_COMPONENT_UFOE] = MT2712_MUTEX_MOD_DISP_UFOE,
+ [DDP_COMPONENT_WDMA0] = MT2712_MUTEX_MOD_DISP_WDMA0,
+ [DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1,
+};
+
static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
- [DDP_COMPONENT_AAL] = MT8173_MUTEX_MOD_DISP_AAL,
+ [DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL,
[DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0,
[DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1,
[DDP_COMPONENT_GAMMA] = MT8173_MUTEX_MOD_DISP_GAMMA,
- [DDP_COMPONENT_OD] = MT8173_MUTEX_MOD_DISP_OD,
+ [DDP_COMPONENT_OD0] = MT8173_MUTEX_MOD_DISP_OD,
[DDP_COMPONENT_OVL0] = MT8173_MUTEX_MOD_DISP_OVL0,
[DDP_COMPONENT_OVL1] = MT8173_MUTEX_MOD_DISP_OVL1,
[DDP_COMPONENT_PWM0] = MT8173_MUTEX_MOD_DISP_PWM0,
@@ -139,7 +178,7 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur,
} else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
*addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
value = OVL_MOUT_EN_RDMA;
- } else if (cur == DDP_COMPONENT_OD && next == DDP_COMPONENT_RDMA0) {
+ } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
value = OD_MOUT_EN_RDMA0;
} else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
@@ -429,6 +468,7 @@ static int mtk_ddp_remove(struct platform_device *pdev)
static const struct of_device_id ddp_driver_dt_match[] = {
{ .compatible = "mediatek,mt2701-disp-mutex", .data = mt2701_mutex_mod},
+ { .compatible = "mediatek,mt2712-disp-mutex", .data = mt2712_mutex_mod},
{ .compatible = "mediatek,mt8173-disp-mutex", .data = mt8173_mutex_mod},
{},
};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 4672317e3ad1..86e8c9e5df41 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -218,7 +218,8 @@ struct mtk_ddp_comp_match {
};
static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
- [DDP_COMPONENT_AAL] = { MTK_DISP_AAL, 0, &ddp_aal },
+ [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal },
+ [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal },
[DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL },
[DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, NULL },
[DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, NULL },
@@ -226,10 +227,13 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_DSI0] = { MTK_DSI, 0, NULL },
[DDP_COMPONENT_DSI1] = { MTK_DSI, 1, NULL },
[DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma },
- [DDP_COMPONENT_OD] = { MTK_DISP_OD, 0, &ddp_od },
+ [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od },
+ [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od },
[DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, NULL },
[DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, NULL },
[DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
+ [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
+ [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
[DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, NULL },
[DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, NULL },
[DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, NULL },
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index a2ca90fc403c..b32c4cc8d051 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -146,11 +146,37 @@ static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = {
DDP_COMPONENT_DPI0,
};
+static const enum mtk_ddp_comp_id mt2712_mtk_ddp_main[] = {
+ DDP_COMPONENT_OVL0,
+ DDP_COMPONENT_COLOR0,
+ DDP_COMPONENT_AAL0,
+ DDP_COMPONENT_OD0,
+ DDP_COMPONENT_RDMA0,
+ DDP_COMPONENT_DPI0,
+ DDP_COMPONENT_PWM0,
+};
+
+static const enum mtk_ddp_comp_id mt2712_mtk_ddp_ext[] = {
+ DDP_COMPONENT_OVL1,
+ DDP_COMPONENT_COLOR1,
+ DDP_COMPONENT_AAL1,
+ DDP_COMPONENT_OD1,
+ DDP_COMPONENT_RDMA1,
+ DDP_COMPONENT_DPI1,
+ DDP_COMPONENT_PWM1,
+};
+
+static const enum mtk_ddp_comp_id mt2712_mtk_ddp_third[] = {
+ DDP_COMPONENT_RDMA2,
+ DDP_COMPONENT_DSI2,
+ DDP_COMPONENT_PWM2,
+};
+
static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
DDP_COMPONENT_OVL0,
DDP_COMPONENT_COLOR0,
- DDP_COMPONENT_AAL,
- DDP_COMPONENT_OD,
+ DDP_COMPONENT_AAL0,
+ DDP_COMPONENT_OD0,
DDP_COMPONENT_RDMA0,
DDP_COMPONENT_UFOE,
DDP_COMPONENT_DSI0,
@@ -173,6 +199,15 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.shadow_register = true,
};
+static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
+ .main_path = mt2712_mtk_ddp_main,
+ .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main),
+ .ext_path = mt2712_mtk_ddp_ext,
+ .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext),
+ .third_path = mt2712_mtk_ddp_third,
+ .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
+};
+
static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
.main_path = mt8173_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
@@ -374,6 +409,7 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
{ .compatible = "mediatek,mt8173-dsi", .data = (void *)MTK_DSI },
{ .compatible = "mediatek,mt8173-dpi", .data = (void *)MTK_DPI },
{ .compatible = "mediatek,mt2701-disp-mutex", .data = (void *)MTK_DISP_MUTEX },
+ { .compatible = "mediatek,mt2712-disp-mutex", .data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt8173-disp-mutex", .data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt2701-disp-pwm", .data = (void *)MTK_DISP_BLS },
{ .compatible = "mediatek,mt8173-disp-pwm", .data = (void *)MTK_DISP_PWM },
@@ -552,6 +588,8 @@ static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend,
static const struct of_device_id mtk_drm_of_ids[] = {
{ .compatible = "mediatek,mt2701-mmsys",
.data = &mt2701_mmsys_driver_data},
+ { .compatible = "mediatek,mt2712-mmsys",
+ .data = &mt2712_mmsys_driver_data},
{ .compatible = "mediatek,mt8173-mmsys",
.data = &mt8173_mmsys_driver_data},
{ }
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index c3378c452c0a..e821342bc2d3 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -17,8 +17,8 @@
#include <linux/io.h>
#include "mtk_drm_ddp_comp.h"
-#define MAX_CRTC 2
-#define MAX_CONNECTOR 2
+#define MAX_CRTC 3
+#define MAX_CONNECTOR 3
struct device;
struct device_node;
@@ -33,6 +33,9 @@ struct mtk_mmsys_driver_data {
unsigned int main_len;
const enum mtk_ddp_comp_id *ext_path;
unsigned int ext_len;
+ enum mtk_ddp_comp_id *third_path;
+ unsigned int third_len;
+
bool shadow_register;
};
--
2.12.5
^ permalink raw reply related
* [PATCH v3 8/8] drm/mediatek: add third ddp path
From: stu.hsieh at mediatek.com @ 2018-05-25 2:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527215665-11937-1-git-send-email-stu.hsieh@mediatek.com>
From: Stu Hsieh <stu.hsieh@mediatek.com>
This patch create third crtc by third ddp path
Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index b32c4cc8d051..3a866e1d6af4 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -267,6 +267,11 @@ static int mtk_drm_kms_init(struct drm_device *drm)
if (ret < 0)
goto err_component_unbind;
+ ret = mtk_drm_crtc_create(drm, private->data->third_path,
+ private->data->third_len);
+ if (ret < 0)
+ goto err_component_unbind;
+
/* Use OVL device for all DMA memory allocations */
np = private->comp_node[private->data->main_path[0]] ?:
private->comp_node[private->data->ext_path[0]];
--
2.12.5
^ permalink raw reply related
* [PATCH] arm64: dts: sprd: fix typo in 'remote-endpoint'
From: Chunyan Zhang @ 2018-05-25 2:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAL_JsqKrsTpgnLfxhcxeucpoh9NkyGwwZq82QUBgJZrdjGYQzg@mail.gmail.com>
Hi Arnd, Olof
Could you please take this patch through arm-soc git?
Thanks,
Chunyan
On 24 May 2018 at 04:30, Rob Herring <robh@kernel.org> wrote:
> On Tue, May 8, 2018 at 8:58 PM, Chunyan Zhang <zhang.lyra@gmail.com> wrote:
>> Hi Rob,
>>
>> On 8 May 2018 at 23:09, Rob Herring <robh@kernel.org> wrote:
>>> dtc now warns on incomplete OF graph endpoint connections:
>>>
>>> arch/arm64/boot/dts/sprd/sp9860g-1h10.dtb: Warning (graph_endpoint): /soc/stm at 10006000/port/endpoint: graph connection to node '/soc/funnel at 10001000/ports/port at 2/endpoint' is not bidirectional
>>>
>>> The cause is a typo in 'remote-endpoint'.
>>
>> Thanks for fixing this and,
>>
>> Acked-by: Chunyan Zhang <zhang.lyra@gmail.com>
>
> Is someone going to apply this? Still seeing warnings in linux-next.
>
> Rob
^ permalink raw reply
* Nokia N900: refcount_t underflow, use after free
From: Suman Anna @ 2018-05-25 2:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180524110533.GA20599@amd>
On 05/24/2018 06:05 AM, Pavel Machek wrote:
> Hi!
>
>>>>
>>>> OK, see if the following fixes the issue for you, only build tested.
>>>
>>> Word-wrapped, so I applied by hand. And yes, the oops at boot is
>>> gone. Thanks!
>>
>> Sorry about that, have to check my mail settings. Anyway will post the
>> patch again, glad that it fixed your issue.
>
> Any news here? AFAICT the bug creeped into v4.17-rcX in the
> meantime...
>
The patch has been on linux-next for sometime now.
regards
Suman
> Pavel
>
>> regards
>> Suman
>>
>>>
>>> (Camera still does not work in -next... kills system. Oh well. Lets
>>> debug that some other day.)
>>>
>>>> 8< ---------------------
>>>> >From bac9a48fb646dc51f2030d676a0dbe3298c3b134 Mon Sep 17 00:00:00 2001
>>>> From: Suman Anna <s-anna@ti.com>
>>>> Date: Fri, 9 Mar 2018 16:39:59 -0600
>>>> Subject: [PATCH] media: omap3isp: fix unbalanced dma_iommu_mapping
>>>>
>>>> The OMAP3 ISP driver manages its MMU mappings through the IOMMU-aware
>>>> ARM DMA backend. The current code creates a dma_iommu_mapping and
>>>> attaches this to the ISP device, but never detaches the mapping in
>>>> either the probe failure paths or the driver remove path resulting
>>>> in an unbalanced mapping refcount and a memory leak. Fix this properly.
>>>>
>>>> Reported-by: Pavel Machek <pavel@ucw.cz>
>>>> Signed-off-by: Suman Anna <s-anna@ti.com>
>>>
>>> Tested-by: Pavel Machek <pavel@ucw.cz>
>>> Pavel
>>>
>
^ permalink raw reply
* [PATCH v2 13/40] vfio: Add support for Shared Virtual Addressing
From: Xu Zaibo @ 2018-05-25 2:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <205c1729-8026-3efe-c363-d37d7150d622@arm.com>
Hi,
On 2018/5/24 23:04, Jean-Philippe Brucker wrote:
> On 24/05/18 13:35, Xu Zaibo wrote:
>>> Right, sva_init() must be called once for any device that intends to use
>>> bind(). For the second process though, group->sva_enabled will be true
>>> so we won't call sva_init() again, only bind().
>> Well, while I create mediated devices based on one parent device to support multiple
>> processes(a new process will create a new 'vfio_group' for the corresponding mediated device,
>> and 'sva_enabled' cannot work any more), in fact, *sva_init and *sva_shutdown are basically
>> working on parent device, so, as a result, I just only need sva initiation and shutdown on the
>> parent device only once. So I change the two as following:
>>
>> @@ -551,8 +565,18 @@ int iommu_sva_device_init(struct device *dev, unsigned long features,
>> if (features & ~IOMMU_SVA_FEAT_IOPF)
>> return -EINVAL;
>>
>> + /* If already exists, do nothing */
>> + mutex_lock(&dev->iommu_param->lock);
>> + if (dev->iommu_param->sva_param) {
>> + mutex_unlock(&dev->iommu_param->lock);
>> + return 0;
>> + }
>> + mutex_unlock(&dev->iommu_param->lock);
>>
>> if (features & IOMMU_SVA_FEAT_IOPF) {
>> ret = iommu_register_device_fault_handler(dev, iommu_queue_iopf,
>>
>>
>> @@ -621,6 +646,14 @@ int iommu_sva_device_shutdown(struct device *dev)
>> if (!domain)
>> return -ENODEV;
>>
>> + /* If any other process is working on the device, shut down does nothing. */
>> + mutex_lock(&dev->iommu_param->lock);
>> + if (!list_empty(&dev->iommu_param->sva_param->mm_list)) {
>> + mutex_unlock(&dev->iommu_param->lock);
>> + return 0;
>> + }
>> + mutex_unlock(&dev->iommu_param->lock);
> I don't think iommu-sva.c is the best place for this, it's probably
> better to implement an intermediate layer (the mediating driver), that
> calls iommu_sva_device_init() and iommu_sva_device_shutdown() once. Then
> vfio-pci would still call these functions itself, but for mdev the
> mediating driver keeps a refcount of groups, and calls device_shutdown()
> only when freeing the last mdev.
>
> A device driver (non mdev in this example) expects to be able to free
> all its resources after sva_device_shutdown() returns. Imagine the
> mm_list isn't empty (mm_exit() is running late), and instead of waiting
> in unbind_dev_all() below, we return 0 immediately. Then the calling
> driver frees its resources, and the mm_exit callback along with private
> data passed to bind() disappear. If a mm_exit() is still running in
> parallel, then it will try to access freed data and corrupt memory. So
> in this function if mm_list isn't empty, the only thing we can do is wait.
>
I still don't understand why we should 'unbind_dev_all', is it possible
to do a 'unbind_dev_pasid'?
Then we can do other things instead of waiting that user may not like. :)
Thanks
Zaibo
>
>> +
>> __iommu_sva_unbind_dev_all(dev);
>>
>> mutex_lock(&dev->iommu_param->lock);
>>
>> I add the above two checkings in both *sva_init and *sva_shutdown, it is working now,
>> but i don't know if it will cause any new problems. What's more, i doubt if it is
>> reasonable to check this to avoid repeating operation in VFIO, maybe it is better to check
>> in IOMMU. :)
>
>
>
> .
>
^ permalink raw reply
* [PATCH] drm/rockchip: vop: fix irq disabled after vop driver probed
From: Tomasz Figa @ 2018-05-25 2:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <25470133.K8n9sLBzRS@diego>
Hi Heiko, Sandy,
On Fri, May 25, 2018 at 7:07 AM Heiko St?bner <heiko@sntech.de> wrote:
> From: Sandy Huang <hjc@rock-chips.com>
> The vop irq is shared between vop and iommu and irq probing in the
> iommu driver moved to the probe function recently. This can in some
> cases lead to a stall if the irq is triggered while the vop driver
> still has it disabled.
> But there is no real need to disable the irq, as the vop can simply
> also track its enabled state and ignore irqs in that case.
> So remove the enable/disable handling and add appropriate condition
> to the irq handler.
> Signed-off-by: Sandy Huang <hjc@rock-chips.com>
> [added an actual commit message]
> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
> ---
> Hi Ezequiel,
> this patch came from a discussion I had with Rockchip people over the
> iommu changes and resulting issues back in april, but somehow was
> forgotten and not posted to the lists. Correcting that now.
> So removing the enable/disable voodoo on the shared interrupt is
> the preferred way.
> drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 13 ++++++-------
> 1 file changed, 7 insertions(+), 7 deletions(-)
> diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
> index 510cdf0..61493d4 100644
> --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
> +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
> @@ -549,8 +549,6 @@ static int vop_enable(struct drm_crtc *crtc)
> spin_unlock(&vop->reg_lock);
> - enable_irq(vop->irq);
> -
While this one should be okay (+/- my comment for vop_isr()), because the
hardware is already powered on and clocked at this point...
> drm_crtc_vblank_on(crtc);
> return 0;
> @@ -596,8 +594,6 @@ static void vop_crtc_atomic_disable(struct drm_crtc
*crtc,
> vop_dsp_hold_valid_irq_disable(vop);
> - disable_irq(vop->irq);
> -
> vop->is_enabled = false;
...this one is more tricky. There might be an interrupt handler still
running at this point. disable_irq() waits for any running handler to
complete before disabling, so we might want to call synchronize_irq() after
setting is_enabled to false.
> /*
> @@ -1168,6 +1164,13 @@ static irqreturn_t vop_isr(int irq, void *data)
> int ret = IRQ_NONE;
> /*
> + * since the irq is shared with iommu, iommu irq is enabled
before vop
> + * enable, so before vop enable we do nothing.
> + */
> + if (!vop->is_enabled)
> + return IRQ_NONE;
This doesn't seem to be properly synchronized. We don't even call it under
a spinlock, so no barriers are issued. Perhaps we should make this atomic_t?
Best regards,
Tomasz
^ permalink raw reply
* [PATCH] ARM: dts: imx51-zii-rdu1: Make sure SD1_WP is low
From: Andrey Smirnov @ 2018-05-25 3:01 UTC (permalink / raw)
To: linux-arm-kernel
Make sure that MX51_PAD_GPIO1_1 does not remain configure as
ALT0/SD1_WP (it is out of reset). This is needed because of external
pull-up resistor attached to that pad that, when left unchanged, will
drive SD1_WP high preventing eSDHC1/eMMC from working correctly.
To fix that add a pinmux configuration line configureing the pad to
function as a GPIO. While we are at it, add a corresponding input GPIO
hog in an effort to minimize current consumption.
Cc: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-arm-kernel at lists.infradead.org
Cc: devicetree at vger.kernel.org
Cc: linux-kernel at vger.kernel.org
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
arch/arm/boot/dts/imx51-zii-rdu1.dts | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts b/arch/arm/boot/dts/imx51-zii-rdu1.dts
index df9eca94d812..d484e7e46b27 100644
--- a/arch/arm/boot/dts/imx51-zii-rdu1.dts
+++ b/arch/arm/boot/dts/imx51-zii-rdu1.dts
@@ -476,6 +476,17 @@
status = "okay";
};
+&gpio1 {
+ unused-sd3-wp-gpio {
+ /*
+ * See pinctrl_esdhc1 below for more details on this
+ */
+ gpio-hog;
+ gpios = <1 GPIO_ACTIVE_HIGH>;
+ input;
+ };
+};
+
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
@@ -660,6 +671,23 @@
MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
+ /*
+ * GPIO1_1 is not directly used by eSDHC1 in
+ * any capacity, but earlier versions of RDU1
+ * used that pin as WP GPIO for eSDHC3 and
+ * because of that that pad has an external
+ * pull-up resistor. This is problematic
+ * because out of reset the pad is configured
+ * as ALT0 which serves as SD1_WP, which, when
+ * pulled high by and external pull-up, will
+ * inhibit execution of any write request to
+ * attached eMMC device.
+ *
+ * To avoid this problem we configure the pad
+ * to ALT1/GPIO and avoid driving SD1_WP
+ * signal high.
+ */
+ MX51_PAD_GPIO1_1__GPIO1_1 0x0000
>;
};
--
2.17.0
^ permalink raw reply related
* [PATCH v3 1/8] drm/mediatek: update dt-bindings for mt2712
From: CK Hu @ 2018-05-25 3:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527215665-11937-2-git-send-email-stu.hsieh@mediatek.com>
Hi, Stu:
On Fri, 2018-05-25 at 10:34 +0800, stu.hsieh at mediatek.com wrote:
> From: Stu Hsieh <stu.hsieh@mediatek.com>
>
> Update device tree binding documentation for the display subsystem for
> Mediatek MT2712 SoCs.
>
I've acked v2 of this patch and v3 is the same as v2, so you should keep
my ack in commit message.
Regards,
CK
> Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
> ---
> Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> index 383183a89164..8469de510001 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> @@ -40,7 +40,7 @@ Required properties (all function blocks):
> "mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt
> "mediatek,<chip>-disp-mutex" - display mutex
> "mediatek,<chip>-disp-od" - overdrive
> - the supported chips are mt2701 and mt8173.
> + the supported chips are mt2701, mt2712 and mt8173.
> - reg: Physical base address and length of the function block register space
> - interrupts: The interrupt signal from the function block (required, except for
> merge and split function blocks).
^ permalink raw reply
* [PATCH v3 2/8] drm/mediatek: support maximum 64 mutex mod
From: CK Hu @ 2018-05-25 3:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527215665-11937-3-git-send-email-stu.hsieh@mediatek.com>
Hi, Stu:
On Fri, 2018-05-25 at 10:34 +0800, stu.hsieh at mediatek.com wrote:
> From: Stu Hsieh <stu.hsieh@mediatek.com>
>
> This patch support that if modules more than 32,
> add index more than 31 when using DISP_REG_MUTEX_MOD2 bit
>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
> Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 75 +++++++++++++++++++++-------------
> 1 file changed, 47 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> index 8130f3dab661..47ffa240bd25 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> @@ -41,31 +41,32 @@
> #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n))
> #define DISP_REG_MUTEX_MOD(n) (0x2c + 0x20 * (n))
> #define DISP_REG_MUTEX_SOF(n) (0x30 + 0x20 * (n))
> +#define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 * (n))
>
> #define INT_MUTEX BIT(1)
>
> -#define MT8173_MUTEX_MOD_DISP_OVL0 BIT(11)
> -#define MT8173_MUTEX_MOD_DISP_OVL1 BIT(12)
> -#define MT8173_MUTEX_MOD_DISP_RDMA0 BIT(13)
> -#define MT8173_MUTEX_MOD_DISP_RDMA1 BIT(14)
> -#define MT8173_MUTEX_MOD_DISP_RDMA2 BIT(15)
> -#define MT8173_MUTEX_MOD_DISP_WDMA0 BIT(16)
> -#define MT8173_MUTEX_MOD_DISP_WDMA1 BIT(17)
> -#define MT8173_MUTEX_MOD_DISP_COLOR0 BIT(18)
> -#define MT8173_MUTEX_MOD_DISP_COLOR1 BIT(19)
> -#define MT8173_MUTEX_MOD_DISP_AAL BIT(20)
> -#define MT8173_MUTEX_MOD_DISP_GAMMA BIT(21)
> -#define MT8173_MUTEX_MOD_DISP_UFOE BIT(22)
> -#define MT8173_MUTEX_MOD_DISP_PWM0 BIT(23)
> -#define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24)
> -#define MT8173_MUTEX_MOD_DISP_OD BIT(25)
> -
> -#define MT2701_MUTEX_MOD_DISP_OVL BIT(3)
> -#define MT2701_MUTEX_MOD_DISP_WDMA BIT(6)
> -#define MT2701_MUTEX_MOD_DISP_COLOR BIT(7)
> -#define MT2701_MUTEX_MOD_DISP_BLS BIT(9)
> -#define MT2701_MUTEX_MOD_DISP_RDMA0 BIT(10)
> -#define MT2701_MUTEX_MOD_DISP_RDMA1 BIT(12)
> +#define MT8173_MUTEX_MOD_DISP_OVL0 11
> +#define MT8173_MUTEX_MOD_DISP_OVL1 12
> +#define MT8173_MUTEX_MOD_DISP_RDMA0 13
> +#define MT8173_MUTEX_MOD_DISP_RDMA1 14
> +#define MT8173_MUTEX_MOD_DISP_RDMA2 15
> +#define MT8173_MUTEX_MOD_DISP_WDMA0 16
> +#define MT8173_MUTEX_MOD_DISP_WDMA1 17
> +#define MT8173_MUTEX_MOD_DISP_COLOR0 18
> +#define MT8173_MUTEX_MOD_DISP_COLOR1 19
> +#define MT8173_MUTEX_MOD_DISP_AAL 20
> +#define MT8173_MUTEX_MOD_DISP_GAMMA 21
> +#define MT8173_MUTEX_MOD_DISP_UFOE 22
> +#define MT8173_MUTEX_MOD_DISP_PWM0 23
> +#define MT8173_MUTEX_MOD_DISP_PWM1 24
> +#define MT8173_MUTEX_MOD_DISP_OD 25
> +
> +#define MT2701_MUTEX_MOD_DISP_OVL 3
> +#define MT2701_MUTEX_MOD_DISP_WDMA 6
> +#define MT2701_MUTEX_MOD_DISP_COLOR 7
> +#define MT2701_MUTEX_MOD_DISP_BLS 9
> +#define MT2701_MUTEX_MOD_DISP_RDMA0 10
> +#define MT2701_MUTEX_MOD_DISP_RDMA1 12
>
> #define MUTEX_SOF_SINGLE_MODE 0
> #define MUTEX_SOF_DSI0 1
> @@ -278,6 +279,7 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex,
> struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp,
> mutex[mutex->id]);
> unsigned int reg;
> + unsigned int offset;
>
> WARN_ON(&ddp->mutex[mutex->id] != mutex);
>
> @@ -292,9 +294,17 @@ void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex,
> reg = MUTEX_SOF_DPI0;
> break;
> default:
> - reg = readl_relaxed(ddp->regs + DISP_REG_MUTEX_MOD(mutex->id));
> - reg |= ddp->mutex_mod[id];
> - writel_relaxed(reg, ddp->regs + DISP_REG_MUTEX_MOD(mutex->id));
> + if (ddp->mutex_mod[id] < 32) {
> + offset = DISP_REG_MUTEX_MOD(mutex->id);
> + reg = readl_relaxed(ddp->regs + offset);
> + reg |= 1 << ddp->mutex_mod[id];
> + writel_relaxed(reg, ddp->regs + offset);
> + } else {
> + offset = DISP_REG_MUTEX_MOD2(mutex->id);
> + reg = readl_relaxed(ddp->regs + offset);
> + reg |= 1 << (ddp->mutex_mod[id] - 32);
> + writel_relaxed(reg, ddp->regs + offset);
> + }
> return;
> }
>
> @@ -307,6 +317,7 @@ void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex,
> struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp,
> mutex[mutex->id]);
> unsigned int reg;
> + unsigned int offset;
>
> WARN_ON(&ddp->mutex[mutex->id] != mutex);
>
> @@ -318,9 +329,17 @@ void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex,
> ddp->regs + DISP_REG_MUTEX_SOF(mutex->id));
> break;
> default:
> - reg = readl_relaxed(ddp->regs + DISP_REG_MUTEX_MOD(mutex->id));
> - reg &= ~(ddp->mutex_mod[id]);
> - writel_relaxed(reg, ddp->regs + DISP_REG_MUTEX_MOD(mutex->id));
> + if (ddp->mutex_mod[id] < 32) {
> + offset = DISP_REG_MUTEX_MOD(mutex->id);
> + reg = readl_relaxed(ddp->regs + offset);
> + reg &= ~(1 << ddp->mutex_mod[id]);
> + writel_relaxed(reg, ddp->regs + offset);
> + } else {
> + offset = DISP_REG_MUTEX_MOD2(mutex->id);
> + reg = readl_relaxed(ddp->regs + offset);
> + reg &= ~(1 << (ddp->mutex_mod[id] - 32));
> + writel_relaxed(reg, ddp->regs + offset);
> + }
> break;
> }
> }
^ permalink raw reply
* [PATCH v6 1/2] ARM: dts: imx: Add basic dtsi file for imx6sll
From: A.s. Dong @ 2018-05-25 3:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526899612-22856-1-git-send-email-ping.bai@nxp.com>
> -----Original Message-----
> From: Jacky Bai
> Sent: Monday, May 21, 2018 6:47 PM
> To: shawnguo at kernel.org; robh+dt at kernel.org; kernel at pengutronix.de
> Cc: Fabio Estevam <fabio.estevam@nxp.com>; devicetree at vger.kernel.org;
> linux-arm-kernel at lists.infradead.org; dl-linux-imx <linux-imx@nxp.com>;
> A.s. Dong <aisheng.dong@nxp.com>; jacky.baip at gmail.com
> Subject: [PATCH v6 1/2] ARM: dts: imx: Add basic dtsi file for imx6sll
>
[...]
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu at 0 {
> + compatible = "arm,cortex-a9";
> + device_type = "cpu";
> + reg = <0>;
> + next-level-cache = <&L2>;
> + operating-points = <
> + /* kHz uV */
> + 996000 1275000
> + 792000 1175000
> + 396000 1075000
> + 198000 975000
> + >;
> + fsl,soc-operating-points = <
> + /* ARM kHz SOC-PU uV */
> + 996000 1175000
> + 792000 1175000
> + 396000 1175000
> + 198000 1175000
> + >;
> + clock-latency = <61036>; /* two CLK32 periods */
> + clocks = <&clks IMX6SLL_CLK_ARM>,
> + <&clks IMX6SLL_CLK_PLL2_PFD2>,
> + <&clks IMX6SLL_CLK_STEP>,
> + <&clks IMX6SLL_CLK_PLL1_SW>,
> + <&clks IMX6SLL_CLK_PLL1_SYS>,
> + <&clks IMX6SLL_CLK_PLL1>,
> + <&clks IMX6SLL_PLL1_BYPASS>,
> + <&clks IMX6SLL_PLL1_BYPASS_SRC>;
> + clock-names = "arm", "pll2_pfd2_396m", "step",
> + "pll1_sw", "pll1_sys", "pll1",
> + "pll1_bypass", "pll1_bypass_src";
> + };
Please remove the unused pll1, pll1_bypass and pll1_bypass_src clocks.
> + };
> +
> + intc: interrupt-controller at a01000 {
> + compatible = "arm,cortex-a9-gic";
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + reg = <0x00a01000 0x1000>,
> + <0x00a00100 0x100>;
> + interrupt-parent = <&intc>;
> + };
> +
> + ckil: clock-ckil {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <32768>;
> + clock-output-names = "ckil";
> + };
> +
> + osc: clock-osc-24m {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <24000000>;
> + clock-output-names = "osc";
> + };
> +
[...]
> +
> + gpt1: timer at 2098000 {
> + compatible = "fsl,imx6dl-gpt";
This looks strange as mx6sll is derived from mx6sl.
How about change to "fsl,imx6sl-gpt" which is already supported?
> + reg = <0x02098000 0x4000>;
> + interrupts = <GIC_SPI 55
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX6SLL_CLK_GPT_BUS>,
> + <&clks IMX6SLL_CLK_GPT_SERIAL>;
> + clock-names = "ipg", "per";
> + };
> +
[...]
> +
> + tempmon: temperature-sensor {
> + compatible = "fsl,imx6sll-tempmon",
> "fsl,imx6sx-tempmon";
> + interrupts = <GIC_SPI 49
> IRQ_TYPE_LEVEL_HIGH>;
> + fsl,tempmon = <&anatop>;
> + fsl,tempmon-data = <&ocotp>;
> + clocks = <&clks
> IMX6SLL_CLK_PLL3_USB_OTG>;
> + status = "disabled";
> + };
> +
Pls move it out of SoC node to root node.
See:
commit 225fa59fddfa7 ("ARM: dts: imx7: Move tempmon node out of bus")
And probably we need switch to the new way?
See:
commit de25b9bb4a4 ("ARM: dts: imx7s: add temperature monitor support")
Otherwise:
Acked-by: Dong Aisheng <Aisheng.dong@nxp.com>
Regards
Dong Aisheng
> + usbphy1: usb-phy at 20c9000 {
> + compatible = "fsl,imx6sll-usbphy",
> "fsl,imx6ul-usbphy",
> + "fsl,imx23-usbphy";
> + reg = <0x020c9000 0x1000>;
> + interrupts = <GIC_SPI 40
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX6SLL_CLK_USBPHY1>;
> + phy-3p0-supply = <®_3p0>;
> + fsl,anatop = <&anatop>;
> + };
> +
> + usbphy2: usb-phy at 20ca000 {
> + compatible = "fsl,imx6sll-usbphy",
> "fsl,imx6ul-usbphy",
> + "fsl,imx23-usbphy";
> + reg = <0x020ca000 0x1000>;
> + interrupts = <GIC_SPI 41
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX6SLL_CLK_USBPHY2>;
> + phy-reg_3p0-supply = <®_3p0>;
> + fsl,anatop = <&anatop>;
> + };
> +
> + snvs: snvs at 20cc000 {
> + compatible = "fsl,sec-v4.0-mon", "syscon",
> "simple-mfd";
> + reg = <0x020cc000 0x4000>;
> +
> + snvs_rtc: snvs-rtc-lp {
> + compatible = "fsl,sec-v4.0-mon-rtc-
> lp";
> + regmap = <&snvs>;
> + offset = <0x34>;
> + interrupts = <GIC_SPI 19
> IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 20
> IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + snvs_poweroff: snvs-poweroff {
> + compatible = "syscon-poweroff";
> + regmap = <&snvs>;
> + offset = <0x38>;
> + mask = <0x61>;
> + };
> +
> + snvs_pwrkey: snvs-powerkey {
> + compatible = "fsl,sec-v4.0-pwrkey";
> + regmap = <&snvs>;
> + interrupts = <GIC_SPI 4
> IRQ_TYPE_LEVEL_HIGH>;
> + linux,keycode = <KEY_POWER>;
> + wakeup-source;
> + };
> + };
> +
> + src: reset-controller at 20d8000 {
> + compatible = "fsl,imx6sll-src";
> + reg = <0x020d8000 0x4000>;
> + interrupts = <GIC_SPI 91
> IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 96
> IRQ_TYPE_LEVEL_HIGH>;
> + #reset-cells = <1>;
> + };
> +
> + gpc: interrupt-controller at 20dc000 {
> + compatible = "fsl,imx6sll-gpc", "fsl,imx6q-
> gpc";
> + reg = <0x020dc000 0x4000>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + interrupts = <GIC_SPI 89
> IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-parent = <&intc>;
> + fsl,mf-mix-wakeup-irq = <0x7c00000 0x7d00
> 0x0 0x1400640>;
> + };
> +
> + iomuxc: pinctrl at 20e0000 {
> + compatible = "fsl,imx6sll-iomuxc";
> + reg = <0x020e0000 0x4000>;
> + };
> +
> + gpr: iomuxc-gpr at 20e4000 {
> + compatible = "fsl,imx6sll-iomuxc-gpr",
> + "fsl,imx6q-iomuxc-gpr", "syscon";
> + reg = <0x020e4000 0x4000>;
> + };
> +
> + csi: csi at 20e8000 {
> + compatible = "fsl,imx6sll-csi", "fsl,imx6s-csi";
> + reg = <0x020e8000 0x4000>;
> + interrupts = <GIC_SPI 7
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX6SLL_CLK_DUMMY>,
> + <&clks IMX6SLL_CLK_CSI>,
> + <&clks IMX6SLL_CLK_DUMMY>;
> + clock-names = "disp-axi", "csi_mclk",
> "disp_dcic";
> + status = "disabled";
> + };
> +
> + sdma: dma-controller at 20ec000 {
> + compatible = "fsl,imx6sll-sdma", "fsl,imx35-
> sdma";
> + reg = <0x020ec000 0x4000>;
> + interrupts = <GIC_SPI 2
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX6SLL_CLK_SDMA>,
> + <&clks IMX6SLL_CLK_SDMA>;
> + clock-names = "ipg", "ahb";
> + #dma-cells = <3>;
> + iram = <&ocram>;
> + fsl,sdma-ram-script-name =
> "imx/sdma/sdma-imx6q.bin";
> + };
> +
> + lcdif: lcd-controller at 20f8000 {
> + compatible = "fsl,imx6sll-lcdif", "fsl,imx28-
> lcdif";
> + reg = <0x020f8000 0x4000>;
> + interrupts = <GIC_SPI 39
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX6SLL_CLK_LCDIF_PIX>,
> + <&clks IMX6SLL_CLK_LCDIF_APB>,
> + <&clks IMX6SLL_CLK_DUMMY>;
> + clock-names = "pix", "axi", "disp_axi";
> + status = "disabled";
> + };
> +
> + dcp: dcp at 20fc000 {
> + compatible = "fsl,imx28-dcp";
> + reg = <0x020fc000 0x4000>;
> + interrupts = <GIC_SPI 99
> IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 100
> IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 101
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX6SLL_CLK_DCP>;
> + clock-names = "dcp";
> + };
> + };
> +
> + aips2: aips-bus at 2100000 {
> + compatible = "fsl,aips-bus", "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0x02100000 0x100000>;
> + ranges;
> +
> + usbotg1: usb at 2184000 {
> + compatible = "fsl,imx6sll-usb", "fsl,imx6ul-
> usb",
> + "fsl,imx27-usb";
> + reg = <0x02184000 0x200>;
> + interrupts = <GIC_SPI 43
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX6SLL_CLK_USBOH3>;
> + fsl,usbphy = <&usbphy1>;
> + fsl,usbmisc = <&usbmisc 0>;
> + fsl,anatop = <&anatop>;
> + ahb-burst-config = <0x0>;
> + tx-burst-size-dword = <0x10>;
> + rx-burst-size-dword = <0x10>;
> + status = "disabled";
> + };
> +
> + usbotg2: usb at 2184200 {
> + compatible = "fsl,imx6sll-usb", "fsl,imx6ul-
> usb",
> + "fsl,imx27-usb";
> + reg = <0x02184200 0x200>;
> + interrupts = <GIC_SPI 42
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX6SLL_CLK_USBOH3>;
> + fsl,usbphy = <&usbphy2>;
> + fsl,usbmisc = <&usbmisc 1>;
> + ahb-burst-config = <0x0>;
> + tx-burst-size-dword = <0x10>;
> + rx-burst-size-dword = <0x10>;
> + status = "disabled";
> + };
> +
> + usbmisc: usbmisc at 2184800 {
> + #index-cells = <1>;
> + compatible = "fsl,imx6sll-usbmisc",
> "fsl,imx6ul-usbmisc",
> + "fsl,imx6q-usbmisc";
> + reg = <0x02184800 0x200>;
> + };
> +
> + usdhc1: mmc at 2190000 {
> + compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-
> usdhc";
> + reg = <0x02190000 0x4000>;
> + interrupts = <GIC_SPI 22
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX6SLL_CLK_USDHC1>,
> + <&clks IMX6SLL_CLK_USDHC1>,
> + <&clks IMX6SLL_CLK_USDHC1>;
> + clock-names = "ipg", "ahb", "per";
> + bus-width = <4>;
> + fsl,tuning-step = <2>;
> + fsl,tuning-start-tap = <20>;
> + status = "disabled";
> + };
> +
> + usdhc2: mmc at 2194000 {
> + compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-
> usdhc";
> + reg = <0x02194000 0x4000>;
> + interrupts = <GIC_SPI 23
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX6SLL_CLK_USDHC2>,
> + <&clks IMX6SLL_CLK_USDHC2>,
> + <&clks IMX6SLL_CLK_USDHC2>;
> + clock-names = "ipg", "ahb", "per";
> + bus-width = <4>;
> + fsl,tuning-step = <2>;
> + fsl,tuning-start-tap = <20>;
> + status = "disabled";
> + };
> +
> + usdhc3: mmc at 2198000 {
> + compatible = "fsl,imx6sll-usdhc", "fsl,imx6sx-
> usdhc";
> + reg = <0x02198000 0x4000>;
> + interrupts = <GIC_SPI 24
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX6SLL_CLK_USDHC3>,
> + <&clks IMX6SLL_CLK_USDHC3>,
> + <&clks IMX6SLL_CLK_USDHC3>;
> + clock-names = "ipg", "ahb", "per";
> + bus-width = <4>;
> + fsl,tuning-step = <2>;
> + fsl,tuning-start-tap = <20>;
> + status = "disabled";
> + };
> +
> + i2c1: i2c at 21a0000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fs,imx6sll-i2c", "fsl,imx21-i2c";
> + reg = <0x021a0000 0x4000>;
> + interrupts = <GIC_SPI 36
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX6SLL_CLK_I2C1>;
> + status = "disabled";
> + };
> +
> + i2c2: i2c at 21a4000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
> + reg = <0x021a4000 0x4000>;
> + interrupts = <GIC_SPI 37
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX6SLL_CLK_I2C2>;
> + status = "disabled";
> + };
> +
> + i2c3: i2c at 21a8000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "fsl,imx6sll-i2c", "fsl,imx21-i2c";
> + reg = <0x021a8000 0x4000>;
> + interrupts = <GIC_SPI 38
> IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX6SLL_CLK_I2C3>;
> + status = "disabled";
> + };
> +
> + mmdc: memory-controller at 21b0000 {
> + compatible = "fsl,imx6sll-mmdc", "fsl,imx6q-
> mmdc";
> + reg = <0x021b0000 0x4000>;
> + };
> +
> + ocotp: ocotp-ctrl at 21bc000 {
> + compatible = "fsl,imx6sll-ocotp", "syscon";
> + reg = <0x021bc000 0x4000>;
> + clocks = <&clks IMX6SLL_CLK_OCOTP>;
> + };
> +
> + audmux: audmux at 21d8000 {
> + compatible = "fsl,imx6sll-audmux",
> "fsl,imx31-audmux";
> + reg = <0x021d8000 0x4000>;
> + status = "disabled";
> + };
> +
> + uart5: serial at 21f4000 {
> + compatible = "fsl,imx6sll-uart", "fsl,imx6q-
> uart",
> + "fsl,imx21-uart";
> + reg = <0x021f4000 0x4000>;
> + interrupts =<GIC_SPI 30
> IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
> + dma-names = "rx", "tx";
> + clocks = <&clks IMX6SLL_CLK_UART5_IPG>,
> + <&clks
> IMX6SLL_CLK_UART5_SERIAL>;
> + clock-names = "ipg", "per";
> + status = "disabled";
> + };
> + };
> + };
> +};
> --
> 1.9.1
^ permalink raw reply
* [PATCH v3 3/8] drm/mediatek: add connection from OD1 to RDMA1
From: CK Hu @ 2018-05-25 3:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527215665-11937-4-git-send-email-stu.hsieh@mediatek.com>
Hi, Stu:
On Fri, 2018-05-25 at 10:34 +0800, stu.hsieh at mediatek.com wrote:
> From: Stu Hsieh <stu.hsieh@mediatek.com>
>
> This patch add the connection from OD1 to RDMA1 for ext path.
>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
> Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> index 47ffa240bd25..0f568dd853d8 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> @@ -151,6 +151,9 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur,
> } else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
> *addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
> value = GAMMA_MOUT_EN_RDMA1;
> + } else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
> + *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> + value = OD1_MOUT_EN_RDMA1;
> } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> *addr = DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN;
> value = RDMA1_MOUT_DPI0;
^ permalink raw reply
* [PATCH v6 2/2] ARM: dts: imx: Add basic dts support for imx6sll EVK board
From: A.s. Dong @ 2018-05-25 3:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526899612-22856-2-git-send-email-ping.bai@nxp.com>
> -----Original Message-----
> From: Jacky Bai
> Sent: Monday, May 21, 2018 6:47 PM
> To: shawnguo at kernel.org; robh+dt at kernel.org; kernel at pengutronix.de
> Cc: Fabio Estevam <fabio.estevam@nxp.com>; devicetree at vger.kernel.org;
> linux-arm-kernel at lists.infradead.org; dl-linux-imx <linux-imx@nxp.com>;
> A.s. Dong <aisheng.dong@nxp.com>; jacky.baip at gmail.com
> Subject: [PATCH v6 2/2] ARM: dts: imx: Add basic dts support for imx6sll EVK
> board
>
> Add dts file support for imx6sll EVK board.
>
> Signed-off-by: Bai Ping <ping.bai@nxp.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---
> change v3->v4
> - update the license indentifier
> - remove leading zero of node
> - remove unused pin from hog group
> change v4->v5
> - use generic name for device node
> - remove unnecessary hog pin group
> change v5->v6
> - no
> ---
> Documentation/devicetree/bindings/arm/fsl.txt | 4 +
> arch/arm/boot/dts/Makefile | 2 +
> arch/arm/boot/dts/imx6sll-evk.dts | 315
> ++++++++++++++++++++++++++
> 3 files changed, 321 insertions(+)
> create mode 100644 arch/arm/boot/dts/imx6sll-evk.dts
>
> diff --git a/Documentation/devicetree/bindings/arm/fsl.txt
> b/Documentation/devicetree/bindings/arm/fsl.txt
> index cdb9dd7..8a1baa2 100644
> --- a/Documentation/devicetree/bindings/arm/fsl.txt
> +++ b/Documentation/devicetree/bindings/arm/fsl.txt
> @@ -53,6 +53,10 @@ i.MX6 Quad SABRE Automotive Board Required root
> node properties:
> - compatible = "fsl,imx6q-sabreauto", "fsl,imx6q";
>
> +i.MX6SLL EVK board
> +Required root node properties:
> + - compatible = "fsl,imx6sll-evk", "fsl,imx6sll";
> +
> Generic i.MX boards
> -------------------
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index f4753b0..f3fb85f 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -521,6 +521,8 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
> dtb-$(CONFIG_SOC_IMX6SL) += \
> imx6sl-evk.dtb \
> imx6sl-warp.dtb
> +dtb-$(CONFIG_SOC_IMX6SLL) += \
> + imx6sll-evk.dtb
> dtb-$(CONFIG_SOC_IMX6SX) += \
> imx6sx-nitrogen6sx.dtb \
> imx6sx-sabreauto.dtb \
> diff --git a/arch/arm/boot/dts/imx6sll-evk.dts b/arch/arm/boot/dts/imx6sll-
> evk.dts
> new file mode 100644
> index 0000000..0cfa4a2
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6sll-evk.dts
> @@ -0,0 +1,315 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright 2016 Freescale Semiconductor, Inc.
> + * Copyright 2017-2018 NXP.
> + *
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include "imx6sll.dtsi"
> +
> +/ {
> + model = "Freescale i.MX6SLL EVK Board";
> + compatible = "fsl,imx6sll-evk", "fsl,imx6sll";
> +
> + memory at 80000000 {
> + reg = <0x80000000 0x80000000>;
> + };
> +
> + backlight {
> + compatible = "pwm-backlight";
> + pwms = <&pwm1 0 5000000>;
> + brightness-levels = <0 4 8 16 32 64 128 255>;
> + default-brightness-level = <6>;
> + status = "okay";
> + };
> +
> + reg_usb_otg1_vbus: regulator-otg1-vbus {
> + compatible = "regulator-fixed";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usb_otg1_vbus>;
> + regulator-name = "usb_otg1_vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + gpio = <&gpio4 0 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
> + reg_usb_otg2_vbus: regulator-otg2-vbus {
> + compatible = "regulator-fixed";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usb_otg2_vbus>;
> + regulator-name = "usb_otg2_vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
> + reg_aud3v: regulator-aud3v {
> + compatible = "regulator-fixed";
> + regulator-name = "wm8962-supply-3v15";
> + regulator-min-microvolt = <3150000>;
> + regulator-max-microvolt = <3150000>;
> + regulator-boot-on;
> + };
> +
> + reg_aud4v: regulator-aud4v {
> + compatible = "regulator-fixed";
> + regulator-name = "wm8962-supply-4v2";
> + regulator-min-microvolt = <4325000>;
> + regulator-max-microvolt = <4325000>;
> + regulator-boot-on;
> + };
> +
> + reg_lcd: regulator-lcd {
> + compatible = "regulator-fixed";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_reg_lcd>;
> + regulator-name = "lcd-pwr";
> + gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
> + reg_sd1_vmmc: regulator-sd1-vmmc {
> + compatible = "regulator-fixed";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_reg_sd1_vmmc>;
> + regulator-name = "SD1_SPWR";
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3000000>;
> + gpio = <&gpio3 30 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +};
> +
> +&cpu0 {
> + arm-supply = <&sw1a_reg>;
> + soc-supply = <&sw1c_reg>;
> +};
> +
> +&i2c1 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c1>;
> + status = "okay";
> +
> + pfuze100: pmic at 8 {
> + compatible = "fsl,pfuze100";
> + reg = <0x08>;
> +
> + regulators {
> + sw1a_reg: sw1ab {
> + regulator-min-microvolt = <300000>;
> + regulator-max-microvolt = <1875000>;
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-ramp-delay = <6250>;
> + };
> +
> + sw1c_reg: sw1c {
> + regulator-min-microvolt = <300000>;
> + regulator-max-microvolt = <1875000>;
> + regulator-boot-on;
> + regulator-always-on;
> + regulator-ramp-delay = <6250>;
> + };
> +
> + sw2_reg: sw2 {
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + sw3a_reg: sw3a {
> + regulator-min-microvolt = <400000>;
> + regulator-max-microvolt = <1975000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + sw3b_reg: sw3b {
> + regulator-min-microvolt = <400000>;
> + regulator-max-microvolt = <1975000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + sw4_reg: sw4 {
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + swbst_reg: swbst {
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5150000>;
> + };
> +
> + snvs_reg: vsnvs {
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <3000000>;
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + vref_reg: vrefddr {
> + regulator-boot-on;
> + regulator-always-on;
> + };
> +
> + vgen1_reg: vgen1 {
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <1550000>;
> + regulator-always-on;
> + };
> +
> + vgen2_reg: vgen2 {
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <1550000>;
> + };
> +
> + vgen3_reg: vgen3 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + vgen4_reg: vgen4 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + vgen5_reg: vgen5 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + vgen6_reg: vgen6 {
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> + };
> + };
> +};
> +
> +&iomuxc {
> + pinctrl_usb_otg1_vbus: vbus1grp {
> + fsl,pins = <
> + MX6SLL_PAD_KEY_COL4__GPIO4_IO00 0x17059
> + >;
> + };
> +
> + pinctrl_usb_otg2_vbus: vbus2grp {
> + fsl,pins = <
> + MX6SLL_PAD_KEY_COL5__GPIO4_IO02 0x17059
> + >;
> + };
> +
> + pinctrl_reg_lcd: reglcdgrp {
> + fsl,pins = <
> + MX6SLL_PAD_ECSPI1_SCLK__GPIO4_IO08 0x17059
> + >;
> + };
> +
> + pinctrl_reg_sd1_vmmc: sd1vmmcgrp {
> + fsl,pins = <
> + MX6SLL_PAD_KEY_COL3__GPIO3_IO30 0x17059
> + >;
> + };
> +
> + pinctrl_uart1: uart1grp {
> + fsl,pins = <
> + MX6SLL_PAD_UART1_TXD__UART1_DCE_TX
> 0x1b0b1
> + MX6SLL_PAD_UART1_RXD__UART1_DCE_RX
> 0x1b0b1
> + >;
> + };
> +
> + pinctrl_usdhc1: usdhc1grp {
> + fsl,pins = <
> + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x17059
> + MX6SLL_PAD_SD1_CLK__SD1_CLK 0x13059
> + MX6SLL_PAD_SD1_DATA0__SD1_DATA0
> 0x17059
> + MX6SLL_PAD_SD1_DATA1__SD1_DATA1
> 0x17059
> + MX6SLL_PAD_SD1_DATA2__SD1_DATA2
> 0x17059
> + MX6SLL_PAD_SD1_DATA3__SD1_DATA3
> 0x17059
> + >;
> + };
> +
> + pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
> + fsl,pins = <
> + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170b9
> + MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130b9
> + MX6SLL_PAD_SD1_DATA0__SD1_DATA0
> 0x170b9
> + MX6SLL_PAD_SD1_DATA1__SD1_DATA1
> 0x170b9
> + MX6SLL_PAD_SD1_DATA2__SD1_DATA2
> 0x170b9
> + MX6SLL_PAD_SD1_DATA3__SD1_DATA3
> 0x170b9
> + >;
> + };
> +
> + pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
> + fsl,pins = <
> + MX6SLL_PAD_SD1_CMD__SD1_CMD 0x170f9
> + MX6SLL_PAD_SD1_CLK__SD1_CLK 0x130f9
> + MX6SLL_PAD_SD1_DATA0__SD1_DATA0
> 0x170f9
> + MX6SLL_PAD_SD1_DATA1__SD1_DATA1
> 0x170f9
> + MX6SLL_PAD_SD1_DATA2__SD1_DATA2
> 0x170f9
> + MX6SLL_PAD_SD1_DATA3__SD1_DATA3
> 0x170f9
> + >;
> + };
> +
> + pinctrl_usbotg1: usbotg1grp {
> + fsl,pins = <
> + MX6SLL_PAD_EPDC_PWR_COM__USB_OTG1_ID
> 0x17059
> + >;
> + };
> +
> + pinctrl_i2c1: i2c1grp {
> + fsl,pins = <
> + MX6SLL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1
> + MX6SLL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1
> + >;
> + };
> +};
Due to iomux node usually may expend largely, we choose better to put iomux node
at the end of this file to make other nodes easily looking.
Acked-by: Dong Aisheng <Aisheng.dong@nxp.com>
Regards
Dong Aisheng
> +
> +&uart1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart1>;
> + status = "okay";
> +};
> +
> +&usdhc1 {
> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> + pinctrl-0 = <&pinctrl_usdhc1>;
> + pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
> + pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
> + cd-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
> + wp-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
> + keep-power-in-suspend;
> + wakeup-source;
> + vmmc-supply = <®_sd1_vmmc>;
> + status = "okay";
> +};
> +
> +&usbotg1 {
> + vbus-supply = <®_usb_otg1_vbus>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usbotg1>;
> + disable-over-current;
> + srp-disable;
> + hnp-disable;
> + adp-disable;
> + status = "okay";
> +};
> +
> +&usbotg2 {
> + vbus-supply = <®_usb_otg2_vbus>;
> + dr_mode = "host";
> + disable-over-current;
> + status = "okay";
> +};
> --
> 1.9.1
^ permalink raw reply
* [GIT PULL] Qualcomm Driver Fixes for 4.17-rc7
From: Andy Gross @ 2018-05-25 3:55 UTC (permalink / raw)
To: linux-arm-kernel
The following changes since commit 771c577c23bac90597c685971d7297ea00f99d11:
Linux 4.17-rc6 (2018-05-20 15:31:38 -0700)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git tags/qcom-fixes-for-4.17-rc7
for you to fetch changes up to 5ec3444c8346c922316f4effafa8afc17defda0e:
firmware: qcom: scm: Fix crash in qcom_scm_call_atomic1() (2018-05-24 22:36:45 -0500)
----------------------------------------------------------------
Qualcomm Fixes for 4.17-rc7
* Fix crash in qcom_scm_call_atomic1()
----------------------------------------------------------------
Niklas Cassel (1):
firmware: qcom: scm: Fix crash in qcom_scm_call_atomic1()
drivers/firmware/qcom_scm-32.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
^ permalink raw reply
* [PATCH] arm64: defconfig: Enable UFS on msm8996
From: Bjorn Andersson @ 2018-05-25 4:02 UTC (permalink / raw)
To: linux-arm-kernel
Enable GLINK RPM so that we get RPM regulators and clocks and enable the
UFS host controller driver and the Qualcomm UFS platform driver. The UFS
phy is selected by the Qualcomm UFS driver.
The simple ondemand devfreq governor must be builtin, as there's no
mechanism for automatically loading it, causing UFS HCD initialization
to fail.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
arch/arm64/configs/defconfig | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 329950545603..895b2d92124d 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -191,6 +191,9 @@ CONFIG_BLK_DEV_SD=y
CONFIG_SCSI_SAS_ATA=y
CONFIG_SCSI_HISI_SAS=y
CONFIG_SCSI_HISI_SAS_PCI=y
+CONFIG_SCSI_UFSHCD=m
+CONFIG_SCSI_UFSHCD_PLATFORM=m
+CONFIG_SCSI_UFS_QCOM=m
CONFIG_ATA=y
CONFIG_SATA_AHCI=y
CONFIG_SATA_AHCI_PLATFORM=y
@@ -574,6 +577,7 @@ CONFIG_TEGRA_IOMMU_SMMU=y
CONFIG_ARM_SMMU=y
CONFIG_ARM_SMMU_V3=y
CONFIG_QCOM_IOMMU=y
+CONFIG_RPMSG_QCOM_GLINK_RPM=y
CONFIG_RPMSG_QCOM_SMD=y
CONFIG_RASPBERRYPI_POWER=y
CONFIG_QCOM_SMEM=y
@@ -585,6 +589,7 @@ CONFIG_ARCH_TEGRA_132_SOC=y
CONFIG_ARCH_TEGRA_210_SOC=y
CONFIG_ARCH_TEGRA_186_SOC=y
CONFIG_ARCH_TEGRA_194_SOC=y
+CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
CONFIG_EXTCON_USB_GPIO=y
CONFIG_EXTCON_USBC_CROS_EC=y
CONFIG_MEMORY=y
--
2.17.0
^ permalink raw reply related
* [PATCH v2 5/5] MAINTAINERS: Add Actions Semi S900 pinctrl entries
From: Andreas Färber @ 2018-05-25 4:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdYF7a-uwye0uwn-pT9Bprj74q1-Pcbq4WLyiE+kYY4j7w@mail.gmail.com>
Am 23.05.2018 um 10:40 schrieb Linus Walleij:
> On Sun, May 20, 2018 at 7:17 AM, Manivannan Sadhasivam
> <manivannan.sadhasivam@linaro.org> wrote:
>
>> Add S900 pinctrl entries under ARCH_ACTIONS
>>
>> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
>
> Patch applied tentatively so we have some maintenance entry for this.
>
> Andreas expressed concerns about the driver earlier, so he might want it
> split from the platform parts and have a separate entry for the pinctrl+GPIO
> so Manivannan can maintain that part, also it makes sense to list
> Manivannan as comaintainer of ARCH_ACTIONS with this in.
>
> Andreas: how would you like to proceed?
>
> I understand that I was a bit pushy or even rude in my last message
> about the maintenance of this platform and the code structure of
> the pin control driver. I am sorry if it caused any bad feelings on your
> side :( social conflicts give me the creeps, I just try my best. Maybe
> my best isn't always what it should be.
I fail to understand how splitting the MAINTAINERS section is going to
help with the pinctrl conflict at hand? The problem is that instead of
refactoring my S500 pinctrl driver to his liking, Mani has submitted a
competing S900 pinctrl driver that you went on to merge. The human
aspect is that merging his driver took the credit away from me having
written the earlier pinctrl driver (based on my rtd1295 pinctrl driver).
The practical aspect is that I can't drop my pinctrl driver from my work
branch until there is equivalent functionality in the merged driver. I
am lacking the time to rewrite S500 pin definitions on top of Mani's
myself at this time, and I haven't seen S500 patches from him yet.
Also I had been investing efforts in explaining the upstreaming process
to Actions, last in November. I see Thomas Liau and Jeff Chen missing in
CC and I have not seen any Reviewed-by or Acked-by from anyone at
Actions on this and the preceding series. There are more chips than the
one on Linaro's 96board, so I would prefer to assure that the design
works for all. Thus I am very critical of you applying the patches
without waiting for review by Actions.
Other aspects are: The reason I wrote the pinctrl driver is that I
experienced a UART TX issue on the Sparky board and was hoping a pinctrl
driver might resolve that, but it didn't. So I still have a mix of
boards where some are working and some are pretty unusable, without any
clues on why.
That said, I don't object to having a separate MAINTAINERS section for
the pinctrl driver(s) as long as I still get CC'ed on changes. We have
wanted to add Mani as R for Actions overall, so that would probably mean
adding me as R to an Actions pinctrl section, to avoid syncing the paths
between two sections. I had previously felt that it does not make sense
to list Mani as co-maintainer (M) for Actions overall since he can't tag
and submit from my repo. And for the record I have offered him to take
over which he didn't want to. I still hope to find some more time to
review and queue his SPS patches, a driver that I have designed and thus
understand and am much happier about the incremental additions there.
A further side note is that I had reached out about setting up an
infradead mailing list linux-actions, but there was no response from
David or anyone. Having an L on the section(s) would avoid messing with
R and hand-maintained CC lists. Any help with that appreciated.
Regards,
Andreas
--
SUSE Linux GmbH, Maxfeldstr. 5, 90409 N?rnberg, Germany
GF: Felix Imend?rffer, Jane Smithard, Graham Norton
HRB 21284 (AG N?rnberg)
^ permalink raw reply
* [PATCH v3 4/8] drm/mediatek: add ddp component AAL1
From: CK Hu @ 2018-05-25 4:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527215665-11937-5-git-send-email-stu.hsieh@mediatek.com>
Hi, Stu:
On Fri, 2018-05-25 at 10:34 +0800, stu.hsieh at mediatek.com wrote:
> From: Stu Hsieh <stu.hsieh@mediatek.com>
>
> This patch add component AAL1 and
> rename AAL to AAL0
>
> Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index 0828cf8bf85c..eee3c0cc2632 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -41,7 +41,8 @@ enum mtk_ddp_comp_type {
> };
>
> enum mtk_ddp_comp_id {
> - DDP_COMPONENT_AAL,
> + DDP_COMPONENT_AAL0,
> + DDP_COMPONENT_AAL1,
Be sure compiling is success when you apply each patch of a series. I
think when you apply to this patch, it would cause compiling error
because some related modification is in the patch 'Add support for
mediatek SOC MT2712'. So move the modification from that patch to this
patch.
Regards,
CK
> DDP_COMPONENT_BLS,
> DDP_COMPONENT_COLOR0,
> DDP_COMPONENT_COLOR1,
^ permalink raw reply
* [PATCH dts/arm/aspeed-g5 v1] ARM: dts: aspeed-g5: Add IPMI KCS node
From: Joel Stanley @ 2018-05-25 4:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <9231baaf-e77c-c517-bca2-083070a53342@linux.intel.com>
Hello Andrew,
On 16 March 2018 at 11:17, Wang, Haiyue <haiyue.wang@linux.intel.com> wrote:
> Hi Joel and Andrew,
>
> Have time to review this patch ? Hope for your comments. :-)
>
> BR,
> Haiyue
>
>
> On 2018-03-07 13:04, Haiyue Wang wrote:
>>
>> The IPMI KCS device part of the LPC interface and is used for
>> communication with the host processor.
>>
>> Signed-off-by: Haiyue Wang <haiyue.wang@linux.intel.com>
Do you have time to take a look at these? The device tree doesn't make
sense to me.
Cheers,
Joel
>> ---
>> arch/arm/boot/dts/aspeed-g5.dtsi | 43
>> +++++++++++++++++++++++++++++++++++++++-
>> 1 file changed, 42 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi
>> b/arch/arm/boot/dts/aspeed-g5.dtsi
>> index 8eac57c..f443169 100644
>> --- a/arch/arm/boot/dts/aspeed-g5.dtsi
>> +++ b/arch/arm/boot/dts/aspeed-g5.dtsi
>> @@ -267,8 +267,40 @@
>> ranges = <0x0 0x1e789000 0x1000>;
>> lpc_bmc: lpc-bmc at 0 {
>> - compatible =
>> "aspeed,ast2500-lpc-bmc";
>> + compatible =
>> "aspeed,ast2500-lpc-bmc", "simple-mfd", "syscon";
>> reg = <0x0 0x80>;
>> + reg-io-width = <4>;
>> +
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges = <0x0 0x0 0x80>;
>> +
>> + kcs1: kcs1 at 0 {
>> + compatible =
>> "aspeed,ast2500-kcs-bmc";
>> + reg = <0x0 0x80>;
>> + interrupts = <8>;
>> + kcs_chan = <1>;
>> + kcs_addr = <0x0>;
>> + status = "disabled";
>> + };
>> +
>> + kcs2: kcs2 at 0 {
>> + compatible =
>> "aspeed,ast2500-kcs-bmc";
>> + reg = <0x0 0x80>;
>> + interrupts = <8>;
>> + kcs_chan = <2>;
>> + kcs_addr = <0x0>;
>> + status = "disabled";
>> + };
>> +
>> + kcs3: kcs3 at 0 {
>> + compatible =
>> "aspeed,ast2500-kcs-bmc";
>> + reg = <0x0 0x80>;
>> + interrupts = <8>;
>> + kcs_chan = <3>;
>> + kcs_addr = <0x0>;
>> + status = "disabled";
>> + };
>> };
>> lpc_host: lpc-host at 80 {
>> @@ -294,6 +326,15 @@
>> status = "disabled";
>> };
>> + kcs4: kcs4 at 0 {
>> + compatible =
>> "aspeed,ast2500-kcs-bmc";
>> + reg = <0x0 0xa0>;
>> + interrupts = <8>;
>> + kcs_chan = <4>;
>> + kcs_addr = <0x0>;
>> + status = "disabled";
>> + };
>> +
>> lhc: lhc at 20 {
>> compatible =
>> "aspeed,ast2500-lhc";
>> reg = <0x20 0x24 0x48
>> 0x8>;
>
>
^ permalink raw reply
* [PATCH v6 05/17] media: rkisp1: add Rockchip ISP1 subdev driver
From: Tomasz Figa @ 2018-05-25 4:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180524113012.mt5b2f2vrhfrn3d7@tarshish>
On Thu, May 24, 2018 at 8:30 PM Baruch Siach <baruch@tkos.co.il> wrote:
> Hi Tomasz,
> On Mon, May 07, 2018 at 06:41:50AM +0000, Tomasz Figa wrote:
> > On Mon, May 7, 2018 at 3:38 PM Baruch Siach <baruch@tkos.co.il> wrote:
> > > On Mon, May 07, 2018 at 06:13:27AM +0000, Tomasz Figa wrote:
> > > > On Thu, May 3, 2018 at 6:09 PM Baruch Siach <baruch@tkos.co.il>
wrote:
> > > > > On Thu, Mar 08, 2018 at 05:47:55PM +0800, Jacob Chen wrote:
> > > > > > +static int rkisp1_isp_sd_s_power(struct v4l2_subdev *sd, int
on)
> > > > > > +{
> > > > > > + struct rkisp1_device *isp_dev = sd_to_isp_dev(sd);
> > > > > > + int ret;
> > > > > > +
> > > > > > + v4l2_dbg(1, rkisp1_debug, &isp_dev->v4l2_dev, "s_power:
%d\n",
> > > > on);
> > > > > > +
> > > > > > + if (on) {
> > > > > > + ret = pm_runtime_get_sync(isp_dev->dev);
> > > > > > + if (ret < 0)
> > > > > > + return ret;
> > > > > > +
> > > > > > + rkisp1_config_clk(isp_dev);
> > > > > > + } else {
> > > > > > + ret = pm_runtime_put(isp_dev->dev);
> > > >
> > > > > I commented this line out to make more than one STREAMON work.
> > Otherwise,
> > > > > the second STREAMON hangs. I guess the bug is not this driver.
> > Probably
> > > > > something in drivers/soc/rockchip/pm_domains.c. Just noting that
in
> > case
> > > > > you or someone on Cc would like to investigate it further.
> > > > >
> > > > > I tested v4.16-rc4 on the Tinkerboard.
> > > >
> > > > Looks like that version doesn't include the IOMMU PM and clock
handling
> > > > rework [1], which should fix a lot of runtime PM issues. FWIW,
> > linux-next
> > > > seems to already include it.
> > > >
> > > > [1] https://lkml.org/lkml/2018/3/23/44
> >
> > > Thanks for the reference.
> >
> > > It looks like the iommu driver part is in Linus' tree already. The DT
> > part is
> > > in the v4.18-armsoc/dts32 branch of Heiko's tree. Am I missing
anything?
> >
> > You're right, most of the series made it in time for 4.17. However, the
DT
> > part (precisely, the clocks properties added to IOMMU nodes) is crucial
for
> > the fixes to be effective.
> >
> > > Anyway, I'll take a look.
> >
> > Thanks for testing. :) (Forgot to mention in my previous email...)
> I finally got around to testing. Unfortunately, kernel v4.17-rc6 with
> cherry-pick of commit c78751f91c0b (ARM: dts: rockchip: add clocks in
iommu
> nodes) from Heiko's tree still exhibit the same problem. STREAMON hangs on
> second try. The same workaround "fixes" it.
Thanks for testing. I'm out of ideas, since the same code seems to work
fine for us in Chrome OS 4.4 kernel. Maybe we could have someone from RK
take a look.
Best regards,
Tomasz
^ permalink raw reply
* [PATCH v3 7/8] drm/mediatek: Add support for mediatek SOC MT2712
From: CK Hu @ 2018-05-25 4:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527215665-11937-8-git-send-email-stu.hsieh@mediatek.com>
Hi, Stu:
I've some inline comment.
On Fri, 2018-05-25 at 10:34 +0800, stu.hsieh at mediatek.com wrote:
> From: Stu Hsieh <stu.hsieh@mediatek.com>
>
> This patch add support for the Mediatek MT2712 DISP subsystem.
> There are two OVL engine and three disp output in MT2712.
>
> Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 46 +++++++++++++++++++++++++++--
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 8 +++--
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 42 ++++++++++++++++++++++++--
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 7 +++--
> 4 files changed, 94 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> index 0f568dd853d8..676726249ae0 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> @@ -61,6 +61,24 @@
> #define MT8173_MUTEX_MOD_DISP_PWM1 24
> #define MT8173_MUTEX_MOD_DISP_OD 25
>
> +#define MT2712_MUTEX_MOD_DISP_OVL0 11
> +#define MT2712_MUTEX_MOD_DISP_OVL1 12
> +#define MT2712_MUTEX_MOD_DISP_RDMA0 13
> +#define MT2712_MUTEX_MOD_DISP_RDMA1 14
> +#define MT2712_MUTEX_MOD_DISP_RDMA2 15
> +#define MT2712_MUTEX_MOD_DISP_WDMA0 16
> +#define MT2712_MUTEX_MOD_DISP_WDMA1 17
> +#define MT2712_MUTEX_MOD_DISP_COLOR0 18
> +#define MT2712_MUTEX_MOD_DISP_COLOR1 19
> +#define MT2712_MUTEX_MOD_DISP_AAL0 20
> +#define MT2712_MUTEX_MOD_DISP_UFOE 22
> +#define MT2712_MUTEX_MOD_DISP_PWM0 23
> +#define MT2712_MUTEX_MOD_DISP_PWM1 24
> +#define MT2712_MUTEX_MOD_DISP_PWM2 10
> +#define MT2712_MUTEX_MOD_DISP_OD0 25
> +#define MT2712_MUTEX_MOD2_DISP_AAL1 33
> +#define MT2712_MUTEX_MOD2_DISP_OD1 34
I would like this to be in the order by index.
> +
> #define MT2701_MUTEX_MOD_DISP_OVL 3
> #define MT2701_MUTEX_MOD_DISP_WDMA 6
> #define MT2701_MUTEX_MOD_DISP_COLOR 7
> @@ -75,6 +93,7 @@
>
> #define OVL0_MOUT_EN_COLOR0 0x1
> #define OD_MOUT_EN_RDMA0 0x1
> +#define OD1_MOUT_EN_RDMA1 BIT(16)
> #define UFOE_MOUT_EN_DSI0 0x1
> #define COLOR0_SEL_IN_OVL0 0x1
> #define OVL1_MOUT_EN_COLOR1 0x1
> @@ -109,12 +128,32 @@ static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA,
> };
>
> +static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> + [DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL0,
> + [DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1,
> + [DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0,
> + [DDP_COMPONENT_COLOR1] = MT2712_MUTEX_MOD_DISP_COLOR1,
> + [DDP_COMPONENT_OD0] = MT2712_MUTEX_MOD_DISP_OD0,
> + [DDP_COMPONENT_OD1] = MT2712_MUTEX_MOD2_DISP_OD1,
> + [DDP_COMPONENT_OVL0] = MT2712_MUTEX_MOD_DISP_OVL0,
> + [DDP_COMPONENT_OVL1] = MT2712_MUTEX_MOD_DISP_OVL1,
> + [DDP_COMPONENT_PWM0] = MT2712_MUTEX_MOD_DISP_PWM0,
> + [DDP_COMPONENT_PWM1] = MT2712_MUTEX_MOD_DISP_PWM1,
> + [DDP_COMPONENT_PWM2] = MT2712_MUTEX_MOD_DISP_PWM2,
> + [DDP_COMPONENT_RDMA0] = MT2712_MUTEX_MOD_DISP_RDMA0,
> + [DDP_COMPONENT_RDMA1] = MT2712_MUTEX_MOD_DISP_RDMA1,
> + [DDP_COMPONENT_RDMA2] = MT2712_MUTEX_MOD_DISP_RDMA2,
> + [DDP_COMPONENT_UFOE] = MT2712_MUTEX_MOD_DISP_UFOE,
> + [DDP_COMPONENT_WDMA0] = MT2712_MUTEX_MOD_DISP_WDMA0,
> + [DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1,
> +};
> +
> static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> - [DDP_COMPONENT_AAL] = MT8173_MUTEX_MOD_DISP_AAL,
> + [DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL,
Move this to the patch 'add ddp component AAL1'.
> [DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0,
> [DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1,
> [DDP_COMPONENT_GAMMA] = MT8173_MUTEX_MOD_DISP_GAMMA,
> - [DDP_COMPONENT_OD] = MT8173_MUTEX_MOD_DISP_OD,
> + [DDP_COMPONENT_OD0] = MT8173_MUTEX_MOD_DISP_OD,
Move this to the patch 'add ddp component OD1'.
> [DDP_COMPONENT_OVL0] = MT8173_MUTEX_MOD_DISP_OVL0,
> [DDP_COMPONENT_OVL1] = MT8173_MUTEX_MOD_DISP_OVL1,
> [DDP_COMPONENT_PWM0] = MT8173_MUTEX_MOD_DISP_PWM0,
> @@ -139,7 +178,7 @@ static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur,
> } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
> *addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
> value = OVL_MOUT_EN_RDMA;
> - } else if (cur == DDP_COMPONENT_OD && next == DDP_COMPONENT_RDMA0) {
> + } else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
Move this to the patch 'add ddp component OD1'.
> *addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> value = OD_MOUT_EN_RDMA0;
> } else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
> @@ -429,6 +468,7 @@ static int mtk_ddp_remove(struct platform_device *pdev)
>
> static const struct of_device_id ddp_driver_dt_match[] = {
> { .compatible = "mediatek,mt2701-disp-mutex", .data = mt2701_mutex_mod},
> + { .compatible = "mediatek,mt2712-disp-mutex", .data = mt2712_mutex_mod},
> { .compatible = "mediatek,mt8173-disp-mutex", .data = mt8173_mutex_mod},
> {},
> };
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 4672317e3ad1..86e8c9e5df41 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -218,7 +218,8 @@ struct mtk_ddp_comp_match {
> };
>
> static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
> - [DDP_COMPONENT_AAL] = { MTK_DISP_AAL, 0, &ddp_aal },
> + [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal },
> + [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal },
Move this to the patch 'add ddp component AAL1'.
> [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL },
> [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, NULL },
> [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, NULL },
> @@ -226,10 +227,13 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, NULL },
> [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, NULL },
> [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma },
> - [DDP_COMPONENT_OD] = { MTK_DISP_OD, 0, &ddp_od },
> + [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od },
> + [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od },
Move this to the patch 'add ddp component OD1'
> [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, NULL },
> [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, NULL },
> [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
> + [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
Move this to the patch 'add ddp component PWM1'
> + [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
Move this to the patch 'add ddp component PWM2'
> [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, NULL },
> [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, NULL },
> [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, NULL },
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index a2ca90fc403c..b32c4cc8d051 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -146,11 +146,37 @@ static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = {
> DDP_COMPONENT_DPI0,
> };
>
> +static const enum mtk_ddp_comp_id mt2712_mtk_ddp_main[] = {
> + DDP_COMPONENT_OVL0,
> + DDP_COMPONENT_COLOR0,
> + DDP_COMPONENT_AAL0,
> + DDP_COMPONENT_OD0,
> + DDP_COMPONENT_RDMA0,
> + DDP_COMPONENT_DPI0,
> + DDP_COMPONENT_PWM0,
> +};
> +
> +static const enum mtk_ddp_comp_id mt2712_mtk_ddp_ext[] = {
> + DDP_COMPONENT_OVL1,
> + DDP_COMPONENT_COLOR1,
> + DDP_COMPONENT_AAL1,
> + DDP_COMPONENT_OD1,
> + DDP_COMPONENT_RDMA1,
> + DDP_COMPONENT_DPI1,
> + DDP_COMPONENT_PWM1,
> +};
> +
> +static const enum mtk_ddp_comp_id mt2712_mtk_ddp_third[] = {
> + DDP_COMPONENT_RDMA2,
> + DDP_COMPONENT_DSI2,
> + DDP_COMPONENT_PWM2,
> +};
> +
> static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = {
> DDP_COMPONENT_OVL0,
> DDP_COMPONENT_COLOR0,
> - DDP_COMPONENT_AAL,
> - DDP_COMPONENT_OD,
> + DDP_COMPONENT_AAL0,
Move this to the patch 'add ddp component AAL1'.
> + DDP_COMPONENT_OD0,
Move this to the patch 'add ddp component OD1'
> DDP_COMPONENT_RDMA0,
> DDP_COMPONENT_UFOE,
> DDP_COMPONENT_DSI0,
> @@ -173,6 +199,15 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
> .shadow_register = true,
> };
>
> +static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
> + .main_path = mt2712_mtk_ddp_main,
> + .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main),
> + .ext_path = mt2712_mtk_ddp_ext,
> + .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext),
> + .third_path = mt2712_mtk_ddp_third,
> + .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
> +};
> +
> static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
> .main_path = mt8173_mtk_ddp_main,
> .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
> @@ -374,6 +409,7 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
> { .compatible = "mediatek,mt8173-dsi", .data = (void *)MTK_DSI },
> { .compatible = "mediatek,mt8173-dpi", .data = (void *)MTK_DPI },
> { .compatible = "mediatek,mt2701-disp-mutex", .data = (void *)MTK_DISP_MUTEX },
> + { .compatible = "mediatek,mt2712-disp-mutex", .data = (void *)MTK_DISP_MUTEX },
> { .compatible = "mediatek,mt8173-disp-mutex", .data = (void *)MTK_DISP_MUTEX },
> { .compatible = "mediatek,mt2701-disp-pwm", .data = (void *)MTK_DISP_BLS },
> { .compatible = "mediatek,mt8173-disp-pwm", .data = (void *)MTK_DISP_PWM },
> @@ -552,6 +588,8 @@ static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend,
> static const struct of_device_id mtk_drm_of_ids[] = {
> { .compatible = "mediatek,mt2701-mmsys",
> .data = &mt2701_mmsys_driver_data},
> + { .compatible = "mediatek,mt2712-mmsys",
> + .data = &mt2712_mmsys_driver_data},
> { .compatible = "mediatek,mt8173-mmsys",
> .data = &mt8173_mmsys_driver_data},
> { }
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> index c3378c452c0a..e821342bc2d3 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> @@ -17,8 +17,8 @@
> #include <linux/io.h>
> #include "mtk_drm_ddp_comp.h"
>
> -#define MAX_CRTC 2
> -#define MAX_CONNECTOR 2
> +#define MAX_CRTC 3
> +#define MAX_CONNECTOR 3
>
> struct device;
> struct device_node;
> @@ -33,6 +33,9 @@ struct mtk_mmsys_driver_data {
> unsigned int main_len;
> const enum mtk_ddp_comp_id *ext_path;
> unsigned int ext_len;
> + enum mtk_ddp_comp_id *third_path;
> + unsigned int third_len;
> +
Move this to the patch 'add third ddp path'.
> bool shadow_register;
> };
>
Regards,
CK
^ permalink raw reply
* [PATCH v3 8/8] drm/mediatek: add third ddp path
From: CK Hu @ 2018-05-25 5:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1527215665-11937-9-git-send-email-stu.hsieh@mediatek.com>
Hi, Stu:
On Fri, 2018-05-25 at 10:34 +0800, stu.hsieh at mediatek.com wrote:
> From: Stu Hsieh <stu.hsieh@mediatek.com>
>
> This patch create third crtc by third ddp path
>
Apply this patch before the patch 'Add support for mediatek SOC MT2712'
because this patch is necessary for mt2712.
> Signed-off-by: Stu Hsieh <stu.hsieh@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index b32c4cc8d051..3a866e1d6af4 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -267,6 +267,11 @@ static int mtk_drm_kms_init(struct drm_device *drm)
> if (ret < 0)
> goto err_component_unbind;
>
> + ret = mtk_drm_crtc_create(drm, private->data->third_path,
> + private->data->third_len);
I think you should prevent doing this for mt8173 and mt2701 because that
two SoC has only two ddp path.
Regards,
CK
> + if (ret < 0)
> + goto err_component_unbind;
> +
> /* Use OVL device for all DMA memory allocations */
> np = private->comp_node[private->data->main_path[0]] ?:
> private->comp_node[private->data->ext_path[0]];
^ permalink raw reply
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