* [PATCH] irqchip/gic-v3-its: fix ITS queue timeout
From: Yang Yingliang @ 2018-06-06 1:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <834fde1b-5ae0-afc6-283f-2a470757e54a@arm.com>
Hi, Julien
On 2018/6/5 18:16, Julien Thierry wrote:
> Hi Yang,
>
> On 05/06/18 07:30, Yang Yingliang wrote:
>> When the kernel booted with maxcpus=x, 'x' is smaller
>> than actual cpu numbers, the TAs of offline cpus won't
>> be set to its->collection.
>>
>> If LPI is bind to offline cpu, sync cmd will use zero TA,
>> it leads to ITS queue timeout. Fix this by choosing a
>> online cpu, if there is no online cpu in cpu_mask.
>>
>> Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
>> ---
>> drivers/irqchip/irq-gic-v3-its.c | 9 +++++++--
>> 1 file changed, 7 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/irqchip/irq-gic-v3-its.c
>> b/drivers/irqchip/irq-gic-v3-its.c
>> index 5416f2b..edd92a9 100644
>> --- a/drivers/irqchip/irq-gic-v3-its.c
>> +++ b/drivers/irqchip/irq-gic-v3-its.c
>> @@ -2309,7 +2309,9 @@ static int its_irq_domain_activate(struct
>> irq_domain *domain,
>> cpu_mask = cpumask_of_node(its_dev->its->numa_node);
>> /* Bind the LPI to the first possible CPU */
>> - cpu = cpumask_first(cpu_mask);
>> + cpu = cpumask_first_and(cpu_mask, cpu_online_mask);
>> + if (!cpu_online(cpu))
>
> Testing for cpu being online here feels a bit redundant.
>
> Since cpu is online if the cpumask_first_and returns a valid cpu, I
> think you could replace this test with:
>
> if (cpu >= nr_cpu_ids)
Yes, I used wrong check here, according to comment of cpumask_first_and,
this func will returns >= nr_cpu_ids if no cpus set in both.
I'll send v2 later.
>
>> + cpu = cpumask_first(cpu_online_mask);
>> its_dev->event_map.col_map[event] = cpu;
>> irq_data_update_effective_affinity(d, cpumask_of(cpu));
>> @@ -2466,7 +2468,10 @@ static int its_vpe_set_affinity(struct
>> irq_data *d,
>> bool force)
>> {
>> struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
>> - int cpu = cpumask_first(mask_val);
>> + int cpu = cpumask_first_and(mask_val, cpu_online_mask);
>> +
>> + if (!cpu_online(cpu))
>
> Same thing here.
>
>> + cpu = cpumask_first(cpu_online_mask);
>> /*
>> * Changing affinity is mega expensive, so let's be as lazy as
>>
>
> Cheers,
>
Thanks,
Yang
^ permalink raw reply
* [PATCH v2] irqchip/gic-v3-its: fix ITS queue timeout
From: Yang Yingliang @ 2018-06-06 2:40 UTC (permalink / raw)
To: linux-arm-kernel
When the kernel booted with maxcpus=x, 'x' is smaller
than actual cpu numbers, the TAs of offline cpus won't
be set to its->collection.
If LPI is bind to offline cpu, sync cmd will use zero TA,
it leads to ITS queue timeout. Fix this by choosing a
online cpu, if there is no online cpu in cpu_mask.
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
---
drivers/irqchip/irq-gic-v3-its.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 5416f2b..d8b9539 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -2309,7 +2309,9 @@ static int its_irq_domain_activate(struct irq_domain *domain,
cpu_mask = cpumask_of_node(its_dev->its->numa_node);
/* Bind the LPI to the first possible CPU */
- cpu = cpumask_first(cpu_mask);
+ cpu = cpumask_first_and(cpu_mask, cpu_online_mask);
+ if (cpu >= nr_cpu_ids)
+ cpu = cpumask_first(cpu_online_mask);
its_dev->event_map.col_map[event] = cpu;
irq_data_update_effective_affinity(d, cpumask_of(cpu));
@@ -2466,7 +2468,10 @@ static int its_vpe_set_affinity(struct irq_data *d,
bool force)
{
struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
- int cpu = cpumask_first(mask_val);
+ int cpu = cpumask_first_and(mask_val, cpu_online_mask);
+
+ if (cpu >= nr_cpu_ids)
+ cpu = cpumask_first(cpu_online_mask);
/*
* Changing affinity is mega expensive, so let's be as lazy as
--
1.8.3
^ permalink raw reply related
* [PATCH v3 0/3] arm64/mm: migrate swapper_pg_dir
From: Jun Yao @ 2018-06-06 4:39 UTC (permalink / raw)
To: linux-arm-kernel
Version 3 changes:
* Fix memory leak problem with CONFIG_ARM64_SW_TTBR0_PAN
* add comment explaining why the flush is needed and also why
__pa_swapper_pg_dir gets placed in the .mmuoff.data.read
section.
[v2] https://www.spinics.net/lists/arm-kernel/msg657549.html
[v1] https://www.spinics.net/lists/kernel/msg2819351.html
Jun Yao (3):
arm64/mm: pass swapper_pg_dir as an argument to __enable_mmu()
arm64/mm: introduce variable to save new swapper_pg_dir address
arm64/mm: migrate swapper_pg_dir and tramp_pg_dir
arch/arm64/include/asm/mmu_context.h | 6 +-
arch/arm64/include/asm/pgtable.h | 3 +
arch/arm64/kernel/cpufeature.c | 2 +-
arch/arm64/kernel/head.S | 6 +-
arch/arm64/kernel/hibernate.c | 2 +-
arch/arm64/kernel/sleep.S | 1 +
arch/arm64/mm/kasan_init.c | 6 +-
arch/arm64/mm/mmu.c | 97 ++++++++++++++++++++--------
8 files changed, 84 insertions(+), 39 deletions(-)
--
2.17.0
^ permalink raw reply
* [PATCH v3 1/3] arm64/mm: pass swapper_pg_dir as an argument to __enable_mmu()
From: Jun Yao @ 2018-06-06 4:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180606043921.19851-1-yaojun8558363@gmail.com>
Introduce __pa_swapper_pg_dir to save physical address of
swapper_pg_dir. And pass it as an argument to __enable_mmu().
Signed-off-by: Jun Yao <yaojun8558363@gmail.com>
---
arch/arm64/include/asm/mmu_context.h | 4 +---
arch/arm64/include/asm/pgtable.h | 1 +
arch/arm64/kernel/cpufeature.c | 2 +-
arch/arm64/kernel/head.S | 6 ++++--
arch/arm64/kernel/hibernate.c | 2 +-
arch/arm64/kernel/sleep.S | 1 +
arch/arm64/mm/kasan_init.c | 4 ++--
arch/arm64/mm/mmu.c | 20 ++++++++++++++++++--
8 files changed, 29 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/mmu_context.h
index 39ec0b8a689e..3eddb871f251 100644
--- a/arch/arm64/include/asm/mmu_context.h
+++ b/arch/arm64/include/asm/mmu_context.h
@@ -141,14 +141,12 @@ static inline void cpu_install_idmap(void)
* Atomically replaces the active TTBR1_EL1 PGD with a new VA-compatible PGD,
* avoiding the possibility of conflicting TLB entries being allocated.
*/
-static inline void cpu_replace_ttbr1(pgd_t *pgdp)
+static inline void cpu_replace_ttbr1(phys_addr_t pgd_phys)
{
typedef void (ttbr_replace_func)(phys_addr_t);
extern ttbr_replace_func idmap_cpu_replace_ttbr1;
ttbr_replace_func *replace_phys;
- phys_addr_t pgd_phys = virt_to_phys(pgdp);
-
replace_phys = (void *)__pa_symbol(idmap_cpu_replace_ttbr1);
cpu_install_idmap();
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index 7c4c8f318ba9..519ab5581b08 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -722,6 +722,7 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
extern pgd_t swapper_pg_end[];
extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
extern pgd_t tramp_pg_dir[PTRS_PER_PGD];
+extern volatile phys_addr_t __pa_swapper_pg_dir;
/*
* Encode and decode a swap entry:
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index d2856b129097..e3d76a9dd67a 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -917,7 +917,7 @@ kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings);
cpu_install_idmap();
- remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir));
+ remap_fn(cpu, num_online_cpus(), __pa_swapper_pg_dir);
cpu_uninstall_idmap();
if (!cpu)
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index b0853069702f..2e871b1cb75f 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -706,6 +706,7 @@ secondary_startup:
* Common entry point for secondary CPUs.
*/
bl __cpu_setup // initialise processor
+ ldr_l x26, __pa_swapper_pg_dir
bl __enable_mmu
ldr x8, =__secondary_switched
br x8
@@ -748,6 +749,7 @@ ENDPROC(__secondary_switched)
* Enable the MMU.
*
* x0 = SCTLR_EL1 value for turning on the MMU.
+ * x26 = TTBR1 value for turning on the MMU.
*
* Returns to the caller via x30/lr. This requires the caller to be covered
* by the .idmap.text section.
@@ -762,9 +764,8 @@ ENTRY(__enable_mmu)
b.ne __no_granule_support
update_early_cpu_boot_status 0, x1, x2
adrp x1, idmap_pg_dir
- adrp x2, swapper_pg_dir
phys_to_ttbr x3, x1
- phys_to_ttbr x4, x2
+ phys_to_ttbr x4, x26
msr ttbr0_el1, x3 // load TTBR0
msr ttbr1_el1, x4 // load TTBR1
isb
@@ -823,6 +824,7 @@ __primary_switch:
mrs x20, sctlr_el1 // preserve old SCTLR_EL1 value
#endif
+ adrp x26, swapper_pg_dir
bl __enable_mmu
#ifdef CONFIG_RELOCATABLE
bl __relocate_kernel
diff --git a/arch/arm64/kernel/hibernate.c b/arch/arm64/kernel/hibernate.c
index 6b2686d54411..0a0a0ca19f9b 100644
--- a/arch/arm64/kernel/hibernate.c
+++ b/arch/arm64/kernel/hibernate.c
@@ -125,7 +125,7 @@ int arch_hibernation_header_save(void *addr, unsigned int max_size)
return -EOVERFLOW;
arch_hdr_invariants(&hdr->invariants);
- hdr->ttbr1_el1 = __pa_symbol(swapper_pg_dir);
+ hdr->ttbr1_el1 = __pa_swapper_pg_dir;
hdr->reenter_kernel = _cpu_resume;
/* We can't use __hyp_get_vectors() because kvm may still be loaded */
diff --git a/arch/arm64/kernel/sleep.S b/arch/arm64/kernel/sleep.S
index bebec8ef9372..03854c329449 100644
--- a/arch/arm64/kernel/sleep.S
+++ b/arch/arm64/kernel/sleep.S
@@ -101,6 +101,7 @@ ENTRY(cpu_resume)
bl el2_setup // if in EL2 drop to EL1 cleanly
bl __cpu_setup
/* enable the MMU early - so we can access sleep_save_stash by va */
+ ldr_l x26, __pa_swapper_pg_dir
bl __enable_mmu
ldr x8, =_cpu_resume
br x8
diff --git a/arch/arm64/mm/kasan_init.c b/arch/arm64/mm/kasan_init.c
index 12145874c02b..dd4f28c19165 100644
--- a/arch/arm64/mm/kasan_init.c
+++ b/arch/arm64/mm/kasan_init.c
@@ -199,7 +199,7 @@ void __init kasan_init(void)
*/
memcpy(tmp_pg_dir, swapper_pg_dir, sizeof(tmp_pg_dir));
dsb(ishst);
- cpu_replace_ttbr1(lm_alias(tmp_pg_dir));
+ cpu_replace_ttbr1(__pa_symbol(tmp_pg_dir));
clear_pgds(KASAN_SHADOW_START, KASAN_SHADOW_END);
@@ -236,7 +236,7 @@ void __init kasan_init(void)
pfn_pte(sym_to_pfn(kasan_zero_page), PAGE_KERNEL_RO));
memset(kasan_zero_page, 0, PAGE_SIZE);
- cpu_replace_ttbr1(lm_alias(swapper_pg_dir));
+ cpu_replace_ttbr1(__pa_swapper_pg_dir);
/* At this point kasan is fully initialized. Enable error messages */
init_task.kasan_depth = 0;
diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
index 2dbb2c9f1ec1..d518e27792ef 100644
--- a/arch/arm64/mm/mmu.c
+++ b/arch/arm64/mm/mmu.c
@@ -55,6 +55,13 @@ u64 idmap_ptrs_per_pgd = PTRS_PER_PGD;
u64 kimage_voffset __ro_after_init;
EXPORT_SYMBOL(kimage_voffset);
+/*
+ * Ensure that hibernate will re-clean this value to the PoC once
+ * it has restored the memory.
+ */
+volatile phys_addr_t __section(".mmuoff.data.read")
+__pa_swapper_pg_dir;
+
/*
* Empty_zero_page is a special page that is used for zero-initialized data
* and COW.
@@ -631,6 +638,15 @@ void __init paging_init(void)
phys_addr_t pgd_phys = early_pgtable_alloc();
pgd_t *pgdp = pgd_set_fixmap(pgd_phys);
+ __pa_swapper_pg_dir = __pa_symbol(swapper_pg_dir);
+
+ /*
+ * We need to clean '__pa_swapper_pg_dir' to the PoC, so that
+ * secondaries will read the new value.
+ */
+ __flush_dcache_area((void *)&__pa_swapper_pg_dir,
+ sizeof(__pa_swapper_pg_dir));
+
map_kernel(pgdp);
map_mem(pgdp);
@@ -642,9 +658,9 @@ void __init paging_init(void)
*
* To do this we need to go via a temporary pgd.
*/
- cpu_replace_ttbr1(__va(pgd_phys));
+ cpu_replace_ttbr1(pgd_phys);
memcpy(swapper_pg_dir, pgdp, PGD_SIZE);
- cpu_replace_ttbr1(lm_alias(swapper_pg_dir));
+ cpu_replace_ttbr1(__pa_swapper_pg_dir);
pgd_clear_fixmap();
memblock_free(pgd_phys, PAGE_SIZE);
--
2.17.0
^ permalink raw reply related
* [PATCH v3 2/3] arm64/mm: introduce variable to save new swapper_pg_dir address
From: Jun Yao @ 2018-06-06 4:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180606043921.19851-1-yaojun8558363@gmail.com>
Prepare for migrating swapper_pg_dir, introduce new_swapper_pg_dir
to save virtual address of swapper_pg_dir.
Signed-off-by: Jun Yao <yaojun8558363@gmail.com>
---
arch/arm64/include/asm/mmu_context.h | 2 +-
arch/arm64/include/asm/pgtable.h | 1 +
arch/arm64/mm/kasan_init.c | 2 +-
arch/arm64/mm/mmu.c | 2 ++
4 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/mmu_context.h
index 3eddb871f251..481c2d16adeb 100644
--- a/arch/arm64/include/asm/mmu_context.h
+++ b/arch/arm64/include/asm/mmu_context.h
@@ -57,7 +57,7 @@ static inline void cpu_set_reserved_ttbr0(void)
static inline void cpu_switch_mm(pgd_t *pgd, struct mm_struct *mm)
{
- BUG_ON(pgd == swapper_pg_dir);
+ BUG_ON(pgd == new_swapper_pg_dir);
cpu_set_reserved_ttbr0();
cpu_do_switch_mm(virt_to_phys(pgd),mm);
}
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index 519ab5581b08..2bda899dcf22 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -723,6 +723,7 @@ extern pgd_t swapper_pg_end[];
extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
extern pgd_t tramp_pg_dir[PTRS_PER_PGD];
extern volatile phys_addr_t __pa_swapper_pg_dir;
+extern pgd_t *new_swapper_pg_dir;
/*
* Encode and decode a swap entry:
diff --git a/arch/arm64/mm/kasan_init.c b/arch/arm64/mm/kasan_init.c
index dd4f28c19165..08bcaae4725e 100644
--- a/arch/arm64/mm/kasan_init.c
+++ b/arch/arm64/mm/kasan_init.c
@@ -197,7 +197,7 @@ void __init kasan_init(void)
* tmp_pg_dir used to keep early shadow mapped until full shadow
* setup will be finished.
*/
- memcpy(tmp_pg_dir, swapper_pg_dir, sizeof(tmp_pg_dir));
+ memcpy(tmp_pg_dir, new_swapper_pg_dir, sizeof(tmp_pg_dir));
dsb(ishst);
cpu_replace_ttbr1(__pa_symbol(tmp_pg_dir));
diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
index d518e27792ef..94056e064c6f 100644
--- a/arch/arm64/mm/mmu.c
+++ b/arch/arm64/mm/mmu.c
@@ -62,6 +62,8 @@ EXPORT_SYMBOL(kimage_voffset);
volatile phys_addr_t __section(".mmuoff.data.read")
__pa_swapper_pg_dir;
+pgd_t *new_swapper_pg_dir = swapper_pg_dir;
+
/*
* Empty_zero_page is a special page that is used for zero-initialized data
* and COW.
--
2.17.0
^ permalink raw reply related
* [PATCH v3 3/3] arm64/mm: migrate swapper_pg_dir and tramp_pg_dir
From: Jun Yao @ 2018-06-06 4:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180606043921.19851-1-yaojun8558363@gmail.com>
Migrate swapper_pg_dir and tramp_pg_dir. And their virtual addresses
do not correlate with kernel's address.
Signed-off-by: Jun Yao <yaojun8558363@gmail.com>
---
arch/arm64/include/asm/pgtable.h | 1 +
arch/arm64/mm/mmu.c | 79 +++++++++++++++++++++-----------
2 files changed, 52 insertions(+), 28 deletions(-)
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index 2bda899dcf22..b032d6c2e390 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -722,6 +722,7 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
extern pgd_t swapper_pg_end[];
extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
extern pgd_t tramp_pg_dir[PTRS_PER_PGD];
+extern pgd_t reserved_ttbr0[PTRS_PER_PGD];
extern volatile phys_addr_t __pa_swapper_pg_dir;
extern pgd_t *new_swapper_pg_dir;
diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
index 94056e064c6f..ba0b55158971 100644
--- a/arch/arm64/mm/mmu.c
+++ b/arch/arm64/mm/mmu.c
@@ -63,6 +63,9 @@ volatile phys_addr_t __section(".mmuoff.data.read")
__pa_swapper_pg_dir;
pgd_t *new_swapper_pg_dir = swapper_pg_dir;
+#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
+pgd_t *new_tramp_pg_dir;
+#endif
/*
* Empty_zero_page is a special page that is used for zero-initialized data
@@ -86,19 +89,14 @@ pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
}
EXPORT_SYMBOL(phys_mem_access_prot);
-static phys_addr_t __init early_pgtable_alloc(void)
+static void __init clear_page_phys(phys_addr_t phys)
{
- phys_addr_t phys;
- void *ptr;
-
- phys = memblock_alloc(PAGE_SIZE, PAGE_SIZE);
-
/*
* The FIX_{PGD,PUD,PMD} slots may be in active use, but the FIX_PTE
* slot will be free, so we can (ab)use the FIX_PTE slot to initialise
* any level of table.
*/
- ptr = pte_set_fixmap(phys);
+ void *ptr = pte_set_fixmap(phys);
memset(ptr, 0, PAGE_SIZE);
@@ -107,6 +105,14 @@ static phys_addr_t __init early_pgtable_alloc(void)
* table walker
*/
pte_clear_fixmap();
+}
+
+static phys_addr_t __init early_pgtable_alloc(void)
+{
+ phys_addr_t phys;
+
+ phys = memblock_alloc(PAGE_SIZE, PAGE_SIZE);
+ clear_page_phys(phys);
return phys;
}
@@ -560,6 +566,10 @@ static int __init map_entry_trampoline(void)
__create_pgd_mapping(tramp_pg_dir, pa_start, TRAMP_VALIAS, PAGE_SIZE,
prot, pgd_pgtable_alloc, 0);
+ memcpy(new_tramp_pg_dir, tramp_pg_dir, PGD_SIZE);
+ memblock_free(__pa_symbol(tramp_pg_dir),
+ __pa_symbol(swapper_pg_dir) - __pa_symbol(tramp_pg_dir));
+
/* Map both the text and data into the kernel page table */
__set_fixmap(FIX_ENTRY_TRAMP_TEXT, pa_start, prot);
if (IS_ENABLED(CONFIG_RANDOMIZE_BASE)) {
@@ -637,10 +647,29 @@ static void __init map_kernel(pgd_t *pgdp)
*/
void __init paging_init(void)
{
- phys_addr_t pgd_phys = early_pgtable_alloc();
- pgd_t *pgdp = pgd_set_fixmap(pgd_phys);
+ phys_addr_t pgd_phys;
+ pgd_t *pgdp;
+ phys_addr_t mem_size;
- __pa_swapper_pg_dir = __pa_symbol(swapper_pg_dir);
+ mem_size = __pa_symbol(swapper_pg_dir) + PAGE_SIZE
+ - (__pa_symbol(idmap_pg_dir) + IDMAP_DIR_SIZE);
+
+ if (mem_size == PAGE_SIZE) {
+ pgd_phys = early_pgtable_alloc();
+ __pa_swapper_pg_dir = pgd_phys;
+ } else {
+ phys_addr_t p;
+
+ pgd_phys = memblock_alloc(mem_size, PAGE_SIZE);
+
+ for (p = pgd_phys; p < pgd_phys + mem_size; p += PAGE_SIZE)
+ clear_page_phys(p);
+
+ #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
+ new_tramp_pg_dir = __va(pgd_phys);
+ #endif
+ __pa_swapper_pg_dir = pgd_phys + mem_size - PAGE_SIZE;
+ }
/*
* We need to clean '__pa_swapper_pg_dir' to the PoC, so that
@@ -649,31 +678,25 @@ void __init paging_init(void)
__flush_dcache_area((void *)&__pa_swapper_pg_dir,
sizeof(__pa_swapper_pg_dir));
+ new_swapper_pg_dir = __va(__pa_swapper_pg_dir);
+
+ pgdp = pgd_set_fixmap(__pa_swapper_pg_dir);
+
map_kernel(pgdp);
map_mem(pgdp);
- /*
- * We want to reuse the original swapper_pg_dir so we don't have to
- * communicate the new address to non-coherent secondaries in
- * secondary_entry, and so cpu_switch_mm can generate the address with
- * adrp+add rather than a load from some global variable.
- *
- * To do this we need to go via a temporary pgd.
- */
- cpu_replace_ttbr1(pgd_phys);
- memcpy(swapper_pg_dir, pgdp, PGD_SIZE);
cpu_replace_ttbr1(__pa_swapper_pg_dir);
+ init_mm.pgd = new_swapper_pg_dir;
pgd_clear_fixmap();
- memblock_free(pgd_phys, PAGE_SIZE);
- /*
- * We only reuse the PGD from the swapper_pg_dir, not the pud + pmd
- * allocated with it.
- */
- memblock_free(__pa_symbol(swapper_pg_dir) + PAGE_SIZE,
- __pa_symbol(swapper_pg_end) - __pa_symbol(swapper_pg_dir)
- - PAGE_SIZE);
+#ifdef CONFIG_ARM64_SW_TTBR0_PAN
+ memblock_free(__pa_symbol(reserved_ttbr0), RESERVED_TTBR0_SIZE);
+#endif
+
+ memblock_free(__pa_symbol(swapper_pg_dir),
+ __pa_symbol(swapper_pg_end) - __pa_symbol(swapper_pg_dir));
+
}
/*
--
2.17.0
^ permalink raw reply related
* [RFC PATCH -tip v5 06/27] arm64: kprobes: Remove jprobe implementation
From: Masami Hiramatsu @ 2018-06-06 4:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180605153420.GA26352@arm.com>
On Tue, 5 Jun 2018 16:34:21 +0100
Will Deacon <will.deacon@arm.com> wrote:
> On Tue, Jun 05, 2018 at 12:51:24AM +0900, Masami Hiramatsu wrote:
> > Remove arch dependent setjump/longjump functions
> > and unused fields in kprobe_ctlblk for jprobes
> > from arch/arm64.
> >
> > Signed-off-by: Masami Hiramatsu <mhiramat@kernel.org>
> > Cc: Catalin Marinas <catalin.marinas@arm.com>
> > Cc: Will Deacon <will.deacon@arm.com>
> > Cc: linux-arm-kernel at lists.infradead.org
> > ---
> > arch/arm64/include/asm/kprobes.h | 1 -
> > arch/arm64/kernel/probes/kprobes.c | 68 ------------------------------------
> > 2 files changed, 69 deletions(-)
>
> Acked-by: Will Deacon <will.deacon@arm.com>
Thank you Will!
--
Masami Hiramatsu <mhiramat@kernel.org>
^ permalink raw reply
* [PATCH v2 0/3] arm64: allwinner: a64: Add initial support for Pinebook
From: Vasily Khoruzhick @ 2018-06-06 5:16 UTC (permalink / raw)
To: linux-arm-kernel
This series adds dts for Pinebook with few prerequisites - PWM and R_I2C
devices nodes.
v2: - add my signoff
- add default pinmux option for PWM
- add alternate pinmux option for R_I2C controller
- add A64 compatible for R_I2C controller
Andre Przywara (1):
arm64: dts: allwinner: a64: Add PWM controllers
Icenowy Zheng (2):
arm64: dts: allwinner: a64: add R_I2C controller
arm64: dts: allwinner: add support for Pinebook
arch/arm64/boot/dts/allwinner/Makefile | 1 +
.../dts/allwinner/sun50i-a64-pinebook.dts | 280 ++++++++++++++++++
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 56 ++++
3 files changed, 337 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
--
2.17.1
^ permalink raw reply
* [PATCH v2 1/3] arm64: dts: allwinner: a64: add R_I2C controller
From: Vasily Khoruzhick @ 2018-06-06 5:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180606051702.6478-1-anarsoul@gmail.com>
From: Icenowy Zheng <icenowy@aosc.io>
Allwinner A64 has a I2C controller, which is in the R_ MMIO zone and has
two groups of pinmuxes on PL bank, so it's called R_I2C.
Add support for this I2C controller and the pinmux which doesn't conflict
with RSB.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 24 +++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 1b2ef28c42bd..dcf957b2e7c8 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -46,6 +46,7 @@
#include <dt-bindings/clock/sun8i-r-ccu.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/sun50i-a64-ccu.h>
+#include <dt-bindings/reset/sun8i-r-ccu.h>
/ {
interrupt-parent = <&gic>;
@@ -655,6 +656,18 @@
#reset-cells = <1>;
};
+ r_i2c: i2c at 1f02400 {
+ compatible = "allwinner,sun50i-a64-i2c",
+ "allwinner,sun6i-a31-i2c";
+ reg = <0x01f02400 0x400>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&r_ccu CLK_APB0_I2C>;
+ resets = <&r_ccu RST_APB0_I2C>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
r_pio: pinctrl at 1f02c00 {
compatible = "allwinner,sun50i-a64-r-pinctrl";
reg = <0x01f02c00 0x400>;
@@ -666,6 +679,17 @@
interrupt-controller;
#interrupt-cells = <3>;
+
+ r_i2c_pins: i2c {
+ pins = "PL0", "PL1";
+ function = "s_i2c";
+ };
+
+ r_i2c_pins_a: i2c-a {
+ pins = "PL8", "PL9";
+ function = "s_i2c";
+ };
+
r_rsb_pins: rsb {
pins = "PL0", "PL1";
function = "s_rsb";
--
2.17.1
^ permalink raw reply related
* [PATCH v2 2/3] arm64: dts: allwinner: a64: Add PWM controllers
From: Vasily Khoruzhick @ 2018-06-06 5:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180606051702.6478-1-anarsoul@gmail.com>
From: Andre Przywara <andre.przywara@arm.com>
The Allwinner A64 SoC features two PWM controllers, which are fully
compatible to the one used in the A13 and H3 chips.
Add the nodes for the devices (one for the "normal" PWM, the other for
the one in the CPUS domain) and the pins their outputs are connected to.
On the A64 the "normal" PWM is muxed together with one of the MDIO pins
used to communicate with the Ethernet PHY, so it won't be usable on many
boards. But the Pinebook laptop uses this pin for controlling the LCD
backlight.
On Pine64 the CPUS PWM pin however is routed to the "RPi2" header,
at the same location as the PWM pin on the RaspberryPi.
Tested on Pinebook and Teres-I
[vasily: fixed comment message as requested by Stefan Bruens, added default
muxing options to pwm and r_pwm nodes]
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Tested-by: Harald Geyer <harald@ccbib.org>
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 32 +++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index dcf957b2e7c8..360bb1a4a504 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -365,6 +365,11 @@
bias-pull-up;
};
+ pwm_pin: pwm_pin {
+ pins = "PD22";
+ function = "pwm";
+ };
+
rmii_pins: rmii_pins {
pins = "PD10", "PD11", "PD13", "PD14", "PD17",
"PD18", "PD19", "PD20", "PD22", "PD23";
@@ -630,6 +635,17 @@
#interrupt-cells = <3>;
};
+ pwm: pwm at 1c21400 {
+ compatible = "allwinner,sun50i-a64-pwm",
+ "allwinner,sun5i-a13-pwm";
+ reg = <0x01c21400 0x400>;
+ clocks = <&osc24M>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_pin>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
rtc: rtc at 1f00000 {
compatible = "allwinner,sun6i-a31-rtc";
reg = <0x01f00000 0x54>;
@@ -668,6 +684,17 @@
#size-cells = <0>;
};
+ r_pwm: pwm at 1f03800 {
+ compatible = "allwinner,sun50i-a64-pwm",
+ "allwinner,sun5i-a13-pwm";
+ reg = <0x01f03800 0x400>;
+ clocks = <&osc24M>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_pwm_pin>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
r_pio: pinctrl at 1f02c00 {
compatible = "allwinner,sun50i-a64-r-pinctrl";
reg = <0x01f02c00 0x400>;
@@ -690,6 +717,11 @@
function = "s_i2c";
};
+ r_pwm_pin: pwm {
+ pins = "PL10";
+ function = "s_pwm";
+ };
+
r_rsb_pins: rsb {
pins = "PL0", "PL1";
function = "s_rsb";
--
2.17.1
^ permalink raw reply related
* [PATCH v2 3/3] arm64: dts: allwinner: add support for Pinebook
From: Vasily Khoruzhick @ 2018-06-06 5:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180606051702.6478-1-anarsoul@gmail.com>
From: Icenowy Zheng <icenowy@aosc.xyz>
Pinebook is a A64-based laptop produced by Pine64, with the following
peripherals:
USB:
- Two external USB ports (one is directly connected to A64's OTG
controller, the other is under a internal hub connected to the host-only
controller.)
- USB HID keyboard and touchpad connected to the internal hub.
- USB UVC camera connected to the internal hub.
Power-related:
- A DC IN jack connected to AXP803's DCIN pin.
- A Li-Polymer battery connected to AXP803's battery pins.
Storage:
- An eMMC by Foresee on the main board (in the product revision of the
main board it's designed to be switchable).
- An external MicroSD card slot.
Display:
- An eDP LCD panel (1366x768) connected via an ANX6345 RGB-eDP bridge.
- A mini HDMI port.
Misc:
- A Hall sensor designed to detect the status of lid, connected to GPIO PL12.
- A headphone jack connected to the SoC's internal codec.
- A debug UART port muxed with headphone jack.
This commit adds basical support for it.
[vasily: squashed several commits into one, added simplefb node, added usbphy
to ehci0 and ohci0 nodes and other cosmetic changes to dts]
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
---
arch/arm64/boot/dts/allwinner/Makefile | 1 +
.../dts/allwinner/sun50i-a64-pinebook.dts | 280 ++++++++++++++++++
2 files changed, 281 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
index 8bebe7da5ed9..a8c6d0c6f2c5 100644
--- a/arch/arm64/boot/dts/allwinner/Makefile
+++ b/arch/arm64/boot/dts/allwinner/Makefile
@@ -4,6 +4,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-nanopi-a64.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-orangepi-win.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinebook.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-teres-i.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-pc2.dtb
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
new file mode 100644
index 000000000000..58253d6f9be1
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
@@ -0,0 +1,280 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.xyz>
+ * Copyright (C) 2018 Vasily Khoruzhick <anarsoul@gmail.com>
+ *
+ */
+
+/dts-v1/;
+
+#include "sun50i-a64.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+ model = "Pinebook";
+ compatible = "pine64,pinebook", "allwinner,sun50i-a64";
+
+ aliases {
+ serial0 = &uart0;
+ ethernet0 = &rtl8723cs;
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm 0 50000 0>;
+ brightness-levels = <0 5 10 15 20 30 40 55 70 85 100>;
+ default-brightness-level = <2>;
+ enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+
+ framebuffer-lcd {
+ panel-supply = <®_dc1sw>;
+ dvdd25-supply = <®_dldo2>;
+ dvdd12-supply = <®_fldo1>;
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+
+ lid_switch {
+ label = "Lid Switch";
+ gpios = <&r_pio 0 12 GPIO_ACTIVE_LOW>; /* PL12 */
+ linux,input-type = <EV_SW>;
+ linux,code = <SW_LID>;
+ linux,can-disable;
+ };
+ };
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
+ };
+};
+
+&ehci0 {
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ vmmc-supply = <®_dcdc1>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+ disable-wp;
+ bus-width = <4>;
+ status = "okay";
+};
+
+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
+ vmmc-supply = <®_dldo4>;
+ vqmmc-supply = <®_eldo1>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ rtl8723cs: wifi at 1 {
+ reg = <1>;
+ };
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins>;
+ vmmc-supply = <®_dcdc1>;
+ vqmmc-supply = <®_eldo1>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ mmc-hs200-1_8v;
+ status = "okay";
+};
+
+&ohci0 {
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&pwm {
+ status = "okay";
+};
+
+&r_rsb {
+ status = "okay";
+
+ axp803: pmic at 3a3 {
+ compatible = "x-powers,axp803";
+ reg = <0x3a3>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ };
+};
+
+/* The ANX6345 eDP-bridge is on r_i2c */
+&r_i2c {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&r_i2c_pins_a>;
+ status = "okay";
+};
+
+#include "axp803.dtsi"
+
+®_aldo1 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-name = "vcc-csi";
+};
+
+®_aldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pl";
+};
+
+®_aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-pll-avcc";
+};
+
+®_dc1sw {
+ regulator-name = "vcc-lcd";
+};
+
+®_dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-3v3";
+};
+
+®_dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-name = "vdd-cpux";
+};
+
+/* DCDC3 is polyphased with DCDC2 */
+
+®_dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vcc-dram";
+};
+
+®_dcdc6 {
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-sys";
+};
+
+®_dldo1 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-hdmi";
+};
+
+®_dldo2 {
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-name = "vcc-edp";
+};
+
+®_dldo3 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "avdd-csi";
+};
+
+®_dldo4 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi";
+};
+
+®_eldo1 {
+ regulator-always-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "cpvdd";
+};
+
+®_eldo3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vdd-1v8-csi";
+};
+
+®_fldo1 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vcc-1v2-hsic";
+};
+
+®_fldo2 {
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-cpus";
+};
+
+®_ldo_io0 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-usb";
+ status = "okay";
+};
+
+®_rtc_ldo {
+ regulator-name = "vcc-rtc";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "host";
+};
+
+&usbphy {
+ usb0_vbus-supply = <®_ldo_io0>;
+ usb1_vbus-supply = <®_ldo_io0>;
+ status = "okay";
+};
--
2.17.1
^ permalink raw reply related
* [PATCH v2 3/3] arm64: dts: allwinner: add support for Pinebook
From: Icenowy Zheng @ 2018-06-06 5:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180606051702.6478-4-anarsoul@gmail.com>
? 2018?6?6? GMT+08:00 ??1:17:02, Vasily Khoruzhick <anarsoul@gmail.com> ??:
>From: Icenowy Zheng <icenowy@aosc.xyz>
Could you change all the mail address to @aosc.io ?
>
>Pinebook is a A64-based laptop produced by Pine64, with the following
>peripherals:
>
>USB:
>- Two external USB ports (one is directly connected to A64's OTG
>controller, the other is under a internal hub connected to the
>host-only
>controller.)
>- USB HID keyboard and touchpad connected to the internal hub.
>- USB UVC camera connected to the internal hub.
>
>Power-related:
>- A DC IN jack connected to AXP803's DCIN pin.
>- A Li-Polymer battery connected to AXP803's battery pins.
>
>Storage:
>- An eMMC by Foresee on the main board (in the product revision of the
>main board it's designed to be switchable).
>- An external MicroSD card slot.
>
>Display:
>- An eDP LCD panel (1366x768) connected via an ANX6345 RGB-eDP bridge.
>- A mini HDMI port.
>
>Misc:
>- A Hall sensor designed to detect the status of lid, connected to GPIO
>PL12.
>- A headphone jack connected to the SoC's internal codec.
>- A debug UART port muxed with headphone jack.
>
>This commit adds basical support for it.
>
>[vasily: squashed several commits into one, added simplefb node, added
>usbphy
> to ehci0 and ohci0 nodes and other cosmetic changes to dts]
>
>Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
>Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
>---
> arch/arm64/boot/dts/allwinner/Makefile | 1 +
> .../dts/allwinner/sun50i-a64-pinebook.dts | 280 ++++++++++++++++++
> 2 files changed, 281 insertions(+)
>create mode 100644
>arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
>
>diff --git a/arch/arm64/boot/dts/allwinner/Makefile
>b/arch/arm64/boot/dts/allwinner/Makefile
>index 8bebe7da5ed9..a8c6d0c6f2c5 100644
>--- a/arch/arm64/boot/dts/allwinner/Makefile
>+++ b/arch/arm64/boot/dts/allwinner/Makefile
>@@ -4,6 +4,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-nanopi-a64.dtb
> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino.dtb
> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-orangepi-win.dtb
>dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb
>sun50i-a64-pine64.dtb
>+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinebook.dtb
> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb
> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-teres-i.dtb
> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-pc2.dtb
>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
>b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
>new file mode 100644
>index 000000000000..58253d6f9be1
>--- /dev/null
>+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
>@@ -0,0 +1,280 @@
>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>+/*
>+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.xyz>
>+ * Copyright (C) 2018 Vasily Khoruzhick <anarsoul@gmail.com>
>+ *
>+ */
>+
>+/dts-v1/;
>+
>+#include "sun50i-a64.dtsi"
>+
>+#include <dt-bindings/gpio/gpio.h>
>+#include <dt-bindings/input/input.h>
>+#include <dt-bindings/pwm/pwm.h>
>+
>+/ {
>+ model = "Pinebook";
>+ compatible = "pine64,pinebook", "allwinner,sun50i-a64";
>+
>+ aliases {
>+ serial0 = &uart0;
>+ ethernet0 = &rtl8723cs;
>+ };
>+
>+ backlight: backlight {
>+ compatible = "pwm-backlight";
>+ pwms = <&pwm 0 50000 0>;
>+ brightness-levels = <0 5 10 15 20 30 40 55 70 85 100>;
>+ default-brightness-level = <2>;
>+ enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */
>+ };
>+
>+ chosen {
>+ stdout-path = "serial0:115200n8";
>+
>+ framebuffer-lcd {
>+ panel-supply = <®_dc1sw>;
>+ dvdd25-supply = <®_dldo2>;
>+ dvdd12-supply = <®_fldo1>;
>+ };
>+ };
>+
>+ gpio_keys {
>+ compatible = "gpio-keys";
>+
>+ lid_switch {
>+ label = "Lid Switch";
>+ gpios = <&r_pio 0 12 GPIO_ACTIVE_LOW>; /* PL12 */
>+ linux,input-type = <EV_SW>;
>+ linux,code = <SW_LID>;
>+ linux,can-disable;
>+ };
>+ };
>+
>+ reg_vcc3v3: vcc3v3 {
>+ compatible = "regulator-fixed";
>+ regulator-name = "vcc3v3";
>+ regulator-min-microvolt = <3300000>;
>+ regulator-max-microvolt = <3300000>;
>+ };
>+
>+ wifi_pwrseq: wifi_pwrseq {
>+ compatible = "mmc-pwrseq-simple";
>+ reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
>+ };
>+};
>+
>+&ehci0 {
>+ phys = <&usbphy 0>;
>+ phy-names = "usb";
>+ status = "okay";
>+};
>+
>+&ehci1 {
>+ status = "okay";
>+};
>+
>+&mmc0 {
>+ pinctrl-names = "default";
>+ pinctrl-0 = <&mmc0_pins>;
>+ vmmc-supply = <®_dcdc1>;
>+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
>+ cd-inverted;
>+ disable-wp;
>+ bus-width = <4>;
>+ status = "okay";
>+};
>+
>+&mmc1 {
>+ pinctrl-names = "default";
>+ pinctrl-0 = <&mmc1_pins>;
>+ vmmc-supply = <®_dldo4>;
>+ vqmmc-supply = <®_eldo1>;
>+ mmc-pwrseq = <&wifi_pwrseq>;
>+ bus-width = <4>;
>+ non-removable;
>+ status = "okay";
>+
>+ rtl8723cs: wifi at 1 {
>+ reg = <1>;
>+ };
>+};
>+
>+&mmc2 {
>+ pinctrl-names = "default";
>+ pinctrl-0 = <&mmc2_pins>;
>+ vmmc-supply = <®_dcdc1>;
>+ vqmmc-supply = <®_eldo1>;
>+ bus-width = <8>;
>+ non-removable;
>+ cap-mmc-hw-reset;
>+ mmc-hs200-1_8v;
>+ status = "okay";
>+};
>+
>+&ohci0 {
>+ phys = <&usbphy 0>;
>+ phy-names = "usb";
>+ status = "okay";
>+};
>+
>+&ohci1 {
>+ status = "okay";
>+};
>+
>+&pwm {
>+ status = "okay";
>+};
>+
>+&r_rsb {
>+ status = "okay";
>+
>+ axp803: pmic at 3a3 {
>+ compatible = "x-powers,axp803";
>+ reg = <0x3a3>;
>+ interrupt-parent = <&r_intc>;
>+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
>+ };
>+};
>+
>+/* The ANX6345 eDP-bridge is on r_i2c */
>+&r_i2c {
>+ clock-frequency = <100000>;
>+ pinctrl-names = "default";
>+ pinctrl-0 = <&r_i2c_pins_a>;
>+ status = "okay";
>+};
>+
>+#include "axp803.dtsi"
>+
>+®_aldo1 {
>+ regulator-min-microvolt = <2800000>;
>+ regulator-max-microvolt = <2800000>;
>+ regulator-name = "vcc-csi";
>+};
>+
>+®_aldo2 {
>+ regulator-always-on;
>+ regulator-min-microvolt = <1800000>;
>+ regulator-max-microvolt = <3300000>;
>+ regulator-name = "vcc-pl";
>+};
>+
>+®_aldo3 {
>+ regulator-always-on;
>+ regulator-min-microvolt = <2700000>;
>+ regulator-max-microvolt = <3300000>;
>+ regulator-name = "vcc-pll-avcc";
>+};
>+
>+®_dc1sw {
>+ regulator-name = "vcc-lcd";
>+};
>+
>+®_dcdc1 {
>+ regulator-always-on;
>+ regulator-min-microvolt = <3300000>;
>+ regulator-max-microvolt = <3300000>;
>+ regulator-name = "vcc-3v3";
>+};
>+
>+®_dcdc2 {
>+ regulator-always-on;
>+ regulator-min-microvolt = <1000000>;
>+ regulator-max-microvolt = <1300000>;
>+ regulator-name = "vdd-cpux";
>+};
>+
>+/* DCDC3 is polyphased with DCDC2 */
>+
>+®_dcdc5 {
>+ regulator-always-on;
>+ regulator-min-microvolt = <1200000>;
>+ regulator-max-microvolt = <1200000>;
>+ regulator-name = "vcc-dram";
>+};
>+
>+®_dcdc6 {
>+ regulator-always-on;
>+ regulator-min-microvolt = <1100000>;
>+ regulator-max-microvolt = <1100000>;
>+ regulator-name = "vdd-sys";
>+};
>+
>+®_dldo1 {
>+ regulator-min-microvolt = <3300000>;
>+ regulator-max-microvolt = <3300000>;
>+ regulator-name = "vcc-hdmi";
>+};
>+
>+®_dldo2 {
>+ regulator-min-microvolt = <2500000>;
>+ regulator-max-microvolt = <2500000>;
>+ regulator-name = "vcc-edp";
>+};
>+
>+®_dldo3 {
>+ regulator-min-microvolt = <3300000>;
>+ regulator-max-microvolt = <3300000>;
>+ regulator-name = "avdd-csi";
>+};
>+
>+®_dldo4 {
>+ regulator-min-microvolt = <3300000>;
>+ regulator-max-microvolt = <3300000>;
>+ regulator-name = "vcc-wifi";
>+};
>+
>+®_eldo1 {
>+ regulator-always-on;
>+ regulator-min-microvolt = <1800000>;
>+ regulator-max-microvolt = <1800000>;
>+ regulator-name = "cpvdd";
>+};
>+
>+®_eldo3 {
>+ regulator-min-microvolt = <1800000>;
>+ regulator-max-microvolt = <1800000>;
>+ regulator-name = "vdd-1v8-csi";
>+};
>+
>+®_fldo1 {
>+ regulator-min-microvolt = <1200000>;
>+ regulator-max-microvolt = <1200000>;
>+ regulator-name = "vcc-1v2-hsic";
>+};
>+
>+®_fldo2 {
>+ regulator-always-on;
>+ regulator-min-microvolt = <1100000>;
>+ regulator-max-microvolt = <1100000>;
>+ regulator-name = "vdd-cpus";
>+};
>+
>+®_ldo_io0 {
>+ regulator-min-microvolt = <3300000>;
>+ regulator-max-microvolt = <3300000>;
>+ regulator-name = "vcc-usb";
>+ status = "okay";
>+};
>+
>+®_rtc_ldo {
>+ regulator-name = "vcc-rtc";
>+};
>+
>+&uart0 {
>+ pinctrl-names = "default";
>+ pinctrl-0 = <&uart0_pins_a>;
>+ status = "okay";
>+};
>+
>+&usb_otg {
>+ dr_mode = "host";
>+};
>+
>+&usbphy {
>+ usb0_vbus-supply = <®_ldo_io0>;
>+ usb1_vbus-supply = <®_ldo_io0>;
>+ status = "okay";
>+};
^ permalink raw reply
* [PATCH v2 3/3] arm64: dts: allwinner: add support for Pinebook
From: Vasily Khoruzhick @ 2018-06-06 5:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <6FB4B99D-5A98-4E6F-B7F5-09063DAAF4A2@aosc.io>
OK, will do.
On Tue, Jun 5, 2018 at 10:20 PM, Icenowy Zheng <icenowy@aosc.io> wrote:
>
>
> ? 2018?6?6? GMT+08:00 ??1:17:02, Vasily Khoruzhick <anarsoul@gmail.com> ??:
>>From: Icenowy Zheng <icenowy@aosc.xyz>
>
> Could you change all the mail address to @aosc.io ?
>
>>
>>Pinebook is a A64-based laptop produced by Pine64, with the following
>>peripherals:
>>
>>USB:
>>- Two external USB ports (one is directly connected to A64's OTG
>>controller, the other is under a internal hub connected to the
>>host-only
>>controller.)
>>- USB HID keyboard and touchpad connected to the internal hub.
>>- USB UVC camera connected to the internal hub.
>>
>>Power-related:
>>- A DC IN jack connected to AXP803's DCIN pin.
>>- A Li-Polymer battery connected to AXP803's battery pins.
>>
>>Storage:
>>- An eMMC by Foresee on the main board (in the product revision of the
>>main board it's designed to be switchable).
>>- An external MicroSD card slot.
>>
>>Display:
>>- An eDP LCD panel (1366x768) connected via an ANX6345 RGB-eDP bridge.
>>- A mini HDMI port.
>>
>>Misc:
>>- A Hall sensor designed to detect the status of lid, connected to GPIO
>>PL12.
>>- A headphone jack connected to the SoC's internal codec.
>>- A debug UART port muxed with headphone jack.
>>
>>This commit adds basical support for it.
>>
>>[vasily: squashed several commits into one, added simplefb node, added
>>usbphy
>> to ehci0 and ohci0 nodes and other cosmetic changes to dts]
>>
>>Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
>>Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
>>---
>> arch/arm64/boot/dts/allwinner/Makefile | 1 +
>> .../dts/allwinner/sun50i-a64-pinebook.dts | 280 ++++++++++++++++++
>> 2 files changed, 281 insertions(+)
>>create mode 100644
>>arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
>>
>>diff --git a/arch/arm64/boot/dts/allwinner/Makefile
>>b/arch/arm64/boot/dts/allwinner/Makefile
>>index 8bebe7da5ed9..a8c6d0c6f2c5 100644
>>--- a/arch/arm64/boot/dts/allwinner/Makefile
>>+++ b/arch/arm64/boot/dts/allwinner/Makefile
>>@@ -4,6 +4,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-nanopi-a64.dtb
>> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino.dtb
>> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-orangepi-win.dtb
>>dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb
>>sun50i-a64-pine64.dtb
>>+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinebook.dtb
>> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb
>> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-teres-i.dtb
>> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-pc2.dtb
>>diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
>>b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
>>new file mode 100644
>>index 000000000000..58253d6f9be1
>>--- /dev/null
>>+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinebook.dts
>>@@ -0,0 +1,280 @@
>>+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>>+/*
>>+ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.xyz>
>>+ * Copyright (C) 2018 Vasily Khoruzhick <anarsoul@gmail.com>
>>+ *
>>+ */
>>+
>>+/dts-v1/;
>>+
>>+#include "sun50i-a64.dtsi"
>>+
>>+#include <dt-bindings/gpio/gpio.h>
>>+#include <dt-bindings/input/input.h>
>>+#include <dt-bindings/pwm/pwm.h>
>>+
>>+/ {
>>+ model = "Pinebook";
>>+ compatible = "pine64,pinebook", "allwinner,sun50i-a64";
>>+
>>+ aliases {
>>+ serial0 = &uart0;
>>+ ethernet0 = &rtl8723cs;
>>+ };
>>+
>>+ backlight: backlight {
>>+ compatible = "pwm-backlight";
>>+ pwms = <&pwm 0 50000 0>;
>>+ brightness-levels = <0 5 10 15 20 30 40 55 70 85 100>;
>>+ default-brightness-level = <2>;
>>+ enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */
>>+ };
>>+
>>+ chosen {
>>+ stdout-path = "serial0:115200n8";
>>+
>>+ framebuffer-lcd {
>>+ panel-supply = <®_dc1sw>;
>>+ dvdd25-supply = <®_dldo2>;
>>+ dvdd12-supply = <®_fldo1>;
>>+ };
>>+ };
>>+
>>+ gpio_keys {
>>+ compatible = "gpio-keys";
>>+
>>+ lid_switch {
>>+ label = "Lid Switch";
>>+ gpios = <&r_pio 0 12 GPIO_ACTIVE_LOW>; /* PL12 */
>>+ linux,input-type = <EV_SW>;
>>+ linux,code = <SW_LID>;
>>+ linux,can-disable;
>>+ };
>>+ };
>>+
>>+ reg_vcc3v3: vcc3v3 {
>>+ compatible = "regulator-fixed";
>>+ regulator-name = "vcc3v3";
>>+ regulator-min-microvolt = <3300000>;
>>+ regulator-max-microvolt = <3300000>;
>>+ };
>>+
>>+ wifi_pwrseq: wifi_pwrseq {
>>+ compatible = "mmc-pwrseq-simple";
>>+ reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
>>+ };
>>+};
>>+
>>+&ehci0 {
>>+ phys = <&usbphy 0>;
>>+ phy-names = "usb";
>>+ status = "okay";
>>+};
>>+
>>+&ehci1 {
>>+ status = "okay";
>>+};
>>+
>>+&mmc0 {
>>+ pinctrl-names = "default";
>>+ pinctrl-0 = <&mmc0_pins>;
>>+ vmmc-supply = <®_dcdc1>;
>>+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
>>+ cd-inverted;
>>+ disable-wp;
>>+ bus-width = <4>;
>>+ status = "okay";
>>+};
>>+
>>+&mmc1 {
>>+ pinctrl-names = "default";
>>+ pinctrl-0 = <&mmc1_pins>;
>>+ vmmc-supply = <®_dldo4>;
>>+ vqmmc-supply = <®_eldo1>;
>>+ mmc-pwrseq = <&wifi_pwrseq>;
>>+ bus-width = <4>;
>>+ non-removable;
>>+ status = "okay";
>>+
>>+ rtl8723cs: wifi at 1 {
>>+ reg = <1>;
>>+ };
>>+};
>>+
>>+&mmc2 {
>>+ pinctrl-names = "default";
>>+ pinctrl-0 = <&mmc2_pins>;
>>+ vmmc-supply = <®_dcdc1>;
>>+ vqmmc-supply = <®_eldo1>;
>>+ bus-width = <8>;
>>+ non-removable;
>>+ cap-mmc-hw-reset;
>>+ mmc-hs200-1_8v;
>>+ status = "okay";
>>+};
>>+
>>+&ohci0 {
>>+ phys = <&usbphy 0>;
>>+ phy-names = "usb";
>>+ status = "okay";
>>+};
>>+
>>+&ohci1 {
>>+ status = "okay";
>>+};
>>+
>>+&pwm {
>>+ status = "okay";
>>+};
>>+
>>+&r_rsb {
>>+ status = "okay";
>>+
>>+ axp803: pmic at 3a3 {
>>+ compatible = "x-powers,axp803";
>>+ reg = <0x3a3>;
>>+ interrupt-parent = <&r_intc>;
>>+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
>>+ };
>>+};
>>+
>>+/* The ANX6345 eDP-bridge is on r_i2c */
>>+&r_i2c {
>>+ clock-frequency = <100000>;
>>+ pinctrl-names = "default";
>>+ pinctrl-0 = <&r_i2c_pins_a>;
>>+ status = "okay";
>>+};
>>+
>>+#include "axp803.dtsi"
>>+
>>+®_aldo1 {
>>+ regulator-min-microvolt = <2800000>;
>>+ regulator-max-microvolt = <2800000>;
>>+ regulator-name = "vcc-csi";
>>+};
>>+
>>+®_aldo2 {
>>+ regulator-always-on;
>>+ regulator-min-microvolt = <1800000>;
>>+ regulator-max-microvolt = <3300000>;
>>+ regulator-name = "vcc-pl";
>>+};
>>+
>>+®_aldo3 {
>>+ regulator-always-on;
>>+ regulator-min-microvolt = <2700000>;
>>+ regulator-max-microvolt = <3300000>;
>>+ regulator-name = "vcc-pll-avcc";
>>+};
>>+
>>+®_dc1sw {
>>+ regulator-name = "vcc-lcd";
>>+};
>>+
>>+®_dcdc1 {
>>+ regulator-always-on;
>>+ regulator-min-microvolt = <3300000>;
>>+ regulator-max-microvolt = <3300000>;
>>+ regulator-name = "vcc-3v3";
>>+};
>>+
>>+®_dcdc2 {
>>+ regulator-always-on;
>>+ regulator-min-microvolt = <1000000>;
>>+ regulator-max-microvolt = <1300000>;
>>+ regulator-name = "vdd-cpux";
>>+};
>>+
>>+/* DCDC3 is polyphased with DCDC2 */
>>+
>>+®_dcdc5 {
>>+ regulator-always-on;
>>+ regulator-min-microvolt = <1200000>;
>>+ regulator-max-microvolt = <1200000>;
>>+ regulator-name = "vcc-dram";
>>+};
>>+
>>+®_dcdc6 {
>>+ regulator-always-on;
>>+ regulator-min-microvolt = <1100000>;
>>+ regulator-max-microvolt = <1100000>;
>>+ regulator-name = "vdd-sys";
>>+};
>>+
>>+®_dldo1 {
>>+ regulator-min-microvolt = <3300000>;
>>+ regulator-max-microvolt = <3300000>;
>>+ regulator-name = "vcc-hdmi";
>>+};
>>+
>>+®_dldo2 {
>>+ regulator-min-microvolt = <2500000>;
>>+ regulator-max-microvolt = <2500000>;
>>+ regulator-name = "vcc-edp";
>>+};
>>+
>>+®_dldo3 {
>>+ regulator-min-microvolt = <3300000>;
>>+ regulator-max-microvolt = <3300000>;
>>+ regulator-name = "avdd-csi";
>>+};
>>+
>>+®_dldo4 {
>>+ regulator-min-microvolt = <3300000>;
>>+ regulator-max-microvolt = <3300000>;
>>+ regulator-name = "vcc-wifi";
>>+};
>>+
>>+®_eldo1 {
>>+ regulator-always-on;
>>+ regulator-min-microvolt = <1800000>;
>>+ regulator-max-microvolt = <1800000>;
>>+ regulator-name = "cpvdd";
>>+};
>>+
>>+®_eldo3 {
>>+ regulator-min-microvolt = <1800000>;
>>+ regulator-max-microvolt = <1800000>;
>>+ regulator-name = "vdd-1v8-csi";
>>+};
>>+
>>+®_fldo1 {
>>+ regulator-min-microvolt = <1200000>;
>>+ regulator-max-microvolt = <1200000>;
>>+ regulator-name = "vcc-1v2-hsic";
>>+};
>>+
>>+®_fldo2 {
>>+ regulator-always-on;
>>+ regulator-min-microvolt = <1100000>;
>>+ regulator-max-microvolt = <1100000>;
>>+ regulator-name = "vdd-cpus";
>>+};
>>+
>>+®_ldo_io0 {
>>+ regulator-min-microvolt = <3300000>;
>>+ regulator-max-microvolt = <3300000>;
>>+ regulator-name = "vcc-usb";
>>+ status = "okay";
>>+};
>>+
>>+®_rtc_ldo {
>>+ regulator-name = "vcc-rtc";
>>+};
>>+
>>+&uart0 {
>>+ pinctrl-names = "default";
>>+ pinctrl-0 = <&uart0_pins_a>;
>>+ status = "okay";
>>+};
>>+
>>+&usb_otg {
>>+ dr_mode = "host";
>>+};
>>+
>>+&usbphy {
>>+ usb0_vbus-supply = <®_ldo_io0>;
>>+ usb1_vbus-supply = <®_ldo_io0>;
>>+ status = "okay";
>>+};
^ permalink raw reply
* panic kexec broken on ARM64?
From: Bhupesh Sharma @ 2018-06-06 5:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180605100151.7fd54381@ezekiel.suse.cz>
Hello Petr,
On Tue, Jun 5, 2018 at 1:31 PM, Petr Tesarik <ptesarik@suse.cz> wrote:
> Hi all,
>
> I have observed hangs after crash on a Raspberry Pi 3 Model B+ board
> when a panic kernel is loaded. I attached a hardware debugger and found
> out that all CPU cores were stopped except one which was stuck in the
> idle thread. It seems that irq_set_irqchip_state() may sleep, which is
> definitely not safe after a kernel panic.
Normally we limit the number of cpus in the crash kernel to 1 (via
maxcpus=1) in distributions like fedora. Can you please share the
command-line/bootargs which you use to invoke the crash kernel.
Also do you get any console output from the crash kernel (you can try
passing earlycon to the crash kernel to see if it crashes early
enough)? If yes, can you please share the same.
> If I'm right, then this is broken in general, but I have only ever seen
> it on RPi 3 Model B+ (even RPi3 Model B works fine), so the issue may
> be more subtle. FWIW the code for 32-bit ARM seems to work just fine
> without this code in machine_kexec_mask_interrupts():
>
> /*
> * First try to remove the active state. If this
> * fails, try to EOI the interrupt.
> */
> ret = irq_set_irqchip_state(i, IRQCHIP_STATE_ACTIVE, false);
>
> I wonder what breaks if this call to irq_set_irqchip_state() is removed.
>
> For reference, here is a stack trace of the process which originally
> triggered the panic:
>
> #0 __switch_to (prev=0xffff000008e62a00 <init_task>, next=0xffff80002b796080) at ../arch/arm64/kernel/process.c:355
> #1 0xffff0000088f584c in context_switch (rf=<optimized out>, next=<optimized out>, prev=<optimized out>, rq=<optimized out>) at ../kernel/sched/core.c:2896
> #2 __schedule (preempt=false) at ../kernel/sched/core.c:3457
> #3 0xffff0000088f5eac in schedule () at ../kernel/sched/core.c:3516
> #4 0xffff0000088f9448 in schedule_timeout (timeout=<optimized out>) at ../kernel/time/timer.c:1743
> #5 0xffff0000088f6afc in do_wait_for_common (state=<optimized out>, timeout=500, action=<optimized out>, x=<optimized out>) at ../kernel/sched/completion.c:77
> #6 __wait_for_common (state=<optimized out>, timeout=<optimized out>, action=<optimized out>, x=<optimized out>) at ../kernel/sched/completion.c:96
> #7 wait_for_common (x=0xffff000008e53848 <init_thread_union+14408>, timeout=500, state=<optimized out>) at ../kernel/sched/completion.c:104
> #8 0xffff0000088f6c1c in wait_for_completion_timeout (x=0xffff000008e53848 <init_thread_union+14408>, timeout=500) at ../kernel/sched/completion.c:144
> #9 0xffff000000a19f1c in usb_start_wait_urb (urb=0xffff80002c1cd700, timeout=5000, actual_length=0xffff000008e538dc <init_thread_union+14556>)
> at ../drivers/usb/core/message.c:61
> #10 0xffff000000a1a05c in usb_internal_control_msg (timeout=<optimized out>, len=<optimized out>, data=<optimized out>, cmd=<optimized out>, pipe=<optimized out>,
> usb_dev=<optimized out>) at ../drivers/usb/core/message.c:100
> #11 usb_control_msg (dev=0xffff80002c348000, pipe=2147484800, request=161 '\241', requesttype=192 '\300', value=0, index=152, data=0xffff80002b6fa080, size=4,
> timeout=5000) at ../drivers/usb/core/message.c:151
> #12 0xffff000001001cd0 in lan78xx_read_reg (index=152, data=0xffff000008e5396c <init_thread_union+14700>, dev=<optimized out>, dev=<optimized out>)
> at ../drivers/net/usb/lan78xx.c:425
Hmmm, this seems a bit misplaced, but are you using a usb-ethernet
adapter which causes a URB submission to timeout?
> #13 0xffff00000100365c in lan78xx_irq_bus_sync_unlock (irqd=<optimized out>) at ../drivers/net/usb/lan78xx.c:1909
> #14 0xffff00000813e590 in chip_bus_sync_unlock (desc=<optimized out>) at ../kernel/irq/internals.h:129
> #15 __irq_put_desc_unlock (desc=0xffff80002c361c00, flags=128, bus=true) at ../kernel/irq/irqdesc.c:804
> #16 0xffff00000813f604 in irq_put_desc_busunlock (flags=<optimized out>, desc=<optimized out>) at ../kernel/irq/internals.h:155
> #17 irq_set_irqchip_state (irq=<optimized out>, which=<optimized out>, val=false) at ../kernel/irq/manage.c:2136
> #18 0xffff00000809b7d4 in machine_kexec_mask_interrupts () at ../arch/arm64/kernel/machine_kexec.c:233
> #19 machine_crash_shutdown (regs=<optimized out>) at ../arch/arm64/kernel/machine_kexec.c:259
> #20 0xffff000008180fd4 in __crash_kexec (regs=0xffff000008e53d70 <init_thread_union+15728>) at ../kernel/kexec_core.c:943
> #21 0xffff0000081810e4 in crash_kexec (regs=0xffff000008e53d70 <init_thread_union+15728>) at ../kernel/kexec_core.c:965
> #22 0xffff00000808ab58 in die (str=<optimized out>, regs=0xffff000008e53d70 <init_thread_union+15728>, err=-2046820348) at ../arch/arm64/kernel/traps.c:266
> #23 0xffff0000080a1c14 in __do_kernel_fault (mm=0x0, addr=0, esr=2248146948, regs=0xffff000008e53d70 <init_thread_union+15728>) at ../arch/arm64/mm/fault.c:226
> #24 0xffff0000088fc8dc in do_page_fault (addr=0, esr=2248146948, regs=0xffff000008e53d70 <init_thread_union+15728>) at ../arch/arm64/mm/fault.c:476
> #25 0xffff0000088fccdc in do_translation_fault (addr=0, esr=2248146948, regs=0xffff000008e53d70 <init_thread_union+15728>) at ../arch/arm64/mm/fault.c:502
> #26 0xffff000008081478 in do_mem_abort (addr=0, esr=2248146948, regs=0xffff000008e53d70 <init_thread_union+15728>) at ../arch/arm64/mm/fault.c:657
> #27 0xffff000008082dd0 in el1_sync () at ../arch/arm64/kernel/entry.S:548
The ESR value from the logs (2248146948) indicates the following about
the panic causes (see ARMv8 Architecture Reference Manual for more
details):
EC -> 100001, Instruction Abort taken without a change in Exception
level (Used for MMU faults generated by instruction accesses and
Synchronous external aborts, including synchronous parity or ECC
errors. Not used for debug related exceptions.)
FnV -> 0, FAR is valid
IFSC -> 000100, Translation fault, level 0
So in brief an Instruction Abort was taken at exception level EL1(?)
which was caused by a translation fault at level 0 and the FAR
register holds the faulting Virtual Address.
So, since you have the hardware debugger, can you try and see the
values of FAR (Fault Address Register) and ELR registers at this point
via the debugger and see if they can indicate the Faulty Address from
which the exception was taken and debug using the same.
If you can share the earlycon messages from the crashkernel and the
values of the above registers, can help you further with debugging the
issue which you are seeing.
Thanks,
Bhupesh
^ permalink raw reply
* [PATCH v3 0/6] Add MCAN Support for dra76x
From: Faiz Abbas @ 2018-06-06 6:08 UTC (permalink / raw)
To: linux-arm-kernel
The following patches add dts and sysconfig support
for MCAN on TI's dra76 SOCs
The patches depend on the following series:
https://patchwork.kernel.org/patch/10221105/
Changes in v3:
1. Added reset functionality to the ti-sysc
driver. This enables me to drop the hwmod
data patch as everything is being done in dt.
2. Dropped ti,hwmods from the dts nodes
3. Fixed the unit address of target-module
and mcan
4. Removed the status="disabled" in dtsi
followed by status="okay" in dts.
Changes in v2:
1. Added Support for mcan in the ti-sysc driver
Also added the target-module node for the same
2. Added clkctrl data for mcan clocks
Faiz Abbas (4):
clk: ti: dra7: Add clkctrl clock data for the mcan clocks
bus: ti-sysc: Add support for using ti-sysc for MCAN on dra76x
bus: ti-sysc: Add support for software reset
ARM: dts: Add generic interconnect target module node for MCAN
Franklin S Cooper Jr (1):
ARM: dts: dra76x: Add MCAN node
Lokesh Vutla (1):
ARM: dts: dra762: Add MCAN clock support
.../devicetree/bindings/bus/ti-sysc.txt | 1 +
arch/arm/boot/dts/dra76-evm.dts | 6 ++
arch/arm/boot/dts/dra76x.dtsi | 65 +++++++++++++++++++
drivers/bus/ti-sysc.c | 58 +++++++++++++++++
drivers/clk/ti/clk-7xx.c | 1 +
include/dt-bindings/bus/ti-sysc.h | 2 +
include/dt-bindings/clock/dra7.h | 1 +
include/linux/platform_data/ti-sysc.h | 1 +
8 files changed, 135 insertions(+)
--
2.17.0
^ permalink raw reply
* [PATCH v3 1/6] ARM: dts: dra762: Add MCAN clock support
From: Faiz Abbas @ 2018-06-06 6:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180606060826.14671-1-faiz_abbas@ti.com>
From: Lokesh Vutla <lokeshvutla@ti.com>
MCAN is clocked by H14 divider of DPLL_GMAC. Unlike other
DPLL dividers this DPLL_GMAC H14 divider is controlled by
control module. Adding support for these clocks.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
---
arch/arm/boot/dts/dra76x.dtsi | 33 +++++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/arch/arm/boot/dts/dra76x.dtsi b/arch/arm/boot/dts/dra76x.dtsi
index 1c88c581ff18..bfc82636999c 100644
--- a/arch/arm/boot/dts/dra76x.dtsi
+++ b/arch/arm/boot/dts/dra76x.dtsi
@@ -17,3 +17,36 @@
&crossbar_mpu {
ti,irqs-skip = <10 67 68 133 139 140>;
};
+
+&scm_conf_clocks {
+ dpll_gmac_h14x2_ctrl_ck: dpll_gmac_h14x2_ctrl_ck at 3fc {
+ #clock-cells = <0>;
+ compatible = "ti,divider-clock";
+ clocks = <&dpll_gmac_x2_ck>;
+ ti,max-div = <63>;
+ reg = <0x03fc>;
+ ti,bit-shift=<20>;
+ ti,latch-bit=<26>;
+ assigned-clocks = <&dpll_gmac_h14x2_ctrl_ck>;
+ assigned-clock-rates = <80000000>;
+ };
+
+ dpll_gmac_h14x2_ctrl_mux_ck: dpll_gmac_h14x2_ctrl_mux_ck at 3fc {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&dpll_gmac_ck>, <&dpll_gmac_h14x2_ctrl_ck>;
+ reg = <0x3fc>;
+ ti,bit-shift = <29>;
+ ti,latch-bit=<26>;
+ assigned-clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>;
+ assigned-clock-parents = <&dpll_gmac_h14x2_ctrl_ck>;
+ };
+
+ mcan_clk: mcan_clk at 3fc {
+ #clock-cells = <0>;
+ compatible = "ti,gate-clock";
+ clocks = <&dpll_gmac_h14x2_ctrl_mux_ck>;
+ ti,bit-shift = <27>;
+ reg = <0x3fc>;
+ };
+};
--
2.17.0
^ permalink raw reply related
* [PATCH v3 2/6] clk: ti: dra7: Add clkctrl clock data for the mcan clocks
From: Faiz Abbas @ 2018-06-06 6:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180606060826.14671-1-faiz_abbas@ti.com>
Add clkctrl data for the m_can clocks and register it within the
clkctrl driver
CC: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
---
drivers/clk/ti/clk-7xx.c | 1 +
include/dt-bindings/clock/dra7.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/clk/ti/clk-7xx.c b/drivers/clk/ti/clk-7xx.c
index fb249a1637a5..71a122b2dc67 100644
--- a/drivers/clk/ti/clk-7xx.c
+++ b/drivers/clk/ti/clk-7xx.c
@@ -708,6 +708,7 @@ static const struct omap_clkctrl_reg_data dra7_wkupaon_clkctrl_regs[] __initcons
{ DRA7_COUNTER_32K_CLKCTRL, NULL, 0, "wkupaon_iclk_mux" },
{ DRA7_UART10_CLKCTRL, dra7_uart10_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0060:24" },
{ DRA7_DCAN1_CLKCTRL, dra7_dcan1_bit_data, CLKF_SW_SUP, "wkupaon_cm:clk:0068:24" },
+ { DRA7_ADC_CLKCTRL, NULL, CLKF_SW_SUP, "mcan_clk"},
{ 0 },
};
diff --git a/include/dt-bindings/clock/dra7.h b/include/dt-bindings/clock/dra7.h
index 5e1061b15aed..d7549c57cac3 100644
--- a/include/dt-bindings/clock/dra7.h
+++ b/include/dt-bindings/clock/dra7.h
@@ -168,5 +168,6 @@
#define DRA7_COUNTER_32K_CLKCTRL DRA7_CLKCTRL_INDEX(0x50)
#define DRA7_UART10_CLKCTRL DRA7_CLKCTRL_INDEX(0x80)
#define DRA7_DCAN1_CLKCTRL DRA7_CLKCTRL_INDEX(0x88)
+#define DRA7_ADC_CLKCTRL DRA7_CLKCTRL_INDEX(0xa0)
#endif
--
2.17.0
^ permalink raw reply related
* [PATCH v3 3/6] bus: ti-sysc: Add support for using ti-sysc for MCAN on dra76x
From: Faiz Abbas @ 2018-06-06 6:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180606060826.14671-1-faiz_abbas@ti.com>
The dra76x MCAN generic interconnect module has a its own
format for the bits in the control registers.
Therefore add a new module type, new regbits and new capabilities
specific to the MCAN module.
Acked-by: Rob Herring <robh@kernel.org>
CC: Tony Lindgren <tony@atomide.com>
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
---
.../devicetree/bindings/bus/ti-sysc.txt | 1 +
drivers/bus/ti-sysc.c | 18 ++++++++++++++++++
include/dt-bindings/bus/ti-sysc.h | 2 ++
include/linux/platform_data/ti-sysc.h | 1 +
4 files changed, 22 insertions(+)
diff --git a/Documentation/devicetree/bindings/bus/ti-sysc.txt b/Documentation/devicetree/bindings/bus/ti-sysc.txt
index 2957a9ae291f..ebbb11144b7b 100644
--- a/Documentation/devicetree/bindings/bus/ti-sysc.txt
+++ b/Documentation/devicetree/bindings/bus/ti-sysc.txt
@@ -36,6 +36,7 @@ Required standard properties:
"ti,sysc-omap-aes"
"ti,sysc-mcasp"
"ti,sysc-usb-host-fs"
+ "ti,sysc-dra7-mcan"
- reg shall have register areas implemented for the interconnect
target module in question such as revision, sysc and syss
diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c
index 7cd2fd04b212..4a2244419b9b 100644
--- a/drivers/bus/ti-sysc.c
+++ b/drivers/bus/ti-sysc.c
@@ -1262,6 +1262,23 @@ static const struct sysc_capabilities sysc_omap4_usb_host_fs = {
.regbits = &sysc_regbits_omap4_usb_host_fs,
};
+static const struct sysc_regbits sysc_regbits_dra7_mcan = {
+ .dmadisable_shift = -ENODEV,
+ .midle_shift = -ENODEV,
+ .sidle_shift = -ENODEV,
+ .clkact_shift = -ENODEV,
+ .enwkup_shift = 4,
+ .srst_shift = 0,
+ .emufree_shift = -ENODEV,
+ .autoidle_shift = -ENODEV,
+};
+
+static const struct sysc_capabilities sysc_dra7_mcan = {
+ .type = TI_SYSC_DRA7_MCAN,
+ .sysc_mask = SYSC_DRA7_MCAN_ENAWAKEUP | SYSC_OMAP4_SOFTRESET,
+ .regbits = &sysc_regbits_dra7_mcan,
+};
+
static int sysc_init_pdata(struct sysc *ddata)
{
struct ti_sysc_platform_data *pdata = dev_get_platdata(ddata->dev);
@@ -1441,6 +1458,7 @@ static const struct of_device_id sysc_match[] = {
{ .compatible = "ti,sysc-mcasp", .data = &sysc_omap4_mcasp, },
{ .compatible = "ti,sysc-usb-host-fs",
.data = &sysc_omap4_usb_host_fs, },
+ { .compatible = "ti,sysc-dra7-mcan", .data = &sysc_dra7_mcan, },
{ },
};
MODULE_DEVICE_TABLE(of, sysc_match);
diff --git a/include/dt-bindings/bus/ti-sysc.h b/include/dt-bindings/bus/ti-sysc.h
index 2c005376ac0e..7138384e2ef9 100644
--- a/include/dt-bindings/bus/ti-sysc.h
+++ b/include/dt-bindings/bus/ti-sysc.h
@@ -15,6 +15,8 @@
/* SmartReflex sysc found on 36xx and later */
#define SYSC_OMAP3_SR_ENAWAKEUP (1 << 26)
+#define SYSC_DRA7_MCAN_ENAWAKEUP (1 << 4)
+
/* SYSCONFIG STANDBYMODE/MIDLEMODE/SIDLEMODE supported by hardware */
#define SYSC_IDLE_FORCE 0
#define SYSC_IDLE_NO 1
diff --git a/include/linux/platform_data/ti-sysc.h b/include/linux/platform_data/ti-sysc.h
index 80ce28d40832..1ea3aab972b4 100644
--- a/include/linux/platform_data/ti-sysc.h
+++ b/include/linux/platform_data/ti-sysc.h
@@ -14,6 +14,7 @@ enum ti_sysc_module_type {
TI_SYSC_OMAP4_SR,
TI_SYSC_OMAP4_MCASP,
TI_SYSC_OMAP4_USB_HOST_FS,
+ TI_SYSC_DRA7_MCAN,
};
struct ti_sysc_cookie {
--
2.17.0
^ permalink raw reply related
* [PATCH v3 4/6] bus: ti-sysc: Add support for software reset
From: Faiz Abbas @ 2018-06-06 6:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180606060826.14671-1-faiz_abbas@ti.com>
Add support for the software reset of a target interconnect
module using its sysconfig and sysstatus registers.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
---
drivers/bus/ti-sysc.c | 40 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c
index 4a2244419b9b..74d716a7bd6e 100644
--- a/drivers/bus/ti-sysc.c
+++ b/drivers/bus/ti-sysc.c
@@ -22,11 +22,14 @@
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <linux/slab.h>
+#include <linux/iopoll.h>
#include <linux/platform_data/ti-sysc.h>
#include <dt-bindings/bus/ti-sysc.h>
+#define MAX_MODULE_SOFTRESET_WAIT 10000
+
static const char * const reg_names[] = { "rev", "sysc", "syss", };
enum sysc_clocks {
@@ -74,6 +77,11 @@ struct sysc {
struct delayed_work idle_work;
};
+void sysc_write(struct sysc *ddata, int offset, u32 value)
+{
+ writel_relaxed(value, ddata->module_va + offset);
+}
+
static u32 sysc_read(struct sysc *ddata, int offset)
{
if (ddata->cfg.quirks & SYSC_QUIRK_16BIT) {
@@ -700,6 +708,26 @@ static void sysc_init_revision_quirks(struct sysc *ddata)
}
}
+static int sysc_reset(struct sysc *ddata)
+{
+ int offset = ddata->offsets[SYSC_SYSCONFIG];
+ int val = sysc_read(ddata, offset);
+
+ val |= (0x1 << ddata->cap->regbits->srst_shift);
+ sysc_write(ddata, offset, val);
+
+ /* Poll on reset status */
+ if (ddata->cfg.quirks & SYSC_QUIRK_RESET_STATUS) {
+ offset = ddata->offsets[SYSC_SYSSTATUS];
+
+ return readl_poll_timeout(ddata->module_va + offset, val,
+ (val & ddata->cfg.syss_mask) == 0x0,
+ 100, MAX_MODULE_SOFTRESET_WAIT);
+ }
+
+ return 0;
+}
+
/* At this point the module is configured enough to read the revision */
static int sysc_init_module(struct sysc *ddata)
{
@@ -716,6 +744,18 @@ static int sysc_init_module(struct sysc *ddata)
return 0;
}
+
+ if (!(ddata->cfg.quirks & SYSC_QUIRK_NO_RESET_ON_INIT) &&
+ !ddata->legacy_mode) {
+ error = sysc_reset(ddata);
+ if (error) {
+ dev_err(ddata->dev, "Reset failed with %d\n", error);
+ pm_runtime_put_sync(ddata->dev);
+
+ return error;
+ }
+ }
+
ddata->revision = sysc_read_revision(ddata);
pm_runtime_put_sync(ddata->dev);
--
2.17.0
^ permalink raw reply related
* [PATCH v3 5/6] ARM: dts: Add generic interconnect target module node for MCAN
From: Faiz Abbas @ 2018-06-06 6:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180606060826.14671-1-faiz_abbas@ti.com>
The ti-sysc driver provides support for manipulating the idle modes
and interconnect level resets.
Add the generic interconnect target module node for MCAN to support
the same.
CC: Tony Lindgren <tony@atomide.com>
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
---
arch/arm/boot/dts/dra76x.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/dra76x.dtsi b/arch/arm/boot/dts/dra76x.dtsi
index bfc82636999c..5157cc431574 100644
--- a/arch/arm/boot/dts/dra76x.dtsi
+++ b/arch/arm/boot/dts/dra76x.dtsi
@@ -11,6 +11,24 @@
/ {
compatible = "ti,dra762", "ti,dra7";
+ ocp {
+ target-module at 42c01900 {
+ compatible = "ti,sysc-dra7-mcan", "ti,sysc";
+ ranges = <0x0 0x42c00000 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x42c01900 0x4>,
+ <0x42c01904 0x4>,
+ <0x42c01908 0x4>;
+ reg-names = "rev", "sysc", "syss";
+ ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET |
+ SYSC_DRA7_MCAN_ENAWAKEUP)>;
+ ti,syss-mask = <1>;
+ clocks = <&wkupaon_clkctrl DRA7_ADC_CLKCTRL 0>;
+ clock-names = "fck";
+ };
+ };
+
};
/* MCAN interrupts are hard-wired to irqs 67, 68 */
--
2.17.0
^ permalink raw reply related
* [PATCH v3 6/6] ARM: dts: dra76x: Add MCAN node
From: Faiz Abbas @ 2018-06-06 6:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180606060826.14671-1-faiz_abbas@ti.com>
From: Franklin S Cooper Jr <fcooper@ti.com>
Add support for the MCAN peripheral which supports both classic
CAN messages along with the new CAN-FD message.
Add MCAN node to evm and enable it with a maximum datarate of 5 mbps
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
---
arch/arm/boot/dts/dra76-evm.dts | 6 ++++++
arch/arm/boot/dts/dra76x.dtsi | 13 +++++++++++++
2 files changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/dra76-evm.dts b/arch/arm/boot/dts/dra76-evm.dts
index 2deb96405d06..b6ac2b6ffc6e 100644
--- a/arch/arm/boot/dts/dra76-evm.dts
+++ b/arch/arm/boot/dts/dra76-evm.dts
@@ -404,3 +404,9 @@
phys = <&pcie1_phy>, <&pcie2_phy>;
phy-names = "pcie-phy0", "pcie-phy1";
};
+
+&m_can0 {
+ can-transceiver {
+ max-bitrate = <5000000>;
+ };
+};
diff --git a/arch/arm/boot/dts/dra76x.dtsi b/arch/arm/boot/dts/dra76x.dtsi
index 5157cc431574..613e4dc0ed3e 100644
--- a/arch/arm/boot/dts/dra76x.dtsi
+++ b/arch/arm/boot/dts/dra76x.dtsi
@@ -26,6 +26,19 @@
ti,syss-mask = <1>;
clocks = <&wkupaon_clkctrl DRA7_ADC_CLKCTRL 0>;
clock-names = "fck";
+
+ m_can0: mcan at 1a00 {
+ compatible = "bosch,m_can";
+ reg = <0x1a00 0x4000>, <0x0 0x18FC>;
+ reg-names = "m_can", "message_ram";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "int0", "int1";
+ clocks = <&mcan_clk>, <&l3_iclk_div>;
+ clock-names = "cclk", "hclk";
+ bosch,mram-cfg = <0x0 0 0 32 0 0 1 1>;
+ };
};
};
--
2.17.0
^ permalink raw reply related
* [PATCH v4 2/3] arm: shmobile: Add the R9A06G032 SMP enabler driver
From: Michel Pollet @ 2018-06-06 6:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <0481173f-6384-98d6-707c-89dc5ef103f0@gmail.com>
Hi Frank,
On 05 June 2018 18:34, Frank wrote:
> On 06/05/18 04:28, Michel Pollet wrote:
> > The Renesas R9A06G032 second CA7 is parked in a ROM pen at boot time,
> > it requires a special enable method to get it started.
> >
> > Signed-off-by: Michel Pollet <michel.pollet@bp.renesas.com>
> > ---
> > arch/arm/mach-shmobile/Makefile | 1 +
> > arch/arm/mach-shmobile/smp-r9a06g032.c | 79
> > ++++++++++++++++++++++++++++++++++
> > 2 files changed, 80 insertions(+)
> > create mode 100644 arch/arm/mach-shmobile/smp-r9a06g032.c
> >
> > diff --git a/arch/arm/mach-shmobile/Makefile
> > b/arch/arm/mach-shmobile/Makefile index 1939f52..d7fc98f 100644
> > --- a/arch/arm/mach-shmobile/Makefile
> > +++ b/arch/arm/mach-shmobile/Makefile
> > @@ -34,6 +34,7 @@ smp-$(CONFIG_ARCH_SH73A0)+= smp-sh73a0.o
> headsmp-scu.o platsmp-scu.o
> > smp-$(CONFIG_ARCH_R8A7779)+= smp-r8a7779.o headsmp-scu.o
> platsmp-scu.o
> > smp-$(CONFIG_ARCH_R8A7790)+= smp-r8a7790.o
> > smp-$(CONFIG_ARCH_R8A7791)+= smp-r8a7791.o
> > +smp-$(CONFIG_ARCH_R9A06G032)+= smp-r9a06g032.o
> > smp-$(CONFIG_ARCH_EMEV2)+= smp-emev2.o headsmp-scu.o
> platsmp-scu.o
> >
> > # PM objects
> > diff --git a/arch/arm/mach-shmobile/smp-r9a06g032.c
> > b/arch/arm/mach-shmobile/smp-r9a06g032.c
> > new file mode 100644
> > index 0000000..cd40e6e
> > --- /dev/null
> > +++ b/arch/arm/mach-shmobile/smp-r9a06g032.c
> > @@ -0,0 +1,79 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * R9A06G032 Second CA7 enabler.
> > + *
> > + * Copyright (C) 2018 Renesas Electronics Europe Limited
> > + *
> > + * Michel Pollet <michel.pollet@bp.renesas.com>,
> <buserror@gmail.com>
> > + * Derived from action,s500-smp
> > + */
> > +
> > +#include <linux/io.h>
> > +#include <linux/of.h>
> > +#include <linux/of_address.h>
> > +#include <linux/smp.h>
> > +
> > +/*
> > + * The second CPU is parked in ROM at boot time. It requires waking
> > +it after
> > + * writing an address into the BOOTADDR register of sysctrl.
> > + *
> > + * So the default value of the "cpu-release-addr" corresponds to
> BOOTADDR...
> > + *
> > + * *However* the BOOTADDR register is not available when the kernel
> > + * starts in NONSEC mode.
> > + *
> > + * So for NONSEC mode, the bootloader re-parks the second CPU into a
> > +pen
> > + * in SRAM, and changes the "cpu-release-addr" of linux's DT to a
> > +SRAM address,
> > + * which is not restricted.
>
> The binding document for cpu-release-addr does not have a definition for 32
> bit arm. The existing definition is only 64 bit arm. Please add the definition
> for 32 bit arm to patch 1.
Hmmm I do find a definition in
Documentation/devicetree/bindings/arm/cpus.txt -- just under where I
added my 'enable-method' -- And it is already used as 32 bits in at least
arch/arm/boot/dts/stih407-family.dtsi.
What do you want me to add to this exactly? Do you want me to just
change "required for systems that have an "enable-method" property
value of "spin-table" to also specify renesas,r9a06g032 ?
Thanks!
Michel
>
> -Frank
>
>
> > + */
> > +
> > +static void __iomem *cpu_bootaddr;
> > +
> > +static DEFINE_SPINLOCK(cpu_lock);
> > +
> > +static int r9a06g032_smp_boot_secondary(unsigned int cpu, struct
> > +task_struct *idle) {
> > +if (!cpu_bootaddr)
> > +return -ENODEV;
> > +
> > +spin_lock(&cpu_lock);
> > +
> > +writel(__pa_symbol(secondary_startup), cpu_bootaddr);
> > +arch_send_wakeup_ipi_mask(cpumask_of(cpu));
> > +
> > +spin_unlock(&cpu_lock);
> > +
> > +return 0;
> > +}
> > +
> > +static void __init r9a06g032_smp_prepare_cpus(unsigned int max_cpus)
> > +{
> > +struct device_node *dn;
> > +int ret;
> > +u32 bootaddr;
> > +
> > +dn = of_get_cpu_node(1, NULL);
> > +if (!dn) {
> > +pr_err("CPU#1: missing device tree node\n");
> > +return;
> > +}
> > +/*
> > + * Determine the address from which the CPU is polling.
> > + * The bootloader *does* change this property
> > + */
> > +ret = of_property_read_u32(dn, "cpu-release-addr", &bootaddr);
> > +of_node_put(dn);
> > +if (ret) {
> > +pr_err("CPU#1: invalid cpu-release-addr property\n");
> > +return;
> > +}
> > +pr_info("CPU#1: cpu-release-addr %08x\n", bootaddr);
> > +
> > +cpu_bootaddr = ioremap(bootaddr, sizeof(bootaddr)); }
> > +
> > +static const struct smp_operations r9a06g032_smp_ops __initconst = {
> > +.smp_prepare_cpus = r9a06g032_smp_prepare_cpus,
> > +.smp_boot_secondary = r9a06g032_smp_boot_secondary, };
> > +CPU_METHOD_OF_DECLARE(r9a06g032_smp, "renesas,r9a06g032-smp",
> > +&r9a06g032_smp_ops);
> >
Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.
^ permalink raw reply
* [PATCH 01/20] coresight: Fix memory leak in coresight_register
From: Arvind Yadav @ 2018-06-06 6:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1528235011-30691-2-git-send-email-suzuki.poulose@arm.com>
Hi Suzuki,
On Wednesday 06 June 2018 03:13 AM, Suzuki K Poulose wrote:
> commit 6403587a930c ("coresight: use put_device() instead of kfree()")
> introduced a memory leak where, if we fail to register the device
> for coresight_device, we don't free the "coresight_device" object,
> which was allocated via kzalloc(). Fix this by jumping to the
> appropriate error path.
put_device() will decrement the last reference and then
free the memory by calling dev->release. Internally
put_device() -> kobject_put() -> kobject_cleanup() which is
responsible to call 'dev -> release' and also free other kobject
resources. If you will see the coresight_device_release. There
we are releasing all allocated memory. Still if you call kfree() again
then it'll be redundancy.
~arvind
>
> Fixes: commit 6403587a930c ("coresight: use put_device() instead of kfree()")
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Arvind Yadav <arvind.yadav.cs@gmail.com>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
> drivers/hwtracing/coresight/coresight.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight.c b/drivers/hwtracing/coresight/coresight.c
> index 4969b32..2893cfe 100644
> --- a/drivers/hwtracing/coresight/coresight.c
> +++ b/drivers/hwtracing/coresight/coresight.c
> @@ -1020,7 +1020,7 @@ struct coresight_device *coresight_register(struct coresight_desc *desc)
> ret = device_register(&csdev->dev);
> if (ret) {
> put_device(&csdev->dev);
> - goto err_kzalloc_csdev;
> + goto err_kzalloc_refcnts;
> }
>
> mutex_lock(&coresight_mutex);
^ permalink raw reply
* [PATCH V2 2/2] arm: dts: sunxi: Add missing cooling device properties for CPUs
From: Maxime Ripard @ 2018-06-06 6:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAGb2v65EX2RwKjxPw+EK4i6rkfgOJoCU2amuFkF-tHQT40isxw@mail.gmail.com>
On Wed, Jun 06, 2018 at 12:02:20AM +0800, Chen-Yu Tsai wrote:
> On Tue, Jun 5, 2018 at 3:11 PM, Maxime Ripard <maxime.ripard@bootlin.com> wrote:
> > On Tue, Jun 05, 2018 at 10:17:49AM +0530, Viresh Kumar wrote:
> >> The cooling device properties, like "#cooling-cells" and
> >> "dynamic-power-coefficient", should either be present for all the CPUs
> >> of a cluster or none. If these are present only for a subset of CPUs of
> >> a cluster then things will start falling apart as soon as the CPUs are
> >> brought online in a different order. For example, this will happen
> >> because the operating system looks for such properties in the CPU node
> >> it is trying to bring up, so that it can register a cooling device.
> >>
> >> Add such missing properties.
> >>
> >> Fix other missing properties (clocks, OPP, clock latency) as well to
> >> make it all work.
> >>
> >> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
> >
> > Applied both, thanks!
>
> Please fix the "ARM" prefix when applying. :)
Done, thanks for the reminder :)
Maxime
--
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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* [PATCH v13 0/3] Fix issues with huge mapping in ioremap for ARM64
From: Chintan Pandya @ 2018-06-06 7:01 UTC (permalink / raw)
To: linux-arm-kernel
This series of patches re-bring huge vmap back for arm64.
Patch 1/3 has been taken by Toshi in his series of patches
by name "[PATCH v3 0/3] fix free pmd/pte page handlings on x86"
to avoid merge conflict with this series.
These patches are tested on 4.16 kernel with Cortex-A75 based SoC.
The test used for verifying these patches is a stress test on
ioremap/unmap which tries to re-use same io-address but changes
size of mapping randomly i.e. 4K to 2M to 1G etc. The same test
used to reproduce 3rd level translation fault without these fixes
(and also of course with Revert "arm64: Enforce BBM for huge IO/VMAP
mappings" being part of the tree).
These patches can also go into '-stable' branch (if accepted)
for 4.6 onwards.
>From V12->V13:
- Dropped v12 3/5 and v12 5/5
- Using existing APIs like pte_offset_kernel and pmd_offset
instead of pmd_page_vaddr & pud_page_vaddr
- Updated commit log message for 3/3
- Some other cosmetic corrections in 3/3
>From V11->V12:
- Introduced p*d_page_vaddr helper macros and using them
- Rebased over current tip
>From V10->V11:
- Updated pud_free_pmd_page & pmd_free_pte_page to use consistent
conding style
- Fixed few bugs by using pmd_page_paddr & pud_page_paddr
>From V9->V10:
- Updated commit log for patch 1/4 by Toshi
- Addressed review comments by Will on patch 3/4
>From V8->V9:
- Used __TLBI_VADDR macros in new TLB flush API
>From V7->V8:
- Properly fixed compilation issue in x86 file
>From V6->V7:
- Fixed compilation issue in x86 case
- V6 patches were not properly enumarated
>From V5->V6:
- Use __flush_tlb_kernel_pgtable() for both PUD and PMD. Remove
"bool tlb_inv" based variance as it is not need now
- Re-naming for consistency
>From V4->V5:
- Add new API __flush_tlb_kernel_pgtable(unsigned long addr)
for kernel addresses
>From V3->V4:
- Add header for 'addr' in x86 implementation
- Re-order pmd/pud clear and table free
- Avoid redundant TLB invalidatation in one perticular case
>From V2->V3:
- Use the exisiting page table free interface to do arm64
specific things
>From V1->V2:
- Rebased my patches on top of "[PATCH v2 1/2] mm/vmalloc:
Add interfaces to free unmapped page table"
- Honored BBM for ARM64
Chintan Pandya (3):
ioremap: Update pgtable free interfaces with addr
arm64: tlbflush: Introduce __flush_tlb_kernel_pgtable
arm64: Implement page table free interfaces
arch/arm64/include/asm/tlbflush.h | 7 ++++++
arch/arm64/mm/mmu.c | 48 +++++++++++++++++++++++++++++++++++----
arch/x86/mm/pgtable.c | 8 ++++---
include/asm-generic/pgtable.h | 8 +++----
lib/ioremap.c | 4 ++--
5 files changed, 62 insertions(+), 13 deletions(-)
--
Qualcomm India Private Limited, on behalf of Qualcomm Innovation
Center, Inc., is a member of Code Aurora Forum, a Linux Foundation
Collaborative Project
^ permalink raw reply
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