* [PATCH] arm64: dts: freescale: Update to use SPDX identifiers
From: Li Yang @ 2018-06-12 18:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAOMZO5C0pk-27ztxeJSENBN_-i9o+2sCoS9Cc75Q_Y=-_z_dQg@mail.gmail.com>
On Tue, Jun 12, 2018 at 1:32 PM, Fabio Estevam <festevam@gmail.com> wrote:
> Hi Li,
>
> On Tue, Jun 12, 2018 at 3:28 PM, Li Yang <leoyang.li@nxp.com> wrote:
>
>> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
>> index 7286b1e..f90c040 100644
>> --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
>> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
>> @@ -1,45 +1,9 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>
> Here you use GPL-2.0+
>
>> /*
>> * Device Tree file for Freescale LS1012A Freedom Board.
>> *
>> * Copyright 2016 Freescale Semiconductor, Inc.
>> *
>> - * This file is dual-licensed: you can use it either under the terms
>> - * of the GPLv2 or the X11 license, at your option. Note that this dual
>
> ,but the original text says GPL-2.0, not GPL-2.0+, so there is a mismatch.
The original text has a conflict probably because some people didn't
regard GPLv2+ as a license name. But the following detailed
explanation mentioned "you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation;either version 2 of the License, or (at your
option) any later version." I think we should honor the more verbosed
text than the briefing(same way for X11 vs MIT).
Regards,
Leo
^ permalink raw reply
* [PATCH v2 1/4] dt-bindings: add bindings for px30 clock controller
From: Rob Herring @ 2018-06-12 19:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1528439519-30135-2-git-send-email-zhangqing@rock-chips.com>
On Fri, Jun 08, 2018 at 02:31:56PM +0800, Elaine Zhang wrote:
> Add devicetree bindings for Rockchip cru which found on
> Rockchip SoCs.
>
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> ---
> .../bindings/clock/rockchip,px30-cru.txt | 67 ++++++++++++++++++++++
> 1 file changed, 67 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt
>
> diff --git a/Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt b/Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt
> new file mode 100644
> index 000000000000..af5a45b680d0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/rockchip,px30-cru.txt
> @@ -0,0 +1,67 @@
> +* Rockchip PX30 Clock and Reset Unit
> +
> +The PX30 clock controller generates and supplies clock to various
> +controllers within the SoC and also implements a reset controller for SoC
> +peripherals.
> +
> +Required Properties:
> +
> +- compatible: PMU for CRU should be "rockchip,px30-pmu-cru"
> +- compatible: CRU should be "rockchip,px30-cru"
> +- reg: physical base address of the controller and length of memory mapped
> + region.
> +- #clock-cells: should be 1.
> +- #reset-cells: should be 1.
> +
> +Optional Properties:
> +
> +- rockchip,grf: phandle to the syscon managing the "general register files"
> + If missing, pll rates are not changeable, due to the missing pll lock status.
> +
> +Each clock is assigned an identifier and client nodes can use this identifier
> +to specify the clock which they consume. All available clocks are defined as
> +preprocessor macros in the dt-bindings/clock/px30-cru.h headers and can be
> +used in device tree sources. Similar macros exist for the reset sources in
> +these files.
> +
> +External clocks:
> +
> +There are several clocks that are generated outside the SoC. It is expected
> +that they are defined using standard clock bindings with following
> +clock-output-names:
> + - "xin24m" - crystal input - required,
> + - "xin32k" - rtc clock - optional,
> + - "i2sx_clkin" - external I2S clock - optional,
> + - "gmac_clkin" - external GMAC clock - optional
> +
> +Example: Clock controller node:
> +
> + pmucru: pmu-clock-controller at ff2bc000 {
s/pmu-clock-controller/clock-controller/
> + compatible = "rockchip,px30-pmucru";
> + reg = <0x0 0xff2bc000 0x0 0x1000>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + cru: clock-controller at ff2b0000 {
> + compatible = "rockchip,px30-cru";
> + reg = <0x0 0xff2b0000 0x0 0x1000>;
> + rockchip,grf = <&grf>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> +Example: UART controller node that consumes the clock generated by the clock
> + controller:
> +
> + uart0: serial at ff030000 {
> + compatible = "rockchip,px30-uart", "snps,dw-apb-uart";
> + reg = <0x0 0xff030000 0x0 0x100>;
> + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>;
> + clock-names = "baudclk", "apb_pclk";
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
Don't show status in examples.
> + };
> +
> --
> 1.9.1
>
>
^ permalink raw reply
* [U-Boot] [RFC PATCH 0/2] ARM: v7: Enable basic framework for supporting bits for CVE-2017-5715
From: Nishanth Menon @ 2018-06-12 19:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAOMZO5CcEf=EhFWknKmCXXLJPOgx=65jLH+X1OAGkg5VxBGVew@mail.gmail.com>
On Tue, May 22, 2018 at 9:05 AM, Fabio Estevam <festevam@gmail.com> wrote:
> On Thu, Jan 25, 2018 at 7:45 PM, Nishanth Menon <nm@ti.com> wrote:
>> Hi Folks,
>>
>> This is a follow through on the discussion we have had in [1].
>> This itself is'nt a complete solution and is based on recommendation
>> This from Arm[2] for variant 2 CVE-2017-5715
>>
>> The Linux kernel discussions are spread out in [3], ATF and OPTEE
>> status are available in [4].
>>
>> This is just an RFC series (build tested at this point) to check if
>> the direction is fine and should follow the final solution once kernel
>> patches get to upstream, IMHO.
>>
>> NOTE: As per ARM recommendations[2], and discussions in list[1] ARM
>> Cortex-A9/12/17 do not need additional steps in u-boot to enable the
>> OS level workarounds.
>>
>> Nishanth Menon (2):
>> ARM: Introduce ability to enable ACR::IBE on Cortex-A8 for
>> CVE-2017-5715
>> ARM: Introduce ability to enable invalidate of BTB on Cortex-A15 for
>> CVE-2017-5715
>
I started respinning the series, while there is definitely a use of
implementing in u-boot,
I am starting to wonder if we should also be doing this in kernel. ->
following is an example:
for OMAP5uEVM (dual A15) with next-20180612 -> Uboot does setup the
IBE bit, so the
CPU0 ICIALLU does get activated however, that is not true for CPU1.
Further if we enter low power states, we'd also start loosing the
context, wont we?
Log:
[ 0.001484] Calibrating delay loop (skipped), value calculated
using timer frequency.. 12.28 BogoMIPS (lpj=61440)
[ 0.001510] pid_max: default: 32768 minimum: 301
[ 0.001804] Security Framework initialized
[ 0.001907] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
[ 0.001928] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 bytes)
[ 0.004144] CPU: Testing write buffer coherency: ok
[ 0.004258] CPU0: Spectre v2: using ICIALLU workaround
[ 0.005130] /cpus/cpu at 0 missing clock-frequency property
[ 0.005159] /cpus/cpu at 1 missing clock-frequency property
[ 0.005178] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[ 0.006660] Setting up static identity map for 0x80100000 - 0x80100078
[ 0.007036] rcu: Hierarchical SRCU implementation.
[ 0.008424] smp: Bringing up secondary CPUs ...
[ 0.010557] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
[ 0.010566] CPU1: Spectre v2: firmware did not set auxiliary
control register IBE bit, system vulnerable
[ 0.011162] smp: Brought up 1 node, 2 CPUs
[ 0.011181] SMP: Total of 2 processors activated (24.57 BogoMIPS).
[ 0.011197] CPU: All CPU(s) started in HYP mode.
[ 0.011211] CPU: Virtualization extensions available.
[ 0.013729] devtmpfs: initialized
[ 0.044497] VFP support v0.3: implementor 41 architecture 4 part 30
variant f rev 0
[ 0.046160] clocksource: jiffies: mask: 0xffffffff max_cycles:
0xffffffff, max_idle_ns: 19112604462750000 ns
[ 0.046201] futex hash table entries: 512 (order: 3, 32768 bytes)
[ 0.046942] pinctrl core: initialized pinctrl subsystem
[ 0.050282] NET: Registered protocol family 16
[ 0.054624] DMA: preallocated 256 KiB pool for atomic coherent allocations
[ 0.055930] omap_hwmod: l3_main_3 using broken dt data from ocp
[ 0.057244] omap_hwmod: l3_main_2 using broken dt data from ocp
[ 0.167706] audit: initializing netlink subsys (disabled)
[ 0.168044] audit: type=2000 audit(0.160:1): state=initialized
audit_enabled=0 res=1
[ 0.168979] (NULL device *): Failed to create dummy-scm_conf at 0
debugfs directory
[ 0.169566] cpuidle: using governor menu
[ 0.184644] OMAP GPIO hardware version 0.1
--
---
Regards,
Nishanth Menon
^ permalink raw reply
* [PATCH v2 2/4] clk: rockchip: add dt-binding header for px30
From: Rob Herring @ 2018-06-12 19:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1528439519-30135-3-git-send-email-zhangqing@rock-chips.com>
On Fri, Jun 08, 2018 at 02:31:57PM +0800, Elaine Zhang wrote:
> Add the dt-bindings header for the px30, that gets shared between
> the clock controller and the clock references in the dts.
> Add softreset ID for px30.
>
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> ---
> include/dt-bindings/clock/px30-cru.h | 402 +++++++++++++++++++++++++++++++++++
> 1 file changed, 402 insertions(+)
> create mode 100644 include/dt-bindings/clock/px30-cru.h
>
> diff --git a/include/dt-bindings/clock/px30-cru.h b/include/dt-bindings/clock/px30-cru.h
> new file mode 100644
> index 000000000000..6b0b9507597a
> --- /dev/null
> +++ b/include/dt-bindings/clock/px30-cru.h
> @@ -0,0 +1,402 @@
> +/*
> + * Copyright (c) 2018 Rockchip Electronics Co. Ltd.
> + * Author: Elaine Zhang<zhangqing@rock-chips.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
Use an SPDX tag instead.
Otherwise,
Reviewed-by: Rob Herring <robh@kernel.org>
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_PX30_H
> +#define _DT_BINDINGS_CLK_ROCKCHIP_PX30_H
> +
> +/* core clocks */
> +#define PLL_APLL 1
> +#define PLL_DPLL 2
> +#define PLL_CPLL 3
> +#define PLL_NPLL 4
> +#define APLL_BOOST_H 5
> +#define APLL_BOOST_L 6
> +#define ARMCLK 7
> +
> +/* sclk gates (special clocks) */
> +#define USB480M 14
> +#define SCLK_PDM 15
> +#define SCLK_I2S0_TX 16
> +#define SCLK_I2S0_TX_OUT 17
> +#define SCLK_I2S0_RX 18
> +#define SCLK_I2S0_RX_OUT 19
> +#define SCLK_I2S1 20
> +#define SCLK_I2S1_OUT 21
> +#define SCLK_I2S2 22
> +#define SCLK_I2S2_OUT 23
> +#define SCLK_UART1 24
> +#define SCLK_UART2 25
> +#define SCLK_UART3 26
> +#define SCLK_UART4 27
> +#define SCLK_UART5 28
> +#define SCLK_I2C0 29
> +#define SCLK_I2C1 30
> +#define SCLK_I2C2 31
> +#define SCLK_I2C3 32
> +#define SCLK_I2C4 33
> +#define SCLK_PWM0 34
> +#define SCLK_PWM1 35
> +#define SCLK_SPI0 36
> +#define SCLK_SPI1 37
> +#define SCLK_TIMER0 38
> +#define SCLK_TIMER1 39
> +#define SCLK_TIMER2 40
> +#define SCLK_TIMER3 41
> +#define SCLK_TIMER4 42
> +#define SCLK_TIMER5 43
> +#define SCLK_TSADC 44
> +#define SCLK_SARADC 45
> +#define SCLK_OTP 46
> +#define SCLK_OTP_USR 47
> +#define SCLK_CRYPTO 48
> +#define SCLK_CRYPTO_APK 49
> +#define SCLK_DDRC 50
> +#define SCLK_ISP 51
> +#define SCLK_CIF_OUT 52
> +#define SCLK_RGA_CORE 53
> +#define SCLK_VOPB_PWM 54
> +#define SCLK_NANDC 55
> +#define SCLK_SDIO 56
> +#define SCLK_EMMC 57
> +#define SCLK_SFC 58
> +#define SCLK_SDMMC 59
> +#define SCLK_OTG_ADP 60
> +#define SCLK_GMAC_SRC 61
> +#define SCLK_GMAC 62
> +#define SCLK_GMAC_RX_TX 63
> +#define SCLK_MAC_REF 64
> +#define SCLK_MAC_REFOUT 65
> +#define SCLK_MAC_OUT 66
> +#define SCLK_SDMMC_DRV 67
> +#define SCLK_SDMMC_SAMPLE 68
> +#define SCLK_SDIO_DRV 69
> +#define SCLK_SDIO_SAMPLE 70
> +#define SCLK_EMMC_DRV 71
> +#define SCLK_EMMC_SAMPLE 72
> +#define SCLK_GPU 73
> +#define SCLK_PVTM 74
> +#define SCLK_CORE_VPU 75
> +#define SCLK_GMAC_RMII 76
> +#define SCLK_UART2_SRC 77
> +#define SCLK_NANDC_DIV 78
> +#define SCLK_NANDC_DIV50 79
> +#define SCLK_SDIO_DIV 80
> +#define SCLK_SDIO_DIV50 81
> +#define SCLK_EMMC_DIV 82
> +#define SCLK_EMMC_DIV50 83
> +#define SCLK_DDRCLK 84
> +#define SCLK_UART1_SRC 85
> +
> +/* dclk gates */
> +#define DCLK_VOPB 150
> +#define DCLK_VOPL 151
> +
> +/* aclk gates */
> +#define ACLK_GPU 170
> +#define ACLK_BUS_PRE 171
> +#define ACLK_CRYPTO 172
> +#define ACLK_VI_PRE 173
> +#define ACLK_VO_PRE 174
> +#define ACLK_VPU 175
> +#define ACLK_PERI_PRE 176
> +#define ACLK_GMAC 178
> +#define ACLK_CIF 179
> +#define ACLK_ISP 180
> +#define ACLK_VOPB 181
> +#define ACLK_VOPL 182
> +#define ACLK_RGA 183
> +#define ACLK_GIC 184
> +#define ACLK_DCF 186
> +#define ACLK_DMAC 187
> +#define ACLK_BUS_SRC 188
> +#define ACLK_PERI_SRC 189
> +
> +/* hclk gates */
> +#define HCLK_BUS_PRE 240
> +#define HCLK_CRYPTO 241
> +#define HCLK_VI_PRE 242
> +#define HCLK_VO_PRE 243
> +#define HCLK_VPU 244
> +#define HCLK_PERI_PRE 245
> +#define HCLK_MMC_NAND 246
> +#define HCLK_SDMMC 247
> +#define HCLK_USB 248
> +#define HCLK_CIF 249
> +#define HCLK_ISP 250
> +#define HCLK_VOPB 251
> +#define HCLK_VOPL 252
> +#define HCLK_RGA 253
> +#define HCLK_NANDC 254
> +#define HCLK_SDIO 255
> +#define HCLK_EMMC 256
> +#define HCLK_SFC 257
> +#define HCLK_OTG 258
> +#define HCLK_HOST 259
> +#define HCLK_HOST_ARB 260
> +#define HCLK_PDM 261
> +#define HCLK_I2S0 262
> +#define HCLK_I2S1 263
> +#define HCLK_I2S2 264
> +
> +/* pclk gates */
> +#define PCLK_BUS_PRE 320
> +#define PCLK_DDR 321
> +#define PCLK_VO_PRE 322
> +#define PCLK_GMAC 323
> +#define PCLK_MIPI_DSI 324
> +#define PCLK_MIPIDSIPHY 325
> +#define PCLK_MIPICSIPHY 326
> +#define PCLK_USB_GRF 327
> +#define PCLK_DCF 328
> +#define PCLK_UART1 329
> +#define PCLK_UART2 330
> +#define PCLK_UART3 331
> +#define PCLK_UART4 332
> +#define PCLK_UART5 333
> +#define PCLK_I2C0 334
> +#define PCLK_I2C1 335
> +#define PCLK_I2C2 336
> +#define PCLK_I2C3 337
> +#define PCLK_I2C4 338
> +#define PCLK_PWM0 339
> +#define PCLK_PWM1 340
> +#define PCLK_SPI0 341
> +#define PCLK_SPI1 342
> +#define PCLK_SARADC 343
> +#define PCLK_TSADC 344
> +#define PCLK_TIMER 345
> +#define PCLK_OTP_NS 346
> +#define PCLK_WDT_NS 347
> +#define PCLK_GPIO1 348
> +#define PCLK_GPIO2 349
> +#define PCLK_GPIO3 350
> +#define PCLK_ISP 351
> +#define PCLK_CIF 352
> +#define PCLK_OTP_PHY 353
> +
> +#define CLK_NR_CLKS (PCLK_OTP_PHY + 1)
> +
> +/* pmu-clocks indices */
> +
> +#define PLL_GPLL 1
> +
> +#define SCLK_RTC32K_PMU 4
> +#define SCLK_WIFI_PMU 5
> +#define SCLK_UART0_PMU 6
> +#define SCLK_PVTM_PMU 7
> +#define PCLK_PMU_PRE 8
> +#define SCLK_REF24M_PMU 9
> +#define SCLK_USBPHY_REF 10
> +#define SCLK_MIPIDSIPHY_REF 11
> +
> +#define XIN24M_DIV 12
> +
> +#define PCLK_GPIO0_PMU 20
> +#define PCLK_UART0_PMU 21
> +
> +#define CLKPMU_NR_CLKS (PCLK_UART0_PMU + 1)
> +
> +/* soft-reset indices */
> +#define SRST_CORE0_PO 0
> +#define SRST_CORE1_PO 1
> +#define SRST_CORE2_PO 2
> +#define SRST_CORE3_PO 3
> +#define SRST_CORE0 4
> +#define SRST_CORE1 5
> +#define SRST_CORE2 6
> +#define SRST_CORE3 7
> +#define SRST_CORE0_DBG 8
> +#define SRST_CORE1_DBG 9
> +#define SRST_CORE2_DBG 10
> +#define SRST_CORE3_DBG 11
> +#define SRST_TOPDBG 12
> +#define SRST_CORE_NOC 13
> +#define SRST_STRC_A 14
> +#define SRST_L2C 15
> +
> +#define SRST_DAP 16
> +#define SRST_CORE_PVTM 17
> +#define SRST_GPU 18
> +#define SRST_GPU_NIU 19
> +#define SRST_UPCTL2 20
> +#define SRST_UPCTL2_A 21
> +#define SRST_UPCTL2_P 22
> +#define SRST_MSCH 23
> +#define SRST_MSCH_P 24
> +#define SRST_DDRMON_P 25
> +#define SRST_DDRSTDBY_P 26
> +#define SRST_DDRSTDBY 27
> +#define SRST_DDRGRF_p 28
> +#define SRST_AXI_SPLIT_A 29
> +#define SRST_AXI_CMD_A 30
> +#define SRST_AXI_CMD_P 31
> +
> +#define SRST_DDRPHY 32
> +#define SRST_DDRPHYDIV 33
> +#define SRST_DDRPHY_P 34
> +#define SRST_VPU_A 36
> +#define SRST_VPU_NIU_A 37
> +#define SRST_VPU_H 38
> +#define SRST_VPU_NIU_H 39
> +#define SRST_VI_NIU_A 40
> +#define SRST_VI_NIU_H 41
> +#define SRST_ISP_H 42
> +#define SRST_ISP 43
> +#define SRST_CIF_A 44
> +#define SRST_CIF_H 45
> +#define SRST_CIF_PCLKIN 46
> +#define SRST_MIPICSIPHY_P 47
> +
> +#define SRST_VO_NIU_A 48
> +#define SRST_VO_NIU_H 49
> +#define SRST_VO_NIU_P 50
> +#define SRST_VOPB_A 51
> +#define SRST_VOPB_H 52
> +#define SRST_VOPB 53
> +#define SRST_PWM_VOPB 54
> +#define SRST_VOPL_A 55
> +#define SRST_VOPL_H 56
> +#define SRST_VOPL 57
> +#define SRST_RGA_A 58
> +#define SRST_RGA_H 59
> +#define SRST_RGA 60
> +#define SRST_MIPIDSI_HOST_P 61
> +#define SRST_MIPIDSIPHY_P 62
> +#define SRST_VPU_CORE 63
> +
> +#define SRST_PERI_NIU_A 64
> +#define SRST_USB_NIU_H 65
> +#define SRST_USB2OTG_H 66
> +#define SRST_USB2OTG 67
> +#define SRST_USB2OTG_ADP 68
> +#define SRST_USB2HOST_H 69
> +#define SRST_USB2HOST_ARB_H 70
> +#define SRST_USB2HOST_AUX_H 71
> +#define SRST_USB2HOST_EHCI 72
> +#define SRST_USB2HOST 73
> +#define SRST_USBPHYPOR 74
> +#define SRST_USBPHY_OTG_PORT 75
> +#define SRST_USBPHY_HOST_PORT 76
> +#define SRST_USBPHY_GRF 77
> +#define SRST_CPU_BOOST_P 78
> +#define SRST_CPU_BOOST 79
> +
> +#define SRST_MMC_NAND_NIU_H 80
> +#define SRST_SDIO_H 81
> +#define SRST_EMMC_H 82
> +#define SRST_SFC_H 83
> +#define SRST_SFC 84
> +#define SRST_SDCARD_NIU_H 85
> +#define SRST_SDMMC_H 86
> +#define SRST_NANDC_H 89
> +#define SRST_NANDC 90
> +#define SRST_GMAC_NIU_A 92
> +#define SRST_GMAC_NIU_P 93
> +#define SRST_GMAC_A 94
> +
> +#define SRST_PMU_NIU_P 96
> +#define SRST_PMU_SGRF_P 97
> +#define SRST_PMU_GRF_P 98
> +#define SRST_PMU 99
> +#define SRST_PMU_MEM_P 100
> +#define SRST_PMU_GPIO0_P 101
> +#define SRST_PMU_UART0_P 102
> +#define SRST_PMU_CRU_P 103
> +#define SRST_PMU_PVTM 104
> +#define SRST_PMU_UART 105
> +#define SRST_PMU_NIU_H 106
> +#define SRST_PMU_DDR_FAIL_SAVE 107
> +#define SRST_PMU_CORE_PERF_A 108
> +#define SRST_PMU_CORE_GRF_P 109
> +#define SRST_PMU_GPU_PERF_A 110
> +#define SRST_PMU_GPU_GRF_P 111
> +
> +#define SRST_CRYPTO_NIU_A 112
> +#define SRST_CRYPTO_NIU_H 113
> +#define SRST_CRYPTO_A 114
> +#define SRST_CRYPTO_H 115
> +#define SRST_CRYPTO 116
> +#define SRST_CRYPTO_APK 117
> +#define SRST_BUS_NIU_H 120
> +#define SRST_USB_NIU_P 121
> +#define SRST_BUS_TOP_NIU_P 122
> +#define SRST_INTMEM_A 123
> +#define SRST_GIC_A 124
> +#define SRST_ROM_H 126
> +#define SRST_DCF_A 127
> +
> +#define SRST_DCF_P 128
> +#define SRST_PDM_H 129
> +#define SRST_PDM 130
> +#define SRST_I2S0_H 131
> +#define SRST_I2S0_TX 132
> +#define SRST_I2S1_H 133
> +#define SRST_I2S1 134
> +#define SRST_I2S2_H 135
> +#define SRST_I2S2 136
> +#define SRST_UART1_P 137
> +#define SRST_UART1 138
> +#define SRST_UART2_P 139
> +#define SRST_UART2 140
> +#define SRST_UART3_P 141
> +#define SRST_UART3 142
> +#define SRST_UART4_P 143
> +
> +#define SRST_UART4 144
> +#define SRST_UART5_P 145
> +#define SRST_UART5 146
> +#define SRST_I2C0_P 147
> +#define SRST_I2C0 148
> +#define SRST_I2C1_P 149
> +#define SRST_I2C1 150
> +#define SRST_I2C2_P 151
> +#define SRST_I2C2 152
> +#define SRST_I2C3_P 153
> +#define SRST_I2C3 154
> +#define SRST_PWM0_P 157
> +#define SRST_PWM0 158
> +#define SRST_PWM1_P 159
> +
> +#define SRST_PWM1 160
> +#define SRST_SPI0_P 161
> +#define SRST_SPI0 162
> +#define SRST_SPI1_P 163
> +#define SRST_SPI1 164
> +#define SRST_SARADC_P 165
> +#define SRST_SARADC 166
> +#define SRST_TSADC_P 167
> +#define SRST_TSADC 168
> +#define SRST_TIMER_P 169
> +#define SRST_TIMER0 170
> +#define SRST_TIMER1 171
> +#define SRST_TIMER2 172
> +#define SRST_TIMER3 173
> +#define SRST_TIMER4 174
> +#define SRST_TIMER5 175
> +
> +#define SRST_OTP_NS_P 176
> +#define SRST_OTP_NS_SBPI 177
> +#define SRST_OTP_NS_USR 178
> +#define SRST_OTP_PHY_P 179
> +#define SRST_OTP_PHY 180
> +#define SRST_WDT_NS_P 181
> +#define SRST_GPIO1_P 182
> +#define SRST_GPIO2_P 183
> +#define SRST_GPIO3_P 184
> +#define SRST_SGRF_P 185
> +#define SRST_GRF_P 186
> +#define SRST_I2S0_RX 191
> +
> +#endif
> --
> 1.9.1
>
>
^ permalink raw reply
* [PATCH v2 2/5] dt: qcom: 8996: thermal: Move to DT initialisation
From: Bjorn Andersson @ 2018-06-12 19:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <683ceb9a7d283bcad47fc6e8e4fcfbd7e76c1018.1528799892.git.amit.kucheria@linaro.org>
On Tue 12 Jun 03:54 PDT 2018, Amit Kucheria wrote:
> We also split up the regmap address space into two, one for the TM
> registers, the other for the SROT registers. This was required to deal with
> different address offsets for the TM and SROT registers across different
> SoC families.
>
> Since tsens-common.c/init_common() currently only registers one address space, the order is important (TM before SROT).This is OK since the code doesn't really use the SROT functionality yet.
Please line wrap this.
>
> Signed-off-by: Amit Kucheria <amit.kucheria@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/msm8996.dtsi | 12 +++++++++++-
> drivers/thermal/qcom/tsens-8996.c | 1 -
> 2 files changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> index 410ae78..b4aab18 100644
> --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> @@ -451,7 +451,17 @@
>
> tsens0: thermal-sensor at 4a8000 {
> compatible = "qcom,msm8996-tsens";
> - reg = <0x4a8000 0x2000>;
> + reg = <0x4a9000 0x1000>, /* TM */
> + <0x4a8000 0x1000>; /* SROT */
> + #qcom,sensors = <13>;
> + #thermal-sensor-cells = <1>;
> + };
> +
> + tsens1: thermal-sensor at 4ac000 {
> + compatible = "qcom,msm8996-tsens";
> + reg = <0x4ad000 0x1000>, /* TM */
> + <0x4ac000 0x1000>; /* SROT */
> + #qcom,sensors = <8>;
> #thermal-sensor-cells = <1>;
> };
>
> diff --git a/drivers/thermal/qcom/tsens-8996.c b/drivers/thermal/qcom/tsens-8996.c
> index e1f7781..6e59078 100644
> --- a/drivers/thermal/qcom/tsens-8996.c
> +++ b/drivers/thermal/qcom/tsens-8996.c
> @@ -79,6 +79,5 @@ static const struct tsens_ops ops_8996 = {
> };
>
> const struct tsens_data data_8996 = {
> - .num_sensors = 13,
This will cause the current 8996 dts to fail probing the tsens. I think
you should just leave this as is, because specifying qcom,sensors in dts
will overwrite this number regardless.
It also would make this change dts specific, which is convenient as it
breaks the interdependency between the different subsystems.
> .ops = &ops_8996,
Regards,
Bjorn
^ permalink raw reply
* [PATCH v1 2/4] dt-bindings: mailbox: provide imx-mailbox documentation
From: Rob Herring @ 2018-06-12 19:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180601065821.28234-3-o.rempel@pengutronix.de>
On Fri, Jun 01, 2018 at 08:58:19AM +0200, Oleksij Rempel wrote:
> Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
> ---
> .../bindings/mailbox/imx-mailbox.txt | 35 +++++++++++++++++++
> 1 file changed, 35 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mailbox/imx-mailbox.txt
>
> diff --git a/Documentation/devicetree/bindings/mailbox/imx-mailbox.txt b/Documentation/devicetree/bindings/mailbox/imx-mailbox.txt
> new file mode 100644
> index 000000000000..a45604b33039
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mailbox/imx-mailbox.txt
> @@ -0,0 +1,35 @@
> +i.MX Messaging Unit
> +===================
> +
> +The i.MX Messaging Unit (MU) contains two register sets: "A" and "B". In most cases
> +they are accessible from all Processor Units. On one hand, at least for mailbox functionality,
> +it makes no difference which application or processor is using which set of the MU. On
Please wrap lines correctly (<80).
> +other hand, the register sets for each of the MU parts are not identical.
> +
> +Required properties:
> +- compatible : Shell be one of:
> + "fsl,imx7s-mu-a" and "fsl,imx7s-mu-b" for i.MX7S or i.MX7D
> +- reg : physical base address of the mailbox and length of
Mix of space and tab.
> + memory mapped region.
> +- #mbox-cells: Common mailbox binding property to identify the number
> + of cells required for the mailbox specifier. Should be 1.
> +- interrupts : interrupt number. The interrupt specifier format
> + depends on the interrupt controller parent.
Just need to say how many interrupts and what they are if more than 1.
> +- clocks : phandle to the input clock.
> +
> +Example:
> + mu0a: mu at 30aa0000 {
mailbox at ...
> + compatible = "fsl,imx7s-mu-a";
> + reg = <0x30aa0000 0x28>;
> + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX7D_MU_ROOT_CLK>;
> + #mbox-cells = <1>;
> + };
> +
> + mu0b: mu at 30ab0000 {
mailbox at ...
> + compatible = "fsl,imx7s-mu-b";
> + reg = <0x30ab0000 0x28>;
> + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clks IMX7D_MU_ROOT_CLK>;
> + #mbox-cells = <1>;
> + };
> --
> 2.17.1
>
^ permalink raw reply
* [PATCH v2 00/27] Add support for R40 HDMI pipeline
From: Jernej Skrabec @ 2018-06-12 20:00 UTC (permalink / raw)
To: linux-arm-kernel
This series adds support for R40 HDMI pipeline. It is a bit special
than other already supported pipelines because it has additional unit
called TCON TOP responsible for relationship configuration between
mixers, TCONs and HDMI. Additionally, it has additional gates for DSI
and TV TCONs, TV encoder clock settings and pin muxing between LCD
and TV encoders.
However, it seems that TCON TOP will become a norm, since newer
Allwinner SoCs like H6 also have this unit.
I tested different possible configurations:
- mixer0 <> TCON-TV0 <> HDMI
- mixer0 <> TCON-TV1 <> HDMI
- mixer1 <> TCON-TV0 <> HDMI
- mixer1 <> TCON-TV1 <> HDMI
Please review.
Best regards,
Jernej
Changes from v1:
- Split DT bindings patch and updated description
- Split HDMI PHY patch
- Move header file from TCON TOP patch to dt bindings patch
- Added Rob reviewed-by tag
- Used clk_hw_register_gate() instead of custom gate registration code
- Reworked TCON TOP to be part of of-graph. Because of that, a lot of
new patches were added.
- Droped mixer index quirk patch
- Reworked TCON support for TCON TOP
- Updated commit messages
Jernej Skrabec (27):
clk: sunxi-ng: r40: Add minimal rate for video PLLs
clk: sunxi-ng: r40: Allow setting parent rate to display related
clocks
clk: sunxi-ng: r40: Export video PLLs
dt-bindings: display: sunxi-drm: Add TCON TOP description
drm/sun4i: Add TCON TOP driver
drm/sun4i: Fix releasing node when enumerating enpoints
drm/sun4i: Split out code for enumerating endpoints in output port
drm/sun4i: Add support for traversing graph with TCON TOP
drm/sun4i: Don't skip TCONs if they don't have channel 0
dt-bindings: display: sun4i-drm: Add R40 TV TCON description
drm/sun4i: tcon: Add support for tcon-top gate
drm/sun4i: tcon: Generalize engine search algorithm
drm/sun4i: Don't check for LVDS and RGB when TCON has only ch1
drm/sun4i: Don't check for panel or bridge on TV TCONs
drm/sun4i: Add support for R40 TV TCON
dt-bindings: display: sun4i-drm: Add R40 mixer compatibles
drm/sun4i: Add support for R40 mixers
dt-bindings: display: sun4i-drm: Add description of A64 HDMI PHY
drm/sun4i: Enable DW HDMI PHY clock
drm/sun4i: Don't change clock bits in DW HDMI PHY driver
drm/sun4i: DW HDMI PHY: Add support for second PLL
drm/sun4i: Add support for second clock parent to DW HDMI PHY clk
driver
drm/sun4i: Add support for A64 HDMI PHY
drm: of: Export drm_crtc_port_mask()
drm/sun4i: DW HDMI: Expand algorithm for possible crtcs
ARM: dts: sun8i: r40: Add HDMI pipeline
ARM: dts: sun8i: r40: Enable HDMI output on BananaPi M2 Ultra
.../bindings/display/sunxi/sun4i-drm.txt | 56 +++-
.../boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 45 +++
arch/arm/boot/dts/sun8i-r40.dtsi | 257 ++++++++++++++++++
drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 58 ++--
drivers/clk/sunxi-ng/ccu-sun8i-r40.h | 8 +-
drivers/gpu/drm/drm_of.c | 4 +-
drivers/gpu/drm/sun4i/Makefile | 3 +-
drivers/gpu/drm/sun4i/sun4i_drv.c | 121 ++++++---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 83 ++++--
drivers/gpu/drm/sun4i/sun4i_tcon.h | 4 +
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 46 +++-
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 8 +-
drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 54 +++-
drivers/gpu/drm/sun4i/sun8i_hdmi_phy_clk.c | 90 ++++--
drivers/gpu/drm/sun4i/sun8i_mixer.c | 24 ++
drivers/gpu/drm/sun4i/sun8i_tcon_top.c | 248 +++++++++++++++++
drivers/gpu/drm/sun4i/sun8i_tcon_top.h | 38 +++
include/drm/drm_of.h | 8 +
include/dt-bindings/clock/sun8i-r40-ccu.h | 4 +
include/dt-bindings/clock/sun8i-tcon-top.h | 11 +
20 files changed, 1047 insertions(+), 123 deletions(-)
create mode 100644 drivers/gpu/drm/sun4i/sun8i_tcon_top.c
create mode 100644 drivers/gpu/drm/sun4i/sun8i_tcon_top.h
create mode 100644 include/dt-bindings/clock/sun8i-tcon-top.h
--
2.17.1
^ permalink raw reply
* [PATCH v2 01/27] clk: sunxi-ng: r40: Add minimal rate for video PLLs
From: Jernej Skrabec @ 2018-06-12 20:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180612200036.21483-1-jernej.skrabec@siol.net>
According to documentation and experience with other similar SoCs, video
PLLs don't work stable if their output frequency is set below 192 MHz.
Because of that, set minimal rate to both R40 video PLLs to 192 MHz.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 46 +++++++++++++++-------------
1 file changed, 24 insertions(+), 22 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
index 933f2e68f42a..c16a62a7bdbd 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
@@ -65,17 +65,18 @@ static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
CLK_SET_RATE_UNGATE);
/* TODO: The result of N/M is required to be in [8, 25] range. */
-static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0",
- "osc24M", 0x0010,
- 8, 7, /* N */
- 0, 4, /* M */
- BIT(24), /* frac enable */
- BIT(25), /* frac select */
- 270000000, /* frac rate 0 */
- 297000000, /* frac rate 1 */
- BIT(31), /* gate */
- BIT(28), /* lock */
- CLK_SET_RATE_UNGATE);
+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video0_clk, "pll-video0",
+ "osc24M", 0x0010,
+ 192000000, /* Minimum rate */
+ 8, 7, /* N */
+ 0, 4, /* M */
+ BIT(24), /* frac enable */
+ BIT(25), /* frac select */
+ 270000000, /* frac rate 0 */
+ 297000000, /* frac rate 1 */
+ BIT(31), /* gate */
+ BIT(28), /* lock */
+ CLK_SET_RATE_UNGATE);
/* TODO: The result of N/M is required to be in [8, 25] range. */
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
@@ -151,17 +152,18 @@ static struct ccu_nk pll_periph1_clk = {
};
/* TODO: The result of N/M is required to be in [8, 25] range. */
-static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1",
- "osc24M", 0x030,
- 8, 7, /* N */
- 0, 4, /* M */
- BIT(24), /* frac enable */
- BIT(25), /* frac select */
- 270000000, /* frac rate 0 */
- 297000000, /* frac rate 1 */
- BIT(31), /* gate */
- BIT(28), /* lock */
- CLK_SET_RATE_UNGATE);
+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video1_clk, "pll-video1",
+ "osc24M", 0x030,
+ 192000000, /* Minimum rate */
+ 8, 7, /* N */
+ 0, 4, /* M */
+ BIT(24), /* frac enable */
+ BIT(25), /* frac select */
+ 270000000, /* frac rate 0 */
+ 297000000, /* frac rate 1 */
+ BIT(31), /* gate */
+ BIT(28), /* lock */
+ CLK_SET_RATE_UNGATE);
static struct ccu_nkm pll_sata_clk = {
.enable = BIT(31),
--
2.17.1
^ permalink raw reply related
* [PATCH v2 02/27] clk: sunxi-ng: r40: Allow setting parent rate to display related clocks
From: Jernej Skrabec @ 2018-06-12 20:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180612200036.21483-1-jernej.skrabec@siol.net>
Display related peripherals need precise clocks to operate correctly.
Allow DE2, TCONs and HDMI to set parent clock.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
index c16a62a7bdbd..fa5317719684 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.c
@@ -655,7 +655,8 @@ static SUNXI_CCU_GATE(dram_deinterlace_clk, "dram-deinterlace", "dram",
static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
- 0x104, 0, 4, 24, 3, BIT(31), 0);
+ 0x104, 0, 4, 24, 3, BIT(31),
+ CLK_SET_RATE_PARENT);
static SUNXI_CCU_M_WITH_MUX_GATE(mp_clk, "mp", de_parents,
0x108, 0, 4, 24, 3, BIT(31), 0);
@@ -667,9 +668,11 @@ static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd0_clk, "tcon-lcd0", tcon_parents,
static SUNXI_CCU_MUX_WITH_GATE(tcon_lcd1_clk, "tcon-lcd1", tcon_parents,
0x114, 24, 3, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_M_WITH_MUX_GATE(tcon_tv0_clk, "tcon-tv0", tcon_parents,
- 0x118, 0, 4, 24, 3, BIT(31), 0);
+ 0x118, 0, 4, 24, 3, BIT(31),
+ CLK_SET_RATE_PARENT);
static SUNXI_CCU_M_WITH_MUX_GATE(tcon_tv1_clk, "tcon-tv1", tcon_parents,
- 0x11c, 0, 4, 24, 3, BIT(31), 0);
+ 0x11c, 0, 4, 24, 3, BIT(31),
+ CLK_SET_RATE_PARENT);
static const char * const deinterlace_parents[] = { "pll-periph0",
"pll-periph1" };
@@ -699,7 +702,8 @@ static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
static const char * const hdmi_parents[] = { "pll-video0", "pll-video1" };
static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
- 0x150, 0, 4, 24, 2, BIT(31), 0);
+ 0x150, 0, 4, 24, 2, BIT(31),
+ CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(hdmi_slow_clk, "hdmi-slow", "osc24M",
0x154, BIT(31), 0);
--
2.17.1
^ permalink raw reply related
* [PATCH v2 03/27] clk: sunxi-ng: r40: Export video PLLs
From: Jernej Skrabec @ 2018-06-12 20:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180612200036.21483-1-jernej.skrabec@siol.net>
Video PLLs need to be referenced in R40 DT as possible HDMI PHY parent.
Export them.
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/clk/sunxi-ng/ccu-sun8i-r40.h | 8 ++++++--
include/dt-bindings/clock/sun8i-r40-ccu.h | 4 ++++
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r40.h b/drivers/clk/sunxi-ng/ccu-sun8i-r40.h
index 0db8e1e97af8..db2a1243f9ff 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-r40.h
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-r40.h
@@ -25,7 +25,9 @@
#define CLK_PLL_AUDIO_2X 4
#define CLK_PLL_AUDIO_4X 5
#define CLK_PLL_AUDIO_8X 6
-#define CLK_PLL_VIDEO0 7
+
+/* PLL_VIDEO0 is exported */
+
#define CLK_PLL_VIDEO0_2X 8
#define CLK_PLL_VE 9
#define CLK_PLL_DDR0 10
@@ -34,7 +36,9 @@
#define CLK_PLL_PERIPH0_2X 13
#define CLK_PLL_PERIPH1 14
#define CLK_PLL_PERIPH1_2X 15
-#define CLK_PLL_VIDEO1 16
+
+/* PLL_VIDEO1 is exported */
+
#define CLK_PLL_VIDEO1_2X 17
#define CLK_PLL_SATA 18
#define CLK_PLL_SATA_OUT 19
diff --git a/include/dt-bindings/clock/sun8i-r40-ccu.h b/include/dt-bindings/clock/sun8i-r40-ccu.h
index 4fa5f69fc297..f9e15a235626 100644
--- a/include/dt-bindings/clock/sun8i-r40-ccu.h
+++ b/include/dt-bindings/clock/sun8i-r40-ccu.h
@@ -43,6 +43,10 @@
#ifndef _DT_BINDINGS_CLK_SUN8I_R40_H_
#define _DT_BINDINGS_CLK_SUN8I_R40_H_
+#define CLK_PLL_VIDEO0 7
+
+#define CLK_PLL_VIDEO1 16
+
#define CLK_CPU 24
#define CLK_BUS_MIPI_DSI 29
--
2.17.1
^ permalink raw reply related
* [PATCH v2 04/27] dt-bindings: display: sunxi-drm: Add TCON TOP description
From: Jernej Skrabec @ 2018-06-12 20:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180612200036.21483-1-jernej.skrabec@siol.net>
TCON TOP main purpose is to configure whole display pipeline. It
determines relationships between mixers and TCONs, selects source TCON
for HDMI, muxes LCD and TV encoder GPIO output, selects TV encoder
clock source and contains additional TV TCON and DSI gates.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
.../bindings/display/sunxi/sun4i-drm.txt | 45 +++++++++++++++++++
include/dt-bindings/clock/sun8i-tcon-top.h | 11 +++++
2 files changed, 56 insertions(+)
create mode 100644 include/dt-bindings/clock/sun8i-tcon-top.h
diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index 3346c1e2a7a0..ef64c589a4b3 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -187,6 +187,51 @@ And on the A23, A31, A31s and A33, you need one more clock line:
- 'lvds-alt': An alternative clock source, separate from the TCON channel 0
clock, that can be used to drive the LVDS clock
+TCON TOP
+--------
+
+TCON TOPs main purpose is to configure whole display pipeline. It determines
+relationships between mixers and TCONs, selects source TCON for HDMI, muxes
+LCD and TV encoder GPIO output, selects TV encoder clock source and contains
+additional TV TCON and DSI gates.
+
+It allows display pipeline to be configured in very different ways:
+
+ / LCD0/LVDS0
+ / TCON-LCD0
+ | \ MIPI DSI
+ mixer0 |
+ \ / TCON-LCD1 - LCD1/LVDS1
+ TCON-TOP
+ / \ TCON-TV0 - TVE0/RGB
+ mixer1 | \
+ | TCON-TOP - HDMI
+ | /
+ \ TCON-TV1 - TVE1/RGB
+
+Note that both TCON TOP references same physical unit.
+
+Required properties:
+ - compatible: value must be one of:
+ * allwinner,sun8i-r40-tcon-top
+ - reg: base address and size of the memory-mapped region.
+ - clocks: phandle to the clocks feeding the TCON TOP
+ * bus: TCON TOP interface clock
+ - clock-names: clock name mentioned above
+ - resets: phandle to the reset line driving the DRC
+ * rst: TCON TOP reset line
+ - reset-names: reset name mentioned above
+ - #clock-cells : must contain 1
+
+- ports: A ports node with endpoint definitions as defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt. The first port
+ should be the input for mixer0 mux. The second should be the output for that
+ mux. Third port should be input for mixer1 mux. Fourth port should be output
+ for mixer1 mux. Fifth port should be input for HDMI mux. Sixth port should
+ be output for it. All output endpoints should have reg property with the id
+ of the target TCON. All ports should have only one enpoint connected to
+ remote endpoint.
+
DRC
---
diff --git a/include/dt-bindings/clock/sun8i-tcon-top.h b/include/dt-bindings/clock/sun8i-tcon-top.h
new file mode 100644
index 000000000000..c05e92770402
--- /dev/null
+++ b/include/dt-bindings/clock/sun8i-tcon-top.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/* Copyright (C) 2018 Jernej Skrabec <jernej.skrabec@siol.net> */
+
+#ifndef _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_
+#define _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_
+
+#define CLK_BUS_TCON_TOP_DSI 0
+#define CLK_BUS_TCON_TOP_TV0 1
+#define CLK_BUS_TCON_TOP_TV1 2
+
+#endif /* _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_ */
--
2.17.1
^ permalink raw reply related
* [PATCH v2 05/27] drm/sun4i: Add TCON TOP driver
From: Jernej Skrabec @ 2018-06-12 20:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180612200036.21483-1-jernej.skrabec@siol.net>
As already described in DT binding, TCON TOP is responsible for
configuring display pipeline. In this initial driver focus is on HDMI
pipeline, so TVE and LCD configuration is not implemented.
Implemented features:
- HDMI source selection
- clock driver (TCON and DSI gating)
- connecting mixers and TCONS
Something similar also existed in previous SoCs, except that it was part
of first TCON.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/gpu/drm/sun4i/Makefile | 3 +-
drivers/gpu/drm/sun4i/sun8i_tcon_top.c | 248 +++++++++++++++++++++++++
drivers/gpu/drm/sun4i/sun8i_tcon_top.h | 38 ++++
3 files changed, 288 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/sun4i/sun8i_tcon_top.c
create mode 100644 drivers/gpu/drm/sun4i/sun8i_tcon_top.h
diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile
index 2589f4acd5ae..09fbfd6304ba 100644
--- a/drivers/gpu/drm/sun4i/Makefile
+++ b/drivers/gpu/drm/sun4i/Makefile
@@ -16,7 +16,8 @@ sun8i-drm-hdmi-y += sun8i_hdmi_phy_clk.o
sun8i-mixer-y += sun8i_mixer.o sun8i_ui_layer.o \
sun8i_vi_layer.o sun8i_ui_scaler.o \
- sun8i_vi_scaler.o sun8i_csc.o
+ sun8i_vi_scaler.o sun8i_csc.o \
+ sun8i_tcon_top.o
sun4i-tcon-y += sun4i_crtc.o
sun4i-tcon-y += sun4i_dotclock.o
diff --git a/drivers/gpu/drm/sun4i/sun8i_tcon_top.c b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
new file mode 100644
index 000000000000..60b17e893f08
--- /dev/null
+++ b/drivers/gpu/drm/sun4i/sun8i_tcon_top.c
@@ -0,0 +1,248 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright (c) 2018 Jernej Skrabec <jernej.skrabec@siol.net> */
+
+#include <drm/drmP.h>
+
+#include <dt-bindings/clock/sun8i-tcon-top.h>
+
+#include <linux/bitfield.h>
+#include <linux/component.h>
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/of_graph.h>
+#include <linux/platform_device.h>
+
+#include "sun8i_tcon_top.h"
+
+struct sun8i_tcon_top_gate {
+ const char *name;
+ u8 bit;
+ int index;
+};
+
+static const struct sun8i_tcon_top_gate gates[] = {
+ {"bus-tcon-top-dsi", TCON_TOP_TCON_DSI_GATE, CLK_BUS_TCON_TOP_DSI},
+ {"bus-tcon-top-tv0", TCON_TOP_TCON_TV0_GATE, CLK_BUS_TCON_TOP_TV0},
+ {"bus-tcon-top-tv1", TCON_TOP_TCON_TV1_GATE, CLK_BUS_TCON_TOP_TV1},
+};
+
+static int sun8i_tcon_top_get_connected_ep_id(struct device_node *node,
+ int port_id)
+{
+ struct device_node *ep, *remote, *port;
+ struct of_endpoint endpoint;
+
+ port = of_graph_get_port_by_id(node, port_id);
+ if (!port)
+ return -ENOENT;
+
+ for_each_available_child_of_node(port, ep) {
+ remote = of_graph_get_remote_port_parent(ep);
+ if (!remote)
+ continue;
+
+ if (of_device_is_available(remote)) {
+ of_graph_parse_endpoint(ep, &endpoint);
+
+ of_node_put(remote);
+
+ return endpoint.id;
+ }
+
+ of_node_put(remote);
+ }
+
+ return -ENOENT;
+}
+
+static int sun8i_tcon_top_bind(struct device *dev, struct device *master,
+ void *data)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct clk_hw_onecell_data *clk_data;
+ struct sun8i_tcon_top *tcon_top;
+ bool mixer0_unused = false;
+ struct resource *res;
+ void __iomem *regs;
+ const char *parent;
+ int ret, i, id;
+ u32 val;
+
+ tcon_top = devm_kzalloc(dev, sizeof(*tcon_top), GFP_KERNEL);
+ if (!tcon_top)
+ return -ENOMEM;
+
+ clk_data = devm_kzalloc(dev, sizeof(*clk_data) +
+ sizeof(*clk_data->hws) * CLK_NUM,
+ GFP_KERNEL);
+ if (!clk_data)
+ return -ENOMEM;
+ tcon_top->clk_data = clk_data;
+
+ spin_lock_init(&tcon_top->reg_lock);
+
+ tcon_top->rst = devm_reset_control_get(dev, "rst");
+ if (IS_ERR(tcon_top->rst)) {
+ dev_err(dev, "Couldn't get our reset line\n");
+ return PTR_ERR(tcon_top->rst);
+ }
+
+ tcon_top->bus = devm_clk_get(dev, "bus");
+ if (IS_ERR(tcon_top->bus)) {
+ dev_err(dev, "Couldn't get the bus clock\n");
+ return PTR_ERR(tcon_top->bus);
+ }
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ regs = devm_ioremap_resource(dev, res);
+ if (IS_ERR(regs))
+ return PTR_ERR(regs);
+
+ ret = reset_control_deassert(tcon_top->rst);
+ if (ret) {
+ dev_err(dev, "Could not deassert ctrl reset control\n");
+ return ret;
+ }
+
+ ret = clk_prepare_enable(tcon_top->bus);
+ if (ret) {
+ dev_err(dev, "Could not enable bus clock\n");
+ goto err_assert_reset;
+ }
+
+ val = 0;
+
+ /* check if HDMI mux output is connected */
+ if (sun8i_tcon_top_get_connected_ep_id(dev->of_node, 5) >= 0) {
+ /* find HDMI input endpoint id, if it is connected at all*/
+ id = sun8i_tcon_top_get_connected_ep_id(dev->of_node, 4);
+ if (id >= 0)
+ val = FIELD_PREP(TCON_TOP_HDMI_SRC_MSK, id + 1);
+ else
+ DRM_DEBUG_DRIVER("TCON TOP HDMI input is not connected\n");
+ } else {
+ DRM_DEBUG_DRIVER("TCON TOP HDMI output is not connected\n");
+ }
+
+ writel(val, regs + TCON_TOP_GATE_SRC_REG);
+
+ val = 0;
+
+ /* process mixer0 mux output */
+ id = sun8i_tcon_top_get_connected_ep_id(dev->of_node, 1);
+ if (id >= 0) {
+ val = FIELD_PREP(TCON_TOP_PORT_DE0_MSK, id);
+ } else {
+ DRM_DEBUG_DRIVER("TCON TOP mixer0 output is not connected\n");
+ mixer0_unused = true;
+ }
+
+ /* process mixer1 mux output */
+ id = sun8i_tcon_top_get_connected_ep_id(dev->of_node, 3);
+ if (id >= 0) {
+ val |= FIELD_PREP(TCON_TOP_PORT_DE1_MSK, id);
+
+ /*
+ * mixer0 mux has priority over mixer1 mux. We have to
+ * make sure mixer0 doesn't overtake TCON from mixer1.
+ */
+ if (mixer0_unused && id == 0)
+ val |= FIELD_PREP(TCON_TOP_PORT_DE0_MSK, 1);
+ } else {
+ DRM_DEBUG_DRIVER("TCON TOP mixer1 output is not connected\n");
+ }
+
+ writel(val, regs + TCON_TOP_PORT_SEL_REG);
+
+ parent = __clk_get_name(tcon_top->bus);
+
+ for (i = 0; i < CLK_NUM; i++) {
+ const struct sun8i_tcon_top_gate *gate = &gates[i];
+ struct clk_hw *hw;
+
+ hw = clk_hw_register_gate(dev, gate->name, parent, 0,
+ regs + TCON_TOP_GATE_SRC_REG,
+ gate->bit, 0, &tcon_top->reg_lock);
+ if (IS_ERR(hw)) {
+ ret = PTR_ERR(hw);
+ goto err_unregister_gates;
+ }
+
+ clk_data->hws[gate->index] = hw;
+ }
+
+ clk_data->num = CLK_NUM;
+
+ ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
+ clk_data);
+ if (ret)
+ goto err_unregister_gates;
+
+ dev_set_drvdata(dev, tcon_top);
+
+ return 0;
+
+err_unregister_gates:
+ for (i = 0; i < CLK_NUM; i++)
+ if (clk_data->hws[i])
+ clk_hw_unregister_gate(clk_data->hws[i]);
+ clk_disable_unprepare(tcon_top->bus);
+err_assert_reset:
+ reset_control_assert(tcon_top->rst);
+
+ return ret;
+}
+
+static void sun8i_tcon_top_unbind(struct device *dev, struct device *master,
+ void *data)
+{
+ struct sun8i_tcon_top *tcon_top = dev_get_drvdata(dev);
+ struct clk_hw_onecell_data *clk_data = tcon_top->clk_data;
+ int i;
+
+ of_clk_del_provider(dev->of_node);
+ for (i = 0; i < CLK_NUM; i++)
+ clk_hw_unregister_gate(clk_data->hws[i]);
+
+ clk_disable_unprepare(tcon_top->bus);
+ reset_control_assert(tcon_top->rst);
+}
+
+static const struct component_ops sun8i_tcon_top_ops = {
+ .bind = sun8i_tcon_top_bind,
+ .unbind = sun8i_tcon_top_unbind,
+};
+
+static int sun8i_tcon_top_probe(struct platform_device *pdev)
+{
+ return component_add(&pdev->dev, &sun8i_tcon_top_ops);
+}
+
+static int sun8i_tcon_top_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &sun8i_tcon_top_ops);
+
+ return 0;
+}
+
+/* sun4i_drv uses this list to check if a device node is a TCON TOP */
+const struct of_device_id sun8i_tcon_top_of_table[] = {
+ { .compatible = "allwinner,sun8i-r40-tcon-top" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, sun8i_tcon_top_of_table);
+EXPORT_SYMBOL(sun8i_tcon_top_of_table);
+
+static struct platform_driver sun8i_tcon_top_platform_driver = {
+ .probe = sun8i_tcon_top_probe,
+ .remove = sun8i_tcon_top_remove,
+ .driver = {
+ .name = "sun8i-tcon-top",
+ .of_match_table = sun8i_tcon_top_of_table,
+ },
+};
+module_platform_driver(sun8i_tcon_top_platform_driver);
+
+MODULE_AUTHOR("Jernej Skrabec <jernej.skrabec@siol.net>");
+MODULE_DESCRIPTION("Allwinner R40 TCON TOP driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/gpu/drm/sun4i/sun8i_tcon_top.h b/drivers/gpu/drm/sun4i/sun8i_tcon_top.h
new file mode 100644
index 000000000000..6cbb9f90d702
--- /dev/null
+++ b/drivers/gpu/drm/sun4i/sun8i_tcon_top.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/* Copyright (c) 2018 Jernej Skrabec <jernej.skrabec@siol.net> */
+
+#ifndef _SUN8I_TCON_TOP_H_
+#define _SUN8I_TCON_TOP_H_
+
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/reset.h>
+#include <linux/spinlock.h>
+
+#define TCON_TOP_PORT_SEL_REG 0x1C
+#define TCON_TOP_PORT_DE0_MSK GENMASK(1, 0)
+#define TCON_TOP_PORT_DE1_MSK GENMASK(5, 4)
+
+#define TCON_TOP_GATE_SRC_REG 0x20
+#define TCON_TOP_HDMI_SRC_MSK GENMASK(29, 28)
+#define TCON_TOP_TCON_TV1_GATE 24
+#define TCON_TOP_TCON_TV0_GATE 20
+#define TCON_TOP_TCON_DSI_GATE 16
+
+#define CLK_NUM 3
+
+struct sun8i_tcon_top {
+ struct clk *bus;
+ struct clk_hw_onecell_data *clk_data;
+ struct reset_control *rst;
+
+ /*
+ * spinlock is used for locking access to registers from different
+ * places - tcon driver and clk subsystem.
+ */
+ spinlock_t reg_lock;
+};
+
+extern const struct of_device_id sun8i_tcon_top_of_table[];
+
+#endif /* _SUN8I_TCON_TOP_H_ */
--
2.17.1
^ permalink raw reply related
* [PATCH v2 06/27] drm/sun4i: Fix releasing node when enumerating enpoints
From: Jernej Skrabec @ 2018-06-12 20:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180612200036.21483-1-jernej.skrabec@siol.net>
sun4i_drv_add_endpoints() has a memory leak since it uses of_node_put()
when remote is equal to NULL and does nothing when remote has a valid
pointer.
Invert the logic to fix memory leak.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/gpu/drm/sun4i/sun4i_drv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c b/drivers/gpu/drm/sun4i/sun4i_drv.c
index 50d19605c38f..e15fa2389e3f 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
@@ -283,7 +283,6 @@ static int sun4i_drv_add_endpoints(struct device *dev,
remote = of_graph_get_remote_port_parent(ep);
if (!remote) {
DRM_DEBUG_DRIVER("Error retrieving the output node\n");
- of_node_put(remote);
continue;
}
@@ -297,11 +296,13 @@ static int sun4i_drv_add_endpoints(struct device *dev,
if (of_graph_parse_endpoint(ep, &endpoint)) {
DRM_DEBUG_DRIVER("Couldn't parse endpoint\n");
+ of_node_put(remote);
continue;
}
if (!endpoint.id) {
DRM_DEBUG_DRIVER("Endpoint is our panel... skipping\n");
+ of_node_put(remote);
continue;
}
}
--
2.17.1
^ permalink raw reply related
* [PATCH v2 07/27] drm/sun4i: Split out code for enumerating endpoints in output port
From: Jernej Skrabec @ 2018-06-12 20:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180612200036.21483-1-jernej.skrabec@siol.net>
Until now, each node has one input port and one output port. However,
with TCON TOP this is no longer true. It has 3 input and 3 output ports.
In order to prepare to this situation, split out the code which checks
all endpoints in input port and adds available components to fifo.
This patch doesn't do any functional change.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/gpu/drm/sun4i/sun4i_drv.c | 84 +++++++++++++++++--------------
1 file changed, 46 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c b/drivers/gpu/drm/sun4i/sun4i_drv.c
index e15fa2389e3f..20193d6f33ba 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
@@ -231,12 +231,55 @@ struct endpoint_list {
DECLARE_KFIFO(fifo, struct device_node *, 16);
};
+static void sun4i_drv_traverse_endpoints(struct endpoint_list *list,
+ struct device_node *node,
+ int port_id)
+{
+ struct device_node *ep, *remote, *port;
+
+ port = of_graph_get_port_by_id(node, port_id);
+ if (!port) {
+ DRM_DEBUG_DRIVER("No output to bind on port %d\n", port_id);
+ return;
+ }
+
+ for_each_available_child_of_node(port, ep) {
+ remote = of_graph_get_remote_port_parent(ep);
+ if (!remote) {
+ DRM_DEBUG_DRIVER("Error retrieving the output node\n");
+ continue;
+ }
+
+ /*
+ * If the node is our TCON, the first port is used for
+ * panel or bridges, and will not be part of the
+ * component framework.
+ */
+ if (sun4i_drv_node_is_tcon(node)) {
+ struct of_endpoint endpoint;
+
+ if (of_graph_parse_endpoint(ep, &endpoint)) {
+ DRM_DEBUG_DRIVER("Couldn't parse endpoint\n");
+ of_node_put(remote);
+ continue;
+ }
+
+ if (!endpoint.id) {
+ DRM_DEBUG_DRIVER("Endpoint is our panel... skipping\n");
+ of_node_put(remote);
+ continue;
+ }
+ }
+
+ kfifo_put(&list->fifo, remote);
+ }
+}
+
static int sun4i_drv_add_endpoints(struct device *dev,
struct endpoint_list *list,
struct component_match **match,
struct device_node *node)
{
- struct device_node *port, *ep, *remote;
int count = 0;
/*
@@ -272,43 +315,8 @@ static int sun4i_drv_add_endpoints(struct device *dev,
count++;
}
- /* Inputs are listed first, then outputs */
- port = of_graph_get_port_by_id(node, 1);
- if (!port) {
- DRM_DEBUG_DRIVER("No output to bind\n");
- return count;
- }
-
- for_each_available_child_of_node(port, ep) {
- remote = of_graph_get_remote_port_parent(ep);
- if (!remote) {
- DRM_DEBUG_DRIVER("Error retrieving the output node\n");
- continue;
- }
-
- /*
- * If the node is our TCON, the first port is used for
- * panel or bridges, and will not be part of the
- * component framework.
- */
- if (sun4i_drv_node_is_tcon(node)) {
- struct of_endpoint endpoint;
-
- if (of_graph_parse_endpoint(ep, &endpoint)) {
- DRM_DEBUG_DRIVER("Couldn't parse endpoint\n");
- of_node_put(remote);
- continue;
- }
-
- if (!endpoint.id) {
- DRM_DEBUG_DRIVER("Endpoint is our panel... skipping\n");
- of_node_put(remote);
- continue;
- }
- }
-
- kfifo_put(&list->fifo, remote);
- }
+ /* each node has at least one output */
+ sun4i_drv_traverse_endpoints(list, node, 1);
return count;
}
--
2.17.1
^ permalink raw reply related
* [PATCH v2 08/27] drm/sun4i: Add support for traversing graph with TCON TOP
From: Jernej Skrabec @ 2018-06-12 20:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180612200036.21483-1-jernej.skrabec@siol.net>
TCON TOP is different from other nodes in graph by having 3 input and 3
output ports. Additionally, connection to TV TCON might lead back to
HDMI mux input port, creating loops.
Add support for traversing such graph.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/gpu/drm/sun4i/sun4i_drv.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c b/drivers/gpu/drm/sun4i/sun4i_drv.c
index 20193d6f33ba..e6c62c079146 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
@@ -26,6 +26,7 @@
#include "sun4i_frontend.h"
#include "sun4i_framebuffer.h"
#include "sun4i_tcon.h"
+#include "sun8i_tcon_top.h"
DEFINE_DRM_GEM_CMA_FOPS(sun4i_drv_fops);
@@ -197,6 +198,11 @@ static bool sun4i_drv_node_is_tcon(struct device_node *node)
return !!of_match_node(sun4i_tcon_of_table, node);
}
+static bool sun4i_drv_node_is_tcon_top(struct device_node *node)
+{
+ return !!of_match_node(sun8i_tcon_top_of_table, node);
+}
+
static int compare_of(struct device *dev, void *data)
{
DRM_DEBUG_DRIVER("Comparing of node %pOF with %pOF\n",
@@ -258,6 +264,18 @@ static void sun4i_drv_traverse_endpoints(struct endpoint_list *list,
if (sun4i_drv_node_is_tcon(node)) {
struct of_endpoint endpoint;
+ /*
+ * TCON TOP is always probed before TCON. However, TCON
+ * points back to TCON TOP when it is source for HDMI.
+ * We have to skip it here to prevent infinite looping
+ * between TCON TOP and TCON.
+ */
+ if (sun4i_drv_node_is_tcon_top(remote)) {
+ DRM_DEBUG_DRIVER("TCON output endpoint is TCON TOP... skipping\n");
+ of_node_put(remote);
+ continue;
+ }
+
if (of_graph_parse_endpoint(ep, &endpoint)) {
DRM_DEBUG_DRIVER("Couldn't parse endpoint\n");
of_node_put(remote);
@@ -318,6 +336,12 @@ static int sun4i_drv_add_endpoints(struct device *dev,
/* each node has at least one output */
sun4i_drv_traverse_endpoints(list, node, 1);
+ /* TCON TOP has second and third output */
+ if (sun4i_drv_node_is_tcon_top(node)) {
+ sun4i_drv_traverse_endpoints(list, node, 3);
+ sun4i_drv_traverse_endpoints(list, node, 5);
+ }
+
return count;
}
--
2.17.1
^ permalink raw reply related
* [PATCH v2 09/27] drm/sun4i: Don't skip TCONs if they don't have channel 0
From: Jernej Skrabec @ 2018-06-12 20:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180612200036.21483-1-jernej.skrabec@siol.net>
TV TCONs (channel 1 only) are always connected to TV or HDMI encoder.
Because of that, all output endpoints on such TCON node will point to a
encoder which is part of component framework.
Correct current graph traversing algorithm in such way that it doesn't
skip output enpoints with id 0 on TV TCONs.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/gpu/drm/sun4i/sun4i_drv.c | 52 +++++++++++++++++++++----------
1 file changed, 35 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c b/drivers/gpu/drm/sun4i/sun4i_drv.c
index e6c62c079146..6ddf4eaccb40 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
@@ -198,6 +198,22 @@ static bool sun4i_drv_node_is_tcon(struct device_node *node)
return !!of_match_node(sun4i_tcon_of_table, node);
}
+static bool sun4i_drv_node_is_tcon_with_ch0(struct device_node *node)
+{
+ const struct of_device_id *match;
+
+ match = of_match_node(sun4i_tcon_of_table, node);
+ if (match) {
+ struct sun4i_tcon_quirks *quirks;
+
+ quirks = (struct sun4i_tcon_quirks *)match->data;
+
+ return quirks->has_channel_0;
+ }
+
+ return false;
+}
+
static bool sun4i_drv_node_is_tcon_top(struct device_node *node)
{
return !!of_match_node(sun8i_tcon_top_of_table, node);
@@ -256,14 +272,7 @@ static void sun4i_drv_traverse_endpoints(struct endpoint_list *list,
continue;
}
- /*
- * If the node is our TCON, the first port is used for
- * panel or bridges, and will not be part of the
- * component framework.
- */
if (sun4i_drv_node_is_tcon(node)) {
- struct of_endpoint endpoint;
-
/*
* TCON TOP is always probed before TCON. However, TCON
* points back to TCON TOP when it is source for HDMI.
@@ -276,16 +285,25 @@ static void sun4i_drv_traverse_endpoints(struct endpoint_list *list,
continue;
}
- if (of_graph_parse_endpoint(ep, &endpoint)) {
- DRM_DEBUG_DRIVER("Couldn't parse endpoint\n");
- of_node_put(remote);
- continue;
- }
-
- if (!endpoint.id) {
- DRM_DEBUG_DRIVER("Endpoint is our panel... skipping\n");
- of_node_put(remote);
- continue;
+ /*
+ * If the node is our TCON with channel 0, the first
+ * port is used for panel or bridges, and will not be
+ * part of the component framework.
+ */
+ if (sun4i_drv_node_is_tcon_with_ch0(node)) {
+ struct of_endpoint endpoint;
+
+ if (of_graph_parse_endpoint(ep, &endpoint)) {
+ DRM_DEBUG_DRIVER("Couldn't parse endpoint\n");
+ of_node_put(remote);
+ continue;
+ }
+
+ if (!endpoint.id) {
+ DRM_DEBUG_DRIVER("Endpoint is our panel... skipping\n");
+ of_node_put(remote);
+ continue;
+ }
}
}
--
2.17.1
^ permalink raw reply related
* [PATCH v2 10/27] dt-bindings: display: sun4i-drm: Add R40 TV TCON description
From: Jernej Skrabec @ 2018-06-12 20:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180612200036.21483-1-jernej.skrabec@siol.net>
TCON description is expanded with R40 TV TCON compatibles. TV TCONs,
which are connected to TCON TOP muxes, such as those on R40 SoC, also
needs additional clock gate to be specified.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
.../devicetree/bindings/display/sunxi/sun4i-drm.txt | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index ef64c589a4b3..68c4b2995624 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -145,6 +145,7 @@ Required properties:
* allwinner,sun8i-a33-tcon
* allwinner,sun8i-a83t-tcon-lcd
* allwinner,sun8i-a83t-tcon-tv
+ * allwinner,sun8i-r40-tcon-tv
* allwinner,sun8i-v3s-tcon
* allwinner,sun9i-a80-tcon-lcd
* allwinner,sun9i-a80-tcon-tv
@@ -178,8 +179,10 @@ For TCONs with channel 0, there is one more clock required:
- 'tcon-ch0': The clock driving the TCON channel 0
For TCONs with channel 1, there is one more clock required:
- 'tcon-ch1': The clock driving the TCON channel 1
+TV TCONs which are connected to TCON TOP (found in R40 SoC) need one more clock:
+ - 'tcon-top': TV TCON gate found in TCON TOP unit
-When TCON support LVDS (all TCONs except TV TCON on A83T and those found
+When TCON support LVDS (all TCONs except TV TCONs on A83T, R40 and those found
in A13, H3, H5 and V3s SoCs), you need one more reset line:
- 'lvds': The reset line driving the LVDS logic
--
2.17.1
^ permalink raw reply related
* [PATCH v2 11/27] drm/sun4i: tcon: Add support for tcon-top gate
From: Jernej Skrabec @ 2018-06-12 20:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180612200036.21483-1-jernej.skrabec@siol.net>
TV TCONs connected to TCON TOP have to enable additional gate in order
to work.
Add support for such TCONs.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 11 +++++++++++
drivers/gpu/drm/sun4i/sun4i_tcon.h | 4 ++++
2 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index 08747fc3ee71..0afb5a94a414 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -688,6 +688,16 @@ static int sun4i_tcon_init_clocks(struct device *dev,
dev_err(dev, "Couldn't get the TCON bus clock\n");
return PTR_ERR(tcon->clk);
}
+
+ if (tcon->quirks->has_tcon_top_gate) {
+ tcon->top_clk = devm_clk_get(dev, "tcon-top");
+ if (IS_ERR(tcon->top_clk)) {
+ dev_err(dev, "Couldn't get the TCON TOP bus clock\n");
+ return PTR_ERR(tcon->top_clk);
+ }
+ clk_prepare_enable(tcon->top_clk);
+ }
+
clk_prepare_enable(tcon->clk);
if (tcon->quirks->has_channel_0) {
@@ -712,6 +722,7 @@ static int sun4i_tcon_init_clocks(struct device *dev,
static void sun4i_tcon_free_clocks(struct sun4i_tcon *tcon)
{
clk_disable_unprepare(tcon->clk);
+ clk_disable_unprepare(tcon->top_clk);
}
static int sun4i_tcon_init_irq(struct device *dev,
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h
index f6a071cd5a6f..652d5c37d7b4 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.h
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h
@@ -224,6 +224,7 @@ struct sun4i_tcon_quirks {
bool needs_de_be_mux; /* sun6i needs mux to select backend */
bool needs_edp_reset; /* a80 edp reset needed for tcon0 access */
bool supports_lvds; /* Does the TCON support an LVDS output? */
+ bool has_tcon_top_gate; /* TCON TOP holds additional gate to enable */
/* callback to handle tcon muxing options */
int (*set_mux)(struct sun4i_tcon *, const struct drm_encoder *);
@@ -249,6 +250,9 @@ struct sun4i_tcon {
u8 dclk_max_div;
u8 dclk_min_div;
+ /* TCON TOP clock */
+ struct clk *top_clk;
+
/* Reset control */
struct reset_control *lcd_rst;
struct reset_control *lvds_rst;
--
2.17.1
^ permalink raw reply related
* [PATCH v2 12/27] drm/sun4i: tcon: Generalize engine search algorithm
From: Jernej Skrabec @ 2018-06-12 20:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180612200036.21483-1-jernej.skrabec@siol.net>
Current "old" method to find engine worked pretty well for DE2. However,
it doesn't work when TCON TOP is between mixer (engine) and TCON. TCON
TOP has multiple input ports, but current engine search algorithm
expects only one.
This can be fixed by first looking for output port id and selecting
matching input by subtracting 1 for the next round. This work even if
there is only one input and output.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 22 ++++++++++++++++++----
1 file changed, 18 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index 0afb5a94a414..5dae623968f7 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -802,12 +802,14 @@ static int sun4i_tcon_init_regmap(struct device *dev,
*/
static struct sunxi_engine *
sun4i_tcon_find_engine_traverse(struct sun4i_drv *drv,
- struct device_node *node)
+ struct device_node *node,
+ u32 port_id)
{
struct device_node *port, *ep, *remote;
struct sunxi_engine *engine = ERR_PTR(-EINVAL);
+ u32 reg = 0;
- port = of_graph_get_port_by_id(node, 0);
+ port = of_graph_get_port_by_id(node, port_id);
if (!port)
return ERR_PTR(-EINVAL);
@@ -837,8 +839,20 @@ sun4i_tcon_find_engine_traverse(struct sun4i_drv *drv,
if (remote == engine->node)
goto out_put_remote;
+ /*
+ * According to device tree binding input ports have even id
+ * number and output ports have odd id. Since component with
+ * more than one input and one output (TCON TOP) exits, correct
+ * remote input id has to be calculated by subtracting 1 from
+ * remote output id. If this for some reason can't be done, 0
+ * is used as input port id.
+ */
+ port = of_graph_get_remote_port(ep);
+ if (!of_property_read_u32(port, "reg", ®) && reg > 0)
+ reg -= 1;
+
/* keep looking through upstream ports */
- engine = sun4i_tcon_find_engine_traverse(drv, remote);
+ engine = sun4i_tcon_find_engine_traverse(drv, remote, reg);
out_put_remote:
of_node_put(remote);
@@ -961,7 +975,7 @@ static struct sunxi_engine *sun4i_tcon_find_engine(struct sun4i_drv *drv,
/* Fallback to old method by traversing input endpoints */
of_node_put(port);
- return sun4i_tcon_find_engine_traverse(drv, node);
+ return sun4i_tcon_find_engine_traverse(drv, node, 0);
}
static int sun4i_tcon_bind(struct device *dev, struct device *master,
--
2.17.1
^ permalink raw reply related
* [PATCH v2 13/27] drm/sun4i: Don't check for LVDS and RGB when TCON has only ch1
From: Jernej Skrabec @ 2018-06-12 20:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180612200036.21483-1-jernej.skrabec@siol.net>
LVDS and RGB interfaces are always connected to TCONs which have channel
0. It doesn't make sense to try to init them on TV TCONs.
Add a check if TCON has channel 0 before trying to init LVDS or RGB
interface.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 32 ++++++++++++++++--------------
1 file changed, 17 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index 5dae623968f7..b1205a7bc20f 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -1117,23 +1117,25 @@ static int sun4i_tcon_bind(struct device *dev, struct device *master,
goto err_free_dotclock;
}
- /*
- * If we have an LVDS panel connected to the TCON, we should
- * just probe the LVDS connector. Otherwise, just probe RGB as
- * we used to.
- */
- remote = of_graph_get_remote_node(dev->of_node, 1, 0);
- if (of_device_is_compatible(remote, "panel-lvds"))
- if (can_lvds)
- ret = sun4i_lvds_init(drm, tcon);
+ if (tcon->quirks->has_channel_0) {
+ /*
+ * If we have an LVDS panel connected to the TCON, we should
+ * just probe the LVDS connector. Otherwise, just probe RGB as
+ * we used to.
+ */
+ remote = of_graph_get_remote_node(dev->of_node, 1, 0);
+ if (of_device_is_compatible(remote, "panel-lvds"))
+ if (can_lvds)
+ ret = sun4i_lvds_init(drm, tcon);
+ else
+ ret = -EINVAL;
else
- ret = -EINVAL;
- else
- ret = sun4i_rgb_init(drm, tcon);
- of_node_put(remote);
+ ret = sun4i_rgb_init(drm, tcon);
+ of_node_put(remote);
- if (ret < 0)
- goto err_free_dotclock;
+ if (ret < 0)
+ goto err_free_dotclock;
+ }
if (tcon->quirks->needs_de_be_mux) {
/*
--
2.17.1
^ permalink raw reply related
* [PATCH v2 14/27] drm/sun4i: Don't check for panel or bridge on TV TCONs
From: Jernej Skrabec @ 2018-06-12 20:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180612200036.21483-1-jernej.skrabec@siol.net>
TV TCONs are always connected to TV or HDMI encoder, so it doesn't make
sense to check if panel or bridge is connected to them.
Check if TCON has channel 0 and only then check for connected panel or
bridges.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index b1205a7bc20f..c9ffa5381185 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -1189,13 +1189,19 @@ static const struct component_ops sun4i_tcon_ops = {
static int sun4i_tcon_probe(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
+ const struct sun4i_tcon_quirks *quirks;
struct drm_bridge *bridge;
struct drm_panel *panel;
int ret;
- ret = drm_of_find_panel_or_bridge(node, 1, 0, &panel, &bridge);
- if (ret == -EPROBE_DEFER)
- return ret;
+ quirks = of_device_get_match_data(&pdev->dev);
+
+ /* panels and bridges are present only on TCONs with channel 0 */
+ if (quirks->has_channel_0) {
+ ret = drm_of_find_panel_or_bridge(node, 1, 0, &panel, &bridge);
+ if (ret == -EPROBE_DEFER)
+ return ret;
+ }
return component_add(&pdev->dev, &sun4i_tcon_ops);
}
--
2.17.1
^ permalink raw reply related
* [PATCH v2 15/27] drm/sun4i: Add support for R40 TV TCON
From: Jernej Skrabec @ 2018-06-12 20:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180612200036.21483-1-jernej.skrabec@siol.net>
R40 TV TCON is similar to the A83T TV TCON, except that it needs
additional gate to be enabled.
Add support for it.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index c9ffa5381185..f20da2aa2165 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -1326,6 +1326,11 @@ static const struct sun4i_tcon_quirks sun8i_a83t_tv_quirks = {
.has_channel_1 = true,
};
+static const struct sun4i_tcon_quirks sun8i_r40_tv_quirks = {
+ .has_channel_1 = true,
+ .has_tcon_top_gate = true,
+};
+
static const struct sun4i_tcon_quirks sun8i_v3s_quirks = {
.has_channel_0 = true,
};
@@ -1350,6 +1355,7 @@ const struct of_device_id sun4i_tcon_of_table[] = {
{ .compatible = "allwinner,sun8i-a33-tcon", .data = &sun8i_a33_quirks },
{ .compatible = "allwinner,sun8i-a83t-tcon-lcd", .data = &sun8i_a83t_lcd_quirks },
{ .compatible = "allwinner,sun8i-a83t-tcon-tv", .data = &sun8i_a83t_tv_quirks },
+ { .compatible = "allwinner,sun8i-r40-tcon-tv", .data = &sun8i_r40_tv_quirks },
{ .compatible = "allwinner,sun8i-v3s-tcon", .data = &sun8i_v3s_quirks },
{ .compatible = "allwinner,sun9i-a80-tcon-lcd", .data = &sun9i_a80_tcon_lcd_quirks },
{ .compatible = "allwinner,sun9i-a80-tcon-tv", .data = &sun9i_a80_tcon_tv_quirks },
--
2.17.1
^ permalink raw reply related
* [PATCH v2 16/27] dt-bindings: display: sun4i-drm: Add R40 mixer compatibles
From: Jernej Skrabec @ 2018-06-12 20:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180612200036.21483-1-jernej.skrabec@siol.net>
R40 DE2 mixers are similar to those found in A83T, except it needs
different clock settings.
Add a compatibles for them.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index 68c4b2995624..d84df6d808c2 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -358,6 +358,8 @@ Required properties:
* allwinner,sun8i-a83t-de2-mixer-0
* allwinner,sun8i-a83t-de2-mixer-1
* allwinner,sun8i-h3-de2-mixer-0
+ * allwinner,sun8i-r40-de2-mixer-0
+ * allwinner,sun8i-r40-de2-mixer-1
* allwinner,sun8i-v3s-de2-mixer
- reg: base address and size of the memory-mapped region.
- clocks: phandles to the clocks feeding the mixer
--
2.17.1
^ permalink raw reply related
* [PATCH v2 17/27] drm/sun4i: Add support for R40 mixers
From: Jernej Skrabec @ 2018-06-12 20:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180612200036.21483-1-jernej.skrabec@siol.net>
Both mixers have similar capabilities as others SoCs with DE2.
First mixer has 1 VI and 3 UI planes and supports HW scaling on all
planes.
Second mixer has 1 VI and 1 UI planes and also supports HW scaling on
all planes.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_mixer.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
index 126899d6f0d3..ee8febb25903 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
@@ -500,6 +500,22 @@ static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg = {
.vi_num = 1,
};
+static const struct sun8i_mixer_cfg sun8i_r40_mixer0_cfg = {
+ .ccsc = 0,
+ .mod_rate = 297000000,
+ .scaler_mask = 0xf,
+ .ui_num = 3,
+ .vi_num = 1,
+};
+
+static const struct sun8i_mixer_cfg sun8i_r40_mixer1_cfg = {
+ .ccsc = 1,
+ .mod_rate = 297000000,
+ .scaler_mask = 0x3,
+ .ui_num = 1,
+ .vi_num = 1,
+};
+
static const struct sun8i_mixer_cfg sun8i_v3s_mixer_cfg = {
.vi_num = 2,
.ui_num = 1,
@@ -521,6 +537,14 @@ static const struct of_device_id sun8i_mixer_of_table[] = {
.compatible = "allwinner,sun8i-h3-de2-mixer-0",
.data = &sun8i_h3_mixer0_cfg,
},
+ {
+ .compatible = "allwinner,sun8i-r40-de2-mixer-0",
+ .data = &sun8i_r40_mixer0_cfg,
+ },
+ {
+ .compatible = "allwinner,sun8i-r40-de2-mixer-1",
+ .data = &sun8i_r40_mixer1_cfg,
+ },
{
.compatible = "allwinner,sun8i-v3s-de2-mixer",
.data = &sun8i_v3s_mixer_cfg,
--
2.17.1
^ permalink raw reply related
* [PATCH v2 18/27] dt-bindings: display: sun4i-drm: Add description of A64 HDMI PHY
From: Jernej Skrabec @ 2018-06-12 20:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180612200036.21483-1-jernej.skrabec@siol.net>
A64 HDMI PHY is similar to H3 HDMI PHY except it has two possible PLL
clock parents. It is compatible to other HDMI PHYs, like that found in
R40.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index d84df6d808c2..6fb45c7a9ac8 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -101,6 +101,7 @@ DWC HDMI PHY
Required properties:
- compatible: value must be one of:
+ * allwinner,sun50i-a64-hdmi-phy
* allwinner,sun8i-a83t-hdmi-phy
* allwinner,sun8i-h3-hdmi-phy
- reg: base address and size of memory-mapped region
@@ -111,8 +112,9 @@ Required properties:
- resets: phandle to the reset controller driving the PHY
- reset-names: must be "phy"
-H3 HDMI PHY requires additional clock:
+H3 and A64 HDMI PHY require additional clocks:
- pll-0: parent of phy clock
+ - pll-1: second possible phy clock parent (A64 only)
TV Encoder
----------
--
2.17.1
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