* [PATCH 08/34] ARM: dts: r8a7744: Add SMP support
From: Simon Horman @ 2018-12-06 21:58 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: Simon Horman, Magnus Damm, linux-arm-kernel, Biju Das
In-Reply-To: <cover.1544125558.git.horms+renesas@verge.net.au>
From: Biju Das <biju.das@bp.renesas.com>
Add DT node for the Advanced Power Management Unit (APMU), add the
second CPU core, and use "renesas,apmu" as "enable-method".
Also add cpu1 phandle node to the PMU interrupt-affinity property.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7744.dtsi | 38 ++++++++++++++++++++++++++++++++------
1 file changed, 32 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index 4d4ddbaba456..2cb6d8fa2fa0 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -49,6 +49,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "renesas,apmu";
cpu0: cpu@0 {
device_type = "cpu";
@@ -69,6 +70,25 @@
< 375000 1000000>;
};
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <1>;
+ clock-frequency = <1500000000>;
+ clocks = <&cpg CPG_CORE R8A7744_CLK_Z>;
+ clock-latency = <300000>; /* 300 us */
+ power-domains = <&sysc R8A7744_PD_CA15_CPU1>;
+ next-level-cache = <&L2_CA15>;
+
+ /* kHz - uV - OPPs unknown yet */
+ operating-points = <1500000 1000000>,
+ <1312500 1000000>,
+ <1125000 1000000>,
+ < 937500 1000000>,
+ < 750000 1000000>,
+ < 375000 1000000>;
+ };
+
L2_CA15: cache-controller-0 {
compatible = "cache";
cache-unified;
@@ -96,7 +116,7 @@
compatible = "arm,cortex-a15-pmu";
interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-affinity = <&cpu0>;
+ interrupt-affinity = <&cpu0>, <&cpu1>;
};
/* External SCIF clock */
@@ -250,6 +270,12 @@
#reset-cells = <1>;
};
+ apmu@e6152000 {
+ compatible = "renesas,r8a7744-apmu", "renesas,apmu";
+ reg = <0 0xe6152000 0 0x188>;
+ cpus = <&cpu0 &cpu1>;
+ };
+
rst: reset-controller@e6160000 {
compatible = "renesas,r8a7744-rst";
reg = <0 0xe6160000 0 0x100>;
@@ -483,7 +509,7 @@
interrupt-controller;
reg = <0 0xf1001000 0 0x1000>, <0 0xf1002000 0 0x2000>,
<0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&cpg CPG_MOD 408>;
clock-names = "clk";
power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
@@ -520,10 +546,10 @@
timer {
compatible = "arm,armv7-timer";
- interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
- <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
/* External USB clock - can be overridden by the board */
--
2.11.0
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* [PATCH 05/34] ARM: dts: r8a7744: Add SYS-DMAC support
From: Simon Horman @ 2018-12-06 21:58 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: Simon Horman, Magnus Damm, linux-arm-kernel, Biju Das
In-Reply-To: <cover.1544125558.git.horms+renesas@verge.net.au>
From: Biju Das <biju.das@bp.renesas.com>
Describe SYS-DMAC0/1 in the R8A7744 device tree.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7744.dtsi | 66 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 66 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi
index f4d0abde3f56..732c5d71191c 100644
--- a/arch/arm/boot/dts/r8a7744.dtsi
+++ b/arch/arm/boot/dts/r8a7744.dtsi
@@ -215,6 +215,72 @@
/* placeholder */
};
+ dmac0: dma-controller@e6700000 {
+ compatible = "renesas,dmac-r8a7744",
+ "renesas,rcar-dmac";
+ reg = <0 0xe6700000 0 0x20000>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = <&cpg CPG_MOD 219>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+ resets = <&cpg 219>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
+
+ dmac1: dma-controller@e6720000 {
+ compatible = "renesas,dmac-r8a7744",
+ "renesas,rcar-dmac";
+ reg = <0 0xe6720000 0 0x20000>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = <&cpg CPG_MOD 218>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7744_PD_ALWAYS_ON>;
+ resets = <&cpg 218>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
+
avb: ethernet@e6800000 {
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
#address-cells = <1>;
--
2.11.0
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* [PATCH 02/34] ARM: dts: r8a7744-iwg20m: Add iWave RZ/G1N Qseven SOM
From: Simon Horman @ 2018-12-06 21:57 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: Simon Horman, Magnus Damm, linux-arm-kernel, Biju Das
In-Reply-To: <cover.1544125558.git.horms+renesas@verge.net.au>
From: Biju Das <biju.das@bp.renesas.com>
Add support for iWave RZ/G1N Qseven System On Module.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7744-iwg20m.dtsi | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
create mode 100644 arch/arm/boot/dts/r8a7744-iwg20m.dtsi
diff --git a/arch/arm/boot/dts/r8a7744-iwg20m.dtsi b/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
new file mode 100644
index 000000000000..6166ae053060
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7744-iwg20m.dtsi
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the iWave RZ/G1N Qseven SOM
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+
+#include "r8a7744.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ compatible = "iwave,g20m", "renesas,r8a7744";
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x40000000>;
+ };
+
+ reg_3p3v: 3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&extal_clk {
+ clock-frequency = <20000000>;
+};
--
2.11.0
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* [PATCH 04/34] ARM: dts: r8a7744-iwg20d-q7: Add support for iWave G20D-Q7 board based on RZ/G1N
From: Simon Horman @ 2018-12-06 21:57 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: Simon Horman, Magnus Damm, linux-arm-kernel, Biju Das
In-Reply-To: <cover.1544125558.git.horms+renesas@verge.net.au>
From: Biju Das <biju.das@bp.renesas.com>
Add support for iWave RainboW-G20D-Qseven board based on RZ/G1N.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/r8a7744-iwg20d-q7.dts | 15 +++++++++++++++
2 files changed, 16 insertions(+)
create mode 100644 arch/arm/boot/dts/r8a7744-iwg20d-q7.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index b0e966d625b9..aba5a25b7eac 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -829,6 +829,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
r8a7743-iwg20d-q7.dtb \
r8a7743-iwg20d-q7-dbcm-ca.dtb \
r8a7743-sk-rzg1m.dtb \
+ r8a7744-iwg20d-q7.dtb \
r8a7745-iwg22d-sodimm.dtb \
r8a7745-iwg22d-sodimm-dbhd-ca.dtb \
r8a7745-sk-rzg1e.dtb \
diff --git a/arch/arm/boot/dts/r8a7744-iwg20d-q7.dts b/arch/arm/boot/dts/r8a7744-iwg20d-q7.dts
new file mode 100644
index 000000000000..1fdac528f274
--- /dev/null
+++ b/arch/arm/boot/dts/r8a7744-iwg20d-q7.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the iWave-RZ/G1N Qseven board
+ *
+ * Copyright (C) 2018 Renesas Electronics Corp.
+ */
+
+/dts-v1/;
+#include "r8a7744-iwg20m.dtsi"
+#include "iwg20d-q7-common.dtsi"
+
+/ {
+ model = "iWave Systems RainboW-G20D-Qseven board based on RZ/G1N";
+ compatible = "iwave,g20d", "iwave,g20m", "renesas,r8a7744";
+};
--
2.11.0
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* [PATCH 01/34] ARM: dts: r8a7743: Remove legacy "renesas, rcar-thermal" compatibility
From: Simon Horman @ 2018-12-06 21:57 UTC (permalink / raw)
To: linux-renesas-soc
Cc: Simon Horman, Magnus Damm, Geert Uytterhoeven, linux-arm-kernel
In-Reply-To: <cover.1544125558.git.horms+renesas@verge.net.au>
From: Geert Uytterhoeven <geert+renesas@glider.be>
The thermal hardware description for the RZ/G1M SoC was added to its DTS
after the introduction of support for thermal zones, and included a
thermal-zones node from the beginning.
Hence there is no need to claim compatibility with
"renesas,rcar-thermal", which would be needed only for backwards
compatibility with kernels predating thermal zone support.
Fixes: 6c76b4f7d89e89f0 ("ARM: dts: r8a7743: Add thermal device to DT")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7743.dtsi | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index 24715f74ae08..3cc33f7ff7fe 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -348,8 +348,7 @@
thermal: thermal@e61f0000 {
compatible = "renesas,thermal-r8a7743",
- "renesas,rcar-gen2-thermal",
- "renesas,rcar-thermal";
+ "renesas,rcar-gen2-thermal";
reg = <0 0xe61f0000 0 0x10>, <0 0xe61f0100 0 0x38>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 522>;
--
2.11.0
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* [GIT PULL] Second Round of Renesas ARM Based SoC DT Updates for v4.21
From: Simon Horman @ 2018-12-06 21:58 UTC (permalink / raw)
To: arm
Cc: Arnd Bergmann, Kevin Hilman, Magnus Damm, linux-renesas-soc,
Olof Johansson, Simon Horman, linux-arm-kernel
Hi Olof, Hi Kevin, Hi Arnd,
Please consider these second round of Renesas ARM based SoC DT updates for v4.21.
This pull request is based on the previous round of
such requests, tagged as renesas-arm-dt-for-v4.21,
which you have already pulled.
The following changes since commit 673df60a880f060e3e94920c7b5f7a9ed8aa65f2:
ARM: dts: r9a06g032: Correct the GIC DT node name (2018-11-28 13:55:30 +0100)
are available in the git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-arm-dt2-for-v4.21
for you to fetch changes up to e259e04748e2798a747d9c363ded50514b15a7b9:
ARM: dts: r8a7744-iwg20m: Add SPI NOR support (2018-12-05 11:52:46 -0800)
----------------------------------------------------------------
Second Round of Renesas ARM Based SoC DT Updates for v4.21
* RZ/G1N (r8a7744) SoC
- Describe in DT: SYS-DMAC, GPIO, Ethernet AVB, SMP, [H]SCIF{A|B},
I2C, USB 2.0 and 3.0 hosts, USB-DMAC, HSUSB, RWDT, Audio, CAN, IRQC,
thermal, CMT, VIN, VSP, IPMMU, PMU, TPU, QSPI MSIOF, and PCIE
- iWave G20D-Q7 board
- Initial support
- Enable eMMC, SDHI and SPIO NOR support
- Add camera daughterboard
* RZ/G1M (r8a7743) SoC
- Remove legacy "renesas,rcar-thermal" compatibility
----------------------------------------------------------------
Biju Das (33):
ARM: dts: r8a7744-iwg20m: Add iWave RZ/G1N Qseven SOM
ARM: dts: r8a7744: Initial SoC device tree
ARM: dts: r8a7744-iwg20d-q7: Add support for iWave G20D-Q7 board based on RZ/G1N
ARM: dts: r8a7744: Add SYS-DMAC support
ARM: dts: r8a7744: Add GPIO support
ARM: dts: r8a7744: Add Ethernet AVB support
ARM: dts: r8a7744: Add SMP support
ARM: dts: r8a7744: Add [H]SCIF{A|B} support
ARM: dts: r8a7744: Add I2C and IIC support
ARM: dts: r8a7744: Add SDHI nodes
ARM: dts: r8a7744: Add MMC node
ARM: dts: r8a7744-iwg20m: Add eMMC support
ARM: dts: r8a7744-iwg20m: Enable SDHI0 controller
ARM: dts: r8a7744: USB 2.0 host support
ARM: dts: r8a7744: Add USB-DMAC and HSUSB device nodes
ARM: dts: r8a7744: Add RWDT node
ARM: dts: r8a7744: Add audio support
ARM: dts: r8a7744: Add CAN support
ARM: dts: r8a7744: Add IRQC support
ARM: dts: r8a7744: Add thermal device to DT
ARM: dts: r8a7744: Add CMT SoC specific support
ARM: dts: r8a7744: add VIN dt support
ARM: dts: r8a7744: Add VSP support
ARM: dts: r8a7744: Add IPMMU DT nodes
ARM: dts: r8a7744: Add PWM SoC support
ARM: dts: r8a7744: Add TPU support
ARM: dts: r8a7744-iwg20d-q7-dbcm-ca: Add device tree for camera DB
ARM: dts: r8a7744: Add QSPI support
ARM: dts: r8a7744: Add MSIOF[012] support
ARM: dts: r8a7744: Add xhci support
ARM: dts: r8a7744: Add PCIe Controller device node
ARM: dts: iwg20d-q7-common: Move cmt/rwdt node out of RZ/G1M SOM
ARM: dts: r8a7744-iwg20m: Add SPI NOR support
Geert Uytterhoeven (1):
ARM: dts: r8a7743: Remove legacy "renesas,rcar-thermal" compatibility
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/iwg20d-q7-common.dtsi | 9 +
arch/arm/boot/dts/r8a7743-iwg20m.dtsi | 9 -
arch/arm/boot/dts/r8a7743.dtsi | 3 +-
arch/arm/boot/dts/r8a7744-iwg20d-q7-dbcm-ca.dts | 17 +
arch/arm/boot/dts/r8a7744-iwg20d-q7.dts | 15 +
arch/arm/boot/dts/r8a7744-iwg20m.dtsi | 90 ++
arch/arm/boot/dts/r8a7744.dtsi | 1741 +++++++++++++++++++++++
8 files changed, 1875 insertions(+), 11 deletions(-)
create mode 100644 arch/arm/boot/dts/r8a7744-iwg20d-q7-dbcm-ca.dts
create mode 100644 arch/arm/boot/dts/r8a7744-iwg20d-q7.dts
create mode 100644 arch/arm/boot/dts/r8a7744-iwg20m.dtsi
create mode 100644 arch/arm/boot/dts/r8a7744.dtsi
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* [PATCH 1/1] ARM: shmobile: defconfig: Enable SII902X
From: Simon Horman @ 2018-12-06 21:57 UTC (permalink / raw)
To: linux-renesas-soc
Cc: Fabrizio Castro, Simon Horman, Magnus Damm, linux-arm-kernel
In-Reply-To: <cover.1544124535.git.horms+renesas@verge.net.au>
From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
The iwg23s board comes with the SiI9022ACNU HDMI transmitter,
this patch makes sure the corresponding driver gets built.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/configs/shmobile_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig
index d090022ca975..9e5a5ade6cab 100644
--- a/arch/arm/configs/shmobile_defconfig
+++ b/arch/arm/configs/shmobile_defconfig
@@ -142,6 +142,7 @@ CONFIG_DRM=y
CONFIG_DRM_RCAR_DU=y
CONFIG_DRM_RCAR_LVDS=y
CONFIG_DRM_DUMB_VGA_DAC=y
+CONFIG_DRM_SII902X=y
CONFIG_DRM_I2C_ADV7511=y
CONFIG_DRM_I2C_ADV7511_AUDIO=y
CONFIG_FB_SH_MOBILE_LCDC=y
--
2.11.0
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* [GIT PULL] Renesas ARM Based SoC Defconfig Updates for v4.21
From: Simon Horman @ 2018-12-06 21:57 UTC (permalink / raw)
To: arm
Cc: Arnd Bergmann, Kevin Hilman, Magnus Damm, linux-renesas-soc,
Olof Johansson, Simon Horman, linux-arm-kernel
Hi Olof, Hi Kevin, Hi Arnd,
Please consider these Renesas ARM based SoC defconfig updates for v4.21.
The following changes since commit 651022382c7f8da46cb4872a545ee1da6d097d2a:
Linux 4.20-rc1 (2018-11-04 15:37:52 -0800)
are available in the git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-arm-defconfig-for-v4.21
for you to fetch changes up to 65a8c17a39f62fd646950fa43efcced0d6fe029c:
ARM: shmobile: defconfig: Enable SII902X (2018-11-05 12:41:09 +0100)
----------------------------------------------------------------
Renesas ARM Based SoC Defconfig Updates for v4.21
* Enable SII902X in shmobile defconfig
----------------------------------------------------------------
Fabrizio Castro (1):
ARM: shmobile: defconfig: Enable SII902X
arch/arm/configs/shmobile_defconfig | 1 +
1 file changed, 1 insertion(+)
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* [GIT PULL] Second Round of Renesas ARM64 Based SoC DT Updates for v4.21
From: Simon Horman @ 2018-12-06 21:57 UTC (permalink / raw)
To: arm
Cc: Arnd Bergmann, Kevin Hilman, Magnus Damm, linux-renesas-soc,
Olof Johansson, Simon Horman, linux-arm-kernel
Hi Olof, Hi Kevin, Hi Arnd,
Please consider these second round of Renesas ARM64 based SoC DT updates
for v4.21.
This pull request is based on the previous round of
such requests, tagged as renesas-arm64-dt-for-v4.21,
which you have already pulled.
The following changes since commit 275e4eb3f21a09b6b8bd4a353b9a01e500240385:
arm64: dts: renesas: Add all CPUs in cooling maps (2018-11-26 09:11:44 +0100)
are available in the git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-arm64-dt2-for-v4.21
for you to fetch changes up to 4fbd4158fe8967e9296516ebae2cfaf7a1c7a214:
arm64: dts: renesas: r8a77995: draak: Add backlight (2018-12-05 11:45:44 -0800)
----------------------------------------------------------------
Second Round of Renesas ARM64 Based SoC DT Updates for v4.21
* R-Car D3 (r8a77995) SoC based Draak board
- Add the backlight device for the LVDS1 output
* R-Car H3 (r8a7795) ES1.0 SoC
- Add missing power domains to IPMMU nodes
* R-Car M3-N (r8a77965) SoC
- Remove non-existent IPMMU-IR
----------------------------------------------------------------
Geert Uytterhoeven (2):
arm64: dts: renesas: r8a77965: Remove non-existent IPMMU-IR
arm64: dts: renesas: r8a7795-es1: Add missing power domains to IPMMU nodes
Laurent Pinchart (1):
arm64: dts: renesas: r8a77995: draak: Add backlight
arch/arm64/boot/dts/renesas/r8a7795-es1.dtsi | 2 ++
arch/arm64/boot/dts/renesas/r8a77965.dtsi | 8 --------
arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 20 ++++++++++++++++++++
3 files changed, 22 insertions(+), 8 deletions(-)
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* [PATCH 3/3] arm64: dts: renesas: r8a77995: draak: Add backlight
From: Simon Horman @ 2018-12-06 21:57 UTC (permalink / raw)
To: linux-renesas-soc
Cc: Simon Horman, Laurent Pinchart, Magnus Damm, linux-arm-kernel
In-Reply-To: <cover.1544126426.git.horms+renesas@verge.net.au>
From: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Add the backlight device for the LVDS1 output, in preparation for panel
support.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a77995-draak.dts | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
index 48bb1d77744f..52d044b9f3f2 100644
--- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts
@@ -24,6 +24,17 @@
stdout-path = "serial0:115200n8";
};
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm1 0 50000>;
+
+ brightness-levels = <256 128 64 16 8 4 0>;
+ default-brightness-level = <6>;
+
+ power-supply = <®_12p0v>;
+ enable-gpios = <&gpio4 0 GPIO_ACTIVE_HIGH>;
+ };
+
composite-in {
compatible = "composite-video-connector";
@@ -104,6 +115,15 @@
regulator-always-on;
};
+ reg_12p0v: regulator1 {
+ compatible = "regulator-fixed";
+ regulator-name = "D12.0V";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
vga {
compatible = "vga-connector";
--
2.11.0
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^ permalink raw reply related
* [PATCH 2/3] arm64: defconfig: Enable scu-simple-card driver
From: Simon Horman @ 2018-12-06 21:57 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: Simon Horman, Magnus Damm, linux-arm-kernel
In-Reply-To: <cover.1544126077.git.horms+renesas@verge.net.au>
Enable the scu-simple-card which is used by
the R-Car E3 (r8a77990) based Ebisu board.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index f88190463481..9d0b42d96f03 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -491,6 +491,7 @@ CONFIG_SND_SOC_RT5514=m
CONFIG_SND_SOC_RT5514_SPI=m
CONFIG_SND_SOC_RT5645=m
CONFIG_SND_SIMPLE_CARD=m
+CONFIG_SND_SIMPLE_SCU_CARD=y
CONFIG_SND_AUDIO_GRAPH_CARD=m
CONFIG_I2C_HID=m
CONFIG_USB=y
--
2.11.0
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* [PATCH 3/3] arm64: defconfig: Enable CONFIG_PHY_RCAR_GEN3_PCIE
From: Simon Horman @ 2018-12-06 21:57 UTC (permalink / raw)
To: linux-renesas-soc
Cc: Simon Horman, Magnus Damm, Geert Uytterhoeven, linux-arm-kernel
In-Reply-To: <cover.1544126077.git.horms+renesas@verge.net.au>
From: Geert Uytterhoeven <geert+renesas@glider.be>
Enable R-Car Gen3 PCIe PHY support, which is needed for PCIe to function
on the Renesas Condor board.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 9d0b42d96f03..77f98a7e860b 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -657,6 +657,7 @@ CONFIG_PHY_HISI_INNO_USB2=y
CONFIG_PHY_MVEBU_CP110_COMPHY=y
CONFIG_PHY_QCOM_QMP=m
CONFIG_PHY_QCOM_USB_HS=y
+CONFIG_PHY_RCAR_GEN3_PCIE=y
CONFIG_PHY_RCAR_GEN3_USB2=y
CONFIG_PHY_RCAR_GEN3_USB3=m
CONFIG_PHY_ROCKCHIP_EMMC=y
--
2.11.0
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^ permalink raw reply related
* [PATCH 1/3] arm64: defconfig: Enable R-Car thermal driver
From: Simon Horman @ 2018-12-06 21:57 UTC (permalink / raw)
To: linux-renesas-soc; +Cc: Simon Horman, Magnus Damm, linux-arm-kernel
In-Reply-To: <cover.1544126077.git.horms+renesas@verge.net.au>
Enable the R-Car thermal driver as a module.
This driver is used in conjunction with the R-Car V3M (r8a77970),
E3 (r8a77990) and D3 (r8a77995) SoCs.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index c9a57d11330b..f88190463481 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -377,6 +377,7 @@ CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
CONFIG_CPU_THERMAL=y
CONFIG_THERMAL_EMULATION=y
CONFIG_ROCKCHIP_THERMAL=m
+CONFIG_RCAR_THERMAL=m
CONFIG_RCAR_GEN3_THERMAL=y
CONFIG_ARMADA_THERMAL=y
CONFIG_BRCMSTB_THERMAL=m
--
2.11.0
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^ permalink raw reply related
* [GIT PULL] Renesas ARM64 Based SoC Defconfig Updates for v4.21
From: Simon Horman @ 2018-12-06 21:57 UTC (permalink / raw)
To: arm
Cc: Arnd Bergmann, Kevin Hilman, Magnus Damm, linux-renesas-soc,
Olof Johansson, Simon Horman, linux-arm-kernel
Hi Olof, Hi Kevin, Hi Arnd,
Please consider these Renesas ARM64 based SoC defconfig updates for v4.21.
The following changes since commit 651022382c7f8da46cb4872a545ee1da6d097d2a:
Linux 4.20-rc1 (2018-11-04 15:37:52 -0800)
are available in the git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-arm64-defconfig-for-v4.21
for you to fetch changes up to fe16bcd6d44f1a2bccc4618119463d9d23a6ae92:
arm64: defconfig: Enable CONFIG_PHY_RCAR_GEN3_PCIE (2018-11-16 06:56:49 -0800)
----------------------------------------------------------------
Renesas ARM64 Based SoC Defconfig Updates for v4.21
* Enable in arm64 defconfig:
- Renesas R-Car Gen3 PCIe PHY driver
- Renesas R-Car thermal driver
- ASoC simple SCU sound card support
----------------------------------------------------------------
Geert Uytterhoeven (1):
arm64: defconfig: Enable CONFIG_PHY_RCAR_GEN3_PCIE
Simon Horman (2):
arm64: defconfig: Enable R-Car thermal driver
arm64: defconfig: Enable scu-simple-card driver
arch/arm64/configs/defconfig | 3 +++
1 file changed, 3 insertions(+)
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^ permalink raw reply
* Re: [PATCH v10 5/7] interconnect: qcom: Add sdm845 interconnect provider driver
From: David Dai @ 2018-12-06 21:53 UTC (permalink / raw)
To: Georgi Djakov, Evan Green
Cc: mark.rutland, sanjayc, maxime.ripard, Michael Turquette,
Bjorn Andersson, Saravana Kannan, Alexandre Bailon,
lorenzo.pieralisi, Vincent Guittot, seansw, khilman, ksitaraman,
devicetree, Arnd Bergmann, linux-pm, linux-arm-msm, robh+dt,
linux-tegra, linux-arm-kernel, gregkh, rjw, linux-kernel,
amit.kucheria, thierry.reding
In-Reply-To: <cfcb39ba-860c-5a3f-911f-ab52b5250390@linaro.org>
On 12/5/2018 8:00 AM, Georgi Djakov wrote:
> Hi Evan,
>
> On 12/1/18 02:39, Evan Green wrote:
>> On Tue, Nov 27, 2018 at 10:04 AM Georgi Djakov <georgi.djakov@linaro.org> wrote:
>>> From: David Dai <daidavid1@codeaurora.org>
>>>
>>> Introduce Qualcomm SDM845 specific provider driver using the
>>> interconnect framework.
>>>
>>> Signed-off-by: David Dai <daidavid1@codeaurora.org>
>>> Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
>>> ---
>>> .../bindings/interconnect/qcom,sdm845.txt | 24 +
>>> drivers/interconnect/Kconfig | 5 +
>>> drivers/interconnect/Makefile | 1 +
>>> drivers/interconnect/qcom/Kconfig | 13 +
>>> drivers/interconnect/qcom/Makefile | 5 +
>>> drivers/interconnect/qcom/sdm845.c | 836 ++++++++++++++++++
>>> .../dt-bindings/interconnect/qcom,sdm845.h | 143 +++
>>> 7 files changed, 1027 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,sdm845.txt
>>> create mode 100644 drivers/interconnect/qcom/Kconfig
>>> create mode 100644 drivers/interconnect/qcom/Makefile
>>> create mode 100644 drivers/interconnect/qcom/sdm845.c
>>> create mode 100644 include/dt-bindings/interconnect/qcom,sdm845.h
>>>
>>> diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sdm845.txt b/Documentation/devicetree/bindings/interconnect/qcom,sdm845.txt
>>> new file mode 100644
>>> index 000000000000..d45150e99665
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/interconnect/qcom,sdm845.txt
>>> @@ -0,0 +1,24 @@
>>> +Qualcomm SDM845 Network-On-Chip interconnect driver binding
>>> +-----------------------------------------------------------
>>> +
>>> +SDM845 interconnect providers support system bandwidth requirements through
>>> +RPMh hardware accelerators known as Bus Clock Manager(BCM). The provider is able
>>> +to communicate with the BCM through the Resource State Coordinator(RSC)
>>> +associated with each execution environment. Provider nodes must reside within
>>> +an RPMh device node pertaining to their RSC and each provider maps to
>>> +a single RPMh resource.
>>> +
>>> +Required properties :
>>> +- compatible : shall contain only one of the following:
>>> + "qcom,sdm845-rsc-hlos"
>> I wonder if maybe hlos isn't necessary. Unless you somehow imagine
>> secure mode would have a device tree entry in here as well? Probably
>> not.
> Ok, will remove it. David, please chime in if you have any concerns with
> this.
No strong preferences in terms of naming, but need to make the
distinction between this and potential other rsc types if we're to add
additional provider drivers.
>>> +- #interconnect-cells : should contain 1
>>> +
>>> +Examples:
>>> +
>>> +apps_rsc: rsc {
>>> + qnoc: qnoc-rsc-hlos {
>>> + compatible = "qcom,sdm845-rsc-hlos";
>>> + #interconnect-cells = <1>;
>>> + };
>>> +};
>>> +
>> ...
>>> diff --git a/drivers/interconnect/qcom/sdm845.c b/drivers/interconnect/qcom/sdm845.c
>>> new file mode 100644
>>> index 000000000000..1678de91ca52
>>> --- /dev/null
>>> +++ b/drivers/interconnect/qcom/sdm845.c
>>> @@ -0,0 +1,836 @@
>> ...
>>> +
>>> +static void tcs_list_gen(struct list_head *bcm_list,
>>> + struct tcs_cmd *tcs_list, int *n)
>> We could make the prototype of this function be:
>>
>> static void tcs_list_gen(struct list_head *bcm_list,
>> struct tcs_cmd tcs_list[SDM845_MAX_VCD], int n[SDM845_MAX_VCD])
>>
>> which would catch errors if somebody later passed in an array that
>> wasn't the right size, since we blindly memset below.
> Yes, sounds good. I will try to optimize it.
>
> Thanks,
> Georgi
>
>>> +{
>>> + struct qcom_icc_bcm *bcm;
>>> + bool commit;
>>> + size_t idx = 0, batch = 0, cur_vcd_size = 0;
>>> +
>>> + memset(n, 0, sizeof(int) * SDM845_MAX_VCD);
>>> +
>>> + list_for_each_entry(bcm, bcm_list, list) {
>>> + commit = false;
>>> + cur_vcd_size++;
>>> + if ((list_is_last(&bcm->list, bcm_list)) ||
>>> + bcm->aux_data.vcd != list_next_entry(bcm, list)->aux_data.vcd) {
>>> + commit = true;
>>> + cur_vcd_size = 0;
>>> + }
>>> + tcs_cmd_gen(&tcs_list[idx], bcm->vote_x, bcm->vote_y,
>>> + bcm->addr, commit);
>>> + idx++;
>>> + n[batch]++;
>>> + /*
>>> + * Batch the BCMs in such a way that we do not split them in
>>> + * multiple payloads when they are under the same VCD. This is
>>> + * to ensure that every BCM is committed since we only set the
>>> + * commit bit on the last BCM request of every VCD.
>>> + */
>>> + if (n[batch] >= MAX_RPMH_PAYLOAD) {
>>> + if (!commit) {
>>> + n[batch] -= cur_vcd_size;
>>> + n[batch + 1] = cur_vcd_size;
>>> + }
>>> + batch++;
>>> + }
>>> + }
>>> +}
>>> +
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
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^ permalink raw reply
* Re: [PATCH] PCI: controller: dwc: Make PCI_IMX6 depend on PCIEPORTBUS
From: Robert Hancock @ 2018-12-06 21:41 UTC (permalink / raw)
To: Lucas Stach, Baruch Siach, Andrey Smirnov
Cc: A.s. Dong, Richard Zhu, linux-pci, linux-kernel, linux-imx,
bhelgaas, Leonard Crestez, cphealy, linux-arm-kernel,
Trent Piepho
In-Reply-To: <ff33ed91-431d-9620-da75-216298a58667@sedsystems.ca>
On 2018-12-06 10:10 a.m., Robert Hancock wrote:
> On 2018-12-06 9:50 a.m., Lucas Stach wrote:
>> Am Donnerstag, den 06.12.2018, 09:45 -0600 schrieb Robert Hancock:
>>> On 2018-12-06 2:10 a.m., Baruch Siach wrote:
>>>> Hi Andrey,
>>>>
>>>> Adding Robert Hancock who reported[1] on a PCIe MSI issue with i.MX6.
>>>>
>>>> Andrey Smirnov writes:
>>>>
>>>>> Building a kernel with CONFIG_PCI_IMX6=y, but CONFIG_PCIEPORTBUS=n
>>>>> produces a system where built-in PCIE bridge (16c3:abcd) isn't bound
>>>>> to pcieport driver. This, in turn, results in a PCIE bus that is
>>>>> capable of enumerating attached PCIE device, but lacks functional
>>>>> interrupt support.
>>>>
>>>> Robert, does that fix your issue?
>>>
>>> Unfortunately, no.. in fact the situation on my setup is even worse with
>>> CONFIG_PCIEPORTBUS enabled: Not only does MSI still not function, but
>>> now INTx interrupts are somehow broken as well - no interrupts are
>>> received. The IRQ information shown in /proc/interrupts is correct, but
>>> the count remains stubbornly at 0.
>>
>> That's expected. The port services will use an MSI IRQ when available
>> and due to a design issue with the DWC PCIe it will not forward any
>> legacy IRQs if any MSI is in use. If any of the PCIe devices in your
>> system are unable to work with MSI IRQs, you must boot with "nomsi" on
>> the kernel command line set.
>
> That seems like an unfortunate design choice on their part.. well that
> would probably argue against adding this as a hard dependency then, if
> non-MSI-supporting PCIe devices can't work with default boot options
> with that set.
>
> I'm looking into testing with an NXP Smart Devices board and some PCIe
> cards to see if I can verify whether MSI works on those or not, since we
> currently don't have a way to independently verify that the MSI
> implementation in our FPGA is working or whether another PCIe device
> works with MSI (the FPGA is integrated on the system board).
I've now done some tests with a NXP SabreSD reference board and an Intel
wireless card:
-With the standard imx_v6_v7 defconfig, MSI does not work, INTx works
-With CONFIG_PCIEPORTBUS=y, MSI does work
So it seems like enabling PCIEPORTBUS should fix our MSI issue on the
CPU side, and our remaining problem is likely on the FPGA device side.
However, there's still the issue that enabling that option breaks INTx
support - I don't have a PCIe card handy that the kernel doesn't enable
MSI for in order to test that on the Sabre board, but based on Lucas's
comment and my results on our board, it definitely seems to be an issue.
I would hope there must be a way to handle that..
--
Robert Hancock
Senior Software Developer
SED Systems
Email: hancock@sedsystems.ca
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^ permalink raw reply
* Re: [PATCH v2 5/6] arch: simplify several early memory allocations
From: Mike Rapoport @ 2018-12-06 21:30 UTC (permalink / raw)
To: Sam Ravnborg
Cc: Michal Hocko, linux-sh, Benjamin Herrenschmidt, linux-mm,
Rich Felker, Paul Mackerras, sparclinux, Vincent Chen, Jonas Bonn,
linux-c6x-dev, Yoshinori Sato, Michael Ellerman, Russell King,
Mark Salter, Arnd Bergmann, Stefan Kristiansson, openrisc,
Greentime Hu, Stafford Horne, Guan Xuetao, linux-arm-kernel,
Michal Simek, linux-kernel, Andrew Morton, linuxppc-dev,
David S. Miller
In-Reply-To: <20181206180826.GB19166@ravnborg.org>
On Thu, Dec 06, 2018 at 07:08:26PM +0100, Sam Ravnborg wrote:
> On Mon, Dec 03, 2018 at 06:49:21PM +0200, Mike Rapoport wrote:
> > On Mon, Dec 03, 2018 at 05:29:08PM +0100, Sam Ravnborg wrote:
> > > Hi Mike.
> > >
> > > > index c37955d..2a17665 100644
> > > > --- a/arch/sparc/kernel/prom_64.c
> > > > +++ b/arch/sparc/kernel/prom_64.c
> > > > @@ -34,16 +34,13 @@
> > > >
> > > > void * __init prom_early_alloc(unsigned long size)
> > > > {
> > > > - unsigned long paddr = memblock_phys_alloc(size, SMP_CACHE_BYTES);
> > > > - void *ret;
> > > > + void *ret = memblock_alloc(size, SMP_CACHE_BYTES);
> > > >
> > > > - if (!paddr) {
> > > > + if (!ret) {
> > > > prom_printf("prom_early_alloc(%lu) failed\n", size);
> > > > prom_halt();
> > > > }
> > > >
> > > > - ret = __va(paddr);
> > > > - memset(ret, 0, size);
> > > > prom_early_allocated += size;
> > > >
> > > > return ret;
> > >
> > > memblock_alloc() calls memblock_alloc_try_nid().
> > > And if allocation fails then memblock_alloc_try_nid() calls panic().
> > > So will we ever hit the prom_halt() code?
> >
> > memblock_phys_alloc_try_nid() also calls panic if an allocation fails. So
> > in either case we never reach prom_halt() code.
>
> So we have code here we never reach - not nice.
> If the idea is to avoid relying on the panic inside memblock_alloc() then
> maybe replace it with a variant that do not call panic?
> To make it clear what happens.
My plan is to completely remove memblock variants that call panic() and
make the callers check the return value.
I've started to work on it, but with the holidays it progresses slower than
I'd like to.
Since the code here was unreachable for several year, a few more weeks
won't make real difference so I'd prefer to keep the variant with panic()
for now.
> Sam
>
--
Sincerely yours,
Mike.
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* [PATCH 57/75] perf cs-etm: Add configuration for ETMv3 trace protocol
From: Arnaldo Carvalho de Melo @ 2018-12-06 21:25 UTC (permalink / raw)
To: Ingo Molnar
Cc: Arnaldo Carvalho de Melo, Mathieu Poirier, Clark Williams,
coresight, linux-kernel, linux-perf-users, Alexander Shishkin,
Peter Zijlstra, Namhyung Kim, Jiri Olsa, linux-arm-kernel
In-Reply-To: <20181206212602.20474-1-acme@kernel.org>
From: Mathieu Poirier <mathieu.poirier@linaro.org>
This patch deals with the proper initialisation of configuration
parameters for the ETMv3 trace protocol in order to properly handle
packets generated by tracers following this specification.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: coresight@lists.linaro.org
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/1543955944-10042-2-git-send-email-mathieu.poirier@linaro.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
.../perf/util/cs-etm-decoder/cs-etm-decoder.h | 8 +++
tools/perf/util/cs-etm.c | 54 ++++++++++++++-----
2 files changed, 48 insertions(+), 14 deletions(-)
diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h
index 9351bd10d864..6b5525410a43 100644
--- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h
+++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h
@@ -53,6 +53,13 @@ struct cs_etm_queue;
typedef u32 (*cs_etm_mem_cb_type)(struct cs_etm_queue *, u64,
size_t, u8 *);
+struct cs_etmv3_trace_params {
+ u32 reg_ctrl;
+ u32 reg_trc_id;
+ u32 reg_ccer;
+ u32 reg_idr;
+};
+
struct cs_etmv4_trace_params {
u32 reg_idr0;
u32 reg_idr1;
@@ -65,6 +72,7 @@ struct cs_etmv4_trace_params {
struct cs_etm_trace_params {
int protocol;
union {
+ struct cs_etmv3_trace_params etmv3;
struct cs_etmv4_trace_params etmv4;
};
};
diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c
index 48ad217bf0df..76e509c32a28 100644
--- a/tools/perf/util/cs-etm.c
+++ b/tools/perf/util/cs-etm.c
@@ -114,15 +114,28 @@ static void cs_etm__dump_event(struct cs_etm_auxtrace *etm,
/* Use metadata to fill in trace parameters for trace decoder */
t_params = zalloc(sizeof(*t_params) * etm->num_cpu);
for (i = 0; i < etm->num_cpu; i++) {
- t_params[i].protocol = CS_ETM_PROTO_ETMV4i;
- t_params[i].etmv4.reg_idr0 = etm->metadata[i][CS_ETMV4_TRCIDR0];
- t_params[i].etmv4.reg_idr1 = etm->metadata[i][CS_ETMV4_TRCIDR1];
- t_params[i].etmv4.reg_idr2 = etm->metadata[i][CS_ETMV4_TRCIDR2];
- t_params[i].etmv4.reg_idr8 = etm->metadata[i][CS_ETMV4_TRCIDR8];
- t_params[i].etmv4.reg_configr =
+ if (etm->metadata[i][CS_ETM_MAGIC] == __perf_cs_etmv3_magic) {
+ t_params[i].protocol = CS_ETM_PROTO_ETMV3;
+ t_params[i].etmv3.reg_ctrl =
+ etm->metadata[i][CS_ETM_ETMCR];
+ t_params[i].etmv3.reg_trc_id =
+ etm->metadata[i][CS_ETM_ETMTRACEIDR];
+ } else if (etm->metadata[i][CS_ETM_MAGIC] ==
+ __perf_cs_etmv4_magic) {
+ t_params[i].protocol = CS_ETM_PROTO_ETMV4i;
+ t_params[i].etmv4.reg_idr0 =
+ etm->metadata[i][CS_ETMV4_TRCIDR0];
+ t_params[i].etmv4.reg_idr1 =
+ etm->metadata[i][CS_ETMV4_TRCIDR1];
+ t_params[i].etmv4.reg_idr2 =
+ etm->metadata[i][CS_ETMV4_TRCIDR2];
+ t_params[i].etmv4.reg_idr8 =
+ etm->metadata[i][CS_ETMV4_TRCIDR8];
+ t_params[i].etmv4.reg_configr =
etm->metadata[i][CS_ETMV4_TRCCONFIGR];
- t_params[i].etmv4.reg_traceidr =
+ t_params[i].etmv4.reg_traceidr =
etm->metadata[i][CS_ETMV4_TRCTRACEIDR];
+ }
}
/* Set decoder parameters to simply print the trace packets */
@@ -352,15 +365,28 @@ static struct cs_etm_queue *cs_etm__alloc_queue(struct cs_etm_auxtrace *etm,
goto out_free;
for (i = 0; i < etm->num_cpu; i++) {
- t_params[i].protocol = CS_ETM_PROTO_ETMV4i;
- t_params[i].etmv4.reg_idr0 = etm->metadata[i][CS_ETMV4_TRCIDR0];
- t_params[i].etmv4.reg_idr1 = etm->metadata[i][CS_ETMV4_TRCIDR1];
- t_params[i].etmv4.reg_idr2 = etm->metadata[i][CS_ETMV4_TRCIDR2];
- t_params[i].etmv4.reg_idr8 = etm->metadata[i][CS_ETMV4_TRCIDR8];
- t_params[i].etmv4.reg_configr =
+ if (etm->metadata[i][CS_ETM_MAGIC] == __perf_cs_etmv3_magic) {
+ t_params[i].protocol = CS_ETM_PROTO_ETMV3;
+ t_params[i].etmv3.reg_ctrl =
+ etm->metadata[i][CS_ETM_ETMCR];
+ t_params[i].etmv3.reg_trc_id =
+ etm->metadata[i][CS_ETM_ETMTRACEIDR];
+ } else if (etm->metadata[i][CS_ETM_MAGIC] ==
+ __perf_cs_etmv4_magic) {
+ t_params[i].protocol = CS_ETM_PROTO_ETMV4i;
+ t_params[i].etmv4.reg_idr0 =
+ etm->metadata[i][CS_ETMV4_TRCIDR0];
+ t_params[i].etmv4.reg_idr1 =
+ etm->metadata[i][CS_ETMV4_TRCIDR1];
+ t_params[i].etmv4.reg_idr2 =
+ etm->metadata[i][CS_ETMV4_TRCIDR2];
+ t_params[i].etmv4.reg_idr8 =
+ etm->metadata[i][CS_ETMV4_TRCIDR8];
+ t_params[i].etmv4.reg_configr =
etm->metadata[i][CS_ETMV4_TRCCONFIGR];
- t_params[i].etmv4.reg_traceidr =
+ t_params[i].etmv4.reg_traceidr =
etm->metadata[i][CS_ETMV4_TRCTRACEIDR];
+ }
}
/* Set decoder parameters to simply print the trace packets */
--
2.19.2
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* [PATCH 58/75] perf cs-etm: Add support for ETMv3 trace decoding
From: Arnaldo Carvalho de Melo @ 2018-12-06 21:25 UTC (permalink / raw)
To: Ingo Molnar
Cc: Arnaldo Carvalho de Melo, Mathieu Poirier, Clark Williams,
coresight, linux-kernel, linux-perf-users, Alexander Shishkin,
Peter Zijlstra, Namhyung Kim, Jiri Olsa, linux-arm-kernel
In-Reply-To: <20181206212602.20474-1-acme@kernel.org>
From: Mathieu Poirier <mathieu.poirier@linaro.org>
Add support for the creation of packet printer and decoder for the ETMv3
trace architecture. That way traces generated by tracers adhering to
that trace protocol can be handled properly by the perf infrastructure.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: coresight@lists.linaro.org
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/1543955944-10042-3-git-send-email-mathieu.poirier@linaro.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
.../perf/util/cs-etm-decoder/cs-etm-decoder.c | 25 +++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c
index 5efb616bd609..952d1f43f3fa 100644
--- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c
+++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c
@@ -116,6 +116,19 @@ int cs_etm_decoder__get_packet(struct cs_etm_decoder *decoder,
return 1;
}
+static int cs_etm_decoder__gen_etmv3_config(struct cs_etm_trace_params *params,
+ ocsd_etmv3_cfg *config)
+{
+ config->reg_idr = params->etmv3.reg_idr;
+ config->reg_ctrl = params->etmv3.reg_ctrl;
+ config->reg_ccer = params->etmv3.reg_ccer;
+ config->reg_trc_id = params->etmv3.reg_trc_id;
+ config->arch_ver = ARCH_V7;
+ config->core_prof = profile_CortexA;
+
+ return 0;
+}
+
static void cs_etm_decoder__gen_etmv4_config(struct cs_etm_trace_params *params,
ocsd_etmv4_cfg *config)
{
@@ -237,10 +250,16 @@ cs_etm_decoder__create_etm_packet_printer(struct cs_etm_trace_params *t_params,
struct cs_etm_decoder *decoder)
{
const char *decoder_name;
+ ocsd_etmv3_cfg config_etmv3;
ocsd_etmv4_cfg trace_config_etmv4;
void *trace_config;
switch (t_params->protocol) {
+ case CS_ETM_PROTO_ETMV3:
+ cs_etm_decoder__gen_etmv3_config(t_params, &config_etmv3);
+ decoder_name = OCSD_BUILTIN_DCD_ETMV3;
+ trace_config = &config_etmv3;
+ break;
case CS_ETM_PROTO_ETMV4i:
cs_etm_decoder__gen_etmv4_config(t_params, &trace_config_etmv4);
decoder_name = OCSD_BUILTIN_DCD_ETMV4I;
@@ -427,11 +446,17 @@ static int cs_etm_decoder__create_etm_packet_decoder(
struct cs_etm_decoder *decoder)
{
const char *decoder_name;
+ ocsd_etmv3_cfg config_etmv3;
ocsd_etmv4_cfg trace_config_etmv4;
void *trace_config;
u8 csid;
switch (t_params->protocol) {
+ case CS_ETM_PROTO_ETMV3:
+ cs_etm_decoder__gen_etmv3_config(t_params, &config_etmv3);
+ decoder_name = OCSD_BUILTIN_DCD_ETMV3;
+ trace_config = &config_etmv3;
+ break;
case CS_ETM_PROTO_ETMV4i:
cs_etm_decoder__gen_etmv4_config(t_params, &trace_config_etmv4);
decoder_name = OCSD_BUILTIN_DCD_ETMV4I;
--
2.19.2
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* [PATCH 59/75] perf cs-etm: Add support for PTMv1.1 decoding
From: Arnaldo Carvalho de Melo @ 2018-12-06 21:25 UTC (permalink / raw)
To: Ingo Molnar
Cc: Arnaldo Carvalho de Melo, Mathieu Poirier, Clark Williams,
coresight, linux-kernel, linux-perf-users, Alexander Shishkin,
Peter Zijlstra, Namhyung Kim, Jiri Olsa, linux-arm-kernel
In-Reply-To: <20181206212602.20474-1-acme@kernel.org>
From: Mathieu Poirier <mathieu.poirier@linaro.org>
This patch is re-using the mechanic set forth by ETMv3 to add support
for PTM decoding. Configuration for both encoding protocol is similar
but the generated stream itself is very different, hence requiring
special handling.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: coresight@lists.linaro.org
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/1543955944-10042-4-git-send-email-mathieu.poirier@linaro.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
.../perf/util/cs-etm-decoder/cs-etm-decoder.c | 10 ++++++--
.../perf/util/cs-etm-decoder/cs-etm-decoder.h | 1 +
tools/perf/util/cs-etm.c | 23 +++++++++++++++++--
3 files changed, 30 insertions(+), 4 deletions(-)
diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c
index 952d1f43f3fa..0b4c8629f578 100644
--- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c
+++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c
@@ -256,8 +256,11 @@ cs_etm_decoder__create_etm_packet_printer(struct cs_etm_trace_params *t_params,
switch (t_params->protocol) {
case CS_ETM_PROTO_ETMV3:
+ case CS_ETM_PROTO_PTM:
cs_etm_decoder__gen_etmv3_config(t_params, &config_etmv3);
- decoder_name = OCSD_BUILTIN_DCD_ETMV3;
+ decoder_name = (t_params->protocol == CS_ETM_PROTO_ETMV3) ?
+ OCSD_BUILTIN_DCD_ETMV3 :
+ OCSD_BUILTIN_DCD_PTM;
trace_config = &config_etmv3;
break;
case CS_ETM_PROTO_ETMV4i:
@@ -453,8 +456,11 @@ static int cs_etm_decoder__create_etm_packet_decoder(
switch (t_params->protocol) {
case CS_ETM_PROTO_ETMV3:
+ case CS_ETM_PROTO_PTM:
cs_etm_decoder__gen_etmv3_config(t_params, &config_etmv3);
- decoder_name = OCSD_BUILTIN_DCD_ETMV3;
+ decoder_name = (t_params->protocol == CS_ETM_PROTO_ETMV3) ?
+ OCSD_BUILTIN_DCD_ETMV3 :
+ OCSD_BUILTIN_DCD_PTM;
trace_config = &config_etmv3;
break;
case CS_ETM_PROTO_ETMV4i:
diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h
index 6b5525410a43..b295dd2b8292 100644
--- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h
+++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h
@@ -96,6 +96,7 @@ enum {
CS_ETM_PROTO_ETMV3 = 1,
CS_ETM_PROTO_ETMV4i,
CS_ETM_PROTO_ETMV4d,
+ CS_ETM_PROTO_PTM,
};
enum {
diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c
index 76e509c32a28..23159c33db2a 100644
--- a/tools/perf/util/cs-etm.c
+++ b/tools/perf/util/cs-etm.c
@@ -83,6 +83,19 @@ static int cs_etm__update_queues(struct cs_etm_auxtrace *etm);
static int cs_etm__process_timeless_queues(struct cs_etm_auxtrace *etm,
pid_t tid, u64 time_);
+/* PTMs ETMIDR [11:8] set to b0011 */
+#define ETMIDR_PTM_VERSION 0x00000300
+
+static u32 cs_etm__get_v7_protocol_version(u32 etmidr)
+{
+ etmidr &= ETMIDR_PTM_VERSION;
+
+ if (etmidr == ETMIDR_PTM_VERSION)
+ return CS_ETM_PROTO_PTM;
+
+ return CS_ETM_PROTO_ETMV3;
+}
+
static void cs_etm__packet_dump(const char *pkt_string)
{
const char *color = PERF_COLOR_BLUE;
@@ -115,7 +128,10 @@ static void cs_etm__dump_event(struct cs_etm_auxtrace *etm,
t_params = zalloc(sizeof(*t_params) * etm->num_cpu);
for (i = 0; i < etm->num_cpu; i++) {
if (etm->metadata[i][CS_ETM_MAGIC] == __perf_cs_etmv3_magic) {
- t_params[i].protocol = CS_ETM_PROTO_ETMV3;
+ u32 etmidr = etm->metadata[i][CS_ETM_ETMIDR];
+
+ t_params[i].protocol =
+ cs_etm__get_v7_protocol_version(etmidr);
t_params[i].etmv3.reg_ctrl =
etm->metadata[i][CS_ETM_ETMCR];
t_params[i].etmv3.reg_trc_id =
@@ -366,7 +382,10 @@ static struct cs_etm_queue *cs_etm__alloc_queue(struct cs_etm_auxtrace *etm,
for (i = 0; i < etm->num_cpu; i++) {
if (etm->metadata[i][CS_ETM_MAGIC] == __perf_cs_etmv3_magic) {
- t_params[i].protocol = CS_ETM_PROTO_ETMV3;
+ u32 etmidr = etm->metadata[i][CS_ETM_ETMIDR];
+
+ t_params[i].protocol =
+ cs_etm__get_v7_protocol_version(etmidr);
t_params[i].etmv3.reg_ctrl =
etm->metadata[i][CS_ETM_ETMCR];
t_params[i].etmv3.reg_trc_id =
--
2.19.2
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* [PATCH 35/75] perf cs-etm: Support for ARM A32/T32 instruction sets in CoreSight trace
From: Arnaldo Carvalho de Melo @ 2018-12-06 21:25 UTC (permalink / raw)
To: Ingo Molnar
Cc: Arnaldo Carvalho de Melo, Clark Williams, coresight, linux-kernel,
linux-perf-users, Alexander Shishkin, Peter Zijlstra,
Namhyung Kim, Robert Walker, Jiri Olsa, linux-arm-kernel
In-Reply-To: <20181206212602.20474-1-acme@kernel.org>
From: Robert Walker <robert.walker@arm.com>
This patch adds support for generating instruction samples from trace of
AArch32 programs using the A32 and T32 instruction sets.
T32 has variable 2 or 4 byte instruction size, so the conversion between
addresses and instruction counts requires extra information from the
trace decoder, requiring version 0.10.0 of OpenCSD. A check for the
OpenCSD library version has been added to the feature check for OpenCSD.
Signed-off-by: Robert Walker <robert.walker@arm.com>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Tested-by: Leo Yan <leo.yan@linaro.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: coresight@lists.linaro.org
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/1543839526-30348-1-git-send-email-robert.walker@arm.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
---
tools/build/feature/test-libopencsd.c | 8 +++
.../perf/util/cs-etm-decoder/cs-etm-decoder.c | 29 ++++++++
.../perf/util/cs-etm-decoder/cs-etm-decoder.h | 10 +++
tools/perf/util/cs-etm.c | 70 ++++++++-----------
4 files changed, 78 insertions(+), 39 deletions(-)
diff --git a/tools/build/feature/test-libopencsd.c b/tools/build/feature/test-libopencsd.c
index 5ff1246e6194..d68eb4fb40cc 100644
--- a/tools/build/feature/test-libopencsd.c
+++ b/tools/build/feature/test-libopencsd.c
@@ -1,6 +1,14 @@
// SPDX-License-Identifier: GPL-2.0
#include <opencsd/c_api/opencsd_c_api.h>
+/*
+ * Check OpenCSD library version is sufficient to provide required features
+ */
+#define OCSD_MIN_VER ((0 << 16) | (10 << 8) | (0))
+#if !defined(OCSD_VER_NUM) || (OCSD_VER_NUM < OCSD_MIN_VER)
+#error "OpenCSD >= 0.10.0 is required"
+#endif
+
int main(void)
{
(void)ocsd_get_version();
diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c
index 938def6d0bb9..5efb616bd609 100644
--- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c
+++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.c
@@ -263,9 +263,12 @@ static void cs_etm_decoder__clear_buffer(struct cs_etm_decoder *decoder)
decoder->tail = 0;
decoder->packet_count = 0;
for (i = 0; i < MAX_BUFFER; i++) {
+ decoder->packet_buffer[i].isa = CS_ETM_ISA_UNKNOWN;
decoder->packet_buffer[i].start_addr = CS_ETM_INVAL_ADDR;
decoder->packet_buffer[i].end_addr = CS_ETM_INVAL_ADDR;
+ decoder->packet_buffer[i].instr_count = 0;
decoder->packet_buffer[i].last_instr_taken_branch = false;
+ decoder->packet_buffer[i].last_instr_size = 0;
decoder->packet_buffer[i].exc = false;
decoder->packet_buffer[i].exc_ret = false;
decoder->packet_buffer[i].cpu = INT_MIN;
@@ -294,11 +297,15 @@ cs_etm_decoder__buffer_packet(struct cs_etm_decoder *decoder,
decoder->packet_count++;
decoder->packet_buffer[et].sample_type = sample_type;
+ decoder->packet_buffer[et].isa = CS_ETM_ISA_UNKNOWN;
decoder->packet_buffer[et].exc = false;
decoder->packet_buffer[et].exc_ret = false;
decoder->packet_buffer[et].cpu = *((int *)inode->priv);
decoder->packet_buffer[et].start_addr = CS_ETM_INVAL_ADDR;
decoder->packet_buffer[et].end_addr = CS_ETM_INVAL_ADDR;
+ decoder->packet_buffer[et].instr_count = 0;
+ decoder->packet_buffer[et].last_instr_taken_branch = false;
+ decoder->packet_buffer[et].last_instr_size = 0;
if (decoder->packet_count == MAX_BUFFER - 1)
return OCSD_RESP_WAIT;
@@ -321,8 +328,28 @@ cs_etm_decoder__buffer_range(struct cs_etm_decoder *decoder,
packet = &decoder->packet_buffer[decoder->tail];
+ switch (elem->isa) {
+ case ocsd_isa_aarch64:
+ packet->isa = CS_ETM_ISA_A64;
+ break;
+ case ocsd_isa_arm:
+ packet->isa = CS_ETM_ISA_A32;
+ break;
+ case ocsd_isa_thumb2:
+ packet->isa = CS_ETM_ISA_T32;
+ break;
+ case ocsd_isa_tee:
+ case ocsd_isa_jazelle:
+ case ocsd_isa_custom:
+ case ocsd_isa_unknown:
+ default:
+ packet->isa = CS_ETM_ISA_UNKNOWN;
+ }
+
packet->start_addr = elem->st_addr;
packet->end_addr = elem->en_addr;
+ packet->instr_count = elem->num_instr_range;
+
switch (elem->last_i_type) {
case OCSD_INSTR_BR:
case OCSD_INSTR_BR_INDIRECT:
@@ -336,6 +363,8 @@ cs_etm_decoder__buffer_range(struct cs_etm_decoder *decoder,
break;
}
+ packet->last_instr_size = elem->last_instr_sz;
+
return ret;
}
diff --git a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h
index 612b5755f742..9351bd10d864 100644
--- a/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h
+++ b/tools/perf/util/cs-etm-decoder/cs-etm-decoder.h
@@ -28,11 +28,21 @@ enum cs_etm_sample_type {
CS_ETM_TRACE_ON = 1 << 1,
};
+enum cs_etm_isa {
+ CS_ETM_ISA_UNKNOWN,
+ CS_ETM_ISA_A64,
+ CS_ETM_ISA_A32,
+ CS_ETM_ISA_T32,
+};
+
struct cs_etm_packet {
enum cs_etm_sample_type sample_type;
+ enum cs_etm_isa isa;
u64 start_addr;
u64 end_addr;
+ u32 instr_count;
u8 last_instr_taken_branch;
+ u8 last_instr_size;
u8 exc;
u8 exc_ret;
int cpu;
diff --git a/tools/perf/util/cs-etm.c b/tools/perf/util/cs-etm.c
index 73430b73570d..48ad217bf0df 100644
--- a/tools/perf/util/cs-etm.c
+++ b/tools/perf/util/cs-etm.c
@@ -31,14 +31,6 @@
#define MAX_TIMESTAMP (~0ULL)
-/*
- * A64 instructions are always 4 bytes
- *
- * Only A64 is supported, so can use this constant for converting between
- * addresses and instruction counts, calculting offsets etc
- */
-#define A64_INSTR_SIZE 4
-
struct cs_etm_auxtrace {
struct auxtrace auxtrace;
struct auxtrace_queues queues;
@@ -510,21 +502,17 @@ static inline void cs_etm__reset_last_branch_rb(struct cs_etm_queue *etmq)
etmq->last_branch_rb->nr = 0;
}
-static inline u64 cs_etm__last_executed_instr(struct cs_etm_packet *packet)
-{
- /* Returns 0 for the CS_ETM_TRACE_ON packet */
- if (packet->sample_type == CS_ETM_TRACE_ON)
- return 0;
+static inline int cs_etm__t32_instr_size(struct cs_etm_queue *etmq,
+ u64 addr) {
+ u8 instrBytes[2];
+ cs_etm__mem_access(etmq, addr, ARRAY_SIZE(instrBytes), instrBytes);
/*
- * The packet records the execution range with an exclusive end address
- *
- * A64 instructions are constant size, so the last executed
- * instruction is A64_INSTR_SIZE before the end address
- * Will need to do instruction level decode for T32 instructions as
- * they can be variable size (not yet supported).
+ * T32 instruction size is indicated by bits[15:11] of the first
+ * 16-bit word of the instruction: 0b11101, 0b11110 and 0b11111
+ * denote a 32-bit instruction.
*/
- return packet->end_addr - A64_INSTR_SIZE;
+ return ((instrBytes[1] & 0xF8) >= 0xE8) ? 4 : 2;
}
static inline u64 cs_etm__first_executed_instr(struct cs_etm_packet *packet)
@@ -536,27 +524,32 @@ static inline u64 cs_etm__first_executed_instr(struct cs_etm_packet *packet)
return packet->start_addr;
}
-static inline u64 cs_etm__instr_count(const struct cs_etm_packet *packet)
+static inline
+u64 cs_etm__last_executed_instr(const struct cs_etm_packet *packet)
{
- /*
- * Only A64 instructions are currently supported, so can get
- * instruction count by dividing.
- * Will need to do instruction level decode for T32 instructions as
- * they can be variable size (not yet supported).
- */
- return (packet->end_addr - packet->start_addr) / A64_INSTR_SIZE;
+ /* Returns 0 for the CS_ETM_TRACE_ON packet */
+ if (packet->sample_type == CS_ETM_TRACE_ON)
+ return 0;
+
+ return packet->end_addr - packet->last_instr_size;
}
-static inline u64 cs_etm__instr_addr(const struct cs_etm_packet *packet,
+static inline u64 cs_etm__instr_addr(struct cs_etm_queue *etmq,
+ const struct cs_etm_packet *packet,
u64 offset)
{
- /*
- * Only A64 instructions are currently supported, so can get
- * instruction address by muliplying.
- * Will need to do instruction level decode for T32 instructions as
- * they can be variable size (not yet supported).
- */
- return packet->start_addr + offset * A64_INSTR_SIZE;
+ if (packet->isa == CS_ETM_ISA_T32) {
+ u64 addr = packet->start_addr;
+
+ while (offset > 0) {
+ addr += cs_etm__t32_instr_size(etmq, addr);
+ offset--;
+ }
+ return addr;
+ }
+
+ /* Assume a 4 byte instruction size (A32/A64) */
+ return packet->start_addr + offset * 4;
}
static void cs_etm__update_last_branch_rb(struct cs_etm_queue *etmq)
@@ -888,9 +881,8 @@ static int cs_etm__sample(struct cs_etm_queue *etmq)
struct cs_etm_auxtrace *etm = etmq->etm;
struct cs_etm_packet *tmp;
int ret;
- u64 instrs_executed;
+ u64 instrs_executed = etmq->packet->instr_count;
- instrs_executed = cs_etm__instr_count(etmq->packet);
etmq->period_instructions += instrs_executed;
/*
@@ -920,7 +912,7 @@ static int cs_etm__sample(struct cs_etm_queue *etmq)
* executed, but PC has not advanced to next instruction)
*/
u64 offset = (instrs_executed - instrs_over - 1);
- u64 addr = cs_etm__instr_addr(etmq->packet, offset);
+ u64 addr = cs_etm__instr_addr(etmq, etmq->packet, offset);
ret = cs_etm__synth_instruction_sample(
etmq, addr, etm->instructions_sample_period);
--
2.19.2
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^ permalink raw reply related
* Re: [PATCH v2 14/34] dt-bindings: arm: Convert Amlogic board/soc bindings to json-schema
From: Rob Herring @ 2018-12-06 21:27 UTC (permalink / raw)
To: Neil Armstrong
Cc: Mark Rutland, devicetree, Kumar Gala, Grant Likely, Sean Hudson,
Kevin Hilman, linuxppc-dev, linux-kernel@vger.kernel.org,
ARM-SoC Maintainers, Carlo Caione, linux-amlogic, Frank Rowand,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
In-Reply-To: <CAL_Jsq+e2m5VaibpvuTYURZ+E=MCSUGH8cokdWYWEjn_jy9iwA@mail.gmail.com>
On Tue, Dec 4, 2018 at 8:44 AM Rob Herring <robh@kernel.org> wrote:
>
> On Tue, Dec 4, 2018 at 2:39 AM Neil Armstrong <narmstrong@baylibre.com> wrote:
> >
> > Hi Rob,
> >
> > You forgot linux-amlogic in CC...
> >
> > On 03/12/2018 22:32, Rob Herring wrote:
> > > Convert Amlogic SoC bindings to DT schema format using json-schema.
> > >
> > > Cc: Carlo Caione <carlo@caione.org>
> > > Cc: Kevin Hilman <khilman@baylibre.com>
> > > Cc: Mark Rutland <mark.rutland@arm.com>
> > > Cc: devicetree@vger.kernel.org
> > > Signed-off-by: Rob Herring <robh@kernel.org>
> > > ---
>
> [...]
>
> > > + - items:
> > > + - enum:
> > > + - amlogic,s400
> > > + - const: amlogic,a113d
> > > + - const: amlogic,meson-axg
> > > + - items:
> > > + - enum:
> > > + - amlogic,u200
> > > + - const: amlogic,g12a
> >
> > but all this feels wrong for me.
> >
> > First of all, this yaml description is not human friendly and not intuitive at all,
> > and secondly with this conversion we loose all the comments about the SoC family relationship
> > with the compatible strings !
> >
> > I really understand the point to have automated verification, but really it's a pain to read
> > (I can't imagine newcomers... the actual DT bindings are already hard to read...) and
> > I feel it will be a real pain to write !
>
> What do you suggest that would be easier? Is it the YAML itself or the
> json-schema vocabulary? For the former, we could use {} and [] to make
> things more json style. But I imagine it is the latter.
>
> There is some learning curve for json-schema and is certainly a
> concern I have, but there would be a learning curve for anything. Our
> choices are use some existing schema language or invent one. All the
> previous efforts (there's been about 5 since 2013) have been inventing
> one, and they've not gone far. There will be far few resources
> available to train people with if we do something custom.
>
> > Can't we mix an "humam text" with a "yaml" part on a same document ? we are in 2018 (nearly 2019),
> > and it should be easy to extract a yaml description from a text document without pain and
> > keep all the human description, no ?
>
> Yes. Please go look at the annotated example in patch 2.
How's this?:
compatible:
oneOf:
- description: Boards with the Amlogic Meson6 SoC
items:
- enum:
- geniatech,atv1200
- const: amlogic,meson6
- description: Boards with the Amlogic Meson8 SoC
items:
- enum:
- minix,neo-x8
- const: amlogic,meson8
- description: Boards with the Amlogic Meson8m2 SoC
items:
- enum:
- tronsmart,mxiii-plus
- const: amlogic,meson8m2
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^ permalink raw reply
* Re: [PATCH v2 2/4] dmaengine: mtk_uart_dma: add Mediatek uart DMA support
From: Sean Wang @ 2018-12-06 21:22 UTC (permalink / raw)
To: long.cheng
Cc: mark.rutland, devicetree, yt.shen, srv_heupstream, gregkh,
linux-kernel, Matthias Brugger, vkoul, robh+dt, linux-mediatek,
linux-serial, jslaby, dmaengine, yingjoe.chen, dan.j.williams,
linux-arm-kernel
In-Reply-To: <1544090140.28871.11.camel@mhfsdcap03>
On Thu, Dec 6, 2018 at 1:55 AM Long Cheng <long.cheng@mediatek.com> wrote:
>
> On Wed, 2018-12-05 at 13:07 -0800, Sean Wang wrote:
> > .
> > On Wed, Dec 5, 2018 at 1:31 AM Long Cheng <long.cheng@mediatek.com> wrote:
> > >
> > > In DMA engine framework, add 8250 mtk dma to support it.
> > >
> > > Signed-off-by: Long Cheng <long.cheng@mediatek.com>
> > > ---
> > > drivers/dma/mediatek/8250_mtk_dma.c | 894 +++++++++++++++++++++++++++++++++++
> > > drivers/dma/mediatek/Kconfig | 11 +
> > > drivers/dma/mediatek/Makefile | 1 +
> > > 3 files changed, 906 insertions(+)
> > > create mode 100644 drivers/dma/mediatek/8250_mtk_dma.c
> > >
> > > diff --git a/drivers/dma/mediatek/8250_mtk_dma.c b/drivers/dma/mediatek/8250_mtk_dma.c
> > > new file mode 100644
> > > index 0000000..3454679
> > > --- /dev/null
> > > +++ b/drivers/dma/mediatek/8250_mtk_dma.c
> > > @@ -0,0 +1,894 @@
> > > +// SPDX-License-Identifier: GPL-2.0
> > > +/*
> > > + * Mediatek 8250 DMA driver.
> > > + *
> > > + * Copyright (c) 2018 MediaTek Inc.
> > > + * Author: Long Cheng <long.cheng@mediatek.com>
> > > + */
> > > +
> > > +#include <linux/clk.h>
> > > +#include <linux/dmaengine.h>
> > > +#include <linux/dma-mapping.h>
> > > +#include <linux/err.h>
> > > +#include <linux/init.h>
> > > +#include <linux/interrupt.h>
> > > +#include <linux/list.h>
> > > +#include <linux/module.h>
> > > +#include <linux/of_dma.h>
> > > +#include <linux/of_device.h>
> > > +#include <linux/platform_device.h>
> > > +#include <linux/slab.h>
> > > +#include <linux/spinlock.h>
> > > +#include <linux/pm_runtime.h>
> > > +#include <linux/iopoll.h>
> > > +
> > > +#include "../virt-dma.h"
> > > +
> > > +#define MTK_APDMA_DEFAULT_REQUESTS 127
> > > +#define MTK_APDMA_CHANNELS (CONFIG_SERIAL_8250_NR_UARTS * 2)
> > > +
> > > +#define VFF_EN_B BIT(0)
> > > +#define VFF_STOP_B BIT(0)
> > > +#define VFF_FLUSH_B BIT(0)
> > > +#define VFF_4G_SUPPORT_B BIT(0)
> > > +#define VFF_RX_INT_EN0_B BIT(0) /*rx valid size >= vff thre*/
> > > +#define VFF_RX_INT_EN1_B BIT(1)
> > > +#define VFF_TX_INT_EN_B BIT(0) /*tx left size >= vff thre*/
> > > +#define VFF_WARM_RST_B BIT(0)
> > > +#define VFF_RX_INT_FLAG_CLR_B (BIT(0) | BIT(1))
> > > +#define VFF_TX_INT_FLAG_CLR_B 0
> > > +#define VFF_STOP_CLR_B 0
> > > +#define VFF_FLUSH_CLR_B 0
> > > +#define VFF_INT_EN_CLR_B 0
> > > +#define VFF_4G_SUPPORT_CLR_B 0
> > > +
> > > +/* interrupt trigger level for tx */
> > > +#define VFF_TX_THRE(n) ((n) * 7 / 8)
> > > +/* interrupt trigger level for rx */
> > > +#define VFF_RX_THRE(n) ((n) * 3 / 4)
> > > +
> > > +#define MTK_DMA_RING_SIZE 0xffffU
> > > +/* invert this bit when wrap ring head again*/
> > > +#define MTK_DMA_RING_WRAP 0x10000U
> > > +
> > > +#define VFF_INT_FLAG 0x00
> > > +#define VFF_INT_EN 0x04
> > > +#define VFF_EN 0x08
> > > +#define VFF_RST 0x0c
> > > +#define VFF_STOP 0x10
> > > +#define VFF_FLUSH 0x14
> > > +#define VFF_ADDR 0x1c
> > > +#define VFF_LEN 0x24
> > > +#define VFF_THRE 0x28
> > > +#define VFF_WPT 0x2c
> > > +#define VFF_RPT 0x30
> > > +/*TX: the buffer size HW can read. RX: the buffer size SW can read.*/
> > > +#define VFF_VALID_SIZE 0x3c
> > > +/*TX: the buffer size SW can write. RX: the buffer size HW can write.*/
> > > +#define VFF_LEFT_SIZE 0x40
> > > +#define VFF_DEBUG_STATUS 0x50
> > > +#define VFF_4G_SUPPORT 0x54
> > > +
> > > +struct mtk_dmadev {
> > > + struct dma_device ddev;
> > > + void __iomem *mem_base[MTK_APDMA_CHANNELS];
> > > + spinlock_t lock; /* dma dev lock */
> > > + struct tasklet_struct task;
> > > + struct list_head pending;
> > > + struct clk *clk;
> > > + unsigned int dma_requests;
> > > + bool support_33bits;
> > > + unsigned int dma_irq[MTK_APDMA_CHANNELS];
> > > + struct mtk_chan *ch[MTK_APDMA_CHANNELS];
> > > +};
> > > +
> > > +struct mtk_chan {
> > > + struct virt_dma_chan vc;
> > > + struct list_head node;
> > > + struct dma_slave_config cfg;
> > > + void __iomem *base;
> > > + struct mtk_dma_desc *desc;
> > > +
> > > + bool stop;
> > > + bool requested;
> > > +
> > > + unsigned int dma_sig;
> >
> > the member can be removed as no real user would refer to it
> >
>
> Ok, i will remove it at next patch
>
> > > + unsigned int dma_ch;
> >
> > a chan_id is already included in struct dma_chan, we can reuse it
> >
>
> chan_id is start from 0. but in this driver, dma info is stored to list.
> if use port1, in filter_fn function, will set dma_ch to 2, 3(tx, rx). So
> can't using chan_id
>
if you use of_dma_xlate_by_chan_id in of_dma_controller_register, the
client device still can get the right channel with the appropriate
chan_id expressed in dmas property in dts.
> > > + unsigned int sgidx;
> >
[ ... ]
> ok, i will modify it
> > > + wpt = mtk_dma_chan_read(c, VFF_WPT);
> > > + wrap = wpt & MTK_DMA_RING_WRAP ? 0U : MTK_DMA_RING_WRAP;
> > > +
> > > + if ((wpt & (len - 1U)) + send < len)
> > > + mtk_dma_chan_write(c, VFF_WPT, wpt + send);
> > > + else
> > > + mtk_dma_chan_write(c, VFF_WPT,
> > > + ((wpt + send) & (len - 1U))
> > > + | wrap);
> > > +
> > > + c->remain_size -= send;
> >
> > I'm curious why you don't need to set up the hardware from the
> > descriptor information
> >
>
> mtk_dma_chan_write is update the hardware. remain_size is length of TX
> data.
I thought it is not enough to be a full dmaengine. if the driver only
supports single continuous data moving for device_prep_slave_sg
callback.
We could try to turn each sg item information such as source or
destination address and data length to be one part of the descriptor.
When a descriptor is being issued, and then program VFF_ADDR/LEN and
issue the data move by other VFF_* registers rather than assuming the
data portion is always the fixed as the user assignment at
mtk_dma_slave_config.
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^ permalink raw reply
* Re: [PATCH v2 2/2] kgdb/treewide: constify struct kgdb_arch arch_kgdb_ops
From: Borislav Petkov @ 2018-12-06 21:12 UTC (permalink / raw)
To: Christophe Leroy
Cc: Rich Felker, Gustavo A. R. Silva, Benjamin Herrenschmidt,
Will Deacon, linux-kernel, Paul Mackerras, sparclinux,
linux-hexagon, Daniel Thompson, Yoshinori Sato, linux-sh,
Michael Ellerman, x86, Russell King, Ingo Molnar, Catalin Marinas,
James Hogan, linux-snps-arc, uclinux-h8-devel, linux-mips,
nios2-dev, Thomas Gleixner, linux-arm-kernel, Michal Simek,
Vineet Gupta, Randy Dunlap, Douglas Anderson, Ralf Baechle,
Richard Kuo, Paul Burton, Jason Wessel, kgdb-bugreport,
Ley Foon Tan, linuxppc-dev, David S. Miller
In-Reply-To: <5e130b11680be09537913aae9649c84ede763ec8.1544083483.git.christophe.leroy@c-s.fr>
On Thu, Dec 06, 2018 at 08:07:40PM +0000, Christophe Leroy wrote:
> checkpatch.pl reports the following:
>
> WARNING: struct kgdb_arch should normally be const
> #28: FILE: arch/mips/kernel/kgdb.c:397:
> +struct kgdb_arch arch_kgdb_ops = {
>
> This report makes sense, as all other ops struct, this
> one should also be const. This patch does the change.
>
> Cc: Vineet Gupta <vgupta@synopsys.com>
> Cc: Russell King <linux@armlinux.org.uk>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will.deacon@arm.com>
> Cc: Yoshinori Sato <ysato@users.sourceforge.jp>
> Cc: Richard Kuo <rkuo@codeaurora.org>
> Cc: Michal Simek <monstr@monstr.eu>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: Paul Burton <paul.burton@mips.com>
> Cc: James Hogan <jhogan@kernel.org>
> Cc: Ley Foon Tan <lftan@altera.com>
> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Cc: Paul Mackerras <paulus@samba.org>
> Cc: Michael Ellerman <mpe@ellerman.id.au>
> Cc: Rich Felker <dalias@libc.org>
> Cc: "David S. Miller" <davem@davemloft.net>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> Cc: Ingo Molnar <mingo@redhat.com>
> Cc: Borislav Petkov <bp@alien8.de>
> Cc: x86@kernel.org
> Acked-by: Daniel Thompson <daniel.thompson@linaro.org>
> Acked-by: Paul Burton <paul.burton@mips.com>
> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
> ---
> v2: Added CCs to all maintainers/supporters identified by get_maintainer.pl and Acks from Daniel and Paul.
>
> arch/arc/kernel/kgdb.c | 2 +-
> arch/arm/kernel/kgdb.c | 2 +-
> arch/arm64/kernel/kgdb.c | 2 +-
> arch/h8300/kernel/kgdb.c | 2 +-
> arch/hexagon/kernel/kgdb.c | 2 +-
> arch/microblaze/kernel/kgdb.c | 2 +-
> arch/mips/kernel/kgdb.c | 2 +-
> arch/nios2/kernel/kgdb.c | 2 +-
> arch/powerpc/kernel/kgdb.c | 2 +-
> arch/sh/kernel/kgdb.c | 2 +-
> arch/sparc/kernel/kgdb_32.c | 2 +-
> arch/sparc/kernel/kgdb_64.c | 2 +-
> arch/x86/kernel/kgdb.c | 2 +-
> include/linux/kgdb.h | 2 +-
> 14 files changed, 14 insertions(+), 14 deletions(-)
...
> diff --git a/arch/x86/kernel/kgdb.c b/arch/x86/kernel/kgdb.c
> index 8e36f249646e..e7effc02f13c 100644
> --- a/arch/x86/kernel/kgdb.c
> +++ b/arch/x86/kernel/kgdb.c
> @@ -804,7 +804,7 @@ int kgdb_arch_remove_breakpoint(struct kgdb_bkpt *bpt)
> (char *)bpt->saved_instr, BREAK_INSTR_SIZE);
> }
>
> -struct kgdb_arch arch_kgdb_ops = {
> +const struct kgdb_arch arch_kgdb_ops = {
> /* Breakpoint instruction: */
> .gdb_bpt_instr = { 0xcc },
> .flags = KGDB_HW_BREAKPOINT,
For the x86 bits:
Acked-by: Borislav Petkov <bp@suse.de>
--
Regards/Gruss,
Boris.
Good mailing practices for 400: avoid top-posting and trim the reply.
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^ permalink raw reply
* Re: [PATCH v2] power: reset: at91-poweroff: move shdwc related data to one structure
From: Sebastian Reichel @ 2018-12-06 20:59 UTC (permalink / raw)
To: Claudiu.Beznea
Cc: alexandre.belloni, linux-pm, linux-kernel, Ludovic.Desroches,
linux-arm-kernel
In-Reply-To: <1544117357-24177-1-git-send-email-claudiu.beznea@microchip.com>
[-- Attachment #1.1: Type: text/plain, Size: 4731 bytes --]
Hi,
On Thu, Dec 06, 2018 at 05:29:46PM +0000, Claudiu.Beznea@microchip.com wrote:
> From: Claudiu Beznea <claudiu.beznea@microchip.com>
>
> Move SHDWC realted data to only one structure to have them grouped.
> Inspired from commit 9be74f0d39c1 ("power: reset: at91-poweroff: make
> mpddrc_base part of struct shdwc").
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
> ---
Thanks, queued.
-- Sebastian
>
> Changes in v2:
> - avoid allocate at91_shdwc and keep it static instead
> - avoid registering at91_shdwc as platform data and use static variable
> instead
>
> drivers/power/reset/at91-poweroff.c | 48 +++++++++++++++++++------------------
> 1 file changed, 25 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/power/reset/at91-poweroff.c b/drivers/power/reset/at91-poweroff.c
> index d3d87af24e55..9e74e131c675 100644
> --- a/drivers/power/reset/at91-poweroff.c
> +++ b/drivers/power/reset/at91-poweroff.c
> @@ -51,14 +51,16 @@ static const char *shdwc_wakeup_modes[] = {
> [AT91_SHDW_WKMODE0_ANYLEVEL] = "any",
> };
>
> -static void __iomem *at91_shdwc_base;
> -static struct clk *sclk;
> -static void __iomem *mpddrc_base;
> +static struct shdwc {
> + struct clk *sclk;
> + void __iomem *shdwc_base;
> + void __iomem *mpddrc_base;
> +} at91_shdwc;
>
> static void __init at91_wakeup_status(struct platform_device *pdev)
> {
> const char *reason;
> - u32 reg = readl(at91_shdwc_base + AT91_SHDW_SR);
> + u32 reg = readl(at91_shdwc.shdwc_base + AT91_SHDW_SR);
>
> /* Simple power-on, just bail out */
> if (!reg)
> @@ -92,9 +94,9 @@ static void at91_poweroff(void)
>
> " b .\n\t"
> :
> - : "r" (mpddrc_base),
> + : "r" (at91_shdwc.mpddrc_base),
> "r" cpu_to_le32(AT91_DDRSDRC_LPDDR2_PWOFF),
> - "r" (at91_shdwc_base),
> + "r" (at91_shdwc.shdwc_base),
> "r" cpu_to_le32(AT91_SHDW_KEY | AT91_SHDW_SHDW)
> : "r6");
> }
> @@ -144,7 +146,7 @@ static void at91_poweroff_dt_set_wakeup_mode(struct platform_device *pdev)
> if (of_property_read_bool(np, "atmel,wakeup-rtt-timer"))
> mode |= AT91_SHDW_RTTWKEN;
>
> - writel(wakeup_mode | mode, at91_shdwc_base + AT91_SHDW_MR);
> + writel(wakeup_mode | mode, at91_shdwc.shdwc_base + AT91_SHDW_MR);
> }
>
> static int __init at91_poweroff_probe(struct platform_device *pdev)
> @@ -155,15 +157,15 @@ static int __init at91_poweroff_probe(struct platform_device *pdev)
> int ret;
>
> res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> - at91_shdwc_base = devm_ioremap_resource(&pdev->dev, res);
> - if (IS_ERR(at91_shdwc_base))
> - return PTR_ERR(at91_shdwc_base);
> + at91_shdwc.shdwc_base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(at91_shdwc.shdwc_base))
> + return PTR_ERR(at91_shdwc.shdwc_base);
>
> - sclk = devm_clk_get(&pdev->dev, NULL);
> - if (IS_ERR(sclk))
> - return PTR_ERR(sclk);
> + at91_shdwc.sclk = devm_clk_get(&pdev->dev, NULL);
> + if (IS_ERR(at91_shdwc.sclk))
> + return PTR_ERR(at91_shdwc.sclk);
>
> - ret = clk_prepare_enable(sclk);
> + ret = clk_prepare_enable(at91_shdwc.sclk);
> if (ret) {
> dev_err(&pdev->dev, "Could not enable slow clock\n");
> return ret;
> @@ -176,20 +178,20 @@ static int __init at91_poweroff_probe(struct platform_device *pdev)
>
> np = of_find_compatible_node(NULL, NULL, "atmel,sama5d3-ddramc");
> if (np) {
> - mpddrc_base = of_iomap(np, 0);
> + at91_shdwc.mpddrc_base = of_iomap(np, 0);
> of_node_put(np);
>
> - if (!mpddrc_base) {
> + if (!at91_shdwc.mpddrc_base) {
> ret = -ENOMEM;
> goto clk_disable;
> }
>
> - ddr_type = readl(mpddrc_base + AT91_DDRSDRC_MDR) &
> + ddr_type = readl(at91_shdwc.mpddrc_base + AT91_DDRSDRC_MDR) &
> AT91_DDRSDRC_MD;
> if (ddr_type != AT91_DDRSDRC_MD_LPDDR2 &&
> ddr_type != AT91_DDRSDRC_MD_LPDDR3) {
> - iounmap(mpddrc_base);
> - mpddrc_base = NULL;
> + iounmap(at91_shdwc.mpddrc_base);
> + at91_shdwc.mpddrc_base = NULL;
> }
> }
>
> @@ -198,7 +200,7 @@ static int __init at91_poweroff_probe(struct platform_device *pdev)
> return 0;
>
> clk_disable:
> - clk_disable_unprepare(sclk);
> + clk_disable_unprepare(at91_shdwc.sclk);
> return ret;
> }
>
> @@ -207,10 +209,10 @@ static int __exit at91_poweroff_remove(struct platform_device *pdev)
> if (pm_power_off == at91_poweroff)
> pm_power_off = NULL;
>
> - if (mpddrc_base)
> - iounmap(mpddrc_base);
> + if (at91_shdwc.mpddrc_base)
> + iounmap(at91_shdwc.mpddrc_base);
>
> - clk_disable_unprepare(sclk);
> + clk_disable_unprepare(at91_shdwc.sclk);
>
> return 0;
> }
> --
> 2.7.4
>
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