* Re: [PATCH 1/2] drm: add cache support for arm64
From: Mark Rutland @ 2019-08-06 14:34 UTC (permalink / raw)
To: Rob Clark
Cc: Sean Paul, Maxime Ripard, Catalin Marinas, Maarten Lankhorst,
LKML, dri-devel, David Airlie, Rob Clark, linux-arm-kernel,
Daniel Vetter, Greg Kroah-Hartman, Thomas Gleixner, Will Deacon,
Christoph Hellwig, Allison Randal
In-Reply-To: <CAJs_Fx6eh1w7c=crMoD5XyEOMzP6orLhqUewErE51cPGYmObBQ@mail.gmail.com>
On Tue, Aug 06, 2019 at 07:11:41AM -0700, Rob Clark wrote:
> On Tue, Aug 6, 2019 at 1:48 AM Christoph Hellwig <hch@lst.de> wrote:
> >
> > This goes in the wrong direction. drm_cflush_* are a bad API we need to
> > get rid of, not add use of it. The reason for that is two-fold:
> >
> > a) it doesn't address how cache maintaince actually works in most
> > platforms. When talking about a cache we three fundamental operations:
> >
> > 1) write back - this writes the content of the cache back to the
> > backing memory
> > 2) invalidate - this remove the content of the cache
> > 3) write back + invalidate - do both of the above
>
> Agreed that drm_cflush_* isn't a great API. In this particular case
> (IIUC), I need wb+inv so that there aren't dirty cache lines that drop
> out to memory later, and so that I don't get a cache hit on
> uncached/wc mmap'ing.
Is there a cacheable alias lying around (e.g. the linear map), or are
these addresses only mapped uncached/wc?
If there's a cacheable alias, performing an invalidate isn't sufficient,
since a CPU can allocate a new (clean) entry at any point in time (e.g.
as a result of prefetching or arbitrary speculation).
Thanks,
Mark.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH] arm64: dts: allwinner: a64: Drop PMU node
From: Robin Murphy @ 2019-08-06 14:35 UTC (permalink / raw)
To: Vasily Khoruzhick, Maxime Ripard, Chen-Yu Tsai, Rob Herring,
Mark Rutland, linux-arm-kernel, devicetree
Cc: Jared D . McNeill, Harald Geyer
In-Reply-To: <20190806140135.4739-1-anarsoul@gmail.com>
On 06/08/2019 15:01, Vasily Khoruzhick wrote:
> Looks like PMU in A64 is broken, it generates no interrupts at all and
> as result 'perf top' shows no events.
Does something like 'perf stat sleep 1' at least count cycles correctly?
It could well just be that the interrupt numbers are wrong...
> Tested on Pine64-LTS.
>
> Fixes: 34a97fcc71c2 ("arm64: dts: allwinner: a64: Add PMU node")
> Cc: Harald Geyer <harald@ccbib.org>
> Cc: Jared D. McNeill <jmcneill@NetBSD.org>
> Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
> ---
> arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 9 ---------
> 1 file changed, 9 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> index 9cc9bdde81ac..cd92f546c483 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> @@ -142,15 +142,6 @@
> clock-output-names = "ext-osc32k";
> };
>
> - pmu {
> - compatible = "arm,cortex-a53-pmu";
> - interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
Cross-referencing between some random DTs in the H6 BSP I happen to have
to hand and the A64 User Manual, it looks a lot like someone just forgot
to subtract 32 from these to satisfy the awkward GIC binding - that
wants the SPI index rather than the actual interrupt source number,
which implies these should probably be 120-123 rather than 152-155.
Robin.
> - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
> - };
> -
> psci {
> compatible = "arm,psci-0.2";
> method = "smc";
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH] arm64: dts: allwinner: a64: Drop PMU node
From: Vasily Khoruzhick @ 2019-08-06 14:45 UTC (permalink / raw)
To: Robin Murphy
Cc: Mark Rutland, devicetree, Jared D . McNeill, Maxime Ripard,
Chen-Yu Tsai, Rob Herring, Harald Geyer, arm-linux
In-Reply-To: <89402d22-d432-9551-e787-c8ede16dbe5f@arm.com>
On Tue, Aug 6, 2019 at 7:35 AM Robin Murphy <robin.murphy@arm.com> wrote:
>
> On 06/08/2019 15:01, Vasily Khoruzhick wrote:
> > Looks like PMU in A64 is broken, it generates no interrupts at all and
> > as result 'perf top' shows no events.
>
> Does something like 'perf stat sleep 1' at least count cycles correctly?
> It could well just be that the interrupt numbers are wrong...
Looks like it does, at least result looks plausible:
$ perf stat sleep 1
Performance counter stats for 'sleep 1':
4.08 msec task-clock:u # 0.004 CPUs
utilized
0 context-switches:u # 0.000 K/sec
0 cpu-migrations:u # 0.000 K/sec
55 page-faults:u # 0.013 M/sec
527,711 cycles:u # 0.129 GHz
197,262 instructions:u # 0.37 insn per
cycle
24,242 branches:u # 5.947 M/sec
5,083 branch-misses:u # 20.97% of all
branches
1.011928625 seconds time elapsed
0.000000000 seconds user
0.007196000 seconds sys
> > Tested on Pine64-LTS.
> >
> > Fixes: 34a97fcc71c2 ("arm64: dts: allwinner: a64: Add PMU node")
> > Cc: Harald Geyer <harald@ccbib.org>
> > Cc: Jared D. McNeill <jmcneill@NetBSD.org>
> > Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
> > ---
> > arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 9 ---------
> > 1 file changed, 9 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> > index 9cc9bdde81ac..cd92f546c483 100644
> > --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> > +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> > @@ -142,15 +142,6 @@
> > clock-output-names = "ext-osc32k";
> > };
> >
> > - pmu {
> > - compatible = "arm,cortex-a53-pmu";
> > - interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
> > - <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
> > - <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
> > - <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
>
> Cross-referencing between some random DTs in the H6 BSP I happen to have
> to hand and the A64 User Manual, it looks a lot like someone just forgot
> to subtract 32 from these to satisfy the awkward GIC binding - that
> wants the SPI index rather than the actual interrupt source number,
> which implies these should probably be 120-123 rather than 152-155.
Tried that, didn't work. 'grep pmu /proc/interrupts' shows zeroes, and
'perf top' is completely silent.
> Robin.
>
> > - interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
> > - };
> > -
> > psci {
> > compatible = "arm,psci-0.2";
> > method = "smc";
> >
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH v3] tracing: Function stack size and its name mismatch in arm64
From: Joel Fernandes @ 2019-08-06 14:47 UTC (permalink / raw)
To: Will Deacon
Cc: Jiping Ma, catalin.marinas, will.deacon, linux-kernel,
Steven Rostedt, takahiro.akashi, mingo, kernel-team,
linux-arm-kernel
In-Reply-To: <20190805112524.ajlmouutqckwpqyd@willie-the-truck>
On Mon, Aug 05, 2019 at 12:25:25PM +0100, Will Deacon wrote:
> [+Akashi, since he may remember more of the gory details here]
>
> On Sat, Aug 03, 2019 at 04:26:42AM -0400, Joel Fernandes wrote:
> > On Fri, Aug 02, 2019 at 11:22:59AM -0400, Steven Rostedt wrote:
> > [snip]
> > > > There is not PC in ARM64 stack, LR is used to for walk_stackframe in
> > > > ARM64. Tere is no the issue in ARM32 because there is PC in ARM32 stack.
> > > > PC is used to calculate the stack size in trace_stack.c, so the
> > > > function name and its stack size appear to be off-by-one.
> > > > ARM64 stack layout:
> > > > LR
> > > > FP
> > > > ......
> > > > LR
> > > > FP
> > > > ......
> > >
> > > I think you are not explaining the issue correctly. From looking at the
> > > document, I think what you want to say is that the LR is saved *after*
> > > the data for the function. Is that correct? If so, then yes, it would
> > > cause the stack tracing algorithm to be incorrect.
> > >
> > > Most archs do this:
> > >
> > > On entry to a function:
> > >
> > > save return address
> > > reserve local variables and such for current function
> > >
> > > I think you are saying that arm64 does this backwards.
> > >
> > > reserve local variables and such for current function
> > > save return address (LR)
> >
> > Actually for arm64 it is like what you said about 'Most archs'. It saves FP
> > and LR first onto the current stack frame, then assigns the top of the stack
> > to FP (marking the new frame). Then executes branch-link, and then allocates
> > space to variables on stack in the callee.
> >
> > Disassembly of prog:
> >
> > int foo(int x, int y) {
> > int a[32];
> > return (x + y + a[31]);
> > }
> >
> > int bar(void) {
> > foo(1, 2);
> > }
> >
> > confirms it:
> >
> > 000000000000073c <bar>:
> > 73c: a9bf7bfd stp x29, x30, [sp, #-16]! <-- save FP and LR
> > 740: 910003fd mov x29, sp <-- create new FP
> > 744: 52800041 mov w1, #0x2 <-- pass arguments
> > 748: 52800020 mov w0, #0x1
> > 74c: 97fffff4 bl 71c <foo> <-- branch (sets LR)
> > 750: d503201f nop
> > 754: a8c17bfd ldp x29, x30, [sp], #16 <-- restore FP, LR
> > 758: d65f03c0 ret
> >
> > 000000000000071c <foo>:
> > 71c: d10243ff sub sp, sp, #0x90 <-- space for local var
> > 720: b9000fe0 str w0, [sp, #12]
> > 724: b9000be1 str w1, [sp, #8]
> > 728: b9400fe1 ldr w1, [sp, #12]
> > 72c: b9400be0 ldr w0, [sp, #8]
> > 730: 0b000021 add w1, w1, w0
> > 734: b9408fe0 ldr w0, [sp, #140]
> > 738: 0b000020 add w0, w1, w0
> > 73c: 910243ff add sp, sp, #0x90 <-- restore sp before ret
> > 740: d65f03c0 ret
>
> I think we need to untangle things a bit here.
>
> The arm64 PCS makes no guarantee about the position of the frame record with
> respect to stack allocations, so relying on this is fragile at best. This is
> partly why the ftrace-with-regs work currently relies on
> -fpatchable-function-entry, since that allows the very beginning of the
> function to be intercepted which I don't think is necessarily the case with
> -pg/_mcount.
>
> For the snippet above, foo is a leaf function and does not have a frame record
> placed on the stack. If we instead look at something like:
>
> __attribute__((noinline)) int baz(int x)
> {
> return x;
> }
>
> __attribute__((noinline)) int bar(int x)
> {
> int a[32];
> return baz(x * a[0]);
> }
>
> int foo(int x)
> {
> return bar(x);
> }
>
> then the first instruction of bar() allocates stack space and pushes
> the frame record at the same time:
>
> stp x29, x30, [sp, -144]!
>
> This can be read as "subtract 144 bytes (32*4 + 16) from the stack pointer,
> write the frame record there and then update the stack pointer to point at the
> bottom of the newly allocated stack", which means that the array 'a[32]' sits
> directly /above/ the frame record on the stack. However, this is just what my
> GCC happened to do today. When we looked at this back in 2015, there were other
> cases we ended up having to identify with heuristics based on what had been
> observed under various compilers:
Right point taken, I was looking at bar()'s stack frame instead of foo()'s.
foo() did not have to save any frame record, so probably my example was
confusing. My bad.
So indeed, it seems an odd ball case.
> http://lists.infradead.org/pipermail/linux-arm-kernel/2015-December/393721.html
>
> This was deemed to be far too fragile, so we didn't merge it in the end.
>
> If this is to work reliably, then we need support from the tools. This was
> raised when we first merged support for ftrace, but I'm not sure it went
> anywhere:
>
> https://gcc.gnu.org/ml/gcc/2016-01/msg00035.html
> So, I completely agree with Steve that we shouldn't be littering the core code
> with #ifdef CONFIG_ARM64, but we probably do need something in the arch backend
> if we're going to do this properly, and that in turn is likely to need a very
> different algorithm from the one currently in use.
Yeah, I am in line with that thought as well. I am reviewing the latest patch
from Steve now to understand it better.
thanks,
- Joel
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH v2] arm64: dts: rockchip: Add dts for Leez RK3399 P710 SBC
From: Rob Herring @ 2019-08-06 14:48 UTC (permalink / raw)
To: Andy Yan
Cc: devicetree, linux-kernel@vger.kernel.org, heiko@sntech.de,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
open list:ARM/Rockchip SoC...
In-Reply-To: <20190805124037.10597-1-andyshrk@gmail.com>
On Mon, Aug 5, 2019 at 6:40 AM Andy Yan <andyshrk@gmail.com> wrote:
>
> P710 is a RK3399 based SBC, designed by Leez [0].
>
> Specification
> - Rockchip RK3399
> - 4/2GB LPDDR4
> - TF sd scard slot
> - eMMC
> - M.2 B-Key for 4G LTE
> - AP6256 for WiFi + BT
> - Gigabit ethernet
> - HDMI out
> - 40 pin header
> - USB 2.0 x 2
> - USB 3.0 x 1
> - USB 3.0 Type-C x 1
> - TYPE-C Power supply
>
> [0]https://leez.lenovo.com
I'm not really convinced Leez is a vendor. Looks like branding to me.
We have enough with company names changing, we don't need changing
brands too. Use 'lenovo'.
Rob
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH V4 06/11] arm64: mm: Introduce VA_BITS_ACTUAL
From: Catalin Marinas @ 2019-08-06 14:48 UTC (permalink / raw)
To: Steve Capper
Cc: crecklin@redhat.com, ard.biesheuvel@linaro.org, maz@kernel.org,
bhsharma@redhat.com, nd, will@kernel.org,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <20190806113202.GA11778@capper-ampere.manchester.arm.com>
On Tue, Aug 06, 2019 at 11:32:04AM +0000, Steve Capper wrote:
> On Mon, Aug 05, 2019 at 06:26:43PM +0100, Catalin Marinas wrote:
> > On Mon, Jul 29, 2019 at 05:21:12PM +0100, Steve Capper wrote:
> > > diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h
> > > index a8a91a573bff..93341f4fe840 100644
> > > --- a/arch/arm64/include/asm/memory.h
> > > +++ b/arch/arm64/include/asm/memory.h
> > > @@ -37,8 +37,6 @@
> > > * VA_START - the first kernel virtual address.
> > > */
> > > #define VA_BITS (CONFIG_ARM64_VA_BITS)
> > > -#define VA_START (UL(0xffffffffffffffff) - \
> > > - (UL(1) << (VA_BITS - 1)) + 1)
> > > #define PAGE_OFFSET (UL(0xffffffffffffffff) - \
> > > (UL(1) << VA_BITS) + 1)
> > > #define KIMAGE_VADDR (MODULES_END)
> > > @@ -166,10 +164,14 @@
> > > #endif
> > >
> > > #ifndef __ASSEMBLY__
> > > +extern u64 vabits_actual;
> > > +#define VA_BITS_ACTUAL ({vabits_actual;})
> >
> > Why not use the variable vabits_actual directly instead of defining a
> > macro?
>
> I thought that it would look better to have an uppercase name for the
> actual VA bits to match the existing code style for VA_BITS.
>
> I can just rename vabits_actual => VA_BITS_ACTUAL and get rid of the
> macro?
By tradition we use uppercase for macros and lowercase for variables. So
I'd definitely keep the variable lowercase.
If you prefer to keep the macro as well, fine by me, I don't think we
should bikeshed here.
--
Catalin
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH V13 12/12] PCI: tegra: Add Tegra194 PCIe support
From: Lorenzo Pieralisi @ 2019-08-06 14:51 UTC (permalink / raw)
To: Vidya Sagar
Cc: mark.rutland, devicetree, mperttunen, mmaddireddy, linux-pci,
catalin.marinas, will.deacon, linux-kernel, kthota, kishon,
linux-tegra, robh+dt, thierry.reding, gustavo.pimentel,
jingoohan1, bhelgaas, digetx, jonathanh, linux-arm-kernel,
sagar.tv
In-Reply-To: <a25bf401-3bbc-ff6d-a493-f454b311dc47@nvidia.com>
On Mon, Aug 05, 2019 at 10:24:42PM +0530, Vidya Sagar wrote:
[...]
> > > > IRQs are enabled when you call a suspend_noirq() callback, so the
> > > > blocking API can be used as long as the IRQ descriptor backing
> > > > the IRQ that will wake-up the blocked call is marked as
> > > > IRQF_NO_SUSPEND.
> > > >
> > > > The problem is not IRQs enabled/disabled at CPU level, the problem is
> > > > the IRQ descriptor of the IRQ required to handle the blocking BPMP call,
> > > > mark it as IRQF_NO_SUSPEND and remove the tegra_bpmp_transfer_atomic()
> > > > call from this code (or please give me a concrete example pinpointing
> > > > why it is needed).
> > > Ideally, using tegra_bpmp_transfer() alone in all paths (.probe() as
> > > well as .resume_noirq()) should have worked as the corresponding IRQ
> > > is already flagged as IRQF_NO_SUSPEND, but, because of the way BPMP-FW
> > > driver in kernel making its interface available through
> > > .resume_early(), tegra_bpmp_transfer() wasn't working as expected and
> > > I pushed a patch (CC'ing you) at
> > > http://patchwork.ozlabs.org/patch/1140973/ to make it .resume_noirq()
> > > from .resume_early(). With that in place, we can just use
> > > tegra_bpmp_trasnfer(). I'll push a new patch with this change once my
> > > BPMP-FW driver patch is approved.
> >
> > Does this leave you with a resume_noirq() callbacks ordering issue to
> > sort out ?
> Not really.
>
> >
> > a.k.a How will you guarantee that the BPMP will resume before the host
> > bridge ?
> It is already taken care of in the following way. PCIe controller's
> device-tree node has an entry with a phandle of BPMP-FW's node to get
> a handle of it and PCIe driver uses tegra_bpmp_get() API for that.
> This API returns -EPROBE_DEFER if BPMP-FW's driver is not ready yet,
> which guarantees that PCIe driver gets loaded only after BPMP-FW's
> driver and this order is followed during noirq phase also.
OK, thanks, this makes much more sense than the original code.
Lorenzo
> > Thanks,
> > Lorenzo
> >
> > > Thanks,
> > > Vidya Sagar
> > > >
> > > > Thanks,
> > > > Lorenzo
> > > >
> > > > > I'll go ahead and make next patch series with this if this looks fine to you.
> > > > >
> > > > > >
> > > > > > > > Actually, if tegra_bpmp_transfer() requires IRQs to be enabled you may
> > > > > > > > even end up in a situation where that blocking call does not wake up
> > > > > > > > because the IRQ in question was disabled in the NOIRQ suspend/resume
> > > > > > > > phase.
> > > > > > > >
> > > > > > > > [...]
> > > > > > > >
> > > > > > > > > > > +static int tegra_pcie_dw_probe(struct platform_device *pdev)
> > > > > > > > > > > +{
> > > > > > > > > > > + const struct tegra_pcie_soc *data;
> > > > > > > > > > > + struct device *dev = &pdev->dev;
> > > > > > > > > > > + struct resource *atu_dma_res;
> > > > > > > > > > > + struct tegra_pcie_dw *pcie;
> > > > > > > > > > > + struct resource *dbi_res;
> > > > > > > > > > > + struct pcie_port *pp;
> > > > > > > > > > > + struct dw_pcie *pci;
> > > > > > > > > > > + struct phy **phys;
> > > > > > > > > > > + char *name;
> > > > > > > > > > > + int ret;
> > > > > > > > > > > + u32 i;
> > > > > > > > > > > +
> > > > > > > > > > > + pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
> > > > > > > > > > > + if (!pcie)
> > > > > > > > > > > + return -ENOMEM;
> > > > > > > > > > > +
> > > > > > > > > > > + pci = &pcie->pci;
> > > > > > > > > > > + pci->dev = &pdev->dev;
> > > > > > > > > > > + pci->ops = &tegra_dw_pcie_ops;
> > > > > > > > > > > + pp = &pci->pp;
> > > > > > > > > > > + pcie->dev = &pdev->dev;
> > > > > > > > > > > +
> > > > > > > > > > > + data = (struct tegra_pcie_soc *)of_device_get_match_data(dev);
> > > > > > > > > > > + if (!data)
> > > > > > > > > > > + return -EINVAL;
> > > > > > > > > > > + pcie->mode = (enum dw_pcie_device_mode)data->mode;
> > > > > > > > > > > +
> > > > > > > > > > > + ret = tegra_pcie_dw_parse_dt(pcie);
> > > > > > > > > > > + if (ret < 0) {
> > > > > > > > > > > + dev_err(dev, "Failed to parse device tree: %d\n", ret);
> > > > > > > > > > > + return ret;
> > > > > > > > > > > + }
> > > > > > > > > > > +
> > > > > > > > > > > + pcie->pex_ctl_supply = devm_regulator_get(dev, "vddio-pex-ctl");
> > > > > > > > > > > + if (IS_ERR(pcie->pex_ctl_supply)) {
> > > > > > > > > > > + dev_err(dev, "Failed to get regulator: %ld\n",
> > > > > > > > > > > + PTR_ERR(pcie->pex_ctl_supply));
> > > > > > > > > > > + return PTR_ERR(pcie->pex_ctl_supply);
> > > > > > > > > > > + }
> > > > > > > > > > > +
> > > > > > > > > > > + pcie->core_clk = devm_clk_get(dev, "core");
> > > > > > > > > > > + if (IS_ERR(pcie->core_clk)) {
> > > > > > > > > > > + dev_err(dev, "Failed to get core clock: %ld\n",
> > > > > > > > > > > + PTR_ERR(pcie->core_clk));
> > > > > > > > > > > + return PTR_ERR(pcie->core_clk);
> > > > > > > > > > > + }
> > > > > > > > > > > +
> > > > > > > > > > > + pcie->appl_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> > > > > > > > > > > + "appl");
> > > > > > > > > > > + if (!pcie->appl_res) {
> > > > > > > > > > > + dev_err(dev, "Failed to find \"appl\" region\n");
> > > > > > > > > > > + return PTR_ERR(pcie->appl_res);
> > > > > > > > > > > + }
> > > > > > > > > > > + pcie->appl_base = devm_ioremap_resource(dev, pcie->appl_res);
> > > > > > > > > > > + if (IS_ERR(pcie->appl_base))
> > > > > > > > > > > + return PTR_ERR(pcie->appl_base);
> > > > > > > > > > > +
> > > > > > > > > > > + pcie->core_apb_rst = devm_reset_control_get(dev, "apb");
> > > > > > > > > > > + if (IS_ERR(pcie->core_apb_rst)) {
> > > > > > > > > > > + dev_err(dev, "Failed to get APB reset: %ld\n",
> > > > > > > > > > > + PTR_ERR(pcie->core_apb_rst));
> > > > > > > > > > > + return PTR_ERR(pcie->core_apb_rst);
> > > > > > > > > > > + }
> > > > > > > > > > > +
> > > > > > > > > > > + phys = devm_kcalloc(dev, pcie->phy_count, sizeof(*phys), GFP_KERNEL);
> > > > > > > > > > > + if (!phys)
> > > > > > > > > > > + return PTR_ERR(phys);
> > > > > > > > > > > +
> > > > > > > > > > > + for (i = 0; i < pcie->phy_count; i++) {
> > > > > > > > > > > + name = kasprintf(GFP_KERNEL, "p2u-%u", i);
> > > > > > > > > > > + if (!name) {
> > > > > > > > > > > + dev_err(dev, "Failed to create P2U string\n");
> > > > > > > > > > > + return -ENOMEM;
> > > > > > > > > > > + }
> > > > > > > > > > > + phys[i] = devm_phy_get(dev, name);
> > > > > > > > > > > + kfree(name);
> > > > > > > > > > > + if (IS_ERR(phys[i])) {
> > > > > > > > > > > + ret = PTR_ERR(phys[i]);
> > > > > > > > > > > + dev_err(dev, "Failed to get PHY: %d\n", ret);
> > > > > > > > > > > + return ret;
> > > > > > > > > > > + }
> > > > > > > > > > > + }
> > > > > > > > > > > +
> > > > > > > > > > > + pcie->phys = phys;
> > > > > > > > > > > +
> > > > > > > > > > > + dbi_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
> > > > > > > > > > > + if (!dbi_res) {
> > > > > > > > > > > + dev_err(dev, "Failed to find \"dbi\" region\n");
> > > > > > > > > > > + return PTR_ERR(dbi_res);
> > > > > > > > > > > + }
> > > > > > > > > > > + pcie->dbi_res = dbi_res;
> > > > > > > > > > > +
> > > > > > > > > > > + pci->dbi_base = devm_ioremap_resource(dev, dbi_res);
> > > > > > > > > > > + if (IS_ERR(pci->dbi_base))
> > > > > > > > > > > + return PTR_ERR(pci->dbi_base);
> > > > > > > > > > > +
> > > > > > > > > > > + /* Tegra HW locates DBI2 at a fixed offset from DBI */
> > > > > > > > > > > + pci->dbi_base2 = pci->dbi_base + 0x1000;
> > > > > > > > > > > +
> > > > > > > > > > > + atu_dma_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> > > > > > > > > > > + "atu_dma");
> > > > > > > > > > > + if (!atu_dma_res) {
> > > > > > > > > > > + dev_err(dev, "Failed to find \"atu_dma\" region\n");
> > > > > > > > > > > + return PTR_ERR(atu_dma_res);
> > > > > > > > > > > + }
> > > > > > > > > > > + pcie->atu_dma_res = atu_dma_res;
> > > > > > > > > > > + pci->atu_base = devm_ioremap_resource(dev, atu_dma_res);
> > > > > > > > > > > + if (IS_ERR(pci->atu_base))
> > > > > > > > > > > + return PTR_ERR(pci->atu_base);
> > > > > > > > > > > +
> > > > > > > > > > > + pcie->core_rst = devm_reset_control_get(dev, "core");
> > > > > > > > > > > + if (IS_ERR(pcie->core_rst)) {
> > > > > > > > > > > + dev_err(dev, "Failed to get core reset: %ld\n",
> > > > > > > > > > > + PTR_ERR(pcie->core_rst));
> > > > > > > > > > > + return PTR_ERR(pcie->core_rst);
> > > > > > > > > > > + }
> > > > > > > > > > > +
> > > > > > > > > > > + pp->irq = platform_get_irq_byname(pdev, "intr");
> > > > > > > > > > > + if (!pp->irq) {
> > > > > > > > > > > + dev_err(dev, "Failed to get \"intr\" interrupt\n");
> > > > > > > > > > > + return -ENODEV;
> > > > > > > > > > > + }
> > > > > > > > > > > +
> > > > > > > > > > > + ret = devm_request_irq(dev, pp->irq, tegra_pcie_irq_handler,
> > > > > > > > > > > + IRQF_SHARED, "tegra-pcie-intr", pcie);
> > > > > > > > > > > + if (ret) {
> > > > > > > > > > > + dev_err(dev, "Failed to request IRQ %d: %d\n", pp->irq, ret);
> > > > > > > > > > > + return ret;
> > > > > > > > > > > + }
> > > > > > > > > > > +
> > > > > > > > > > > + pcie->bpmp = tegra_bpmp_get(dev);
> > > > > > > > > > > + if (IS_ERR(pcie->bpmp))
> > > > > > > > > > > + return PTR_ERR(pcie->bpmp);
> > > > > > > > > > > +
> > > > > > > > > > > + platform_set_drvdata(pdev, pcie);
> > > > > > > > > > > +
> > > > > > > > > > > + if (pcie->mode == DW_PCIE_RC_TYPE) {
> > > > > > > > > > > + ret = tegra_pcie_config_rp(pcie);
> > > > > > > > > > > + if (ret && ret != -ENOMEDIUM)
> > > > > > > > > > > + goto fail;
> > > > > > > > > > > + else
> > > > > > > > > > > + return 0;
> > > > > > > > > >
> > > > > > > > > > So if the link is not up we still go ahead and make probe
> > > > > > > > > > succeed. What for ?
> > > > > > > > > We may need root port to be available to support hot-plugging of
> > > > > > > > > endpoint devices, so, we don't fail the probe.
> > > > > > > >
> > > > > > > > We need it or we don't. If you do support hotplugging of endpoint
> > > > > > > > devices point me at the code, otherwise link up failure means
> > > > > > > > failure to probe.
> > > > > > > Currently hotplugging of endpoint is not supported, but it is one of
> > > > > > > the use cases that we may add support for in future.
> > > > > >
> > > > > > You should elaborate on this, I do not understand what you mean,
> > > > > > either the root port(s) supports hotplug or it does not.
> > > > > >
> > > > > > > But, why should we fail probe if link up doesn't happen? As such,
> > > > > > > nothing went wrong in terms of root port initialization right? I
> > > > > > > checked other DWC based implementations and following are not failing
> > > > > > > the probe pci-dra7xx.c, pcie-armada8k.c, pcie-artpec6.c, pcie-histb.c,
> > > > > > > pcie-kirin.c, pcie-spear13xx.c, pci-exynos.c, pci-imx6.c,
> > > > > > > pci-keystone.c, pci-layerscape.c
> > > > > > >
> > > > > > > Although following do fail the probe if link is not up. pcie-qcom.c,
> > > > > > > pcie-uniphier.c, pci-meson.c
> > > > > > >
> > > > > > > So, to me, it looks more like a choice we can make whether to fail the
> > > > > > > probe or not and in this case we are choosing not to fail.
> > > > > >
> > > > > > I disagree. I had an offline chat with Bjorn and whether link-up should
> > > > > > fail the probe or not depends on whether the root port(s) is hotplug
> > > > > > capable or not and this in turn relies on the root port "Slot
> > > > > > implemented" bit in the PCI Express capabilities register.
> > > > > >
> > > > > > It is a choice but it should be based on evidence.
> > > > > >
> > > > > > Lorenzo
> > > > > With Bjorn's latest comment on top of this, I think we are good not to fail
> > > > > the probe here.
> > > > >
> > > > > - Vidya Sagar
> > > > > >
> > > > >
> > >
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH 04/20] MAINTAINERS: Add new Marvell CN9130-based files to track
From: Miquel Raynal @ 2019-08-06 14:54 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: devicetree, Yan Markman, Antoine Tenart, Grzegorz Jaszczyk,
Gregory Clement, Maxime Chevallier, Nadav Haklai,
Thomas Petazzoni, Miquel Raynal, Stefan Chulski, Marcin Wojtas,
linux-arm-kernel
In-Reply-To: <20190806145500.24109-1-miquel.raynal@bootlin.com>
Marvell has a new branch of products called CN9130 based on AP807 and
CP115 which are derivatives of the currently supported AP806 and
CP110. Update the MAINTAINERS entry to reflect this change in the
naming.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
MAINTAINERS | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 783569e3c4b4..0d35614fc5e0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1865,7 +1865,7 @@ F: arch/arm/boot/dts/dove*
F: arch/arm/boot/dts/orion5x*
T: git git://git.infradead.org/linux-mvebu.git
-ARM/Marvell Kirkwood and Armada 370, 375, 38x, 39x, XP, 3700, 7K/8K SOC support
+ARM/Marvell Kirkwood and Armada 370, 375, 38x, 39x, XP, 3700, 7K/8K, CN9130 SOC support
M: Jason Cooper <jason@lakedaemon.net>
M: Andrew Lunn <andrew@lunn.ch>
M: Gregory Clement <gregory.clement@bootlin.com>
@@ -1877,6 +1877,7 @@ F: arch/arm/boot/dts/kirkwood*
F: arch/arm/configs/mvebu_*_defconfig
F: arch/arm/mach-mvebu/
F: arch/arm64/boot/dts/marvell/armada*
+F: arch/arm64/boot/dts/marvell/cn913*
F: drivers/cpufreq/armada-37xx-cpufreq.c
F: drivers/cpufreq/armada-8k-cpufreq.c
F: drivers/cpufreq/mvebu-cpufreq.c
--
2.20.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH 07/20] arm64: dts: marvell: Add support for AP807/AP807-quad
From: Miquel Raynal @ 2019-08-06 14:54 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: devicetree, Yan Markman, Antoine Tenart, Grzegorz Jaszczyk,
Gregory Clement, Maxime Chevallier, Nadav Haklai,
Thomas Petazzoni, Miquel Raynal, Stefan Chulski, Marcin Wojtas,
linux-arm-kernel
In-Reply-To: <20190806145500.24109-1-miquel.raynal@bootlin.com>
Describe AP807 and AP807-quad support.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
.../boot/dts/marvell/armada-ap807-quad.dtsi | 51 +++++++++++++++++++
arch/arm64/boot/dts/marvell/armada-ap807.dtsi | 29 +++++++++++
2 files changed, 80 insertions(+)
create mode 100644 arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
create mode 100644 arch/arm64/boot/dts/marvell/armada-ap807.dtsi
diff --git a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
new file mode 100644
index 000000000000..65364691257d
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree file for Marvell Armada AP807 Quad
+ *
+ * Copyright (C) 2019 Marvell Technology Group Ltd.
+ */
+
+#include "armada-ap807.dtsi"
+
+/ {
+ model = "Marvell Armada AP807 Quad";
+ compatible = "marvell,armada-ap807-quad", "marvell,armada-ap807";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x000>;
+ enable-method = "psci";
+ #cooling-cells = <2>;
+ clocks = <&cpu_clk 0>;
+ };
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x001>;
+ enable-method = "psci";
+ #cooling-cells = <2>;
+ clocks = <&cpu_clk 0>;
+ };
+ cpu2: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x100>;
+ enable-method = "psci";
+ #cooling-cells = <2>;
+ clocks = <&cpu_clk 1>;
+ };
+ cpu3: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72", "arm,armv8";
+ reg = <0x101>;
+ enable-method = "psci";
+ #cooling-cells = <2>;
+ clocks = <&cpu_clk 1>;
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/marvell/armada-ap807.dtsi b/arch/arm64/boot/dts/marvell/armada-ap807.dtsi
new file mode 100644
index 000000000000..623010f3ca89
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/armada-ap807.dtsi
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree file for Marvell Armada AP807
+ *
+ * Copyright (C) 2019 Marvell Technology Group Ltd.
+ */
+
+#define AP_NAME ap807
+#include "armada-ap80x.dtsi"
+
+/ {
+ model = "Marvell Armada AP807";
+ compatible = "marvell,armada-ap807";
+};
+
+&ap_syscon0 {
+ ap_clk: clock {
+ compatible = "marvell,ap807-clock";
+ #clock-cells = <1>;
+ };
+};
+
+&ap_syscon1 {
+ cpu_clk: clock-cpu {
+ compatible = "marvell,ap807-cpu-clock";
+ clocks = <&ap_clk 0>, <&ap_clk 1>;
+ #clock-cells = <1>;
+ };
+};
--
2.20.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH 06/20] arm64: dts: marvell: Move clocks to AP806 specific file
From: Miquel Raynal @ 2019-08-06 14:54 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: devicetree, Yan Markman, Antoine Tenart, Grzegorz Jaszczyk,
Gregory Clement, Maxime Chevallier, Nadav Haklai,
Thomas Petazzoni, Miquel Raynal, Stefan Chulski, Marcin Wojtas,
linux-arm-kernel
In-Reply-To: <20190806145500.24109-1-miquel.raynal@bootlin.com>
Regular clocks and CPU clocks are specific to AP806, move them out of
the generic AP80x file so that AP807 can use its own clocks.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 16 ++++++++++++++++
arch/arm64/boot/dts/marvell/armada-ap80x.dtsi | 12 ------------
2 files changed, 16 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
index cdadb28f287e..866628679ac7 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
@@ -12,3 +12,19 @@
model = "Marvell Armada AP806";
compatible = "marvell,armada-ap806";
};
+
+&ap_syscon0 {
+ ap_clk: clock {
+ compatible = "marvell,ap806-clock";
+ #clock-cells = <1>;
+ };
+};
+
+&ap_syscon1 {
+ cpu_clk: clock-cpu@278 {
+ compatible = "marvell,ap806-cpu-clock";
+ clocks = <&ap_clk 0>, <&ap_clk 1>;
+ #clock-cells = <1>;
+ reg = <0x278 0xa30>;
+ };
+};
diff --git a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
index c44cd7c64bf6..b74b5cf724be 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
@@ -248,11 +248,6 @@
compatible = "syscon", "simple-mfd";
reg = <0x6f4000 0x2000>;
- ap_clk: clock {
- compatible = "marvell,ap806-clock";
- #clock-cells = <1>;
- };
-
ap_pinctrl: pinctrl {
compatible = "marvell,ap806-pinctrl";
@@ -278,13 +273,6 @@
#address-cells = <1>;
#size-cells = <1>;
- cpu_clk: clock-cpu@278 {
- compatible = "marvell,ap806-cpu-clock";
- clocks = <&ap_clk 0>, <&ap_clk 1>;
- #clock-cells = <1>;
- reg = <0x278 0xa30>;
- };
-
ap_thermal: thermal-sensor@80 {
compatible = "marvell,armada-ap806-thermal";
reg = <0x80 0x10>;
--
2.20.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH 08/20] arm64: dts: marvell: Add AP806-dual cache description
From: Miquel Raynal @ 2019-08-06 14:54 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: devicetree, Yan Markman, Antoine Tenart, Grzegorz Jaszczyk,
Gregory Clement, Maxime Chevallier, Nadav Haklai,
Thomas Petazzoni, Miquel Raynal, Stefan Chulski, Marcin Wojtas,
linux-arm-kernel
In-Reply-To: <20190806145500.24109-1-miquel.raynal@bootlin.com>
From: Grzegorz Jaszczyk <jaz@semihalf.com>
Adding appropriate entries to device-tree allows the cache description
to show up in sysfs under: /sys/devices/system/cpu/cpuX/cache/.
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
.../boot/dts/marvell/armada-ap806-dual.dtsi | 21 +++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
index 62ae016ee6aa..09849558a776 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
@@ -22,6 +22,13 @@
enable-method = "psci";
#cooling-cells = <2>;
clocks = <&cpu_clk 0>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2>;
};
cpu1: cpu@1 {
device_type = "cpu";
@@ -30,6 +37,20 @@
enable-method = "psci";
#cooling-cells = <2>;
clocks = <&cpu_clk 0>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2>;
+ };
+
+ l2: l2-cache {
+ compatible = "cache";
+ cache-size = <0x80000>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
};
};
};
--
2.20.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH 09/20] arm64: dts: marvell: Add AP806-quad cache description
From: Miquel Raynal @ 2019-08-06 14:54 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: devicetree, Yan Markman, Antoine Tenart, Grzegorz Jaszczyk,
Gregory Clement, Maxime Chevallier, Nadav Haklai,
Thomas Petazzoni, Miquel Raynal, Stefan Chulski, Marcin Wojtas,
linux-arm-kernel
In-Reply-To: <20190806145500.24109-1-miquel.raynal@bootlin.com>
From: Grzegorz Jaszczyk <jaz@semihalf.com>
Adding appropriate entries to device-tree allows the cache description
to show up in sysfs under: /sys/devices/system/cpu/cpuX/cache/.
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
.../boot/dts/marvell/armada-ap806-quad.dtsi | 42 +++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
index 2f1a968b1b6b..2984bd9cf6ae 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
@@ -22,6 +22,13 @@
enable-method = "psci";
#cooling-cells = <2>;
clocks = <&cpu_clk 0>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_0>;
};
cpu1: cpu@1 {
device_type = "cpu";
@@ -30,6 +37,13 @@
enable-method = "psci";
#cooling-cells = <2>;
clocks = <&cpu_clk 0>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_0>;
};
cpu2: cpu@100 {
device_type = "cpu";
@@ -38,6 +52,13 @@
enable-method = "psci";
#cooling-cells = <2>;
clocks = <&cpu_clk 1>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_1>;
};
cpu3: cpu@101 {
device_type = "cpu";
@@ -46,6 +67,27 @@
enable-method = "psci";
#cooling-cells = <2>;
clocks = <&cpu_clk 1>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_1>;
+ };
+
+ l2_0: l2-cache0 {
+ compatible = "cache";
+ cache-size = <0x80000>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ };
+
+ l2_1: l2-cache1 {
+ compatible = "cache";
+ cache-size = <0x80000>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
};
};
--
2.20.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH 05/20] arm64: dts: marvell: Prepare the introduction of AP807 based SoCs
From: Miquel Raynal @ 2019-08-06 14:54 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: devicetree, Yan Markman, Antoine Tenart, Grzegorz Jaszczyk,
Gregory Clement, Maxime Chevallier, Nadav Haklai,
Thomas Petazzoni, Miquel Raynal, Konstantin Porotchkin,
Stefan Chulski, Marcin Wojtas, linux-arm-kernel
In-Reply-To: <20190806145500.24109-1-miquel.raynal@bootlin.com>
From: Konstantin Porotchkin <kostap@marvell.com>
Prepare the support for Marvell AP807 die. This die is very similar to
AP806 but uses different DDR PHY. AP807 is a major component of CN9130
SoC series.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 448 +----------------
arch/arm64/boot/dts/marvell/armada-ap80x.dtsi | 456 ++++++++++++++++++
2 files changed, 458 insertions(+), 446 deletions(-)
create mode 100644 arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
index a23ddd46efc5..cdadb28f287e 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
@@ -5,454 +5,10 @@
* Device Tree file for Marvell Armada AP806.
*/
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/thermal/thermal.h>
-
-/dts-v1/;
+#define AP_NAME ap806
+#include "armada-ap80x.dtsi"
/ {
model = "Marvell Armada AP806";
compatible = "marvell,armada-ap806";
- #address-cells = <2>;
- #size-cells = <2>;
-
- aliases {
- serial0 = &uart0;
- serial1 = &uart1;
- gpio0 = &ap_gpio;
- spi0 = &spi0;
- };
-
- psci {
- compatible = "arm,psci-0.2";
- method = "smc";
- };
-
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- /*
- * This area matches the mapping done with a
- * mainline U-Boot, and should be updated by the
- * bootloader.
- */
-
- psci-area@4000000 {
- reg = <0x0 0x4000000 0x0 0x200000>;
- no-map;
- };
- };
-
- ap806 {
- #address-cells = <2>;
- #size-cells = <2>;
- compatible = "simple-bus";
- interrupt-parent = <&gic>;
- ranges;
-
- config-space@f0000000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- ranges = <0x0 0x0 0xf0000000 0x1000000>;
-
- gic: interrupt-controller@210000 {
- compatible = "arm,gic-400";
- #interrupt-cells = <3>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- interrupt-controller;
- interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
- reg = <0x210000 0x10000>,
- <0x220000 0x20000>,
- <0x240000 0x20000>,
- <0x260000 0x20000>;
-
- gic_v2m0: v2m@280000 {
- compatible = "arm,gic-v2m-frame";
- msi-controller;
- reg = <0x280000 0x1000>;
- arm,msi-base-spi = <160>;
- arm,msi-num-spis = <32>;
- };
- gic_v2m1: v2m@290000 {
- compatible = "arm,gic-v2m-frame";
- msi-controller;
- reg = <0x290000 0x1000>;
- arm,msi-base-spi = <192>;
- arm,msi-num-spis = <32>;
- };
- gic_v2m2: v2m@2a0000 {
- compatible = "arm,gic-v2m-frame";
- msi-controller;
- reg = <0x2a0000 0x1000>;
- arm,msi-base-spi = <224>;
- arm,msi-num-spis = <32>;
- };
- gic_v2m3: v2m@2b0000 {
- compatible = "arm,gic-v2m-frame";
- msi-controller;
- reg = <0x2b0000 0x1000>;
- arm,msi-base-spi = <256>;
- arm,msi-num-spis = <32>;
- };
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
- };
-
- pmu {
- compatible = "arm,cortex-a72-pmu";
- interrupt-parent = <&pic>;
- interrupts = <17>;
- };
-
- odmi: odmi@300000 {
- compatible = "marvell,odmi-controller";
- interrupt-controller;
- msi-controller;
- marvell,odmi-frames = <4>;
- reg = <0x300000 0x4000>,
- <0x304000 0x4000>,
- <0x308000 0x4000>,
- <0x30C000 0x4000>;
- marvell,spi-base = <128>, <136>, <144>, <152>;
- };
-
- gicp: gicp@3f0040 {
- compatible = "marvell,ap806-gicp";
- reg = <0x3f0040 0x10>;
- marvell,spi-ranges = <64 64>, <288 64>;
- msi-controller;
- };
-
- pic: interrupt-controller@3f0100 {
- compatible = "marvell,armada-8k-pic";
- reg = <0x3f0100 0x10>;
- #interrupt-cells = <1>;
- interrupt-controller;
- interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- sei: interrupt-controller@3f0200 {
- compatible = "marvell,ap806-sei";
- reg = <0x3f0200 0x40>;
- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
- #interrupt-cells = <1>;
- interrupt-controller;
- msi-controller;
- };
-
- xor@400000 {
- compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
- reg = <0x400000 0x1000>,
- <0x410000 0x1000>;
- msi-parent = <&gic_v2m0>;
- clocks = <&ap_clk 3>;
- dma-coherent;
- };
-
- xor@420000 {
- compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
- reg = <0x420000 0x1000>,
- <0x430000 0x1000>;
- msi-parent = <&gic_v2m0>;
- clocks = <&ap_clk 3>;
- dma-coherent;
- };
-
- xor@440000 {
- compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
- reg = <0x440000 0x1000>,
- <0x450000 0x1000>;
- msi-parent = <&gic_v2m0>;
- clocks = <&ap_clk 3>;
- dma-coherent;
- };
-
- xor@460000 {
- compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
- reg = <0x460000 0x1000>,
- <0x470000 0x1000>;
- msi-parent = <&gic_v2m0>;
- clocks = <&ap_clk 3>;
- dma-coherent;
- };
-
- spi0: spi@510600 {
- compatible = "marvell,armada-380-spi";
- reg = <0x510600 0x50>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&ap_clk 3>;
- status = "disabled";
- };
-
- i2c0: i2c@511000 {
- compatible = "marvell,mv78230-i2c";
- reg = <0x511000 0x20>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
- timeout-ms = <1000>;
- clocks = <&ap_clk 3>;
- status = "disabled";
- };
-
- uart0: serial@512000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x512000 0x100>;
- reg-shift = <2>;
- interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
- reg-io-width = <1>;
- clocks = <&ap_clk 3>;
- status = "disabled";
- };
-
- uart1: serial@512100 {
- compatible = "snps,dw-apb-uart";
- reg = <0x512100 0x100>;
- reg-shift = <2>;
- interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
- reg-io-width = <1>;
- clocks = <&ap_clk 3>;
- status = "disabled";
-
- };
-
- watchdog: watchdog@610000 {
- compatible = "arm,sbsa-gwdt";
- reg = <0x610000 0x1000>, <0x600000 0x1000>;
- interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- ap_sdhci0: sdhci@6e0000 {
- compatible = "marvell,armada-ap806-sdhci";
- reg = <0x6e0000 0x300>;
- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "core";
- clocks = <&ap_clk 4>;
- dma-coherent;
- marvell,xenon-phy-slow-mode;
- status = "disabled";
- };
-
- ap_syscon0: system-controller@6f4000 {
- compatible = "syscon", "simple-mfd";
- reg = <0x6f4000 0x2000>;
-
- ap_clk: clock {
- compatible = "marvell,ap806-clock";
- #clock-cells = <1>;
- };
-
- ap_pinctrl: pinctrl {
- compatible = "marvell,ap806-pinctrl";
-
- uart0_pins: uart0-pins {
- marvell,pins = "mpp11", "mpp19";
- marvell,function = "uart0";
- };
- };
-
- ap_gpio: gpio@1040 {
- compatible = "marvell,armada-8k-gpio";
- offset = <0x1040>;
- ngpios = <20>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&ap_pinctrl 0 0 20>;
- };
- };
-
- ap_syscon1: system-controller@6f8000 {
- compatible = "syscon", "simple-mfd";
- reg = <0x6f8000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- cpu_clk: clock-cpu@278 {
- compatible = "marvell,ap806-cpu-clock";
- clocks = <&ap_clk 0>, <&ap_clk 1>;
- #clock-cells = <1>;
- reg = <0x278 0xa30>;
- };
-
- ap_thermal: thermal-sensor@80 {
- compatible = "marvell,armada-ap806-thermal";
- reg = <0x80 0x10>;
- interrupt-parent = <&sei>;
- interrupts = <18>;
- #thermal-sensor-cells = <1>;
- };
- };
- };
- };
-
- /*
- * The thermal IP features one internal sensor plus, if applicable, one
- * remote channel wired to one sensor per CPU.
- *
- * Only one thermal zone per AP/CP may trigger interrupts at a time, the
- * first one that will have a critical trip point will be chosen.
- */
- thermal-zones {
- ap_thermal_ic: ap-thermal-ic {
- polling-delay-passive = <0>; /* Interrupt driven */
- polling-delay = <0>; /* Interrupt driven */
-
- thermal-sensors = <&ap_thermal 0>;
-
- trips {
- ap_crit: ap-crit {
- temperature = <100000>; /* mC degrees */
- hysteresis = <2000>; /* mC degrees */
- type = "critical";
- };
- };
-
- cooling-maps { };
- };
-
- ap_thermal_cpu0: ap-thermal-cpu0 {
- polling-delay-passive = <1000>;
- polling-delay = <1000>;
-
- thermal-sensors = <&ap_thermal 1>;
-
- trips {
- cpu0_hot: cpu0-hot {
- temperature = <85000>;
- hysteresis = <2000>;
- type = "passive";
- };
- cpu0_emerg: cpu0-emerg {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "passive";
- };
- };
-
- cooling-maps {
- map0_hot: map0-hot {
- trip = <&cpu0_hot>;
- cooling-device = <&cpu0 1 2>,
- <&cpu1 1 2>;
- };
- map0_emerg: map0-ermerg {
- trip = <&cpu0_emerg>;
- cooling-device = <&cpu0 3 3>,
- <&cpu1 3 3>;
- };
- };
- };
-
- ap_thermal_cpu1: ap-thermal-cpu1 {
- polling-delay-passive = <1000>;
- polling-delay = <1000>;
-
- thermal-sensors = <&ap_thermal 2>;
-
- trips {
- cpu1_hot: cpu1-hot {
- temperature = <85000>;
- hysteresis = <2000>;
- type = "passive";
- };
- cpu1_emerg: cpu1-emerg {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "passive";
- };
- };
-
- cooling-maps {
- map1_hot: map1-hot {
- trip = <&cpu1_hot>;
- cooling-device = <&cpu0 1 2>,
- <&cpu1 1 2>;
- };
- map1_emerg: map1-emerg {
- trip = <&cpu1_emerg>;
- cooling-device = <&cpu0 3 3>,
- <&cpu1 3 3>;
- };
- };
- };
-
- ap_thermal_cpu2: ap-thermal-cpu2 {
- polling-delay-passive = <1000>;
- polling-delay = <1000>;
-
- thermal-sensors = <&ap_thermal 3>;
-
- trips {
- cpu2_hot: cpu2-hot {
- temperature = <85000>;
- hysteresis = <2000>;
- type = "passive";
- };
- cpu2_emerg: cpu2-emerg {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "passive";
- };
- };
-
- cooling-maps {
- map2_hot: map2-hot {
- trip = <&cpu2_hot>;
- cooling-device = <&cpu2 1 2>,
- <&cpu3 1 2>;
- };
- map2_emerg: map2-emerg {
- trip = <&cpu2_emerg>;
- cooling-device = <&cpu2 3 3>,
- <&cpu3 3 3>;
- };
- };
- };
-
- ap_thermal_cpu3: ap-thermal-cpu3 {
- polling-delay-passive = <1000>;
- polling-delay = <1000>;
-
- thermal-sensors = <&ap_thermal 4>;
-
- trips {
- cpu3_hot: cpu3-hot {
- temperature = <85000>;
- hysteresis = <2000>;
- type = "passive";
- };
- cpu3_emerg: cpu3-emerg {
- temperature = <95000>;
- hysteresis = <2000>;
- type = "passive";
- };
- };
-
- cooling-maps {
- map3_hot: map3-bhot {
- trip = <&cpu3_hot>;
- cooling-device = <&cpu2 1 2>,
- <&cpu3 1 2>;
- };
- map3_emerg: map3-emerg {
- trip = <&cpu3_emerg>;
- cooling-device = <&cpu2 3 3>,
- <&cpu3 3 3>;
- };
- };
- };
- };
};
diff --git a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
new file mode 100644
index 000000000000..c44cd7c64bf6
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
@@ -0,0 +1,456 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 Marvell Technology Group Ltd.
+ *
+ * Device Tree file for Marvell Armada AP80x.
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/thermal/thermal.h>
+
+/dts-v1/;
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ gpio0 = &ap_gpio;
+ spi0 = &spi0;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /*
+ * This area matches the mapping done with a
+ * mainline U-Boot, and should be updated by the
+ * bootloader.
+ */
+
+ psci-area@4000000 {
+ reg = <0x0 0x4000000 0x0 0x200000>;
+ no-map;
+ };
+ };
+
+ ap806 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges;
+
+ config-space@f0000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x0 0x0 0xf0000000 0x1000000>;
+
+ gic: interrupt-controller@210000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ reg = <0x210000 0x10000>,
+ <0x220000 0x20000>,
+ <0x240000 0x20000>,
+ <0x260000 0x20000>;
+
+ gic_v2m0: v2m@280000 {
+ compatible = "arm,gic-v2m-frame";
+ msi-controller;
+ reg = <0x280000 0x1000>;
+ arm,msi-base-spi = <160>;
+ arm,msi-num-spis = <32>;
+ };
+ gic_v2m1: v2m@290000 {
+ compatible = "arm,gic-v2m-frame";
+ msi-controller;
+ reg = <0x290000 0x1000>;
+ arm,msi-base-spi = <192>;
+ arm,msi-num-spis = <32>;
+ };
+ gic_v2m2: v2m@2a0000 {
+ compatible = "arm,gic-v2m-frame";
+ msi-controller;
+ reg = <0x2a0000 0x1000>;
+ arm,msi-base-spi = <224>;
+ arm,msi-num-spis = <32>;
+ };
+ gic_v2m3: v2m@2b0000 {
+ compatible = "arm,gic-v2m-frame";
+ msi-controller;
+ reg = <0x2b0000 0x1000>;
+ arm,msi-base-spi = <256>;
+ arm,msi-num-spis = <32>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a72-pmu";
+ interrupt-parent = <&pic>;
+ interrupts = <17>;
+ };
+
+ odmi: odmi@300000 {
+ compatible = "marvell,odmi-controller";
+ interrupt-controller;
+ msi-controller;
+ marvell,odmi-frames = <4>;
+ reg = <0x300000 0x4000>,
+ <0x304000 0x4000>,
+ <0x308000 0x4000>,
+ <0x30C000 0x4000>;
+ marvell,spi-base = <128>, <136>, <144>, <152>;
+ };
+
+ gicp: gicp@3f0040 {
+ compatible = "marvell,ap806-gicp";
+ reg = <0x3f0040 0x10>;
+ marvell,spi-ranges = <64 64>, <288 64>;
+ msi-controller;
+ };
+
+ pic: interrupt-controller@3f0100 {
+ compatible = "marvell,armada-8k-pic";
+ reg = <0x3f0100 0x10>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sei: interrupt-controller@3f0200 {
+ compatible = "marvell,ap806-sei";
+ reg = <0x3f0200 0x40>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ msi-controller;
+ };
+
+ xor@400000 {
+ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
+ reg = <0x400000 0x1000>,
+ <0x410000 0x1000>;
+ msi-parent = <&gic_v2m0>;
+ clocks = <&ap_clk 3>;
+ dma-coherent;
+ };
+
+ xor@420000 {
+ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
+ reg = <0x420000 0x1000>,
+ <0x430000 0x1000>;
+ msi-parent = <&gic_v2m0>;
+ clocks = <&ap_clk 3>;
+ dma-coherent;
+ };
+
+ xor@440000 {
+ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
+ reg = <0x440000 0x1000>,
+ <0x450000 0x1000>;
+ msi-parent = <&gic_v2m0>;
+ clocks = <&ap_clk 3>;
+ dma-coherent;
+ };
+
+ xor@460000 {
+ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
+ reg = <0x460000 0x1000>,
+ <0x470000 0x1000>;
+ msi-parent = <&gic_v2m0>;
+ clocks = <&ap_clk 3>;
+ dma-coherent;
+ };
+
+ spi0: spi@510600 {
+ compatible = "marvell,armada-380-spi";
+ reg = <0x510600 0x50>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ap_clk 3>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@511000 {
+ compatible = "marvell,mv78230-i2c";
+ reg = <0x511000 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ timeout-ms = <1000>;
+ clocks = <&ap_clk 3>;
+ status = "disabled";
+ };
+
+ uart0: serial@512000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x512000 0x100>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <1>;
+ clocks = <&ap_clk 3>;
+ status = "disabled";
+ };
+
+ uart1: serial@512100 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x512100 0x100>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <1>;
+ clocks = <&ap_clk 3>;
+ status = "disabled";
+
+ };
+
+ watchdog: watchdog@610000 {
+ compatible = "arm,sbsa-gwdt";
+ reg = <0x610000 0x1000>, <0x600000 0x1000>;
+ interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ ap_sdhci0: sdhci@6e0000 {
+ compatible = "marvell,armada-ap806-sdhci";
+ reg = <0x6e0000 0x300>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core";
+ clocks = <&ap_clk 4>;
+ dma-coherent;
+ marvell,xenon-phy-slow-mode;
+ status = "disabled";
+ };
+
+ ap_syscon0: system-controller@6f4000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x6f4000 0x2000>;
+
+ ap_clk: clock {
+ compatible = "marvell,ap806-clock";
+ #clock-cells = <1>;
+ };
+
+ ap_pinctrl: pinctrl {
+ compatible = "marvell,ap806-pinctrl";
+
+ uart0_pins: uart0-pins {
+ marvell,pins = "mpp11", "mpp19";
+ marvell,function = "uart0";
+ };
+ };
+
+ ap_gpio: gpio@1040 {
+ compatible = "marvell,armada-8k-gpio";
+ offset = <0x1040>;
+ ngpios = <20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&ap_pinctrl 0 0 20>;
+ };
+ };
+
+ ap_syscon1: system-controller@6f8000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x6f8000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpu_clk: clock-cpu@278 {
+ compatible = "marvell,ap806-cpu-clock";
+ clocks = <&ap_clk 0>, <&ap_clk 1>;
+ #clock-cells = <1>;
+ reg = <0x278 0xa30>;
+ };
+
+ ap_thermal: thermal-sensor@80 {
+ compatible = "marvell,armada-ap806-thermal";
+ reg = <0x80 0x10>;
+ interrupt-parent = <&sei>;
+ interrupts = <18>;
+ #thermal-sensor-cells = <1>;
+ };
+ };
+ };
+ };
+
+ /*
+ * The thermal IP features one internal sensor plus, if applicable, one
+ * remote channel wired to one sensor per CPU.
+ *
+ * Only one thermal zone per AP/CP may trigger interrupts at a time, the
+ * first one that will have a critical trip point will be chosen.
+ */
+ thermal-zones {
+ ap_thermal_ic: ap-thermal-ic {
+ polling-delay-passive = <0>; /* Interrupt driven */
+ polling-delay = <0>; /* Interrupt driven */
+
+ thermal-sensors = <&ap_thermal 0>;
+
+ trips {
+ ap_crit: ap-crit {
+ temperature = <100000>; /* mC degrees */
+ hysteresis = <2000>; /* mC degrees */
+ type = "critical";
+ };
+ };
+
+ cooling-maps { };
+ };
+
+ ap_thermal_cpu0: ap-thermal-cpu0 {
+ polling-delay-passive = <1000>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&ap_thermal 1>;
+
+ trips {
+ cpu0_hot: cpu0-hot {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu0_emerg: cpu0-emerg {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ map0_hot: map0-hot {
+ trip = <&cpu0_hot>;
+ cooling-device = <&cpu0 1 2>,
+ <&cpu1 1 2>;
+ };
+ map0_emerg: map0-ermerg {
+ trip = <&cpu0_emerg>;
+ cooling-device = <&cpu0 3 3>,
+ <&cpu1 3 3>;
+ };
+ };
+ };
+
+ ap_thermal_cpu1: ap-thermal-cpu1 {
+ polling-delay-passive = <1000>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&ap_thermal 2>;
+
+ trips {
+ cpu1_hot: cpu1-hot {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu1_emerg: cpu1-emerg {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ map1_hot: map1-hot {
+ trip = <&cpu1_hot>;
+ cooling-device = <&cpu0 1 2>,
+ <&cpu1 1 2>;
+ };
+ map1_emerg: map1-emerg {
+ trip = <&cpu1_emerg>;
+ cooling-device = <&cpu0 3 3>,
+ <&cpu1 3 3>;
+ };
+ };
+ };
+
+ ap_thermal_cpu2: ap-thermal-cpu2 {
+ polling-delay-passive = <1000>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&ap_thermal 3>;
+
+ trips {
+ cpu2_hot: cpu2-hot {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu2_emerg: cpu2-emerg {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ map2_hot: map2-hot {
+ trip = <&cpu2_hot>;
+ cooling-device = <&cpu2 1 2>,
+ <&cpu3 1 2>;
+ };
+ map2_emerg: map2-emerg {
+ trip = <&cpu2_emerg>;
+ cooling-device = <&cpu2 3 3>,
+ <&cpu3 3 3>;
+ };
+ };
+ };
+
+ ap_thermal_cpu3: ap-thermal-cpu3 {
+ polling-delay-passive = <1000>;
+ polling-delay = <1000>;
+
+ thermal-sensors = <&ap_thermal 4>;
+
+ trips {
+ cpu3_hot: cpu3-hot {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu3_emerg: cpu3-emerg {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ map3_hot: map3-bhot {
+ trip = <&cpu3_hot>;
+ cooling-device = <&cpu2 1 2>,
+ <&cpu3 1 2>;
+ };
+ map3_emerg: map3-emerg {
+ trip = <&cpu3_emerg>;
+ cooling-device = <&cpu2 3 3>,
+ <&cpu3 3 3>;
+ };
+ };
+ };
+ };
+};
--
2.20.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH 11/20] arm64: dts: marvell: Fix CP110 NAND controller node multi-line comment alignment
From: Miquel Raynal @ 2019-08-06 14:54 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: devicetree, Yan Markman, Antoine Tenart, Grzegorz Jaszczyk,
Gregory Clement, Maxime Chevallier, Nadav Haklai,
Thomas Petazzoni, Miquel Raynal, Stefan Chulski, Marcin Wojtas,
linux-arm-kernel
In-Reply-To: <20190806145500.24109-1-miquel.raynal@bootlin.com>
Fix this tiny typo before renaming/changing this file.
Fixes: 72a3713fadfd ("arm64: dts: marvell: de-duplicate CP110 description")
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
index d81944902650..8259fc8f86f2 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
@@ -438,10 +438,10 @@
CP110_LABEL(nand_controller): nand@720000 {
/*
- * Due to the limitation of the pins available
- * this controller is only usable on the CPM
- * for A7K and on the CPS for A8K.
- */
+ * Due to the limitation of the pins available
+ * this controller is only usable on the CPM
+ * for A7K and on the CPS for A8K.
+ */
compatible = "marvell,armada-8k-nand-controller",
"marvell,armada370-nand-controller";
reg = <0x720000 0x54>;
--
2.20.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH 10/20] arm64: dts: marvell: Add AP807-quad cache description
From: Miquel Raynal @ 2019-08-06 14:54 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: devicetree, Yan Markman, Antoine Tenart, Grzegorz Jaszczyk,
Gregory Clement, Maxime Chevallier, Nadav Haklai,
Thomas Petazzoni, Miquel Raynal, Stefan Chulski, Marcin Wojtas,
linux-arm-kernel
In-Reply-To: <20190806145500.24109-1-miquel.raynal@bootlin.com>
From: Grzegorz Jaszczyk <jaz@semihalf.com>
Adding appropriate entries to device-tree allows the cache description
to show up in sysfs under: /sys/devices/system/cpu/cpuX/cache/.
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
.../boot/dts/marvell/armada-ap807-quad.dtsi | 42 +++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
index 65364691257d..840466e143b4 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
@@ -22,6 +22,13 @@
enable-method = "psci";
#cooling-cells = <2>;
clocks = <&cpu_clk 0>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_0>;
};
cpu1: cpu@1 {
device_type = "cpu";
@@ -30,6 +37,13 @@
enable-method = "psci";
#cooling-cells = <2>;
clocks = <&cpu_clk 0>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_0>;
};
cpu2: cpu@100 {
device_type = "cpu";
@@ -38,6 +52,13 @@
enable-method = "psci";
#cooling-cells = <2>;
clocks = <&cpu_clk 1>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_1>;
};
cpu3: cpu@101 {
device_type = "cpu";
@@ -46,6 +67,27 @@
enable-method = "psci";
#cooling-cells = <2>;
clocks = <&cpu_clk 1>;
+ i-cache-size = <0xc000>;
+ i-cache-line-size = <64>;
+ i-cache-sets = <256>;
+ d-cache-size = <0x8000>;
+ d-cache-line-size = <64>;
+ d-cache-sets = <256>;
+ next-level-cache = <&l2_1>;
+ };
+
+ l2_0: l2-cache0 {
+ compatible = "cache";
+ cache-size = <0x80000>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
+ };
+
+ l2_1: l2-cache1 {
+ compatible = "cache";
+ cache-size = <0x80000>;
+ cache-line-size = <64>;
+ cache-sets = <512>;
};
};
};
--
2.20.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH 12/20] arm64: dts: marvell: Prepare the introduction of CP115
From: Miquel Raynal @ 2019-08-06 14:54 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: devicetree, Yan Markman, Antoine Tenart, Grzegorz Jaszczyk,
Gregory Clement, Maxime Chevallier, Nadav Haklai,
Thomas Petazzoni, Miquel Raynal, Stefan Chulski, Marcin Wojtas,
linux-arm-kernel
In-Reply-To: <20190806145500.24109-1-miquel.raynal@bootlin.com>
CP110 and CP115 are almost the same in terms of features and have a
very limited set of differences. Let's create an armada-cp11x.dtsi
file which will be used to instantiate both CP110 and CP115
nodes.
The only changes between the two armada-cp11{0,x}.dtsi files are the
following naming in macros: s/CP110/CP11X/.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 28 +-
arch/arm64/boot/dts/marvell/armada-80x0.dtsi | 56 +-
.../arm64/boot/dts/marvell/armada-common.dtsi | 4 +-
arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 575 +----------------
arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 579 ++++++++++++++++++
5 files changed, 627 insertions(+), 615 deletions(-)
create mode 100644 arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
index e5c6d7c25819..4e78ccd207b7 100644
--- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
@@ -17,23 +17,23 @@
/*
* Instantiate the CP110
*/
-#define CP110_NAME cp0
-#define CP110_BASE f2000000
-#define CP110_PCIE_IO_BASE 0xf9000000
-#define CP110_PCIE_MEM_BASE 0xf6000000
-#define CP110_PCIE0_BASE f2600000
-#define CP110_PCIE1_BASE f2620000
-#define CP110_PCIE2_BASE f2640000
+#define CP11X_NAME cp0
+#define CP11X_BASE f2000000
+#define CP11X_PCIE_IO_BASE 0xf9000000
+#define CP11X_PCIE_MEM_BASE 0xf6000000
+#define CP11X_PCIE0_BASE f2600000
+#define CP11X_PCIE1_BASE f2620000
+#define CP11X_PCIE2_BASE f2640000
#include "armada-cp110.dtsi"
-#undef CP110_NAME
-#undef CP110_BASE
-#undef CP110_PCIE_IO_BASE
-#undef CP110_PCIE_MEM_BASE
-#undef CP110_PCIE0_BASE
-#undef CP110_PCIE1_BASE
-#undef CP110_PCIE2_BASE
+#undef CP11X_NAME
+#undef CP11X_BASE
+#undef CP11X_PCIE_IO_BASE
+#undef CP11X_PCIE_MEM_BASE
+#undef CP11X_PCIE0_BASE
+#undef CP11X_PCIE1_BASE
+#undef CP11X_PCIE2_BASE
&cp0_gpio1 {
status = "okay";
diff --git a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
index 8129b40f12a4..ebb98836ec9c 100644
--- a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
@@ -19,44 +19,44 @@
/*
* Instantiate the master CP110
*/
-#define CP110_NAME cp0
-#define CP110_BASE f2000000
-#define CP110_PCIE_IO_BASE 0xf9000000
-#define CP110_PCIE_MEM_BASE 0xf6000000
-#define CP110_PCIE0_BASE f2600000
-#define CP110_PCIE1_BASE f2620000
-#define CP110_PCIE2_BASE f2640000
+#define CP11X_NAME cp0
+#define CP11X_BASE f2000000
+#define CP11X_PCIE_IO_BASE 0xf9000000
+#define CP11X_PCIE_MEM_BASE 0xf6000000
+#define CP11X_PCIE0_BASE f2600000
+#define CP11X_PCIE1_BASE f2620000
+#define CP11X_PCIE2_BASE f2640000
#include "armada-cp110.dtsi"
-#undef CP110_NAME
-#undef CP110_BASE
-#undef CP110_PCIE_IO_BASE
-#undef CP110_PCIE_MEM_BASE
-#undef CP110_PCIE0_BASE
-#undef CP110_PCIE1_BASE
-#undef CP110_PCIE2_BASE
+#undef CP11X_NAME
+#undef CP11X_BASE
+#undef CP11X_PCIE_IO_BASE
+#undef CP11X_PCIE_MEM_BASE
+#undef CP11X_PCIE0_BASE
+#undef CP11X_PCIE1_BASE
+#undef CP11X_PCIE2_BASE
/*
* Instantiate the slave CP110
*/
-#define CP110_NAME cp1
-#define CP110_BASE f4000000
-#define CP110_PCIE_IO_BASE 0xfd000000
-#define CP110_PCIE_MEM_BASE 0xfa000000
-#define CP110_PCIE0_BASE f4600000
-#define CP110_PCIE1_BASE f4620000
-#define CP110_PCIE2_BASE f4640000
+#define CP11X_NAME cp1
+#define CP11X_BASE f4000000
+#define CP11X_PCIE_IO_BASE 0xfd000000
+#define CP11X_PCIE_MEM_BASE 0xfa000000
+#define CP11X_PCIE0_BASE f4600000
+#define CP11X_PCIE1_BASE f4620000
+#define CP11X_PCIE2_BASE f4640000
#include "armada-cp110.dtsi"
-#undef CP110_NAME
-#undef CP110_BASE
-#undef CP110_PCIE_IO_BASE
-#undef CP110_PCIE_MEM_BASE
-#undef CP110_PCIE0_BASE
-#undef CP110_PCIE1_BASE
-#undef CP110_PCIE2_BASE
+#undef CP11X_NAME
+#undef CP11X_BASE
+#undef CP11X_PCIE_IO_BASE
+#undef CP11X_PCIE_MEM_BASE
+#undef CP11X_PCIE0_BASE
+#undef CP11X_PCIE1_BASE
+#undef CP11X_PCIE2_BASE
/* The 80x0 has two CP blocks, but uses only one block from each. */
&cp1_gpio1 {
diff --git a/arch/arm64/boot/dts/marvell/armada-common.dtsi b/arch/arm64/boot/dts/marvell/armada-common.dtsi
index b29c6405d214..c04c6c475022 100644
--- a/arch/arm64/boot/dts/marvell/armada-common.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-common.dtsi
@@ -6,6 +6,6 @@
/* Common definitions used by Armada 7K/8K DTs */
#define PASTER(x, y) x ## y
#define EVALUATOR(x, y) PASTER(x, y)
-#define CP110_LABEL(name) EVALUATOR(CP110_NAME, EVALUATOR(_, name))
-#define CP110_NODE_NAME(name) EVALUATOR(CP110_NAME, EVALUATOR(-, name))
+#define CP11X_LABEL(name) EVALUATOR(CP11X_NAME, EVALUATOR(_, name))
+#define CP11X_NODE_NAME(name) EVALUATOR(CP11X_NAME, EVALUATOR(-, name))
#define ADDRESSIFY(addr) EVALUATOR(0x, addr)
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
index 8259fc8f86f2..4fd33b0fa56e 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
@@ -1,579 +1,12 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Copyright (C) 2016 Marvell Technology Group Ltd.
+ * Copyright (C) 2019 Marvell Technology Group Ltd.
*
* Device Tree file for Marvell Armada CP110.
*/
-#include <dt-bindings/interrupt-controller/mvebu-icu.h>
-#include <dt-bindings/thermal/thermal.h>
+#define CP11X_TYPE cp110
-#include "armada-common.dtsi"
+#include "armada-cp11x.dtsi"
-#define CP110_PCIEx_IO_BASE(iface) (CP110_PCIE_IO_BASE + (iface * 0x10000))
-#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIE_MEM_BASE + (iface * 0x1000000))
-#define CP110_PCIEx_CONF_BASE(iface) (CP110_PCIEx_MEM_BASE(iface) + 0xf00000)
-
-/ {
- /*
- * The contents of the node are defined below, in order to
- * save one indentation level
- */
- CP110_NAME: CP110_NAME { };
-
- /*
- * CPs only have one sensor in the thermal IC.
- *
- * The cooling maps are empty as there are no cooling devices.
- */
- thermal-zones {
- CP110_LABEL(thermal_ic): CP110_NODE_NAME(thermal-ic) {
- polling-delay-passive = <0>; /* Interrupt driven */
- polling-delay = <0>; /* Interrupt driven */
-
- thermal-sensors = <&CP110_LABEL(thermal) 0>;
-
- trips {
- CP110_LABEL(crit): crit {
- temperature = <100000>; /* mC degrees */
- hysteresis = <2000>; /* mC degrees */
- type = "critical";
- };
- };
-
- cooling-maps { };
- };
- };
-};
-
-&CP110_NAME {
- #address-cells = <2>;
- #size-cells = <2>;
- compatible = "simple-bus";
- interrupt-parent = <&CP110_LABEL(icu_nsr)>;
- ranges;
-
- config-space@CP110_BASE {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- ranges = <0x0 0x0 ADDRESSIFY(CP110_BASE) 0x2000000>;
-
- CP110_LABEL(ethernet): ethernet@0 {
- compatible = "marvell,armada-7k-pp22";
- reg = <0x0 0x100000>, <0x129000 0xb000>;
- clocks = <&CP110_LABEL(clk) 1 3>, <&CP110_LABEL(clk) 1 9>,
- <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 6>,
- <&CP110_LABEL(clk) 1 18>;
- clock-names = "pp_clk", "gop_clk",
- "mg_clk", "mg_core_clk", "axi_clk";
- marvell,system-controller = <&CP110_LABEL(syscon0)>;
- status = "disabled";
- dma-coherent;
-
- CP110_LABEL(eth0): eth0 {
- interrupts = <39 IRQ_TYPE_LEVEL_HIGH>,
- <43 IRQ_TYPE_LEVEL_HIGH>,
- <47 IRQ_TYPE_LEVEL_HIGH>,
- <51 IRQ_TYPE_LEVEL_HIGH>,
- <55 IRQ_TYPE_LEVEL_HIGH>,
- <59 IRQ_TYPE_LEVEL_HIGH>,
- <63 IRQ_TYPE_LEVEL_HIGH>,
- <67 IRQ_TYPE_LEVEL_HIGH>,
- <71 IRQ_TYPE_LEVEL_HIGH>,
- <129 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hif0", "hif1", "hif2",
- "hif3", "hif4", "hif5", "hif6", "hif7",
- "hif8", "link";
- port-id = <0>;
- gop-port-id = <0>;
- status = "disabled";
- };
-
- CP110_LABEL(eth1): eth1 {
- interrupts = <40 IRQ_TYPE_LEVEL_HIGH>,
- <44 IRQ_TYPE_LEVEL_HIGH>,
- <48 IRQ_TYPE_LEVEL_HIGH>,
- <52 IRQ_TYPE_LEVEL_HIGH>,
- <56 IRQ_TYPE_LEVEL_HIGH>,
- <60 IRQ_TYPE_LEVEL_HIGH>,
- <64 IRQ_TYPE_LEVEL_HIGH>,
- <68 IRQ_TYPE_LEVEL_HIGH>,
- <72 IRQ_TYPE_LEVEL_HIGH>,
- <128 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hif0", "hif1", "hif2",
- "hif3", "hif4", "hif5", "hif6", "hif7",
- "hif8", "link";
- port-id = <1>;
- gop-port-id = <2>;
- status = "disabled";
- };
-
- CP110_LABEL(eth2): eth2 {
- interrupts = <41 IRQ_TYPE_LEVEL_HIGH>,
- <45 IRQ_TYPE_LEVEL_HIGH>,
- <49 IRQ_TYPE_LEVEL_HIGH>,
- <53 IRQ_TYPE_LEVEL_HIGH>,
- <57 IRQ_TYPE_LEVEL_HIGH>,
- <61 IRQ_TYPE_LEVEL_HIGH>,
- <65 IRQ_TYPE_LEVEL_HIGH>,
- <69 IRQ_TYPE_LEVEL_HIGH>,
- <73 IRQ_TYPE_LEVEL_HIGH>,
- <127 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hif0", "hif1", "hif2",
- "hif3", "hif4", "hif5", "hif6", "hif7",
- "hif8", "link";
- port-id = <2>;
- gop-port-id = <3>;
- status = "disabled";
- };
- };
-
- CP110_LABEL(comphy): phy@120000 {
- compatible = "marvell,comphy-cp110";
- reg = <0x120000 0x6000>;
- marvell,system-controller = <&CP110_LABEL(syscon0)>;
- clocks = <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 6>,
- <&CP110_LABEL(clk) 1 18>;
- clock-names = "mg_clk", "mg_core_clk", "axi_clk";
- #address-cells = <1>;
- #size-cells = <0>;
-
- CP110_LABEL(comphy0): phy@0 {
- reg = <0>;
- #phy-cells = <1>;
- };
-
- CP110_LABEL(comphy1): phy@1 {
- reg = <1>;
- #phy-cells = <1>;
- };
-
- CP110_LABEL(comphy2): phy@2 {
- reg = <2>;
- #phy-cells = <1>;
- };
-
- CP110_LABEL(comphy3): phy@3 {
- reg = <3>;
- #phy-cells = <1>;
- };
-
- CP110_LABEL(comphy4): phy@4 {
- reg = <4>;
- #phy-cells = <1>;
- };
-
- CP110_LABEL(comphy5): phy@5 {
- reg = <5>;
- #phy-cells = <1>;
- };
- };
-
- CP110_LABEL(mdio): mdio@12a200 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "marvell,orion-mdio";
- reg = <0x12a200 0x10>;
- clocks = <&CP110_LABEL(clk) 1 9>, <&CP110_LABEL(clk) 1 5>,
- <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>;
- status = "disabled";
- };
-
- CP110_LABEL(xmdio): mdio@12a600 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "marvell,xmdio";
- reg = <0x12a600 0x10>;
- clocks = <&CP110_LABEL(clk) 1 5>,
- <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>;
- status = "disabled";
- };
-
- CP110_LABEL(icu): interrupt-controller@1e0000 {
- compatible = "marvell,cp110-icu";
- reg = <0x1e0000 0x440>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- CP110_LABEL(icu_nsr): interrupt-controller@10 {
- compatible = "marvell,cp110-icu-nsr";
- reg = <0x10 0x20>;
- #interrupt-cells = <2>;
- interrupt-controller;
- msi-parent = <&gicp>;
- };
-
- CP110_LABEL(icu_sei): interrupt-controller@50 {
- compatible = "marvell,cp110-icu-sei";
- reg = <0x50 0x10>;
- #interrupt-cells = <2>;
- interrupt-controller;
- msi-parent = <&sei>;
- };
- };
-
- CP110_LABEL(rtc): rtc@284000 {
- compatible = "marvell,armada-8k-rtc";
- reg = <0x284000 0x20>, <0x284080 0x24>;
- reg-names = "rtc", "rtc-soc";
- interrupts = <77 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- CP110_LABEL(syscon0): system-controller@440000 {
- compatible = "syscon", "simple-mfd";
- reg = <0x440000 0x2000>;
-
- CP110_LABEL(clk): clock {
- compatible = "marvell,cp110-clock";
- #clock-cells = <2>;
- };
-
- CP110_LABEL(gpio1): gpio@100 {
- compatible = "marvell,armada-8k-gpio";
- offset = <0x100>;
- ngpios = <32>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>;
- interrupt-controller;
- interrupts = <86 IRQ_TYPE_LEVEL_HIGH>,
- <85 IRQ_TYPE_LEVEL_HIGH>,
- <84 IRQ_TYPE_LEVEL_HIGH>,
- <83 IRQ_TYPE_LEVEL_HIGH>;
- #interrupt-cells = <2>;
- status = "disabled";
- };
-
- CP110_LABEL(gpio2): gpio@140 {
- compatible = "marvell,armada-8k-gpio";
- offset = <0x140>;
- ngpios = <31>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&CP110_LABEL(pinctrl) 0 32 31>;
- interrupt-controller;
- interrupts = <82 IRQ_TYPE_LEVEL_HIGH>,
- <81 IRQ_TYPE_LEVEL_HIGH>,
- <80 IRQ_TYPE_LEVEL_HIGH>,
- <79 IRQ_TYPE_LEVEL_HIGH>;
- #interrupt-cells = <2>;
- status = "disabled";
- };
- };
-
- CP110_LABEL(syscon1): system-controller@400000 {
- compatible = "syscon", "simple-mfd";
- reg = <0x400000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- CP110_LABEL(thermal): thermal-sensor@70 {
- compatible = "marvell,armada-cp110-thermal";
- reg = <0x70 0x10>;
- interrupts-extended =
- <&CP110_LABEL(icu_sei) 116 IRQ_TYPE_LEVEL_HIGH>;
- #thermal-sensor-cells = <1>;
- };
- };
-
- CP110_LABEL(usb3_0): usb3@500000 {
- compatible = "marvell,armada-8k-xhci",
- "generic-xhci";
- reg = <0x500000 0x4000>;
- dma-coherent;
- interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "core", "reg";
- clocks = <&CP110_LABEL(clk) 1 22>,
- <&CP110_LABEL(clk) 1 16>;
- status = "disabled";
- };
-
- CP110_LABEL(usb3_1): usb3@510000 {
- compatible = "marvell,armada-8k-xhci",
- "generic-xhci";
- reg = <0x510000 0x4000>;
- dma-coherent;
- interrupts = <105 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "core", "reg";
- clocks = <&CP110_LABEL(clk) 1 23>,
- <&CP110_LABEL(clk) 1 16>;
- status = "disabled";
- };
-
- CP110_LABEL(sata0): sata@540000 {
- compatible = "marvell,armada-8k-ahci",
- "generic-ahci";
- reg = <0x540000 0x30000>;
- dma-coherent;
- interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&CP110_LABEL(clk) 1 15>,
- <&CP110_LABEL(clk) 1 16>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
-
- sata-port@0 {
- reg = <0>;
- };
-
- sata-port@1 {
- reg = <1>;
- };
- };
-
- CP110_LABEL(xor0): xor@6a0000 {
- compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
- reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>;
- dma-coherent;
- msi-parent = <&gic_v2m0>;
- clock-names = "core", "reg";
- clocks = <&CP110_LABEL(clk) 1 8>,
- <&CP110_LABEL(clk) 1 14>;
- };
-
- CP110_LABEL(xor1): xor@6c0000 {
- compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
- reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>;
- dma-coherent;
- msi-parent = <&gic_v2m0>;
- clock-names = "core", "reg";
- clocks = <&CP110_LABEL(clk) 1 7>,
- <&CP110_LABEL(clk) 1 14>;
- };
-
- CP110_LABEL(spi0): spi@700600 {
- compatible = "marvell,armada-380-spi";
- reg = <0x700600 0x50>;
- #address-cells = <0x1>;
- #size-cells = <0x0>;
- clock-names = "core", "axi";
- clocks = <&CP110_LABEL(clk) 1 21>,
- <&CP110_LABEL(clk) 1 17>;
- status = "disabled";
- };
-
- CP110_LABEL(spi1): spi@700680 {
- compatible = "marvell,armada-380-spi";
- reg = <0x700680 0x50>;
- #address-cells = <1>;
- #size-cells = <0>;
- clock-names = "core", "axi";
- clocks = <&CP110_LABEL(clk) 1 21>,
- <&CP110_LABEL(clk) 1 17>;
- status = "disabled";
- };
-
- CP110_LABEL(i2c0): i2c@701000 {
- compatible = "marvell,mv78230-i2c";
- reg = <0x701000 0x20>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <120 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "core", "reg";
- clocks = <&CP110_LABEL(clk) 1 21>,
- <&CP110_LABEL(clk) 1 17>;
- status = "disabled";
- };
-
- CP110_LABEL(i2c1): i2c@701100 {
- compatible = "marvell,mv78230-i2c";
- reg = <0x701100 0x20>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <121 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "core", "reg";
- clocks = <&CP110_LABEL(clk) 1 21>,
- <&CP110_LABEL(clk) 1 17>;
- status = "disabled";
- };
-
- CP110_LABEL(uart0): serial@702000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x702000 0x100>;
- reg-shift = <2>;
- interrupts = <122 IRQ_TYPE_LEVEL_HIGH>;
- reg-io-width = <1>;
- clock-names = "baudclk", "apb_pclk";
- clocks = <&CP110_LABEL(clk) 1 21>,
- <&CP110_LABEL(clk) 1 17>;
- status = "disabled";
- };
-
- CP110_LABEL(uart1): serial@702100 {
- compatible = "snps,dw-apb-uart";
- reg = <0x702100 0x100>;
- reg-shift = <2>;
- interrupts = <123 IRQ_TYPE_LEVEL_HIGH>;
- reg-io-width = <1>;
- clock-names = "baudclk", "apb_pclk";
- clocks = <&CP110_LABEL(clk) 1 21>,
- <&CP110_LABEL(clk) 1 17>;
- status = "disabled";
- };
-
- CP110_LABEL(uart2): serial@702200 {
- compatible = "snps,dw-apb-uart";
- reg = <0x702200 0x100>;
- reg-shift = <2>;
- interrupts = <124 IRQ_TYPE_LEVEL_HIGH>;
- reg-io-width = <1>;
- clock-names = "baudclk", "apb_pclk";
- clocks = <&CP110_LABEL(clk) 1 21>,
- <&CP110_LABEL(clk) 1 17>;
- status = "disabled";
- };
-
- CP110_LABEL(uart3): serial@702300 {
- compatible = "snps,dw-apb-uart";
- reg = <0x702300 0x100>;
- reg-shift = <2>;
- interrupts = <125 IRQ_TYPE_LEVEL_HIGH>;
- reg-io-width = <1>;
- clock-names = "baudclk", "apb_pclk";
- clocks = <&CP110_LABEL(clk) 1 21>,
- <&CP110_LABEL(clk) 1 17>;
- status = "disabled";
- };
-
- CP110_LABEL(nand_controller): nand@720000 {
- /*
- * Due to the limitation of the pins available
- * this controller is only usable on the CPM
- * for A7K and on the CPS for A8K.
- */
- compatible = "marvell,armada-8k-nand-controller",
- "marvell,armada370-nand-controller";
- reg = <0x720000 0x54>;
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <115 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "core", "reg";
- clocks = <&CP110_LABEL(clk) 1 2>,
- <&CP110_LABEL(clk) 1 17>;
- marvell,system-controller = <&CP110_LABEL(syscon0)>;
- status = "disabled";
- };
-
- CP110_LABEL(trng): trng@760000 {
- compatible = "marvell,armada-8k-rng",
- "inside-secure,safexcel-eip76";
- reg = <0x760000 0x7d>;
- interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "core", "reg";
- clocks = <&CP110_LABEL(clk) 1 25>,
- <&CP110_LABEL(clk) 1 17>;
- status = "okay";
- };
-
- CP110_LABEL(sdhci0): sdhci@780000 {
- compatible = "marvell,armada-cp110-sdhci";
- reg = <0x780000 0x300>;
- interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "core", "axi";
- clocks = <&CP110_LABEL(clk) 1 4>, <&CP110_LABEL(clk) 1 18>;
- dma-coherent;
- status = "disabled";
- };
-
- CP110_LABEL(crypto): crypto@800000 {
- compatible = "inside-secure,safexcel-eip197b";
- reg = <0x800000 0x200000>;
- interrupts = <87 IRQ_TYPE_LEVEL_HIGH>,
- <88 IRQ_TYPE_LEVEL_HIGH>,
- <89 IRQ_TYPE_LEVEL_HIGH>,
- <90 IRQ_TYPE_LEVEL_HIGH>,
- <91 IRQ_TYPE_LEVEL_HIGH>,
- <92 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "mem", "ring0", "ring1",
- "ring2", "ring3", "eip";
- clock-names = "core", "reg";
- clocks = <&CP110_LABEL(clk) 1 26>,
- <&CP110_LABEL(clk) 1 17>;
- dma-coherent;
- };
- };
-
- CP110_LABEL(pcie0): pcie@CP110_PCIE0_BASE {
- compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
- reg = <0 ADDRESSIFY(CP110_PCIE0_BASE) 0 0x10000>,
- <0 CP110_PCIEx_CONF_BASE(0) 0 0x80000>;
- reg-names = "ctrl", "config";
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- device_type = "pci";
- dma-coherent;
- msi-parent = <&gic_v2m0>;
-
- bus-range = <0 0xff>;
- ranges =
- /* downstream I/O */
- <0x81000000 0 CP110_PCIEx_IO_BASE(0) 0 CP110_PCIEx_IO_BASE(0) 0 0x10000
- /* non-prefetchable memory */
- 0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0 CP110_PCIEx_MEM_BASE(0) 0 0xf00000>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &CP110_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>;
- interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
- num-lanes = <1>;
- clock-names = "core", "reg";
- clocks = <&CP110_LABEL(clk) 1 13>, <&CP110_LABEL(clk) 1 14>;
- status = "disabled";
- };
-
- CP110_LABEL(pcie1): pcie@CP110_PCIE1_BASE {
- compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
- reg = <0 ADDRESSIFY(CP110_PCIE1_BASE) 0 0x10000>,
- <0 CP110_PCIEx_CONF_BASE(1) 0 0x80000>;
- reg-names = "ctrl", "config";
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- device_type = "pci";
- dma-coherent;
- msi-parent = <&gic_v2m0>;
-
- bus-range = <0 0xff>;
- ranges =
- /* downstream I/O */
- <0x81000000 0 CP110_PCIEx_IO_BASE(1) 0 CP110_PCIEx_IO_BASE(1) 0 0x10000
- /* non-prefetchable memory */
- 0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0 CP110_PCIEx_MEM_BASE(1) 0 0xf00000>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &CP110_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>;
- interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
-
- num-lanes = <1>;
- clock-names = "core", "reg";
- clocks = <&CP110_LABEL(clk) 1 11>, <&CP110_LABEL(clk) 1 14>;
- status = "disabled";
- };
-
- CP110_LABEL(pcie2): pcie@CP110_PCIE2_BASE {
- compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
- reg = <0 ADDRESSIFY(CP110_PCIE2_BASE) 0 0x10000>,
- <0 CP110_PCIEx_CONF_BASE(2) 0 0x80000>;
- reg-names = "ctrl", "config";
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- device_type = "pci";
- dma-coherent;
- msi-parent = <&gic_v2m0>;
-
- bus-range = <0 0xff>;
- ranges =
- /* downstream I/O */
- <0x81000000 0 CP110_PCIEx_IO_BASE(2) 0 CP110_PCIEx_IO_BASE(2) 0 0x10000
- /* non-prefetchable memory */
- 0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0 CP110_PCIEx_MEM_BASE(2) 0 0xf00000>;
- interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &CP110_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>;
- interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
-
- num-lanes = <1>;
- clock-names = "core", "reg";
- clocks = <&CP110_LABEL(clk) 1 12>, <&CP110_LABEL(clk) 1 14>;
- status = "disabled";
- };
-};
+#undef CP11X_TYPE
diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
new file mode 100644
index 000000000000..3e77cf34604c
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
@@ -0,0 +1,579 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2016 Marvell Technology Group Ltd.
+ *
+ * Device Tree file for Marvell Armada CP11x.
+ */
+
+#include <dt-bindings/interrupt-controller/mvebu-icu.h>
+#include <dt-bindings/thermal/thermal.h>
+
+#include "armada-common.dtsi"
+
+#define CP11X_PCIEx_IO_BASE(iface) (CP11X_PCIE_IO_BASE + (iface * 0x10000))
+#define CP11X_PCIEx_MEM_BASE(iface) (CP11X_PCIE_MEM_BASE + (iface * 0x1000000))
+#define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) + 0xf00000)
+
+/ {
+ /*
+ * The contents of the node are defined below, in order to
+ * save one indentation level
+ */
+ CP11X_NAME: CP11X_NAME { };
+
+ /*
+ * CPs only have one sensor in the thermal IC.
+ *
+ * The cooling maps are empty as there are no cooling devices.
+ */
+ thermal-zones {
+ CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(thermal-ic) {
+ polling-delay-passive = <0>; /* Interrupt driven */
+ polling-delay = <0>; /* Interrupt driven */
+
+ thermal-sensors = <&CP11X_LABEL(thermal) 0>;
+
+ trips {
+ CP11X_LABEL(crit): crit {
+ temperature = <100000>; /* mC degrees */
+ hysteresis = <2000>; /* mC degrees */
+ type = "critical";
+ };
+ };
+
+ cooling-maps { };
+ };
+ };
+};
+
+&CP11X_NAME {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ interrupt-parent = <&CP11X_LABEL(icu_nsr)>;
+ ranges;
+
+ config-space@CP11X_BASE {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ ranges = <0x0 0x0 ADDRESSIFY(CP11X_BASE) 0x2000000>;
+
+ CP11X_LABEL(ethernet): ethernet@0 {
+ compatible = "marvell,armada-7k-pp22";
+ reg = <0x0 0x100000>, <0x129000 0xb000>;
+ clocks = <&CP11X_LABEL(clk) 1 3>, <&CP11X_LABEL(clk) 1 9>,
+ <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>,
+ <&CP11X_LABEL(clk) 1 18>;
+ clock-names = "pp_clk", "gop_clk",
+ "mg_clk", "mg_core_clk", "axi_clk";
+ marvell,system-controller = <&CP11X_LABEL(syscon0)>;
+ status = "disabled";
+ dma-coherent;
+
+ CP11X_LABEL(eth0): eth0 {
+ interrupts = <39 IRQ_TYPE_LEVEL_HIGH>,
+ <43 IRQ_TYPE_LEVEL_HIGH>,
+ <47 IRQ_TYPE_LEVEL_HIGH>,
+ <51 IRQ_TYPE_LEVEL_HIGH>,
+ <55 IRQ_TYPE_LEVEL_HIGH>,
+ <59 IRQ_TYPE_LEVEL_HIGH>,
+ <63 IRQ_TYPE_LEVEL_HIGH>,
+ <67 IRQ_TYPE_LEVEL_HIGH>,
+ <71 IRQ_TYPE_LEVEL_HIGH>,
+ <129 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hif0", "hif1", "hif2",
+ "hif3", "hif4", "hif5", "hif6", "hif7",
+ "hif8", "link";
+ port-id = <0>;
+ gop-port-id = <0>;
+ status = "disabled";
+ };
+
+ CP11X_LABEL(eth1): eth1 {
+ interrupts = <40 IRQ_TYPE_LEVEL_HIGH>,
+ <44 IRQ_TYPE_LEVEL_HIGH>,
+ <48 IRQ_TYPE_LEVEL_HIGH>,
+ <52 IRQ_TYPE_LEVEL_HIGH>,
+ <56 IRQ_TYPE_LEVEL_HIGH>,
+ <60 IRQ_TYPE_LEVEL_HIGH>,
+ <64 IRQ_TYPE_LEVEL_HIGH>,
+ <68 IRQ_TYPE_LEVEL_HIGH>,
+ <72 IRQ_TYPE_LEVEL_HIGH>,
+ <128 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hif0", "hif1", "hif2",
+ "hif3", "hif4", "hif5", "hif6", "hif7",
+ "hif8", "link";
+ port-id = <1>;
+ gop-port-id = <2>;
+ status = "disabled";
+ };
+
+ CP11X_LABEL(eth2): eth2 {
+ interrupts = <41 IRQ_TYPE_LEVEL_HIGH>,
+ <45 IRQ_TYPE_LEVEL_HIGH>,
+ <49 IRQ_TYPE_LEVEL_HIGH>,
+ <53 IRQ_TYPE_LEVEL_HIGH>,
+ <57 IRQ_TYPE_LEVEL_HIGH>,
+ <61 IRQ_TYPE_LEVEL_HIGH>,
+ <65 IRQ_TYPE_LEVEL_HIGH>,
+ <69 IRQ_TYPE_LEVEL_HIGH>,
+ <73 IRQ_TYPE_LEVEL_HIGH>,
+ <127 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hif0", "hif1", "hif2",
+ "hif3", "hif4", "hif5", "hif6", "hif7",
+ "hif8", "link";
+ port-id = <2>;
+ gop-port-id = <3>;
+ status = "disabled";
+ };
+ };
+
+ CP11X_LABEL(comphy): phy@120000 {
+ compatible = "marvell,comphy-cp110";
+ reg = <0x120000 0x6000>;
+ marvell,system-controller = <&CP11X_LABEL(syscon0)>;
+ clocks = <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>,
+ <&CP11X_LABEL(clk) 1 18>;
+ clock-names = "mg_clk", "mg_core_clk", "axi_clk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ CP11X_LABEL(comphy0): phy@0 {
+ reg = <0>;
+ #phy-cells = <1>;
+ };
+
+ CP11X_LABEL(comphy1): phy@1 {
+ reg = <1>;
+ #phy-cells = <1>;
+ };
+
+ CP11X_LABEL(comphy2): phy@2 {
+ reg = <2>;
+ #phy-cells = <1>;
+ };
+
+ CP11X_LABEL(comphy3): phy@3 {
+ reg = <3>;
+ #phy-cells = <1>;
+ };
+
+ CP11X_LABEL(comphy4): phy@4 {
+ reg = <4>;
+ #phy-cells = <1>;
+ };
+
+ CP11X_LABEL(comphy5): phy@5 {
+ reg = <5>;
+ #phy-cells = <1>;
+ };
+ };
+
+ CP11X_LABEL(mdio): mdio@12a200 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "marvell,orion-mdio";
+ reg = <0x12a200 0x10>;
+ clocks = <&CP11X_LABEL(clk) 1 9>, <&CP11X_LABEL(clk) 1 5>,
+ <&CP11X_LABEL(clk) 1 6>, <&CP11X_LABEL(clk) 1 18>;
+ status = "disabled";
+ };
+
+ CP11X_LABEL(xmdio): mdio@12a600 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "marvell,xmdio";
+ reg = <0x12a600 0x10>;
+ clocks = <&CP11X_LABEL(clk) 1 5>,
+ <&CP11X_LABEL(clk) 1 6>, <&CP11X_LABEL(clk) 1 18>;
+ status = "disabled";
+ };
+
+ CP11X_LABEL(icu): interrupt-controller@1e0000 {
+ compatible = "marvell,cp110-icu";
+ reg = <0x1e0000 0x440>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ CP11X_LABEL(icu_nsr): interrupt-controller@10 {
+ compatible = "marvell,cp110-icu-nsr";
+ reg = <0x10 0x20>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ msi-parent = <&gicp>;
+ };
+
+ CP11X_LABEL(icu_sei): interrupt-controller@50 {
+ compatible = "marvell,cp110-icu-sei";
+ reg = <0x50 0x10>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ msi-parent = <&sei>;
+ };
+ };
+
+ CP11X_LABEL(rtc): rtc@284000 {
+ compatible = "marvell,armada-8k-rtc";
+ reg = <0x284000 0x20>, <0x284080 0x24>;
+ reg-names = "rtc", "rtc-soc";
+ interrupts = <77 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ CP11X_LABEL(syscon0): system-controller@440000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x440000 0x2000>;
+
+ CP11X_LABEL(clk): clock {
+ compatible = "marvell,cp110-clock";
+ #clock-cells = <2>;
+ };
+
+ CP11X_LABEL(gpio1): gpio@100 {
+ compatible = "marvell,armada-8k-gpio";
+ offset = <0x100>;
+ ngpios = <32>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&CP11X_LABEL(pinctrl) 0 0 32>;
+ interrupt-controller;
+ interrupts = <86 IRQ_TYPE_LEVEL_HIGH>,
+ <85 IRQ_TYPE_LEVEL_HIGH>,
+ <84 IRQ_TYPE_LEVEL_HIGH>,
+ <83 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+
+ CP11X_LABEL(gpio2): gpio@140 {
+ compatible = "marvell,armada-8k-gpio";
+ offset = <0x140>;
+ ngpios = <31>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&CP11X_LABEL(pinctrl) 0 32 31>;
+ interrupt-controller;
+ interrupts = <82 IRQ_TYPE_LEVEL_HIGH>,
+ <81 IRQ_TYPE_LEVEL_HIGH>,
+ <80 IRQ_TYPE_LEVEL_HIGH>,
+ <79 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <2>;
+ status = "disabled";
+ };
+ };
+
+ CP11X_LABEL(syscon1): system-controller@400000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x400000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ CP11X_LABEL(thermal): thermal-sensor@70 {
+ compatible = "marvell,armada-cp110-thermal";
+ reg = <0x70 0x10>;
+ interrupts-extended =
+ <&CP11X_LABEL(icu_sei) 116 IRQ_TYPE_LEVEL_HIGH>;
+ #thermal-sensor-cells = <1>;
+ };
+ };
+
+ CP11X_LABEL(usb3_0): usb3@500000 {
+ compatible = "marvell,armada-8k-xhci",
+ "generic-xhci";
+ reg = <0x500000 0x4000>;
+ dma-coherent;
+ interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core", "reg";
+ clocks = <&CP11X_LABEL(clk) 1 22>,
+ <&CP11X_LABEL(clk) 1 16>;
+ status = "disabled";
+ };
+
+ CP11X_LABEL(usb3_1): usb3@510000 {
+ compatible = "marvell,armada-8k-xhci",
+ "generic-xhci";
+ reg = <0x510000 0x4000>;
+ dma-coherent;
+ interrupts = <105 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core", "reg";
+ clocks = <&CP11X_LABEL(clk) 1 23>,
+ <&CP11X_LABEL(clk) 1 16>;
+ status = "disabled";
+ };
+
+ CP11X_LABEL(sata0): sata@540000 {
+ compatible = "marvell,armada-8k-ahci",
+ "generic-ahci";
+ reg = <0x540000 0x30000>;
+ dma-coherent;
+ interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&CP11X_LABEL(clk) 1 15>,
+ <&CP11X_LABEL(clk) 1 16>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ sata-port@0 {
+ reg = <0>;
+ };
+
+ sata-port@1 {
+ reg = <1>;
+ };
+ };
+
+ CP11X_LABEL(xor0): xor@6a0000 {
+ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
+ reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>;
+ dma-coherent;
+ msi-parent = <&gic_v2m0>;
+ clock-names = "core", "reg";
+ clocks = <&CP11X_LABEL(clk) 1 8>,
+ <&CP11X_LABEL(clk) 1 14>;
+ };
+
+ CP11X_LABEL(xor1): xor@6c0000 {
+ compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
+ reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>;
+ dma-coherent;
+ msi-parent = <&gic_v2m0>;
+ clock-names = "core", "reg";
+ clocks = <&CP11X_LABEL(clk) 1 7>,
+ <&CP11X_LABEL(clk) 1 14>;
+ };
+
+ CP11X_LABEL(spi0): spi@700600 {
+ compatible = "marvell,armada-380-spi";
+ reg = <0x700600 0x50>;
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ clock-names = "core", "axi";
+ clocks = <&CP11X_LABEL(clk) 1 21>,
+ <&CP11X_LABEL(clk) 1 17>;
+ status = "disabled";
+ };
+
+ CP11X_LABEL(spi1): spi@700680 {
+ compatible = "marvell,armada-380-spi";
+ reg = <0x700680 0x50>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-names = "core", "axi";
+ clocks = <&CP11X_LABEL(clk) 1 21>,
+ <&CP11X_LABEL(clk) 1 17>;
+ status = "disabled";
+ };
+
+ CP11X_LABEL(i2c0): i2c@701000 {
+ compatible = "marvell,mv78230-i2c";
+ reg = <0x701000 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <120 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core", "reg";
+ clocks = <&CP11X_LABEL(clk) 1 21>,
+ <&CP11X_LABEL(clk) 1 17>;
+ status = "disabled";
+ };
+
+ CP11X_LABEL(i2c1): i2c@701100 {
+ compatible = "marvell,mv78230-i2c";
+ reg = <0x701100 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <121 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core", "reg";
+ clocks = <&CP11X_LABEL(clk) 1 21>,
+ <&CP11X_LABEL(clk) 1 17>;
+ status = "disabled";
+ };
+
+ CP11X_LABEL(uart0): serial@702000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x702000 0x100>;
+ reg-shift = <2>;
+ interrupts = <122 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <1>;
+ clock-names = "baudclk", "apb_pclk";
+ clocks = <&CP11X_LABEL(clk) 1 21>,
+ <&CP11X_LABEL(clk) 1 17>;
+ status = "disabled";
+ };
+
+ CP11X_LABEL(uart1): serial@702100 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x702100 0x100>;
+ reg-shift = <2>;
+ interrupts = <123 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <1>;
+ clock-names = "baudclk", "apb_pclk";
+ clocks = <&CP11X_LABEL(clk) 1 21>,
+ <&CP11X_LABEL(clk) 1 17>;
+ status = "disabled";
+ };
+
+ CP11X_LABEL(uart2): serial@702200 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x702200 0x100>;
+ reg-shift = <2>;
+ interrupts = <124 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <1>;
+ clock-names = "baudclk", "apb_pclk";
+ clocks = <&CP11X_LABEL(clk) 1 21>,
+ <&CP11X_LABEL(clk) 1 17>;
+ status = "disabled";
+ };
+
+ CP11X_LABEL(uart3): serial@702300 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x702300 0x100>;
+ reg-shift = <2>;
+ interrupts = <125 IRQ_TYPE_LEVEL_HIGH>;
+ reg-io-width = <1>;
+ clock-names = "baudclk", "apb_pclk";
+ clocks = <&CP11X_LABEL(clk) 1 21>,
+ <&CP11X_LABEL(clk) 1 17>;
+ status = "disabled";
+ };
+
+ CP11X_LABEL(nand_controller): nand@720000 {
+ /*
+ * Due to the limitation of the pins available
+ * this controller is only usable on the CPM
+ * for A7K and on the CPS for A8K.
+ */
+ compatible = "marvell,armada-8k-nand-controller",
+ "marvell,armada370-nand-controller";
+ reg = <0x720000 0x54>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <115 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core", "reg";
+ clocks = <&CP11X_LABEL(clk) 1 2>,
+ <&CP11X_LABEL(clk) 1 17>;
+ marvell,system-controller = <&CP11X_LABEL(syscon0)>;
+ status = "disabled";
+ };
+
+ CP11X_LABEL(trng): trng@760000 {
+ compatible = "marvell,armada-8k-rng",
+ "inside-secure,safexcel-eip76";
+ reg = <0x760000 0x7d>;
+ interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core", "reg";
+ clocks = <&CP11X_LABEL(clk) 1 25>,
+ <&CP11X_LABEL(clk) 1 17>;
+ status = "okay";
+ };
+
+ CP11X_LABEL(sdhci0): sdhci@780000 {
+ compatible = "marvell,armada-cp110-sdhci";
+ reg = <0x780000 0x300>;
+ interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "core", "axi";
+ clocks = <&CP11X_LABEL(clk) 1 4>, <&CP11X_LABEL(clk) 1 18>;
+ dma-coherent;
+ status = "disabled";
+ };
+
+ CP11X_LABEL(crypto): crypto@800000 {
+ compatible = "inside-secure,safexcel-eip197b";
+ reg = <0x800000 0x200000>;
+ interrupts = <87 IRQ_TYPE_LEVEL_HIGH>,
+ <88 IRQ_TYPE_LEVEL_HIGH>,
+ <89 IRQ_TYPE_LEVEL_HIGH>,
+ <90 IRQ_TYPE_LEVEL_HIGH>,
+ <91 IRQ_TYPE_LEVEL_HIGH>,
+ <92 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mem", "ring0", "ring1",
+ "ring2", "ring3", "eip";
+ clock-names = "core", "reg";
+ clocks = <&CP11X_LABEL(clk) 1 26>,
+ <&CP11X_LABEL(clk) 1 17>;
+ dma-coherent;
+ };
+ };
+
+ CP11X_LABEL(pcie0): pcie@CP11X_PCIE0_BASE {
+ compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
+ reg = <0 ADDRESSIFY(CP11X_PCIE0_BASE) 0 0x10000>,
+ <0 CP11X_PCIEx_CONF_BASE(0) 0 0x80000>;
+ reg-names = "ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ dma-coherent;
+ msi-parent = <&gic_v2m0>;
+
+ bus-range = <0 0xff>;
+ ranges =
+ /* downstream I/O */
+ <0x81000000 0 CP11X_PCIEx_IO_BASE(0) 0 CP11X_PCIEx_IO_BASE(0) 0 0x10000
+ /* non-prefetchable memory */
+ 0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_BASE(0) 0 0xf00000>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
+ num-lanes = <1>;
+ clock-names = "core", "reg";
+ clocks = <&CP11X_LABEL(clk) 1 13>, <&CP11X_LABEL(clk) 1 14>;
+ status = "disabled";
+ };
+
+ CP11X_LABEL(pcie1): pcie@CP11X_PCIE1_BASE {
+ compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
+ reg = <0 ADDRESSIFY(CP11X_PCIE1_BASE) 0 0x10000>,
+ <0 CP11X_PCIEx_CONF_BASE(1) 0 0x80000>;
+ reg-names = "ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ dma-coherent;
+ msi-parent = <&gic_v2m0>;
+
+ bus-range = <0 0xff>;
+ ranges =
+ /* downstream I/O */
+ <0x81000000 0 CP11X_PCIEx_IO_BASE(1) 0 CP11X_PCIEx_IO_BASE(1) 0 0x10000
+ /* non-prefetchable memory */
+ 0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_BASE(1) 0 0xf00000>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
+
+ num-lanes = <1>;
+ clock-names = "core", "reg";
+ clocks = <&CP11X_LABEL(clk) 1 11>, <&CP11X_LABEL(clk) 1 14>;
+ status = "disabled";
+ };
+
+ CP11X_LABEL(pcie2): pcie@CP11X_PCIE2_BASE {
+ compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
+ reg = <0 ADDRESSIFY(CP11X_PCIE2_BASE) 0 0x10000>,
+ <0 CP11X_PCIEx_CONF_BASE(2) 0 0x80000>;
+ reg-names = "ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ #interrupt-cells = <1>;
+ device_type = "pci";
+ dma-coherent;
+ msi-parent = <&gic_v2m0>;
+
+ bus-range = <0 0xff>;
+ ranges =
+ /* downstream I/O */
+ <0x81000000 0 CP11X_PCIEx_IO_BASE(2) 0 CP11X_PCIEx_IO_BASE(2) 0 0x10000
+ /* non-prefetchable memory */
+ 0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_BASE(2) 0 0xf00000>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
+
+ num-lanes = <1>;
+ clock-names = "core", "reg";
+ clocks = <&CP11X_LABEL(clk) 1 12>, <&CP11X_LABEL(clk) 1 14>;
+ status = "disabled";
+ };
+};
--
2.20.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH 13/20] arm64: dts: marvell: Drop PCIe I/O ranges from CP11x file
From: Miquel Raynal @ 2019-08-06 14:54 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: devicetree, Yan Markman, Antoine Tenart, Grzegorz Jaszczyk,
Gregory Clement, Maxime Chevallier, Nadav Haklai,
Thomas Petazzoni, Miquel Raynal, Stefan Chulski, Marcin Wojtas,
linux-arm-kernel
In-Reply-To: <20190806145500.24109-1-miquel.raynal@bootlin.com>
As an example, Armada 70x0 and 80x0 SoC 0xf9000000 region points to
RUNIT/SPICS0 while it is referenced in the DT as PCIe I/O memory
range. This shows that I/O memory has never been used/working on the
old SoCs despite the region being advertised. As PCIe I/O ranges will
not be supported in newer SoCs using CP11x co-processors, let's
simply drop them. It is not harmful in any case as PCIe device drivers
can do it all with the regular mapped memory anyway.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 2 --
.../boot/dts/marvell/armada-8040-mcbin.dtsi | 3 +--
arch/arm64/boot/dts/marvell/armada-80x0.dtsi | 4 ----
arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 16 +++-------------
4 files changed, 4 insertions(+), 21 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
index 4e78ccd207b7..ac28903ea409 100644
--- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
@@ -19,7 +19,6 @@
*/
#define CP11X_NAME cp0
#define CP11X_BASE f2000000
-#define CP11X_PCIE_IO_BASE 0xf9000000
#define CP11X_PCIE_MEM_BASE 0xf6000000
#define CP11X_PCIE0_BASE f2600000
#define CP11X_PCIE1_BASE f2620000
@@ -29,7 +28,6 @@
#undef CP11X_NAME
#undef CP11X_BASE
-#undef CP11X_PCIE_IO_BASE
#undef CP11X_PCIE_MEM_BASE
#undef CP11X_PCIE0_BASE
#undef CP11X_PCIE1_BASE
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
index d250f4b2bfed..572e2610e0a3 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi
@@ -179,8 +179,7 @@
num-lanes = <4>;
num-viewport = <8>;
reset-gpios = <&cp0_gpio2 20 GPIO_ACTIVE_LOW>;
- ranges = <0x81000000 0x0 0xf9010000 0x0 0xf9010000 0x0 0x10000
- 0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>;
+ ranges = <0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>;
phys = <&cp0_comphy0 0>, <&cp0_comphy1 0>,
<&cp0_comphy2 0>, <&cp0_comphy3 0>;
phy-names = "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy",
diff --git a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
index ebb98836ec9c..902eed571bcc 100644
--- a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
@@ -21,7 +21,6 @@
*/
#define CP11X_NAME cp0
#define CP11X_BASE f2000000
-#define CP11X_PCIE_IO_BASE 0xf9000000
#define CP11X_PCIE_MEM_BASE 0xf6000000
#define CP11X_PCIE0_BASE f2600000
#define CP11X_PCIE1_BASE f2620000
@@ -31,7 +30,6 @@
#undef CP11X_NAME
#undef CP11X_BASE
-#undef CP11X_PCIE_IO_BASE
#undef CP11X_PCIE_MEM_BASE
#undef CP11X_PCIE0_BASE
#undef CP11X_PCIE1_BASE
@@ -42,7 +40,6 @@
*/
#define CP11X_NAME cp1
#define CP11X_BASE f4000000
-#define CP11X_PCIE_IO_BASE 0xfd000000
#define CP11X_PCIE_MEM_BASE 0xfa000000
#define CP11X_PCIE0_BASE f4600000
#define CP11X_PCIE1_BASE f4620000
@@ -52,7 +49,6 @@
#undef CP11X_NAME
#undef CP11X_BASE
-#undef CP11X_PCIE_IO_BASE
#undef CP11X_PCIE_MEM_BASE
#undef CP11X_PCIE0_BASE
#undef CP11X_PCIE1_BASE
diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
index 3e77cf34604c..7d1ab097453d 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
@@ -10,7 +10,6 @@
#include "armada-common.dtsi"
-#define CP11X_PCIEx_IO_BASE(iface) (CP11X_PCIE_IO_BASE + (iface * 0x10000))
#define CP11X_PCIEx_MEM_BASE(iface) (CP11X_PCIE_MEM_BASE + (iface * 0x1000000))
#define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) + 0xf00000)
@@ -507,11 +506,8 @@
msi-parent = <&gic_v2m0>;
bus-range = <0 0xff>;
- ranges =
- /* downstream I/O */
- <0x81000000 0 CP11X_PCIEx_IO_BASE(0) 0 CP11X_PCIEx_IO_BASE(0) 0 0x10000
/* non-prefetchable memory */
- 0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_BASE(0) 0 0xf00000>;
+ ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_BASE(0) 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
@@ -534,11 +530,8 @@
msi-parent = <&gic_v2m0>;
bus-range = <0 0xff>;
- ranges =
- /* downstream I/O */
- <0x81000000 0 CP11X_PCIEx_IO_BASE(1) 0 CP11X_PCIEx_IO_BASE(1) 0 0x10000
/* non-prefetchable memory */
- 0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_BASE(1) 0 0xf00000>;
+ ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_BASE(1) 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
@@ -562,11 +555,8 @@
msi-parent = <&gic_v2m0>;
bus-range = <0 0xff>;
- ranges =
- /* downstream I/O */
- <0x81000000 0 CP11X_PCIEx_IO_BASE(2) 0 CP11X_PCIEx_IO_BASE(2) 0 0x10000
/* non-prefetchable memory */
- 0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_BASE(2) 0 0xf00000>;
+ ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_BASE(2) 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
--
2.20.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH 14/20] arm64: dts: marvell: Externalize PCIe macros from CP11x file
From: Miquel Raynal @ 2019-08-06 14:54 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: devicetree, Yan Markman, Antoine Tenart, Grzegorz Jaszczyk,
Gregory Clement, Maxime Chevallier, Nadav Haklai,
Thomas Petazzoni, Miquel Raynal, Stefan Chulski, Marcin Wojtas,
linux-arm-kernel
In-Reply-To: <20190806145500.24109-1-miquel.raynal@bootlin.com>
PCIe macros are specific to CP110 and will not fit CP115
constraints. To keep the same way the files are organized, just move
some macros out of the CP11x generic file and define them directly in
SoC DTSI, instead of defining single addresses in the SoC DTSI and
reusing them in macros.
In the end:
* CP11X_PCIE_MEM_BASE SoC define is dropped
* CP11X_PCIEx_MEM_BASE is moved out of the generic DT to be put in the
SoC files as it replaces the above definition.
* As the CP11X_PCIEx_MEM_SIZE macro is also subject to change with
newer SoCs, we put it in the SoC files as well.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 6 ++++--
arch/arm64/boot/dts/marvell/armada-80x0.dtsi | 12 ++++++++----
arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 9 ++++-----
3 files changed, 16 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
index ac28903ea409..293403a1a333 100644
--- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
@@ -19,7 +19,8 @@
*/
#define CP11X_NAME cp0
#define CP11X_BASE f2000000
-#define CP11X_PCIE_MEM_BASE 0xf6000000
+#define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000))
+#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
#define CP11X_PCIE0_BASE f2600000
#define CP11X_PCIE1_BASE f2620000
#define CP11X_PCIE2_BASE f2640000
@@ -28,7 +29,8 @@
#undef CP11X_NAME
#undef CP11X_BASE
-#undef CP11X_PCIE_MEM_BASE
+#undef CP11X_PCIEx_MEM_BASE
+#undef CP11X_PCIEx_MEM_SIZE
#undef CP11X_PCIE0_BASE
#undef CP11X_PCIE1_BASE
#undef CP11X_PCIE2_BASE
diff --git a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
index 902eed571bcc..ee67c70bf02e 100644
--- a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
@@ -21,7 +21,8 @@
*/
#define CP11X_NAME cp0
#define CP11X_BASE f2000000
-#define CP11X_PCIE_MEM_BASE 0xf6000000
+#define CP11X_PCIEx_MEM_BASE(iface) (0xf6000000 + (iface * 0x1000000))
+#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
#define CP11X_PCIE0_BASE f2600000
#define CP11X_PCIE1_BASE f2620000
#define CP11X_PCIE2_BASE f2640000
@@ -30,7 +31,8 @@
#undef CP11X_NAME
#undef CP11X_BASE
-#undef CP11X_PCIE_MEM_BASE
+#undef CP11X_PCIEx_MEM_BASE
+#undef CP11X_PCIEx_MEM_SIZE
#undef CP11X_PCIE0_BASE
#undef CP11X_PCIE1_BASE
#undef CP11X_PCIE2_BASE
@@ -40,7 +42,8 @@
*/
#define CP11X_NAME cp1
#define CP11X_BASE f4000000
-#define CP11X_PCIE_MEM_BASE 0xfa000000
+#define CP11X_PCIEx_MEM_BASE(iface) (0xfa000000 + (iface * 0x1000000))
+#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
#define CP11X_PCIE0_BASE f4600000
#define CP11X_PCIE1_BASE f4620000
#define CP11X_PCIE2_BASE f4640000
@@ -49,7 +52,8 @@
#undef CP11X_NAME
#undef CP11X_BASE
-#undef CP11X_PCIE_MEM_BASE
+#undef CP11X_PCIEx_MEM_BASE
+#undef CP11X_PCIEx_MEM_SIZE
#undef CP11X_PCIE0_BASE
#undef CP11X_PCIE1_BASE
#undef CP11X_PCIE2_BASE
diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
index 7d1ab097453d..9dcf16beabf5 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
@@ -10,8 +10,7 @@
#include "armada-common.dtsi"
-#define CP11X_PCIEx_MEM_BASE(iface) (CP11X_PCIE_MEM_BASE + (iface * 0x1000000))
-#define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) + 0xf00000)
+#define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) + CP11X_PCIEx_MEM_SIZE(iface))
/ {
/*
@@ -507,7 +506,7 @@
bus-range = <0 0xff>;
/* non-prefetchable memory */
- ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_BASE(0) 0 0xf00000>;
+ ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_SIZE(0)>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
@@ -531,7 +530,7 @@
bus-range = <0 0xff>;
/* non-prefetchable memory */
- ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_BASE(1) 0 0xf00000>;
+ ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_SIZE(1)>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
@@ -556,7 +555,7 @@
bus-range = <0 0xff>;
/* non-prefetchable memory */
- ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_BASE(2) 0 0xf00000>;
+ ranges = <0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_SIZE(2)>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
--
2.20.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH 15/20] arm64: dts: marvell: Add support for CP115
From: Miquel Raynal @ 2019-08-06 14:54 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: devicetree, Yan Markman, Antoine Tenart, Grzegorz Jaszczyk,
Gregory Clement, Maxime Chevallier, Nadav Haklai,
Thomas Petazzoni, Miquel Raynal, Stefan Chulski, Marcin Wojtas,
linux-arm-kernel
In-Reply-To: <20190806145500.24109-1-miquel.raynal@bootlin.com>
Create a DTSI file based on the CP11x one. Differences will be
described in the near future.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
arch/arm64/boot/dts/marvell/armada-cp115.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
create mode 100644 arch/arm64/boot/dts/marvell/armada-cp115.dtsi
diff --git a/arch/arm64/boot/dts/marvell/armada-cp115.dtsi b/arch/arm64/boot/dts/marvell/armada-cp115.dtsi
new file mode 100644
index 000000000000..1d0a9653e681
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/armada-cp115.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 Marvell Technology Group Ltd.
+ *
+ * Device Tree file for Marvell Armada CP115.
+ */
+
+#define CP11X_TYPE cp115
+
+#include "armada-cp11x.dtsi"
+
+#undef CP11X_TYPE
--
2.20.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH 16/20] dt-bindings: marvell: Declare the CN913x SoC compatibles
From: Miquel Raynal @ 2019-08-06 14:54 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: devicetree, Yan Markman, Antoine Tenart, Grzegorz Jaszczyk,
Gregory Clement, Maxime Chevallier, Nadav Haklai,
Thomas Petazzoni, Miquel Raynal, Stefan Chulski, Marcin Wojtas,
linux-arm-kernel
In-Reply-To: <20190806145500.24109-1-miquel.raynal@bootlin.com>
From: Grzegorz Jaszczyk <jaz@semihalf.com>
Describe the compatible properties for the new Marvell SoCs:
* CN9130: 1x AP807-quad + 1x CP115 (1x embedded)
* CN9131: 1x AP807-quad + 2x CP115 (1x embedded + 1x modular)
* CN9132: 1x AP807-quad + 3x CP115 (1x embedded + 2x modular)
CP115 are similar to CP110 in terms of features.
There are three development boards based on these SoCs:
* CN9130-DB: comes as a single mother board (with the CP115 bundled)
* CN9131-DB: same as CN9130-DB with one additional modular CP115
* CN9132-DB: same as CN9130-DB with two additional modular CP115
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
.../bindings/arm/marvell/armada-7k-8k.txt | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.txt b/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.txt
index df98a9c82a8c..8eb34ca4c4f0 100644
--- a/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.txt
+++ b/Documentation/devicetree/bindings/arm/marvell/armada-7k-8k.txt
@@ -1,7 +1,7 @@
Marvell Armada 7K/8K Platforms Device Tree Bindings
---------------------------------------------------
-Boards using a SoC of the Marvell Armada 7K or 8K families must carry
+Boards using a SoC of the Marvell Armada 7K/8K or CN913x families must carry
the following root node property:
- compatible, with one of the following values:
@@ -18,6 +18,17 @@ the following root node property:
- "marvell,armada8040", "marvell,armada-ap806-quad", "marvell,armada-ap806"
when the SoC being used is the Armada 8040
+ - "marvell,cn9130", "marvell,armada-ap807-quad", "marvell,armada-ap807"
+ when the SoC being used is the Armada CN9130 with no external CP.
+
+ - "marvell,cn9131", "marvell,cn9130",
+ "marvell,armada-ap807-quad", "marvell,armada-ap807"
+ when the SoC being used is the Armada CN9130 with one external CP.
+
+ - "marvell,cn9132", "marvell,cn9131", "marvell,cn9130",
+ "marvell,armada-ap807-quad", "marvell,armada-ap807"
+ when the SoC being used is the Armada CN9130 with two external CPs.
+
Example:
compatible = "marvell,armada7040-db", "marvell,armada7040",
--
2.20.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH 17/20] arm64: dts: marvell: Add support for Marvell CN9130 SoC support
From: Miquel Raynal @ 2019-08-06 14:54 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: devicetree, Yan Markman, Antoine Tenart, Grzegorz Jaszczyk,
Gregory Clement, Maxime Chevallier, Nadav Haklai,
Thomas Petazzoni, Miquel Raynal, Stefan Chulski, Marcin Wojtas,
linux-arm-kernel
In-Reply-To: <20190806145500.24109-1-miquel.raynal@bootlin.com>
A CN9130 SoC has one AP807 and one internal CP115.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
arch/arm64/boot/dts/marvell/cn9130.dtsi | 37 +++++++++++++++++++++++++
1 file changed, 37 insertions(+)
create mode 100644 arch/arm64/boot/dts/marvell/cn9130.dtsi
diff --git a/arch/arm64/boot/dts/marvell/cn9130.dtsi b/arch/arm64/boot/dts/marvell/cn9130.dtsi
new file mode 100644
index 000000000000..a2b7e5ec979d
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/cn9130.dtsi
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ *
+ * Device tree for the CN9130 SoC.
+ */
+
+#include "armada-ap807-quad.dtsi"
+
+/ {
+ model = "Marvell Armada CN9130 SoC";
+ compatible = "marvell,cn9130", "marvell,armada-ap807-quad",
+ "marvell,armada-ap807";
+};
+
+/*
+ * Instantiate the internal CP115
+ */
+
+#define CP11X_NAME cp0
+#define CP11X_BASE f2000000
+#define CP11X_PCIEx_MEM_BASE(iface) ((iface == 0) ? 0xc0000000 : \
+ 0xe0000000 + ((iface - 1) * 0x1000000))
+#define CP11X_PCIEx_MEM_SIZE(iface) ((iface == 0) ? 0x1ff00000 : 0xf00000)
+#define CP11X_PCIE0_BASE f2600000
+#define CP11X_PCIE1_BASE f2620000
+#define CP11X_PCIE2_BASE f2640000
+
+#include "armada-cp115.dtsi"
+
+#undef CP11X_NAME
+#undef CP11X_BASE
+#undef CP11X_PCIEx_MEM_BASE
+#undef CP11X_PCIEx_MEM_SIZE
+#undef CP11X_PCIE0_BASE
+#undef CP11X_PCIE1_BASE
+#undef CP11X_PCIE2_BASE
--
2.20.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH 18/20] arm64: dts: marvell: Add support for Marvell CN9130-DB
From: Miquel Raynal @ 2019-08-06 14:54 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: devicetree, Yan Markman, Antoine Tenart, Grzegorz Jaszczyk,
Gregory Clement, Maxime Chevallier, Nadav Haklai,
Thomas Petazzoni, Miquel Raynal, Stefan Chulski, Marcin Wojtas,
linux-arm-kernel
In-Reply-To: <20190806145500.24109-1-miquel.raynal@bootlin.com>
From: Grzegorz Jaszczyk <jaz@semihalf.com>
Add basic support for the Marvell CN9130 modular development board. It
is based on a CN9130 SoC (one AP807 and one internal CP115), extended
via 2xMoCi interface to possibly add up to two more external CP115
(one located on the main board and the other on the board extension).
Available interfaces:
* AP UART
* AP eMMC
* AP SDHCI (disabled)
* CPO GPIO-0
* CPO GPIO-1
* CP0 CRYPTO-0 (disabled)
* CP0 I2C-0
* CP0 I2C-1
* CP0 SDHCI-0
* CP0 NAND-0
* CP0 SPI-1
* CP0 ETH-0 (SFI with SFP cage not working yet, disabled)
* CP0 ETH-1 (RGMII)
* CP0 ETH-2 (RGMII)
* CP0 SATA-0-1
* CP0 USB3-0 (High-speed only)
* CP0 USB3-1 (High-speed only)
* CP0 PCIe-0 x4
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
arch/arm64/boot/dts/marvell/Makefile | 1 +
arch/arm64/boot/dts/marvell/cn9130-db.dts | 403 ++++++++++++++++++++++
2 files changed, 404 insertions(+)
create mode 100644 arch/arm64/boot/dts/marvell/cn9130-db.dts
diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile
index caed4334f27d..922910d05863 100644
--- a/arch/arm64/boot/dts/marvell/Makefile
+++ b/arch/arm64/boot/dts/marvell/Makefile
@@ -9,3 +9,4 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-db.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin-singleshot.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-8080-db.dtb
+dtb-$(CONFIG_ARCH_MVEBU) += cn9130-db.dtb
diff --git a/arch/arm64/boot/dts/marvell/cn9130-db.dts b/arch/arm64/boot/dts/marvell/cn9130-db.dts
new file mode 100644
index 000000000000..ce49a70d88a0
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/cn9130-db.dts
@@ -0,0 +1,403 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ *
+ * Device tree for the CN9130-DB board.
+ */
+
+#include "cn9130.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Marvell Armada CN9130-DB";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ aliases {
+ gpio1 = &cp0_gpio1;
+ gpio2 = &cp0_gpio2;
+ i2c0 = &cp0_i2c0;
+ ethernet0 = &cp0_eth0;
+ ethernet1 = &cp0_eth1;
+ ethernet2 = &cp0_eth2;
+ spi1 = &cp0_spi0;
+ spi2 = &cp0_spi1;
+ };
+
+ memory@00000000 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ ap0_reg_sd_vccq: ap0_sd_vccq@0 {
+ compatible = "regulator-gpio";
+ regulator-name = "ap0_sd_vccq";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&expander0 8 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x1 3300000 0x0>;
+ };
+
+ cp0_reg_usb3_vbus0: cp0_usb3_vbus@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp0-xhci0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ cp0_usb3_0_phy0: cp0_usb3_phy@0 {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <&cp0_reg_usb3_vbus0>;
+ };
+
+ cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp0-xhci1-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ cp0_usb3_0_phy1: cp0_usb3_phy@1 {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <&cp0_reg_usb3_vbus1>;
+ };
+
+ cp0_reg_sd_vccq: cp0_sd_vccq@0 {
+ compatible = "regulator-gpio";
+ regulator-name = "cp0_sd_vccq";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&expander0 15 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x1
+ 3300000 0x0>;
+ };
+
+ cp0_reg_sd_vcc: cp0_sd_vcc@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp0_sd_vcc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ cp0_sfp_eth0: sfp-eth@0 {
+ compatible = "sff,sfp";
+ i2c-bus = <&cp0_sfpp0_i2c>;
+ los-gpio = <&cp0_module_expander1 11 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&cp0_module_expander1 10 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&cp0_module_expander1 9 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = <&cp0_module_expander1 8 GPIO_ACTIVE_HIGH>;
+ /*
+ * SFP cages are unconnected on early PCBs because of an the I2C
+ * lanes not being connected. Prevent the port for being
+ * unusable by disabling the SFP node.
+ */
+ status = "disabled";
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+/* on-board eMMC - U9 */
+&ap_sdhci0 {
+ pinctrl-names = "default";
+ bus-width = <8>;
+ vqmmc-supply = <&ap0_reg_sd_vccq>;
+ status = "okay";
+};
+
+&cp0_crypto {
+ status = "disabled";
+};
+
+&cp0_ethernet {
+ status = "okay";
+};
+
+/* SLM-1521-V2, CON9 */
+&cp0_eth0 {
+ status = "disabled";
+ phy-mode = "10gbase-kr";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp0_comphy4 0>;
+ managed = "in-band-status";
+ sfp = <&cp0_sfp_eth0>;
+};
+
+/* CON56 */
+&cp0_eth1 {
+ status = "okay";
+ phy = <&phy0>;
+ phy-mode = "rgmii-id";
+};
+
+/* CON57 */
+&cp0_eth2 {
+ status = "okay";
+ phy = <&phy1>;
+ phy-mode = "rgmii-id";
+};
+
+&cp0_gpio1 {
+ status = "okay";
+};
+
+&cp0_gpio2 {
+ status = "okay";
+};
+
+&cp0_i2c0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_i2c0_pins>;
+ clock-frequency = <100000>;
+
+ /* U36 */
+ expander0: pca953x@21 {
+ compatible = "nxp,pca9555";
+ pinctrl-names = "default";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x21>;
+ status = "okay";
+ };
+
+ /* U42 */
+ eeprom0: eeprom@50 {
+ compatible = "atmel,24c64";
+ reg = <0x50>;
+ pagesize = <0x20>;
+ };
+
+ /* U38 */
+ eeprom1: eeprom@57 {
+ compatible = "atmel,24c64";
+ reg = <0x57>;
+ pagesize = <0x20>;
+ };
+};
+
+&cp0_i2c1 {
+ status = "okay";
+ clock-frequency = <100000>;
+
+ /* SLM-1521-V2 - U3 */
+ i2c-mux@72 { /* verify address - depends on dpr */
+ compatible = "nxp,pca9544";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x72>;
+ cp0_sfpp0_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* U12 */
+ cp0_module_expander1: pca9555@21 {
+ compatible = "nxp,pca9555";
+ pinctrl-names = "default";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x21>;
+ };
+
+ };
+ };
+};
+
+&cp0_mdio {
+ status = "okay";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ };
+};
+
+/* U54 */
+&cp0_nand_controller {
+ pinctrl-names = "default";
+ pinctrl-0 = <&nand_pins &nand_rb>;
+
+ nand@0 {
+ reg = <0>;
+ label = "main-storage";
+ nand-rb = <0>;
+ nand-ecc-mode = "hw";
+ nand-on-flash-bbt;
+ nand-ecc-strength = <8>;
+ nand-ecc-step-size = <512>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "U-Boot";
+ reg = <0 0x200000>;
+ };
+ partition@200000 {
+ label = "Linux";
+ reg = <0x200000 0xd00000>;
+ };
+ partition@1000000 {
+ label = "Filesystem";
+ reg = <0x1000000 0x3f000000>;
+ };
+ };
+ };
+};
+
+/* SLM-1521-V2, CON6 */
+&cp0_pcie0 {
+ status = "okay";
+ num-lanes = <4>;
+ num-viewport = <8>;
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp0_comphy0 0
+ &cp0_comphy1 0
+ &cp0_comphy2 0
+ &cp0_comphy3 0>;
+};
+
+&cp0_sata0 {
+ status = "okay";
+
+ /* SLM-1521-V2, CON2 */
+ sata-port@1 {
+ status = "okay";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp0_comphy5 1>;
+ };
+};
+
+/* CON 28 */
+&cp0_sdhci0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_sdhci_pins
+ &cp0_sdhci_cd_pins>;
+ bus-width = <4>;
+ cd-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;
+ no-1-8-v;
+ vqmmc-supply = <&cp0_reg_sd_vccq>;
+ vmmc-supply = <&cp0_reg_sd_vcc>;
+};
+
+/* U55 */
+&cp0_spi1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp0_spi0_pins>;
+ reg = <0x700680 0x50>;
+
+ spi-flash@0 {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ /* On-board MUX does not allow higher frequencies */
+ spi-max-frequency = <40000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "U-Boot-0";
+ reg = <0x0 0x200000>;
+ };
+
+ partition@400000 {
+ label = "Filesystem-0";
+ reg = <0x200000 0xe00000>;
+ };
+ };
+ };
+};
+
+&cp0_syscon0 {
+ cp0_pinctrl: pinctrl {
+ compatible = "marvell,cp115-standalone-pinctrl";
+
+ cp0_i2c0_pins: cp0-i2c-pins-0 {
+ marvell,pins = "mpp37", "mpp38";
+ marvell,function = "i2c0";
+ };
+ cp0_i2c1_pins: cp0-i2c-pins-1 {
+ marvell,pins = "mpp35", "mpp36";
+ marvell,function = "i2c1";
+ };
+ cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
+ marvell,pins = "mpp0", "mpp1", "mpp2",
+ "mpp3", "mpp4", "mpp5",
+ "mpp6", "mpp7", "mpp8",
+ "mpp9", "mpp10", "mpp11";
+ marvell,function = "ge0";
+ };
+ cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
+ marvell,pins = "mpp44", "mpp45", "mpp46",
+ "mpp47", "mpp48", "mpp49",
+ "mpp50", "mpp51", "mpp52",
+ "mpp53", "mpp54", "mpp55";
+ marvell,function = "ge1";
+ };
+ cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 {
+ marvell,pins = "mpp43";
+ marvell,function = "gpio";
+ };
+ cp0_sdhci_pins: cp0-sdhi-pins-0 {
+ marvell,pins = "mpp56", "mpp57", "mpp58",
+ "mpp59", "mpp60", "mpp61";
+ marvell,function = "sdio";
+ };
+ cp0_spi0_pins: cp0-spi-pins-0 {
+ marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
+ marvell,function = "spi1";
+ };
+ nand_pins: nand-pins {
+ marvell,pins = "mpp15", "mpp16", "mpp17", "mpp18",
+ "mpp19", "mpp20", "mpp21", "mpp22",
+ "mpp23", "mpp24", "mpp25", "mpp26",
+ "mpp27";
+ marvell,function = "dev";
+ };
+ nand_rb: nand-rb {
+ marvell,pins = "mpp13";
+ marvell,function = "nf";
+ };
+ };
+};
+
+&cp0_usb3_0 {
+ status = "okay";
+ usb-phy = <&cp0_usb3_0_phy0>;
+ phy-names = "usb";
+};
+
+&cp0_usb3_1 {
+ status = "okay";
+ usb-phy = <&cp0_usb3_0_phy1>;
+ phy-names = "usb";
+};
--
2.20.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH 19/20] arm64: dts: marvell: Add support for Marvell CN9131-DB
From: Miquel Raynal @ 2019-08-06 14:54 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: devicetree, Yan Markman, Antoine Tenart, Grzegorz Jaszczyk,
Gregory Clement, Maxime Chevallier, Nadav Haklai,
Thomas Petazzoni, Miquel Raynal, Stefan Chulski, Marcin Wojtas,
linux-arm-kernel
In-Reply-To: <20190806145500.24109-1-miquel.raynal@bootlin.com>
From: Grzegorz Jaszczyk <jaz@semihalf.com>
Extend the support of the CN9130 by adding an external CP115.
The last number indicates how many external CP115 are used.
New available interfaces:
* CP1 CRYPTO-0 (disabled)
* CP1 ETH-0 (SFI, problem with the SFP cage, disabled)
* CP1 GPIO-1
* CP1 GPIO-2
* CP1 I2C-0
* CP1 PCIe-0 x2
* CP1 SPI-1
* CP1 SATA-0-1
* CP1 USB3-1
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
arch/arm64/boot/dts/marvell/Makefile | 1 +
arch/arm64/boot/dts/marvell/cn9131-db.dts | 202 ++++++++++++++++++++++
2 files changed, 203 insertions(+)
create mode 100644 arch/arm64/boot/dts/marvell/cn9131-db.dts
diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile
index 922910d05863..92767d5be069 100644
--- a/arch/arm64/boot/dts/marvell/Makefile
+++ b/arch/arm64/boot/dts/marvell/Makefile
@@ -10,3 +10,4 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin-singleshot.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-8080-db.dtb
dtb-$(CONFIG_ARCH_MVEBU) += cn9130-db.dtb
+dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db.dtb
diff --git a/arch/arm64/boot/dts/marvell/cn9131-db.dts b/arch/arm64/boot/dts/marvell/cn9131-db.dts
new file mode 100644
index 000000000000..3c975f98b2a3
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/cn9131-db.dts
@@ -0,0 +1,202 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ *
+ * Device tree for the CN9131-DB board.
+ */
+
+#include "cn9130-db.dts"
+
+/ {
+ model = "Marvell Armada CN9131-DB";
+ compatible = "marvell,cn9131", "marvell,cn9130",
+ "marvell,armada-ap807-quad", "marvell,armada-ap807";
+
+ aliases {
+ gpio3 = &cp1_gpio1;
+ gpio4 = &cp1_gpio2;
+ ethernet3 = &cp1_eth0;
+ ethernet4 = &cp1_eth1;
+ };
+
+ cp1_reg_usb3_vbus0: cp1_usb3_vbus@0 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_xhci0_vbus_pins>;
+ regulator-name = "cp1-xhci0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&cp1_gpio1 3 GPIO_ACTIVE_HIGH>;
+ };
+
+ cp1_usb3_0_phy0: cp1_usb3_phy0 {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <&cp1_reg_usb3_vbus0>;
+ };
+
+ cp1_sfp_eth1: sfp-eth1 {
+ compatible = "sff,sfp";
+ i2c-bus = <&cp1_i2c0>;
+ los-gpio = <&cp1_gpio1 11 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&cp1_gpio1 10 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&cp1_gpio1 9 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_sfp_pins>;
+ /*
+ * SFP cages are unconnected on early PCBs because of an the I2C
+ * lanes not being connected. Prevent the port for being
+ * unusable by disabling the SFP node.
+ */
+ status = "disabled";
+ };
+};
+
+/*
+ * Instantiate the first slave CP115
+ */
+
+#define CP11X_NAME cp1
+#define CP11X_BASE f4000000
+#define CP11X_PCIEx_MEM_BASE(iface) (0xe2000000 + (iface * 0x1000000))
+#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
+#define CP11X_PCIE0_BASE f4600000
+#define CP11X_PCIE1_BASE f4620000
+#define CP11X_PCIE2_BASE f4640000
+
+#include "armada-cp115.dtsi"
+
+#undef CP11X_NAME
+#undef CP11X_BASE
+#undef CP11X_PCIEx_MEM_BASE
+#undef CP11X_PCIEx_MEM_SIZE
+#undef CP11X_PCIE0_BASE
+#undef CP11X_PCIE1_BASE
+#undef CP11X_PCIE2_BASE
+
+&cp1_crypto {
+ status = "disabled";
+};
+
+&cp1_ethernet {
+ status = "okay";
+};
+
+/* CON50 */
+&cp1_eth0 {
+ status = "disabled";
+ phy-mode = "10gbase-kr";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp1_comphy4 0>;
+ managed = "in-band-status";
+ sfp = <&cp1_sfp_eth1>;
+};
+
+&cp1_gpio1 {
+ status = "okay";
+};
+
+&cp1_gpio2 {
+ status = "okay";
+};
+
+&cp1_i2c0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_i2c0_pins>;
+ clock-frequency = <100000>;
+};
+
+/* CON40 */
+&cp1_pcie0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_pcie_reset_pins>;
+ num-lanes = <2>;
+ num-viewport = <8>;
+ marvell,reset-gpio = <&cp1_gpio1 0 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp1_comphy0 0
+ &cp1_comphy1 0>;
+};
+
+&cp1_sata0 {
+ status = "okay";
+
+ /* CON32 */
+ sata-port@1 {
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp1_comphy5 1>;
+ };
+};
+
+/* U24 */
+&cp1_spi1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp1_spi0_pins>;
+ reg = <0x700680 0x50>;
+
+ spi-flash@0 {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ compatible = "jedec,spi-nor";
+ reg = <0x0>;
+ /* On-board MUX does not allow higher frequencies */
+ spi-max-frequency = <40000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "U-Boot-1";
+ reg = <0x0 0x200000>;
+ };
+
+ partition@400000 {
+ label = "Filesystem-1";
+ reg = <0x200000 0xe00000>;
+ };
+ };
+ };
+
+};
+
+&cp1_syscon0 {
+ cp1_pinctrl: pinctrl {
+ compatible = "marvell,cp115-standalone-pinctrl";
+
+ cp1_i2c0_pins: cp1-i2c-pins-0 {
+ marvell,pins = "mpp37", "mpp38";
+ marvell,function = "i2c0";
+ };
+ cp1_spi0_pins: cp1-spi-pins-0 {
+ marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
+ marvell,function = "spi1";
+ };
+ cp1_xhci0_vbus_pins: cp1-xhci0-vbus-pins {
+ marvell,pins = "mpp3";
+ marvell,function = "gpio";
+ };
+ cp1_sfp_pins: sfp-pins {
+ marvell,pins = "mpp8", "mpp9", "mpp10", "mpp11";
+ marvell,function = "gpio";
+ };
+ cp1_pcie_reset_pins: cp1-pcie-reset-pins {
+ marvell,pins = "mpp0";
+ marvell,function = "gpio";
+ };
+ };
+};
+
+/* CON58 */
+&cp1_usb3_1 {
+ status = "okay";
+ usb-phy = <&cp1_usb3_0_phy0>;
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp1_comphy3 1>;
+ phy-names = "usb";
+};
--
2.20.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH 20/20] arm64: dts: marvell: Add support for Marvell CN9132-DB
From: Miquel Raynal @ 2019-08-06 14:55 UTC (permalink / raw)
To: Rob Herring, Mark Rutland
Cc: devicetree, Yan Markman, Antoine Tenart, Grzegorz Jaszczyk,
Gregory Clement, Maxime Chevallier, Nadav Haklai,
Thomas Petazzoni, Miquel Raynal, Stefan Chulski, Marcin Wojtas,
linux-arm-kernel
In-Reply-To: <20190806145500.24109-1-miquel.raynal@bootlin.com>
From: Grzegorz Jaszczyk <jaz@semihalf.com>
Extend the support of the CN9131 with yet another additional CP115.
The last number indicates how many external CP115 are used.
New available interfaces:
* CP2 CRYPTO-0 (disabled)
* CP2 ETH-0 (SFI, problem with the SFP cage, disabled)
* CP2 GPIO-1
* CP2 GPIO-2
* CP2 I2C-0
* CP2 PCIe-0 x2
* CP2 PCIe-2 x1 (disabled)
* CP2 SDHCI-0
* CP2 USB3-1 (High-speed)
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
arch/arm64/boot/dts/marvell/Makefile | 1 +
arch/arm64/boot/dts/marvell/cn9132-db.dts | 221 ++++++++++++++++++++++
2 files changed, 222 insertions(+)
create mode 100644 arch/arm64/boot/dts/marvell/cn9132-db.dts
diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile
index 92767d5be069..2af91b78d645 100644
--- a/arch/arm64/boot/dts/marvell/Makefile
+++ b/arch/arm64/boot/dts/marvell/Makefile
@@ -11,3 +11,4 @@ dtb-$(CONFIG_ARCH_MVEBU) += armada-8040-mcbin-singleshot.dtb
dtb-$(CONFIG_ARCH_MVEBU) += armada-8080-db.dtb
dtb-$(CONFIG_ARCH_MVEBU) += cn9130-db.dtb
dtb-$(CONFIG_ARCH_MVEBU) += cn9131-db.dtb
+dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb
diff --git a/arch/arm64/boot/dts/marvell/cn9132-db.dts b/arch/arm64/boot/dts/marvell/cn9132-db.dts
new file mode 100644
index 000000000000..4ef0df3097ca
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/cn9132-db.dts
@@ -0,0 +1,221 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ *
+ * Device tree for the CN9132-DB board.
+ */
+
+#include "cn9131-db.dts"
+
+/ {
+ model = "Marvell Armada CN9132-DB";
+ compatible = "marvell,cn9132", "marvell,cn9131", "marvell,cn9130",
+ "marvell,armada-ap807-quad", "marvell,armada-ap807";
+
+ aliases {
+ gpio5 = &cp2_gpio1;
+ gpio6 = &cp2_gpio2;
+ ethernet5 = &cp2_eth0;
+ };
+
+ cp2_reg_usb3_vbus0: cp2_usb3_vbus@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp2-xhci0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ cp2_usb3_0_phy0: cp2_usb3_phy0 {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <&cp2_reg_usb3_vbus0>;
+ };
+
+ cp2_reg_usb3_vbus1: cp2_usb3_vbus@1 {
+ compatible = "regulator-fixed";
+ regulator-name = "cp2-xhci1-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>;
+ };
+
+ cp2_usb3_0_phy1: cp2_usb3_phy1 {
+ compatible = "usb-nop-xceiv";
+ vcc-supply = <&cp2_reg_usb3_vbus1>;
+ };
+
+ cp2_reg_sd_vccq: cp2_sd_vccq@0 {
+ compatible = "regulator-gpio";
+ regulator-name = "cp2_sd_vcc";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ gpios = <&cp2_gpio2 17 GPIO_ACTIVE_HIGH>;
+ states = <1800000 0x1 3300000 0x0>;
+ };
+
+ cp2_sfp_eth0: sfp-eth0 {
+ compatible = "sff,sfp";
+ i2c-bus = <&cp2_sfpp0_i2c>;
+ los-gpio = <&cp2_module_expander1 11 GPIO_ACTIVE_HIGH>;
+ mod-def0-gpio = <&cp2_module_expander1 10 GPIO_ACTIVE_LOW>;
+ tx-disable-gpio = <&cp2_module_expander1 9 GPIO_ACTIVE_HIGH>;
+ tx-fault-gpio = <&cp2_module_expander1 8 GPIO_ACTIVE_HIGH>;
+ /*
+ * SFP cages are unconnected on early PCBs because of an the I2C
+ * lanes not being connected. Prevent the port for being
+ * unusable by disabling the SFP node.
+ */
+ status = "disabled";
+ };
+};
+
+/*
+ * Instantiate the second slave CP115
+ */
+
+#define CP11X_NAME cp2
+#define CP11X_BASE f6000000
+#define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000))
+#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
+#define CP11X_PCIE0_BASE f6600000
+#define CP11X_PCIE1_BASE f6620000
+#define CP11X_PCIE2_BASE f6640000
+
+#include "armada-cp115.dtsi"
+
+#undef CP11X_NAME
+#undef CP11X_BASE
+#undef CP11X_PCIEx_MEM_BASE
+#undef CP11X_PCIEx_MEM_SIZE
+#undef CP11X_PCIE0_BASE
+#undef CP11X_PCIE1_BASE
+#undef CP11X_PCIE2_BASE
+
+&cp2_crypto {
+ status = "disabled";
+};
+
+&cp2_ethernet {
+ status = "okay";
+};
+
+/* SLM-1521-V2, CON9 */
+&cp2_eth0 {
+ status = "disabled";
+ phy-mode = "10gbase-kr";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp2_comphy4 0>;
+ managed = "in-band-status";
+ sfp = <&cp2_sfp_eth0>;
+};
+
+&cp2_gpio1 {
+ status = "okay";
+};
+
+&cp2_gpio2 {
+ status = "okay";
+};
+
+&cp2_i2c0 {
+ clock-frequency = <100000>;
+
+ /* SLM-1521-V2 - U3 */
+ i2c-mux@72 {
+ compatible = "nxp,pca9544";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x72>;
+ cp2_sfpp0_i2c: i2c@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ };
+
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ /* U12 */
+ cp2_module_expander1: pca9555@21 {
+ compatible = "nxp,pca9555";
+ pinctrl-names = "default";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x21>;
+ };
+ };
+ };
+};
+
+/* SLM-1521-V2, CON6 */
+&cp2_pcie0 {
+ status = "okay";
+ num-lanes = <2>;
+ num-viewport = <8>;
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp2_comphy0 0
+ &cp2_comphy1 0>;
+};
+
+/* SLM-1521-V2, CON8 */
+&cp2_pcie2 {
+ status = "okay";
+ num-lanes = <1>;
+ num-viewport = <8>;
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp2_comphy5 2>;
+};
+
+&cp2_sata0 {
+ status = "okay";
+
+ /* SLM-1521-V2, CON4 */
+ sata-port@0 {
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp2_comphy2 0>;
+ };
+};
+
+/* CON 2 on SLM-1683 - microSD */
+&cp2_sdhci0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&cp2_sdhci_pins>;
+ bus-width = <4>;
+ cd-gpios = <&cp2_gpio2 23 GPIO_ACTIVE_LOW>;
+ vqmmc-supply = <&cp2_reg_sd_vccq>;
+};
+
+&cp2_syscon0 {
+ cp2_pinctrl: pinctrl {
+ compatible = "marvell,cp115-standalone-pinctrl";
+
+ cp2_i2c0_pins: cp2-i2c-pins-0 {
+ marvell,pins = "mpp37", "mpp38";
+ marvell,function = "i2c0";
+ };
+ cp2_sdhci_pins: cp2-sdhi-pins-0 {
+ marvell,pins = "mpp56", "mpp57", "mpp58",
+ "mpp59", "mpp60", "mpp61";
+ marvell,function = "sdio";
+ };
+ };
+};
+
+&cp2_usb3_0 {
+ status = "okay";
+ usb-phy = <&cp2_usb3_0_phy0>;
+ phy-names = "usb";
+};
+
+/* SLM-1521-V2, CON11 */
+&cp2_usb3_1 {
+ status = "okay";
+ usb-phy = <&cp2_usb3_0_phy1>;
+ phy-names = "usb";
+ /* Generic PHY, providing serdes lanes */
+ phys = <&cp2_comphy3 1>;
+};
--
2.20.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* Re: [PATCH V4 10/11] arm64: mm: Introduce 52-bit Kernel VAs
From: Catalin Marinas @ 2019-08-06 14:55 UTC (permalink / raw)
To: Steve Capper
Cc: crecklin, ard.biesheuvel, maz, bhsharma, will, linux-arm-kernel
In-Reply-To: <20190729162117.832-11-steve.capper@arm.com>
On Mon, Jul 29, 2019 at 05:21:16PM +0100, Steve Capper wrote:
> @@ -759,13 +759,14 @@ config ARM64_VA_BITS_47
> config ARM64_VA_BITS_48
> bool "48-bit"
>
> -config ARM64_USER_VA_BITS_52
> - bool "52-bit (user)"
> +config ARM64_VA_BITS_52
> + bool "52-bit"
I think we should change defconfig as well to make this the default. We
tend to make defconfig cover all the architecture features we support
and people can disable them if they get in the way (performance).
--
Catalin
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox