* [PATCH v5 05/18] thermal: sun8i: rework for sun8i_ths_get_temp()
From: Yangtao Li @ 2019-08-10 5:28 UTC (permalink / raw)
To: rui.zhang, edubezval, daniel.lezcano, robh+dt, mark.rutland,
maxime.ripard, wens, mchehab+samsung, davem, gregkh,
Jonathan.Cameron, nicolas.ferre
Cc: Yangtao Li, devicetree, linux-kernel, linux-arm-kernel, linux-pm
In-Reply-To: <20190810052829.6032-1-tiny.windzz@gmail.com>
For different socs, the way they get and calculate the
temperature is roughly the same. So get the difference
from device compatible.
Difference point:
1) temperature calculation formula parameters
2) ths data register start address
Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
---
drivers/thermal/sun8i_thermal.c | 17 +++++++++++------
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/thermal/sun8i_thermal.c b/drivers/thermal/sun8i_thermal.c
index e9c2acbaac74..f338fa25b98e 100644
--- a/drivers/thermal/sun8i_thermal.c
+++ b/drivers/thermal/sun8i_thermal.c
@@ -22,9 +22,6 @@
#define MAX_SENSOR_NUM 4
-#define SUN50I_H6_OFFSET -2794
-#define SUN50I_H6_SCALE -67
-
#define FT_TEMP_MASK GENMASK(11, 0)
#define TEMP_CALIB_MASK GENMASK(11, 0)
#define TEMP_TO_REG 672
@@ -58,6 +55,10 @@ struct tsensor {
struct ths_thermal_chip {
int sensor_num;
+ int offset;
+ int scale;
+ int ft_deviation;
+ int temp_data_base;
};
struct ths_device {
@@ -73,7 +74,7 @@ struct ths_device {
static int sun8i_ths_reg2temp(struct ths_device *tmdev,
int reg)
{
- return (reg + SUN50I_H6_OFFSET) * SUN50I_H6_SCALE;
+ return (reg + tmdev->chip->offset) * tmdev->chip->scale;
}
static int sun8i_ths_get_temp(void *data, int *temp)
@@ -82,7 +83,7 @@ static int sun8i_ths_get_temp(void *data, int *temp)
struct ths_device *tmdev = s->tmdev;
int val;
- regmap_read(tmdev->regmap, SUN50I_H6_THS_TEMP_DATA +
+ regmap_read(tmdev->regmap, tmdev->chip->temp_data_base +
0x4 * s->id, &val);
/* ths have no data yet */
@@ -98,7 +99,7 @@ static int sun8i_ths_get_temp(void *data, int *temp)
* temperature above is also used when the sensor is calibrated. If
* do this, the correct calibration formula is hard to know.
*/
- *temp += SUN50I_H6_FT_DEVIATION;
+ *temp += tmdev->chip->ft_deviation;
return 0;
}
@@ -389,6 +390,10 @@ static int sun8i_ths_remove(struct platform_device *pdev)
static const struct ths_thermal_chip sun50i_h6_ths = {
.sensor_num = 2,
+ .offset = -2794,
+ .scale = -67,
+ .ft_deviation = SUN50I_H6_FT_DEVIATION,
+ .temp_data_base = SUN50I_H6_THS_TEMP_DATA,
};
static const struct of_device_id of_ths_match[] = {
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v5 06/18] thermal: sun8i: get ths init func from device compatible
From: Yangtao Li @ 2019-08-10 5:28 UTC (permalink / raw)
To: rui.zhang, edubezval, daniel.lezcano, robh+dt, mark.rutland,
maxime.ripard, wens, mchehab+samsung, davem, gregkh,
Jonathan.Cameron, nicolas.ferre
Cc: Yangtao Li, devicetree, linux-kernel, linux-arm-kernel, linux-pm
In-Reply-To: <20190810052829.6032-1-tiny.windzz@gmail.com>
There are some differences in register initialization for
different socs. So we get different initialization functions
from device compatible.
Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
---
drivers/thermal/sun8i_thermal.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/thermal/sun8i_thermal.c b/drivers/thermal/sun8i_thermal.c
index f338fa25b98e..ad877b54f58e 100644
--- a/drivers/thermal/sun8i_thermal.c
+++ b/drivers/thermal/sun8i_thermal.c
@@ -59,6 +59,7 @@ struct ths_thermal_chip {
int scale;
int ft_deviation;
int temp_data_base;
+ int (*init)(struct ths_device *tmdev);
};
struct ths_device {
@@ -356,7 +357,7 @@ static int sun8i_ths_probe(struct platform_device *pdev)
if (irq < 0)
return irq;
- ret = sun50i_h6_thermal_init(tmdev);
+ ret = tmdev->chip->init(tmdev);
if (ret)
return ret;
@@ -394,6 +395,7 @@ static const struct ths_thermal_chip sun50i_h6_ths = {
.scale = -67,
.ft_deviation = SUN50I_H6_FT_DEVIATION,
.temp_data_base = SUN50I_H6_THS_TEMP_DATA,
+ .init = sun50i_h6_thermal_init,
};
static const struct of_device_id of_ths_match[] = {
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v5 07/18] thermal: sun8i: rework for ths irq handler func
From: Yangtao Li @ 2019-08-10 5:28 UTC (permalink / raw)
To: rui.zhang, edubezval, daniel.lezcano, robh+dt, mark.rutland,
maxime.ripard, wens, mchehab+samsung, davem, gregkh,
Jonathan.Cameron, nicolas.ferre
Cc: Yangtao Li, devicetree, linux-kernel, linux-arm-kernel, linux-pm
In-Reply-To: <20190810052829.6032-1-tiny.windzz@gmail.com>
Here, we do something to prepare for the subsequent
support of multiple platforms.
1) rename sun50i_h6_irq_thread to sun8i_irq_thread, because
this function should be suitable for all platforms.
2) introduce irq_ack callback to mask interrupt register
differences.
Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
---
drivers/thermal/sun8i_thermal.c | 27 ++++++++++++++++++++-------
1 file changed, 20 insertions(+), 7 deletions(-)
diff --git a/drivers/thermal/sun8i_thermal.c b/drivers/thermal/sun8i_thermal.c
index ad877b54f58e..b934bc81eba7 100644
--- a/drivers/thermal/sun8i_thermal.c
+++ b/drivers/thermal/sun8i_thermal.c
@@ -60,6 +60,7 @@ struct ths_thermal_chip {
int ft_deviation;
int temp_data_base;
int (*init)(struct ths_device *tmdev);
+ int (*irq_ack)(struct ths_device *tmdev);
};
struct ths_device {
@@ -116,23 +117,34 @@ static const struct regmap_config config = {
.fast_io = true,
};
-static irqreturn_t sun50i_h6_irq_thread(int irq, void *data)
+static int sun50i_h6_irq_ack(struct ths_device *tmdev)
{
- struct ths_device *tmdev = data;
- int i, state;
+ int i, state, ret = 0;
regmap_read(tmdev->regmap, SUN50I_H6_THS_DIS, &state);
for (i = 0; i < tmdev->chip->sensor_num; i++) {
-
if (state & SUN50I_H6_THS_DATA_IRQ_STS(i)) {
- /* clear data irq pending */
regmap_write(tmdev->regmap, SUN50I_H6_THS_DIS,
SUN50I_H6_THS_DATA_IRQ_STS(i));
+ ret |= BIT(i);
+ }
+ }
+
+ return ret;
+}
+static irqreturn_t sun8i_irq_thread(int irq, void *data)
+{
+ struct ths_device *tmdev = data;
+ int i, state;
+
+ state = tmdev->chip->irq_ack(tmdev);
+
+ for (i = 0; i < tmdev->chip->sensor_num; i++) {
+ if (state & BIT(i))
thermal_zone_device_update(tmdev->sensor[i].tzd,
THERMAL_EVENT_UNSPECIFIED);
- }
}
return IRQ_HANDLED;
@@ -371,7 +383,7 @@ static int sun8i_ths_probe(struct platform_device *pdev)
* the end.
*/
ret = devm_request_threaded_irq(dev, irq, NULL,
- sun50i_h6_irq_thread,
+ sun8i_irq_thread,
IRQF_ONESHOT, "ths", tmdev);
if (ret)
return ret;
@@ -396,6 +408,7 @@ static const struct ths_thermal_chip sun50i_h6_ths = {
.ft_deviation = SUN50I_H6_FT_DEVIATION,
.temp_data_base = SUN50I_H6_THS_TEMP_DATA,
.init = sun50i_h6_thermal_init,
+ .irq_ack = sun50i_h6_irq_ack,
};
static const struct of_device_id of_ths_match[] = {
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v5 08/18] thermal: sun8i: support mod clocks
From: Yangtao Li @ 2019-08-10 5:28 UTC (permalink / raw)
To: rui.zhang, edubezval, daniel.lezcano, robh+dt, mark.rutland,
maxime.ripard, wens, mchehab+samsung, davem, gregkh,
Jonathan.Cameron, nicolas.ferre
Cc: Yangtao Li, devicetree, linux-kernel, linux-arm-kernel, linux-pm
In-Reply-To: <20190810052829.6032-1-tiny.windzz@gmail.com>
H3 has extra clock, so introduce something in ths_thermal_chip/ths_device
and adds the process of the clock.
This is pre-work for supprt it.
Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
---
drivers/thermal/sun8i_thermal.c | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/thermal/sun8i_thermal.c b/drivers/thermal/sun8i_thermal.c
index b934bc81eba7..6f4294c2aba7 100644
--- a/drivers/thermal/sun8i_thermal.c
+++ b/drivers/thermal/sun8i_thermal.c
@@ -54,6 +54,7 @@ struct tsensor {
};
struct ths_thermal_chip {
+ bool has_mod_clk;
int sensor_num;
int offset;
int scale;
@@ -69,6 +70,7 @@ struct ths_device {
struct regmap *regmap;
struct reset_control *reset;
struct clk *bus_clk;
+ struct clk *mod_clk;
struct tsensor sensor[MAX_SENSOR_NUM];
};
@@ -274,6 +276,12 @@ static int sun8i_ths_resource_init(struct ths_device *tmdev)
if (IS_ERR(tmdev->bus_clk))
return PTR_ERR(tmdev->bus_clk);
+ if (tmdev->chip->has_mod_clk) {
+ tmdev->mod_clk = devm_clk_get(&pdev->dev, "mod");
+ if (IS_ERR(tmdev->mod_clk))
+ return PTR_ERR(tmdev->mod_clk);
+ }
+
ret = reset_control_deassert(tmdev->reset);
if (ret)
return ret;
@@ -282,12 +290,18 @@ static int sun8i_ths_resource_init(struct ths_device *tmdev)
if (ret)
goto assert_reset;
- ret = sun50i_ths_calibrate(tmdev);
+ ret = clk_prepare_enable(tmdev->mod_clk);
if (ret)
goto bus_disable;
+ ret = sun50i_ths_calibrate(tmdev);
+ if (ret)
+ goto mod_disable;
+
return 0;
+mod_disable:
+ clk_disable_unprepare(tmdev->mod_clk);
bus_disable:
clk_disable_unprepare(tmdev->bus_clk);
assert_reset:
@@ -395,6 +409,7 @@ static int sun8i_ths_remove(struct platform_device *pdev)
{
struct ths_device *tmdev = platform_get_drvdata(pdev);
+ clk_disable_unprepare(tmdev->mod_clk);
clk_disable_unprepare(tmdev->bus_clk);
reset_control_assert(tmdev->reset);
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v5 09/18] thermal: sun8i: rework for ths calibrate func
From: Yangtao Li @ 2019-08-10 5:28 UTC (permalink / raw)
To: rui.zhang, edubezval, daniel.lezcano, robh+dt, mark.rutland,
maxime.ripard, wens, mchehab+samsung, davem, gregkh,
Jonathan.Cameron, nicolas.ferre
Cc: Yangtao Li, devicetree, linux-kernel, linux-arm-kernel, linux-pm
In-Reply-To: <20190810052829.6032-1-tiny.windzz@gmail.com>
Here, we do something to prepare for the subsequent
support of multiple platforms.
1) rename sun50i_ths_calibrate to sun8i_ths_calibrate, because
this function should be suitable for all platforms now.
2) introduce calibrate callback to mask calibration method
differences.
Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
---
drivers/thermal/sun8i_thermal.c | 86 ++++++++++++++++++---------------
1 file changed, 48 insertions(+), 38 deletions(-)
diff --git a/drivers/thermal/sun8i_thermal.c b/drivers/thermal/sun8i_thermal.c
index 6f4294c2aba7..47c20c4c69e7 100644
--- a/drivers/thermal/sun8i_thermal.c
+++ b/drivers/thermal/sun8i_thermal.c
@@ -60,6 +60,8 @@ struct ths_thermal_chip {
int scale;
int ft_deviation;
int temp_data_base;
+ int (*calibrate)(struct ths_device *tmdev,
+ u16 *caldata, int callen);
int (*init)(struct ths_device *tmdev);
int (*irq_ack)(struct ths_device *tmdev);
};
@@ -152,45 +154,14 @@ static irqreturn_t sun8i_irq_thread(int irq, void *data)
return IRQ_HANDLED;
}
-static int sun50i_ths_calibrate(struct ths_device *tmdev)
+static int sun50i_h6_ths_calibrate(struct ths_device *tmdev,
+ u16 *caldata, int callen)
{
- struct nvmem_cell *calcell;
struct device *dev = tmdev->dev;
- u16 *caldata;
- size_t callen;
- int ft_temp;
- int i, ret = 0;
-
- calcell = devm_nvmem_cell_get(dev, "calib");
- if (IS_ERR(calcell)) {
- if (PTR_ERR(calcell) == -EPROBE_DEFER)
- return -EPROBE_DEFER;
- /*
- * Even if the external calibration data stored in sid is
- * not accessible, the THS hardware can still work, although
- * the data won't be so accurate.
- *
- * The default value of calibration register is 0x800 for
- * every sensor, and the calibration value is usually 0x7xx
- * or 0x8xx, so they won't be away from the default value
- * for a lot.
- *
- * So here we do not return error if the calibartion data is
- * not available, except the probe needs deferring.
- */
- goto out;
- }
+ int i, ft_temp;
- caldata = nvmem_cell_read(calcell, &callen);
- if (IS_ERR(caldata)) {
- ret = PTR_ERR(caldata);
- goto out;
- }
-
- if (!caldata[0] || callen < 2 + 2 * tmdev->chip->sensor_num) {
- ret = -EINVAL;
- goto out_free;
- }
+ if (!caldata[0] || callen < 2 + 2 * tmdev->chip->sensor_num)
+ return -EINVAL;
/*
* efuse layout:
@@ -245,7 +216,45 @@ static int sun50i_ths_calibrate(struct ths_device *tmdev)
cdata << offset);
}
-out_free:
+ return 0;
+}
+
+static int sun8i_ths_calibrate(struct ths_device *tmdev)
+{
+ struct nvmem_cell *calcell;
+ struct device *dev = tmdev->dev;
+ u16 *caldata;
+ size_t callen;
+ int ret = 0;
+
+ calcell = devm_nvmem_cell_get(dev, "calib");
+ if (IS_ERR(calcell)) {
+ if (PTR_ERR(calcell) == -EPROBE_DEFER)
+ return -EPROBE_DEFER;
+ /*
+ * Even if the external calibration data stored in sid is
+ * not accessible, the THS hardware can still work, although
+ * the data won't be so accurate.
+ *
+ * The default value of calibration register is 0x800 for
+ * every sensor, and the calibration value is usually 0x7xx
+ * or 0x8xx, so they won't be away from the default value
+ * for a lot.
+ *
+ * So here we do not return error if the calibartion data is
+ * not available, except the probe needs deferring.
+ */
+ goto out;
+ }
+
+ caldata = nvmem_cell_read(calcell, &callen);
+ if (IS_ERR(caldata)) {
+ ret = PTR_ERR(caldata);
+ goto out;
+ }
+
+ tmdev->chip->calibrate(tmdev, caldata, callen);
+
kfree(caldata);
out:
return ret;
@@ -294,7 +303,7 @@ static int sun8i_ths_resource_init(struct ths_device *tmdev)
if (ret)
goto bus_disable;
- ret = sun50i_ths_calibrate(tmdev);
+ ret = sun8i_ths_calibrate(tmdev);
if (ret)
goto mod_disable;
@@ -422,6 +431,7 @@ static const struct ths_thermal_chip sun50i_h6_ths = {
.scale = -67,
.ft_deviation = SUN50I_H6_FT_DEVIATION,
.temp_data_base = SUN50I_H6_THS_TEMP_DATA,
+ .calibrate = sun50i_h6_ths_calibrate,
.init = sun50i_h6_thermal_init,
.irq_ack = sun50i_h6_irq_ack,
};
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v5 10/18] dt-bindings: thermal: add binding document for h3 thermal controller
From: Yangtao Li @ 2019-08-10 5:28 UTC (permalink / raw)
To: rui.zhang, edubezval, daniel.lezcano, robh+dt, mark.rutland,
maxime.ripard, wens, mchehab+samsung, davem, gregkh,
Jonathan.Cameron, nicolas.ferre
Cc: Yangtao Li, devicetree, linux-kernel, linux-arm-kernel, linux-pm
In-Reply-To: <20190810052829.6032-1-tiny.windzz@gmail.com>
This patch adds binding document for allwinner h3 thermal controller.
Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
---
.../bindings/thermal/sun8i-thermal.yaml | 81 ++++++++++++++++++-
1 file changed, 78 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/thermal/sun8i-thermal.yaml b/Documentation/devicetree/bindings/thermal/sun8i-thermal.yaml
index e0973199ba3c..6624cf6b1ce8 100644
--- a/Documentation/devicetree/bindings/thermal/sun8i-thermal.yaml
+++ b/Documentation/devicetree/bindings/thermal/sun8i-thermal.yaml
@@ -16,6 +16,7 @@ description: |-
properties:
compatible:
enum:
+ - allwinner,sun8i-h3-ths
- allwinner,sun50i-h6-ths
reg:
@@ -28,13 +29,21 @@ properties:
maxItems: 1
clocks:
- maxItems: 1
+ minItems: 1
+ maxItems: 2
+ items:
+ - description: ths bus clock
+ - description: ths mod clock
clock-names:
- const: bus
+ minItems: 1
+ maxItems: 2
+ items:
+ - const: bus
+ - const: mod
"#thermal-sensor-cells":
- const: 1
+ enum: [ 0, 1 ]
nvmem-cells:
description: ths calibrate data
@@ -51,9 +60,75 @@ required:
- interrupts
- "#thermal-sensor-cells"
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: allwinner,sun50i-h6-ths
+
+ then:
+ properties:
+ clocks:
+ minItems: 1
+ maxItems: 1
+
+ clock-names:
+ minItems: 1
+ maxItems: 1
+
+ else:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+
+ clock-names:
+ minItems: 2
+ maxItems: 2
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: allwinner,sun8i-h3-ths
+
+ then:
+ properties:
+ "#thermal-sensor-cells":
+ const: 0
+
+ else:
+ properties:
+ "#thermal-sensor-cells":
+ const: 1
+
additionalProperties: false
examples:
+ - |
+ ths: ths@1c25000 {
+ compatible = "allwinner,sun8i-h3-ths";
+ reg = <0x01c25000 0x400>;
+ clocks = <&ccu CLK_BUS_THS>, <&ccu CLK_THS>;
+ clock-names = "bus", "mod";
+ resets = <&ccu RST_BUS_THS>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ nvmem-cells = <&tsen_calib>;
+ nvmem-cell-names = "calib";
+ #thermal-sensor-cells = <0>;
+ };
+
+ sid: sid@1c14000 {
+ compatible = "allwinner,sun8i-h3-sid";
+ reg = <0x1c14000 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ tsen_calib: calib@34 {
+ reg = <0x34 2>;
+ };
+ };
+
- |
ths: ths@5070400 {
compatible = "allwinner,sun50i-h6-ths";
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v5 11/18] thermal: sun8i: add thermal driver for h3
From: Yangtao Li @ 2019-08-10 5:28 UTC (permalink / raw)
To: rui.zhang, edubezval, daniel.lezcano, robh+dt, mark.rutland,
maxime.ripard, wens, mchehab+samsung, davem, gregkh,
Jonathan.Cameron, nicolas.ferre
Cc: Yangtao Li, devicetree, linux-kernel, linux-arm-kernel, linux-pm
In-Reply-To: <20190810052829.6032-1-tiny.windzz@gmail.com>
This patch adds the support for allwinner h3 thermal sensor.
Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
---
drivers/thermal/sun8i_thermal.c | 91 +++++++++++++++++++++++++++++++++
1 file changed, 91 insertions(+)
diff --git a/drivers/thermal/sun8i_thermal.c b/drivers/thermal/sun8i_thermal.c
index 47c20c4c69e7..41ce8cdc0546 100644
--- a/drivers/thermal/sun8i_thermal.c
+++ b/drivers/thermal/sun8i_thermal.c
@@ -27,6 +27,14 @@
#define TEMP_TO_REG 672
#define CALIBRATE_DEFAULT 0x800
+#define SUN8I_THS_CTRL0 0x00
+#define SUN8I_THS_CTRL2 0x40
+#define SUN8I_THS_IC 0x44
+#define SUN8I_THS_IS 0x48
+#define SUN8I_THS_MFC 0x70
+#define SUN8I_THS_TEMP_CALIB 0x74
+#define SUN8I_THS_TEMP_DATA 0x80
+
#define SUN50I_THS_CTRL0 0x00
#define SUN50I_H6_THS_ENABLE 0x04
#define SUN50I_H6_THS_PC 0x08
@@ -36,6 +44,10 @@
#define SUN50I_H6_THS_TEMP_CALIB 0xa0
#define SUN50I_H6_THS_TEMP_DATA 0xc0
+#define SUN8I_THS_CTRL0_T_ACQ0(x) (GENMASK(15, 0) & (x))
+#define SUN8I_THS_CTRL2_T_ACQ1(x) ((GENMASK(15, 0) & (x)) << 16)
+#define SUN8I_THS_DATA_IRQ_STS(x) BIT(x + 8)
+
#define SUN50I_THS_CTRL0_T_ACQ(x) ((GENMASK(15, 0) & (x)) << 16)
#define SUN50I_THS_FILTER_EN BIT(2)
#define SUN50I_THS_FILTER_TYPE(x) (GENMASK(1, 0) & (x))
@@ -121,6 +133,23 @@ static const struct regmap_config config = {
.fast_io = true,
};
+static int sun8i_h3_irq_ack(struct ths_device *tmdev)
+{
+ int i, state, ret = 0;
+
+ regmap_read(tmdev->regmap, SUN8I_THS_IS, &state);
+
+ for (i = 0; i < tmdev->chip->sensor_num; i++) {
+ if (state & SUN8I_THS_DATA_IRQ_STS(i)) {
+ regmap_write(tmdev->regmap, SUN8I_THS_IS,
+ SUN8I_THS_DATA_IRQ_STS(i));
+ ret |= BIT(i);
+ }
+ }
+
+ return ret;
+}
+
static int sun50i_h6_irq_ack(struct ths_device *tmdev)
{
int i, state, ret = 0;
@@ -154,6 +183,26 @@ static irqreturn_t sun8i_irq_thread(int irq, void *data)
return IRQ_HANDLED;
}
+static int sun8i_h3_ths_calibrate(struct ths_device *tmdev,
+ u16 *caldata, int callen)
+{
+ int i;
+
+ if (!caldata[0] || callen < 2 * tmdev->chip->sensor_num)
+ return -EINVAL;
+
+ for (i = 0; i < tmdev->chip->sensor_num; i++) {
+ int offset = (i % 2) << 4;
+
+ regmap_update_bits(tmdev->regmap,
+ SUN8I_THS_TEMP_CALIB + (4 * (i >> 1)),
+ 0xfff << offset,
+ caldata[i] << offset);
+ }
+
+ return 0;
+}
+
static int sun50i_h6_ths_calibrate(struct ths_device *tmdev,
u16 *caldata, int callen)
{
@@ -319,6 +368,36 @@ static int sun8i_ths_resource_init(struct ths_device *tmdev)
return ret;
}
+static int sun8i_h3_thermal_init(struct ths_device *tmdev)
+{
+ int val;
+
+ /* average over 4 samples */
+ regmap_write(tmdev->regmap, SUN8I_THS_MFC,
+ SUN50I_THS_FILTER_EN |
+ SUN50I_THS_FILTER_TYPE(1));
+ /*
+ * period = (x + 1) * 4096 / clkin; ~10ms
+ * enable data interrupt
+ */
+ val = GENMASK(7 + tmdev->chip->sensor_num, 8);
+ regmap_write(tmdev->regmap, SUN8I_THS_IC,
+ SUN50I_H6_THS_PC_TEMP_PERIOD(58) | val);
+ /*
+ * clkin = 24MHz
+ * T acquire = clkin / (x + 1)
+ * = 20us
+ * enable sensor
+ */
+ regmap_write(tmdev->regmap, SUN8I_THS_CTRL0,
+ SUN8I_THS_CTRL0_T_ACQ0(479));
+ val = GENMASK(tmdev->chip->sensor_num - 1, 0);
+ regmap_write(tmdev->regmap, SUN8I_THS_CTRL2,
+ SUN8I_THS_CTRL2_T_ACQ1(479) | val);
+
+ return 0;
+}
+
static int sun50i_h6_thermal_init(struct ths_device *tmdev)
{
int val;
@@ -425,6 +504,17 @@ static int sun8i_ths_remove(struct platform_device *pdev)
return 0;
}
+static const struct ths_thermal_chip sun8i_h3_ths = {
+ .sensor_num = 1,
+ .offset = -1794,
+ .scale = -121,
+ .has_mod_clk = true,
+ .temp_data_base = SUN8I_THS_TEMP_DATA,
+ .calibrate = sun8i_h3_ths_calibrate,
+ .init = sun8i_h3_thermal_init,
+ .irq_ack = sun8i_h3_irq_ack,
+};
+
static const struct ths_thermal_chip sun50i_h6_ths = {
.sensor_num = 2,
.offset = -2794,
@@ -437,6 +527,7 @@ static const struct ths_thermal_chip sun50i_h6_ths = {
};
static const struct of_device_id of_ths_match[] = {
+ { .compatible = "allwinner,sun8i-h3-ths", .data = &sun8i_h3_ths },
{ .compatible = "allwinner,sun50i-h6-ths", .data = &sun50i_h6_ths },
{ /* sentinel */ },
};
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v5 12/18] dt-bindings: thermal: add binding document for a64 thermal controller
From: Yangtao Li @ 2019-08-10 5:28 UTC (permalink / raw)
To: rui.zhang, edubezval, daniel.lezcano, robh+dt, mark.rutland,
maxime.ripard, wens, mchehab+samsung, davem, gregkh,
Jonathan.Cameron, nicolas.ferre
Cc: Yangtao Li, devicetree, linux-kernel, linux-arm-kernel, linux-pm
In-Reply-To: <20190810052829.6032-1-tiny.windzz@gmail.com>
This patch adds binding document for allwinner a64 thermal controller.
Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
---
Documentation/devicetree/bindings/thermal/sun8i-thermal.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/thermal/sun8i-thermal.yaml b/Documentation/devicetree/bindings/thermal/sun8i-thermal.yaml
index 6624cf6b1ce8..f935b4fab8ec 100644
--- a/Documentation/devicetree/bindings/thermal/sun8i-thermal.yaml
+++ b/Documentation/devicetree/bindings/thermal/sun8i-thermal.yaml
@@ -17,6 +17,7 @@ properties:
compatible:
enum:
- allwinner,sun8i-h3-ths
+ - allwinner,sun50i-a64-ths
- allwinner,sun50i-h6-ths
reg:
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v5 13/18] thermal: sun8i: add thermal driver for A64
From: Yangtao Li @ 2019-08-10 5:28 UTC (permalink / raw)
To: rui.zhang, edubezval, daniel.lezcano, robh+dt, mark.rutland,
maxime.ripard, wens, mchehab+samsung, davem, gregkh,
Jonathan.Cameron, nicolas.ferre
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-pm
In-Reply-To: <20190810052829.6032-1-tiny.windzz@gmail.com>
From: Vasily Khoruzhick <anarsoul@gmail.com>
Thermal sensor controller in A64 is similar to H3, but it has 3 sensors.
Extend H3 functions to add support for multiple sensors.
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
---
drivers/thermal/sun8i_thermal.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/thermal/sun8i_thermal.c b/drivers/thermal/sun8i_thermal.c
index 41ce8cdc0546..3259081da841 100644
--- a/drivers/thermal/sun8i_thermal.c
+++ b/drivers/thermal/sun8i_thermal.c
@@ -515,6 +515,17 @@ static const struct ths_thermal_chip sun8i_h3_ths = {
.irq_ack = sun8i_h3_irq_ack,
};
+static const struct ths_thermal_chip sun50i_a64_ths = {
+ .sensor_num = 3,
+ .offset = -2170,
+ .scale = -117,
+ .has_mod_clk = true,
+ .temp_data_base = SUN8I_THS_TEMP_DATA,
+ .calibrate = sun8i_h3_ths_calibrate,
+ .init = sun8i_h3_thermal_init,
+ .irq_ack = sun8i_h3_irq_ack,
+};
+
static const struct ths_thermal_chip sun50i_h6_ths = {
.sensor_num = 2,
.offset = -2794,
@@ -528,6 +539,7 @@ static const struct ths_thermal_chip sun50i_h6_ths = {
static const struct of_device_id of_ths_match[] = {
{ .compatible = "allwinner,sun8i-h3-ths", .data = &sun8i_h3_ths },
+ { .compatible = "allwinner,sun50i-a64-ths", .data = &sun50i_a64_ths },
{ .compatible = "allwinner,sun50i-h6-ths", .data = &sun50i_h6_ths },
{ /* sentinel */ },
};
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v5 14/18] dt-bindings: thermal: add binding document for h5 thermal controller
From: Yangtao Li @ 2019-08-10 5:28 UTC (permalink / raw)
To: rui.zhang, edubezval, daniel.lezcano, robh+dt, mark.rutland,
maxime.ripard, wens, mchehab+samsung, davem, gregkh,
Jonathan.Cameron, nicolas.ferre
Cc: Yangtao Li, devicetree, linux-kernel, linux-arm-kernel, linux-pm
In-Reply-To: <20190810052829.6032-1-tiny.windzz@gmail.com>
This patch adds binding document for allwinner h5 thermal controller.
Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
---
Documentation/devicetree/bindings/thermal/sun8i-thermal.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/thermal/sun8i-thermal.yaml b/Documentation/devicetree/bindings/thermal/sun8i-thermal.yaml
index f935b4fab8ec..2e28f5b33d33 100644
--- a/Documentation/devicetree/bindings/thermal/sun8i-thermal.yaml
+++ b/Documentation/devicetree/bindings/thermal/sun8i-thermal.yaml
@@ -18,6 +18,7 @@ properties:
enum:
- allwinner,sun8i-h3-ths
- allwinner,sun50i-a64-ths
+ - allwinner,sun50i-h5-ths
- allwinner,sun50i-h6-ths
reg:
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v5 15/18] thermal: sun8i: allow to use custom temperature calculation function
From: Yangtao Li @ 2019-08-10 5:28 UTC (permalink / raw)
To: rui.zhang, edubezval, daniel.lezcano, robh+dt, mark.rutland,
maxime.ripard, wens, mchehab+samsung, davem, gregkh,
Jonathan.Cameron, nicolas.ferre
Cc: devicetree, Icenowy Zheng, linux-kernel, linux-arm-kernel,
linux-pm
In-Reply-To: <20190810052829.6032-1-tiny.windzz@gmail.com>
From: Icenowy Zheng <icenowy@aosc.io>
The H5 temperature calculation function is strange. Firstly, it's
segmented. Secondly, the formula of two sensors are different in the
second segment.
Allow to use a custom temperature calculation function, in case of
the function is complex.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
drivers/thermal/sun8i_thermal.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/thermal/sun8i_thermal.c b/drivers/thermal/sun8i_thermal.c
index 3259081da841..a761e2afda08 100644
--- a/drivers/thermal/sun8i_thermal.c
+++ b/drivers/thermal/sun8i_thermal.c
@@ -76,6 +76,7 @@ struct ths_thermal_chip {
u16 *caldata, int callen);
int (*init)(struct ths_device *tmdev);
int (*irq_ack)(struct ths_device *tmdev);
+ int (*calc_temp)(int id, int reg);
};
struct ths_device {
@@ -90,9 +91,12 @@ struct ths_device {
/* Temp Unit: millidegree Celsius */
static int sun8i_ths_reg2temp(struct ths_device *tmdev,
- int reg)
+ int id, int reg)
{
- return (reg + tmdev->chip->offset) * tmdev->chip->scale;
+ if (tmdev->chip->calc_temp)
+ return tmdev->chip->calc_temp(id, reg);
+ else
+ return (reg + tmdev->chip->offset) * tmdev->chip->scale;
}
static int sun8i_ths_get_temp(void *data, int *temp)
@@ -108,7 +112,7 @@ static int sun8i_ths_get_temp(void *data, int *temp)
if (!val)
return -EAGAIN;
- *temp = sun8i_ths_reg2temp(tmdev, val);
+ *temp = sun8i_ths_reg2temp(tmdev, s->id, val);
/*
* XX - According to the original sdk, there are some platforms(rarely)
* that add a fixed offset value after calculating the temperature
@@ -232,7 +236,7 @@ static int sun50i_h6_ths_calibrate(struct ths_device *tmdev,
for (i = 0; i < tmdev->chip->sensor_num; i++) {
int reg = (int)caldata[i + 1];
- int sensor_temp = sun8i_ths_reg2temp(tmdev, reg);
+ int sensor_temp = sun8i_ths_reg2temp(tmdev, i, reg);
int delta, cdata, offset;
/*
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v5 16/18] thermal: sun8i: add support for Allwinner H5 thermal sensor
From: Yangtao Li @ 2019-08-10 5:28 UTC (permalink / raw)
To: rui.zhang, edubezval, daniel.lezcano, robh+dt, mark.rutland,
maxime.ripard, wens, mchehab+samsung, davem, gregkh,
Jonathan.Cameron, nicolas.ferre
Cc: devicetree, Icenowy Zheng, linux-kernel, linux-arm-kernel,
linux-pm
In-Reply-To: <20190810052829.6032-1-tiny.windzz@gmail.com>
From: Icenowy Zheng <icenowy@aosc.io>
The thermal sensor in Allwinner H5 has 2 sensors, and they have a
special segmented temperature calculation formula.
Add support for this thermal sensor.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
drivers/thermal/sun8i_thermal.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/drivers/thermal/sun8i_thermal.c b/drivers/thermal/sun8i_thermal.c
index a761e2afda08..78a888d85cba 100644
--- a/drivers/thermal/sun8i_thermal.c
+++ b/drivers/thermal/sun8i_thermal.c
@@ -99,6 +99,16 @@ static int sun8i_ths_reg2temp(struct ths_device *tmdev,
return (reg + tmdev->chip->offset) * tmdev->chip->scale;
}
+static int sun50i_h5_calc_temp(int id, int reg)
+{
+ if (reg >= 0x500)
+ return -1191 * reg / 10 + 223000;
+ else if (!id)
+ return -1452 * reg / 10 + 259000;
+ else
+ return -1590 * reg / 10 + 276000;
+}
+
static int sun8i_ths_get_temp(void *data, int *temp)
{
struct tsensor *s = data;
@@ -530,6 +540,16 @@ static const struct ths_thermal_chip sun50i_a64_ths = {
.irq_ack = sun8i_h3_irq_ack,
};
+static const struct ths_thermal_chip sun50i_h5_ths = {
+ .sensor_num = 2,
+ .has_mod_clk = true,
+ .temp_data_base = SUN8I_THS_TEMP_DATA,
+ .calibrate = sun8i_h3_ths_calibrate,
+ .init = sun8i_h3_thermal_init,
+ .irq_ack = sun8i_h3_irq_ack,
+ .calc_temp = sun50i_h5_calc_temp,
+};
+
static const struct ths_thermal_chip sun50i_h6_ths = {
.sensor_num = 2,
.offset = -2794,
@@ -544,6 +564,7 @@ static const struct ths_thermal_chip sun50i_h6_ths = {
static const struct of_device_id of_ths_match[] = {
{ .compatible = "allwinner,sun8i-h3-ths", .data = &sun8i_h3_ths },
{ .compatible = "allwinner,sun50i-a64-ths", .data = &sun50i_a64_ths },
+ { .compatible = "allwinner,sun50i-h5-ths", .data = &sun50i_h5_ths },
{ .compatible = "allwinner,sun50i-h6-ths", .data = &sun50i_h6_ths },
{ /* sentinel */ },
};
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v5 17/18] dt-bindings: thermal: add binding document for r40 thermal controller
From: Yangtao Li @ 2019-08-10 5:28 UTC (permalink / raw)
To: rui.zhang, edubezval, daniel.lezcano, robh+dt, mark.rutland,
maxime.ripard, wens, mchehab+samsung, davem, gregkh,
Jonathan.Cameron, nicolas.ferre
Cc: Yangtao Li, devicetree, linux-kernel, linux-arm-kernel, linux-pm
In-Reply-To: <20190810052829.6032-1-tiny.windzz@gmail.com>
This patch adds binding document for allwinner r40 thermal controller.
Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
---
Documentation/devicetree/bindings/thermal/sun8i-thermal.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/thermal/sun8i-thermal.yaml b/Documentation/devicetree/bindings/thermal/sun8i-thermal.yaml
index 2e28f5b33d33..28c438d3bfea 100644
--- a/Documentation/devicetree/bindings/thermal/sun8i-thermal.yaml
+++ b/Documentation/devicetree/bindings/thermal/sun8i-thermal.yaml
@@ -17,6 +17,7 @@ properties:
compatible:
enum:
- allwinner,sun8i-h3-ths
+ - allwinner,sun8i-r40-ths
- allwinner,sun50i-a64-ths
- allwinner,sun50i-h5-ths
- allwinner,sun50i-h6-ths
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v5 18/18] thermal: sun8i: add support for Allwinner R40 thermal sensor
From: Yangtao Li @ 2019-08-10 5:28 UTC (permalink / raw)
To: rui.zhang, edubezval, daniel.lezcano, robh+dt, mark.rutland,
maxime.ripard, wens, mchehab+samsung, davem, gregkh,
Jonathan.Cameron, nicolas.ferre
Cc: devicetree, Icenowy Zheng, linux-kernel, linux-arm-kernel,
linux-pm
In-Reply-To: <20190810052829.6032-1-tiny.windzz@gmail.com>
From: Icenowy Zheng <icenowy@aosc.io>
The thermal sensor in Allwinner R40 SoC is quite similar to the one in
Allwinner A64 SoC, with only slightly different temperature calculation
formula.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
drivers/thermal/sun8i_thermal.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/thermal/sun8i_thermal.c b/drivers/thermal/sun8i_thermal.c
index 78a888d85cba..0de9a56c3775 100644
--- a/drivers/thermal/sun8i_thermal.c
+++ b/drivers/thermal/sun8i_thermal.c
@@ -529,6 +529,17 @@ static const struct ths_thermal_chip sun8i_h3_ths = {
.irq_ack = sun8i_h3_irq_ack,
};
+static const struct ths_thermal_chip sun8i_r40_ths = {
+ .sensor_num = 3,
+ .offset = -2222,
+ .scale = -113,
+ .has_mod_clk = true,
+ .temp_data_base = SUN8I_THS_TEMP_DATA,
+ .calibrate = sun8i_h3_ths_calibrate,
+ .init = sun8i_h3_thermal_init,
+ .irq_ack = sun8i_h3_irq_ack,
+};
+
static const struct ths_thermal_chip sun50i_a64_ths = {
.sensor_num = 3,
.offset = -2170,
@@ -563,6 +574,7 @@ static const struct ths_thermal_chip sun50i_h6_ths = {
static const struct of_device_id of_ths_match[] = {
{ .compatible = "allwinner,sun8i-h3-ths", .data = &sun8i_h3_ths },
+ { .compatible = "allwinner,sun8i-r40-ths", .data = &sun8i_r40_ths },
{ .compatible = "allwinner,sun50i-a64-ths", .data = &sun50i_a64_ths },
{ .compatible = "allwinner,sun50i-h5-ths", .data = &sun50i_h5_ths },
{ .compatible = "allwinner,sun50i-h6-ths", .data = &sun50i_h6_ths },
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v5 13/18] thermal: sun8i: add thermal driver for A64
From: Yangtao Li @ 2019-08-10 5:32 UTC (permalink / raw)
To: rui.zhang, edubezval, daniel.lezcano, robh+dt, mark.rutland,
maxime.ripard, wens, mchehab+samsung, davem, gregkh,
Jonathan.Cameron, nicolas.ferre
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-pm
From: Vasily Khoruzhick <anarsoul@gmail.com>
Thermal sensor controller in A64 is similar to H3, but it has 3 sensors.
Extend H3 functions to add support for multiple sensors.
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
---
drivers/thermal/sun8i_thermal.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/thermal/sun8i_thermal.c b/drivers/thermal/sun8i_thermal.c
index 41ce8cdc0546..3259081da841 100644
--- a/drivers/thermal/sun8i_thermal.c
+++ b/drivers/thermal/sun8i_thermal.c
@@ -515,6 +515,17 @@ static const struct ths_thermal_chip sun8i_h3_ths = {
.irq_ack = sun8i_h3_irq_ack,
};
+static const struct ths_thermal_chip sun50i_a64_ths = {
+ .sensor_num = 3,
+ .offset = -2170,
+ .scale = -117,
+ .has_mod_clk = true,
+ .temp_data_base = SUN8I_THS_TEMP_DATA,
+ .calibrate = sun8i_h3_ths_calibrate,
+ .init = sun8i_h3_thermal_init,
+ .irq_ack = sun8i_h3_irq_ack,
+};
+
static const struct ths_thermal_chip sun50i_h6_ths = {
.sensor_num = 2,
.offset = -2794,
@@ -528,6 +539,7 @@ static const struct ths_thermal_chip sun50i_h6_ths = {
static const struct of_device_id of_ths_match[] = {
{ .compatible = "allwinner,sun8i-h3-ths", .data = &sun8i_h3_ths },
+ { .compatible = "allwinner,sun50i-a64-ths", .data = &sun50i_a64_ths },
{ .compatible = "allwinner,sun50i-h6-ths", .data = &sun50i_h6_ths },
{ /* sentinel */ },
};
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* Re: [PATCH v5 08/18] thermal: sun8i: support mod clocks
From: Vasily Khoruzhick @ 2019-08-10 6:16 UTC (permalink / raw)
To: Yangtao Li
Cc: Mark Rutland, devicetree, Linux PM, Maxime Ripard,
Greg Kroah-Hartman, Daniel Lezcano, linux-kernel,
Eduardo Valentin, Chen-Yu Tsai, Rob Herring, Jonathan.Cameron,
Mauro Carvalho Chehab, rui.zhang, David S. Miller, arm-linux
In-Reply-To: <20190810052829.6032-9-tiny.windzz@gmail.com>
On Fri, Aug 9, 2019 at 10:31 PM Yangtao Li <tiny.windzz@gmail.com> wrote:
>
> H3 has extra clock, so introduce something in ths_thermal_chip/ths_device
> and adds the process of the clock.
>
> This is pre-work for supprt it.
>
> Signed-off-by: Yangtao Li <tiny.windzz@gmail.com>
> ---
> drivers/thermal/sun8i_thermal.c | 17 ++++++++++++++++-
> 1 file changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/thermal/sun8i_thermal.c b/drivers/thermal/sun8i_thermal.c
> index b934bc81eba7..6f4294c2aba7 100644
> --- a/drivers/thermal/sun8i_thermal.c
> +++ b/drivers/thermal/sun8i_thermal.c
> @@ -54,6 +54,7 @@ struct tsensor {
> };
>
> struct ths_thermal_chip {
> + bool has_mod_clk;
> int sensor_num;
> int offset;
> int scale;
> @@ -69,6 +70,7 @@ struct ths_device {
> struct regmap *regmap;
> struct reset_control *reset;
> struct clk *bus_clk;
> + struct clk *mod_clk;
> struct tsensor sensor[MAX_SENSOR_NUM];
> };
>
> @@ -274,6 +276,12 @@ static int sun8i_ths_resource_init(struct ths_device *tmdev)
> if (IS_ERR(tmdev->bus_clk))
> return PTR_ERR(tmdev->bus_clk);
>
> + if (tmdev->chip->has_mod_clk) {
> + tmdev->mod_clk = devm_clk_get(&pdev->dev, "mod");
> + if (IS_ERR(tmdev->mod_clk))
> + return PTR_ERR(tmdev->mod_clk);
> + }
> +
> ret = reset_control_deassert(tmdev->reset);
> if (ret)
> return ret;
> @@ -282,12 +290,18 @@ static int sun8i_ths_resource_init(struct ths_device *tmdev)
> if (ret)
> goto assert_reset;
>
> - ret = sun50i_ths_calibrate(tmdev);
> + ret = clk_prepare_enable(tmdev->mod_clk);
You have to set rate of modclk before enabling it since you can't rely
on whatever bootloader left for you.
Also I found that parameters you're using for PC_TEMP_PERIOD, ACQ0 and
ACQ1 are too aggressive and may result in high interrupt rate to the
point when it may stall RCU. I changed driver a bit to use params from
Philipp Rossak's work (modclk set to 4MHz, PC_TEMP_PERIOD is 7, ACQ0
is 255, ACQ1 is 63) and it fixed RCU stalls for me, see [1] for
details.
[1] https://github.com/anarsoul/linux-2.6/commit/46b8bb0fe2ccd1cd88fa9181a2ecbf79e8d513b2
> if (ret)
> goto bus_disable;
>
> + ret = sun50i_ths_calibrate(tmdev);
> + if (ret)
> + goto mod_disable;
> +
> return 0;
>
> +mod_disable:
> + clk_disable_unprepare(tmdev->mod_clk);
> bus_disable:
> clk_disable_unprepare(tmdev->bus_clk);
> assert_reset:
> @@ -395,6 +409,7 @@ static int sun8i_ths_remove(struct platform_device *pdev)
> {
> struct ths_device *tmdev = platform_get_drvdata(pdev);
>
> + clk_disable_unprepare(tmdev->mod_clk);
> clk_disable_unprepare(tmdev->bus_clk);
> reset_control_assert(tmdev->reset);
>
> --
> 2.17.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH v4 0/5] iommu/amd: Convert the AMD iommu driver to the dma-iommu api
From: Christoph Hellwig @ 2019-08-10 7:19 UTC (permalink / raw)
To: Tom Murphy, Joerg Roedel
Cc: Heiko Stuebner, Will Deacon, virtualization, David Brown,
Thierry Reding, linux-s390, linux-samsung-soc,
Jean-Philippe Brucker, Krzysztof Kozlowski, Jonathan Hunter,
linux-rockchip, Andy Gross, Matthias Brugger, Gerald Schaefer,
linux-arm-msm, linux-mediatek, linux-tegra, linux-arm-kernel,
Robin Murphy, linux-kernel, iommu, Kukjin Kim, David Woodhouse
In-Reply-To: <20190624061945.GA4912@infradead.org>
On Sun, Jun 23, 2019 at 11:19:45PM -0700, Christoph Hellwig wrote:
> Tom,
>
> next time please cc Jerg as the AMD IOMMU maintainer.
>
> Joerg, any chance you could review this? Toms patches to convert the
> AMD and Intel IOMMU drivers to the dma-iommu code are going to make my
> life in DMA land significantly easier, so I have a vested interest
> in this series moving forward :)
Tom, can you repost the series? Seems like there hasn't been any
news for a month.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH v4 2/2] perf machine: arm/arm64: Improve completeness for kernel address space
From: Leo Yan @ 2019-08-10 7:21 UTC (permalink / raw)
To: Arnaldo Carvalho de Melo, Alexander Shishkin, Jiri Olsa,
Namhyung Kim, Alexei Starovoitov, Daniel Borkmann,
Martin KaFai Lau, Song Liu, Yonghong Song, David Miller,
Milian Wolff, Donald Yandt, Davidlohr Bueso, Wei Li,
Adrian Hunter, Mark Drayton, Tzvetomir Stoyanov (VMware),
linux-kernel, netdev, bpf, clang-built-linux, Mathieu Poirier
Cc: Peter Zijlstra, coresight, Suzuki Poulouse, linux-arm-kernel,
Leo Yan
In-Reply-To: <20190810072135.27072-1-leo.yan@linaro.org>
Arm and arm64 architecture reserve some memory regions prior to the
symbol '_stext' and these memory regions later will be used by device
module and BPF jit. The current code misses to consider these memory
regions thus any address in the regions will be taken as user space
mode, but perf cannot find the corresponding dso with the wrong CPU
mode so we misses to generate samples for device module and BPF
related trace data.
This patch parse the link scripts to get the memory size prior to start
address and reduce this size from 'machine>->kernel_start', then can
get a fixed up kernel start address which contain memory regions for
device module and BPF. Finally, machine__get_kernel_start() can reflect
more complete kernel memory regions and perf can successfully generate
samples.
The reason for parsing the link scripts is Arm architecture changes text
offset dependent on different platforms, which define multiple text
offsets in $kernel/arch/arm/Makefile. This offset is decided when build
kernel and the final value is extended in the link script, so we can
extract the used value from the link script. We use the same way to
parse arm64 link script as well. If fail to find the link script, the
pre start memory size is assumed as zero, in this case it has no any
change caused with this patch.
Below is detailed info for testing this patch:
- Install or build LLVM/Clang;
- Configure perf with ~/.perfconfig:
root@debian:~# cat ~/.perfconfig
# this file is auto-generated.
[llvm]
clang-path = /mnt/build/llvm-build/build/install/bin/clang
kbuild-dir = /mnt/linux-kernel/linux-cs-dev/
clang-opt = "-g"
dump-obj = true
[trace]
show_zeros = yes
show_duration = no
no_inherit = yes
show_timestamp = no
show_arg_names = no
args_alignment = 40
show_prefix = yes
- Run 'perf trace' command with eBPF event:
root@debian:~# perf trace -e string \
-e $kernel/tools/perf/examples/bpf/augmented_raw_syscalls.c
- Read eBPF program memory mapping in kernel:
root@debian:~# echo 1 > /proc/sys/net/core/bpf_jit_kallsyms
root@debian:~# cat /proc/kallsyms | grep -E "bpf_prog_.+_sys_[enter|exit]"
ffff00000008a0d0 t bpf_prog_e470211b846088d5_sys_enter [bpf]
ffff00000008c6a4 t bpf_prog_29c7ae234d79bd5c_sys_exit [bpf]
- Launch any program which accesses file system frequently so can hit
the system calls trace flow with eBPF event;
- Capture CoreSight trace data with filtering eBPF program:
root@debian:~# perf record -e cs_etm/@tmc_etr0/ \
--filter 'filter 0xffff00000008a0d0/0x800' -a sleep 5s
- Decode the eBPF program symbol 'bpf_prog_f173133dc38ccf87_sys_enter':
root@debian:~# perf script -F,ip,sym
Frame deformatter: Found 4 FSYNCS
0 [unknown]
ffff00000008a1ac bpf_prog_e470211b846088d5_sys_enter
ffff00000008a250 bpf_prog_e470211b846088d5_sys_enter
0 [unknown]
ffff00000008a124 bpf_prog_e470211b846088d5_sys_enter
0 [unknown]
ffff00000008a14c bpf_prog_e470211b846088d5_sys_enter
ffff00000008a13c bpf_prog_e470211b846088d5_sys_enter
ffff00000008a14c bpf_prog_e470211b846088d5_sys_enter
0 [unknown]
ffff00000008a180 bpf_prog_e470211b846088d5_sys_enter
0 [unknown]
ffff00000008a1ac bpf_prog_e470211b846088d5_sys_enter
ffff00000008a190 bpf_prog_e470211b846088d5_sys_enter
ffff00000008a1ac bpf_prog_e470211b846088d5_sys_enter
ffff00000008a250 bpf_prog_e470211b846088d5_sys_enter
0 [unknown]
ffff00000008a124 bpf_prog_e470211b846088d5_sys_enter
0 [unknown]
ffff00000008a14c bpf_prog_e470211b846088d5_sys_enter
0 [unknown]
ffff00000008a180 bpf_prog_e470211b846088d5_sys_enter
[...]
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Suzuki Poulouse <suzuki.poulose@arm.com>
Cc: coresight@lists.linaro.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Leo Yan <leo.yan@linaro.org>
---
tools/perf/Makefile.config | 22 ++++++++++++++++++++++
tools/perf/arch/arm/util/Build | 2 ++
tools/perf/arch/arm/util/machine.c | 17 +++++++++++++++++
tools/perf/arch/arm64/util/Build | 1 +
tools/perf/arch/arm64/util/machine.c | 17 +++++++++++++++++
5 files changed, 59 insertions(+)
create mode 100644 tools/perf/arch/arm/util/machine.c
create mode 100644 tools/perf/arch/arm64/util/machine.c
diff --git a/tools/perf/Makefile.config b/tools/perf/Makefile.config
index e4988f49ea79..76e0ad0b4fd2 100644
--- a/tools/perf/Makefile.config
+++ b/tools/perf/Makefile.config
@@ -51,6 +51,17 @@ endif
ifeq ($(SRCARCH),arm)
NO_PERF_REGS := 0
LIBUNWIND_LIBS = -lunwind -lunwind-arm
+ PRE_START_SIZE := 0
+ ifneq ($(wildcard $(srctree)/arch/$(SRCARCH)/kernel/vmlinux.lds),)
+ # Extract info from lds:
+ # . = ((0xC0000000)) + 0x00208000;
+ # PRE_START_SIZE := 0x00208000
+ PRE_START_SIZE := $(shell egrep ' \. \= \({2}0x[0-9a-fA-F]+\){2}' \
+ $(srctree)/arch/$(SRCARCH)/kernel/vmlinux.lds | \
+ sed -e 's/[(|)|.|=|+|<|;|-]//g' -e 's/ \+/ /g' -e 's/^[ \t]*//' | \
+ awk -F' ' '{printf "0x%x", $$2}' 2>/dev/null)
+ endif
+ CFLAGS += -DARM_PRE_START_SIZE=$(PRE_START_SIZE)
endif
ifeq ($(SRCARCH),arm64)
@@ -58,6 +69,17 @@ ifeq ($(SRCARCH),arm64)
NO_SYSCALL_TABLE := 0
CFLAGS += -I$(OUTPUT)arch/arm64/include/generated
LIBUNWIND_LIBS = -lunwind -lunwind-aarch64
+ PRE_START_SIZE := 0
+ ifneq ($(wildcard $(srctree)/arch/$(SRCARCH)/kernel/vmlinux.lds),)
+ # Extract info from lds:
+ # . = ((((((((0xffffffffffffffff)) - (((1)) << (48)) + 1) + (0)) + (0x08000000))) + (0x08000000))) + 0x00080000;
+ # PRE_START_SIZE := (0x08000000 + 0x08000000 + 0x00080000) = 0x10080000
+ PRE_START_SIZE := $(shell egrep ' \. \= \({8}0x[0-9a-fA-F]+\){2}' \
+ $(srctree)/arch/$(SRCARCH)/kernel/vmlinux.lds | \
+ sed -e 's/[(|)|.|=|+|<|;|-]//g' -e 's/ \+/ /g' -e 's/^[ \t]*//' | \
+ awk -F' ' '{printf "0x%x", $$6+$$7+$$8}' 2>/dev/null)
+ endif
+ CFLAGS += -DARM_PRE_START_SIZE=$(PRE_START_SIZE)
endif
ifeq ($(SRCARCH),csky)
diff --git a/tools/perf/arch/arm/util/Build b/tools/perf/arch/arm/util/Build
index 296f0eac5e18..efa6b768218a 100644
--- a/tools/perf/arch/arm/util/Build
+++ b/tools/perf/arch/arm/util/Build
@@ -1,3 +1,5 @@
+perf-y += machine.o
+
perf-$(CONFIG_DWARF) += dwarf-regs.o
perf-$(CONFIG_LOCAL_LIBUNWIND) += unwind-libunwind.o
diff --git a/tools/perf/arch/arm/util/machine.c b/tools/perf/arch/arm/util/machine.c
new file mode 100644
index 000000000000..db172894e4ea
--- /dev/null
+++ b/tools/perf/arch/arm/util/machine.c
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <linux/types.h>
+#include <linux/string.h>
+#include <stdlib.h>
+
+#include "../../util/machine.h"
+
+void arch__fix_kernel_text_start(u64 *start)
+{
+ /*
+ * On arm, the 16MB virtual memory space prior to 'kernel_start' is
+ * allocated to device modules, a PMD table if CONFIG_HIGHMEM is
+ * enabled and a PGD table. To reflect the complete kernel address
+ * space, compensate the pre-defined regions for kernel start address.
+ */
+ *start = *start - ARM_PRE_START_SIZE;
+}
diff --git a/tools/perf/arch/arm64/util/Build b/tools/perf/arch/arm64/util/Build
index 3cde540d2fcf..8081fb8a7b3d 100644
--- a/tools/perf/arch/arm64/util/Build
+++ b/tools/perf/arch/arm64/util/Build
@@ -1,4 +1,5 @@
perf-y += header.o
+perf-y += machine.o
perf-y += sym-handling.o
perf-$(CONFIG_DWARF) += dwarf-regs.o
perf-$(CONFIG_LOCAL_LIBUNWIND) += unwind-libunwind.o
diff --git a/tools/perf/arch/arm64/util/machine.c b/tools/perf/arch/arm64/util/machine.c
new file mode 100644
index 000000000000..61058dca8c5a
--- /dev/null
+++ b/tools/perf/arch/arm64/util/machine.c
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0
+#include <linux/types.h>
+#include <linux/string.h>
+#include <stdlib.h>
+
+#include "../../util/machine.h"
+
+void arch__fix_kernel_text_start(u64 *start)
+{
+ /*
+ * On arm64, the root PGD table, device module memory region and
+ * BPF jit region are prior to 'kernel_start'. To reflect the
+ * complete kernel address space, compensate these pre-defined
+ * regions for kernel start address.
+ */
+ *start = *start - ARM_PRE_START_SIZE;
+}
--
2.17.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* Re: [PATCH 00/16] ARM: remove ks8695 and w90x900 platforms
From: Greg Kroah-Hartman @ 2019-08-10 7:29 UTC (permalink / raw)
To: Arnd Bergmann
Cc: linux-arm-kernel, alsa-devel, linux-kernel,
Bartlomiej Zolnierkiewicz, Miquel Raynal, netdev, Linus Walleij,
Dmitry Torokhov, linux-fbdev, Wanzongshun (Vincent), linux-spi,
linux-gpio, soc, Greg Ungerer, linux-mtd, Mark Brown,
linux-serial, linux-input, David S. Miller, Guenter Roeck
In-Reply-To: <20190809202749.742267-1-arnd@arndb.de>
On Fri, Aug 09, 2019 at 10:27:28PM +0200, Arnd Bergmann wrote:
> As discussed previously, these two ARM platforms have no
> known remaining users, let's remove them completely.
>
> Subsystem maintainers: feel free to take the driver removals
> through your respective trees, they are all independent of
> one another. We can merge any remaining patches through the
> soc tree.
Serial and USB host controller driver patches applied, thanks!
greg k-h
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH] ARM: dts: Update the NSPIRE DTS files for DRM
From: Linus Walleij @ 2019-08-10 7:42 UTC (permalink / raw)
To: arm, soc
Cc: Fabian Vogt, Daniel Tang, Linus Walleij, Sam Ravnborg,
linux-arm-kernel
The DRM subsystem graphics drivers require more granular
definition of the connection between display drivers and
panels, and a proper panel compatible. This utilizes the
bindings merged to the DRM subsystem to properly define
the display on the NSPIRE devices.
We also do away with the undocumented DT binding
"lcd-type".
We add both the clocks to the CLCD block so the driver
have full control over its clocking.
Cc: Daniel Tang <dt.tangr@gmail.com>
Cc: Fabian Vogt <fabian@ritter-vogt.de>
Tested-by: Fabian Vogt <fabian@ritter-vogt.de>
Acked-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ARM SoC folks:
Please apply this directly for v5.4 DTS changes.
I have negotiated with the NSPIRE maintainers to do
this change.
This is a split from the v3 patch
"ARM: nspire: Move CLCD set-up to device tree"
so you can apply DTS changes separately.
---
arch/arm/boot/dts/nspire-classic.dtsi | 15 ++++++++++++++-
arch/arm/boot/dts/nspire-cx.dts | 15 ++++++++++++++-
arch/arm/boot/dts/nspire.dtsi | 10 ++++++++--
3 files changed, 36 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/nspire-classic.dtsi b/arch/arm/boot/dts/nspire-classic.dtsi
index c53f42777851..41744cc2bc72 100644
--- a/arch/arm/boot/dts/nspire-classic.dtsi
+++ b/arch/arm/boot/dts/nspire-classic.dtsi
@@ -8,7 +8,11 @@
/include/ "nspire.dtsi"
&lcd {
- lcd-type = "classic";
+ port {
+ clcd_pads: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
};
&fast_timer {
@@ -69,6 +73,15 @@
#interrupt-cells = <1>;
};
};
+
+ panel {
+ compatible = "ti,nspire-classic-lcd-panel";
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&clcd_pads>;
+ };
+ };
+ };
chosen {
bootargs = "debug earlyprintk console=tty0 console=ttyS0,115200n8 root=/dev/ram0";
};
diff --git a/arch/arm/boot/dts/nspire-cx.dts b/arch/arm/boot/dts/nspire-cx.dts
index da95c3736651..0c16b04e2744 100644
--- a/arch/arm/boot/dts/nspire-cx.dts
+++ b/arch/arm/boot/dts/nspire-cx.dts
@@ -9,7 +9,11 @@
/include/ "nspire.dtsi"
&lcd {
- lcd-type = "cx";
+ port {
+ clcd_pads: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
};
&fast_timer {
@@ -106,6 +110,15 @@
};
};
};
+
+ panel {
+ compatible = "ti,nspire-cx-lcd-panel";
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&clcd_pads>;
+ };
+ };
+ };
chosen {
bootargs = "debug earlyprintk console=tty0 console=ttyAMA0,115200n8 root=/dev/ram0";
};
diff --git a/arch/arm/boot/dts/nspire.dtsi b/arch/arm/boot/dts/nspire.dtsi
index c35fd6667716..d9a0fd7524dc 100644
--- a/arch/arm/boot/dts/nspire.dtsi
+++ b/arch/arm/boot/dts/nspire.dtsi
@@ -95,8 +95,14 @@
reg = <0xC0000000 0x1000>;
interrupts = <21>;
- clocks = <&apb_pclk>;
- clock-names = "apb_pclk";
+ /*
+ * We assume the same clock is fed to APB and CLCDCLK.
+ * There is some code to scale the clock down by a factor
+ * 48 for the display so likely the frequency to the
+ * display is 1MHz and the CLCDCLK is 48 MHz.
+ */
+ clocks = <&apb_pclk>, <&apb_pclk>;
+ clock-names = "clcdclk", "apb_pclk";
};
adc: adc@C4000000 {
--
2.21.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH] ARM: mach-nspire: Kill off CLCD auxdata
From: Linus Walleij @ 2019-08-10 7:50 UTC (permalink / raw)
To: arm, soc
Cc: Fabian Vogt, Daniel Tang, Linus Walleij, Sam Ravnborg,
linux-arm-kernel
After transitioning the CLCD to use DRM we can now kill off
the final piece of auxdata on the NSPIRE.
Cc: Daniel Tang <dt.tangr@gmail.com>
Cc: Fabian Vogt <fabian@ritter-vogt.de>
Tested-by: Fabian Vogt <fabian@ritter-vogt.de>
Acked-by: Sam Ravnborg <sam@ravnborg.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ARM SoC folks:
Please apply this directly for v5.4 wherever NSPIRE changes
go.
I have negotiated with the NSPIRE maintainers to do
this change.
This is a split from the v3 patch
"ARM: nspire: Move CLCD set-up to device tree"
so you can apply machine changes separately.
---
arch/arm/mach-nspire/Makefile | 1 -
arch/arm/mach-nspire/clcd.c | 114 ----------------------------------
arch/arm/mach-nspire/clcd.h | 10 ---
arch/arm/mach-nspire/nspire.c | 25 --------
4 files changed, 150 deletions(-)
delete mode 100644 arch/arm/mach-nspire/clcd.c
delete mode 100644 arch/arm/mach-nspire/clcd.h
diff --git a/arch/arm/mach-nspire/Makefile b/arch/arm/mach-nspire/Makefile
index 1d568c600452..4716b9b9aa7b 100644
--- a/arch/arm/mach-nspire/Makefile
+++ b/arch/arm/mach-nspire/Makefile
@@ -1,3 +1,2 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-y += nspire.o
-obj-y += clcd.o
diff --git a/arch/arm/mach-nspire/clcd.c b/arch/arm/mach-nspire/clcd.c
deleted file mode 100644
index 44738dcb391d..000000000000
--- a/arch/arm/mach-nspire/clcd.c
+++ /dev/null
@@ -1,114 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * linux/arch/arm/mach-nspire/clcd.c
- *
- * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
- */
-
-#include <linux/init.h>
-#include <linux/of.h>
-#include <linux/amba/bus.h>
-#include <linux/amba/clcd.h>
-#include <linux/dma-mapping.h>
-
-static struct clcd_panel nspire_cx_lcd_panel = {
- .mode = {
- .name = "Color LCD",
- .refresh = 60,
- .xres = 320,
- .yres = 240,
- .sync = 0,
- .vmode = FB_VMODE_NONINTERLACED,
- .pixclock = 1,
- .hsync_len = 6,
- .vsync_len = 1,
- .right_margin = 50,
- .left_margin = 38,
- .lower_margin = 3,
- .upper_margin = 17,
- },
- .width = 65, /* ~6.50 cm */
- .height = 49, /* ~4.87 cm */
- .tim2 = TIM2_IPC,
- .cntl = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
- .bpp = 16,
- .caps = CLCD_CAP_565,
-};
-
-static struct clcd_panel nspire_classic_lcd_panel = {
- .mode = {
- .name = "Grayscale LCD",
- .refresh = 60,
- .xres = 320,
- .yres = 240,
- .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
- .vmode = FB_VMODE_NONINTERLACED,
- .pixclock = 1,
- .hsync_len = 6,
- .vsync_len = 1,
- .right_margin = 6,
- .left_margin = 6,
- },
- .width = 71, /* 7.11cm */
- .height = 53, /* 5.33cm */
- .tim2 = 0x80007d0,
- .cntl = CNTL_LCDMONO8,
- .bpp = 8,
- .grayscale = 1,
- .caps = CLCD_CAP_5551,
-};
-
-int nspire_clcd_setup(struct clcd_fb *fb)
-{
- struct clcd_panel *panel;
- size_t panel_size;
- const char *type;
- dma_addr_t dma;
- int err;
-
- BUG_ON(!fb->dev->dev.of_node);
-
- err = of_property_read_string(fb->dev->dev.of_node, "lcd-type", &type);
- if (err) {
- pr_err("CLCD: Could not find lcd-type property\n");
- return err;
- }
-
- if (!strcmp(type, "cx")) {
- panel = &nspire_cx_lcd_panel;
- } else if (!strcmp(type, "classic")) {
- panel = &nspire_classic_lcd_panel;
- } else {
- pr_err("CLCD: Unknown lcd-type %s\n", type);
- return -EINVAL;
- }
-
- panel_size = ((panel->mode.xres * panel->mode.yres) * panel->bpp) / 8;
- panel_size = ALIGN(panel_size, PAGE_SIZE);
-
- fb->fb.screen_base = dma_alloc_wc(&fb->dev->dev, panel_size, &dma,
- GFP_KERNEL);
-
- if (!fb->fb.screen_base) {
- pr_err("CLCD: unable to map framebuffer\n");
- return -ENOMEM;
- }
-
- fb->fb.fix.smem_start = dma;
- fb->fb.fix.smem_len = panel_size;
- fb->panel = panel;
-
- return 0;
-}
-
-int nspire_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
-{
- return dma_mmap_wc(&fb->dev->dev, vma, fb->fb.screen_base,
- fb->fb.fix.smem_start, fb->fb.fix.smem_len);
-}
-
-void nspire_clcd_remove(struct clcd_fb *fb)
-{
- dma_free_wc(&fb->dev->dev, fb->fb.fix.smem_len, fb->fb.screen_base,
- fb->fb.fix.smem_start);
-}
diff --git a/arch/arm/mach-nspire/clcd.h b/arch/arm/mach-nspire/clcd.h
deleted file mode 100644
index 7f36bd8511c5..000000000000
--- a/arch/arm/mach-nspire/clcd.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * linux/arch/arm/mach-nspire/clcd.h
- *
- * Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
- */
-
-int nspire_clcd_setup(struct clcd_fb *fb);
-int nspire_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma);
-void nspire_clcd_remove(struct clcd_fb *fb);
diff --git a/arch/arm/mach-nspire/nspire.c b/arch/arm/mach-nspire/nspire.c
index 957bd0c0fbd5..2d4abb0288b9 100644
--- a/arch/arm/mach-nspire/nspire.c
+++ b/arch/arm/mach-nspire/nspire.c
@@ -12,14 +12,12 @@
#include <linux/irqchip/arm-vic.h>
#include <linux/clkdev.h>
#include <linux/amba/bus.h>
-#include <linux/amba/clcd.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <asm/mach/map.h>
#include "mmio.h"
-#include "clcd.h"
static const char *const nspire_dt_match[] __initconst = {
"ti,nspire",
@@ -29,28 +27,6 @@ static const char *const nspire_dt_match[] __initconst = {
NULL,
};
-static struct clcd_board nspire_clcd_data = {
- .name = "LCD",
- .caps = CLCD_CAP_5551 | CLCD_CAP_565,
- .check = clcdfb_check,
- .decode = clcdfb_decode,
- .setup = nspire_clcd_setup,
- .mmap = nspire_clcd_mmap,
- .remove = nspire_clcd_remove,
-};
-
-
-static struct of_dev_auxdata nspire_auxdata[] __initdata = {
- OF_DEV_AUXDATA("arm,pl111", NSPIRE_LCD_PHYS_BASE,
- NULL, &nspire_clcd_data),
- { }
-};
-
-static void __init nspire_init(void)
-{
- of_platform_default_populate(NULL, nspire_auxdata, NULL);
-}
-
static void nspire_restart(enum reboot_mode mode, const char *cmd)
{
void __iomem *base = ioremap(NSPIRE_MISC_PHYS_BASE, SZ_4K);
@@ -62,6 +38,5 @@ static void nspire_restart(enum reboot_mode mode, const char *cmd)
DT_MACHINE_START(NSPIRE, "TI-NSPIRE")
.dt_compat = nspire_dt_match,
- .init_machine = nspire_init,
.restart = nspire_restart,
MACHINE_END
--
2.21.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v9 00/21] MT8183 IOMMU SUPPORT
From: Yong Wu @ 2019-08-10 7:58 UTC (permalink / raw)
To: Joerg Roedel, Matthias Brugger, Robin Murphy, Will Deacon
Cc: youlin.pei, devicetree, Nicolas Boichat, cui.zhang,
srv_heupstream, chao.hao, linux-kernel, Evan Green, Tomasz Figa,
iommu, Rob Herring, linux-mediatek, yong.wu, ming-fan.chen,
anan.sun, Matthias Kaehlcke, linux-arm-kernel
This patchset mainly adds support for mt8183 IOMMU and SMI.
mt8183 has only one M4U like mt8173 and is also MTK IOMMU gen2 which
uses ARM Short-Descriptor translation table format.
The mt8183 M4U-SMI HW diagram is as below:
EMI
|
M4U
|
----------
| |
gals0-rx gals1-rx
| |
| |
gals0-tx gals1-tx
| |
------------
SMI Common
------------
|
+-----+-----+--------+-----+-----+-------+-------+
| | | | | | | |
| | gals-rx gals-rx | gals-rx gals-rx gals-rx
| | | | | | | |
| | | | | | | |
| | gals-tx gals-tx | gals-tx gals-tx gals-tx
| | | | | | | |
larb0 larb1 IPU0 IPU1 larb4 larb5 larb6 CCU
disp vdec img cam venc img cam
All the connections are HW fixed, SW can NOT adjust it.
Compared with mt8173, we add a GALS(Global Async Local Sync) module
between SMI-common and M4U, and additional GALS between larb2/3/5/6
and SMI-common. GALS can help synchronize for the modules in different
clock frequency, it can be seen as a "asynchronous fifo".
GALS can only help transfer the command/data while it doesn't have
the configuring register, thus it has the special "smi" clock and it
doesn't have the "apb" clock. From the diagram above, we add "gals0"
and "gals1" clocks for smi-common and add a "gals" clock for smi-larb.
From the diagram above, IPU0/IPU1(Image Processor Unit) and CCU(Camera
Control Unit) is connected with smi-common directly, we can take them
as "larb2", "larb3" and "larb7", and their register spaces are
different with the normal larb.
The dtsi was sent at: [1] https://lore.kernel.org/patchwork/patch/1054099/
Change notes:
v9:
1) rebase on v5.3-rc1.
2) In v7s, Use oas to implement MTK 4GB mode. It nearly reconstruct the
patch, so I don't keep the R-b.
v8: https://lists.linuxfoundation.org/pipermail/iommu/2019-June/037095.html
1) From the 4GB mode:
a. Move the patch sequency(Move "iommu/mediatek: Fix iova_to_phys PA
start for 4GB mode" before "iommu/io-pgtable-arm-v7s: Extend MediaTek
4G Mode").
b. Remove the patch "Rename enable_4GB to dram_is_4gb" and Use Evan's
suggestion.
2) add a "union" for smi gen1/gen2 base.
3) Clean up the structure "struct mtk_smi_iommu" since it have only one item,
suggested from Matthias.
v7: https://lists.linuxfoundation.org/pipermail/iommu/2019-June/036552.html
1) rebase on v5.2-rc1.
2) Add fixed tags in patch 20.
3) Remove shutdown patch. I will send it independently if necessary.
v6: https://lists.linuxfoundation.org/pipermail/iommu/2019-February/033685.html
1) rebase on v5.0-rc1.
2) About the register name (VLD_PA_RNG), Keep consistent in the patches.
3) In the 4GB mode, Always add MTK_4GB_quirk.
4) Reword some commit message helped from Evan. like common->smi_ao_base is
completely different from common->base; STANDARD_AXI_MODE reg is completely
different from CTRL_MISC; commit in the shutdown patch.
5) Add 2 new patches again:
iommu/mediatek: Rename enable_4GB to dram_is_4gb
iommu/mediatek: Fix iova_to_phys PA start for 4GB mode
v5: https://lists.linuxfoundation.org/pipermail/iommu/2019-January/032387.html
1) Remove this patch "iommu/mediatek: Constify iommu_ops" from here as it
was applied for v5.0.
2) Again, add 3 preparing patches. Move two property into the plat_data.
iommu/mediatek: Move vld_pa_rng into plat_data
iommu/mediatek: Move reset_axi into plat_data
iommu/mediatek: Refine protect memory definition
3) Add shutdown callback for mtk_iommu_v1 in patch[19/20].
v4: http://lists.infradead.org/pipermail/linux-mediatek/2018-December/016205.html
1) Add 3 preparing patches. Seperate some minor meaningful code into
a new patch according to Matthias's suggestion.
memory: mtk-smi: Add gals support
iommu/mediatek: Add larb-id remapped support
iommu/mediatek: Add bclk can be supported optionally
2) rebase on "iommu/mediatek: Make it explicitly non-modular"
which was applied.
https://lore.kernel.org/patchwork/patch/1020125/
3) add some comment about "mediatek,larb-id" in the commit message of
the patch "mtk-smi: Get rid of need_larbid".
4) Fix bus_sel value.
v3: https://lists.linuxfoundation.org/pipermail/iommu/2018-November/031121.html
1) rebase on v4.20-rc1.
2) In the dt-binding, add a minor string "mt7623" which also use gen1
since Matthias added it in v4.20.
3) About v7s:
a) for paddr_to_pte, change the param from "arm_v7s_io_pgtable" to
"arm_pgtable_cfg", according to Robin suggestion.
b) Don't use CONFIG_PHYS_ADDR_T_64BIT.
c) add a little comment(pgtable address still don't over 4GB) in the
commit message of the patch "Extend MediaTek 4GB Mode".
4) add "iommu/mediatek: Constify iommu_ops" into this patchset. this may
be helpful for review and merge.
https://lists.linuxfoundation.org/pipermail/iommu/2018-October/030637.html
v2: https://lists.linuxfoundation.org/pipermail/iommu/2018-September/030164.html
1) Fix typo in the commit message of dt-binding.
2) Change larb2/larb3 to the special larbs.
3) Refactor the larb-id remapped array(larbid_remapped), then we
don't need add the new function(mtk_iommu_get_larbid).
4) Add a new patch for v7s two helpers(paddr_to_iopte and
iopte_to_paddr).
5) Change some comment for MTK 4GB mode.
v1: base on v4.19-rc1.
http://lists.infradead.org/pipermail/linux-mediatek/2018-September/014881.html
Yong Wu (21):
dt-bindings: mediatek: Add binding for mt8183 IOMMU and SMI
iommu/mediatek: Use a struct as the platform data
memory: mtk-smi: Use a general config_port interface
memory: mtk-smi: Use a struct for the platform data for smi-common
iommu/io-pgtable-arm-v7s: Add paddr_to_iopte and iopte_to_paddr
helpers
iommu/io-pgtable-arm-v7s: Use ias/oas to check the valid iova/pa
iommu/io-pgtable-arm-v7s: Rename 4GB quirk to QUIRK_MTK_EXT
iommu/io-pgtable-arm-v7s: Extend MediaTek 4GB Mode
iommu/mediatek: Add bclk can be supported optionally
iommu/mediatek: Add larb-id remapped support
iommu/mediatek: Refine protect memory definition
iommu/mediatek: Move reset_axi into plat_data
iommu/mediatek: Move vld_pa_rng into plat_data
memory: mtk-smi: Add gals support
iommu/mediatek: Add mt8183 IOMMU support
iommu/mediatek: Add mmu1 support
memory: mtk-smi: Invoke pm runtime_callback to enable clocks
memory: mtk-smi: Add bus_sel for mt8183
iommu/mediatek: Fix VLD_PA_RNG register backup when suspend
memory: mtk-smi: Get rid of need_larbid
iommu/mediatek: Clean up struct mtk_smi_iommu
.../devicetree/bindings/iommu/mediatek,iommu.txt | 30 ++-
.../memory-controllers/mediatek,smi-common.txt | 12 +-
.../memory-controllers/mediatek,smi-larb.txt | 4 +
drivers/iommu/io-pgtable-arm-v7s.c | 84 +++++--
drivers/iommu/mtk_iommu.c | 143 +++++++----
drivers/iommu/mtk_iommu.h | 21 +-
drivers/iommu/mtk_iommu_v1.c | 6 +-
drivers/memory/mtk-smi.c | 268 ++++++++++++++-------
include/dt-bindings/memory/mt8183-larb-port.h | 130 ++++++++++
include/linux/io-pgtable.h | 11 +-
include/soc/mediatek/smi.h | 5 -
11 files changed, 533 insertions(+), 181 deletions(-)
create mode 100644 include/dt-bindings/memory/mt8183-larb-port.h
--
1.9.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH v9 02/21] iommu/mediatek: Use a struct as the platform data
From: Yong Wu @ 2019-08-10 7:58 UTC (permalink / raw)
To: Joerg Roedel, Matthias Brugger, Robin Murphy, Will Deacon
Cc: youlin.pei, devicetree, Nicolas Boichat, cui.zhang,
srv_heupstream, chao.hao, linux-kernel, Evan Green, Tomasz Figa,
iommu, Rob Herring, linux-mediatek, yong.wu, ming-fan.chen,
anan.sun, Matthias Kaehlcke, linux-arm-kernel
In-Reply-To: <1565423901-17008-1-git-send-email-yong.wu@mediatek.com>
Use a struct as the platform special data instead of the enumeration.
This is a prepare patch for adding mt8183 iommu support.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Reviewed-by: Evan Green <evgreen@chromium.org>
---
drivers/iommu/mtk_iommu.c | 24 ++++++++++++++++--------
drivers/iommu/mtk_iommu.h | 6 +++++-
2 files changed, 21 insertions(+), 9 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 82e4be4..c6e6dc3 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -46,7 +46,7 @@
#define REG_MMU_CTRL_REG 0x110
#define F_MMU_PREFETCH_RT_REPLACE_MOD BIT(4)
#define F_MMU_TF_PROTECT_SEL_SHIFT(data) \
- ((data)->m4u_plat == M4U_MT2712 ? 4 : 5)
+ ((data)->plat_data->m4u_plat == M4U_MT2712 ? 4 : 5)
/* It's named by F_MMU_TF_PROT_SEL in mt2712. */
#define F_MMU_TF_PROTECT_SEL(prot, data) \
(((prot) & 0x3) << F_MMU_TF_PROTECT_SEL_SHIFT(data))
@@ -512,7 +512,7 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
}
regval = F_MMU_TF_PROTECT_SEL(2, data);
- if (data->m4u_plat == M4U_MT8173)
+ if (data->plat_data->m4u_plat == M4U_MT8173)
regval |= F_MMU_PREFETCH_RT_REPLACE_MOD;
writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);
@@ -533,14 +533,14 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
F_INT_PRETETCH_TRANSATION_FIFO_FAULT;
writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL);
- if (data->m4u_plat == M4U_MT8173)
+ if (data->plat_data->m4u_plat == M4U_MT8173)
regval = (data->protect_base >> 1) | (data->enable_4GB << 31);
else
regval = lower_32_bits(data->protect_base) |
upper_32_bits(data->protect_base);
writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR);
- if (data->enable_4GB && data->m4u_plat != M4U_MT8173) {
+ if (data->enable_4GB && data->plat_data->m4u_plat != M4U_MT8173) {
/*
* If 4GB mode is enabled, the validate PA range is from
* 0x1_0000_0000 to 0x1_ffff_ffff. here record bit[32:30].
@@ -551,7 +551,7 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
writel_relaxed(0, data->base + REG_MMU_DCM_DIS);
/* It's MISC control register whose default value is ok except mt8173.*/
- if (data->m4u_plat == M4U_MT8173)
+ if (data->plat_data->m4u_plat == M4U_MT8173)
writel_relaxed(0, data->base + REG_MMU_STANDARD_AXI_MODE);
if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0,
@@ -584,7 +584,7 @@ static int mtk_iommu_probe(struct platform_device *pdev)
if (!data)
return -ENOMEM;
data->dev = dev;
- data->m4u_plat = (enum mtk_iommu_plat)of_device_get_match_data(dev);
+ data->plat_data = of_device_get_match_data(dev);
/* Protect memory. HW will access here while translation fault.*/
protect = devm_kzalloc(dev, MTK_PROTECT_PA_ALIGN * 2, GFP_KERNEL);
@@ -732,9 +732,17 @@ static int __maybe_unused mtk_iommu_resume(struct device *dev)
SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_iommu_suspend, mtk_iommu_resume)
};
+static const struct mtk_iommu_plat_data mt2712_data = {
+ .m4u_plat = M4U_MT2712,
+};
+
+static const struct mtk_iommu_plat_data mt8173_data = {
+ .m4u_plat = M4U_MT8173,
+};
+
static const struct of_device_id mtk_iommu_of_ids[] = {
- { .compatible = "mediatek,mt2712-m4u", .data = (void *)M4U_MT2712},
- { .compatible = "mediatek,mt8173-m4u", .data = (void *)M4U_MT8173},
+ { .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data},
+ { .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data},
{}
};
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index 59337323..9725b08 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -32,6 +32,10 @@ enum mtk_iommu_plat {
M4U_MT8173,
};
+struct mtk_iommu_plat_data {
+ enum mtk_iommu_plat m4u_plat;
+};
+
struct mtk_iommu_domain;
struct mtk_iommu_data {
@@ -48,7 +52,7 @@ struct mtk_iommu_data {
bool tlb_flush_active;
struct iommu_device iommu;
- enum mtk_iommu_plat m4u_plat;
+ const struct mtk_iommu_plat_data *plat_data;
struct list_head list;
};
--
1.9.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v9 01/21] dt-bindings: mediatek: Add binding for mt8183 IOMMU and SMI
From: Yong Wu @ 2019-08-10 7:58 UTC (permalink / raw)
To: Joerg Roedel, Matthias Brugger, Robin Murphy, Will Deacon
Cc: youlin.pei, devicetree, Nicolas Boichat, cui.zhang,
srv_heupstream, chao.hao, linux-kernel, Evan Green, Tomasz Figa,
iommu, Rob Herring, linux-mediatek, yong.wu, ming-fan.chen,
anan.sun, Matthias Kaehlcke, linux-arm-kernel
In-Reply-To: <1565423901-17008-1-git-send-email-yong.wu@mediatek.com>
This patch adds decriptions for mt8183 IOMMU and SMI.
mt8183 has only one M4U like mt8173 and is also MTK IOMMU gen2 which
uses ARM Short-Descriptor translation table format.
The mt8183 M4U-SMI HW diagram is as below:
EMI
|
M4U
|
----------
| |
gals0-rx gals1-rx
| |
| |
gals0-tx gals1-tx
| |
------------
SMI Common
------------
|
+-----+-----+--------+-----+-----+-------+-------+
| | | | | | | |
| | gals-rx gals-rx | gals-rx gals-rx gals-rx
| | | | | | | |
| | | | | | | |
| | gals-tx gals-tx | gals-tx gals-tx gals-tx
| | | | | | | |
larb0 larb1 IPU0 IPU1 larb4 larb5 larb6 CCU
disp vdec img cam venc img cam
All the connections are HW fixed, SW can NOT adjust it.
Compared with mt8173, we add a GALS(Global Async Local Sync) module
between SMI-common and M4U, and additional GALS between larb2/3/5/6
and SMI-common. GALS can help synchronize for the modules in different
clock frequency, it can be seen as a "asynchronous fifo".
GALS can only help transfer the command/data while it doesn't have
the configuring register, thus it has the special "smi" clock and it
doesn't have the "apb" clock. From the diagram above, we add "gals0"
and "gals1" clocks for smi-common and add a "gals" clock for smi-larb.
From the diagram above, IPU0/IPU1(Image Processor Unit) and CCU(Camera
Control Unit) is connected with smi-common directly, we can take them
as "larb2", "larb3" and "larb7", and their register spaces are
different with the normal larb.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Evan Green <evgreen@chromium.org>
---
.../devicetree/bindings/iommu/mediatek,iommu.txt | 30 ++++-
.../memory-controllers/mediatek,smi-common.txt | 12 +-
.../memory-controllers/mediatek,smi-larb.txt | 4 +
include/dt-bindings/memory/mt8183-larb-port.h | 130 +++++++++++++++++++++
4 files changed, 170 insertions(+), 6 deletions(-)
create mode 100644 include/dt-bindings/memory/mt8183-larb-port.h
diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
index 6922db5..ce59a50 100644
--- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
+++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
@@ -11,10 +11,23 @@ ARM Short-Descriptor translation table format for address translation.
|
m4u (Multimedia Memory Management Unit)
|
+ +--------+
+ | |
+ gals0-rx gals1-rx (Global Async Local Sync rx)
+ | |
+ | |
+ gals0-tx gals1-tx (Global Async Local Sync tx)
+ | | Some SoCs may have GALS.
+ +--------+
+ |
SMI Common(Smart Multimedia Interface Common)
|
+----------------+-------
| |
+ | gals-rx There may be GALS in some larbs.
+ | |
+ | |
+ | gals-tx
| |
SMI larb0 SMI larb1 ... SoCs have several SMI local arbiter(larb).
(display) (vdec)
@@ -36,6 +49,10 @@ each local arbiter.
like display, video decode, and camera. And there are different ports
in each larb. Take a example, There are many ports like MC, PP, VLD in the
video decode local arbiter, all these ports are according to the video HW.
+ In some SoCs, there may be a GALS(Global Async Local Sync) module between
+smi-common and m4u, and additional GALS module between smi-larb and
+smi-common. GALS can been seen as a "asynchronous fifo" which could help
+synchronize for the modules in different clock frequency.
Required properties:
- compatible : must be one of the following string:
@@ -44,18 +61,25 @@ Required properties:
"mediatek,mt7623-m4u", "mediatek,mt2701-m4u" for mt7623 which uses
generation one m4u HW.
"mediatek,mt8173-m4u" for mt8173 which uses generation two m4u HW.
+ "mediatek,mt8183-m4u" for mt8183 which uses generation two m4u HW.
- reg : m4u register base and size.
- interrupts : the interrupt of m4u.
- clocks : must contain one entry for each clock-names.
-- clock-names : must be "bclk", It is the block clock of m4u.
+- clock-names : Only 1 optional clock:
+ - "bclk": the block clock of m4u.
+ Here is the list which require this "bclk":
+ - mt2701, mt2712, mt7623 and mt8173.
+ Note that m4u use the EMI clock which always has been enabled before kernel
+ if there is no this "bclk".
- mediatek,larbs : List of phandle to the local arbiters in the current Socs.
Refer to bindings/memory-controllers/mediatek,smi-larb.txt. It must sort
according to the local arbiter index, like larb0, larb1, larb2...
- iommu-cells : must be 1. This is the mtk_m4u_id according to the HW.
Specifies the mtk_m4u_id as defined in
dt-binding/memory/mt2701-larb-port.h for mt2701, mt7623
- dt-binding/memory/mt2712-larb-port.h for mt2712, and
- dt-binding/memory/mt8173-larb-port.h for mt8173.
+ dt-binding/memory/mt2712-larb-port.h for mt2712,
+ dt-binding/memory/mt8173-larb-port.h for mt8173, and
+ dt-binding/memory/mt8183-larb-port.h for mt8183.
Example:
iommu: iommu@10205000 {
diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
index e937ddd..b478ade 100644
--- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.txt
@@ -2,9 +2,10 @@ SMI (Smart Multimedia Interface) Common
The hardware block diagram please check bindings/iommu/mediatek,iommu.txt
-Mediatek SMI have two generations of HW architecture, mt2712 and mt8173 use
-the second generation of SMI HW while mt2701 uses the first generation HW of
-SMI.
+Mediatek SMI have two generations of HW architecture, here is the list
+which generation the SoCs use:
+generation 1: mt2701 and mt7623.
+generation 2: mt2712, mt8173 and mt8183.
There's slight differences between the two SMI, for generation 2, the
register which control the iommu port is at each larb's register base. But
@@ -19,6 +20,7 @@ Required properties:
"mediatek,mt2712-smi-common"
"mediatek,mt7623-smi-common", "mediatek,mt2701-smi-common"
"mediatek,mt8173-smi-common"
+ "mediatek,mt8183-smi-common"
- reg : the register and size of the SMI block.
- power-domains : a phandle to the power domain of this local arbiter.
- clocks : Must contain an entry for each entry in clock-names.
@@ -30,6 +32,10 @@ Required properties:
They may be the same if both source clocks are the same.
- "async" : asynchronous clock, it help transform the smi clock into the emi
clock domain, this clock is only needed by generation 1 smi HW.
+ and these 2 option clocks for generation 2 smi HW:
+ - "gals0": the path0 clock of GALS(Global Async Local Sync).
+ - "gals1": the path1 clock of GALS(Global Async Local Sync).
+ Here is the list which has this GALS: mt8183.
Example:
smi_common: smi@14022000 {
diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
index 94eddca..4b369b3 100644
--- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt
@@ -8,6 +8,7 @@ Required properties:
"mediatek,mt2712-smi-larb"
"mediatek,mt7623-smi-larb", "mediatek,mt2701-smi-larb"
"mediatek,mt8173-smi-larb"
+ "mediatek,mt8183-smi-larb"
- reg : the register and size of this local arbiter.
- mediatek,smi : a phandle to the smi_common node.
- power-domains : a phandle to the power domain of this local arbiter.
@@ -16,6 +17,9 @@ Required properties:
- "apb" : Advanced Peripheral Bus clock, It's the clock for setting
the register.
- "smi" : It's the clock for transfer data and command.
+ and this optional clock name:
+ - "gals": the clock for GALS(Global Async Local Sync).
+ Here is the list which has this GALS: mt8183.
Required property for mt2701, mt2712 and mt7623:
- mediatek,larb-id :the hardware id of this larb.
diff --git a/include/dt-bindings/memory/mt8183-larb-port.h b/include/dt-bindings/memory/mt8183-larb-port.h
new file mode 100644
index 0000000..2c579f3
--- /dev/null
+++ b/include/dt-bindings/memory/mt8183-larb-port.h
@@ -0,0 +1,130 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018 MediaTek Inc.
+ * Author: Yong Wu <yong.wu@mediatek.com>
+ */
+#ifndef __DTS_IOMMU_PORT_MT8183_H
+#define __DTS_IOMMU_PORT_MT8183_H
+
+#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port))
+
+#define M4U_LARB0_ID 0
+#define M4U_LARB1_ID 1
+#define M4U_LARB2_ID 2
+#define M4U_LARB3_ID 3
+#define M4U_LARB4_ID 4
+#define M4U_LARB5_ID 5
+#define M4U_LARB6_ID 6
+#define M4U_LARB7_ID 7
+
+/* larb0 */
+#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0)
+#define M4U_PORT_DISP_2L_OVL0_LARB0 MTK_M4U_ID(M4U_LARB0_ID, 1)
+#define M4U_PORT_DISP_2L_OVL1_LARB0 MTK_M4U_ID(M4U_LARB0_ID, 2)
+#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 3)
+#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 4)
+#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5)
+#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 6)
+#define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB0_ID, 7)
+#define M4U_PORT_MDP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 8)
+#define M4U_PORT_DISP_FAKE0 MTK_M4U_ID(M4U_LARB0_ID, 9)
+
+/* larb1 */
+#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB1_ID, 0)
+#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB1_ID, 1)
+#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB1_ID, 2)
+#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB1_ID, 3)
+#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB1_ID, 4)
+#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB1_ID, 5)
+#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB1_ID, 6)
+
+/* larb2 VPU0 */
+#define M4U_PORT_IMG_IPUO MTK_M4U_ID(M4U_LARB2_ID, 0)
+#define M4U_PORT_IMG_IPU3O MTK_M4U_ID(M4U_LARB2_ID, 1)
+#define M4U_PORT_IMG_IPUI MTK_M4U_ID(M4U_LARB2_ID, 2)
+
+/* larb3 VPU1 */
+#define M4U_PORT_CAM_IPUO MTK_M4U_ID(M4U_LARB3_ID, 0)
+#define M4U_PORT_CAM_IPU2O MTK_M4U_ID(M4U_LARB3_ID, 1)
+#define M4U_PORT_CAM_IPU3O MTK_M4U_ID(M4U_LARB3_ID, 2)
+#define M4U_PORT_CAM_IPUI MTK_M4U_ID(M4U_LARB3_ID, 3)
+#define M4U_PORT_CAM_IPU2I MTK_M4U_ID(M4U_LARB3_ID, 4)
+
+/* larb4 */
+#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB4_ID, 0)
+#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB4_ID, 1)
+#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB4_ID, 2)
+#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB4_ID, 3)
+#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB4_ID, 4)
+#define M4U_PORT_JPGENC_RDMA MTK_M4U_ID(M4U_LARB4_ID, 5)
+#define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB4_ID, 6)
+#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB4_ID, 7)
+#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB4_ID, 8)
+#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB4_ID, 9)
+#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB4_ID, 10)
+
+/* larb5 */
+#define M4U_PORT_CAM_IMGI MTK_M4U_ID(M4U_LARB5_ID, 0)
+#define M4U_PORT_CAM_IMG2O MTK_M4U_ID(M4U_LARB5_ID, 1)
+#define M4U_PORT_CAM_IMG3O MTK_M4U_ID(M4U_LARB5_ID, 2)
+#define M4U_PORT_CAM_VIPI MTK_M4U_ID(M4U_LARB5_ID, 3)
+#define M4U_PORT_CAM_LCEI MTK_M4U_ID(M4U_LARB5_ID, 4)
+#define M4U_PORT_CAM_SMXI MTK_M4U_ID(M4U_LARB5_ID, 5)
+#define M4U_PORT_CAM_SMXO MTK_M4U_ID(M4U_LARB5_ID, 6)
+#define M4U_PORT_CAM_WPE0_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 7)
+#define M4U_PORT_CAM_WPE0_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 8)
+#define M4U_PORT_CAM_WPE0_WDMA MTK_M4U_ID(M4U_LARB5_ID, 9)
+#define M4U_PORT_CAM_FDVT_RP MTK_M4U_ID(M4U_LARB5_ID, 10)
+#define M4U_PORT_CAM_FDVT_WR MTK_M4U_ID(M4U_LARB5_ID, 11)
+#define M4U_PORT_CAM_FDVT_RB MTK_M4U_ID(M4U_LARB5_ID, 12)
+#define M4U_PORT_CAM_WPE1_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 13)
+#define M4U_PORT_CAM_WPE1_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 14)
+#define M4U_PORT_CAM_WPE1_WDMA MTK_M4U_ID(M4U_LARB5_ID, 15)
+#define M4U_PORT_CAM_DPE_RDMA MTK_M4U_ID(M4U_LARB5_ID, 16)
+#define M4U_PORT_CAM_DPE_WDMA MTK_M4U_ID(M4U_LARB5_ID, 17)
+#define M4U_PORT_CAM_MFB_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 18)
+#define M4U_PORT_CAM_MFB_RDMA1 MTK_M4U_ID(M4U_LARB5_ID, 19)
+#define M4U_PORT_CAM_MFB_WDMA MTK_M4U_ID(M4U_LARB5_ID, 20)
+#define M4U_PORT_CAM_RSC_RDMA0 MTK_M4U_ID(M4U_LARB5_ID, 21)
+#define M4U_PORT_CAM_RSC_WDMA MTK_M4U_ID(M4U_LARB5_ID, 22)
+#define M4U_PORT_CAM_OWE_RDMA MTK_M4U_ID(M4U_LARB5_ID, 23)
+#define M4U_PORT_CAM_OWE_WDMA MTK_M4U_ID(M4U_LARB5_ID, 24)
+
+/* larb6 */
+#define M4U_PORT_CAM_IMGO MTK_M4U_ID(M4U_LARB6_ID, 0)
+#define M4U_PORT_CAM_RRZO MTK_M4U_ID(M4U_LARB6_ID, 1)
+#define M4U_PORT_CAM_AAO MTK_M4U_ID(M4U_LARB6_ID, 2)
+#define M4U_PORT_CAM_AFO MTK_M4U_ID(M4U_LARB6_ID, 3)
+#define M4U_PORT_CAM_LSCI0 MTK_M4U_ID(M4U_LARB6_ID, 4)
+#define M4U_PORT_CAM_LSCI1 MTK_M4U_ID(M4U_LARB6_ID, 5)
+#define M4U_PORT_CAM_PDO MTK_M4U_ID(M4U_LARB6_ID, 6)
+#define M4U_PORT_CAM_BPCI MTK_M4U_ID(M4U_LARB6_ID, 7)
+#define M4U_PORT_CAM_LCSO MTK_M4U_ID(M4U_LARB6_ID, 8)
+#define M4U_PORT_CAM_CAM_RSSO_A MTK_M4U_ID(M4U_LARB6_ID, 9)
+#define M4U_PORT_CAM_UFEO MTK_M4U_ID(M4U_LARB6_ID, 10)
+#define M4U_PORT_CAM_SOCO MTK_M4U_ID(M4U_LARB6_ID, 11)
+#define M4U_PORT_CAM_SOC1 MTK_M4U_ID(M4U_LARB6_ID, 12)
+#define M4U_PORT_CAM_SOC2 MTK_M4U_ID(M4U_LARB6_ID, 13)
+#define M4U_PORT_CAM_CCUI MTK_M4U_ID(M4U_LARB6_ID, 14)
+#define M4U_PORT_CAM_CCUO MTK_M4U_ID(M4U_LARB6_ID, 15)
+#define M4U_PORT_CAM_RAWI_A MTK_M4U_ID(M4U_LARB6_ID, 16)
+#define M4U_PORT_CAM_CCUG MTK_M4U_ID(M4U_LARB6_ID, 17)
+#define M4U_PORT_CAM_PSO MTK_M4U_ID(M4U_LARB6_ID, 18)
+#define M4U_PORT_CAM_AFO_1 MTK_M4U_ID(M4U_LARB6_ID, 19)
+#define M4U_PORT_CAM_LSCI_2 MTK_M4U_ID(M4U_LARB6_ID, 20)
+#define M4U_PORT_CAM_PDI MTK_M4U_ID(M4U_LARB6_ID, 21)
+#define M4U_PORT_CAM_FLKO MTK_M4U_ID(M4U_LARB6_ID, 22)
+#define M4U_PORT_CAM_LMVO MTK_M4U_ID(M4U_LARB6_ID, 23)
+#define M4U_PORT_CAM_UFGO MTK_M4U_ID(M4U_LARB6_ID, 24)
+#define M4U_PORT_CAM_SPARE MTK_M4U_ID(M4U_LARB6_ID, 25)
+#define M4U_PORT_CAM_SPARE_2 MTK_M4U_ID(M4U_LARB6_ID, 26)
+#define M4U_PORT_CAM_SPARE_3 MTK_M4U_ID(M4U_LARB6_ID, 27)
+#define M4U_PORT_CAM_SPARE_4 MTK_M4U_ID(M4U_LARB6_ID, 28)
+#define M4U_PORT_CAM_SPARE_5 MTK_M4U_ID(M4U_LARB6_ID, 29)
+#define M4U_PORT_CAM_SPARE_6 MTK_M4U_ID(M4U_LARB6_ID, 30)
+
+/* CCU */
+#define M4U_PORT_CCU0 MTK_M4U_ID(M4U_LARB7_ID, 0)
+#define M4U_PORT_CCU1 MTK_M4U_ID(M4U_LARB7_ID, 1)
+
+#endif
--
1.9.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH v9 05/21] iommu/io-pgtable-arm-v7s: Add paddr_to_iopte and iopte_to_paddr helpers
From: Yong Wu @ 2019-08-10 7:58 UTC (permalink / raw)
To: Joerg Roedel, Matthias Brugger, Robin Murphy, Will Deacon
Cc: youlin.pei, devicetree, Nicolas Boichat, cui.zhang,
srv_heupstream, chao.hao, linux-kernel, Evan Green, Tomasz Figa,
iommu, Rob Herring, linux-mediatek, yong.wu, ming-fan.chen,
anan.sun, Matthias Kaehlcke, linux-arm-kernel
In-Reply-To: <1565423901-17008-1-git-send-email-yong.wu@mediatek.com>
Add two helper functions: paddr_to_iopte and iopte_to_paddr.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Reviewed-by: Robin Murphy <robin.murphy@arm.com>
Reviewed-by: Evan Green <evgreen@chromium.org>
---
drivers/iommu/io-pgtable-arm-v7s.c | 45 ++++++++++++++++++++++++++++----------
1 file changed, 33 insertions(+), 12 deletions(-)
diff --git a/drivers/iommu/io-pgtable-arm-v7s.c b/drivers/iommu/io-pgtable-arm-v7s.c
index 0fc8dfa..72f1880 100644
--- a/drivers/iommu/io-pgtable-arm-v7s.c
+++ b/drivers/iommu/io-pgtable-arm-v7s.c
@@ -169,18 +169,38 @@ struct arm_v7s_io_pgtable {
spinlock_t split_lock;
};
+static bool arm_v7s_pte_is_cont(arm_v7s_iopte pte, int lvl);
+
static dma_addr_t __arm_v7s_dma_addr(void *pages)
{
return (dma_addr_t)virt_to_phys(pages);
}
-static arm_v7s_iopte *iopte_deref(arm_v7s_iopte pte, int lvl)
+static arm_v7s_iopte paddr_to_iopte(phys_addr_t paddr, int lvl,
+ struct io_pgtable_cfg *cfg)
{
+ return paddr & ARM_V7S_LVL_MASK(lvl);
+}
+
+static phys_addr_t iopte_to_paddr(arm_v7s_iopte pte, int lvl,
+ struct io_pgtable_cfg *cfg)
+{
+ arm_v7s_iopte mask;
+
if (ARM_V7S_PTE_IS_TABLE(pte, lvl))
- pte &= ARM_V7S_TABLE_MASK;
+ mask = ARM_V7S_TABLE_MASK;
+ else if (arm_v7s_pte_is_cont(pte, lvl))
+ mask = ARM_V7S_LVL_MASK(lvl) * ARM_V7S_CONT_PAGES;
else
- pte &= ARM_V7S_LVL_MASK(lvl);
- return phys_to_virt(pte);
+ mask = ARM_V7S_LVL_MASK(lvl);
+
+ return pte & mask;
+}
+
+static arm_v7s_iopte *iopte_deref(arm_v7s_iopte pte, int lvl,
+ struct arm_v7s_io_pgtable *data)
+{
+ return phys_to_virt(iopte_to_paddr(pte, lvl, &data->iop.cfg));
}
static void *__arm_v7s_alloc_table(int lvl, gfp_t gfp,
@@ -396,7 +416,7 @@ static int arm_v7s_init_pte(struct arm_v7s_io_pgtable *data,
if (num_entries > 1)
pte = arm_v7s_pte_to_cont(pte, lvl);
- pte |= paddr & ARM_V7S_LVL_MASK(lvl);
+ pte |= paddr_to_iopte(paddr, lvl, cfg);
__arm_v7s_set_pte(ptep, pte, num_entries, cfg);
return 0;
@@ -462,7 +482,7 @@ static int __arm_v7s_map(struct arm_v7s_io_pgtable *data, unsigned long iova,
}
if (ARM_V7S_PTE_IS_TABLE(pte, lvl)) {
- cptep = iopte_deref(pte, lvl);
+ cptep = iopte_deref(pte, lvl, data);
} else if (pte) {
/* We require an unmap first */
WARN_ON(!selftest_running);
@@ -512,7 +532,8 @@ static void arm_v7s_free_pgtable(struct io_pgtable *iop)
arm_v7s_iopte pte = data->pgd[i];
if (ARM_V7S_PTE_IS_TABLE(pte, 1))
- __arm_v7s_free_table(iopte_deref(pte, 1), 2, data);
+ __arm_v7s_free_table(iopte_deref(pte, 1, data),
+ 2, data);
}
__arm_v7s_free_table(data->pgd, 1, data);
kmem_cache_destroy(data->l2_tables);
@@ -582,7 +603,7 @@ static size_t arm_v7s_split_blk_unmap(struct arm_v7s_io_pgtable *data,
if (!ARM_V7S_PTE_IS_TABLE(pte, 1))
return 0;
- tablep = iopte_deref(pte, 1);
+ tablep = iopte_deref(pte, 1, data);
return __arm_v7s_unmap(data, iova, size, 2, tablep);
}
@@ -641,7 +662,7 @@ static size_t __arm_v7s_unmap(struct arm_v7s_io_pgtable *data,
io_pgtable_tlb_add_flush(iop, iova, blk_size,
ARM_V7S_BLOCK_SIZE(lvl + 1), false);
io_pgtable_tlb_sync(iop);
- ptep = iopte_deref(pte[i], lvl);
+ ptep = iopte_deref(pte[i], lvl, data);
__arm_v7s_free_table(ptep, lvl + 1, data);
} else if (iop->cfg.quirks & IO_PGTABLE_QUIRK_NON_STRICT) {
/*
@@ -666,7 +687,7 @@ static size_t __arm_v7s_unmap(struct arm_v7s_io_pgtable *data,
}
/* Keep on walkin' */
- ptep = iopte_deref(pte[0], lvl);
+ ptep = iopte_deref(pte[0], lvl, data);
return __arm_v7s_unmap(data, iova, size, lvl + 1, ptep);
}
@@ -692,7 +713,7 @@ static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops,
do {
ptep += ARM_V7S_LVL_IDX(iova, ++lvl);
pte = READ_ONCE(*ptep);
- ptep = iopte_deref(pte, lvl);
+ ptep = iopte_deref(pte, lvl, data);
} while (ARM_V7S_PTE_IS_TABLE(pte, lvl));
if (!ARM_V7S_PTE_IS_VALID(pte))
@@ -701,7 +722,7 @@ static phys_addr_t arm_v7s_iova_to_phys(struct io_pgtable_ops *ops,
mask = ARM_V7S_LVL_MASK(lvl);
if (arm_v7s_pte_is_cont(pte, lvl))
mask *= ARM_V7S_CONT_PAGES;
- return (pte & mask) | (iova & ~mask);
+ return iopte_to_paddr(pte, lvl, &data->iop.cfg) | (iova & ~mask);
}
static struct io_pgtable *arm_v7s_alloc_pgtable(struct io_pgtable_cfg *cfg,
--
1.9.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox