* [PATCH V2 1/6] arm64: dts: imx8mn-ddr4-evk: Add i2c1 support
From: Anson Huang @ 2019-08-17 22:28 UTC (permalink / raw)
To: robh+dt, mark.rutland, shawnguo, s.hauer, kernel, festevam,
mturquette, sboyd, rjw, viresh.kumar, leonard.crestez, abel.vesa,
devicetree, linux-arm-kernel, linux-kernel, linux-clk, linux-pm
Cc: Linux-imx
Enable i2c1 on i.MX8MN DDR4 EVK board.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
No changes.
---
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
index 9b2c172..5fce5b1 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
@@ -50,6 +50,13 @@
>;
};
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
+ MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
+ >;
+ };
+
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
fsl,pins = <
MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
@@ -182,6 +189,13 @@
};
};
+&i2c1 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+};
+
&snvs_pwrkey {
status = "okay";
};
--
2.7.4
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* [PATCH V2 2/6] arm64: dts: imx8mn-ddr4-evk: Add rohm, bd71847 PMIC support
From: Anson Huang @ 2019-08-17 22:28 UTC (permalink / raw)
To: robh+dt, mark.rutland, shawnguo, s.hauer, kernel, festevam,
mturquette, sboyd, rjw, viresh.kumar, leonard.crestez, abel.vesa,
devicetree, linux-arm-kernel, linux-kernel, linux-clk, linux-pm
Cc: Linux-imx
In-Reply-To: <1566080900-2539-1-git-send-email-Anson.Huang@nxp.com>
On i.MX8MN DDR4 EVK board, there is a rohm,bd71847 PMIC
on i2c1 bus, enable it.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
No changes.
---
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts | 109 ++++++++++++++++++++++
1 file changed, 109 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
index 5fce5b1..10ebf77 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
@@ -57,6 +57,12 @@
>;
};
+ pinctrl_pmic: pmicirq {
+ fsl,pins = <
+ MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
+ >;
+ };
+
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
fsl,pins = <
MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
@@ -194,6 +200,109 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
+
+ pmic@4b {
+ compatible = "rohm,bd71847";
+ reg = <0x4b>;
+ pinctrl-0 = <&pinctrl_pmic>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <3 GPIO_ACTIVE_LOW>;
+ rohm,reset-snvs-powered;
+
+ regulators {
+ buck1_reg: BUCK1 {
+ regulator-name = "BUCK1";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ };
+
+ buck2_reg: BUCK2 {
+ regulator-name = "BUCK2";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ };
+
+ buck3_reg: BUCK3 {
+ // BUCK5 in datasheet
+ regulator-name = "BUCK3";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1350000>;
+ };
+
+ buck4_reg: BUCK4 {
+ // BUCK6 in datasheet
+ regulator-name = "BUCK4";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck5_reg: BUCK5 {
+ // BUCK7 in datasheet
+ regulator-name = "BUCK5";
+ regulator-min-microvolt = <1605000>;
+ regulator-max-microvolt = <1995000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck6_reg: BUCK6 {
+ // BUCK8 in datasheet
+ regulator-name = "BUCK6";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1_reg: LDO1 {
+ regulator-name = "LDO1";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo2_reg: LDO2 {
+ regulator-name = "LDO2";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo3_reg: LDO3 {
+ regulator-name = "LDO3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo4_reg: LDO4 {
+ regulator-name = "LDO4";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo6_reg: LDO6 {
+ regulator-name = "LDO6";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
};
&snvs_pwrkey {
--
2.7.4
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* [PATCH V2 5/6] clk: imx8mn: Improve ARM PLL table to support CPU frequency scaling
From: Anson Huang @ 2019-08-17 22:28 UTC (permalink / raw)
To: robh+dt, mark.rutland, shawnguo, s.hauer, kernel, festevam,
mturquette, sboyd, rjw, viresh.kumar, leonard.crestez, abel.vesa,
devicetree, linux-arm-kernel, linux-kernel, linux-clk, linux-pm
Cc: Linux-imx
In-Reply-To: <1566080900-2539-1-git-send-email-Anson.Huang@nxp.com>
i.MX8MN supports CPU running at 1.5GHz/1.4GHz/1.2GHz, add missing
frequency for ARM PLL table, also add .rate_count assignment which
is necessary for searching required PLL rate from the table.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
Changes since V1:
- Improve commit log, no code change.
---
drivers/clk/imx/clk-imx8mn.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index ecd1062..3f1239a 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -42,6 +42,8 @@ enum {
static const struct imx_pll14xx_rate_table imx8mn_pll1416x_tbl[] = {
PLL_1416X_RATE(1800000000U, 225, 3, 0),
PLL_1416X_RATE(1600000000U, 200, 3, 0),
+ PLL_1416X_RATE(1500000000U, 375, 3, 1),
+ PLL_1416X_RATE(1400000000U, 350, 3, 1),
PLL_1416X_RATE(1200000000U, 300, 3, 1),
PLL_1416X_RATE(1000000000U, 250, 3, 1),
PLL_1416X_RATE(800000000U, 200, 3, 1),
@@ -82,6 +84,7 @@ static struct imx_pll14xx_clk imx8mn_dram_pll = {
static struct imx_pll14xx_clk imx8mn_arm_pll = {
.type = PLL_1416X,
.rate_table = imx8mn_pll1416x_tbl,
+ .rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
};
static struct imx_pll14xx_clk imx8mn_gpu_pll = {
--
2.7.4
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* [PATCH V2 3/6] cpufreq: Use imx-cpufreq-dt for i.MX8MN's speed grading
From: Anson Huang @ 2019-08-17 22:28 UTC (permalink / raw)
To: robh+dt, mark.rutland, shawnguo, s.hauer, kernel, festevam,
mturquette, sboyd, rjw, viresh.kumar, leonard.crestez, abel.vesa,
devicetree, linux-arm-kernel, linux-kernel, linux-clk, linux-pm
Cc: Linux-imx
In-Reply-To: <1566080900-2539-1-git-send-email-Anson.Huang@nxp.com>
Add i.MX8MN to blacklist, so that imx-cpufreq-dt driver can handle
speed grading bits just like other i.MX8M SoCs.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
No changes.
---
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index ec2057d..febcec8 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -109,6 +109,7 @@ static const struct of_device_id blacklist[] __initconst = {
{ .compatible = "fsl,imx7d", },
{ .compatible = "fsl,imx8mq", },
{ .compatible = "fsl,imx8mm", },
+ { .compatible = "fsl,imx8mn", },
{ .compatible = "marvell,armadaxp", },
--
2.7.4
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* [PATCH V2 4/6] cpufreq: imx-cpufreq-dt: Add i.MX8MN support
From: Anson Huang @ 2019-08-17 22:28 UTC (permalink / raw)
To: robh+dt, mark.rutland, shawnguo, s.hauer, kernel, festevam,
mturquette, sboyd, rjw, viresh.kumar, leonard.crestez, abel.vesa,
devicetree, linux-arm-kernel, linux-kernel, linux-clk, linux-pm
Cc: Linux-imx
In-Reply-To: <1566080900-2539-1-git-send-email-Anson.Huang@nxp.com>
i.MX8MN has different speed grading definition as below, it has 4 bits
to define speed grading, add support for it.
SPEED_GRADE[3:0] MHz
0000 2300
0001 2200
0010 2100
0011 2000
0100 1900
0101 1800
0110 1700
0111 1600
1000 1500
1001 1400
1010 1300
1011 1200
1100 1100
1101 1000
1110 900
1111 800
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
No changes.
---
drivers/cpufreq/imx-cpufreq-dt.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/cpufreq/imx-cpufreq-dt.c b/drivers/cpufreq/imx-cpufreq-dt.c
index 4f85f31..35db14c 100644
--- a/drivers/cpufreq/imx-cpufreq-dt.c
+++ b/drivers/cpufreq/imx-cpufreq-dt.c
@@ -16,6 +16,7 @@
#define OCOTP_CFG3_SPEED_GRADE_SHIFT 8
#define OCOTP_CFG3_SPEED_GRADE_MASK (0x3 << 8)
+#define IMX8MN_OCOTP_CFG3_SPEED_GRADE_MASK (0xf << 8)
#define OCOTP_CFG3_MKT_SEGMENT_SHIFT 6
#define OCOTP_CFG3_MKT_SEGMENT_MASK (0x3 << 6)
@@ -34,7 +35,12 @@ static int imx_cpufreq_dt_probe(struct platform_device *pdev)
if (ret)
return ret;
- speed_grade = (cell_value & OCOTP_CFG3_SPEED_GRADE_MASK) >> OCOTP_CFG3_SPEED_GRADE_SHIFT;
+ if (of_machine_is_compatible("fsl,imx8mn"))
+ speed_grade = (cell_value & IMX8MN_OCOTP_CFG3_SPEED_GRADE_MASK)
+ >> OCOTP_CFG3_SPEED_GRADE_SHIFT;
+ else
+ speed_grade = (cell_value & OCOTP_CFG3_SPEED_GRADE_MASK)
+ >> OCOTP_CFG3_SPEED_GRADE_SHIFT;
mkt_segment = (cell_value & OCOTP_CFG3_MKT_SEGMENT_MASK) >> OCOTP_CFG3_MKT_SEGMENT_SHIFT;
/*
--
2.7.4
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* [PATCH V2 6/6] arm64: dts: imx8mn: Add cpu-freq support
From: Anson Huang @ 2019-08-17 22:28 UTC (permalink / raw)
To: robh+dt, mark.rutland, shawnguo, s.hauer, kernel, festevam,
mturquette, sboyd, rjw, viresh.kumar, leonard.crestez, abel.vesa,
devicetree, linux-arm-kernel, linux-kernel, linux-clk, linux-pm
Cc: Linux-imx
In-Reply-To: <1566080900-2539-1-git-send-email-Anson.Huang@nxp.com>
Add A53 OPP table, cpu regulator and speed grading node to
support cpu-freq driver.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
No changes.
---
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts | 4 +++
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 41 +++++++++++++++++++++++
2 files changed, 45 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
index 10ebf77..11c705d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
@@ -27,6 +27,10 @@
};
};
+&A53_0 {
+ cpu-supply = <&buck2_reg>;
+};
+
&iomuxc {
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index 1d8899b..785f4c4 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -51,6 +51,9 @@
clocks = <&clk IMX8MN_CLK_ARM>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ operating-points-v2 = <&a53_opp_table>;
+ nvmem-cells = <&cpu_speed_grade>;
+ nvmem-cell-names = "speed_grade";
};
A53_1: cpu@1 {
@@ -61,6 +64,7 @@
clocks = <&clk IMX8MN_CLK_ARM>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ operating-points-v2 = <&a53_opp_table>;
};
A53_2: cpu@2 {
@@ -71,6 +75,7 @@
clocks = <&clk IMX8MN_CLK_ARM>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ operating-points-v2 = <&a53_opp_table>;
};
A53_3: cpu@3 {
@@ -81,6 +86,7 @@
clocks = <&clk IMX8MN_CLK_ARM>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ operating-points-v2 = <&a53_opp_table>;
};
A53_L2: l2-cache0 {
@@ -88,6 +94,35 @@
};
};
+ a53_opp_table: opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <850000>;
+ opp-supported-hw = <0xb00>, <0x7>;
+ clock-latency-ns = <150000>;
+ opp-suspend;
+ };
+
+ opp-1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
+ opp-microvolt = <950000>;
+ opp-supported-hw = <0x300>, <0x7>;
+ clock-latency-ns = <150000>;
+ opp-suspend;
+ };
+
+ opp-1500000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-microvolt = <1000000>;
+ opp-supported-hw = <0x100>, <0x3>;
+ clock-latency-ns = <150000>;
+ opp-suspend;
+ };
+ };
+
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0x80000000>;
@@ -288,6 +323,12 @@
compatible = "fsl,imx8mn-ocotp", "fsl,imx7d-ocotp", "syscon";
reg = <0x30350000 0x10000>;
clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpu_speed_grade: speed-grade@10 {
+ reg = <0x10 4>;
+ };
};
anatop: anatop@30360000 {
--
2.7.4
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* RE: [PATCH 5/6] clk: imx8mn: Add necessary frequency support for ARM PLL table
From: Stephen Boyd @ 2019-08-18 1:11 UTC (permalink / raw)
To: devicetree@vger.kernel.org, festevam@gmail.com,
kernel@pengutronix.de, linux-arm-kernel@lists.infradead.org,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-pm@vger.kernel.org, mark.rutland@arm.com,
mturquette@baylibre.com, rjw@rjwysocki.net, robh+dt@kernel.org,
s.hauer@pengutronix.de, shawnguo@kernel.org,
viresh.kumar@linaro.org, Abel Vesa, Anson Huang, Leonard Crestez
Cc: dl-linux-imx
In-Reply-To: <DB3PR0402MB3916D320EB51B2D9E28D55E1F5AE0@DB3PR0402MB3916.eurprd04.prod.outlook.com>
Quoting Anson Huang (2019-08-17 15:22:01)
> Hi, Stephen
>
> > Quoting Anson.Huang@nxp.com (2019-08-15 03:59:42)
> > > diff --git a/drivers/clk/imx/clk-imx8mn.c
> > > b/drivers/clk/imx/clk-imx8mn.c index ecd1062..3f1239a 100644
> > > --- a/drivers/clk/imx/clk-imx8mn.c
> > > +++ b/drivers/clk/imx/clk-imx8mn.c
> > > @@ -82,6 +84,7 @@ static struct imx_pll14xx_clk imx8mn_dram_pll = {
> > > static struct imx_pll14xx_clk imx8mn_arm_pll = {
> > > .type = PLL_1416X,
> > > .rate_table = imx8mn_pll1416x_tbl,
> > > + .rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
> >
> > Why is rate_count added? That's not described in the commit text.
>
> rate_count is necessary for table search during set_rate, it was missed previously,
> I will add it into commit text in V2.
>
Right, isn't that a more critical fix to make by itself instead of
rolling into this change that adds a few more frequencies?
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* Re: [PATCH 1/5] dt-bindings: clock: Add Bitmain BM1880 SoC clock controller binding
From: Stephen Boyd @ 2019-08-18 1:16 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: devicetree, mturquette, linux-kernel, darren.tsao, robh+dt,
haitao.suo, fisher.cheng, alec.lin, linux-clk, linux-arm-kernel
In-Reply-To: <20190817035845.GD14652@Mani-XPS-13-9360>
Quoting Manivannan Sadhasivam (2019-08-16 20:58:45)
> On Fri, Aug 16, 2019 at 08:46:11PM -0700, Stephen Boyd wrote:
> > Quoting Manivannan Sadhasivam (2019-08-16 20:34:22)
> > > On Wed, Aug 07, 2019 at 10:01:28PM -0700, Stephen Boyd wrote:
> > > > Quoting Manivannan Sadhasivam (2019-07-05 08:14:36)
> > > > > +It is expected that it is defined using standard clock bindings as "osc".
> > > > > +
> > > > > +Example:
> > > > > +
> > > > > + clk: clock-controller@800 {
> > > > > + compatible = "bitmain,bm1880-clk";
> > > > > + reg = <0xe8 0x0c>,<0x800 0xb0>;
> > > >
> > > > It looks weird still. What hardware module is this actually part of?
> > > > Some larger power manager block?
> > > >
> > >
> > > These are all part of the sysctrl block (clock + pinctrl + reset) and the
> > > register domains got split between system and pll.
> > >
> >
> > And that can't be one node that probes the clk, pinctrl, and reset
> > drivers from C code?
>
> It is not a MFD for sure. It's just grouping of the register domains together.
>
Are there datasheets? I'm not saying it's an "MFD", just saying that
it's one hardware IP block delivered by the SoC integrator. It's
already odd that there are two register properties.
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* Re: [PATCH 4/5] clk: Add driver for Bitmain BM1880 SoC clock controller
From: Stephen Boyd @ 2019-08-18 1:21 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: devicetree, mturquette, linux-kernel, darren.tsao, robh+dt,
haitao.suo, fisher.cheng, alec.lin, linux-clk, linux-arm-kernel
In-Reply-To: <20190817035557.GC14652@Mani-XPS-13-9360>
Quoting Manivannan Sadhasivam (2019-08-16 20:55:57)
> Hi Stephen,
>
> On Wed, Aug 07, 2019 at 10:15:59PM -0700, Stephen Boyd wrote:
> > Quoting Manivannan Sadhasivam (2019-07-05 08:14:39)
> > > diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> > > index fc1e0cf44995..ffc61ed85ade 100644
> > > --- a/drivers/clk/Kconfig
> > > +++ b/drivers/clk/Kconfig
> > > @@ -304,6 +304,12 @@ config COMMON_CLK_FIXED_MMIO
> > > help
> > > Support for Memory Mapped IO Fixed clocks
> > >
> > > +config COMMON_CLK_BM1880
> > > + bool "Clock driver for Bitmain BM1880 SoC"
> > > + depends on ARCH_BITMAIN || COMPILE_TEST
> > > + help
> > > + This driver supports the clocks on Bitmain BM1880 SoC.
> >
> > Can you add this config somewhere else besides the end? Preferably
> > close to alphabetically in this file.
> >
>
> Okay. I got confused by the fact that Makefile is sorted but not the
> Kconfig.
Ok. I'll make a reminder to sort the Kconfig after -rc1 next time.
>
> > > +
> > > source "drivers/clk/actions/Kconfig"
> > > source "drivers/clk/analogbits/Kconfig"
> > > source "drivers/clk/bcm/Kconfig"
> > > diff --git a/drivers/clk/clk-bm1880.c b/drivers/clk/clk-bm1880.c
> > > new file mode 100644
> > > index 000000000000..26cdb75bb936
> > > --- /dev/null
> > > +++ b/drivers/clk/clk-bm1880.c
[....]
> > > +
> > > +struct clk *bm1880_clk_register_pll(const struct bm1880_pll_clock *pll_clk,
> > > + void __iomem *sys_base)
> > > +{
> > > + struct bm1880_pll_hw_clock *pll_hw;
> > > + struct clk_init_data init;
> > > + struct clk_hw *hw;
> > > + int err;
> > > +
> > > + pll_hw = kzalloc(sizeof(*pll_hw), GFP_KERNEL);
> > > + if (!pll_hw)
> > > + return ERR_PTR(-ENOMEM);
> > > +
> > > + init.name = pll_clk->name;
> > > + init.ops = &bm1880_pll_ops;
> > > + init.flags = pll_clk->flags;
> > > + init.parent_names = &pll_clk->parent;
> >
> > Can you use the new way of specifying parents instead of using strings
> > for everything?
> >
>
> Sure, will do it for clocks which doesn't use helper APIs.
>
> > > + init.num_parents = 1;
> > > +
> > > + pll_hw->hw.init = &init;
> > > + pll_hw->pll.reg = pll_clk->reg;
> > > + pll_hw->base = sys_base;
> > > +
> > > + hw = &pll_hw->hw;
> > > + err = clk_hw_register(NULL, hw);
> > > +
> > > + if (err) {
> > > + kfree(pll_hw);
> > > + return ERR_PTR(err);
> > > + }
> > > +
> > > + return hw->clk;
> >
> > Can this return the clk_hw pointer instead?
> >
>
> What is the benefit? I see that only hw:init is going to be NULL in future.
Eventually we will remove ->clk from struct clk_hw and then this will
break. It also clearly makes this driver a clk provider driver and not a
clk consumer.
> So, I'll keep it as it is.
Please no!
> > > + bm1880_clk_unregister_pll(data->clk_data.clks[clks[i].id]);
> > > +
> > > + return PTR_ERR(clk);
> > > +}
> > > +
> > > +int bm1880_clk_register_mux(const struct bm1880_mux_clock *clks,
> > > + int num_clks, struct bm1880_clock_data *data)
> > > +{
> > > + struct clk *clk;
> > > + void __iomem *sys_base = data->sys_base;
> > > + int i;
> > > +
> > > + for (i = 0; i < num_clks; i++) {
> > > + clk = clk_register_mux(NULL, clks[i].name,
> >
> > Can you use the clk_hw based APIs for generic type clks?
> >
>
> IMO using helper APIs greatly reduce code size and makes the driver
> look more clean. So I prefer to use the helpers wherever applicable.
> When you plan to deprecate those, I'll switch over to plain clk_hw APIs.
We have clk_hw_register_mux(). Please use it. The clk based registration
APIs are deprecated.
> > > + kfree(clk_data);
> > > +}
> > > +
> > > +CLK_OF_DECLARE_DRIVER(bm1880_clk, "bitmain,bm1880-clk", bm1880_clk_init);
> >
> > Is there a reason why it can't be a platform driver?
> >
>
> Hmm, I looked into the majority of drivers which live under `driver/clk/`.
> Most of them are using CLK_OF_DECLARE_DRIVER, so I thought that only drivers
> which have a separate directory are preferred by the maintainers to use
> platform driver way.
>
> Anyway, I can switch over to platform driver and that's what I prefer.
>
Yes please use a platform driver unless it doesn't work for some reason.
Even then, use a platform driver and CLK_OF_DECLARE_DRIVER() in
conjunction to register the early clks from the OF_DECLARED section and
then adopt the rest to the proper device driver later on. This way we
gain the benefits of driver core.
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* RE: [PATCH 5/6] clk: imx8mn: Add necessary frequency support for ARM PLL table
From: Anson Huang @ 2019-08-18 6:19 UTC (permalink / raw)
To: Stephen Boyd, devicetree@vger.kernel.org, festevam@gmail.com,
kernel@pengutronix.de, linux-arm-kernel@lists.infradead.org,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-pm@vger.kernel.org, mark.rutland@arm.com,
mturquette@baylibre.com, rjw@rjwysocki.net, robh+dt@kernel.org,
s.hauer@pengutronix.de, shawnguo@kernel.org,
viresh.kumar@linaro.org, Abel Vesa, Leonard Crestez
Cc: dl-linux-imx
In-Reply-To: <20190818011133.CE6F52173B@mail.kernel.org>
Hi, Stephen
> Quoting Anson Huang (2019-08-17 15:22:01)
> > Hi, Stephen
> >
> > > Quoting Anson.Huang@nxp.com (2019-08-15 03:59:42)
> > > > diff --git a/drivers/clk/imx/clk-imx8mn.c
> > > > b/drivers/clk/imx/clk-imx8mn.c index ecd1062..3f1239a 100644
> > > > --- a/drivers/clk/imx/clk-imx8mn.c
> > > > +++ b/drivers/clk/imx/clk-imx8mn.c
> > > > @@ -82,6 +84,7 @@ static struct imx_pll14xx_clk imx8mn_dram_pll =
> > > > { static struct imx_pll14xx_clk imx8mn_arm_pll = {
> > > > .type = PLL_1416X,
> > > > .rate_table = imx8mn_pll1416x_tbl,
> > > > + .rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
> > >
> > > Why is rate_count added? That's not described in the commit text.
> >
> > rate_count is necessary for table search during set_rate, it was
> > missed previously, I will add it into commit text in V2.
> >
>
> Right, isn't that a more critical fix to make by itself instead of rolling into this
> change that adds a few more frequencies?
Right, let me split this patch into two patches and resend the V2.
Thanks,
Anson.
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^ permalink raw reply
* [PATCH RESEND V2 1/7] arm64: dts: imx8mn-ddr4-evk: Add i2c1 support
From: Anson Huang @ 2019-08-18 6:32 UTC (permalink / raw)
To: robh+dt, mark.rutland, shawnguo, s.hauer, kernel, festevam,
mturquette, sboyd, rjw, viresh.kumar, leonard.crestez, abel.vesa,
devicetree, linux-arm-kernel, linux-kernel, linux-clk, linux-pm
Cc: Linux-imx
Enable i2c1 on i.MX8MN DDR4 EVK board.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
No changes.
---
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
index 9b2c172..5fce5b1 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
@@ -50,6 +50,13 @@
>;
};
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
+ MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
+ >;
+ };
+
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
fsl,pins = <
MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
@@ -182,6 +189,13 @@
};
};
+&i2c1 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+};
+
&snvs_pwrkey {
status = "okay";
};
--
2.7.4
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* [PATCH RESEND V2 2/7] arm64: dts: imx8mn-ddr4-evk: Add rohm, bd71847 PMIC support
From: Anson Huang @ 2019-08-18 6:32 UTC (permalink / raw)
To: robh+dt, mark.rutland, shawnguo, s.hauer, kernel, festevam,
mturquette, sboyd, rjw, viresh.kumar, leonard.crestez, abel.vesa,
devicetree, linux-arm-kernel, linux-kernel, linux-clk, linux-pm
Cc: Linux-imx
In-Reply-To: <1566109945-11149-1-git-send-email-Anson.Huang@nxp.com>
On i.MX8MN DDR4 EVK board, there is a rohm,bd71847 PMIC
on i2c1 bus, enable it.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
No changes.
---
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts | 109 ++++++++++++++++++++++
1 file changed, 109 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
index 5fce5b1..10ebf77 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
@@ -57,6 +57,12 @@
>;
};
+ pinctrl_pmic: pmicirq {
+ fsl,pins = <
+ MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
+ >;
+ };
+
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
fsl,pins = <
MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
@@ -194,6 +200,109 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
+
+ pmic@4b {
+ compatible = "rohm,bd71847";
+ reg = <0x4b>;
+ pinctrl-0 = <&pinctrl_pmic>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <3 GPIO_ACTIVE_LOW>;
+ rohm,reset-snvs-powered;
+
+ regulators {
+ buck1_reg: BUCK1 {
+ regulator-name = "BUCK1";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ };
+
+ buck2_reg: BUCK2 {
+ regulator-name = "BUCK2";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <1250>;
+ };
+
+ buck3_reg: BUCK3 {
+ // BUCK5 in datasheet
+ regulator-name = "BUCK3";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1350000>;
+ };
+
+ buck4_reg: BUCK4 {
+ // BUCK6 in datasheet
+ regulator-name = "BUCK4";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck5_reg: BUCK5 {
+ // BUCK7 in datasheet
+ regulator-name = "BUCK5";
+ regulator-min-microvolt = <1605000>;
+ regulator-max-microvolt = <1995000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ buck6_reg: BUCK6 {
+ // BUCK8 in datasheet
+ regulator-name = "BUCK6";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1_reg: LDO1 {
+ regulator-name = "LDO1";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo2_reg: LDO2 {
+ regulator-name = "LDO2";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo3_reg: LDO3 {
+ regulator-name = "LDO3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo4_reg: LDO4 {
+ regulator-name = "LDO4";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo6_reg: LDO6 {
+ regulator-name = "LDO6";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
};
&snvs_pwrkey {
--
2.7.4
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* [PATCH RESEND V2 3/7] cpufreq: Use imx-cpufreq-dt for i.MX8MN's speed grading
From: Anson Huang @ 2019-08-18 6:32 UTC (permalink / raw)
To: robh+dt, mark.rutland, shawnguo, s.hauer, kernel, festevam,
mturquette, sboyd, rjw, viresh.kumar, leonard.crestez, abel.vesa,
devicetree, linux-arm-kernel, linux-kernel, linux-clk, linux-pm
Cc: Linux-imx
In-Reply-To: <1566109945-11149-1-git-send-email-Anson.Huang@nxp.com>
Add i.MX8MN to blacklist, so that imx-cpufreq-dt driver can handle
speed grading bits just like other i.MX8M SoCs.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
No changes.
---
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index ec2057d..febcec8 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -109,6 +109,7 @@ static const struct of_device_id blacklist[] __initconst = {
{ .compatible = "fsl,imx7d", },
{ .compatible = "fsl,imx8mq", },
{ .compatible = "fsl,imx8mm", },
+ { .compatible = "fsl,imx8mn", },
{ .compatible = "marvell,armadaxp", },
--
2.7.4
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* [PATCH RESEND V2 4/7] cpufreq: imx-cpufreq-dt: Add i.MX8MN support
From: Anson Huang @ 2019-08-18 6:32 UTC (permalink / raw)
To: robh+dt, mark.rutland, shawnguo, s.hauer, kernel, festevam,
mturquette, sboyd, rjw, viresh.kumar, leonard.crestez, abel.vesa,
devicetree, linux-arm-kernel, linux-kernel, linux-clk, linux-pm
Cc: Linux-imx
In-Reply-To: <1566109945-11149-1-git-send-email-Anson.Huang@nxp.com>
i.MX8MN has different speed grading definition as below, it has 4 bits
to define speed grading, add support for it.
SPEED_GRADE[3:0] MHz
0000 2300
0001 2200
0010 2100
0011 2000
0100 1900
0101 1800
0110 1700
0111 1600
1000 1500
1001 1400
1010 1300
1011 1200
1100 1100
1101 1000
1110 900
1111 800
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
No changes.
---
drivers/cpufreq/imx-cpufreq-dt.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/cpufreq/imx-cpufreq-dt.c b/drivers/cpufreq/imx-cpufreq-dt.c
index 4f85f31..35db14c 100644
--- a/drivers/cpufreq/imx-cpufreq-dt.c
+++ b/drivers/cpufreq/imx-cpufreq-dt.c
@@ -16,6 +16,7 @@
#define OCOTP_CFG3_SPEED_GRADE_SHIFT 8
#define OCOTP_CFG3_SPEED_GRADE_MASK (0x3 << 8)
+#define IMX8MN_OCOTP_CFG3_SPEED_GRADE_MASK (0xf << 8)
#define OCOTP_CFG3_MKT_SEGMENT_SHIFT 6
#define OCOTP_CFG3_MKT_SEGMENT_MASK (0x3 << 6)
@@ -34,7 +35,12 @@ static int imx_cpufreq_dt_probe(struct platform_device *pdev)
if (ret)
return ret;
- speed_grade = (cell_value & OCOTP_CFG3_SPEED_GRADE_MASK) >> OCOTP_CFG3_SPEED_GRADE_SHIFT;
+ if (of_machine_is_compatible("fsl,imx8mn"))
+ speed_grade = (cell_value & IMX8MN_OCOTP_CFG3_SPEED_GRADE_MASK)
+ >> OCOTP_CFG3_SPEED_GRADE_SHIFT;
+ else
+ speed_grade = (cell_value & OCOTP_CFG3_SPEED_GRADE_MASK)
+ >> OCOTP_CFG3_SPEED_GRADE_SHIFT;
mkt_segment = (cell_value & OCOTP_CFG3_MKT_SEGMENT_MASK) >> OCOTP_CFG3_MKT_SEGMENT_SHIFT;
/*
--
2.7.4
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* [PATCH RESEND V2 5/7] clk: imx8mn: Add missing rate_count assignment for each PLL structure
From: Anson Huang @ 2019-08-18 6:32 UTC (permalink / raw)
To: robh+dt, mark.rutland, shawnguo, s.hauer, kernel, festevam,
mturquette, sboyd, rjw, viresh.kumar, leonard.crestez, abel.vesa,
devicetree, linux-arm-kernel, linux-kernel, linux-clk, linux-pm
Cc: Linux-imx
In-Reply-To: <1566109945-11149-1-git-send-email-Anson.Huang@nxp.com>
Add .rate_count assignment which is necessary for searching required
PLL rate from the each PLL table.
Fixes: 96d6392b54db ("clk: imx: Add support for i.MX8MN clock driver")
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
Changes since V1:
- split the patch into 2 patches, #1 fixed those missing .rate_count assignment,
#2 add missing frequency points.
---
drivers/clk/imx/clk-imx8mn.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index ecd1062..b5a027c 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -67,36 +67,43 @@ static const struct imx_pll14xx_rate_table imx8mn_drampll_tbl[] = {
static struct imx_pll14xx_clk imx8mn_audio_pll = {
.type = PLL_1443X,
.rate_table = imx8mn_audiopll_tbl,
+ .rate_count = ARRAY_SIZE(imx8mn_audiopll_tbl),
};
static struct imx_pll14xx_clk imx8mn_video_pll = {
.type = PLL_1443X,
.rate_table = imx8mn_videopll_tbl,
+ .rate_count = ARRAY_SIZE(imx8mn_videopll_tbl),
};
static struct imx_pll14xx_clk imx8mn_dram_pll = {
.type = PLL_1443X,
.rate_table = imx8mn_drampll_tbl,
+ .rate_count = ARRAY_SIZE(imx8mn_drampll_tbl),
};
static struct imx_pll14xx_clk imx8mn_arm_pll = {
.type = PLL_1416X,
.rate_table = imx8mn_pll1416x_tbl,
+ .rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
};
static struct imx_pll14xx_clk imx8mn_gpu_pll = {
.type = PLL_1416X,
.rate_table = imx8mn_pll1416x_tbl,
+ .rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
};
static struct imx_pll14xx_clk imx8mn_vpu_pll = {
.type = PLL_1416X,
.rate_table = imx8mn_pll1416x_tbl,
+ .rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
};
static struct imx_pll14xx_clk imx8mn_sys_pll = {
.type = PLL_1416X,
.rate_table = imx8mn_pll1416x_tbl,
+ .rate_count = ARRAY_SIZE(imx8mn_pll1416x_tbl),
};
static const char * const pll_ref_sels[] = { "osc_24m", "dummy", "dummy", "dummy", };
--
2.7.4
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* [PATCH RESEND V2 6/7] clk: imx8mn: Add necessary frequency support for ARM PLL table
From: Anson Huang @ 2019-08-18 6:32 UTC (permalink / raw)
To: robh+dt, mark.rutland, shawnguo, s.hauer, kernel, festevam,
mturquette, sboyd, rjw, viresh.kumar, leonard.crestez, abel.vesa,
devicetree, linux-arm-kernel, linux-kernel, linux-clk, linux-pm
Cc: Linux-imx
In-Reply-To: <1566109945-11149-1-git-send-email-Anson.Huang@nxp.com>
i.MX8MN supports CPU running at 1.5GHz/1.4GHz/1.2GHz, add missing
frequency for ARM PLL table.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
Changes since V1:
- split the patch into 2 patches, #1 fixed those missing .rate_count assignment,
#2 add missing frequency points.
---
drivers/clk/imx/clk-imx8mn.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c
index b5a027c..48884f9 100644
--- a/drivers/clk/imx/clk-imx8mn.c
+++ b/drivers/clk/imx/clk-imx8mn.c
@@ -42,6 +42,8 @@ enum {
static const struct imx_pll14xx_rate_table imx8mn_pll1416x_tbl[] = {
PLL_1416X_RATE(1800000000U, 225, 3, 0),
PLL_1416X_RATE(1600000000U, 200, 3, 0),
+ PLL_1416X_RATE(1500000000U, 375, 3, 1),
+ PLL_1416X_RATE(1400000000U, 350, 3, 1),
PLL_1416X_RATE(1200000000U, 300, 3, 1),
PLL_1416X_RATE(1000000000U, 250, 3, 1),
PLL_1416X_RATE(800000000U, 200, 3, 1),
--
2.7.4
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^ permalink raw reply related
* [PATCH RESEND V2 7/7] arm64: dts: imx8mn: Add cpu-freq support
From: Anson Huang @ 2019-08-18 6:32 UTC (permalink / raw)
To: robh+dt, mark.rutland, shawnguo, s.hauer, kernel, festevam,
mturquette, sboyd, rjw, viresh.kumar, leonard.crestez, abel.vesa,
devicetree, linux-arm-kernel, linux-kernel, linux-clk, linux-pm
Cc: Linux-imx
In-Reply-To: <1566109945-11149-1-git-send-email-Anson.Huang@nxp.com>
Add A53 OPP table, cpu regulator and speed grading node to
support cpu-freq driver.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
No changes.
---
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts | 4 +++
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 41 +++++++++++++++++++++++
2 files changed, 45 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
index 10ebf77..11c705d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
@@ -27,6 +27,10 @@
};
};
+&A53_0 {
+ cpu-supply = <&buck2_reg>;
+};
+
&iomuxc {
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index 1d8899b..785f4c4 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -51,6 +51,9 @@
clocks = <&clk IMX8MN_CLK_ARM>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ operating-points-v2 = <&a53_opp_table>;
+ nvmem-cells = <&cpu_speed_grade>;
+ nvmem-cell-names = "speed_grade";
};
A53_1: cpu@1 {
@@ -61,6 +64,7 @@
clocks = <&clk IMX8MN_CLK_ARM>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ operating-points-v2 = <&a53_opp_table>;
};
A53_2: cpu@2 {
@@ -71,6 +75,7 @@
clocks = <&clk IMX8MN_CLK_ARM>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ operating-points-v2 = <&a53_opp_table>;
};
A53_3: cpu@3 {
@@ -81,6 +86,7 @@
clocks = <&clk IMX8MN_CLK_ARM>;
enable-method = "psci";
next-level-cache = <&A53_L2>;
+ operating-points-v2 = <&a53_opp_table>;
};
A53_L2: l2-cache0 {
@@ -88,6 +94,35 @@
};
};
+ a53_opp_table: opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt = <850000>;
+ opp-supported-hw = <0xb00>, <0x7>;
+ clock-latency-ns = <150000>;
+ opp-suspend;
+ };
+
+ opp-1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
+ opp-microvolt = <950000>;
+ opp-supported-hw = <0x300>, <0x7>;
+ clock-latency-ns = <150000>;
+ opp-suspend;
+ };
+
+ opp-1500000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-microvolt = <1000000>;
+ opp-supported-hw = <0x100>, <0x3>;
+ clock-latency-ns = <150000>;
+ opp-suspend;
+ };
+ };
+
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0x80000000>;
@@ -288,6 +323,12 @@
compatible = "fsl,imx8mn-ocotp", "fsl,imx7d-ocotp", "syscon";
reg = <0x30350000 0x10000>;
clocks = <&clk IMX8MN_CLK_OCOTP_ROOT>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpu_speed_grade: speed-grade@10 {
+ reg = <0x10 4>;
+ };
};
anatop: anatop@30360000 {
--
2.7.4
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^ permalink raw reply related
* Re: [PATCH 1/3] nvmem: mxs-ocotp: update MODULE_AUTHOR() email address
From: Srinivas Kandagatla @ 2019-08-18 9:08 UTC (permalink / raw)
To: Stefan Wahren, Jean Delvare, Guenter Roeck, David S. Miller,
Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team
Cc: linux-hwmon, netdev, linux-kernel, linux-arm-kernel
In-Reply-To: <1565720249-6549-1-git-send-email-wahrenst@gmx.net>
On 13/08/2019 19:17, Stefan Wahren wrote:
> The email address listed in MODULE_AUTHOR() will be disabled in the
> near future. Replace it with my private one.
>
> Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
> =2D--
> drivers/nvmem/mxs-ocotp.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Applied thanks.
--srini
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^ permalink raw reply
* Re: [PATCH nvmem v2 0/2] nvmem: imx: add i.MX8QM platform support
From: Srinivas Kandagatla @ 2019-08-18 9:34 UTC (permalink / raw)
To: fugang.duan
Cc: mark.rutland, robh, festevam, devicetree, gregkh, s.hauer,
linux-kernel, kernel, shawnguo, linux-arm-kernel
In-Reply-To: <20190807040320.1760-1-fugang.duan@nxp.com>
On 07/08/2019 05:03, fugang.duan@nxp.com wrote:
> From: Fugang Duan <fugang.duan@nxp.com>
>
> The patch set is to add i.MX8QM platform support for i.MX8 SCU
> OCOTP driver due to i.MX8QM efuse table has some difference with
> i.MX8QXP platform.
>
> V2:
> - Add dt-bindings for the new compatible string support.
>
> Fugang Duan (2):
> nvmem: imx: add i.MX8QM platform support
> dt-bindings: fsl: scu: add new compatible string for ocotp
>
Applied thanks.
--srini
> Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt | 4 +++-
> drivers/nvmem/imx-ocotp-scu.c | 7 +++++++
> 2 files changed, 10 insertions(+), 1 deletion(-)
>
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^ permalink raw reply
* [PATCH] spi: zynq-qspi: Fix missing spi_unregister_controller when unload module
From: Axel Lin @ 2019-08-18 9:51 UTC (permalink / raw)
To: Mark Brown; +Cc: Axel Lin, Michal Simek, linux-arm-kernel, linux-spi
Use devm_spi_register_controller to fix missing spi_unregister_controller
when unload module.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
---
drivers/spi/spi-zynq-qspi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/spi-zynq-qspi.c b/drivers/spi/spi-zynq-qspi.c
index 3155e2cabb1e..4a5326ccf65a 100644
--- a/drivers/spi/spi-zynq-qspi.c
+++ b/drivers/spi/spi-zynq-qspi.c
@@ -694,7 +694,7 @@ static int zynq_qspi_probe(struct platform_device *pdev)
ctlr->setup = zynq_qspi_setup_op;
ctlr->max_speed_hz = clk_get_rate(xqspi->refclk) / 2;
ctlr->dev.of_node = np;
- ret = spi_register_controller(ctlr);
+ ret = devm_spi_register_controller(&pdev->dev, ctlr);
if (ret) {
dev_err(&pdev->dev, "spi_register_master failed\n");
goto clk_dis_all;
--
2.20.1
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^ permalink raw reply related
* wifi on Motorola Droid 4 in 5.3-rc2
From: Pavel Machek @ 2019-08-18 10:46 UTC (permalink / raw)
To: kernel list, linux-arm-kernel, linux-omap, tony, sre, nekit1000,
mpartap, merlijn
Cc: linux-wireless
[-- Attachment #1.1: Type: text/plain, Size: 1227 bytes --]
Hi!
First, I guess I should mention that this is first time I'm attempting
to get wifi going on D4.
I'm getting this:
user@devuan:~/g/ofono$ sudo ifconfig wlan0 down
user@devuan:~/g/ofono$ sudo ifconfig wlan0 up
user@devuan:~/g/ofono$ sudo iwlist wlan0 scan
wlan0 Interface doesn't support scanning.
user@devuan:~/g/ofono$ sudo ifconfig wlan0 down
user@devuan:~/g/ofono$ sudo iwlist wlan0 scan
wlan0 Interface doesn't support scanning.
user@devuan:~/g/ofono$
I'm getting this warning during bootup:
[ 13.733703] asoc-audio-graph-card soundcard: No GPIO consumer pa
found
[ 14.279724] wlcore: WARNING Detected unconfigured mac address in
nvs, derive from fuse instead.
[ 14.293273] wlcore: WARNING Your device performance is not
optimized.
[ 14.304443] wlcore: WARNING Please use the calibrator tool to
configure your device.
[ 14.317474] wlcore: loaded
[ 16.977325] motmdm serial0-0: motmdm_dlci_send_command: AT+VERSION=
got MASERATIBP_N_05.25.00R,026.0R,XSAMASR01VRZNA026.0R,???
Any ideas?
Best regards,
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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* Re: wifi on Motorola Droid 4 in 5.3-rc2
From: Michael Nazzareno Trimarchi @ 2019-08-18 10:53 UTC (permalink / raw)
To: Pavel Machek
Cc: mpartap, Tony Lindgren, Merlijn Wajer,
open list:TI WILINK WIRELES..., kernel list, Sebastian Reichel,
nekit1000, Linux OMAP Mailing List, linux-arm-kernel
In-Reply-To: <20190818104629.GA27360@amd>
Hi
On Sun, Aug 18, 2019 at 12:46 PM Pavel Machek <pavel@ucw.cz> wrote:
>
> Hi!
>
> First, I guess I should mention that this is first time I'm attempting
> to get wifi going on D4.
>
> I'm getting this:
>
> user@devuan:~/g/ofono$ sudo ifconfig wlan0 down
> user@devuan:~/g/ofono$ sudo ifconfig wlan0 up
> user@devuan:~/g/ofono$ sudo iwlist wlan0 scan
> wlan0 Interface doesn't support scanning.
>
Try to use iw command. iwlist use an obsolete interface that you need
to activate in kernel for back compatibility with old command. Can be
your problem?
Michael
> user@devuan:~/g/ofono$ sudo ifconfig wlan0 down
> user@devuan:~/g/ofono$ sudo iwlist wlan0 scan
> wlan0 Interface doesn't support scanning.
>
> user@devuan:~/g/ofono$
>
> I'm getting this warning during bootup:
>
> [ 13.733703] asoc-audio-graph-card soundcard: No GPIO consumer pa
> found
> [ 14.279724] wlcore: WARNING Detected unconfigured mac address in
> nvs, derive from fuse instead.
> [ 14.293273] wlcore: WARNING Your device performance is not
> optimized.
> [ 14.304443] wlcore: WARNING Please use the calibrator tool to
> configure your device.
> [ 14.317474] wlcore: loaded
> [ 16.977325] motmdm serial0-0: motmdm_dlci_send_command: AT+VERSION=
> got MASERATIBP_N_05.25.00R,026.0R,XSAMASR01VRZNA026.0R,???
>
> Any ideas?
>
> Best regards,
> Pavel
>
> --
> (english) http://www.livejournal.com/~pavelmachek
> (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
--
| Michael Nazzareno Trimarchi Amarula Solutions BV |
| COO - Founder Cruquiuskade 47 |
| +31(0)851119172 Amsterdam 1018 AM NL |
| [`as] http://www.amarulasolutions.com |
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* Re: wifi on Motorola Droid 4 in 5.3-rc2
From: Pavel Machek @ 2019-08-18 11:43 UTC (permalink / raw)
To: Michael Nazzareno Trimarchi
Cc: mpartap, Tony Lindgren, Merlijn Wajer,
open list:TI WILINK WIRELES..., kernel list, Sebastian Reichel,
nekit1000, Linux OMAP Mailing List, linux-arm-kernel
In-Reply-To: <CAOf5uwnUx3mtGGHFGqKB30qcb_AMhMEhHLp2pf-4pUdhi7KP7w@mail.gmail.com>
[-- Attachment #1.1: Type: text/plain, Size: 3271 bytes --]
On Sun 2019-08-18 12:53:01, Michael Nazzareno Trimarchi wrote:
> Hi
>
> On Sun, Aug 18, 2019 at 12:46 PM Pavel Machek <pavel@ucw.cz> wrote:
> >
> > Hi!
> >
> > First, I guess I should mention that this is first time I'm attempting
> > to get wifi going on D4.
> >
> > I'm getting this:
> >
> > user@devuan:~/g/ofono$ sudo ifconfig wlan0 down
> > user@devuan:~/g/ofono$ sudo ifconfig wlan0 up
> > user@devuan:~/g/ofono$ sudo iwlist wlan0 scan
> > wlan0 Interface doesn't support scanning.
> >
>
> Try to use iw command. iwlist use an obsolete interface that you need
> to activate in kernel for back compatibility with old command. Can be
> your problem?
Let me see ... CONFIG_CFG80211_WEXT was not set.
Tried enabling it, and now I got. I remember getting it before,
too... let me try few more boots, perhaps it is random.
Best regards,
Pavel
[ 13.653778] panel-dsi-cm 58004000.encoder:display: using lookup
tables for GPIO lookup
[ 13.661834] panel-dsi-cm 58004000.encoder:display: No GPIO consumer
te found
[ 14.756622] ------------[ cut here ]------------
[ 14.761352] WARNING: CPU: 0 PID: 20 at
/data/fast/l/k/drivers/net/wireless/ti/wlcore/sdio.c:86
wl12xx_sdio_raw_read+0xa8/0x128
[ 14.772888] Modules linked in:
[ 14.776062] CPU: 0 PID: 20 Comm: kworker/0:1 Tainted: G W
5.3.0-rc4-58571-gdbaece1 #85
[ 14.783630] Hardware name: Generic OMAP4 (Flattened Device Tree)
[ 14.791381] Workqueue: events request_firmware_work_func
[ 14.796813] [<c010f2b4>] (unwind_backtrace) from [<c010b528>]
(show_stack+0x10/0x14)
[ 14.804595] [<c010b528>] (show_stack) from [<c08c1d68>]
(dump_stack+0xa8/0xc8)
[ 14.811950] [<c08c1d68>] (dump_stack) from [<c012df4c>]
(__warn+0xe8/0x114)
[ 14.816894] [<c012df4c>] (__warn) from [<c012dfb4>]
(warn_slowpath_null+0x3c/0x48)
[ 14.826629] [<c012dfb4>] (warn_slowpath_null) from [<c0566674>]
(wl12xx_sdio_raw_read+0xa8/0x128)
[ 14.835540] [<c0566674>] (wl12xx_sdio_raw_read) from [<c0567704>]
(wl12xx_get_mac+0x134/0x260)
[ 14.844268] [<c0567704>] (wl12xx_get_mac) from [<c05530cc>]
(wlcore_nvs_cb+0x270/0xb64)
[ 14.852355] [<c05530cc>] (wlcore_nvs_cb) from [<c04d7264>]
(request_firmware_work_func+0x3c/0x64)
[ 14.861267] [<c04d7264>] (request_firmware_work_func) from
[<c01455c0>] (process_one_work+0x140/0x348)
[ 14.870697] [<c01455c0>] (process_one_work) from [<c0145964>]
(worker_thread+0x164/0x4b0)
[ 14.878906] [<c0145964>] (worker_thread) from [<c014a788>]
(kthread+0x110/0x148)
[ 14.883636] [<c014a788>] (kthread) from [<c01010e8>]
(ret_from_fork+0x14/0x2c)
[ 14.893615] Exception stack(0xeda0bfb0 to 0xeda0bff8)
[ 14.893615] bfa0: 00000000
00000000 00000000 00000000
[ 14.903625] bfc0: 00000000 00000000 00000000 00000000 00000000
00000000 00000000 00000000
[ 14.913635] bfe0: 00000000 00000000 00000000 00000000 00000013
00000000
[ 14.922058] ---[ end trace b611e5d6e7d5aa92 ]---
[ 14.926788] wl1271_sdio mmc4:0001:2: sdio read failed (-110)
[ 14.932525] wlcore: ERROR couldn't get hw info
--
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(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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* Re: wifi on Motorola Droid 4 in 5.3-rc2
From: Pavel Machek @ 2019-08-18 11:46 UTC (permalink / raw)
To: Michael Nazzareno Trimarchi
Cc: mpartap, Tony Lindgren, Merlijn Wajer,
open list:TI WILINK WIRELES..., kernel list, Sebastian Reichel,
nekit1000, Linux OMAP Mailing List, linux-arm-kernel
In-Reply-To: <CAOf5uwnUx3mtGGHFGqKB30qcb_AMhMEhHLp2pf-4pUdhi7KP7w@mail.gmail.com>
[-- Attachment #1.1: Type: text/plain, Size: 760 bytes --]
Hi!
> > First, I guess I should mention that this is first time I'm attempting
> > to get wifi going on D4.
> >
> > I'm getting this:
> >
> > user@devuan:~/g/ofono$ sudo ifconfig wlan0 down
> > user@devuan:~/g/ofono$ sudo ifconfig wlan0 up
> > user@devuan:~/g/ofono$ sudo iwlist wlan0 scan
> > wlan0 Interface doesn't support scanning.
> >
>
> Try to use iw command. iwlist use an obsolete interface that you need
> to activate in kernel for back compatibility with old command. Can be
> your problem?
Two more reboots (with no changes in the config) and wifi now
works. Thanks!
Pavel
--
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(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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* Re: [PATCH v3 4/5] arm64: perf: Enable pmu counter direct access for perf event on armv8
From: kbuild test robot @ 2019-08-18 12:37 UTC (permalink / raw)
To: Raphael Gault
Cc: mark.rutland, raph.gault+kdev, peterz, catalin.marinas,
will.deacon, linux-kernel, acme, Raphael Gault, mingo, kbuild-all,
linux-arm-kernel
In-Reply-To: <20190816125934.18509-5-raphael.gault@arm.com>
[-- Attachment #1: Type: text/plain, Size: 3028 bytes --]
Hi Raphael,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on linus/master]
[cannot apply to v5.3-rc4 next-20190816]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Raphael-Gault/perf-arm64-Add-test-to-check-userspace-access-to-hardware-counters/20190818-182238
config: arm-omap2plus_defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (GCC) 7.4.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
GCC_VERSION=7.4.0 make.cross ARCH=arm
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
drivers/perf/arm_pmu.c: In function 'refresh_pmuserenr':
>> drivers/perf/arm_pmu.c:784:2: error: implicit declaration of function 'perf_switch_user_access'; did you mean 'perf_fetch_caller_regs'? [-Werror=implicit-function-declaration]
perf_switch_user_access(mm);
^~~~~~~~~~~~~~~~~~~~~~~
perf_fetch_caller_regs
drivers/perf/arm_pmu.c: In function 'armpmu_event_mapped':
>> drivers/perf/arm_pmu.c:804:36: error: 'mm_context_t {aka struct <anonymous>}' has no member named 'pmu_direct_access'
if (atomic_inc_return(&mm->context.pmu_direct_access) == 1)
^
drivers/perf/arm_pmu.c: In function 'armpmu_event_unmapped':
drivers/perf/arm_pmu.c:813:38: error: 'mm_context_t {aka struct <anonymous>}' has no member named 'pmu_direct_access'
if (atomic_dec_and_test(&mm->context.pmu_direct_access))
^
cc1: some warnings being treated as errors
vim +784 drivers/perf/arm_pmu.c
781
782 static void refresh_pmuserenr(void *mm)
783 {
> 784 perf_switch_user_access(mm);
785 }
786
787 static void armpmu_event_mapped(struct perf_event *event, struct mm_struct *mm)
788 {
789 if (!(event->hw.flags & ARMPMU_EL0_RD_CNTR))
790 return;
791
792 /*
793 * This function relies on not being called concurrently in two
794 * tasks in the same mm. Otherwise one task could observe
795 * pmu_direct_access > 1 and return all the way back to
796 * userspace with user access disabled while another task is still
797 * doing on_each_cpu_mask() to enable user access.
798 *
799 * For now, this can't happen because all callers hold mmap_sem
800 * for write. If this changes, we'll need a different solution.
801 */
802 lockdep_assert_held_write(&mm->mmap_sem);
803
> 804 if (atomic_inc_return(&mm->context.pmu_direct_access) == 1)
805 on_each_cpu(refresh_pmuserenr, mm, 1);
806 }
807
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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