* [PATCH v3 2/8] clk: Warn if clk_init_data is not zero initialized
From: Manivannan Sadhasivam @ 2019-08-19 13:01 UTC (permalink / raw)
To: sboyd, mturquette, robh+dt
Cc: devicetree, Manivannan Sadhasivam, darren.tsao, linux-kernel,
linux-arm-kernel, fisher.cheng, alec.lin, linux-clk, haitao.suo
In-Reply-To: <20190819130143.18778-1-manivannan.sadhasivam@linaro.org>
The new implementation for determining parent map uses multiple ways
to pass parent info. The order in which it gets processed depends on
the first available member. Hence, it is necessary to zero init the
clk_init_data struct so that the expected member gets processed correctly.
So, add a warning if multiple clk_init_data members are available during
clk registration.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
drivers/clk/clk.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index c0990703ce54..7d6d6984c979 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -3497,6 +3497,14 @@ static int clk_core_populate_parent_map(struct clk_core *core)
if (!num_parents)
return 0;
+ /*
+ * Check for non-zero initialized clk_init_data struct. This is
+ * required because, we only require one of the (parent_names/
+ * parent_data/parent_hws) to be set at a time. Otherwise, the
+ * current code would use first available member.
+ */
+ WARN_ON((parent_names && parent_data) || (parent_names && parent_hws));
+
/*
* Avoid unnecessary string look-ups of clk_core's possible parents by
* having a cache of names/clk_hw pointers to clk_core pointers.
--
2.17.1
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* [PATCH v3 1/8] clk: Zero init clk_init_data in helpers
From: Manivannan Sadhasivam @ 2019-08-19 13:01 UTC (permalink / raw)
To: sboyd, mturquette, robh+dt
Cc: devicetree, Manivannan Sadhasivam, darren.tsao, linux-kernel,
linux-arm-kernel, fisher.cheng, alec.lin, linux-clk, haitao.suo
In-Reply-To: <20190819130143.18778-1-manivannan.sadhasivam@linaro.org>
The clk_init_data struct needs to be initialized to zero for the new
parent_map implementation to work correctly. Otherwise, the member which
is available first will get processed.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
drivers/clk/clk-composite.c | 2 +-
drivers/clk/clk-divider.c | 2 +-
drivers/clk/clk-fixed-rate.c | 2 +-
drivers/clk/clk-gate.c | 2 +-
drivers/clk/clk-mux.c | 2 +-
5 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
index b06038b8f658..4d579f9d20f6 100644
--- a/drivers/clk/clk-composite.c
+++ b/drivers/clk/clk-composite.c
@@ -208,7 +208,7 @@ struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
unsigned long flags)
{
struct clk_hw *hw;
- struct clk_init_data init;
+ struct clk_init_data init = { NULL };
struct clk_composite *composite;
struct clk_ops *clk_composite_ops;
int ret;
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 3f9ff78c4a2a..65dd8137f9ec 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -471,7 +471,7 @@ static struct clk_hw *_register_divider(struct device *dev, const char *name,
{
struct clk_divider *div;
struct clk_hw *hw;
- struct clk_init_data init;
+ struct clk_init_data init = { NULL };
int ret;
if (clk_divider_flags & CLK_DIVIDER_HIWORD_MASK) {
diff --git a/drivers/clk/clk-fixed-rate.c b/drivers/clk/clk-fixed-rate.c
index a7e4aef7a376..746c3ecdc5b3 100644
--- a/drivers/clk/clk-fixed-rate.c
+++ b/drivers/clk/clk-fixed-rate.c
@@ -58,7 +58,7 @@ struct clk_hw *clk_hw_register_fixed_rate_with_accuracy(struct device *dev,
{
struct clk_fixed_rate *fixed;
struct clk_hw *hw;
- struct clk_init_data init;
+ struct clk_init_data init = { NULL };
int ret;
/* allocate fixed-rate clock */
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index 1b99fc962745..8ed83ec730cb 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -141,7 +141,7 @@ struct clk_hw *clk_hw_register_gate(struct device *dev, const char *name,
{
struct clk_gate *gate;
struct clk_hw *hw;
- struct clk_init_data init;
+ struct clk_init_data init = { NULL };
int ret;
if (clk_gate_flags & CLK_GATE_HIWORD_MASK) {
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 66e91f740508..2caa6b2a9ee5 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -153,7 +153,7 @@ struct clk_hw *clk_hw_register_mux_table(struct device *dev, const char *name,
{
struct clk_mux *mux;
struct clk_hw *hw;
- struct clk_init_data init;
+ struct clk_init_data init = { NULL };
u8 width = 0;
int ret;
--
2.17.1
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* [PATCH v3 0/8] Add Bitmain BM1880 clock driver
From: Manivannan Sadhasivam @ 2019-08-19 13:01 UTC (permalink / raw)
To: sboyd, mturquette, robh+dt
Cc: devicetree, Manivannan Sadhasivam, darren.tsao, linux-kernel,
linux-arm-kernel, fisher.cheng, alec.lin, linux-clk, haitao.suo
Hello,
This patchset adds common clock driver for Bitmain BM1880 SoC clock
controller. The clock controller consists of gate, divider, mux
and pll clocks with different compositions. Hence, the driver uses
composite clock structure in place where multiple clocking units are
combined together.
This patchset also removes UART fixed clock and sources clocks from clock
controller for Sophon Edge board where the driver has been validated.
Thanks,
Mani
Changes in v3:
* Switched to clk_hw_{register/unregister} APIs
* Returned clk_hw from the in-driver registration helpers
Changes in v2:
* Converted the dt binding to YAML
* Incorporated review comments from Stephen (majority of change is switching
to new way of specifying clk parents)
Manivannan Sadhasivam (8):
clk: Zero init clk_init_data in helpers
clk: Warn if clk_init_data is not zero initialized
clk: Add clk_hw_unregister_composite helper function definition
dt-bindings: clock: Add devicetree binding for BM1880 SoC
arm64: dts: bitmain: Add clock controller support for BM1880 SoC
arm64: dts: bitmain: Source common clock for UART controllers
clk: Add common clock driver for BM1880 SoC
MAINTAINERS: Add entry for BM1880 SoC clock driver
.../bindings/clock/bitmain,bm1880-clk.yaml | 83 ++
MAINTAINERS | 2 +
.../boot/dts/bitmain/bm1880-sophon-edge.dts | 9 -
arch/arm64/boot/dts/bitmain/bm1880.dtsi | 28 +
drivers/clk/Kconfig | 6 +
drivers/clk/Makefile | 1 +
drivers/clk/clk-bm1880.c | 966 ++++++++++++++++++
drivers/clk/clk-composite.c | 13 +-
drivers/clk/clk-divider.c | 2 +-
drivers/clk/clk-fixed-rate.c | 2 +-
drivers/clk/clk-gate.c | 2 +-
drivers/clk/clk-mux.c | 2 +-
drivers/clk/clk.c | 8 +
include/dt-bindings/clock/bm1880-clock.h | 82 ++
14 files changed, 1192 insertions(+), 14 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml
create mode 100644 drivers/clk/clk-bm1880.c
create mode 100644 include/dt-bindings/clock/bm1880-clock.h
--
2.17.1
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* Re: [PATCH v2] gpio: pl061: Fix the issue failed to register the ACPI interrtupion
From: Wei Xu @ 2019-08-19 12:59 UTC (permalink / raw)
To: Andy Shevchenko
Cc: salil.mehta, jinying, tangkunshan, liguozhu, Linus Walleij,
John Garry, Rafael J. Wysocki, Linux Kernel Mailing List,
shameerali.kolothum.thodi, Linuxarm, open list:GPIO SUBSYSTEM,
huangdaode, Jonathan Cameron, shiju.jose, Mika Westerberg,
zhangyi.ac, linux-arm Mailing List, Len Brown
In-Reply-To: <CAHp75VfjE4V7yY1b3JYd_Mk9-8RTok2WCN=-MMrUBw5NN90o2A@mail.gmail.com>
Hi Andy,
Thanks!
On 2019/8/16 21:40, Andy Shevchenko wrote:
> On Fri, Aug 16, 2019 at 12:07 PM Wei Xu <xuwei5@hisilicon.com> wrote:
>> Invoke acpi_gpiochip_request_interrupts after the acpi data has been
>> attached to the pl061 acpi node to register interruption.
>>
>> Otherwise it will be failed to register interruption for the ACPI case.
>> Because in the gpiochip_add_data_with_key, acpi_gpiochip_add is invoked
>> after gpiochip_add_irqchip but at that time the acpi data has not been
>> attached yet.
>> 2. cat /proc/interrupts in the guest console:
>>
>> estuary:/$ cat /proc/interrupts
>> CPU0
>> 2: 3228 GICv3 27 Level arch_timer
>> 4: 15 GICv3 33 Level uart-pl011
>> 42: 0 GICv3 23 Level arm-pmu
>> IPI0: 0 Rescheduling interrupts
>> IPI1: 0 Function call interrupts
>> IPI2: 0 CPU stop interrupts
>> IPI3: 0 CPU stop (for crash dump) interrupts
>> IPI4: 0 Timer broadcast interrupts
>> IPI5: 0 IRQ work interrupts
>> IPI6: 0 CPU wake-up interrupts
>> Err: 0
>>
>> But on QEMU v3.0.0 and Linux kernel v5.2.0-rc7, pl061 interruption is
>> there as below:
>>
>> estuary:/$ cat /proc/interrupts
>> CPU0
>> 2: 2648 GICv3 27 Level arch_timer
>> 4: 12 GICv3 33 Level uart-pl011
>> 42: 0 GICv3 23 Level arm-pmu
>> 43: 0 ARMH0061:00 3 Edge ACPI:Event
>> IPI0: 0 Rescheduling interrupts
>> IPI1: 0 Function call interrupts
>> IPI2: 0 CPU stop interrupts
>> IPI3: 0 CPU stop (for crash dump) interrupts
>> IPI4: 0 Timer broadcast interrupts
>> IPI5: 0 IRQ work interrupts
>> IPI6: 0 CPU wake-up interrupts
>> Err: 0
> In above show only affected line.
OK. Will update it in v3.
>> And the whole dmesg log on Linux kernel v5.2.0-rc7 is as below:
> NO!
> Please, remove this huge noise!
Sorry for the noise!
I will drop it in v3.
Best Regards,
Wei
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* [PATCH] arm64: dts: renesas: r8a77970: sort nodes
From: Yoshihiro Kaneko @ 2019-08-19 12:56 UTC (permalink / raw)
To: linux-renesas-soc
Cc: Magnus Damm, Simon Horman, Geert Uytterhoeven, linux-arm-kernel
Sort nodes.
If node address is present
* Sort by node address, grouping all nodes with the same compat string
and sorting the group alphabetically.
Else
* Sort alphabetically
This should not have any run-time effect.
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
---
This patch is based on the master branch of Geert Uytterhoeven's renesas-devel
tree.
arch/arm64/boot/dts/renesas/r8a77970.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
index 5b6164d..0cd3b37 100644
--- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi
@@ -1181,6 +1181,9 @@
polling-delay = <1000>;
thermal-sensors = <&thermal>;
+ cooling-maps {
+ };
+
trips {
cpu-crit {
temperature = <120000>;
@@ -1188,9 +1191,6 @@
type = "critical";
};
};
-
- cooling-maps {
- };
};
};
--
1.9.1
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* Re: [PATCH] arm64: kasan: fix phys_to_virt() false positive on tag-based kasan
From: Will Deacon @ 2019-08-19 12:56 UTC (permalink / raw)
To: Walter Wu
Cc: wsd_upstream, Catalin Marinas, Will Deacon, linux-kernel,
kasan-dev, linux-mediatek, Alexander Potapenko, linux-arm-kernel,
Andrey Konovalov, Matthias Brugger, Andrey Ryabinin,
Andrew Morton, Dmitry Vyukov
In-Reply-To: <20190819114420.2535-1-walter-zh.wu@mediatek.com>
On Mon, Aug 19, 2019 at 07:44:20PM +0800, Walter Wu wrote:
> __arm_v7s_unmap() call iopte_deref() to translate pyh_to_virt address,
> but it will modify pointer tag into 0xff, so there is a false positive.
>
> When enable tag-based kasan, phys_to_virt() function need to rewrite
> its original pointer tag in order to avoid kasan report an incorrect
> memory corruption.
Hmm. Which tree did you see this on? We've recently queued a load of fixes
in this area, but I /thought/ they were only needed after the support for
52-bit virtual addressing in the kernel.
Will
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* [PATCH] arm64: dts: renesas: r8a7796: sort nodes
From: Yoshihiro Kaneko @ 2019-08-19 12:56 UTC (permalink / raw)
To: linux-renesas-soc
Cc: Magnus Damm, Simon Horman, Geert Uytterhoeven, linux-arm-kernel
Sort nodes.
If node address is present
* Sort by node address, grouping all nodes with the same compat string
and sorting the group alphabetically.
Else
* Sort alphabetically
This should not have any run-time effect.
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
---
This patch is based on the master branch of Geert Uytterhoeven's renesas-devel
tree.
arch/arm64/boot/dts/renesas/r8a7796.dtsi | 152 +++++++++++++++----------------
1 file changed, 76 insertions(+), 76 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
index 26df5b8..3dc9d73 100644
--- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi
@@ -1833,6 +1833,17 @@
"ssi.1", "ssi.0";
status = "disabled";
+ rcar_sound,ctu {
+ ctu00: ctu-0 { };
+ ctu01: ctu-1 { };
+ ctu02: ctu-2 { };
+ ctu03: ctu-3 { };
+ ctu10: ctu-4 { };
+ ctu11: ctu-5 { };
+ ctu12: ctu-6 { };
+ ctu13: ctu-7 { };
+ };
+
rcar_sound,dvc {
dvc0: dvc-0 {
dmas = <&audma1 0xbc>;
@@ -1849,17 +1860,6 @@
mix1: mix-1 { };
};
- rcar_sound,ctu {
- ctu00: ctu-0 { };
- ctu01: ctu-1 { };
- ctu02: ctu-2 { };
- ctu03: ctu-3 { };
- ctu10: ctu-4 { };
- ctu11: ctu-5 { };
- ctu12: ctu-6 { };
- ctu13: ctu-7 { };
- };
-
rcar_sound,src {
src0: src-0 {
interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
@@ -1913,6 +1913,59 @@
};
};
+ rcar_sound,ssi {
+ ssi0: ssi-0 {
+ interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x01>, <&audma1 0x02>;
+ dma-names = "rx", "tx";
+ };
+ ssi1: ssi-1 {
+ interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x03>, <&audma1 0x04>;
+ dma-names = "rx", "tx";
+ };
+ ssi2: ssi-2 {
+ interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x05>, <&audma1 0x06>;
+ dma-names = "rx", "tx";
+ };
+ ssi3: ssi-3 {
+ interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x07>, <&audma1 0x08>;
+ dma-names = "rx", "tx";
+ };
+ ssi4: ssi-4 {
+ interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x09>, <&audma1 0x0a>;
+ dma-names = "rx", "tx";
+ };
+ ssi5: ssi-5 {
+ interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0b>, <&audma1 0x0c>;
+ dma-names = "rx", "tx";
+ };
+ ssi6: ssi-6 {
+ interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0d>, <&audma1 0x0e>;
+ dma-names = "rx", "tx";
+ };
+ ssi7: ssi-7 {
+ interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0f>, <&audma1 0x10>;
+ dma-names = "rx", "tx";
+ };
+ ssi8: ssi-8 {
+ interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x11>, <&audma1 0x12>;
+ dma-names = "rx", "tx";
+ };
+ ssi9: ssi-9 {
+ interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x13>, <&audma1 0x14>;
+ dma-names = "rx", "tx";
+ };
+ };
+
rcar_sound,ssiu {
ssiu00: ssiu-0 {
dmas = <&audma0 0x15>, <&audma1 0x16>;
@@ -2123,59 +2176,6 @@
dma-names = "rx", "tx";
};
};
-
- rcar_sound,ssi {
- ssi0: ssi-0 {
- interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x01>, <&audma1 0x02>;
- dma-names = "rx", "tx";
- };
- ssi1: ssi-1 {
- interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x03>, <&audma1 0x04>;
- dma-names = "rx", "tx";
- };
- ssi2: ssi-2 {
- interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x05>, <&audma1 0x06>;
- dma-names = "rx", "tx";
- };
- ssi3: ssi-3 {
- interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x07>, <&audma1 0x08>;
- dma-names = "rx", "tx";
- };
- ssi4: ssi-4 {
- interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x09>, <&audma1 0x0a>;
- dma-names = "rx", "tx";
- };
- ssi5: ssi-5 {
- interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0b>, <&audma1 0x0c>;
- dma-names = "rx", "tx";
- };
- ssi6: ssi-6 {
- interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0d>, <&audma1 0x0e>;
- dma-names = "rx", "tx";
- };
- ssi7: ssi-7 {
- interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0f>, <&audma1 0x10>;
- dma-names = "rx", "tx";
- };
- ssi8: ssi-8 {
- interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x11>, <&audma1 0x12>;
- dma-names = "rx", "tx";
- };
- ssi9: ssi-9 {
- interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x13>, <&audma1 0x14>;
- dma-names = "rx", "tx";
- };
- };
};
audma0: dma-controller@ec700000 {
@@ -2860,6 +2860,18 @@
thermal-sensors = <&tsc 2>;
sustainable-power = <3874>;
+ cooling-maps {
+ map0 {
+ trip = <&target>;
+ cooling-device = <&a57_0 2 4>;
+ contribution = <1024>;
+ };
+ map1 {
+ trip = <&target>;
+ cooling-device = <&a53_0 0 2>;
+ contribution = <1024>;
+ };
+ };
trips {
target: trip-point1 {
temperature = <100000>;
@@ -2873,18 +2885,6 @@
type = "critical";
};
};
- cooling-maps {
- map0 {
- trip = <&target>;
- cooling-device = <&a57_0 2 4>;
- contribution = <1024>;
- };
- map1 {
- trip = <&target>;
- cooling-device = <&a53_0 0 2>;
- contribution = <1024>;
- };
- };
};
};
--
1.9.1
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* [PATCH] arm64: dts: renesas: r8a774c0: sort nodes
From: Yoshihiro Kaneko @ 2019-08-19 12:56 UTC (permalink / raw)
To: linux-renesas-soc
Cc: Magnus Damm, Simon Horman, Geert Uytterhoeven, linux-arm-kernel
Sort nodes.
If node address is present
* Sort by node address, grouping all nodes with the same compat string
and sorting the group alphabetically.
Else
* Sort alphabetically
This should not have any run-time effect.
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
---
This patch is based on the master branch of Geert Uytterhoeven's renesas-devel
tree.
arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 90 +++++++++++++++----------------
1 file changed, 45 insertions(+), 45 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index 746775f..dc80c1a 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -1371,6 +1371,17 @@
"ssi.1", "ssi.0";
status = "disabled";
+ rcar_sound,ctu {
+ ctu00: ctu-0 { };
+ ctu01: ctu-1 { };
+ ctu02: ctu-2 { };
+ ctu03: ctu-3 { };
+ ctu10: ctu-4 { };
+ ctu11: ctu-5 { };
+ ctu12: ctu-6 { };
+ ctu13: ctu-7 { };
+ };
+
rcar_sound,dvc {
dvc0: dvc-0 {
dmas = <&audma0 0xbc>;
@@ -1387,17 +1398,6 @@
mix1: mix-1 { };
};
- rcar_sound,ctu {
- ctu00: ctu-0 { };
- ctu01: ctu-1 { };
- ctu02: ctu-2 { };
- ctu03: ctu-3 { };
- ctu10: ctu-4 { };
- ctu11: ctu-5 { };
- ctu12: ctu-6 { };
- ctu13: ctu-7 { };
- };
-
rcar_sound,src {
src0: src-0 {
interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
@@ -1706,13 +1706,24 @@
renesas,fcp = <&fcpvb0>;
};
- fcpvb0: fcp@fe96f000 {
- compatible = "renesas,fcpv";
- reg = <0 0xfe96f000 0 0x200>;
- clocks = <&cpg CPG_MOD 607>;
+ vspd0: vsp@fea20000 {
+ compatible = "renesas,vsp2";
+ reg = <0 0xfea20000 0 0x7000>;
+ interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 623>;
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 607>;
- iommus = <&ipmmu_vp0 5>;
+ resets = <&cpg 623>;
+ renesas,fcp = <&fcpvd0>;
+ };
+
+ vspd1: vsp@fea28000 {
+ compatible = "renesas,vsp2";
+ reg = <0 0xfea28000 0 0x7000>;
+ interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 622>;
+ power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+ resets = <&cpg 622>;
+ renesas,fcp = <&fcpvd1>;
};
vspi0: vsp@fe9a0000 {
@@ -1725,23 +1736,13 @@
renesas,fcp = <&fcpvi0>;
};
- fcpvi0: fcp@fe9af000 {
+ fcpvb0: fcp@fe96f000 {
compatible = "renesas,fcpv";
- reg = <0 0xfe9af000 0 0x200>;
- clocks = <&cpg CPG_MOD 611>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 611>;
- iommus = <&ipmmu_vp0 8>;
- };
-
- vspd0: vsp@fea20000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfea20000 0 0x7000>;
- interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 623>;
+ reg = <0 0xfe96f000 0 0x200>;
+ clocks = <&cpg CPG_MOD 607>;
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 623>;
- renesas,fcp = <&fcpvd0>;
+ resets = <&cpg 607>;
+ iommus = <&ipmmu_vp0 5>;
};
fcpvd0: fcp@fea27000 {
@@ -1753,16 +1754,6 @@
iommus = <&ipmmu_vi0 8>;
};
- vspd1: vsp@fea28000 {
- compatible = "renesas,vsp2";
- reg = <0 0xfea28000 0 0x7000>;
- interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&cpg CPG_MOD 622>;
- power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
- resets = <&cpg 622>;
- renesas,fcp = <&fcpvd1>;
- };
-
fcpvd1: fcp@fea2f000 {
compatible = "renesas,fcpv";
reg = <0 0xfea2f000 0 0x200>;
@@ -1772,6 +1763,15 @@
iommus = <&ipmmu_vi0 9>;
};
+ fcpvi0: fcp@fe9af000 {
+ compatible = "renesas,fcpv";
+ reg = <0 0xfe9af000 0 0x200>;
+ clocks = <&cpg CPG_MOD 611>;
+ power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
+ resets = <&cpg 611>;
+ iommus = <&ipmmu_vp0 8>;
+ };
+
csi40: csi2@feaa0000 {
compatible = "renesas,r8a774c0-csi2";
reg = <0 0xfeaa0000 0 0x10000>;
@@ -1908,6 +1908,9 @@
polling-delay = <1000>;
thermal-sensors = <&thermal>;
+ cooling-maps {
+ };
+
trips {
cpu-crit {
temperature = <120000>;
@@ -1915,9 +1918,6 @@
type = "critical";
};
};
-
- cooling-maps {
- };
};
};
--
1.9.1
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^ permalink raw reply related
* [PATCH] arm64: dts: renesas: r8a774c0-cat874: sort nodes
From: Yoshihiro Kaneko @ 2019-08-19 12:55 UTC (permalink / raw)
To: linux-renesas-soc
Cc: Magnus Damm, Simon Horman, Geert Uytterhoeven, linux-arm-kernel
Sort nodes.
If node address is present
* Sort by node address, grouping all nodes with the same compat string
and sorting the group alphabetically.
Else
* Sort alphabetically
This should not have any run-time effect.
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
---
This patch is based on the master branch of Geert Uytterhoeven's renesas-devel
tree.
arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
index 651383c..aaa37158 100644
--- a/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
+++ b/arch/arm64/boot/dts/renesas/r8a774c0-cat874.dts
@@ -82,13 +82,13 @@
simple-audio-card,bitclock-master = <&sndcpu>;
simple-audio-card,frame-master = <&sndcpu>;
- sndcpu: simple-audio-card,cpu {
- sound-dai = <&rcar_sound>;
- };
-
sndcodec: simple-audio-card,codec {
sound-dai = <&tda19988>;
};
+
+ sndcpu: simple-audio-card,cpu {
+ sound-dai = <&rcar_sound>;
+ };
};
vcc_sdhi0: regulator-vcc-sdhi0 {
@@ -313,16 +313,16 @@
power-source = <1800>;
};
- sound_pins: sound {
- groups = "ssi01239_ctrl", "ssi0_data";
- function = "ssi";
- };
-
sound_clk_pins: sound_clk {
groups = "audio_clkout1_a";
function = "audio_clk";
};
+ sound_pins: sound {
+ groups = "ssi01239_ctrl", "ssi0_data";
+ function = "ssi";
+ };
+
usb30_pins: usb30 {
groups = "usb30", "usb30_id";
function = "usb30";
--
1.9.1
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^ permalink raw reply related
* [PATCH] arm64: dts: renesas: r8a774a1: sort nodes
From: Yoshihiro Kaneko @ 2019-08-19 12:54 UTC (permalink / raw)
To: linux-renesas-soc
Cc: Magnus Damm, Simon Horman, Geert Uytterhoeven, linux-arm-kernel
Sort nodes.
If node address is present
* Sort by node address, grouping all nodes with the same compat string
and sorting the group alphabetically.
Else
* Sort alphabetically
This should not have any run-time effect.
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
---
This patch is based on the master branch of Geert Uytterhoeven's renesas-devel
tree.
arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 174 +++++++++++++++---------------
1 file changed, 87 insertions(+), 87 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index bdb4675..06c7c84 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -1726,6 +1726,28 @@
"ssi.1", "ssi.0";
status = "disabled";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ };
+ port@1 {
+ reg = <1>;
+ };
+ };
+
+ rcar_sound,ctu {
+ ctu00: ctu-0 { };
+ ctu01: ctu-1 { };
+ ctu02: ctu-2 { };
+ ctu03: ctu-3 { };
+ ctu10: ctu-4 { };
+ ctu11: ctu-5 { };
+ ctu12: ctu-6 { };
+ ctu13: ctu-7 { };
+ };
+
rcar_sound,dvc {
dvc0: dvc-0 {
dmas = <&audma1 0xbc>;
@@ -1742,17 +1764,6 @@
mix1: mix-1 { };
};
- rcar_sound,ctu {
- ctu00: ctu-0 { };
- ctu01: ctu-1 { };
- ctu02: ctu-2 { };
- ctu03: ctu-3 { };
- ctu10: ctu-4 { };
- ctu11: ctu-5 { };
- ctu12: ctu-6 { };
- ctu13: ctu-7 { };
- };
-
rcar_sound,src {
src0: src-0 {
interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
@@ -1806,6 +1817,59 @@
};
};
+ rcar_sound,ssi {
+ ssi0: ssi-0 {
+ interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x01>, <&audma1 0x02>;
+ dma-names = "rx", "tx";
+ };
+ ssi1: ssi-1 {
+ interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x03>, <&audma1 0x04>;
+ dma-names = "rx", "tx";
+ };
+ ssi2: ssi-2 {
+ interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x05>, <&audma1 0x06>;
+ dma-names = "rx", "tx";
+ };
+ ssi3: ssi-3 {
+ interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x07>, <&audma1 0x08>;
+ dma-names = "rx", "tx";
+ };
+ ssi4: ssi-4 {
+ interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x09>, <&audma1 0x0a>;
+ dma-names = "rx", "tx";
+ };
+ ssi5: ssi-5 {
+ interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0b>, <&audma1 0x0c>;
+ dma-names = "rx", "tx";
+ };
+ ssi6: ssi-6 {
+ interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0d>, <&audma1 0x0e>;
+ dma-names = "rx", "tx";
+ };
+ ssi7: ssi-7 {
+ interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0f>, <&audma1 0x10>;
+ dma-names = "rx", "tx";
+ };
+ ssi8: ssi-8 {
+ interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x11>, <&audma1 0x12>;
+ dma-names = "rx", "tx";
+ };
+ ssi9: ssi-9 {
+ interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x13>, <&audma1 0x14>;
+ dma-names = "rx", "tx";
+ };
+ };
+
rcar_sound,ssiu {
ssiu00: ssiu-0 {
dmas = <&audma0 0x15>, <&audma1 0x16>;
@@ -2016,70 +2080,6 @@
dma-names = "rx", "tx";
};
};
-
- rcar_sound,ssi {
- ssi0: ssi-0 {
- interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x01>, <&audma1 0x02>;
- dma-names = "rx", "tx";
- };
- ssi1: ssi-1 {
- interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x03>, <&audma1 0x04>;
- dma-names = "rx", "tx";
- };
- ssi2: ssi-2 {
- interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x05>, <&audma1 0x06>;
- dma-names = "rx", "tx";
- };
- ssi3: ssi-3 {
- interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x07>, <&audma1 0x08>;
- dma-names = "rx", "tx";
- };
- ssi4: ssi-4 {
- interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x09>, <&audma1 0x0a>;
- dma-names = "rx", "tx";
- };
- ssi5: ssi-5 {
- interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0b>, <&audma1 0x0c>;
- dma-names = "rx", "tx";
- };
- ssi6: ssi-6 {
- interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0d>, <&audma1 0x0e>;
- dma-names = "rx", "tx";
- };
- ssi7: ssi-7 {
- interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x0f>, <&audma1 0x10>;
- dma-names = "rx", "tx";
- };
- ssi8: ssi-8 {
- interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x11>, <&audma1 0x12>;
- dma-names = "rx", "tx";
- };
- ssi9: ssi-9 {
- interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&audma0 0x13>, <&audma1 0x14>;
- dma-names = "rx", "tx";
- };
- };
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
- port@0 {
- reg = <0>;
- };
- port@1 {
- reg = <1>;
- };
- };
};
audma0: dma-controller@ec700000 {
@@ -2746,6 +2746,18 @@
thermal-sensors = <&tsc 2>;
sustainable-power = <3874>;
+ cooling-maps {
+ map0 {
+ trip = <&target>;
+ cooling-device = <&a57_0 0 2>;
+ contribution = <1024>;
+ };
+ map1 {
+ trip = <&target>;
+ cooling-device = <&a53_0 0 2>;
+ contribution = <1024>;
+ };
+ };
trips {
target: trip-point1 {
temperature = <100000>;
@@ -2759,18 +2771,6 @@
type = "critical";
};
};
- cooling-maps {
- map0 {
- trip = <&target>;
- cooling-device = <&a57_0 0 2>;
- contribution = <1024>;
- };
- map1 {
- trip = <&target>;
- cooling-device = <&a53_0 0 2>;
- contribution = <1024>;
- };
- };
};
};
--
1.9.1
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^ permalink raw reply related
* Re: [PATCH 0/4] arm64: KPROBES_ON_FTRACE
From: Mark Rutland @ 2019-08-19 12:53 UTC (permalink / raw)
To: Jisheng Zhang
Cc: Catalin Marinas, x86@kernel.org, linux-kernel@vger.kernel.org,
Anil S Keshavamurthy, Ingo Molnar, Borislav Petkov,
Masami Hiramatsu, H. Peter Anvin, Naveen N. Rao, Steven Rostedt,
Thomas Gleixner, Will Deacon, David S. Miller,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <20190819192422.5ed79702@xhacker.debian>
Hi,
On Mon, Aug 19, 2019 at 11:35:27AM +0000, Jisheng Zhang wrote:
> Implement KPROBES_ON_FTRACE for arm64.
It would be very helpful if the cover letter could explain what
KPROBES_ON_FTRACE is, and why it is wanted.
It's not clear to me whether this is enabling new functionality for
kprobes via ftrace, or whether this is an optimization for kprobes using
ftrace under the hood.
Thanks,
Mark.
>
> Applied after FTRACE_WITH_REGS:
> http://lists.infradead.org/pipermail/linux-arm-kernel/2019-August/674404.html
>
> Jisheng Zhang (4):
> kprobes: adjust kprobe addr for KPROBES_ON_FTRACE
> kprobes/x86: use instruction_pointer and instruction_pointer_set
> kprobes: move kprobe_ftrace_handler() from x86 and make it weak
> arm64: implement KPROBES_ON_FTRACE
>
> arch/arm64/Kconfig | 1 +
> arch/arm64/kernel/probes/Makefile | 1 +
> arch/arm64/kernel/probes/ftrace.c | 16 +++++++++++
> arch/x86/kernel/kprobes/ftrace.c | 43 ----------------------------
> kernel/kprobes.c | 47 +++++++++++++++++++++++++++++++
> 5 files changed, 65 insertions(+), 43 deletions(-)
> create mode 100644 arch/arm64/kernel/probes/ftrace.c
>
> --
> 2.23.0.rc1
>
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^ permalink raw reply
* Re: [PATCH v3 02/11] dt-bindings: clock: imx-lpcg: add support to parse clocks from device tree
From: Daniel Baluta @ 2019-08-19 12:42 UTC (permalink / raw)
To: Aisheng Dong, linux-clk@vger.kernel.org
Cc: devicetree@vger.kernel.org, daniel.baluta@gmail.com,
sboyd@kernel.org, mturquette@baylibre.com, robh+dt@kernel.org,
dl-linux-imx, kernel@pengutronix.de, Fabio Estevam,
shawnguo@kernel.org, linux-arm-kernel@lists.infradead.org
In-Reply-To: <1563289265-10977-3-git-send-email-aisheng.dong@nxp.com>
On Tue, 2019-07-16 at 23:00 +0800, Dong Aisheng wrote:
> MX8QM and MX8QXP LPCG Clocks are mostly the same except they may
> reside
> in different subsystems across CPUs and also vary a bit on the
> availability.
>
> Same as SCU clock, we want to move the clock definition into device
> tree
> which can fully decouple the dependency of Clock ID definition from
> device
> tree and make us be able to write a fully generic lpcg clock driver.
>
> And we can also use the existence of clock nodes in device tree to
> address
> the device and clock availability differences across different SoCs.
>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Sascha Hauer <kernel@pengutronix.de>
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> ---
> ChangeLog:
> v2->v3:
> * no changes
> v1->v2:
> * Update example
> * Add power domain property
> ---
> .../devicetree/bindings/clock/imx8qxp-lpcg.txt | 34
> ++++++++++++++++++----
> 1 file changed, 28 insertions(+), 6 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt
> b/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt
> index 965cfa4..6fc2fd8 100644
> --- a/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt
> +++ b/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt
> @@ -11,6 +11,21 @@ enabled by these control bits, it might still not
> be running based
> on the base resource.
>
> Required properties:
> +- compatible: Should be one of:
> + "fsl,imx8qxp-lpcg"
> + "fsl,imx8qm-lpcg" followed by "fsl,imx8qxp-
> lpcg".
> +- reg: Address and length of the register set.
> +- #clock-cells: Should be 1. One LPCG supports multiple
> clocks.
> +- clocks: Input parent clocks phandle array for each
> clock.
> +- bit-offset: An integer array indicating the bit
> offset for each clock.
> +- hw-autogate: Boolean array indicating whether
> supports HW autogate for
> + each clock.
> +- clock-output-names: Shall be the corresponding names of the
> outputs.
> + NOTE this property must be specified in the
> same order
> + as the clock bit-offset and hw-autogate
> property.
> +- power-domains: Should contain the power domain used by this
> clock.
> +
> +Legacy binding (DEPRECATED):
> - compatible: Should be one of:
> "fsl,imx8qxp-lpcg-adma",
> "fsl,imx8qxp-lpcg-conn",
> @@ -33,10 +48,17 @@ Examples:
>
> #include <dt-bindings/clock/imx8qxp-clock.h>
>
> -conn_lpcg: clock-controller@5b200000 {
> - compatible = "fsl,imx8qxp-lpcg-conn";
> - reg = <0x5b200000 0xb0000>;
> +sdhc0_lpcg: clock-controller@5b200000 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x5b200000 0x10000>;
> #clock-cells = <1>;
> + clocks = <&sdhc0_clk IMX_SC_PM_CLK_PER>,
> + <&conn_ipg_clk>, <&conn_axi_clk>;
> + bit-offset = <0 16 20>;
> + clock-output-names = "sdhc0_lpcg_per_clk",
> + "sdhc0_lpcg_ipg_clk",
> + "sdhc0_lpcg_ahb_clk";
> + power-domains = <&pd IMX_SC_R_SDHC_0>;
> };
>
> usdhc1: mmc@5b010000 {
> @@ -44,8 +66,8 @@ usdhc1: mmc@5b010000 {
> interrupt-parent = <&gic>;
> interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
> reg = <0x5b010000 0x10000>;
> - clocks = <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_IPG_CLK>,
> - <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_PER_CLK>,
> - <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_HCLK>;
> + clocks = <&sdhc0_lpcg 1>,
> + <&sdhc0_lpcg 0>,
> + <&sdhc0_lpcg 2>;
Is it possible to replace magic constants 1, 0, 2 with some meaningful
constants?
Are they the same with: IMX_SC_PM_CLK_PER, etc?
> clock-names = "ipg", "per", "ahb";
> };
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^ permalink raw reply
* Re: [PATCH v3 01/11] dt-bindings: firmware: imx-scu: new binding to parse clocks from device tree
From: Daniel Baluta @ 2019-08-19 12:36 UTC (permalink / raw)
To: dongas86@gmail.com, shawnguo@kernel.org
Cc: Aisheng Dong, devicetree@vger.kernel.org, sboyd@kernel.org,
mturquette@baylibre.com, robh+dt@kernel.org, dl-linux-imx,
kernel@pengutronix.de, Fabio Estevam, Daniel Baluta,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org
In-Reply-To: <CAA+hA=Sm0MAHNwH1sZQfK8cO+3jLkue97u=ceFiUv34+qGos1Q@mail.gmail.com>
On Mon, 2019-08-05 at 11:48 +0800, Dong Aisheng wrote:
> On Sun, Aug 4, 2019 at 11:49 AM Shawn Guo <shawnguo@kernel.org>
> wrote:
> >
> > On Tue, Jul 16, 2019 at 11:00:55PM +0800, Dong Aisheng wrote:
> > > There's a few limitations on the original one cell clock binding
> > > (#clock-cells = <1>) that we have to define some SW clock IDs for
> > > device
> > > tree to reference. This may cause troubles if we want to use
> > > common
> > > clock IDs for multi platforms support when the clock of those
> > > platforms
> > > are mostly the same.
> > > e.g. Current clock IDs name are defined with SS prefix.
> > >
> > > However the device may reside in different SS across CPUs, that
> > > means the
> > > SS prefix may not valid anymore for a new SoC. Furthermore, the
> > > device
> > > availability of those clocks may also vary a bit.
> > >
> > > For such situation, we want to eliminate the using of SW Clock
> > > IDs and
> > > change to use a more close to HW one instead.
> > > For SCU clocks usage, only two params required: Resource id +
> > > Clock Type.
> >
> > If this is how SCU firmware addresses the clock, I agree that it's
> > worth
> > witching to this new bindings, which describes the hardware (SCU
> > firmware in this case) better, IMO.
> >
> > > Both parameters are platform independent. So we could use two
> > > cells binding
> > > to pass those parameters,
> > >
> > > Cc: Rob Herring <robh+dt@kernel.org>
> > > Cc: Stephen Boyd <sboyd@kernel.org>
> > > Cc: Shawn Guo <shawnguo@kernel.org>
> > > Cc: Sascha Hauer <kernel@pengutronix.de>
> > > Cc: Michael Turquette <mturquette@baylibre.com>
> > > Cc: devicetree@vger.kernel.org
> > > Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> > > ---
> > > ChangeLog:
> > > v2->v3:
> > > * Changed to two cells binding and register all clocks in driver
> > > instead of parse from device tree.
> > > v1->v2:
> > > * changed to one cell binding inspired by arm,scpi.txt
> > > Documentation/devicetree/bindings/arm/arm,scpi.txt
> > > Resource ID is encoded in 'reg' property.
> > > Clock type is encoded in generic clock-indices property.
> > > Then we don't have to search all the DT nodes to fetch
> > > those two value to construct clocks which is relatively
> > > low efficiency.
> > > * Add required power-domain property as well.
> > > ---
> > > .../devicetree/bindings/arm/freescale/fsl,scu.txt | 12
> > > +++++++-----
> > > include/dt-bindings/firmware/imx/rsrc.h | 17
> > > +++++++++++++++++
> > > 2 files changed, 24 insertions(+), 5 deletions(-)
> > >
> > > diff --git
> > > a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
> > > b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
> > > index 5d7dbab..351d335 100644
> > > --- a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
> > > +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt
> > > @@ -89,7 +89,10 @@ Required properties:
> > > "fsl,imx8qm-clock"
> > > "fsl,imx8qxp-clock"
> > > followed by "fsl,scu-clk"
> > > -- #clock-cells: Should be 1. Contains the Clock ID
> > > value.
> > > +- #clock-cells: Should be either
> > > + 2: Contains the Resource and Clock ID
> > > value.
> > > + or
> > > + 1: Contains the Clock ID value.
> > > (DEPRECATED)
> > > - clocks: List of clock specifiers, must contain an
> > > entry for
> > > each required entry in clock-names
> > > - clock-names: Should include entries
> > > "xtal_32KHz", "xtal_24MHz"
> > > @@ -162,7 +165,7 @@ firmware {
> > >
> > > clk: clk {
> > > compatible = "fsl,imx8qxp-clk", "fsl,scu-
> > > clk";
> > > - #clock-cells = <1>;
> > > + #clock-cells = <2>;
> > > };
> > >
> > > iomuxc {
> > > @@ -192,8 +195,7 @@ serial@5a060000 {
> > > ...
> > > pinctrl-names = "default";
> > > pinctrl-0 = <&pinctrl_lpuart0>;
> > > - clocks = <&clk IMX8QXP_UART0_CLK>,
> > > - <&clk IMX8QXP_UART0_IPG_CLK>;
> > > - clock-names = "per", "ipg";
> > > + clocks = <&uart0_clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>;
> > > + clock-names = "ipg";
> > > power-domains = <&pd IMX_SC_R_UART_0>;
> > > };
> > > diff --git a/include/dt-bindings/firmware/imx/rsrc.h
> > > b/include/dt-bindings/firmware/imx/rsrc.h
> > > index 4e61f64..fbeaca7 100644
> > > --- a/include/dt-bindings/firmware/imx/rsrc.h
> > > +++ b/include/dt-bindings/firmware/imx/rsrc.h
> > > @@ -547,4 +547,21 @@
> > > #define IMX_SC_R_ATTESTATION 545
> > > #define IMX_SC_R_LAST 546
> > >
> > > +/*
> > > + * Defines for SC PM CLK
> > > + */
> > > +#define IMX_SC_PM_CLK_SLV_BUS 0 /* Slave
> > > bus clock */
> > > +#define IMX_SC_PM_CLK_MST_BUS 1 /* Master
> > > bus clock */
> > > +#define IMX_SC_PM_CLK_PER 2 /* Peripheral clock
> > > */
> > > +#define IMX_SC_PM_CLK_PHY 3 /* Phy clock */
> > > +#define IMX_SC_PM_CLK_MISC 4 /* Misc clock */
>
> This is for typical device resource.
>
> > > +#define IMX_SC_PM_CLK_MISC0 0 /* Misc 0 clock */
> > > +#define IMX_SC_PM_CLK_MISC1 1 /* Misc 1 clock */
> > > +#define IMX_SC_PM_CLK_MISC2 2 /* Misc 2 clock */
> > > +#define IMX_SC_PM_CLK_MISC3 3 /* Misc 3 clock */
> > > +#define IMX_SC_PM_CLK_MISC4 4 /* Misc 4 clock */
>
> This is for some special clock types which do not belong to above
> normal clock types.
> Used very rare in SCU firmware.
> e.g.
> enet0_mac0_rxclk SC_R_ENE T_0 / SC_PM_CL K_MISC0
>
> > > +#define IMX_SC_PM_CLK_CPU 2 /* CPU clock */
> > > +#define IMX_SC_PM_CLK_PLL 4 /* PLL */
> > > +#define IMX_SC_PM_CLK_BYPASS 4 /* Bypass clock */
>
> They're for specific clock types for CPU/PLL/BYPASS only.
Hi Aisheng,
Yes, please separate this types of clocks in their own sections with
proper description.
>
> >
> > It seems that there are several sets of clock type which apply to
> > different resources/devices? If so, can you separate them a bit
> > with
> > some comments to make the list easier for readers?
> >
>
>
So, please send v4 with all comments fixed. I can help with testing.
I am also intrested in seeing this get in!
thanks,
Daniel.
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^ permalink raw reply
* Re: [PATCH 4/3] pwm: atmel: document known weaknesses of both hardware and software
From: Claudiu.Beznea @ 2019-08-19 12:28 UTC (permalink / raw)
To: u.kleine-koenig
Cc: linux-pwm, alexandre.belloni, Ludovic.Desroches, thierry.reding,
linux-arm-kernel
In-Reply-To: <20190819104617.kujgwthxtjy6cssa@pengutronix.de>
On 19.08.2019 13:46, Uwe Kleine-König wrote:
> External E-Mail
>
>
> On Mon, Aug 19, 2019 at 09:26:04AM +0000, Claudiu.Beznea@microchip.com wrote:
>>
>>
>> On 16.08.2019 12:37, Uwe Kleine-König wrote:
>>> External E-Mail
>>>
>>>
>>> Signed-off-by: Uwe Kleine-König <uwe@kleine-koenig.org>
>>> ---
>>> drivers/pwm/pwm-atmel.c | 10 ++++++++++
>>> 1 file changed, 10 insertions(+)
>>>
>>> diff --git a/drivers/pwm/pwm-atmel.c b/drivers/pwm/pwm-atmel.c
>>> index 42fe7bc043a8..1ddb93db9627 100644
>>> --- a/drivers/pwm/pwm-atmel.c
>>> +++ b/drivers/pwm/pwm-atmel.c
>>> @@ -7,6 +7,16 @@
>>> *
>>> * Reference manual for "atmel,at91sam9rl-pwm":
>>> * http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11032-32-bit-ARM926EJ-S-Microcontroller-SAM9G25_Datasheet.pdf
>>> + *
>>> + * Limitations:
>>> + * - Periods start with the inactive level.
>>
>> Are you talking here about the normal polarity (from documentation: By
>> definition, normal polarity characterizes a signal starts high for the
>> duration of the duty cycle and goes low for the remainder of the period.)
>
> When .polarity = PWM_POLARITY_NORMAL is passed to atmel_pwm_apply() the
> drivers sets PWM_CMR_CPOL=0 which according to the datasheet (linked
> above) means: "The output waveform starts at a low level."
>
> So maybe just the logic has to be inverted there,
Agree.
> but then maybe the
> output gets active instead of inactive when the PWM is disabled.
Yes, this would happen. Playing again with CPOL when disabling may be a
solution.
> (Which in my book is ok, but it's Thierry's opinion that counts here.)
>
>> If yes, this should be solved by playing with CPOL bit of CMR.
>>
>>> + * - Hardware has to be stopped in general to update settings.
>>
>> Sama5d2 has duty cycle that could be updated on the fly.
>
> There is some functionality in the 9G25, too. I didn't understand it
> completely but maybe it only helps updating one of period or duty cycle.
>
>>> + *
>>> + * Software bugs/possible improvements:
>>> + * - When atmel_pwm_apply() is called with state->enabled=false a change in
>>> + * state->polarity isn't honored.
>>
>> I know that when configuring a PWM one should get the current state of the
>> PWM, change it, then pass it to the driver via pwm_apply_state().
>
> That seems to be a common pattern at least. IMHO letting the consumer
> just configure the state that should be used should be fine, too.>
>> In case one would call the pwm_apply_state() with state->enabled =
>> false the state would be stored in PWM specific object (of type struct
>> pwm_device). On the next apply, with enabled = true, all the PWM
>> parameters would be actually applied to hardware. So, until
>> enable=true the PWM state would only be cached by PWM core specific
>> objects (in pwm_apply_state()).
>
> I fail to follow what you mean here. If a PWM runs with (say) normal
> polarity and you call pwm_apply_state(mypwm, { .polarity =
> PWM_POLARITY_INVERSED, .enabled = false, }); the apply callback of the
> lowlevel driver is called and supposed to configure the output to yield
> a constant high.
Ok, I see it now. I'll put it on my queue.
Thank you,
Claudiu Beznea
>
>>> + * - Instead of sleeping to wait for a completed period, the interrupt
>>> + * functionality could be used.
>>> */
>>>
>>> #include <linux/clk.h>
>>>
>
> Best regards
> Uwe
>
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^ permalink raw reply
* Re: [PATCH 2/3] serial: mxs-auart: Don't check for mctrl_gpio_to_gpiod() returning error
From: Simon Horman @ 2019-08-19 12:26 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Pengutronix Kernel Team, linux-serial, Richard Genoud,
Greg Kroah-Hartman, Sascha Hauer, Jiri Slaby, Frieder Schrempf,
linux-renesas-soc, NXP Linux Team, Fabio Estevam,
Uwe Kleine-König, Shawn Guo, linux-arm-kernel
In-Reply-To: <20190814092924.13857-3-geert+renesas@glider.be>
On Wed, Aug 14, 2019 at 11:29:23AM +0200, Geert Uytterhoeven wrote:
> Since commit 1d267ea6539f2663 ("serial: mctrl-gpio: simplify init
> routine"), mctrl_gpio_init() returns failure if the assignment to any
> member of the gpio array results in an error pointer.
> Since commit c359522194593815 ("serial: mctrl_gpio: Avoid probe failures
> in case of missing gpiolib"), mctrl_gpio_to_gpiod() returns NULL in the
> !CONFIG_GPIOLIB case.
> Hence there is no longer a need to check for mctrl_gpio_to_gpiod()
> returning an error value. A simple NULL check is sufficient.
>
> This follows the spirit of commit 445df7ff3fd1a0a9 ("serial: mctrl-gpio:
> drop usages of IS_ERR_OR_NULL") in the mctrl-gpio core.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
> ---
> drivers/tty/serial/mxs-auart.c | 6 ++----
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/tty/serial/mxs-auart.c b/drivers/tty/serial/mxs-auart.c
> index 4c188f4079b3ea68..e3452597068292f9 100644
> --- a/drivers/tty/serial/mxs-auart.c
> +++ b/drivers/tty/serial/mxs-auart.c
> @@ -969,10 +969,8 @@ static int mxs_auart_dma_init(struct mxs_auart_port *s)
>
> }
>
> -#define RTS_AT_AUART() IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(s->gpios, \
> - UART_GPIO_RTS))
> -#define CTS_AT_AUART() IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(s->gpios, \
> - UART_GPIO_CTS))
> +#define RTS_AT_AUART() !mctrl_gpio_to_gpiod(s->gpios, UART_GPIO_RTS)
> +#define CTS_AT_AUART() !mctrl_gpio_to_gpiod(s->gpios, UART_GPIO_CTS)
> static void mxs_auart_settermios(struct uart_port *u,
> struct ktermios *termios,
> struct ktermios *old)
> --
> 2.17.1
>
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^ permalink raw reply
* Re: [PATCH] ARM: vf610-zii-cfu1: Add node for switch watchdog
From: Shawn Guo @ 2019-08-19 12:10 UTC (permalink / raw)
To: Andrey Smirnov
Cc: Cory Tusar, Fabio Estevam, linux-arm-kernel, Chris Healy,
linux-kernel
In-Reply-To: <20190814193536.15088-1-andrew.smirnov@gmail.com>
On Wed, Aug 14, 2019 at 12:35:36PM -0700, Andrey Smirnov wrote:
> Add I2C child node for switch watchdog present on CFU1.
>
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> Signed-off-by: Cory Tusar <cory.tusar@zii.aero>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Chris Healy <cphealy@gmail.com>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
Applied, thanks.
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^ permalink raw reply
* Re: [PATCH v2] iommu/arm-smmu: Break insecure users by disabling bypass by default
From: Will Deacon @ 2019-08-19 12:09 UTC (permalink / raw)
To: Thierry Reding
Cc: Marc Gonzalez, Joerg Roedel, Will Deacon, Douglas Anderson,
Jon Hunter, linux-tegra, Robin Murphy, Linux ARM
In-Reply-To: <20190819112856.GA28102@ulmo>
On Mon, Aug 19, 2019 at 01:28:56PM +0200, Thierry Reding wrote:
> Perhaps an alternative would be to add a property to the SMMU node that
> lists a set of stream IDs for which to enable bypass by default. We
> could let the firmware set that when the display hardware has been set
> up. That way when the kernel boots we can keep scanning from the
> reserved memory and the ARM SMMU driver would not disable bypass for the
> display hardware. Only when the display hardware is actually attached to
> the IOMMU domain, and the 1:1 mappings have been created would bypass be
> disabled, and at that point there should be no SMMU faults anymore, so
> we have cleanly transitioned to the kernel.
>
> Any thoughts?
There is currently an extension to IORT under discussion which should
address this problem, so it would make a lot of sense for the DT solution
to follow the same approach. I think it will end up being along the lines
that you suggest, although we won't just enable bypass because that leaves
memory wide open if the device driver doesn't probe and it also creates
an issue because device attach typically happens before the endpoint
driver has probed.
So the flow would look something like:
- Firmware describes a physical region of memory which must be
reserved by the OS.
- Additionally, firmware describes a master -> reserved memory
linkage as part of the IOMMU description.
- When the IOMMU probes, these reserved memory regions will be
mapped 1:1 for the relevant master.
This is similar to RMRR on x86, except that the mappings are intended to
be less rigid and can be torn down if the endpoint driver decides to do
that or for things like device passthrough.
If we get that working, we should update our booting.txt so that DMA is
allowed during boot in the limited cases which this covers.
Will
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^ permalink raw reply
* Re: [PATCH] bus: imx-weim: module_platform_driver()
From: Shawn Guo @ 2019-08-19 12:08 UTC (permalink / raw)
To: Sascha Hauer; +Cc: Pengutronix Kernel Team, linux-arm-kernel, NXP Linux Team
In-Reply-To: <20190814082316.30300-1-s.hauer@pengutronix.de>
On Wed, Aug 14, 2019 at 10:23:16AM +0200, Sascha Hauer wrote:
> Switch from module_platform_driver_probe() to module_platform_driver().
> The former is not suitable for booting with device tree as the driver
> will be registered before the device and thus won't be probed again
> when the device is present.
>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Applied with subject updated like below.
bus: imx-weim: use module_platform_driver()
Shawn
> ---
> drivers/bus/imx-weim.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/bus/imx-weim.c b/drivers/bus/imx-weim.c
> index db74334ca5ef..8a9f8a4328c2 100644
> --- a/drivers/bus/imx-weim.c
> +++ b/drivers/bus/imx-weim.c
> @@ -183,8 +183,7 @@ static int __init weim_timing_setup(struct device *dev,
> return 0;
> }
>
> -static int __init weim_parse_dt(struct platform_device *pdev,
> - void __iomem *base)
> +static int weim_parse_dt(struct platform_device *pdev, void __iomem *base)
> {
> const struct of_device_id *of_id = of_match_device(weim_id_table,
> &pdev->dev);
> @@ -217,7 +216,7 @@ static int __init weim_parse_dt(struct platform_device *pdev,
> return ret;
> }
>
> -static int __init weim_probe(struct platform_device *pdev)
> +static int weim_probe(struct platform_device *pdev)
> {
> struct resource *res;
> struct clk *clk;
> @@ -254,8 +253,9 @@ static struct platform_driver weim_driver = {
> .name = "imx-weim",
> .of_match_table = weim_id_table,
> },
> + .probe = weim_probe,
> };
> -module_platform_driver_probe(weim_driver, weim_probe);
> +module_platform_driver(weim_driver);
>
> MODULE_AUTHOR("Freescale Semiconductor Inc.");
> MODULE_DESCRIPTION("i.MX EIM Controller Driver");
> --
> 2.20.1
>
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^ permalink raw reply
* Re: [PATCH v7 0/9] drm: cec: convert DRM drivers to the new notifier API
From: Hans Verkuil @ 2019-08-19 12:00 UTC (permalink / raw)
To: Dariusz Marcinkiewicz
Cc: Kate Stewart, Neil Armstrong, Daniel Vetter, dri-devel, open list,
Hans Verkuil, Dhinakaran Pandiyan, Sam Ravnborg,
linux-samsung-soc, David Francis, amd-gfx, Leo Li,
Jerry (Fangzhi) Zuo, Allison Randal, nouveau, linux-media,
Jonas Karlman, Jani Nikula, intel-gfx, Russell King, Sean Paul,
Rodrigo Vivi, linux-tegra, Thomas Gleixner, linux-arm-kernel,
Thomas Lim, Jernej Skrabec, Greg Kroah-Hartman, Douglas Anderson,
Manasi Navare, Alex Deucher, Colin Ian King, Enrico Weigelt,
Laurent Pinchart
In-Reply-To: <CALFZZQHu1C_8idxkwjBdxpW=y9gKmDnLOeTHZ9iAkNo7YubZHg@mail.gmail.com>
On 8/19/19 1:28 PM, Dariusz Marcinkiewicz wrote:
> On Mon, Aug 19, 2019 at 11:38 AM Hans Verkuil <hverkuil-cisco@xs4all.nl> wrote:
>>
>> Hi all,
>>
> Hi Hans.
>> The patches in this series can be applied independently from each other.
>>
>> If you maintain one of these drivers and you want to merge it for v5.4
>> yourself, then please do so and let me know. If you prefer I commit it
>> to drm-misc, then please review and (hopefully) Ack the patch.
>>
>> I would really like to get this in for v5.4 so I can get the userspace
>> bits in for v5.4 as well through the media subsystem.
>>
>> Dariusz, can you post a v7.1 for patch 5/9 fixing the typo?
>>
> Done.
>
> I think it would be good to test v7 changes to dw-hdmi and tda998x on
> a real hardware. Hans, do you think you would be able to test those?
>
> Thank you.
>
I'll try to do this for dw-hdmi today, but the tda998x testing will have to wait
until next week.
Regards,
Hans
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^ permalink raw reply
* Re: [PATCH] clk: imx8mn: fix int pll clk gate
From: Shawn Guo @ 2019-08-19 11:59 UTC (permalink / raw)
To: Peng Fan
Cc: Abel Vesa, Anson Huang, Stephen Boyd, mturquette@baylibre.com,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
dl-linux-imx, kernel@pengutronix.de, festevam@gmail.com,
s.hauer@pengutronix.de, linux-arm-kernel@lists.infradead.org,
Jacky Bai
In-Reply-To: <AM0PR04MB4481D73817CFCB7491DE89CB88A80@AM0PR04MB4481.eurprd04.prod.outlook.com>
On Mon, Aug 19, 2019 at 01:05:42AM +0000, Peng Fan wrote:
> Hi Stephen,
>
> > Subject: Re: [PATCH] clk: imx8mn: fix int pll clk gate
> >
> > Quoting peng.fan@nxp.com (2019-08-13 18:53:12)
> > > From: Peng Fan <peng.fan@nxp.com>
> > >
> > > To Frac pll, the gate shift is 13, however to Int PLL the gate shift
> > > is 11.
> > >
> > > Cc: <stable@vger.kernel.org>
> > > Fixes: 96d6392b54db ("clk: imx: Add support for i.MX8MN clock driver")
> > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > Reviewed-by: Jacky Bai <ping.bai@nxp.com>
> > > ---
> >
> > This is a fix for a change in -next. Why is stable Cced?
>
> Sorry, that was added by mistaken. Should I resend v2 to drop it?
Applied with both stable and Fixes tag dropped, as the commit ID is
unstable before it lands on mainline.
Shawn
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^ permalink raw reply
* Re: [PATCH] PCI: Fix misspelled words.
From: Thomas Petazzoni @ 2019-08-19 11:58 UTC (permalink / raw)
To: Krzysztof Wilczynski
Cc: Mark Rutland, devicetree, Richard Zhu, Fabio Estevam,
Sascha Hauer, linux-kernel, Rob Herring, Bjorn Helgaas,
NXP Linux Team, Pengutronix Kernel Team, linux-pci, Shawn Guo,
linux-arm-kernel, Lucas Stach
In-Reply-To: <20190819115306.27338-1-kw@linux.com>
On Mon, 19 Aug 2019 13:53:06 +0200
Krzysztof Wilczynski <kw@linux.com> wrote:
> Fix misspelled words in include/linux/pci.h, drivers/pci/Kconfig,
> and in the documentation for Freescale i.MX6 and Marvell Armada 7K/8K
> PCIe interfaces. No functional change intended.
>
> Related commit 96291d565550 ("PCI: Fix typos and whitespace errors").
>
> Signed-off-by: Krzysztof Wilczynski <kw@linux.com>
> ---
> Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt | 2 +-
> Documentation/devicetree/bindings/pci/pci-armada8k.txt | 2 +-
For pci-armada8k.txt:
Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Thomas
--
Thomas Petazzoni, CTO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
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^ permalink raw reply
* Re: [PATCH 0/4] clk: imx8m: Fix incorrect parents
From: Shawn Guo @ 2019-08-19 11:55 UTC (permalink / raw)
To: Leonard Crestez
Cc: Dong Aisheng, Jacky Bai, Anson Huang, Stephen Boyd,
Michael Turquette, linux-imx, kernel, Fabio Estevam, linux-clk,
linux-arm-kernel, Abel Vesa
In-Reply-To: <cover.1565715590.git.leonard.crestez@nxp.com>
On Tue, Aug 13, 2019 at 08:05:27PM +0300, Leonard Crestez wrote:
> No checks are made to ensure the parents in the _sels arrays actually
> exist and it turns out that several are incorrect.
>
> I found the errors using a hack to clk core, is there a better way?
> Link: https://github.com/cdleonard/linux/commit/da32c2e76eb373e8a03aec905af2eef28a7997a7
>
> Also add imx8mn GIC clock while we're at it because otherwise parent
> could get disabled and lock the system.
>
> Leonard Crestez (4):
> clk: imx8mq: Fix sys3 pll references
> clk: imx8mm: Fix incorrect parents
> clk: imx8mn: Fix incorrect parents
> clk: imx8mn: Add GIC clock
Applied all, thanks.
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^ permalink raw reply
* Re: [PATCH 0/2] ARM: psci: cpuidle: defconfig updates
From: Shawn Guo @ 2019-08-19 11:53 UTC (permalink / raw)
To: Lorenzo Pieralisi
Cc: Mark Rutland, Ulf Hansson, Catalin Marinas, Daniel Lezcano, soc,
Sudeep Holla, Will Deacon, LAKML
In-Reply-To: <20190819102053.GA30692@e121166-lin.cambridge.arm.com>
On Mon, Aug 19, 2019 at 11:21:03AM +0100, Lorenzo Pieralisi wrote:
> On Mon, Aug 19, 2019 at 09:57:17AM +0200, Shawn Guo wrote:
> > On Wed, Aug 14, 2019 at 01:52:37PM +0100, Lorenzo Pieralisi wrote:
> > > Rerouting defconfig updates related to this patch series:
> > >
> > > https://lore.kernel.org/linux-arm-kernel/cover.1565348376.git.lorenzo.pieralisi@arm.com/
> > >
> > > to arm-soc, as agreed in:
> > >
> > > https://lore.kernel.org/linux-arm-kernel/58d9677db3510ed106fe23118090c84f78a44102.1565348376.git.lorenzo.pieralisi@arm.com/
> > >
> > > Patches [1-6] are already queued in the ARM64 tree.
> > >
> > > Please consider pulling these defconfig changes, thank you very much.
> >
> > We, platform maintainers, also send arch/arm64/configs/defconfig changes
> > to arm-soc folk. So I applied both patches to IMX tree and will send
> > them to arm-soc for 5.4 inclusion.
>
> Hi Shawn,
>
> there is no need, these updates were already pulled in arm-soc so
> there is nothing to do, please drop them.
Ah, okay. Dropped them.
Shawn
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^ permalink raw reply
* [PATCH] PCI: Fix misspelled words.
From: Krzysztof Wilczynski @ 2019-08-19 11:53 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: Mark Rutland, devicetree, Richard Zhu, Thomas Petazzoni,
Fabio Estevam, Sascha Hauer, linux-kernel, Rob Herring,
NXP Linux Team, Pengutronix Kernel Team, linux-pci, Shawn Guo,
linux-arm-kernel, Lucas Stach
Fix misspelled words in include/linux/pci.h, drivers/pci/Kconfig,
and in the documentation for Freescale i.MX6 and Marvell Armada 7K/8K
PCIe interfaces. No functional change intended.
Related commit 96291d565550 ("PCI: Fix typos and whitespace errors").
Signed-off-by: Krzysztof Wilczynski <kw@linux.com>
---
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt | 2 +-
Documentation/devicetree/bindings/pci/pci-armada8k.txt | 2 +-
drivers/pci/Kconfig | 2 +-
include/linux/pci.h | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
index a7f5f5afa0e6..de4b2baf91e8 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
@@ -50,7 +50,7 @@ Additional required properties for imx7d-pcie and imx8mq-pcie:
- power-domains: Must be set to a phandle pointing to PCIE_PHY power domain
- resets: Must contain phandles to PCIe-related reset lines exposed by SRC
IP block
-- reset-names: Must contain the following entires:
+- reset-names: Must contain the following entries:
- "pciephy"
- "apps"
- "turnoff"
diff --git a/Documentation/devicetree/bindings/pci/pci-armada8k.txt b/Documentation/devicetree/bindings/pci/pci-armada8k.txt
index 9e3fc15e1af8..1aaa09254001 100644
--- a/Documentation/devicetree/bindings/pci/pci-armada8k.txt
+++ b/Documentation/devicetree/bindings/pci/pci-armada8k.txt
@@ -11,7 +11,7 @@ Required properties:
- reg-names:
- "ctrl" for the control register region
- "config" for the config space region
-- interrupts: Interrupt specifier for the PCIe controler
+- interrupts: Interrupt specifier for the PCIe controller
- clocks: reference to the PCIe controller clocks
- clock-names: mandatory if there is a second clock, in this case the
name must be "core" for the first clock and "reg" for the second
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 2ab92409210a..46f4912a370d 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -170,7 +170,7 @@ config PCI_P2PDMA
Many PCIe root complexes do not support P2P transactions and
it's hard to tell which support it at all, so at this time,
- P2P DMA transations must be between devices behind the same root
+ P2P DMA transactions must be between devices behind the same root
port.
If unsure, say N.
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 463486016290..5a89854bd3cb 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -961,7 +961,7 @@ resource_size_t pcibios_align_resource(void *, const struct resource *,
resource_size_t,
resource_size_t);
-/* Weak but can be overriden by arch */
+/* Weak but can be overridden by arch */
void pci_fixup_cardbus(struct pci_bus *);
/* Generic PCI functions used internally */
--
2.22.0
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^ permalink raw reply related
* Re: [PATCH v3 2/2] arm64: dts: imx: Add i.mx8mq nitrogen8m basic dts support
From: Shawn Guo @ 2019-08-19 11:49 UTC (permalink / raw)
To: Dafna Hirschfeld
Cc: mark.rutland, devicetree, s.hauer, linux-kernel, Troy Kisky,
Gary Bisson, robh+dt, kernel, kernel, ezequiel, linux-arm-kernel
In-Reply-To: <20190813125147.29605-1-dafna.hirschfeld@collabora.com>
On Tue, Aug 13, 2019 at 02:51:46PM +0200, Dafna Hirschfeld wrote:
> From: Gary Bisson <gary.bisson@boundarydevices.com>
>
> Add basic dts support for i.MX8MQ NITROGEN8M.
>
> Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com>
> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
> [Dafna: porting vendor's code to mainline]
> Signed-off-by: Dafna Hirschfeld <dafna.hirschfeld@collabora.com>
> ---
> arch/arm64/boot/dts/freescale/Makefile | 1 +
> .../boot/dts/freescale/imx8mq-nitrogen.dts | 400 ++++++++++++++++++
> 2 files changed, 401 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts
>
> diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
> index 8c0c4343e586..e2c6c93f47b6 100644
> --- a/arch/arm64/boot/dts/freescale/Makefile
> +++ b/arch/arm64/boot/dts/freescale/Makefile
> @@ -25,6 +25,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb
> +dtb-$(CONFIG_ARCH_MXC) += imx8mq-nitrogen.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8mq-pico-pi.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb
> dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts b/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts
> new file mode 100644
> index 000000000000..da25ea9055cd
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts
> @@ -0,0 +1,400 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright 2018 Boundary Devices
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/input/input.h>
> +#include "imx8mq.dtsi"
> +
> +/ {
> + model = "Boundary Devices i.MX8MQ Nitrogen8M";
> + compatible = "boundary,imx8mq-nitrogen8m", "fsl,imx8mq";
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + memory@40000000 {
> + device_type = "memory";
> + reg = <0x00000000 0x40000000 0 0x80000000>;
> + };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_gpio_keys>;
> +
> + power {
> + label = "Power Button";
> + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
> + linux,code = <KEY_POWER>;
> + gpio-key,wakeup;
Please check Documentation/devicetree/bindings/power/wakeup-source.txt.
> + };
> + };
> +
> + reg_vref_0v9: regulator-vref-0v9 {
> + compatible = "regulator-fixed";
> + regulator-name = "vref-0v9";
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <900000>;
> + };
> +
> + reg_vref_1v8: regulator-vref-1v8 {
> + compatible = "regulator-fixed";
> + regulator-name = "vref-1v8";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + reg_vref_2v5: regulator-vref-2v5 {
> + compatible = "regulator-fixed";
> + regulator-name = "vref-2v5";
> + regulator-min-microvolt = <2500000>;
> + regulator-max-microvolt = <2500000>;
> + };
> +
> + reg_vref_3v3: regulator-vref-3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "vref-3v3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + reg_vref_5v: regulator-vref-5v {
> + compatible = "regulator-fixed";
> + regulator-name = "vref-5v";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + };
> +};
> +
> +
> +&fec1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_fec1>;
> + phy-mode = "rgmii-id";
> + phy-handle = <ðphy0>;
> + fsl,magic-packet;
> + status = "okay";
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ethphy0: ethernet-phy@4 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <4>;
> + interrupts-extended = <&gpio1 11 IRQ_TYPE_LEVEL_LOW>;
> + };
> + };
> +};
> +
> +&i2c1 {
> + clock-frequency = <400000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c1>;
> + status = "okay";
> +
> + i2cmux@70 {
> + compatible = "nxp,pca9546";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c1_pca9546>;
> + reg = <0x70>;
> + reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + i2c1a: i2c1@0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
Please have a newline between property list and child node.
> + reg_arm_dram: regulator@60 {
> + compatible = "fcs,fan53555";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_reg_arm_dram>;
> + reg = <0x60>;
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-always-on;
> + vsel-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
> + };
> + };
> +
> + i2c1b: i2c1@1 {
> + reg = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg_dram_1p1v: regulator@60 {
> + compatible = "fcs,fan53555";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_reg_dram_1p1v>;
> + reg = <0x60>;
> + regulator-min-microvolt = <1100000>;
> + regulator-max-microvolt = <1100000>;
> + regulator-always-on;
> + vsel-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>;
> + };
> + };
> +
> + i2c1c: i2c1@2 {
> + reg = <2>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg_soc_gpu_vpu: regulator@60 {
> + compatible = "fcs,fan53555";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_reg_soc_gpu_vpu>;
> + reg = <0x60>;
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-always-on;
> + vsel-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
> + };
> + };
> +
> + i2c1d: i2c1@3 {
> + reg = <3>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + rtc@68 {
> + compatible = "microcrystal,rv4162";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c1d_rv4162>;
> + reg = <0x68>;
> + interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_LOW>;
> + wakeup-source;
> + };
> + };
> + };
> +};
> +
> +&uart1 { /* console */
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart1>;
> + assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
> + assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
> + status = "okay";
> +};
> +
> +&uart2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart2>;
> + assigned-clocks = <&clk IMX8MQ_CLK_UART2>;
> + assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
> + status = "okay";
> +};
> +
> +&usdhc1 {
> + bus-width = <8>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usdhc1>;
> + non-removable;
> + vmmc-supply = <®_vref_1v8>;
> + status = "okay";
> +};
> +
> +&wdog1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_wdog>;
> + fsl,ext-reset-output;
> + status = "okay";
> +};
> +
> +&iomuxc {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_hog>;
Have a newline.
> + pinctrl_hog: hoggrp {
> + fsl,pins = <
> + /* J17 connector, odd */
> + MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x19 /* Pin 19 */
> + MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19 /* Pin 21 */
> + MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x19 /* Pin 23 */
> + MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x19 /* Pin 25 */
> + MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x19 /* Pin 27 */
> + MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x19 /* Pin 29 */
> + MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x19 /* Pin 31 */
> + MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x19 /* Pin 33 */
> + MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x19 /* Pin 35 */
> + MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x19 /* Pin 39 */
> + MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x19 /* Pin 41 */
> + MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x19 /* Pin 43 */
> + MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19 /* Pin 45 */
> + MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x19 /* Pin 47 */
> + MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* Pin 49 */
> + MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* Pin 51 */
> +
> + /* J17 connector, even */
> + MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 /* Pin 44 */
> + MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 /* Pin 48 */
> + MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* Pin 50 */
> + MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 /* Pin 54 */
> + MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* Pin 56 */
> +
> + /* J18 connector, odd */
> + MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 /* Pin 41 */
> + MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 /* Pin 43 */
> + MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 /* Pin 45 */
> + MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x19 /* Pin 47 */
> + MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 /* Pin 49 */
> + MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x19 /* Pin 53 */
> +
> + /* J18 connector, even */
> + MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x19 /* Pin 32 */
> + MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x19 /* Pin 36 */
> + MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6 0x19 /* Pin 38 */
> + MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x19 /* Pin 40 */
> + MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x19 /* Pin 42 */
> + MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* Pin 44 */
> + MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x19 /* Pin 46 */
> +
> + /* J13 Pin 2, WL_WAKE */
> + MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0xd6
> + /* J13 Pin 4, WL_IRQ, not needed for Silex */
> + MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21 0xd6
> + /* J13 pin 9, unused */
> + MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19
> + /* J13 Pin 41, BT_CLK_REQ */
> + MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0xd6
> + /* J13 Pin 42, BT_HOST_WAKE */
> + MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0xd6
> +
> + /* Clock for both CSI1 and CSI2 */
> + MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x07
> + /* test points */
> + MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0xc1 /* TP87 */
> + >;
> + };
> +
> + pinctrl_fec1: fec1grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
> + MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
> + MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
> + MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
> + MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
> + MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
> + MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
> + MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
> + MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
> + MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
> + MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
> + MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
> + MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
> + MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
> + MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
> + MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x59
> + >;
> + };
> +
> + pinctrl_gpio_keys: gpio-keysgrp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
> + >;
> + };
> +
> +
> + pinctrl_i2c1: i2c1grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
> + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
> + >;
> + };
> +
> + pinctrl_i2c1_pca9546: i2c1-pca9546grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x49
> + >;
> + };
> +
> + pinctrl_i2c1d_rv4162: i2c1d-rv4162grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x49
> + >;
> + };
> +
> + pinctrl_reg_arm_dram: reg-arm-dram {
Please consistently name pinctrl nodes like:
pinctrl_xxx: xxxgrp {
...
};
Shawn
> + fsl,pins = <
> + MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x16
> + >;
> + };
> +
> + pinctrl_reg_dram_1p1v: reg-dram-1p1v {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11 0x16
> + >;
> + };
> +
> + pinctrl_reg_soc_gpu_vpu: reg-soc-gpu-vpu {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x16
> + >;
> + };
> +
> + pinctrl_uart1: uart1grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x45
> + MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x45
> + >;
> + };
> +
> + pinctrl_uart2: uart2grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x45
> + MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x45
> + >;
> + };
> +
> + pinctrl_usdhc1: usdhc1grp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
> + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
> + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
> + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
> + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
> + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
> + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
> + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
> + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
> + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
> + MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
> + >;
> + };
> +
> + pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
> + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
> + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
> + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
> + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
> + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
> + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
> + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
> + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
> + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
> + >;
> + };
> +
> + pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
> + fsl,pins = <
> + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
> + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
> + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
> + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
> + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
> + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
> + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
> + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
> + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
> + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
> + >;
> + };
> +
> + pinctrl_wdog: wdoggrp {
> + fsl,pins = <
> + MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
> + >;
> + };
> +};
> --
> 2.20.1
>
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