* [PATCH v1 0/6] Allow kexec reboot for GICv3 and device tree
From: Pavel Tatashin @ 2019-08-26 19:00 UTC (permalink / raw)
To: pasha.tatashin, jmorris, sashal, kexec, linux-kernel,
linux-arm-kernel, marc.zyngier, james.morse, vladimir.murzin,
mark.rutland
Marc Zyngier added the support for kexec and GICv3 for EFI based systems.
However, it is still not possible todo on systems with device trees.
Here is EFI fixes from Marc:
https://lore.kernel.org/lkml/20180921195954.21574-1-marc.zyngier@arm.com
For Device Tree variant: lets allow reserve a memory region in interrupt
controller node, and use this property to allocate interrupt tables.
This way we are safe during kexec, as these page tables are going to stay
the same after kexec.
Pavel Tatashin (6):
rqchip/gic-v3-its: reset prop table outside of allocation
rqchip/gic-v3-its: use temporary va / pa variables
rqchip/gic-v3-its: add reset pending table function
rqchip/gic-v3-its: move reset pending table outside of allocator
rqchip/gic-v3-its: move reset pending table outside of allocator
dt-bindings: interrupt-controller: add optional memory-region
.../interrupt-controller/arm,gic-v3.yaml | 7 +
drivers/irqchip/irq-gic-v3-its.c | 121 +++++++++++++-----
2 files changed, 96 insertions(+), 32 deletions(-)
--
2.23.0
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^ permalink raw reply
* [PATCH v1 1/6] rqchip/gic-v3-its: reset prop table outside of allocation
From: Pavel Tatashin @ 2019-08-26 19:00 UTC (permalink / raw)
To: pasha.tatashin, jmorris, sashal, kexec, linux-kernel,
linux-arm-kernel, marc.zyngier, james.morse, vladimir.murzin,
mark.rutland
In-Reply-To: <20190826190056.27854-1-pasha.tatashin@soleen.com>
In preparation of adding another variant of allocation, move
the resetting outside of the current allocator.
Signed-off-by: Pavel Tatashin <pasha.tatashin@soleen.com>
---
drivers/irqchip/irq-gic-v3-its.c | 13 +++----------
1 file changed, 3 insertions(+), 10 deletions(-)
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 1b5c3672aea2..ada18748ed1c 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -1621,15 +1621,7 @@ static void gic_reset_prop_table(void *va)
static struct page *its_allocate_prop_table(gfp_t gfp_flags)
{
- struct page *prop_page;
-
- prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ));
- if (!prop_page)
- return NULL;
-
- gic_reset_prop_table(page_address(prop_page));
-
- return prop_page;
+ return alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ));
}
static void its_free_prop_table(struct page *prop_page)
@@ -1685,7 +1677,6 @@ static int __init its_setup_lpi_prop_table(void)
gic_rdists->prop_table_va = memremap(gic_rdists->prop_table_pa,
LPI_PROPBASE_SZ,
MEMREMAP_WB);
- gic_reset_prop_table(gic_rdists->prop_table_va);
} else {
struct page *page;
@@ -1703,6 +1694,7 @@ static int __init its_setup_lpi_prop_table(void)
WARN_ON(gic_reserve_range(gic_rdists->prop_table_pa,
LPI_PROPBASE_SZ));
}
+ gic_reset_prop_table(gic_rdists->prop_table_va);
pr_info("GICv3: using LPI property table @%pa\n",
&gic_rdists->prop_table_pa);
@@ -3079,6 +3071,7 @@ static int its_vpe_irq_domain_alloc(struct irq_domain *domain, unsigned int virq
its_lpi_free(bitmap, base, nr_ids);
return -ENOMEM;
}
+ gic_reset_prop_table(page_address(vprop_page));
vm->db_bitmap = bitmap;
vm->db_lpi_base = base;
--
2.23.0
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^ permalink raw reply related
* [PATCH v1 2/6] rqchip/gic-v3-its: use temporary va / pa variables
From: Pavel Tatashin @ 2019-08-26 19:00 UTC (permalink / raw)
To: pasha.tatashin, jmorris, sashal, kexec, linux-kernel,
linux-arm-kernel, marc.zyngier, james.morse, vladimir.murzin,
mark.rutland
In-Reply-To: <20190826190056.27854-1-pasha.tatashin@soleen.com>
This is a cleanup, that will help later when a variant that does not
require memremap is added.
Signed-off-by: Pavel Tatashin <pasha.tatashin@soleen.com>
---
drivers/irqchip/irq-gic-v3-its.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index ada18748ed1c..656b6c6e1bf8 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -1668,15 +1668,17 @@ static int gic_reserve_range(phys_addr_t addr, unsigned long size)
static int __init its_setup_lpi_prop_table(void)
{
if (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) {
+ unsigned long pa;
u64 val;
+ void *va;
val = gicr_read_propbaser(gic_data_rdist_rd_base() + GICR_PROPBASER);
lpi_id_bits = (val & GICR_PROPBASER_IDBITS_MASK) + 1;
- gic_rdists->prop_table_pa = val & GENMASK_ULL(51, 12);
- gic_rdists->prop_table_va = memremap(gic_rdists->prop_table_pa,
- LPI_PROPBASE_SZ,
- MEMREMAP_WB);
+ pa = val & GENMASK_ULL(51, 12);
+ va = memremap(pa, LPI_PROPBASE_SZ, MEMREMAP_WB);
+ gic_rdists->prop_table_pa = pa;
+ gic_rdists->prop_table_va = va;
} else {
struct page *page;
--
2.23.0
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^ permalink raw reply related
* [PATCH v1 3/6] rqchip/gic-v3-its: add reset pending table function
From: Pavel Tatashin @ 2019-08-26 19:00 UTC (permalink / raw)
To: pasha.tatashin, jmorris, sashal, kexec, linux-kernel,
linux-arm-kernel, marc.zyngier, james.morse, vladimir.murzin,
mark.rutland
In-Reply-To: <20190826190056.27854-1-pasha.tatashin@soleen.com>
Add function that is similar to gic_reset_prop_table but for pending
table.
Signed-off-by: Pavel Tatashin <pasha.tatashin@soleen.com>
---
drivers/irqchip/irq-gic-v3-its.c | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 656b6c6e1bf8..124e2cb890cd 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -1989,17 +1989,23 @@ static int its_alloc_collections(struct its_node *its)
return 0;
}
+static void gic_reset_pending_table(void *va)
+{
+ memset(va, 0, LPI_PENDBASE_SZ);
+
+ /* Make sure the GIC will observe the zero-ed page */
+ gic_flush_dcache_to_poc(va, LPI_PENDBASE_SZ);
+}
+
static struct page *its_allocate_pending_table(gfp_t gfp_flags)
{
struct page *pend_page;
- pend_page = alloc_pages(gfp_flags | __GFP_ZERO,
- get_order(LPI_PENDBASE_SZ));
+ pend_page = alloc_pages(gfp_flags, get_order(LPI_PENDBASE_SZ));
if (!pend_page)
return NULL;
- /* Make sure the GIC will observe the zero-ed page */
- gic_flush_dcache_to_poc(page_address(pend_page), LPI_PENDBASE_SZ);
+ gic_reset_pending_table(page_address(pend_page));
return pend_page;
}
--
2.23.0
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^ permalink raw reply related
* [PATCH v1 4/6] rqchip/gic-v3-its: move reset pending table outside of allocator
From: Pavel Tatashin @ 2019-08-26 19:00 UTC (permalink / raw)
To: pasha.tatashin, jmorris, sashal, kexec, linux-kernel,
linux-arm-kernel, marc.zyngier, james.morse, vladimir.murzin,
mark.rutland
In-Reply-To: <20190826190056.27854-1-pasha.tatashin@soleen.com>
Again, in preparation of adding a new allocator, move the reset function
outside of the current allocator.
Signed-off-by: Pavel Tatashin <pasha.tatashin@soleen.com>
---
drivers/irqchip/irq-gic-v3-its.c | 12 +++---------
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 124e2cb890cd..d5f3508ca11f 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -1999,15 +1999,7 @@ static void gic_reset_pending_table(void *va)
static struct page *its_allocate_pending_table(gfp_t gfp_flags)
{
- struct page *pend_page;
-
- pend_page = alloc_pages(gfp_flags, get_order(LPI_PENDBASE_SZ));
- if (!pend_page)
- return NULL;
-
- gic_reset_pending_table(page_address(pend_page));
-
- return pend_page;
+ return alloc_pages(gfp_flags, get_order(LPI_PENDBASE_SZ));
}
static void its_free_pending_table(struct page *pt)
@@ -2064,6 +2056,7 @@ static int __init allocate_lpi_tables(void)
pr_err("Failed to allocate PENDBASE for CPU%d\n", cpu);
return -ENOMEM;
}
+ gic_reset_pending_table(page_address(pend_page));
gic_data_rdist_cpu(cpu)->pend_page = pend_page;
}
@@ -3007,6 +3000,7 @@ static int its_vpe_init(struct its_vpe *vpe)
its_vpe_id_free(vpe_id);
return -ENOMEM;
}
+ gic_reset_pending_table(page_address(vpt_page));
if (!its_alloc_vpe_table(vpe_id)) {
its_vpe_id_free(vpe_id);
--
2.23.0
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^ permalink raw reply related
* [PATCH v1 6/6] dt-bindings: interrupt-controller: add optional memory-region
From: Pavel Tatashin @ 2019-08-26 19:00 UTC (permalink / raw)
To: pasha.tatashin, jmorris, sashal, kexec, linux-kernel,
linux-arm-kernel, marc.zyngier, james.morse, vladimir.murzin,
mark.rutland
In-Reply-To: <20190826190056.27854-1-pasha.tatashin@soleen.com>
Allow pre-reserve memory in device tree that can be used in interrupt
controller tabes. This memory is required when kexec functionality is needed
with GICv3 controler and device trees.
Signed-off-by: Pavel Tatashin <pasha.tatashin@soleen.com>
---
.../bindings/interrupt-controller/arm,gic-v3.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
index c34df35a25fc..7640aaa97302 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
@@ -102,6 +102,13 @@ properties:
- $ref: /schemas/types.yaml#/definitions/uint32
- maximum: 4096 # Should be enough?
+ memory-region:
+ description:
+ Memory used to allocate property and pending tables.
+ Required if kexec functionality is needed.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint64
+
msi-controller:
description:
Only present if the Message Based Interrupt functionnality is
--
2.23.0
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* [PATCH v1 5/6] rqchip/gic-v3-its: move reset pending table outside of allocator
From: Pavel Tatashin @ 2019-08-26 19:00 UTC (permalink / raw)
To: pasha.tatashin, jmorris, sashal, kexec, linux-kernel,
linux-arm-kernel, marc.zyngier, james.morse, vladimir.murzin,
mark.rutland
In-Reply-To: <20190826190056.27854-1-pasha.tatashin@soleen.com>
Allow to use reserved memory for interrupt controller tables.
Currently, it is not possible to do kexec reboots without possible memory
corruption using device tree and GICv3 interrupt controller.
GICv3 can be configured once during boot, and location of tables cannot
be changed thereafter.
The fix is to allow to reserve memory region in interrupt controller device
property, and use it to do allocations.
Signed-off-by: Pavel Tatashin <pasha.tatashin@soleen.com>
---
drivers/irqchip/irq-gic-v3-its.c | 82 ++++++++++++++++++++++++++++----
1 file changed, 72 insertions(+), 10 deletions(-)
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index d5f3508ca11f..aeda8760cc4e 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -47,6 +47,54 @@
static u32 lpi_id_bits;
+/*
+ * Describes reserved memory region in interrupt controller.
+ * The memory reserved: [pa_start, pa_end)
+ */
+struct of_resv {
+ unsigned long pa_start;
+ unsigned long pa_end;
+};
+
+static struct page __init *get_of_page(struct of_resv *resv, unsigned long size)
+{
+ unsigned long pa = ALIGN(resv->pa_start, size);
+ unsigned long pa_next = pa + size;
+
+ /* Check if there is enough memory reserved to do another allocation */
+ if (pa_next > resv->pa_end)
+ return NULL;
+
+ resv->pa_start = pa_next;
+ memset(phys_to_virt(pa), 0, size);
+
+ return phys_to_page(pa);
+}
+
+/*
+ * Memory controller might have a reserved memory region to be used for table
+ * allocations. This is a requirement for kexec reboots.
+ */
+static void __init its_of_mem_region(struct device_node *node,
+ struct of_resv **resv,
+ struct of_resv *resv_buf)
+{
+ struct device_node *np = of_parse_phandle(node, "memory-region", 0);
+ struct resource mem_res;
+
+ if (!np)
+ return;
+
+ if (of_address_to_resource(np, 0, &mem_res)) {
+ pr_warn("%pOF: address to resource failed\n", np);
+ return;
+ }
+
+ resv_buf->pa_start = mem_res.start;
+ resv_buf->pa_end = mem_res.start + resource_size(&mem_res);
+ *resv = resv_buf;
+}
+
/*
* We allocate memory for PROPBASE to cover 2 ^ lpi_id_bits LPIs to
* deal with (one configuration byte per interrupt). PENDBASE has to
@@ -1665,7 +1713,7 @@ static int gic_reserve_range(phys_addr_t addr, unsigned long size)
return 0;
}
-static int __init its_setup_lpi_prop_table(void)
+static int __init its_setup_lpi_prop_table(struct of_resv *resv)
{
if (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) {
unsigned long pa;
@@ -1676,7 +1724,10 @@ static int __init its_setup_lpi_prop_table(void)
lpi_id_bits = (val & GICR_PROPBASER_IDBITS_MASK) + 1;
pa = val & GENMASK_ULL(51, 12);
- va = memremap(pa, LPI_PROPBASE_SZ, MEMREMAP_WB);
+ if (resv)
+ va = phys_to_virt(pa);
+ else
+ va = memremap(pa, LPI_PROPBASE_SZ, MEMREMAP_WB);
gic_rdists->prop_table_pa = pa;
gic_rdists->prop_table_va = va;
} else {
@@ -1685,7 +1736,10 @@ static int __init its_setup_lpi_prop_table(void)
lpi_id_bits = min_t(u32,
GICD_TYPER_ID_BITS(gic_rdists->gicd_typer),
ITS_MAX_LPI_NRBITS);
- page = its_allocate_prop_table(GFP_NOWAIT);
+ if (resv)
+ page = get_of_page(resv, LPI_PROPBASE_SZ);
+ else
+ page = its_allocate_prop_table(GFP_NOWAIT);
if (!page) {
pr_err("Failed to allocate PROPBASE\n");
return -ENOMEM;
@@ -2009,7 +2063,8 @@ static void its_free_pending_table(struct page *pt)
/*
* Booting with kdump and LPIs enabled is generally fine. Any other
- * case is wrong in the absence of firmware/EFI support.
+ * case is wrong in the absence of firmware/EFI support or reserve-memory
+ * in device tree for interrupt controller.
*/
static bool enabled_lpis_allowed(void)
{
@@ -2023,7 +2078,7 @@ static bool enabled_lpis_allowed(void)
return gic_check_reserved_range(addr, LPI_PROPBASE_SZ);
}
-static int __init allocate_lpi_tables(void)
+static int __init allocate_lpi_tables(struct of_resv *resv)
{
u64 val;
int err, cpu;
@@ -2039,7 +2094,7 @@ static int __init allocate_lpi_tables(void)
pr_info("GICv3: Using preallocated redistributor tables\n");
}
- err = its_setup_lpi_prop_table();
+ err = its_setup_lpi_prop_table(resv);
if (err)
return err;
@@ -2051,7 +2106,10 @@ static int __init allocate_lpi_tables(void)
for_each_possible_cpu(cpu) {
struct page *pend_page;
- pend_page = its_allocate_pending_table(GFP_NOWAIT);
+ if (resv)
+ pend_page = get_of_page(resv, LPI_PENDBASE_SZ);
+ else
+ pend_page = its_allocate_pending_table(GFP_NOWAIT);
if (!pend_page) {
pr_err("Failed to allocate PENDBASE for CPU%d\n", cpu);
return -ENOMEM;
@@ -3957,16 +4015,20 @@ int __init its_init(struct fwnode_handle *handle, struct rdists *rdists,
struct irq_domain *parent_domain)
{
struct device_node *of_node;
+ struct of_resv resv_buf;
+ struct of_resv *resv = NULL;
struct its_node *its;
bool has_v4 = false;
int err;
its_parent = parent_domain;
of_node = to_of_node(handle);
- if (of_node)
+ if (of_node) {
its_of_probe(of_node);
- else
+ its_of_mem_region(of_node, &resv, &resv_buf);
+ } else {
its_acpi_probe();
+ }
if (list_empty(&its_nodes)) {
pr_warn("ITS: No ITS available, not enabling LPIs\n");
@@ -3975,7 +4037,7 @@ int __init its_init(struct fwnode_handle *handle, struct rdists *rdists,
gic_rdists = rdists;
- err = allocate_lpi_tables();
+ err = allocate_lpi_tables(resv);
if (err)
return err;
--
2.23.0
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* Re: [PATCH v1 0/6] Allow kexec reboot for GICv3 and device tree
From: Marc Zyngier @ 2019-08-26 19:13 UTC (permalink / raw)
To: Pavel Tatashin
Cc: sashal, mark.rutland, vladimir.murzin, kexec, jmorris,
linux-kernel, james.morse, linux-arm-kernel
In-Reply-To: <20190826190056.27854-1-pasha.tatashin@soleen.com>
On Mon, 26 Aug 2019 15:00:50 -0400
Pavel Tatashin <pasha.tatashin@soleen.com> wrote:
> Marc Zyngier added the support for kexec and GICv3 for EFI based systems.
> However, it is still not possible todo on systems with device trees.
>
> Here is EFI fixes from Marc:
> https://lore.kernel.org/lkml/20180921195954.21574-1-marc.zyngier@arm.com
>
> For Device Tree variant: lets allow reserve a memory region in interrupt
> controller node, and use this property to allocate interrupt tables.
There is no such thing as a "device tree variant". As long as your
bootloader implements EFI, everything will work correctly, whether
you're using DT, ACPI, or the anything else.
This already works today, without any need to add anything to the
kernel (I have systems using EDK II and u-boot, both implementing EFI,
and I'm able to kexec without any issue). If your bootloader doesn't
support EFI, here's a good opportunity to implement it!
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
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^ permalink raw reply
* Re: [PATCH v3 00/15] Improvements and fixes for mxsfb DRM driver
From: Leonard Crestez @ 2019-08-26 19:19 UTC (permalink / raw)
To: Stefan Agner, Robert Chiras
Cc: Marek Vasut, Mark Rutland, Pengutronix Kernel Team,
devicetree@vger.kernel.org, David Airlie, Fabio Estevam,
Guido Günther, linux-kernel@vger.kernel.org,
dri-devel@lists.freedesktop.org, Rob Herring, dl-linux-imx,
Daniel Vetter, Shawn Guo, Sascha Hauer,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <3bd35686e046048d35cd4987567a13cf@agner.ch>
On 26.08.2019 17:35, Stefan Agner wrote:
> On 2019-08-26 14:05, Guido Günther wrote:
>> Hi,
>> On Wed, Aug 21, 2019 at 01:15:40PM +0300, Robert Chiras wrote:
>>> This patch-set improves the use of eLCDIF block on iMX 8 SoCs (like 8MQ, 8MM
>>> and 8QXP). Following, are the new features added and fixes from this
>>> patch-set:
>>
>> I've applied this whole series on top of my NWL work and it looks good
>> with a DSI panel. Applying the whole series also fixes an issue where
>> after unblank the output was sometimes shifted about half a screen width
>> to the right (which didn't happen with DCSS). So at least from the parts
>> I could test:
>>
>> Tested-by: Guido Günther <agx@sigxcpu.org>
>>
>> for the whole thing.
>
> Thanks for testing! What SoC did you use? I think it would be good to
> also give this a try on i.MX 7 or i.MX 6ULL before merging.
I did a quick test on imx6sx-sdb and it seems that [PATCH 07/15]
"drm/mxsfb: Fix the vblank events" causes a hang on boot, even without a
panel.
If I revert that particular patch it seems to be fine: the new pixel
formats seem to work in modetest (checked with sii,43wvf1g panel).
--
Regards,
Leonard
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^ permalink raw reply
* Re: [RFC PATCH 0/7] Unify SMP stop generic logic to common code
From: Cristian Marussi @ 2019-08-26 19:33 UTC (permalink / raw)
To: Christoph Hellwig
Cc: linux-arch, mark.rutland, peterz, catalin.marinas, linux-kernel,
takahiro.akashi, james.morse, hidehiro.kawai.ez, tglx, will,
dave.martin, linux-arm-kernel
In-Reply-To: <20190826153401.GB9591@infradead.org>
Hi Christoph
thanks for the review.
On 8/26/19 4:34 PM, Christoph Hellwig wrote:
> On Fri, Aug 23, 2019 at 12:57:13PM +0100, Cristian Marussi wrote:
>> An architecture willing to rely on this SMP common logic has to define its
>> own helpers and set CONFIG_ARCH_USE_COMMON_SMP_STOP=y.
>> The series wire this up for arm64.
>>
>> Behaviour is not changed for architectures not adopting this new common
>> logic.
>
> Seens like this common code only covers arm64. I think we should
> generally have at least two users for common code.
>
Yes absolutely, but this RFC was an attempt at first to explore if this
approach was deemed sensible upstream or not, so I wired up only arm64 for now.
Thanks
Cristian
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^ permalink raw reply
* [PATCH v2 0/3] coresight: Add barrier packet when moving offset forward
From: Mathieu Poirier @ 2019-08-26 19:46 UTC (permalink / raw)
To: suzuki.poulose, leo.yan, mike.leach
Cc: alexander.shishkin, yabinc, linux-kernel, linux-arm-kernel
This set builds on top of an original patch by Yabin Cui[1] that deals with
cases where the ETR buffer it bigger than the space available in the perf
ring buffer. The work herein complements Yabin's by inserting barrier
packets after the head of the memory buffer has been moved forward in order
for the trace decoder to still synchronise with the trace stream.
Applies cleanly to the coresight next branch.
Thanks,
Mathieu
[1]. https://lkml.org/lkml/2019/8/14/1336
New to V2:
- Added Yabin's Tested-by.
- Addressed Leo's comment about extending the solution to the sysfs
interface.
- Split the work in 3 patches rather than 2.
Mathieu Poirier (3):
coresight: tmc: Make memory width mask computation into a function
coresight: tmc-etr: Decouple buffer sync and barrier packet insertion
coresight: tmc-etr: Add barrier packets when moving offset forward
.../hwtracing/coresight/coresight-tmc-etf.c | 23 +--------
.../hwtracing/coresight/coresight-tmc-etr.c | 47 ++++++++++++++-----
drivers/hwtracing/coresight/coresight-tmc.c | 28 +++++++++++
drivers/hwtracing/coresight/coresight-tmc.h | 1 +
4 files changed, 67 insertions(+), 32 deletions(-)
--
2.17.1
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^ permalink raw reply
* [PATCH v2 1/3] coresight: tmc: Make memory width mask computation into a function
From: Mathieu Poirier @ 2019-08-26 19:46 UTC (permalink / raw)
To: suzuki.poulose, leo.yan, mike.leach
Cc: alexander.shishkin, yabinc, linux-kernel, linux-arm-kernel
In-Reply-To: <20190826194605.3791-1-mathieu.poirier@linaro.org>
Make the computation of a memory mask representing the width of the memory
bus into a function so that it can be re-used by the ETR driver.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
.../hwtracing/coresight/coresight-tmc-etf.c | 23 ++-------------
drivers/hwtracing/coresight/coresight-tmc.c | 28 +++++++++++++++++++
drivers/hwtracing/coresight/coresight-tmc.h | 1 +
3 files changed, 31 insertions(+), 21 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c
index 23b7ff00af5c..807416b75ecc 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etf.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c
@@ -479,30 +479,11 @@ static unsigned long tmc_update_etf_buffer(struct coresight_device *csdev,
* traces.
*/
if (!buf->snapshot && to_read > handle->size) {
- u32 mask = 0;
-
- /*
- * The value written to RRP must be byte-address aligned to
- * the width of the trace memory databus _and_ to a frame
- * boundary (16 byte), whichever is the biggest. For example,
- * for 32-bit, 64-bit and 128-bit wide trace memory, the four
- * LSBs must be 0s. For 256-bit wide trace memory, the five
- * LSBs must be 0s.
- */
- switch (drvdata->memwidth) {
- case TMC_MEM_INTF_WIDTH_32BITS:
- case TMC_MEM_INTF_WIDTH_64BITS:
- case TMC_MEM_INTF_WIDTH_128BITS:
- mask = GENMASK(31, 4);
- break;
- case TMC_MEM_INTF_WIDTH_256BITS:
- mask = GENMASK(31, 5);
- break;
- }
+ u32 mask = tmc_get_memwidth_mask(drvdata);
/*
* Make sure the new size is aligned in accordance with the
- * requirement explained above.
+ * requirement explained in function tmc_get_memwidth_mask().
*/
to_read = handle->size & mask;
/* Move the RAM read pointer up */
diff --git a/drivers/hwtracing/coresight/coresight-tmc.c b/drivers/hwtracing/coresight/coresight-tmc.c
index 3055bf8e2236..1cf82fa58289 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.c
+++ b/drivers/hwtracing/coresight/coresight-tmc.c
@@ -70,6 +70,34 @@ void tmc_disable_hw(struct tmc_drvdata *drvdata)
writel_relaxed(0x0, drvdata->base + TMC_CTL);
}
+u32 tmc_get_memwidth_mask(struct tmc_drvdata *drvdata)
+{
+ u32 mask = 0;
+
+ /*
+ * When moving RRP or an offset address forward, the new values must
+ * be byte-address aligned to the width of the trace memory databus
+ * _and_ to a frame boundary (16 byte), whichever is the biggest. For
+ * example, for 32-bit, 64-bit and 128-bit wide trace memory, the four
+ * LSBs must be 0s. For 256-bit wide trace memory, the five LSBs must
+ * be 0s.
+ */
+ switch (drvdata->memwidth) {
+ case TMC_MEM_INTF_WIDTH_32BITS:
+ /* fallthrough */
+ case TMC_MEM_INTF_WIDTH_64BITS:
+ /* fallthrough */
+ case TMC_MEM_INTF_WIDTH_128BITS:
+ mask = GENMASK(31, 4);
+ break;
+ case TMC_MEM_INTF_WIDTH_256BITS:
+ mask = GENMASK(31, 5);
+ break;
+ }
+
+ return mask;
+}
+
static int tmc_read_prepare(struct tmc_drvdata *drvdata)
{
int ret = 0;
diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
index 9dbcdf453e22..71de978575f3 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.h
+++ b/drivers/hwtracing/coresight/coresight-tmc.h
@@ -255,6 +255,7 @@ void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata);
void tmc_flush_and_stop(struct tmc_drvdata *drvdata);
void tmc_enable_hw(struct tmc_drvdata *drvdata);
void tmc_disable_hw(struct tmc_drvdata *drvdata);
+u32 tmc_get_memwidth_mask(struct tmc_drvdata *drvdata);
/* ETB/ETF functions */
int tmc_read_prepare_etb(struct tmc_drvdata *drvdata);
--
2.17.1
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^ permalink raw reply related
* [PATCH v2 2/3] coresight: tmc-etr: Decouple buffer sync and barrier packet insertion
From: Mathieu Poirier @ 2019-08-26 19:46 UTC (permalink / raw)
To: suzuki.poulose, leo.yan, mike.leach
Cc: alexander.shishkin, yabinc, linux-kernel, linux-arm-kernel
In-Reply-To: <20190826194605.3791-1-mathieu.poirier@linaro.org>
If less space is available in the perf ring buffer than the ETR buffer,
barrier packets inserted in the trace stream by tmc_sync_etr_buf() are
skipped over when the head of the buffer is moved forward, resulting in
traces that can't be decoded.
This patch decouples the process of syncing ETR buffers and the addition
of barrier packets in order to perform the latter once the offset in the
trace buffer has been properly computed.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
.../hwtracing/coresight/coresight-tmc-etr.c | 18 ++++++++++++------
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index 4f000a03152e..bae47272de98 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -946,10 +946,6 @@ static void tmc_sync_etr_buf(struct tmc_drvdata *drvdata)
WARN_ON(!etr_buf->ops || !etr_buf->ops->sync);
etr_buf->ops->sync(etr_buf, rrp, rwp);
-
- /* Insert barrier packets at the beginning, if there was an overflow */
- if (etr_buf->full)
- tmc_etr_buf_insert_barrier_packet(etr_buf, etr_buf->offset);
}
static void __tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
@@ -1086,6 +1082,13 @@ static void tmc_etr_sync_sysfs_buf(struct tmc_drvdata *drvdata)
drvdata->sysfs_buf = NULL;
} else {
tmc_sync_etr_buf(drvdata);
+ /*
+ * Insert barrier packets at the beginning, if there was
+ * an overflow.
+ */
+ if (etr_buf->full)
+ tmc_etr_buf_insert_barrier_packet(etr_buf,
+ etr_buf->offset);
}
}
@@ -1502,11 +1505,16 @@ tmc_update_etr_buffer(struct coresight_device *csdev,
CS_LOCK(drvdata->base);
spin_unlock_irqrestore(&drvdata->spinlock, flags);
+ lost = etr_buf->full;
size = etr_buf->len;
if (!etr_perf->snapshot && size > handle->size) {
size = handle->size;
lost = true;
}
+
+ /* Insert barrier packets at the beginning, if there was an overflow */
+ if (lost)
+ tmc_etr_buf_insert_barrier_packet(etr_buf, etr_buf->offset);
tmc_etr_sync_perf_buffer(etr_perf, size);
/*
@@ -1517,8 +1525,6 @@ tmc_update_etr_buffer(struct coresight_device *csdev,
*/
if (etr_perf->snapshot)
handle->head += size;
-
- lost |= etr_buf->full;
out:
/*
* Don't set the TRUNCATED flag in snapshot mode because 1) the
--
2.17.1
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^ permalink raw reply related
* [PATCH v2 3/3] coresight: tmc-etr: Add barrier packets when moving offset forward
From: Mathieu Poirier @ 2019-08-26 19:46 UTC (permalink / raw)
To: suzuki.poulose, leo.yan, mike.leach
Cc: alexander.shishkin, yabinc, linux-kernel, linux-arm-kernel
In-Reply-To: <20190826194605.3791-1-mathieu.poirier@linaro.org>
This patch adds barrier packets in the trace stream when the offset in the
data buffer needs to be moved forward. Otherwise the decoder isn't aware
of the break in the stream and can't synchronise itself with the trace
data.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Tested-by: Yabin Cui <yabinc@google.com>
---
.../hwtracing/coresight/coresight-tmc-etr.c | 29 +++++++++++++++----
1 file changed, 24 insertions(+), 5 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index bae47272de98..625882bc8b08 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -1418,10 +1418,11 @@ static void tmc_free_etr_buffer(void *config)
* buffer to the perf ring buffer.
*/
static void tmc_etr_sync_perf_buffer(struct etr_perf_buffer *etr_perf,
+ unsigned long src_offset,
unsigned long to_copy)
{
long bytes;
- long pg_idx, pg_offset, src_offset;
+ long pg_idx, pg_offset;
unsigned long head = etr_perf->head;
char **dst_pages, *src_buf;
struct etr_buf *etr_buf = etr_perf->etr_buf;
@@ -1430,7 +1431,6 @@ static void tmc_etr_sync_perf_buffer(struct etr_perf_buffer *etr_perf,
pg_idx = head >> PAGE_SHIFT;
pg_offset = head & (PAGE_SIZE - 1);
dst_pages = (char **)etr_perf->pages;
- src_offset = etr_buf->offset + etr_buf->len - to_copy;
while (to_copy > 0) {
/*
@@ -1478,7 +1478,7 @@ tmc_update_etr_buffer(struct coresight_device *csdev,
void *config)
{
bool lost = false;
- unsigned long flags, size = 0;
+ unsigned long flags, offset, size = 0;
struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
struct etr_perf_buffer *etr_perf = config;
struct etr_buf *etr_buf = etr_perf->etr_buf;
@@ -1506,16 +1506,35 @@ tmc_update_etr_buffer(struct coresight_device *csdev,
spin_unlock_irqrestore(&drvdata->spinlock, flags);
lost = etr_buf->full;
+ offset = etr_buf->offset;
size = etr_buf->len;
+
+ /*
+ * The ETR buffer may be bigger than the space available in the
+ * perf ring buffer (handle->size). If so advance the offset so that we
+ * get the latest trace data. In snapshot mode none of that matters
+ * since we are expected to clobber stale data in favour of the latest
+ * traces.
+ */
if (!etr_perf->snapshot && size > handle->size) {
- size = handle->size;
+ u32 mask = tmc_get_memwidth_mask(drvdata);
+
+ /*
+ * Make sure the new size is aligned in accordance with the
+ * requirement explained in function tmc_get_memwidth_mask().
+ */
+ size = handle->size & mask;
+ offset = etr_buf->offset + etr_buf->len - size;
+
+ if (offset >= etr_buf->size)
+ offset -= etr_buf->size;
lost = true;
}
/* Insert barrier packets at the beginning, if there was an overflow */
if (lost)
tmc_etr_buf_insert_barrier_packet(etr_buf, etr_buf->offset);
- tmc_etr_sync_perf_buffer(etr_perf, size);
+ tmc_etr_sync_perf_buffer(etr_perf, offset, size);
/*
* In snapshot mode we simply increment the head by the number of byte
--
2.17.1
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^ permalink raw reply related
* Re: [RFC PATCH 5/7] arm64: smp: use generic SMP stop common code
From: Cristian Marussi @ 2019-08-26 19:58 UTC (permalink / raw)
To: Christoph Hellwig
Cc: linux-arch, mark.rutland, peterz, catalin.marinas, linux-kernel,
takahiro.akashi, james.morse, hidehiro.kawai.ez, tglx, will,
dave.martin, linux-arm-kernel
In-Reply-To: <20190826153236.GA9591@infradead.org>
Hi
On 8/26/19 4:32 PM, Christoph Hellwig wrote:
>> +config ARCH_USE_COMMON_SMP_STOP
>> + def_bool y if SMP
>
> The option belongs into common code and the arch code shoud only
> select it.
>
In fact that was my first approach, but then I noticed that in kernel/ topdir
there was no generic Kconfig but only subsystem specific ones:
Kconfig.freezer Kconfig.hz Kconfig.locks Kconfig.preempt
while instead looking into archs top level Kconfig, beside the usual arch/Kconfig selects,
I could find this similar sort of "reversed" approach in which the arch defined and
selected a CONFIG which was indeed then used only in common code like in:
20:37 $ egrep -R ARCH_HAS_CACHE_LINE_SIZE .
./arch/arc/Kconfig:config ARCH_HAS_CACHE_LINE_SIZE
./arch/x86/Kconfig:config ARCH_HAS_CACHE_LINE_SIZE
./arch/arm64/Kconfig:config ARCH_HAS_CACHE_LINE_SIZE
./include/linux/cache.h:#ifndef CONFIG_ARCH_HAS_CACHE_LINE_SIZE
20:39 $ egrep -R ARCH_HAS_KEXEC_PURGATORY .
./arch/powerpc/Kconfig:config ARCH_HAS_KEXEC_PURGATORY
./arch/x86/Kconfig:config ARCH_HAS_KEXEC_PURGATORY
./arch/s390/Kconfig:config ARCH_HAS_KEXEC_PURGATORY
./arch/s390/purgatory/Makefile:obj-$(CONFIG_ARCH_HAS_KEXEC_PURGATORY) += kexec-purgatory.o
./arch/s390/Kbuild:obj-$(CONFIG_ARCH_HAS_KEXEC_PURGATORY) += purgatory/
./kernel/kexec_file.c: if (!IS_ENABLED(CONFIG_ARCH_HAS_KEXEC_PURGATORY))
so I thought it was an acceptable option and I went for it, not to introduce a new kernel/Kconfig.smp
just for this new config option; but in fact I could have missed the real reason underlying these two
different choices.
Thanks
Cristian
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^ permalink raw reply
* [PATCH v2] soc: xilinx: Set CAP_UNUSABLE requirement for versal while powering down domain
From: Jolly Shah @ 2019-08-26 20:30 UTC (permalink / raw)
To: matthias.bgg, andy.gross, shawnguo, geert+renesas,
bjorn.andersson, sean.wang, m.szyprowski, michal.simek
Cc: Tejas Patel, Jolly Shah, rajanv, linux-kernel, linux-arm-kernel
From: Tejas Patel <tejas.patel@xilinx.com>
For "0" requirement which is used to inform firmware that device is
not required currently by master, Versal PLM (Platform Loader and
Manager) which runs on Platform Management Controller and is responsible
platform management of devices that disables clock, power it down
and reset the device. genpd_power_off() is being called during runtime
suspend also. So, if any device goes to runtime suspend state during
resumes it needs to be re-initialized again. It is possible that
drivers do not reinitialize device upon resume from runtime suspend
every time ans so dont want it to be powered down or get reset
during runtime suspend.
In Versal PLM new PM_CAP_UNUSABLE capability is added, which disables
clock only and avoids power down and reset during runtime suspend. Power
and reset will be gated with core suspend.So, this patch sets
CAPABILITY_UNUSABLE requirement during gpd_power_off()
if platform is other than zynqmp.
Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
---
drivers/soc/xilinx/zynqmp_pm_domains.c | 10 ++++++++--
include/linux/firmware/xlnx-zynqmp.h | 3 ++-
2 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/soc/xilinx/zynqmp_pm_domains.c b/drivers/soc/xilinx/zynqmp_pm_domains.c
index 600f57c..23d90cb 100644
--- a/drivers/soc/xilinx/zynqmp_pm_domains.c
+++ b/drivers/soc/xilinx/zynqmp_pm_domains.c
@@ -2,7 +2,7 @@
/*
* ZynqMP Generic PM domain support
*
- * Copyright (C) 2015-2018 Xilinx, Inc.
+ * Copyright (C) 2015-2019 Xilinx, Inc.
*
* Davorin Mista <davorin.mista@aggios.com>
* Jolly Shah <jollys@xilinx.com>
@@ -25,6 +25,8 @@
static const struct zynqmp_eemi_ops *eemi_ops;
+static int min_capability;
+
/**
* struct zynqmp_pm_domain - Wrapper around struct generic_pm_domain
* @gpd: Generic power domain
@@ -106,7 +108,7 @@ static int zynqmp_gpd_power_off(struct generic_pm_domain *domain)
int ret;
struct pm_domain_data *pdd, *tmp;
struct zynqmp_pm_domain *pd;
- u32 capabilities = 0;
+ u32 capabilities = min_capability;
bool may_wakeup;
if (!eemi_ops->set_requirement)
@@ -283,6 +285,10 @@ static int zynqmp_gpd_probe(struct platform_device *pdev)
if (!domains)
return -ENOMEM;
+ if (!of_device_is_compatible(dev->parent->of_node,
+ "xlnx,zynqmp-firmware"))
+ min_capability = ZYNQMP_PM_CAPABILITY_UNUSABLE;
+
for (i = 0; i < ZYNQMP_NUM_DOMAINS; i++, pd++) {
pd->node_id = 0;
pd->gpd.name = kasprintf(GFP_KERNEL, "domain%d", i);
diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
index 778abbb..b8a7c22 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -2,7 +2,7 @@
/*
* Xilinx Zynq MPSoC Firmware layer
*
- * Copyright (C) 2014-2018 Xilinx
+ * Copyright (C) 2014-2019 Xilinx
*
* Michal Simek <michal.simek@xilinx.com>
* Davorin Mista <davorin.mista@aggios.com>
@@ -46,6 +46,7 @@
#define ZYNQMP_PM_CAPABILITY_ACCESS 0x1U
#define ZYNQMP_PM_CAPABILITY_CONTEXT 0x2U
#define ZYNQMP_PM_CAPABILITY_WAKEUP 0x4U
+#define ZYNQMP_PM_CAPABILITY_UNUSABLE 0x8U
/*
* Firmware FPGA Manager flags
--
2.7.4
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^ permalink raw reply related
* Re: [PATCH RESEND v11 7/8] open: openat2(2) syscall
From: sbaugh @ 2019-08-26 19:50 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux-arch, sparclinux, linux-ia64, linux-parisc, linux-sh,
linux-api, linux-kernel, linux-mips, linuxppc-dev, linux-alpha,
linux-fsdevel, linux-arm-kernel
In-Reply-To: <20190820033406.29796-8-cyphar@cyphar.com>
Aleksa Sarai <cyphar@cyphar.com> writes:
> To this end, we introduce the openat2(2) syscall. It provides all of the
> features of openat(2) through the @how->flags argument, but also
> also provides a new @how->resolve argument which exposes RESOLVE_* flags
> that map to our new LOOKUP_* flags. It also eliminates the long-standing
> ugliness of variadic-open(2) by embedding it in a struct.
I don't like this usage of a structure in memory to pass arguments that
would fit in registers. This would be quite inconvenient for me as a
userspace developer.
Others have brought up issues with this: the issue of seccomp, and the
issue of mismatch between the userspace interface and the kernel
interface, are the most important for me. I want to add another,
admittedly somewhat niche, concern.
This interfaces requires a program to allocate memory (even on the
stack) just to pass arguments to the kernel which could be passed
without allocating that memory. That makes it more difficult and less
efficient to use this syscall in any case where memory is not so easily
allocatable: such as early program startup or assembly, where the stack
may be limited in size or not even available yet, or when injecting a
syscall while ptracing.
A struct-passing interface was needed for clone, since we ran out of
registers; but we have not run out of registers yet for openat, so it
would be nice to avoid this if we can. We can always expand later...
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^ permalink raw reply
* [PATCH 02/20] dt-bindings: timer: Convert Allwinner A10 Timer to a schema
From: Daniel Lezcano @ 2019-08-26 20:43 UTC (permalink / raw)
To: tglx
Cc: Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Maxime Ripard, linux-kernel, Chen-Yu Tsai, Rob Herring,
moderated list:ARM/Allwinner sunXi SoC support
In-Reply-To: <20190826204407.17759-1-daniel.lezcano@linaro.org>
From: Maxime Ripard <maxime.ripard@bootlin.com>
The older Allwinner SoCs have a Timer supported in Linux, with a matching
Device Tree binding.
While the original binding only mentions one interrupt, the timer actually
has 6 of them.
Now that we have the DT validation in place, let's convert the device tree
bindings for that controller over to a YAML schemas.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
.../timer/allwinner,sun4i-a10-timer.yaml | 76 +++++++++++++++++++
.../bindings/timer/allwinner,sun4i-timer.txt | 19 -----
2 files changed, 76 insertions(+), 19 deletions(-)
create mode 100644 Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml
delete mode 100644 Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt
diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml b/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml
new file mode 100644
index 000000000000..7292a424092c
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml
@@ -0,0 +1,76 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/allwinner,sun4i-a10-timer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Allwinner A10 Timer Device Tree Bindings
+
+maintainers:
+ - Chen-Yu Tsai <wens@csie.org>
+ - Maxime Ripard <maxime.ripard@bootlin.com>
+
+properties:
+ compatible:
+ enum:
+ - allwinner,sun4i-a10-timer
+ - allwinner,suniv-f1c100s-timer
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description:
+ List of timers interrupts
+
+ clocks:
+ maxItems: 1
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ items:
+ const: allwinner,sun4i-a10-timer
+
+ then:
+ properties:
+ interrupts:
+ minItems: 6
+ maxItems: 6
+
+ - if:
+ properties:
+ compatible:
+ items:
+ const: allwinner,suniv-f1c100s-timer
+
+ then:
+ properties:
+ interrupts:
+ minItems: 3
+ maxItems: 3
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ timer {
+ compatible = "allwinner,sun4i-a10-timer";
+ reg = <0x01c20c00 0x400>;
+ interrupts = <22>,
+ <23>,
+ <24>,
+ <25>,
+ <67>,
+ <68>;
+ clocks = <&osc>;
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt b/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt
deleted file mode 100644
index 3da9d515c03a..000000000000
--- a/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-Allwinner A1X SoCs Timer Controller
-
-Required properties:
-
-- compatible : should be one of the following:
- "allwinner,sun4i-a10-timer"
- "allwinner,suniv-f1c100s-timer"
-- reg : Specifies base physical address and size of the registers.
-- interrupts : The interrupt of the first timer
-- clocks: phandle to the source clock (usually a 24 MHz fixed clock)
-
-Example:
-
-timer {
- compatible = "allwinner,sun4i-a10-timer";
- reg = <0x01c20c00 0x400>;
- interrupts = <22>;
- clocks = <&osc>;
-};
--
2.17.1
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* [PATCH 03/20] dt-bindings: timer: Add missing compatibles
From: Daniel Lezcano @ 2019-08-26 20:43 UTC (permalink / raw)
To: tglx
Cc: Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Maxime Ripard, linux-kernel, Chen-Yu Tsai, Rob Herring,
moderated list:ARM/Allwinner sunXi SoC support
In-Reply-To: <20190826204407.17759-1-daniel.lezcano@linaro.org>
From: Maxime Ripard <maxime.ripard@bootlin.com>
Newer Allwinner SoCs have different number of interrupts, let's add
different compatibles for all of them to deal with this properly.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
.../timer/allwinner,sun4i-a10-timer.yaml | 26 +++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml b/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml
index 7292a424092c..20adc1c8e9cc 100644
--- a/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml
+++ b/Documentation/devicetree/bindings/timer/allwinner,sun4i-a10-timer.yaml
@@ -14,6 +14,8 @@ properties:
compatible:
enum:
- allwinner,sun4i-a10-timer
+ - allwinner,sun8i-a23-timer
+ - allwinner,sun8i-v3s-timer
- allwinner,suniv-f1c100s-timer
reg:
@@ -39,6 +41,30 @@ allOf:
minItems: 6
maxItems: 6
+ - if:
+ properties:
+ compatible:
+ items:
+ const: allwinner,sun8i-a23-timer
+
+ then:
+ properties:
+ interrupts:
+ minItems: 2
+ maxItems: 2
+
+ - if:
+ properties:
+ compatible:
+ items:
+ const: allwinner,sun8i-v3s-timer
+
+ then:
+ properties:
+ interrupts:
+ minItems: 3
+ maxItems: 3
+
- if:
properties:
compatible:
--
2.17.1
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* [PATCH 04/20] clocksource: sun4i: Add missing compatibles
From: Daniel Lezcano @ 2019-08-26 20:43 UTC (permalink / raw)
To: tglx
Cc: Maxime Ripard, Chen-Yu Tsai, linux-kernel,
moderated list:ARM/Allwinner sunXi SoC support
In-Reply-To: <20190826204407.17759-1-daniel.lezcano@linaro.org>
From: Maxime Ripard <maxime.ripard@bootlin.com>
Newer Allwinner SoCs have different number of interrupts, let's add
different compatibles for all of them to deal with this properly.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/clocksource/timer-sun4i.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/clocksource/timer-sun4i.c b/drivers/clocksource/timer-sun4i.c
index 65f38f6ca714..0ba8155b8287 100644
--- a/drivers/clocksource/timer-sun4i.c
+++ b/drivers/clocksource/timer-sun4i.c
@@ -219,5 +219,9 @@ static int __init sun4i_timer_init(struct device_node *node)
}
TIMER_OF_DECLARE(sun4i, "allwinner,sun4i-a10-timer",
sun4i_timer_init);
+TIMER_OF_DECLARE(sun8i_a23, "allwinner,sun8i-a23-timer",
+ sun4i_timer_init);
+TIMER_OF_DECLARE(sun8i_v3s, "allwinner,sun8i-v3s-timer",
+ sun4i_timer_init);
TIMER_OF_DECLARE(suniv, "allwinner,suniv-f1c100s-timer",
sun4i_timer_init);
--
2.17.1
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* [PATCH 05/20] dt-bindings: timer: Convert Allwinner A13 HSTimer to a schema
From: Daniel Lezcano @ 2019-08-26 20:43 UTC (permalink / raw)
To: tglx
Cc: Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Maxime Ripard, linux-kernel, Chen-Yu Tsai, Rob Herring,
moderated list:ARM/Allwinner sunXi SoC support
In-Reply-To: <20190826204407.17759-1-daniel.lezcano@linaro.org>
From: Maxime Ripard <maxime.ripard@bootlin.com>
The newer Allwinner SoCs have a High Speed Timer supported in Linux, with a
matching Device Tree binding.
Now that we have the DT validation in place, let's convert the device tree
bindings for that controller over to a YAML schemas.
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
.../timer/allwinner,sun5i-a13-hstimer.txt | 26 ------
.../timer/allwinner,sun5i-a13-hstimer.yaml | 79 +++++++++++++++++++
2 files changed, 79 insertions(+), 26 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt
create mode 100644 Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml
diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt
deleted file mode 100644
index 2c5c1be78360..000000000000
--- a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-Allwinner SoCs High Speed Timer Controller
-
-Required properties:
-
-- compatible : should be "allwinner,sun5i-a13-hstimer" or
- "allwinner,sun7i-a20-hstimer"
-- reg : Specifies base physical address and size of the registers.
-- interrupts : The interrupts of these timers (2 for the sun5i IP, 4 for the sun7i
- one)
-- clocks: phandle to the source clock (usually the AHB clock)
-
-Optional properties:
-- resets: phandle to a reset controller asserting the timer
-
-Example:
-
-timer@1c60000 {
- compatible = "allwinner,sun7i-a20-hstimer";
- reg = <0x01c60000 0x1000>;
- interrupts = <0 51 1>,
- <0 52 1>,
- <0 53 1>,
- <0 54 1>;
- clocks = <&ahb1_gates 19>;
- resets = <&ahb1rst 19>;
-};
diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml
new file mode 100644
index 000000000000..dfa0c41fd261
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/allwinner,sun5i-a13-hstimer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Allwinner A13 High-Speed Timer Device Tree Bindings
+
+maintainers:
+ - Chen-Yu Tsai <wens@csie.org>
+ - Maxime Ripard <maxime.ripard@bootlin.com>
+
+properties:
+ compatible:
+ oneOf:
+ - const: allwinner,sun5i-a13-hstimer
+ - const: allwinner,sun7i-a20-hstimer
+ - items:
+ - const: allwinner,sun6i-a31-hstimer
+ - const: allwinner,sun7i-a20-hstimer
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 2
+ maxItems: 4
+ items:
+ - description: Timer 0 Interrupt
+ - description: Timer 1 Interrupt
+ - description: Timer 2 Interrupt
+ - description: Timer 3 Interrupt
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+if:
+ properties:
+ compatible:
+ items:
+ const: allwinner,sun5i-a13-hstimer
+
+then:
+ properties:
+ interrupts:
+ minItems: 2
+ maxItems: 2
+
+else:
+ properties:
+ interrupts:
+ minItems: 4
+ maxItems: 4
+
+additionalProperties: false
+
+examples:
+ - |
+ timer@1c60000 {
+ compatible = "allwinner,sun7i-a20-hstimer";
+ reg = <0x01c60000 0x1000>;
+ interrupts = <0 51 1>,
+ <0 52 1>,
+ <0 53 1>,
+ <0 54 1>;
+ clocks = <&ahb1_gates 19>;
+ resets = <&ahb1rst 19>;
+ };
+
+...
--
2.17.1
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* [PATCH 06/20] clocksource/drivers/tcb_clksrc: Register delay timer
From: Daniel Lezcano @ 2019-08-26 20:43 UTC (permalink / raw)
To: tglx
Cc: Alexandre Belloni, Ludovic Desroches, linux-kernel,
moderated list:ARM/Microchip AT91 SoC support
In-Reply-To: <20190826204407.17759-1-daniel.lezcano@linaro.org>
From: Alexandre Belloni <alexandre.belloni@bootlin.com>
Implement and register delay timer to allow get_cycles() to work properly.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/clocksource/Kconfig | 2 +-
drivers/clocksource/timer-atmel-tcb.c | 18 ++++++++++++++++++
2 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 5e9317dc3d39..a642c23b2fba 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -429,7 +429,7 @@ config ATMEL_ST
config ATMEL_TCB_CLKSRC
bool "Atmel TC Block timer driver" if COMPILE_TEST
- depends on HAS_IOMEM
+ depends on ARM && HAS_IOMEM
select TIMER_OF if OF
help
Support for Timer Counter Blocks on Atmel SoCs.
diff --git a/drivers/clocksource/timer-atmel-tcb.c b/drivers/clocksource/timer-atmel-tcb.c
index 6ed31f9def7e..7427b07495a8 100644
--- a/drivers/clocksource/timer-atmel-tcb.c
+++ b/drivers/clocksource/timer-atmel-tcb.c
@@ -6,6 +6,7 @@
#include <linux/irq.h>
#include <linux/clk.h>
+#include <linux/delay.h>
#include <linux/err.h>
#include <linux/ioport.h>
#include <linux/io.h>
@@ -125,6 +126,18 @@ static u64 notrace tc_sched_clock_read32(void)
return tc_get_cycles32(&clksrc);
}
+static struct delay_timer tc_delay_timer;
+
+static unsigned long tc_delay_timer_read(void)
+{
+ return tc_get_cycles(&clksrc);
+}
+
+static unsigned long notrace tc_delay_timer_read32(void)
+{
+ return tc_get_cycles32(&clksrc);
+}
+
#ifdef CONFIG_GENERIC_CLOCKEVENTS
struct tc_clkevt_device {
@@ -432,6 +445,7 @@ static int __init tcb_clksrc_init(struct device_node *node)
/* setup ony channel 0 */
tcb_setup_single_chan(&tc, best_divisor_idx);
tc_sched_clock = tc_sched_clock_read32;
+ tc_delay_timer.read_current_timer = tc_delay_timer_read32;
} else {
/* we have three clocks no matter what the
* underlying platform supports.
@@ -444,6 +458,7 @@ static int __init tcb_clksrc_init(struct device_node *node)
/* setup both channel 0 & 1 */
tcb_setup_dual_chan(&tc, best_divisor_idx);
tc_sched_clock = tc_sched_clock_read;
+ tc_delay_timer.read_current_timer = tc_delay_timer_read;
}
/* and away we go! */
@@ -458,6 +473,9 @@ static int __init tcb_clksrc_init(struct device_node *node)
sched_clock_register(tc_sched_clock, 32, divided_rate);
+ tc_delay_timer.freq = divided_rate;
+ register_current_timer_delay(&tc_delay_timer);
+
return 0;
err_unregister_clksrc:
--
2.17.1
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* [PATCH 07/20] clocksource/drivers/imx-sysctr: Add internal clock divider handle
From: Daniel Lezcano @ 2019-08-26 20:43 UTC (permalink / raw)
To: tglx
Cc: Anson Huang, Shawn Guo, Sascha Hauer, linux-kernel,
NXP Linux Team, Pengutronix Kernel Team, Fabio Estevam,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
In-Reply-To: <20190826204407.17759-1-daniel.lezcano@linaro.org>
From: Anson Huang <Anson.Huang@nxp.com>
The system counter block guide states that the base clock is
internally divided by 3 before use, that means the clock input of
system counter defined in DT should be base clock which is normally
from OSC, and then internally divided by 3 before use.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
drivers/clocksource/timer-imx-sysctr.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/clocksource/timer-imx-sysctr.c b/drivers/clocksource/timer-imx-sysctr.c
index fd7d68066efb..b7c80a368a1b 100644
--- a/drivers/clocksource/timer-imx-sysctr.c
+++ b/drivers/clocksource/timer-imx-sysctr.c
@@ -20,6 +20,8 @@
#define SYS_CTR_EN 0x1
#define SYS_CTR_IRQ_MASK 0x2
+#define SYS_CTR_CLK_DIV 0x3
+
static void __iomem *sys_ctr_base;
static u32 cmpcr;
@@ -134,6 +136,9 @@ static int __init sysctr_timer_init(struct device_node *np)
if (ret)
return ret;
+ /* system counter clock is divided by 3 internally */
+ to_sysctr.of_clk.rate /= SYS_CTR_CLK_DIV;
+
sys_ctr_base = timer_of_base(&to_sysctr);
cmpcr = readl(sys_ctr_base + CMPCR);
cmpcr &= ~SYS_CTR_EN;
--
2.17.1
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* [PATCH 08/20] arm64: dts: imx8mm: Add system counter node
From: Daniel Lezcano @ 2019-08-26 20:43 UTC (permalink / raw)
To: tglx
Cc: Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Jacky Bai, Anson Huang, Fabio Estevam, Sascha Hauer, linux-kernel,
Daniel Baluta, Rob Herring, NXP Linux Team,
Pengutronix Kernel Team, Leonard Crestez, Shawn Guo,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
In-Reply-To: <20190826204407.17759-1-daniel.lezcano@linaro.org>
From: Anson Huang <Anson.Huang@nxp.com>
Add i.MX8MM system counter node to enable timer-imx-sysctr
broadcast timer driver.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 232a7412755a..89ef22a8f81e 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -510,6 +510,14 @@
#pwm-cells = <2>;
status = "disabled";
};
+
+ system_counter: timer@306a0000 {
+ compatible = "nxp,sysctr-timer";
+ reg = <0x306a0000 0x20000>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc_24m>;
+ clock-names = "per";
+ };
};
aips3: bus@30800000 {
--
2.17.1
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* [PATCH 09/20] arm64: dts: imx8mq: Add system counter node
From: Daniel Lezcano @ 2019-08-26 20:43 UTC (permalink / raw)
To: tglx
Cc: Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Abel Vesa, Anson Huang, Carlo Caione, Andrey Smirnov,
Fabio Estevam, Sascha Hauer, Angus Ainslie (Purism), linux-kernel,
Rob Herring, NXP Linux Team, Pengutronix Kernel Team, Shawn Guo,
Guido Günther,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
Lucas Stach
In-Reply-To: <20190826204407.17759-1-daniel.lezcano@linaro.org>
From: Anson Huang <Anson.Huang@nxp.com>
Add i.MX8MQ system counter node to enable timer-imx-sysctr
broadcast timer driver.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index d09b808eff87..b4529773af51 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -635,6 +635,14 @@
#pwm-cells = <2>;
status = "disabled";
};
+
+ system_counter: timer@306a0000 {
+ compatible = "nxp,sysctr-timer";
+ reg = <0x306a0000 0x20000>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&osc_25m>;
+ clock-names = "per";
+ };
};
bus@30800000 { /* AIPS3 */
--
2.17.1
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