* Re: [PATCH] PCI: Fix misspelled words.
From: Rob Herring @ 2019-08-27 16:53 UTC (permalink / raw)
To: Krzysztof Wilczynski
Cc: devicetree, Richard Zhu, Thomas Petazzoni, linux-pci,
Sascha Hauer, linux-kernel, Bjorn Helgaas, NXP Linux Team,
Pengutronix Kernel Team, Fabio Estevam, linux-arm-kernel,
Lucas Stach
In-Reply-To: <20190819115306.27338-1-kw@linux.com>
On Mon, 19 Aug 2019 13:53:06 +0200, Krzysztof Wilczynski wrote:
> Fix misspelled words in include/linux/pci.h, drivers/pci/Kconfig,
> and in the documentation for Freescale i.MX6 and Marvell Armada 7K/8K
> PCIe interfaces. No functional change intended.
>
> Related commit 96291d565550 ("PCI: Fix typos and whitespace errors").
>
> Signed-off-by: Krzysztof Wilczynski <kw@linux.com>
> ---
> Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt | 2 +-
> Documentation/devicetree/bindings/pci/pci-armada8k.txt | 2 +-
> drivers/pci/Kconfig | 2 +-
> include/linux/pci.h | 2 +-
> 4 files changed, 4 insertions(+), 4 deletions(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
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* [PATCH v3 1/4] vesnin: add wdt2 section with alt-boot option
From: Ivan Mikhaylov @ 2019-08-27 16:54 UTC (permalink / raw)
To: Guenter Roeck, Wim Van Sebroeck
Cc: Mark Rutland, devicetree, linux-watchdog, linux-aspeed,
Andrew Jeffery, openbmc, Alexander Amelkin, linux-kernel,
Rob Herring, Joel Stanley, Ivan Mikhaylov, linux-arm-kernel
In-Reply-To: <20190827165426.17037-1-i.mikhaylov@yadro.com>
Adds wdt2 section with 'alt-boot' option into dts for vesnin.
Signed-off-by: Ivan Mikhaylov <i.mikhaylov@yadro.com>
---
arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts b/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts
index 0b9e29c3212e..2ee26c86a32e 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts
@@ -222,3 +222,7 @@
&vuart {
status = "okay";
};
+
+&wdt2 {
+ aspeed,alt-boot;
+};
--
2.20.1
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* [PATCH v3 2/4] vesnin: add secondary SPI flash chip
From: Ivan Mikhaylov @ 2019-08-27 16:54 UTC (permalink / raw)
To: Guenter Roeck, Wim Van Sebroeck
Cc: Mark Rutland, devicetree, linux-watchdog, linux-aspeed,
Andrew Jeffery, openbmc, Alexander Amelkin, linux-kernel,
Rob Herring, Joel Stanley, Ivan Mikhaylov, linux-arm-kernel
In-Reply-To: <20190827165426.17037-1-i.mikhaylov@yadro.com>
Adds secondary SPI flash chip into dts for vesnin.
Signed-off-by: Ivan Mikhaylov <i.mikhaylov@yadro.com>
---
arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts b/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts
index 2ee26c86a32e..db4cc3df61ce 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts
@@ -81,6 +81,14 @@
label = "bmc";
#include "openbmc-flash-layout.dtsi"
};
+
+ flash@1 {
+ status = "okay";
+ reg = < 1 >;
+ compatible = "jedec,spi-nor";
+ m25p,fast-read;
+ label = "alt";
+ };
};
&spi {
--
2.20.1
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* [PATCH v3 0/4] add dual-boot support
From: Ivan Mikhaylov @ 2019-08-27 16:54 UTC (permalink / raw)
To: Guenter Roeck, Wim Van Sebroeck
Cc: Mark Rutland, devicetree, linux-watchdog, linux-aspeed,
Andrew Jeffery, openbmc, Alexander Amelkin, linux-kernel,
Rob Herring, Joel Stanley, Ivan Mikhaylov, linux-arm-kernel
ASPEED SoCs support dual-boot feature for SPI Flash.
When strapped appropriately, the SoC starts wdt2 (/dev/watchdog1)
and if within a minute it is not disabled, it goes off and reboots
the SoC from an alternate SPI Flash chip by changing CS0 controls
to actually drive CS1 line.
When booted from alternate chip, in order to access the main chip
at CS0, the user must reset the appropriate bit in the watchdog
hardware. There is no interface that would allow to do that from
an embedded firmware startup script.
This commit implements support for that feature:
* Enable 'alt-boot' option for wdt2
* Enable secondary SPI flash chip
* Make it possible to get access to the primary SPI flash chip at CS0
after booting from the alternate chip at CS1. A sysfs interface is added
to provide an easy way for embedded firmware startup scripts to clear
the chip select bit to gain access to the primary flash chip in order
to allow for recovery of its contents.
Ivan Mikhaylov (4):
vesnin: add wdt2 section with alt-boot option
vesnin: add secondary SPI flash chip
watchdog/aspeed: add support for dual boot
aspeed/watchdog: Add access_cs0 option for alt-boot
.../ABI/testing/sysfs-class-watchdog | 34 ++++++++++
arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts | 12 ++++
drivers/watchdog/aspeed_wdt.c | 65 ++++++++++++++++++-
3 files changed, 110 insertions(+), 1 deletion(-)
--
2.20.1
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* [PATCH v3 3/4] watchdog/aspeed: add support for dual boot
From: Ivan Mikhaylov @ 2019-08-27 16:54 UTC (permalink / raw)
To: Guenter Roeck, Wim Van Sebroeck
Cc: Mark Rutland, devicetree, linux-watchdog, linux-aspeed,
Andrew Jeffery, openbmc, Alexander Amelkin, linux-kernel,
Rob Herring, Joel Stanley, Ivan Mikhaylov, linux-arm-kernel
In-Reply-To: <20190827165426.17037-1-i.mikhaylov@yadro.com>
Set WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION into WDT_CLEAR_TIMEOUT_STATUS
to clear out boot code source and re-enable access to the primary SPI flash
chip while booted via wdt2 from the alternate chip.
AST2400 datasheet says:
"In the 2nd flash booting mode, all the address mapping to CS0# would be
re-directed to CS1#. And CS0# is not accessable under this mode. To access
CS0#, firmware should clear the 2nd boot mode register in the WDT2 status
register WDT30.bit[1]."
Signed-off-by: Ivan Mikhaylov <i.mikhaylov@yadro.com>
---
drivers/watchdog/aspeed_wdt.c | 65 ++++++++++++++++++++++++++++++++++-
1 file changed, 64 insertions(+), 1 deletion(-)
diff --git a/drivers/watchdog/aspeed_wdt.c b/drivers/watchdog/aspeed_wdt.c
index cc71861e033a..d27030d766ed 100644
--- a/drivers/watchdog/aspeed_wdt.c
+++ b/drivers/watchdog/aspeed_wdt.c
@@ -53,6 +53,8 @@ MODULE_DEVICE_TABLE(of, aspeed_wdt_of_table);
#define WDT_CTRL_ENABLE BIT(0)
#define WDT_TIMEOUT_STATUS 0x10
#define WDT_TIMEOUT_STATUS_BOOT_SECONDARY BIT(1)
+#define WDT_CLEAR_TIMEOUT_STATUS 0x14
+#define WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION BIT(0)
/*
* WDT_RESET_WIDTH controls the characteristics of the external pulse (if
@@ -165,6 +167,60 @@ static int aspeed_wdt_restart(struct watchdog_device *wdd,
return 0;
}
+/* access_cs0 shows if cs0 is accessible, hence the reverted bit */
+static ssize_t access_cs0_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct aspeed_wdt *wdt = dev_get_drvdata(dev);
+ uint32_t status = readl(wdt->base + WDT_TIMEOUT_STATUS);
+
+ return sprintf(buf, "%u\n",
+ !(status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY));
+}
+
+static ssize_t access_cs0_store(struct device *dev,
+ struct device_attribute *attr, const char *buf,
+ size_t size)
+{
+ struct aspeed_wdt *wdt = dev_get_drvdata(dev);
+ unsigned long val;
+
+ if (kstrtoul(buf, 10, &val))
+ return -EINVAL;
+
+ if (val)
+ writel(WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION,
+ wdt->base + WDT_CLEAR_TIMEOUT_STATUS);
+
+ return size;
+}
+
+/*
+ * This attribute exists only if the system has booted from the alternate
+ * flash with 'alt-boot' option.
+ *
+ * At alternate flash the 'access_cs0' sysfs node provides:
+ * ast2400: a way to get access to the primary SPI flash chip at CS0
+ * after booting from the alternate chip at CS1.
+ * ast2500: a way to restore the normal address mapping from
+ * (CS0->CS1, CS1->CS0) to (CS0->CS0, CS1->CS1).
+ *
+ * Clearing the boot code selection and timeout counter also resets to the
+ * initial state the chip select line mapping. When the SoC is in normal
+ * mapping state (i.e. booted from CS0), clearing those bits does nothing for
+ * both versions of the SoC. For alternate boot mode (booted from CS1 due to
+ * wdt2 expiration) the behavior differs as described above.
+ *
+ * This option can be used with wdt2 (watchdog1) only.
+ */
+static DEVICE_ATTR_RW(access_cs0);
+
+static struct attribute *bswitch_attrs[] = {
+ &dev_attr_access_cs0.attr,
+ NULL
+};
+ATTRIBUTE_GROUPS(bswitch);
+
static const struct watchdog_ops aspeed_wdt_ops = {
.start = aspeed_wdt_start,
.stop = aspeed_wdt_stop,
@@ -306,9 +362,16 @@ static int aspeed_wdt_probe(struct platform_device *pdev)
}
status = readl(wdt->base + WDT_TIMEOUT_STATUS);
- if (status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY)
+ if (status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY) {
wdt->wdd.bootstatus = WDIOF_CARDRESET;
+ if (of_device_is_compatible(np, "aspeed,ast2400-wdt") ||
+ of_device_is_compatible(np, "aspeed,ast2500-wdt"))
+ wdt->wdd.groups = bswitch_groups;
+ }
+
+ dev_set_drvdata(dev, wdt);
+
return devm_watchdog_register_device(dev, &wdt->wdd);
}
--
2.20.1
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* [PATCH v3 4/4] aspeed/watchdog: Add access_cs0 option for alt-boot
From: Ivan Mikhaylov @ 2019-08-27 16:54 UTC (permalink / raw)
To: Guenter Roeck, Wim Van Sebroeck
Cc: Mark Rutland, devicetree, linux-watchdog, linux-aspeed,
Andrew Jeffery, openbmc, Alexander Amelkin, linux-kernel,
Rob Herring, Joel Stanley, Ivan Mikhaylov, linux-arm-kernel
In-Reply-To: <20190827165426.17037-1-i.mikhaylov@yadro.com>
The option for the ast2400/2500 to get access to CS0 at runtime.
Signed-off-by: Ivan Mikhaylov <i.mikhaylov@yadro.com>
---
.../ABI/testing/sysfs-class-watchdog | 34 +++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/Documentation/ABI/testing/sysfs-class-watchdog b/Documentation/ABI/testing/sysfs-class-watchdog
index 6317ade5ad19..675f9b537661 100644
--- a/Documentation/ABI/testing/sysfs-class-watchdog
+++ b/Documentation/ABI/testing/sysfs-class-watchdog
@@ -72,3 +72,37 @@ Description:
It is a read/write file. When read, the currently assigned
pretimeout governor is returned. When written, it sets
the pretimeout governor.
+
+What: /sys/class/watchdog/watchdog1/access_cs0
+Date: August 2019
+Contact: Ivan Mikhaylov <i.mikhaylov@yadro.com>,
+ Alexander Amelkin <a.amelkin@yadro.com>
+Description:
+ It is a read/write file. This attribute exists only if the
+ system has booted from the alternate flash chip due to
+ expiration of a watchdog timer of AST2400/AST2500 when
+ alternate boot function was enabled with 'aspeed,alt-boot'
+ devicetree option for that watchdog or with an appropriate
+ h/w strapping (for WDT2 only).
+
+ At alternate flash the 'access_cs0' sysfs node provides:
+ ast2400: a way to get access to the primary SPI flash
+ chip at CS0 after booting from the alternate
+ chip at CS1.
+ ast2500: a way to restore the normal address mapping
+ from (CS0->CS1, CS1->CS0) to (CS0->CS0,
+ CS1->CS1).
+
+ Clearing the boot code selection and timeout counter also
+ resets to the initial state the chip select line mapping. When
+ the SoC is in normal mapping state (i.e. booted from CS0),
+ clearing those bits does nothing for both versions of the SoC.
+ For alternate boot mode (booted from CS1 due to wdt2
+ expiration) the behavior differs as described above.
+
+ This option can be used with wdt2 (watchdog1) only.
+
+ When read, the current status of the boot code selection is
+ shown. When written with any non-zero value, it clears
+ the boot code selection and the timeout counter, which results
+ in chipselect reset for AST2400/AST2500.
--
2.20.1
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* Re: [PATCH V4 01/11] dt-bindings: firmware: imx-scu: new binding to parse clocks from device tree
From: Rob Herring @ 2019-08-27 17:04 UTC (permalink / raw)
To: Dong Aisheng
Cc: Dong Aisheng, devicetree, sboyd, mturquette, linux-imx, kernel,
fabio.estevam, shawnguo, linux-clk, linux-arm-kernel
In-Reply-To: <1566299605-15641-2-git-send-email-aisheng.dong@nxp.com>
On Tue, 20 Aug 2019 07:13:15 -0400, Dong Aisheng wrote:
> There's a few limitations on the original one cell clock binding
> (#clock-cells = <1>) that we have to define some SW clock IDs for device
> tree to reference. This may cause troubles if we want to use common
> clock IDs for multi platforms support when the clock of those platforms
> are mostly the same.
> e.g. Current clock IDs name are defined with SS prefix.
>
> However the device may reside in different SS across CPUs, that means the
> SS prefix may not valid anymore for a new SoC. Furthermore, the device
> availability of those clocks may also vary a bit.
>
> For such situation, we want to eliminate the using of SW Clock IDs and
> change to use a more close to HW one instead.
> For SCU clocks usage, only two params required: Resource id + Clock Type.
> Both parameters are platform independent. So we could use two cells binding
> to pass those parameters,
>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Sascha Hauer <kernel@pengutronix.de>
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> ---
> ChangeLog:
> v3->v4:
> * add some comments for various clock types
> v2->v3:
> * Changed to two cells binding and register all clocks in driver
> instead of parse from device tree.
> v1->v2:
> * changed to one cell binding inspired by arm,scpi.txt
> Documentation/devicetree/bindings/arm/arm,scpi.txt
> Resource ID is encoded in 'reg' property.
> Clock type is encoded in generic clock-indices property.
> Then we don't have to search all the DT nodes to fetch
> those two value to construct clocks which is relatively
> low efficiency.
> * Add required power-domain property as well.
> ---
> .../devicetree/bindings/arm/freescale/fsl,scu.txt | 12 ++++++-----
> include/dt-bindings/firmware/imx/rsrc.h | 23 ++++++++++++++++++++++
> 2 files changed, 30 insertions(+), 5 deletions(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
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* [PATCH 3/3] i2c: bcm2835: Add full name of devicetree node to adapter name
From: Stefan Wahren @ 2019-08-27 17:04 UTC (permalink / raw)
To: Wolfram Sang, Eric Anholt, Florian Fainelli, Ray Jui,
Scott Branden
Cc: linux-i2c, linux-arm-kernel, Stefan Wahren
In-Reply-To: <1566925456-5928-1-git-send-email-wahrenst@gmx.net>
Inspired by Lori Hikichi's patch for iproc, this adds the full name of
the devicetree node to the adapter name. With the introduction of
BCM2711 it's very difficult to distinguish between the multiple instances.
Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
---
drivers/i2c/busses/i2c-bcm2835.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/i2c/busses/i2c-bcm2835.c b/drivers/i2c/busses/i2c-bcm2835.c
index ab5502f..e01b2b5 100644
--- a/drivers/i2c/busses/i2c-bcm2835.c
+++ b/drivers/i2c/busses/i2c-bcm2835.c
@@ -472,7 +472,8 @@ static int bcm2835_i2c_probe(struct platform_device *pdev)
i2c_set_adapdata(adap, i2c_dev);
adap->owner = THIS_MODULE;
adap->class = I2C_CLASS_DEPRECATED;
- strlcpy(adap->name, "bcm2835 I2C adapter", sizeof(adap->name));
+ snprintf(adap->name, sizeof(adap->name), "bcm2835 (%s)",
+ of_node_full_name(pdev->dev.of_node));
adap->algo = &bcm2835_i2c_algo;
adap->dev.parent = &pdev->dev;
adap->dev.of_node = pdev->dev.of_node;
--
2.7.4
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* [PATCH 1/3] dt-bindings: i2c: bcm2835: Add brcm,bcm2711 compatible
From: Stefan Wahren @ 2019-08-27 17:04 UTC (permalink / raw)
To: Wolfram Sang, Eric Anholt, Florian Fainelli, Ray Jui,
Scott Branden
Cc: linux-i2c, linux-arm-kernel, Stefan Wahren
In-Reply-To: <1566925456-5928-1-git-send-email-wahrenst@gmx.net>
Add a new compatible for the BCM2711, which hasn't the clock stretch bug.
Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/i2c/brcm,bcm2835-i2c.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/i2c/brcm,bcm2835-i2c.txt b/Documentation/devicetree/bindings/i2c/brcm,bcm2835-i2c.txt
index e9de375..c9a6587 100644
--- a/Documentation/devicetree/bindings/i2c/brcm,bcm2835-i2c.txt
+++ b/Documentation/devicetree/bindings/i2c/brcm,bcm2835-i2c.txt
@@ -1,7 +1,9 @@
Broadcom BCM2835 I2C controller
Required properties:
-- compatible : Should be "brcm,bcm2835-i2c".
+- compatible : Should be one of:
+ "brcm,bcm2711-i2c"
+ "brcm,bcm2835-i2c"
- reg: Should contain register location and length.
- interrupts: Should contain interrupt.
- clocks : The clock feeding the I2C controller.
--
2.7.4
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* [PATCH 0/3] i2c: bcm2835: Add bcm2711 support
From: Stefan Wahren @ 2019-08-27 17:04 UTC (permalink / raw)
To: Wolfram Sang, Eric Anholt, Florian Fainelli, Ray Jui,
Scott Branden
Cc: linux-i2c, linux-arm-kernel, Stefan Wahren
This series has been split out of the recent Raspberry Pi 4 support
series [1]. I hope patch 1 and 2 have a chance to get into Linux 5.4.
Changes since split:
- add Rob's and Eric's Reviewed-by
- address Wolfram's comment regarding of_device_get_match_data
- add patch to distinguish the many interfaces on bcm2711
[1] - https://marc.info/?linux-arm-kernel&m=3D156571347332483
Stefan Wahren (3):
dt-bindings: i2c: bcm2835: Add brcm,bcm2711 compatible
i2c: bcm2835: Avoid clk stretch quirk for BCM2711
i2c: bcm2835: Add full name of devicetree node to adapter name
Documentation/devicetree/bindings/i2c/brcm,bcm2835-i2c.txt | 4 +++-
drivers/i2c/busses/i2c-bcm2835.c | 11 +++++++----
2 files changed, 10 insertions(+), 5 deletions(-)
--
2.7.4
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* [PATCH 2/3] i2c: bcm2835: Avoid clk stretch quirk for BCM2711
From: Stefan Wahren @ 2019-08-27 17:04 UTC (permalink / raw)
To: Wolfram Sang, Eric Anholt, Florian Fainelli, Ray Jui,
Scott Branden
Cc: linux-i2c, linux-arm-kernel, Stefan Wahren
In-Reply-To: <1566925456-5928-1-git-send-email-wahrenst@gmx.net>
The I2C block on the BCM2711 isn't affected by the clk stretching bug.
So there is no need to apply the corresponding quirk.
Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
---
drivers/i2c/busses/i2c-bcm2835.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/i2c/busses/i2c-bcm2835.c b/drivers/i2c/busses/i2c-bcm2835.c
index 67752f7..ab5502f 100644
--- a/drivers/i2c/busses/i2c-bcm2835.c
+++ b/drivers/i2c/busses/i2c-bcm2835.c
@@ -12,6 +12,7 @@
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
+#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
@@ -389,7 +390,7 @@ static const struct i2c_algorithm bcm2835_i2c_algo = {
};
/*
- * This HW was reported to have problems with clock stretching:
+ * The BCM2835 was reported to have problems with clock stretching:
* http://www.advamation.com/knowhow/raspberrypi/rpi-i2c-bug.html
* https://www.raspberrypi.org/forums/viewtopic.php?p=146272
*/
@@ -475,7 +476,7 @@ static int bcm2835_i2c_probe(struct platform_device *pdev)
adap->algo = &bcm2835_i2c_algo;
adap->dev.parent = &pdev->dev;
adap->dev.of_node = pdev->dev.of_node;
- adap->quirks = &bcm2835_i2c_quirks;
+ adap->quirks = of_device_get_match_data(&pdev->dev);
bcm2835_i2c_writel(i2c_dev, BCM2835_I2C_C, 0);
@@ -501,7 +502,8 @@ static int bcm2835_i2c_remove(struct platform_device *pdev)
}
static const struct of_device_id bcm2835_i2c_of_match[] = {
- { .compatible = "brcm,bcm2835-i2c" },
+ { .compatible = "brcm,bcm2711-i2c" },
+ { .compatible = "brcm,bcm2835-i2c", .data = &bcm2835_i2c_quirks },
{},
};
MODULE_DEVICE_TABLE(of, bcm2835_i2c_of_match);
--
2.7.4
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^ permalink raw reply related
* Re: [PATCH V4 02/11] dt-bindings: clock: imx-lpcg: add support to parse clocks from device tree
From: Rob Herring @ 2019-08-27 17:05 UTC (permalink / raw)
To: Dong Aisheng
Cc: Dong Aisheng, devicetree, sboyd, mturquette, linux-imx, kernel,
fabio.estevam, shawnguo, linux-clk, linux-arm-kernel
In-Reply-To: <1566299605-15641-3-git-send-email-aisheng.dong@nxp.com>
On Tue, 20 Aug 2019 07:13:16 -0400, Dong Aisheng wrote:
> MX8QM and MX8QXP LPCG Clocks are mostly the same except they may reside
> in different subsystems across CPUs and also vary a bit on the availability.
>
> Same as SCU clock, we want to move the clock definition into device tree
> which can fully decouple the dependency of Clock ID definition from device
> tree and make us be able to write a fully generic lpcg clock driver.
>
> And we can also use the existence of clock nodes in device tree to address
> the device and clock availability differences across different SoCs.
>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Sascha Hauer <kernel@pengutronix.de>
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> ---
> ChangeLog:
> v3->v4:
> * change bit-offset property to clock-indices
> * use constant macro to define clock indinces
> * drop hw-autogate property which is still not used by drivers
> v2->v3:
> * no changes
> v1->v2:
> * Update example
> * Add power domain property
> ---
> .../devicetree/bindings/clock/imx8qxp-lpcg.txt | 36 ++++++++++++++++++----
> include/dt-bindings/clock/imx8-lpcg.h | 14 +++++++++
> 2 files changed, 44 insertions(+), 6 deletions(-)
> create mode 100644 include/dt-bindings/clock/imx8-lpcg.h
>
Reviewed-by: Rob Herring <robh@kernel.org>
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^ permalink raw reply
* [PATCH] arm64: KVM: Device mappings should be execute-never
From: James Morse @ 2019-08-27 17:06 UTC (permalink / raw)
To: linux-arm-kernel, kvmarm
Cc: Suzuki K Poulose, Catalin Marinas, James Morse, Marc Zyngier,
Will Deacon, Julien Thierry
Since commit 2f6ea23f63cca ("arm64: KVM: Avoid marking pages as XN in
Stage-2 if CTR_EL0.DIC is set"), KVM has stopped marking normal memory
as execute-never at stage2 when the system supports D->I Coherency at
the PoU. This avoids KVM taking a trap when the page is first executed,
in order to clean it to PoU.
The patch that added this change also wrapped PAGE_S2_DEVICE mappings
up in this too. The upshot is, if your CPU caches support DIC ...
you can execute devices.
Revert the PAGE_S2_DEVICE change so PTE_S2_XN is always used
directly.
Fixes: 2f6ea23f63cca ("arm64: KVM: Avoid marking pages as XN in Stage-2 if CTR_EL0.DIC is set")
Signed-off-by: James Morse <james.morse@arm.com>
---
arch/arm64/include/asm/pgtable-prot.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/pgtable-prot.h b/arch/arm64/include/asm/pgtable-prot.h
index 92d2e9f28f28..9a21b84536f2 100644
--- a/arch/arm64/include/asm/pgtable-prot.h
+++ b/arch/arm64/include/asm/pgtable-prot.h
@@ -77,7 +77,7 @@
})
#define PAGE_S2 __pgprot(_PROT_DEFAULT | PAGE_S2_MEMATTR(NORMAL) | PTE_S2_RDONLY | PAGE_S2_XN)
-#define PAGE_S2_DEVICE __pgprot(_PROT_DEFAULT | PAGE_S2_MEMATTR(DEVICE_nGnRE) | PTE_S2_RDONLY | PAGE_S2_XN)
+#define PAGE_S2_DEVICE __pgprot(_PROT_DEFAULT | PAGE_S2_MEMATTR(DEVICE_nGnRE) | PTE_S2_RDONLY | PTE_S2_XN)
#define PAGE_NONE __pgprot(((_PAGE_DEFAULT) & ~PTE_VALID) | PTE_PROT_NONE | PTE_RDONLY | PTE_NG | PTE_PXN | PTE_UXN)
#define PAGE_SHARED __pgprot(_PAGE_DEFAULT | PTE_USER | PTE_NG | PTE_PXN | PTE_UXN | PTE_WRITE)
--
2.20.1
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^ permalink raw reply related
* [PATCH] arm64: kpti: ensure patched kernel text is fetched from PoU
From: Mark Rutland @ 2019-08-27 17:12 UTC (permalink / raw)
To: linux-arm-kernel; +Cc: Mark Rutland, Catalin Marinas, James Morse, Will Deacon
While the MMUs is disabled, I-cache speculation can result in
instructions being fetched from the PoC. During boot we may patch
instructions (e.g. for alternatives and jump labels), and these may be
dirty at the PoU (and stale at the PoC).
Thus, while the MMU is disabled in the KPTI pagetable fixup code we may
load stale instructions into the I-cache, potentially leading to
subsequent crashes when executing regions of code which have been
modified at runtime.
Similarly to commit:
8ec41987436d566f ("arm64: mm: ensure patched kernel text is fetched from PoU")
... we can invalidate the I-cache after enabling the MMU to prevent such
issues.
The KPTI pagetable fixup code itself should be clean to the PoC per the
boot protocol, so no maintenance is required for this code.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: James Morse <james.morse@arm.com>
Cc: Will Deacon <will@kernel.org>
---
arch/arm64/mm/proc.S | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index 7dbf2be470f6..28a8f7b87ff0 100644
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -286,6 +286,15 @@ skip_pgd:
msr sctlr_el1, x18
isb
+ /*
+ * Invalidate the local I-cache so that any instructions fetched
+ * speculatively from the PoC are discarded, since they may have
+ * been dynamically patched at the PoU.
+ */
+ ic iallu
+ dsb nsh
+ isb
+
/* Set the flag to zero to indicate that we're all done */
str wzr, [flag_ptr]
ret
--
2.11.0
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^ permalink raw reply related
* Re: [PATCH 6/6] PCI: tegra: Add support to enable slot regulators
From: Andrew Murray @ 2019-08-27 17:13 UTC (permalink / raw)
To: Vidya Sagar
Cc: devicetree, lorenzo.pieralisi, mperttunen, mmaddireddy, kthota,
gustavo.pimentel, linux-kernel, robh+dt, kishon, linux-tegra,
thierry.reding, linux-pci, bhelgaas, digetx, jonathanh,
linux-arm-kernel, sagar.tv
In-Reply-To: <91f8914a-22a9-8b7c-bc00-c309a21d83db@nvidia.com>
On Tue, Aug 27, 2019 at 09:54:17PM +0530, Vidya Sagar wrote:
> On 8/27/2019 9:17 PM, Andrew Murray wrote:
> > On Mon, Aug 26, 2019 at 01:01:43PM +0530, Vidya Sagar wrote:
> > > Add support to get regulator information of 3.3V and 12V supplies of a PCIe
> > > slot from the respective controller's device-tree node and enable those
> > > supplies. This is required in platforms like p2972-0000 where the supplies
> > > to x16 slot owned by C5 controller need to be enabled before attempting to
> > > enumerate the devices.
> > >
> > > Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> > > ---
> > > drivers/pci/controller/dwc/pcie-tegra194.c | 65 ++++++++++++++++++++++
> > > 1 file changed, 65 insertions(+)
> > >
> > > diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> > > index 8a27b25893c9..97de2151a738 100644
> > > --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> > > +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> > > @@ -278,6 +278,8 @@ struct tegra_pcie_dw {
> > > u32 aspm_l0s_enter_lat;
> > > struct regulator *pex_ctl_supply;
> > > + struct regulator *slot_ctl_3v3;
> > > + struct regulator *slot_ctl_12v;
> > > unsigned int phy_count;
> > > struct phy **phys;
> > > @@ -1047,6 +1049,59 @@ static void tegra_pcie_downstream_dev_to_D0(struct tegra_pcie_dw *pcie)
> > > }
> > > }
> > > +static void tegra_pcie_get_slot_regulators(struct tegra_pcie_dw *pcie)
> > > +{
> > > + pcie->slot_ctl_3v3 = devm_regulator_get_optional(pcie->dev, "vpcie3v3");
> > > + if (IS_ERR(pcie->slot_ctl_3v3))
> > > + pcie->slot_ctl_3v3 = NULL;
> > > +
> > > + pcie->slot_ctl_12v = devm_regulator_get_optional(pcie->dev, "vpcie12v");
> > > + if (IS_ERR(pcie->slot_ctl_12v))
> > > + pcie->slot_ctl_12v = NULL;
> >
> > Do these need to take into consideration -EPROBE_DEFER?
> Since these are devm_* APIs, isn't it taken care of automatically?
devm_regulator_get_optional can still return -EPROBE_DEFER - for times when
"lookup could succeed in the future".
It's probably helpful here for your driver to distinguish between there not
being a regulator specified in the DT, and there being a regulator but there
is no device for it yet. For the latter case - your driver would probe but
nothing would enumerate.
See pcie-rockchip-host.c for an example of where this is handled.
Of course if, for whatever reason it is unlikely you'll ever get -EPROBE_DEFER
then maybe it's OK as it is.
Thanks,
Andrew Murray
>
> >
> > Thanks,
> >
> > Andrew Murray
> >
> > > +}
> > > +
> > > +static int tegra_pcie_enable_slot_regulators(struct tegra_pcie_dw *pcie)
> > > +{
> > > + int ret;
> > > +
> > > + if (pcie->slot_ctl_3v3) {
> > > + ret = regulator_enable(pcie->slot_ctl_3v3);
> > > + if (ret < 0) {
> > > + dev_err(pcie->dev,
> > > + "Failed to enable 3V3 slot supply: %d\n", ret);
> > > + return ret;
> > > + }
> > > + }
> > > +
> > > + if (pcie->slot_ctl_12v) {
> > > + ret = regulator_enable(pcie->slot_ctl_12v);
> > > + if (ret < 0) {
> > > + dev_err(pcie->dev,
> > > + "Failed to enable 12V slot supply: %d\n", ret);
> > > + if (pcie->slot_ctl_3v3)
> > > + regulator_disable(pcie->slot_ctl_3v3);
> > > + return ret;
> > > + }
> > > + }
> > > +
> > > + /*
> > > + * According to PCI Express Card Electromechanical Specification
> > > + * Revision 1.1, Table-2.4, T_PVPERL (Power stable to PERST# inactive)
> > > + * should be a minimum of 100ms.
> > > + */
> > > + msleep(100);
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +static void tegra_pcie_disable_slot_regulators(struct tegra_pcie_dw *pcie)
> > > +{
> > > + if (pcie->slot_ctl_12v)
> > > + regulator_disable(pcie->slot_ctl_12v);
> > > + if (pcie->slot_ctl_3v3)
> > > + regulator_disable(pcie->slot_ctl_3v3);
> > > +}
> > > +
> > > static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie,
> > > bool en_hw_hot_rst)
> > > {
> > > @@ -1060,6 +1115,10 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie,
> > > return ret;
> > > }
> > > + ret = tegra_pcie_enable_slot_regulators(pcie);
> > > + if (ret < 0)
> > > + goto fail_slot_reg_en;
> > > +
> > > ret = regulator_enable(pcie->pex_ctl_supply);
> > > if (ret < 0) {
> > > dev_err(pcie->dev, "Failed to enable regulator: %d\n", ret);
> > > @@ -1142,6 +1201,8 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie,
> > > fail_core_clk:
> > > regulator_disable(pcie->pex_ctl_supply);
> > > fail_reg_en:
> > > + tegra_pcie_disable_slot_regulators(pcie);
> > > +fail_slot_reg_en:
> > > tegra_pcie_bpmp_set_ctrl_state(pcie, false);
> > > return ret;
> > > @@ -1174,6 +1235,8 @@ static int __deinit_controller(struct tegra_pcie_dw *pcie)
> > > return ret;
> > > }
> > > + tegra_pcie_disable_slot_regulators(pcie);
> > > +
> > > ret = tegra_pcie_bpmp_set_ctrl_state(pcie, false);
> > > if (ret) {
> > > dev_err(pcie->dev, "Failed to disable controller %d: %d\n",
> > > @@ -1372,6 +1435,8 @@ static int tegra_pcie_dw_probe(struct platform_device *pdev)
> > > return ret;
> > > }
> > > + tegra_pcie_get_slot_regulators(pcie);
> > > +
> > > pcie->pex_ctl_supply = devm_regulator_get(dev, "vddio-pex-ctl");
> > > if (IS_ERR(pcie->pex_ctl_supply)) {
> > > dev_err(dev, "Failed to get regulator: %ld\n",
> > > --
> > > 2.17.1
> > >
>
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^ permalink raw reply
* Re: [PATCH v3 2/7] dt-bindings: mmc: Add Actions Semi SD/MMC/SDIO controller binding
From: Rob Herring @ 2019-08-27 17:19 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: devicetree, ulf.hansson, sboyd, linux-actions, linus.walleij,
linux-mmc, linux-kernel, thomas.liau, linux-clk, afaerber,
linux-arm-kernel
In-Reply-To: <20190821025629.15470-3-manivannan.sadhasivam@linaro.org>
On Wed, Aug 21, 2019 at 08:26:24AM +0530, Manivannan Sadhasivam wrote:
> Add devicetree YAML binding for Actions Semi Owl SoC's SD/MMC/SDIO
> controller.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> ---
> .../devicetree/bindings/mmc/owl-mmc.yaml | 62 +++++++++++++++++++
> 1 file changed, 62 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mmc/owl-mmc.yaml
>
> diff --git a/Documentation/devicetree/bindings/mmc/owl-mmc.yaml b/Documentation/devicetree/bindings/mmc/owl-mmc.yaml
> new file mode 100644
> index 000000000000..f7eff4c43017
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mmc/owl-mmc.yaml
> @@ -0,0 +1,62 @@
> +# SPDX-License-Identifier: GPL-2.0
(GPL-2.0-only OR BSD-2-Clause) for new bindings please.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mmc/owl-mmc.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Actions Semi Owl SoCs SD/MMC/SDIO controller
> +
> +allOf:
> + - $ref: "mmc-controller.yaml"
> +
> +maintainers:
> + - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> +
> +properties:
> + "#address-cells": true
> + "#size-cells": true
You can drop these.
> +
> + compatible:
> + const: actions,owl-mmc
> +
> + reg:
> + maxItems: 1
> +
> + interrupts:
> + maxItems: 1
> +
> + clocks:
> + minItems: 1
> +
> + resets:
> + maxItems: 1
> +
> + dmas:
> + maxItems: 1
> +
> + dma-names:
> + const: mmc
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> + - resets
> + - dmas
> + - dma-names
> +
> +examples:
> + - |
> + mmc0: mmc@e0330000 {
> + compatible = "actions,owl-mmc";
> + reg = <0x0 0xe0330000 0x0 0x4000>;
> + interrupts = <0 42 4>;
> + clocks = <&cmu 56>;
> + resets = <&cmu 23>;
> + dmas = <&dma 2>;
> + dma-names = "mmc";
> + bus-width = <4>;
> + };
> +
> +...
> --
> 2.17.1
>
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^ permalink raw reply
* Re: [PATCH v3 3/4] watchdog/aspeed: add support for dual boot
From: Guenter Roeck @ 2019-08-27 17:21 UTC (permalink / raw)
To: Ivan Mikhaylov
Cc: Mark Rutland, devicetree, linux-watchdog, linux-aspeed,
Andrew Jeffery, openbmc, Alexander Amelkin, linux-kernel,
Rob Herring, Joel Stanley, Wim Van Sebroeck, linux-arm-kernel
In-Reply-To: <20190827165426.17037-4-i.mikhaylov@yadro.com>
On Tue, Aug 27, 2019 at 07:54:25PM +0300, Ivan Mikhaylov wrote:
> Set WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION into WDT_CLEAR_TIMEOUT_STATUS
> to clear out boot code source and re-enable access to the primary SPI flash
> chip while booted via wdt2 from the alternate chip.
>
> AST2400 datasheet says:
> "In the 2nd flash booting mode, all the address mapping to CS0# would be
> re-directed to CS1#. And CS0# is not accessable under this mode. To access
> CS0#, firmware should clear the 2nd boot mode register in the WDT2 status
> register WDT30.bit[1]."
>
> Signed-off-by: Ivan Mikhaylov <i.mikhaylov@yadro.com>
Please run "checkpatch --strict" on this patch and fix the reported problems
(I _did_ ask for proper multi-line aligment before, but there are a couple
of other issues as well).
Thanks,
Guenter
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^ permalink raw reply
* Re: [PATCH v2 1/2] dt-bindings: irq: Convert Allwinner IRQ Controller to a schema
From: Rob Herring @ 2019-08-27 17:23 UTC (permalink / raw)
To: Maxime Ripard
Cc: Mark Rutland, devicetree, jason, Maxime Ripard, maz,
Maxime Ripard, Chen-Yu Tsai, tglx, Frank Rowand, linux-arm-kernel
In-Reply-To: <20190821082138.11049-1-mripard@kernel.org>
On Wed, 21 Aug 2019 10:21:37 +0200, Maxime Ripard wrote:
> From: Maxime Ripard <maxime.ripard@bootlin.com>
>
> The Allwinner SoCs have an interrupt controller supported in Linux, with a
> matching Device Tree binding.
>
> Now that we have the DT validation in place, let's convert the device tree
> bindings for that controller over to a YAML schemas.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
>
> ---
>
> Changes from v1:
> - Remove Fixme and add additionalProperties to false
> - Add unit address for the example
> ---
> .../allwinner,sun4i-a10-ic.yaml | 47 +++++++++++++++++++
> .../allwinner,sun4i-ic.txt | 20 --------
> 2 files changed, 47 insertions(+), 20 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-a10-ic.yaml
> delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt
>
Applied, thanks.
Rob
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^ permalink raw reply
* Re: [PATCH v2 2/2] dt-bindings: irq: Convert Allwinner NMI Controller to a schema
From: Rob Herring @ 2019-08-27 17:24 UTC (permalink / raw)
To: Maxime Ripard
Cc: Mark Rutland, devicetree, jason, Maxime Ripard, maz,
Maxime Ripard, Chen-Yu Tsai, tglx, Frank Rowand, linux-arm-kernel
In-Reply-To: <20190821082138.11049-2-mripard@kernel.org>
On Wed, 21 Aug 2019 10:21:38 +0200, Maxime Ripard wrote:
> From: Maxime Ripard <maxime.ripard@bootlin.com>
>
> The Allwinner SoCs have an interrupt controller called NMI supported in
> Linux, with a matching Device Tree binding.
>
> Now that we have the DT validation in place, let's convert the device tree
> bindings for that controller over to a YAML schemas.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
>
> ---
>
> Changes from v1:
> - Remove the custom select and rely on the deprecated property instead
> ---
> .../allwinner,sun7i-a20-sc-nmi.yaml | 70 +++++++++++++++++++
> .../allwinner,sunxi-nmi.txt | 29 --------
> 2 files changed, 70 insertions(+), 29 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml
> delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-nmi.txt
>
Applied, thanks.
Rob
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^ permalink raw reply
* Re: [PATCH v3 10/15] dt-bindings: display: Add max-memory-bandwidth property for mxsfb
From: Rob Herring @ 2019-08-27 17:25 UTC (permalink / raw)
To: Robert Chiras
Cc: Marek Vasut, devicetree, Pengutronix Kernel Team, dri-devel,
David Airlie, Guido Günther, linux-kernel, Stefan Agner,
NXP Linux Team, Daniel Vetter, Fabio Estevam, Sascha Hauer,
linux-arm-kernel
In-Reply-To: <1566382555-12102-11-git-send-email-robert.chiras@nxp.com>
On Wed, 21 Aug 2019 13:15:50 +0300, Robert Chiras wrote:
> Add new optional property 'max-memory-bandwidth', to limit the maximum
> bandwidth used by the MXSFB_DRM driver.
>
> Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
> ---
> Documentation/devicetree/bindings/display/mxsfb.txt | 5 +++++
> 1 file changed, 5 insertions(+)
>
Reviewed-by: Rob Herring <robh@kernel.org>
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* Re: [PATCH 3/8] coresight: etm4x: Add missing API to set EL match on address filters
From: Mathieu Poirier @ 2019-08-27 17:57 UTC (permalink / raw)
To: Mike Leach; +Cc: Coresight ML, linux-arm-kernel, Suzuki K. Poulose
In-Reply-To: <CAJ9a7VgAYwCONqwJHTb9QunN0Q4R3E82kxzpSJXV9kv2dpRnHw@mail.gmail.com>
On Tue, 27 Aug 2019 at 04:55, Mike Leach <mike.leach@linaro.org> wrote:
>
> Hi Mathieu,
>
> On Mon, 26 Aug 2019 at 23:59, Mathieu Poirier
> <mathieu.poirier@linaro.org> wrote:
> >
> > On Mon, Aug 19, 2019 at 09:57:15PM +0100, Mike Leach wrote:
> > > TRCACATRn registers have match bits for secure and non-secure exception
> > > levels which are not accessible by the sysfs API.
> > > This adds a new sysfs parameter to enable this - addr_exlevel_s_ns.
> > >
> > > Signed-off-by: Mike Leach <mike.leach@linaro.org>
> > > ---
> > > .../coresight/coresight-etm4x-sysfs.c | 39 +++++++++++++++++++
> > > 1 file changed, 39 insertions(+)
> > >
> > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > > index fa1d6a938f6c..7eab5d7d0b62 100644
> > > --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > > +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> > > @@ -1233,6 +1233,44 @@ static ssize_t addr_context_store(struct device *dev,
> > > }
> > > static DEVICE_ATTR_RW(addr_context);
> > >
> > > +static ssize_t addr_exlevel_s_ns_show(struct device *dev,
> > > + struct device_attribute *attr,
> > > + char *buf)
> > > +{
> > > + u8 idx;
> > > + unsigned long val;
> > > + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > > + struct etmv4_config *config = &drvdata->config;
> > > +
> > > + spin_lock(&drvdata->spinlock);
> > > + idx = config->addr_idx;
> > > + val = BMVAL(config->addr_acc[idx], 14, 8);
> > > + spin_unlock(&drvdata->spinlock);
> > > + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> > > +}
> > > +
> > > +static ssize_t addr_exlevel_s_ns_store(struct device *dev,
> > > + struct device_attribute *attr,
> > > + const char *buf, size_t size)
> > > +{
> > > + u8 idx;
> > > + unsigned long val;
> > > + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> > > + struct etmv4_config *config = &drvdata->config;
> > > +
> > > + if (kstrtoul(buf, 16, &val))
> > > + return -EINVAL;
> > > +
> > > + spin_lock(&drvdata->spinlock);
> > > + idx = config->addr_idx;
> > > + /* clear Exlevel_ns & Exlevel_s bits[14:12, 11:8] */
> > > + config->addr_acc[idx] &= ~(GENMASK(14, 8));
> > > + config->addr_acc[idx] |= (val << 8);
> > > + spin_unlock(&drvdata->spinlock);
> > > + return size;
> > > +}
> > > +static DEVICE_ATTR_RW(addr_exlevel_s_ns);
> > > +
> > > static ssize_t seq_idx_show(struct device *dev,
> > > struct device_attribute *attr,
> > > char *buf)
> > > @@ -2038,6 +2076,7 @@ static struct attribute *coresight_etmv4_attrs[] = {
> > > &dev_attr_addr_stop.attr,
> > > &dev_attr_addr_ctxtype.attr,
> > > &dev_attr_addr_context.attr,
> > > + &dev_attr_addr_exlevel_s_ns.attr,
> > > &dev_attr_seq_idx.attr,
> > > &dev_attr_seq_state.attr,
> > > &dev_attr_seq_event.attr,
> >
> > I'm ok with this patch but the new entry needs to be documented in [1].
>
> It is in a later patch.
Very well
>
> > But
> > before moving forward with that I'm wondering if this is the way to go. Would
> > it be better to consolidate type, ctxtype, context and exlevel_s_ns in a single
> > entry, say addr_acc_type? We'd shed a fair amount of code and make it more
> > simple for users to configure.
> >
>
> It will mean the user has less writes to do - but is it really simpler
> to understand?
>
> At present each feature takes the input value and interprets / shifts
> it to set the relevant bits in the address comparator control
> registers (context type being a string input rather than bit values).
>
> The alternative is to require the user to understand the bit values -
> which they may well do if they are referring to the ETM docs to
> program in this detail, and provide a correct input value for their
> requirements.
>
> My addition adds to the API, rather than changes it, but if you prefer
> we could go with an update to a single feature to control this value
> in the comparator control registers.
I am definitely not strongly opinionated on this - it is an idea I
wanted to float by you. Since you don't seem to have a strong
position either we can just carry on with this patch and revisit in
the future if need be.
>
> Mike
>
> >
> > [1]. Documentation/ABI/testing/sysfs-bus-coresight-devices-etm4x
> >
> > > --
> > > 2.17.1
> > >
>
>
>
> --
> Mike Leach
> Principal Engineer, ARM Ltd.
> Manchester Design Centre. UK
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* Re: [PATCH 1/5] dt-bindings: sound: sun4i-spdif: Fix dma-names warning
From: Mark Brown @ 2019-08-27 18:14 UTC (permalink / raw)
To: Maxime Ripard
Cc: Mark Rutland, devicetree, alsa-devel, Liam Girdwood, Chen-Yu Tsai,
Rob Herring, Frank Rowand, linux-arm-kernel
In-Reply-To: <20190827142547.14577-1-mripard@kernel.org>
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On Tue, Aug 27, 2019 at 04:25:43PM +0200, Maxime Ripard wrote:
> From: Maxime Ripard <maxime.ripard@bootlin.com>
>
> Even though the H6 compatible has been properly added, the exeption for the
> number of DMA channels hasn't been updated, leading in a validation
> warning.
Please use subject lines matching the style for the subsystem. This
makes it easier for people to identify relevant patches. This
doesn't even have ASoC in it...
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* Re: [PATCH] ARM: OMAP2+: Delete an unnecessary kfree() call in omap_hsmmc_pdata_init()
From: Ladislav Michl @ 2019-08-27 18:14 UTC (permalink / raw)
To: Tony Lindgren
Cc: Paul Walmsley, Balaji T K, kernel-janitors, Kishore Kadiyala,
Russell King, LKML, Markus Elfring, Nikolaus Schaller, linux-omap,
linux-arm-kernel, Benoit Cousson
In-Reply-To: <20190826162050.GX52127@atomide.com>
On Mon, Aug 26, 2019 at 09:20:50AM -0700, Tony Lindgren wrote:
> * Markus Elfring <Markus.Elfring@web.de> [190826 06:31]:
> > From: Markus Elfring <elfring@users.sourceforge.net>
> > Date: Mon, 26 Aug 2019 15:05:31 +0200
> >
> > A null pointer would be passed to a call of the function "kfree" directly
> > after a call of the function "kzalloc" failed at one place.
> > Remove this superfluous function call.
> >
> > This issue was detected by using the Coccinelle software.
>
> Applying into omap-for-v5.4/soc thanks.
Is it really wise touching almost dead code? Last user is pandora board, so
+Cc: Nikolaus Schaller <hns@goldelico.com>
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* Re: [PATCH V7 1/3] perf: imx8_ddr_perf: add AXI ID filter support
From: Will Deacon @ 2019-08-27 18:30 UTC (permalink / raw)
To: Joakim Zhang
Cc: mark.rutland@arm.com, Frank Li, robin.murphy@arm.com,
dl-linux-imx, linux-arm-kernel@lists.infradead.org
In-Reply-To: <20190827023557.7071-1-qiangqing.zhang@nxp.com>
Hi Joakim,
On Tue, Aug 27, 2019 at 02:39:32AM +0000, Joakim Zhang wrote:
> AXI filtering is used by CSV modes 0x41 and 0x42 to count reads or
> writes with an ARID or AWID matching filter setting. Granularity is at
> subsystem level. Implementation does not allow filtring between masters
> within a subsystem. Filter is defined with 2 configuration parameters.
>
> --AXI_ID defines AxID matching value
> --AXI_MASKING defines which bits of AxID are meaningful for the matching
> 0：corresponding bit is masked
> 1: corresponding bit is not masked, i.e. used to do the matching
>
> When non-masked bits are matching corresponding AXI_ID bits then counter
> is incremented. This filter allows counting read or write access from a
> subsystem or multiple subsystems.
>
> Perf counter is incremented if AxID && AXI_MASKING == AXI_ID && AXI_MASKING
>
> AXI_ID and AXI_MASKING are mapped on DPCR1 register in performance counter.
>
> Read and write AXI ID filter should write same value to DPCR1 if want to
> specify at the same time as this filter is shared between counters.
>
> e.g.
> perf stat -a -e imx8_ddr0/axid-read,axi_id=0xMMMMDDDD/,imx8_ddr0/axid-write,axi_id=0xMMMMDDDD/ cmd
> MMMM: AXI_MASKING DDDD: AXI_ID
> perf stat -a -e imx8_ddr0/axid-read,axi_id=0x12/ cmd, which will monitor ARID=0x12
>
> NOTE: AXI_MASKING is inverted at driver(i.e. set bits are bits to mask), so
> that the user can just specify axi_id to monitor a specific id, rather than
> having to specify axi_id=0xffff<id>.
[...]
> @@ -138,9 +156,11 @@ static struct attribute_group ddr_perf_events_attr_group = {
> };
>
> PMU_FORMAT_ATTR(event, "config:0-7");
> +PMU_FORMAT_ATTR(axi_id, "config1:0-31");
I still don't think this is quite what Mark was suggesting. My understanding
of his email [1] was that you would do something like:
PMU_FORMAT_ATTR(axi_id, "config1:0-15");
PMU_FORMAT_ATTR(axi_mask, "config1:16-31");
and then if the user omits to specify axi_mask, it has a value of 0 which
means that all of the axi_id bits are matched (i.e. the driver inverts
the mask internally). I think that's actually what your code is doing:
> @@ -288,6 +337,21 @@ static int ddr_perf_event_add(struct perf_event *event, int flags)
> struct hw_perf_event *hwc = &event->hw;
> int counter;
> int cfg = event->attr.config;
> + int cfg1 = event->attr.config1;
> +
> + if (pmu->devtype_data->quirks & DDR_CAP_AXI_ID_FILTER) {
> + int i;
> +
> + for (i = 1; i < NUM_COUNTERS; i++) {
> + if (pmu->events[i] &&
> + !ddr_perf_filters_compatible(event, pmu->events[i]))
> + return -EINVAL;
> + }
> +
> + /* revert axi_id masking value */
> + cfg1 ^= AXI_MASKING_REVERT;
it's just that the user ABI should probably separate these two fields out
as above.
I was going to make the change when merging this patch, but you need to
update the Documentation in the second patch too.
Will
[1] https://lkml.kernel.org/r/20190823125719.GD55480@lakrids.cambridge.arm.com
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* Re: [PATCH next v10 03/11] dt-bindings: usb: add binding for USB GPIO based connection detection driver
From: Rob Herring @ 2019-08-27 18:31 UTC (permalink / raw)
To: Chunfeng Yun
Cc: Mark Rutland, devicetree, Heikki Krogerus, Hans de Goede,
Greg Kroah-Hartman, Linus Walleij, linux-usb, linux-kernel,
Biju Das, Badhri Jagan Sridharan, Andy Shevchenko, linux-mediatek,
Min Guo, Matthias Brugger, Nagarjuna Kristam, Adam Thomson,
linux-arm-kernel, Li Jun
In-Reply-To: <1566547041-20804-4-git-send-email-chunfeng.yun@mediatek.com>
On Fri, Aug 23, 2019 at 03:57:13PM +0800, Chunfeng Yun wrote:
> It's used to support dual role switch via GPIO when use Type-B
> receptacle, typically the USB ID pin is connected to an input
> GPIO, and also used to enable/disable device when the USB Vbus
> pin is connected to an input GPIO.
>
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
> v9~v10 no changes
>
> v8 changes:
> 1. rename the title
> 2. change the compatible as "linux,usb-conn-gpio" instead of
> "linux,typeb-conn-gpio"
I don't think that is an improvement. How about 'gpio-usb-b-connector'
to be consistent.
>
> v7 changes:
> 1. add description for device only mode
>
> v6 changes:
> 1. remove status and port nodes in example
> 2. make vbus-supply as optional property
>
> v5 changes:
> 1. treat type-B connector as child device of USB controller's, but not
> as a separate virtual device, suggested by Rob
> 2. put connector's port node under connector node, suggested by Rob
>
> v4 no changes
>
> v3 changes:
> 1. treat type-B connector as a virtual device, but not child device of
> USB controller's
>
> v2 changes:
> 1. new patch to make binding clear suggested by Hans
> ---
> .../devicetree/bindings/usb/usb-conn-gpio.txt | 31 +++++++++++++++++++
> 1 file changed, 31 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/usb/usb-conn-gpio.txt
>
> diff --git a/Documentation/devicetree/bindings/usb/usb-conn-gpio.txt b/Documentation/devicetree/bindings/usb/usb-conn-gpio.txt
> new file mode 100644
> index 000000000000..d4d107fedc22
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/usb-conn-gpio.txt
> @@ -0,0 +1,31 @@
> +USB GPIO Based Connection Detection
> +
> +This is typically used to switch dual role mode from the USB ID pin connected
> +to an input GPIO, and also used to enable/disable device mode from the USB
> +Vbus pin connected to an input GPIO.
> +
> +Required properties:
> +- compatible : should include "linux,usb-conn-gpio" and "usb-b-connector".
> +- id-gpios, vbus-gpios : input gpios, either one of them must be present,
> + and both can be present as well.
> + see connector/usb-connector.txt
> +
> +Optional properties:
> +- vbus-supply : can be present if needed when supports dual role mode.
> + see connector/usb-connector.txt
> +
> +- Sub-nodes:
> + - port : can be present.
> + see graph.txt
> +
> +Example:
> +
> +&mtu3 {
> + connector {
> + compatible = "linux,usb-conn-gpio", "usb-b-connector";
> + label = "micro-USB";
'label' is for a human identifying a particular connector when there are
multiple (of the same type). So not a great example here.
> + type = "micro";
> + id-gpios = <&pio 12 GPIO_ACTIVE_HIGH>;
> + vbus-supply = <&usb_p0_vbus>;
> + };
> +};
> --
> 2.23.0
>
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