* RE: [PATCH v4 0/8] Enable Linux guests on Hyper-V on ARM64
From: Michael Kelley @ 2019-08-28 3:33 UTC (permalink / raw)
To: will.deacon@arm.com, catalin.marinas@arm.com,
mark.rutland@arm.com, marc.zyngier@arm.com,
linux-arm-kernel@lists.infradead.org, gregkh@linuxfoundation.org,
linux-kernel@vger.kernel.org, linux-hyperv@vger.kernel.org,
devel@linuxdriverproject.org, olaf@aepfle.de, apw@canonical.com,
vkuznets, jasowang@redhat.com, marcelo.cerri@canonical.com,
KY Srinivasan
Cc: Sunil Muthuswamy, boqun.feng
In-Reply-To: <1565122133-9086-1-git-send-email-mikelley@microsoft.com>
From: Michael Kelley <mikelley@microsoft.com> Sent: Tuesday, August 6, 2019 1:31 PM
>
> This series enables Linux guests running on Hyper-V on ARM64
> hardware. New ARM64-specific code in arch/arm64/hyperv initializes
> Hyper-V, including its interrupts and hypercall mechanism.
> Existing architecture independent drivers for Hyper-V's VMbus and
> synthetic devices just work when built for ARM64. Hyper-V code is
> built and included in the image and modules only if CONFIG_HYPERV
> is enabled.
>
> The eight patches are organized as follows:
> 1) Add include files that define the Hyper-V interface as
> described in the Hyper-V Top Level Functional Spec (TLFS), plus
> additional definitions specific to Linux running on Hyper-V.
>
> 2 thru 6) Add core Hyper-V support on ARM64, including hypercalls,
> interrupt handlers, kexec & panic handlers, and core hypervisor
> initialization.
>
> 7) Update the existing VMbus driver to generalize interrupt
> management across x86/x64 and ARM64.
>
> 8) Make CONFIG_HYPERV selectable on ARM64 in addition to x86/x64.
>
I'm hoping to get some feedback from the ARM64 maintainers on this
series. Previous feedback has been incorporated, so it should be
close to being able to go in.
Michael
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^ permalink raw reply
* Re: [PATCH 5/8] coresight: etm4x: Improve usability of sysfs API.
From: Leo Yan @ 2019-08-28 3:36 UTC (permalink / raw)
To: Mike Leach; +Cc: coresight, linux-arm-kernel, mathieu.poirier
In-Reply-To: <20190819205720.24457-6-mike.leach@linaro.org>
On Mon, Aug 19, 2019 at 09:57:17PM +0100, Mike Leach wrote:
> Some changes to make the sysfs programming more intuitive.
>
> 1) Setting include / exclude on a range had to be done by setting
> the bit in 'mode' before setting the range. However, setting this
> bit also had the effect of altering the current range as well.
>
> Changed to only set include / exclude setting of a range at the point of
> setting that range. Either use a 3rd input parameter as the include exclude
> value, or if not present use the current value of 'mode'. Do not change
> current range when 'mode' changes.
>
> 2) Context ID and VM ID masks required 2 value inputs, even when the
> second value is ignored as insufficient CID / VMID comparators are
> implemented.
> Permit a single value to be used if that is sufficient to cover all
> implemented comparators.
>
> Signed-off-by: Mike Leach <mike.leach@linaro.org>
> ---
> .../coresight/coresight-etm4x-sysfs.c | 24 +++++++++++++------
> 1 file changed, 17 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> index 3bcc260c9e55..baac5b48b7ac 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> @@ -297,8 +297,6 @@ static ssize_t mode_store(struct device *dev,
>
> spin_lock(&drvdata->spinlock);
> config->mode = val & ETMv4_MODE_ALL;
> - etm4_set_mode_exclude(drvdata,
> - config->mode & ETM_MODE_EXCLUDE ? true : false);
>
> if (drvdata->instrp0 == true) {
> /* start by clearing instruction P0 field */
> @@ -972,8 +970,12 @@ static ssize_t addr_range_store(struct device *dev,
> unsigned long val1, val2;
> struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> struct etmv4_config *config = &drvdata->config;
> + int elements, exclude;
>
> - if (sscanf(buf, "%lx %lx", &val1, &val2) != 2)
> + elements = sscanf(buf, "%lx %lx %x", &val1, &val2, &exclude);
> +
> + /* exclude is optional, but need at least two parameter */
> + if (elements < 2)
> return -EINVAL;
> /* lower address comparator cannot have a higher address value */
> if (val1 > val2)
> @@ -1001,9 +1003,11 @@ static ssize_t addr_range_store(struct device *dev,
> /*
> * Program include or exclude control bits for vinst or vdata
> * whenever we change addr comparators to ETM_ADDR_TYPE_RANGE
> + * use supplied value, or default to bit set in 'mode'
> */
> - etm4_set_mode_exclude(drvdata,
> - config->mode & ETM_MODE_EXCLUDE ? true : false);
> + if (elements != 3)
> + exclude = config->mode & ETM_MODE_EXCLUDE;
> + etm4_set_mode_exclude(drvdata, exclude ? true : false);
>
> spin_unlock(&drvdata->spinlock);
> return size;
> @@ -1787,6 +1791,7 @@ static ssize_t ctxid_masks_store(struct device *dev,
> unsigned long val1, val2, mask;
> struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> struct etmv4_config *config = &drvdata->config;
> + int nr_inputs;
>
> /*
> * Don't use contextID tracing if coming from a PID namespace. See
> @@ -1802,7 +1807,9 @@ static ssize_t ctxid_masks_store(struct device *dev,
> */
> if (!drvdata->ctxid_size || !drvdata->numcidc)
> return -EINVAL;
> - if (sscanf(buf, "%lx %lx", &val1, &val2) != 2)
> + /* one mask if < 4 comparators, two for up to 8 */
One maks is <= 4 comparators.
> + nr_inputs = sscanf(buf, "%lx %lx", &val1, &val2);
> + if ((drvdata->numcidc > 4) && (nr_inputs != 2))
> return -EINVAL;
>
> spin_lock(&drvdata->spinlock);
> @@ -1976,6 +1983,7 @@ static ssize_t vmid_masks_store(struct device *dev,
> unsigned long val1, val2, mask;
> struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> struct etmv4_config *config = &drvdata->config;
> + int nr_inputs;
>
> /*
> * only implemented when vmid tracing is enabled, i.e. at least one
> @@ -1983,7 +1991,9 @@ static ssize_t vmid_masks_store(struct device *dev,
> */
> if (!drvdata->vmid_size || !drvdata->numvmidc)
> return -EINVAL;
> - if (sscanf(buf, "%lx %lx", &val1, &val2) != 2)
> + /* one mask if < 4 comparators, two for up to 8 */
One maks is <= 4 comparators.
> + nr_inputs = sscanf(buf, "%lx %lx", &val1, &val2);
> + if ((drvdata->numvmidc > 4) && (nr_inputs != 2))
> return -EINVAL;
>
> spin_lock(&drvdata->spinlock);
> --
> 2.17.1
>
> _______________________________________________
> CoreSight mailing list
> CoreSight@lists.linaro.org
> https://lists.linaro.org/mailman/listinfo/coresight
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH v2 -next] net: mediatek: remove set but not used variable 'status'
From: David Miller @ 2019-08-28 3:48 UTC (permalink / raw)
To: maowenan
Cc: nbd, nelson.chang, netdev, sean.wang, kernel-janitors,
linux-kernel, linux-mediatek, john, matthias.bgg,
linux-arm-kernel
In-Reply-To: <20190826013118.22720-1-maowenan@huawei.com>
From: Mao Wenan <maowenan@huawei.com>
Date: Mon, 26 Aug 2019 09:31:18 +0800
> Fixes gcc '-Wunused-but-set-variable' warning:
> drivers/net/ethernet/mediatek/mtk_eth_soc.c: In function mtk_handle_irq:
> drivers/net/ethernet/mediatek/mtk_eth_soc.c:1951:6: warning: variable status set but not used [-Wunused-but-set-variable]
>
> Fixes: 296c9120752b ("net: ethernet: mediatek: Add MT7628/88 SoC support")
> Signed-off-by: Mao Wenan <maowenan@huawei.com>
Applied to net-next.
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^ permalink raw reply
* Re: [PATCH 6/8] coresight: etm4x: Add view comparator settings API to sysfs.
From: Leo Yan @ 2019-08-28 4:00 UTC (permalink / raw)
To: Mike Leach; +Cc: coresight, linux-arm-kernel, mathieu.poirier
In-Reply-To: <20190819205720.24457-7-mike.leach@linaro.org>
Hi Mike,
On Mon, Aug 19, 2019 at 09:57:18PM +0100, Mike Leach wrote:
> Currently it is not possible to view the current settings of a given
> address comparator without knowing what type it is set to. For example, if
> a comparator is set as an addr_start comparator, attempting to read
> addr_stop for the same index will result in an error.
>
> addr_cmp_view is added to allow the user to see the current settings of
> the indexed address comparator without resorting to trail and error when
> the set type is not known.
>
> Signed-off-by: Mike Leach <mike.leach@linaro.org>
> ---
> .../coresight/coresight-etm4x-sysfs.c | 51 +++++++++++++++++++
> 1 file changed, 51 insertions(+)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> index baac5b48b7ac..483976074779 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> @@ -1272,6 +1272,56 @@ static ssize_t addr_exlevel_s_ns_store(struct device *dev,
> }
> static DEVICE_ATTR_RW(addr_exlevel_s_ns);
>
> +static const char * const addr_type_names[] = {
> + "unused",
> + "single",
> + "range",
> + "start",
> + "stop"
> +};
> +
> +static ssize_t addr_cmp_view_show(struct device *dev,
> + struct device_attribute *attr, char *buf)
> +{
> + u8 idx, addr_type;
> + unsigned long addr_v, addr_v2, addr_ctrl;
Some nitpicks, if you disagree, just ignore them :)
nitpicks: maybe we can use 'addr_v1' and 'addr_v2', we even can use
'addr_l' and 'addr_h'.
> + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + struct etmv4_config *config = &drvdata->config;
> + int size = 0;
> + bool exclude = false;
> +
> + spin_lock(&drvdata->spinlock);
> + idx = config->addr_idx;
> + addr_v = config->addr_val[idx];
> + addr_ctrl = config->addr_acc[idx];
> + addr_type = config->addr_type[idx];
> + if (addr_type == ETM_ADDR_TYPE_RANGE) {
> + if (idx%2) {
if (idx & 0x1)
> + idx -= 1;
> + addr_v2 = addr_v;
> + addr_v = config->addr_val[idx];
> + } else
> + addr_v2 = config->addr_val[idx+1];
The code style doc [1] suggests to use braces for 'else' as well.
> + exclude = config->viiectlr & BIT(idx / 2 + 16);
> + }
> + spin_unlock(&drvdata->spinlock);
> + if (addr_type) {
> + size = scnprintf(buf, PAGE_SIZE, "addr_cmp[%i] %s %#lx", idx,
> + addr_type_names[addr_type], addr_v);
> + if (addr_type == ETM_ADDR_TYPE_RANGE) {
> + size += scnprintf(buf+size, PAGE_SIZE-size,
s/buf+size/buf + size
s/PAGE_SIZE-size/PAGE_SIZE - size
> + " %#lx %s", addr_v2,
> + exclude ? "exclude" : "include");
> + }
> + size += scnprintf(buf+size, PAGE_SIZE-size,
s/buf+size/buf + size
This patch logic is clear for me, so you could add my review tag:
Reviewed-by: Leo Yan <leo.yan@linaro.org>
Thanks,
Leo Yan
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/coding-style.rst#n194
> + " ctrl(%#lx)\n", addr_ctrl);
> + } else {
> + size = scnprintf(buf, PAGE_SIZE, "addr_cmp[%i] unused\n", idx);
> + }
> + return size;
> +}
> +static DEVICE_ATTR_RO(addr_cmp_view);
> +
> static ssize_t vinst_pe_cmp_start_stop_show(struct device *dev,
> struct device_attribute *attr,
> char *buf)
> @@ -2117,6 +2167,7 @@ static struct attribute *coresight_etmv4_attrs[] = {
> &dev_attr_addr_ctxtype.attr,
> &dev_attr_addr_context.attr,
> &dev_attr_addr_exlevel_s_ns.attr,
> + &dev_attr_addr_cmp_view.attr,
> &dev_attr_vinst_pe_cmp_start_stop.attr,
> &dev_attr_seq_idx.attr,
> &dev_attr_seq_state.attr,
> --
> 2.17.1
>
> _______________________________________________
> CoreSight mailing list
> CoreSight@lists.linaro.org
> https://lists.linaro.org/mailman/listinfo/coresight
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^ permalink raw reply
* RE: [PATCH v2 08/10] PCI: layerscape: Add EP mode support for ls1088a and ls2088a
From: Xiaowei Bao @ 2019-08-28 4:29 UTC (permalink / raw)
To: Andrew Murray
Cc: mark.rutland@arm.com, Roy Zang, lorenzo.pieralisi@arm.co,
arnd@arndb.de, devicetree@vger.kernel.org,
gregkh@linuxfoundation.org, linuxppc-dev@lists.ozlabs.org,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
kishon@ti.com, M.h. Lian, robh+dt@kernel.org,
gustavo.pimentel@synopsys.com, jingoohan1@gmail.com,
bhelgaas@google.com, Leo Li, shawnguo@kernel.org, Mingkai Hu,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <20190827133429.GM14582@e119886-lin.cambridge.arm.com>
> -----Original Message-----
> From: Andrew Murray <andrew.murray@arm.com>
> Sent: 2019年8月27日 21:34
> To: Xiaowei Bao <xiaowei.bao@nxp.com>
> Cc: bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com;
> shawnguo@kernel.org; Leo Li <leoyang.li@nxp.com>; kishon@ti.com;
> lorenzo.pieralisi@arm.co; arnd@arndb.de; gregkh@linuxfoundation.org; M.h.
> Lian <minghuan.lian@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Roy
> Zang <roy.zang@nxp.com>; jingoohan1@gmail.com;
> gustavo.pimentel@synopsys.com; linux-pci@vger.kernel.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; linuxppc-dev@lists.ozlabs.org
> Subject: Re: [PATCH v2 08/10] PCI: layerscape: Add EP mode support for
> ls1088a and ls2088a
>
> On Mon, Aug 26, 2019 at 09:49:35AM +0000, Xiaowei Bao wrote:
> >
> >
> > > -----Original Message-----
> > > From: Andrew Murray <andrew.murray@arm.com>
> > > Sent: 2019年8月23日 22:28
> > > To: Xiaowei Bao <xiaowei.bao@nxp.com>
> > > Cc: bhelgaas@google.com; robh+dt@kernel.org; mark.rutland@arm.com;
> > > shawnguo@kernel.org; Leo Li <leoyang.li@nxp.com>; kishon@ti.com;
> > > lorenzo.pieralisi@arm.co; arnd@arndb.de; gregkh@linuxfoundation.org;
> M.h.
> > > Lian <minghuan.lian@nxp.com>; Mingkai Hu <mingkai.hu@nxp.com>; Roy
> > > Zang <roy.zang@nxp.com>; jingoohan1@gmail.com;
> > > gustavo.pimentel@synopsys.com; linux-pci@vger.kernel.org;
> > > devicetree@vger.kernel.org; linux-kernel@vger.kernel.org;
> > > linux-arm-kernel@lists.infradead.org; linuxppc-dev@lists.ozlabs.org
> > > Subject: Re: [PATCH v2 08/10] PCI: layerscape: Add EP mode support
> > > for ls1088a and ls2088a
> > >
> > > On Thu, Aug 22, 2019 at 07:22:40PM +0800, Xiaowei Bao wrote:
> > > > Add PCIe EP mode support for ls1088a and ls2088a, there are some
> > > > difference between LS1 and LS2 platform, so refactor the code of
> > > > the EP driver.
> > > >
> > > > Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
> > > > ---
> > > > v2:
> > > > - New mechanism for layerscape EP driver.
> > >
> > > Was there a v1 of this patch?
> > >
> > > >
> > > > drivers/pci/controller/dwc/pci-layerscape-ep.c | 76
> > > > ++++++++++++++++++++------
> > > > 1 file changed, 58 insertions(+), 18 deletions(-)
> > > >
> > > > diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c
> > > > b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> > > > index 7ca5fe8..2a66f07 100644
> > > > --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c
> > > > +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> > > > @@ -20,27 +20,29 @@
> > > >
> > > > #define PCIE_DBI2_OFFSET 0x1000 /* DBI2 base address*/
> > > >
> > > > -struct ls_pcie_ep {
> > > > - struct dw_pcie *pci;
> > > > - struct pci_epc_features *ls_epc;
> > > > +#define to_ls_pcie_ep(x) dev_get_drvdata((x)->dev)
> > > > +
> > > > +struct ls_pcie_ep_drvdata {
> > > > + u32 func_offset;
> > > > + const struct dw_pcie_ep_ops *ops;
> > > > + const struct dw_pcie_ops *dw_pcie_ops;
> > > > };
> > > >
> > > > -#define to_ls_pcie_ep(x) dev_get_drvdata((x)->dev)
> > > > +struct ls_pcie_ep {
> > > > + struct dw_pcie *pci;
> > > > + struct pci_epc_features *ls_epc;
> > > > + const struct ls_pcie_ep_drvdata *drvdata; };
> > > >
> > > > static int ls_pcie_establish_link(struct dw_pcie *pci) {
> > > > return 0;
> > > > }
> > > >
> > > > -static const struct dw_pcie_ops ls_pcie_ep_ops = {
> > > > +static const struct dw_pcie_ops dw_ls_pcie_ep_ops = {
> > > > .start_link = ls_pcie_establish_link, };
> > > >
> > > > -static const struct of_device_id ls_pcie_ep_of_match[] = {
> > > > - { .compatible = "fsl,ls-pcie-ep",},
> > > > - { },
> > > > -};
> > > > -
> > > > static const struct pci_epc_features*
> > > > ls_pcie_ep_get_features(struct dw_pcie_ep *ep) { @@ -82,10 +84,44
> > > > @@ static int ls_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> > > > }
> > > > }
> > > >
> > > > -static const struct dw_pcie_ep_ops pcie_ep_ops = {
> > > > +static unsigned int ls_pcie_ep_func_conf_select(struct dw_pcie_ep
> *ep,
> > > > + u8 func_no)
> > > > +{
> > > > + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> > > > + struct ls_pcie_ep *pcie = to_ls_pcie_ep(pci);
> > > > + u8 header_type;
> > > > +
> > > > + header_type = ioread8(pci->dbi_base + PCI_HEADER_TYPE);
> > > > +
> > > > + if (header_type & (1 << 7))
> > > > + return pcie->drvdata->func_offset * func_no;
> > > > + else
> > > > + return 0;
> > >
> > > It looks like there isn't a PCI define for multi function, the
> > > nearest I could find was PCI_HEADER_TYPE_MULTIDEVICE in
> > > hotplug/ibmphp.h. A comment above the test might be helpful to explain
> the test.
> >
> > OK, I will add a comment above this code.
> >
> > >
> > > As the ls_pcie_ep_drvdata structures are static, the unset
> > > .func_offset will be initialised to 0, so you could just drop the test above.
> >
> > Due to the different PCIe controller have different property, e.g.
> > PCIe controller1 support multiple function feature, but PCIe
> > controller2 don't support this feature, so I need to check which
> > controller support it and return the correct offset value, but each board only
> have one ls_pcie_ep_drvdata, ^_^.
>
> Yes but if they don't support the feature then func_offset will be 0.
>
> >
> > >
> > > However something to the effect of the following may help spot
> > > misconfiguration:
> > >
> > > WARN_ON(func_no && !pcie->drvdata->func_offset); return
> > > pcie->drvdata->func_offset * func_no;
> > >
> > > The WARN is probably quite useful as if you are attempting to use
> > > non-zero functions and func_offset isn't set - then things may
> > > appear to work normally but actually will break horribly.
> >
> > As discussion before, I think the func_offset should not depends on
> > the function number, even if other platforms of NXP may be use write
> > registers way to access the different function config space.
>
> I agree that func_offset is an optional parameter. But if you are attempting to
> determine the offset of a function and you are given a non-zero function
> number - then something has gone wrong if func_offset is 0.
I have understood you means, maybe I need to set a flag in the driver_data struct,
because I may add other platform of NXP, these platform use the write register
method to access different function, e.g.
write func_num to register, then we can access this func_num config space.
I will modify the code like this? Do you have better advice?
Case1:
diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c
index 004a7e8..8a0d6df 100644
--- a/drivers/pci/controller/dwc/pci-layerscape-ep.c
+++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
@@ -23,6 +23,7 @@
#define to_ls_pcie_ep(x) dev_get_drvdata((x)->dev)
struct ls_pcie_ep_drvdata {
+ u8 func_config_flag;
u32 func_offset;
const struct dw_pcie_ep_ops *ops;
const struct dw_pcie_ops *dw_pcie_ops;
@@ -97,8 +98,14 @@ static unsigned int ls_pcie_ep_func_conf_select(struct dw_pcie_ep *ep,
* Read the Header Type register of config space to check
* whether this PCI device support the multiple function.
*/
- if (header_type & (1 << 7))
- return pcie->drvdata->func_offset * func_no;
+ if (header_type & (1 << 7)) {
+ if (pcie->drvdata->func_config_flag) {
+ iowrite32((func_num << n), pci->dbi_base + PCI_XXXX_XXX);
+ } else {
+ WARN_ON(func_no && !pcie->drvdata->func_offset);
+ return pcie->drvdata->func_offset * func_no;
+ }
+ }
return 0;
}
Of course, I don't need to set the flag this time, because I don't use the second method(write
register method), so the code like this:
case2:
+static unsigned int ls_pcie_ep_func_conf_select(struct dw_pcie_ep *ep,
u8 func_no) {
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
struct ls_pcie_ep *pcie = to_ls_pcie_ep(pci);
u8 header_type;
of course, this code is not requied, due to the
pcie->drvdata->func_offset is 0, but I think this is more clear
if use this code.
header_type = ioread8(pci->dbi_base + PCI_HEADER_TYPE);
/*
* Read the Header Type register of config space to check
* whether this PCI device support the multiple function.
*/
if (header_type & (1 << 7)) {
WARN_ON(func_no && !pcie->drvdata->func_offset);
return pcie->drvdata->func_offset * func_no;
}
return 0;
}
Or like this:
Case3:
+static unsigned int ls_pcie_ep_func_conf_select(struct dw_pcie_ep *ep,
u8 func_no) {
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
struct ls_pcie_ep *pcie = to_ls_pcie_ep(pci);
WARN_ON(func_no && !pcie->drvdata->func_offset);
return pcie->drvdata->func_offset * func_no;
}
Of course, we can return a -1 by adjuring the (func_no && !pcie->drvdata->func_offset)
Valu in case1
Thanks
Xiaowei
>
> Thanks,
>
> Andrew Murray
>
> >
> > I have added the comments above the code, as follow, do you have any
> advice?
> > +static unsigned int ls_pcie_ep_func_conf_select(struct dw_pcie_ep *ep,
> > + u8 func_no) {
> > + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> > + struct ls_pcie_ep *pcie = to_ls_pcie_ep(pci);
> > + u8 header_type;
> > +
> > + header_type = ioread8(pci->dbi_base + PCI_HEADER_TYPE);
> > +
> > + /*
> > + * Read the Header Type register of config space to check
> > + * whether this PCI device support the multiple function.
> > + */
> > + if (header_type & (1 << 7))
> > + return pcie->drvdata->func_offset * func_no;
> > +
> > + return 0;
> > +}
> >
> > Thanks a lot for your detail comments.
> >
> > >
> > > Thanks,
> > >
> > > Andrew Murray
> > >
> > > > +}
> > > > +
> > > > +static const struct dw_pcie_ep_ops ls_pcie_ep_ops = {
> > > > .ep_init = ls_pcie_ep_init,
> > > > .raise_irq = ls_pcie_ep_raise_irq,
> > > > .get_features = ls_pcie_ep_get_features,
> > > > + .func_conf_select = ls_pcie_ep_func_conf_select, };
> > > > +
> > > > +static const struct ls_pcie_ep_drvdata ls1_ep_drvdata = {
> > > > + .ops = &ls_pcie_ep_ops,
> > > > + .dw_pcie_ops = &dw_ls_pcie_ep_ops, };
> > > > +
> > > > +static const struct ls_pcie_ep_drvdata ls2_ep_drvdata = {
> > > > + .func_offset = 0x20000,
> > > > + .ops = &ls_pcie_ep_ops,
> > > > + .dw_pcie_ops = &dw_ls_pcie_ep_ops, };
> > > > +
> > > > +static const struct of_device_id ls_pcie_ep_of_match[] = {
> > > > + { .compatible = "fsl,ls1046a-pcie-ep", .data = &ls1_ep_drvdata },
> > > > + { .compatible = "fsl,ls1088a-pcie-ep", .data = &ls2_ep_drvdata },
> > > > + { .compatible = "fsl,ls2088a-pcie-ep", .data = &ls2_ep_drvdata },
> > > > + { },
> > > > };
> > > >
> > > > static int __init ls_add_pcie_ep(struct ls_pcie_ep *pcie, @@
> > > > -98,7
> > > > +134,7 @@ static int __init ls_add_pcie_ep(struct ls_pcie_ep
> > > > +*pcie,
> > > > int ret;
> > > >
> > > > ep = &pci->ep;
> > > > - ep->ops = &pcie_ep_ops;
> > > > + ep->ops = pcie->drvdata->ops;
> > > >
> > > > res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> > > "addr_space");
> > > > if (!res)
> > > > @@ -137,14 +173,11 @@ static int __init ls_pcie_ep_probe(struct
> > > platform_device *pdev)
> > > > if (!ls_epc)
> > > > return -ENOMEM;
> > > >
> > > > - dbi_base = platform_get_resource_byname(pdev,
> IORESOURCE_MEM,
> > > "regs");
> > > > - pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base);
> > > > - if (IS_ERR(pci->dbi_base))
> > > > - return PTR_ERR(pci->dbi_base);
> > > > + pcie->drvdata = of_device_get_match_data(dev);
> > > >
> > > > - pci->dbi_base2 = pci->dbi_base + PCIE_DBI2_OFFSET;
> > > > pci->dev = dev;
> > > > - pci->ops = &ls_pcie_ep_ops;
> > > > + pci->ops = pcie->drvdata->dw_pcie_ops;
> > > > +
> > > > pcie->pci = pci;
> > > >
> > > > ls_epc->linkup_notifier = false, @@ -152,6 +185,13 @@ static int
> > > > __init ls_pcie_ep_probe(struct platform_device *pdev)
> > > >
> > > > pcie->ls_epc = ls_epc;
> > > >
> > > > + dbi_base = platform_get_resource_byname(pdev,
> IORESOURCE_MEM,
> > > "regs");
> > > > + pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base);
> > > > + if (IS_ERR(pci->dbi_base))
> > > > + return PTR_ERR(pci->dbi_base);
> > > > +
> > > > + pci->dbi_base2 = pci->dbi_base + PCIE_DBI2_OFFSET;
> > > > +
> > > > platform_set_drvdata(pdev, pcie);
> > > >
> > > > ret = ls_add_pcie_ep(pcie, pdev);
> > > > --
> > > > 2.9.5
> > > >
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* Re: [PATCH 7/8] coresight: etm4x: Add missing single-shot control API to sysfs
From: Leo Yan @ 2019-08-28 5:18 UTC (permalink / raw)
To: Mike Leach; +Cc: coresight, linux-arm-kernel, mathieu.poirier
In-Reply-To: <20190819205720.24457-8-mike.leach@linaro.org>
On Mon, Aug 19, 2019 at 09:57:19PM +0100, Mike Leach wrote:
> An API to control single-shot comparator operation was missing from sysfs.
> This adds the parameters to sysfs to allow programming of this feature.
>
> Signed-off-by: Mike Leach <mike.leach@linaro.org>
> ---
> .../coresight/coresight-etm4x-sysfs.c | 122 ++++++++++++++++++
> drivers/hwtracing/coresight/coresight-etm4x.c | 26 +++-
> drivers/hwtracing/coresight/coresight-etm4x.h | 3 +
> 3 files changed, 150 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> index 483976074779..7c019dda1236 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c
> @@ -239,6 +239,7 @@ static ssize_t reset_store(struct device *dev,
> for (i = 0; i < drvdata->nr_resource; i++)
> config->res_ctrl[i] = 0x0;
>
> + config->ss_idx = 0x0;
> for (i = 0; i < drvdata->nr_ss_cmp; i++) {
> config->ss_ctrl[i] = 0x0;
> config->ss_pe_cmp[i] = 0x0;
> @@ -1713,6 +1714,123 @@ static ssize_t res_ctrl_store(struct device *dev,
> }
> static DEVICE_ATTR_RW(res_ctrl);
>
> +static ssize_t sshot_idx_show(struct device *dev,
> + struct device_attribute *attr, char *buf)
> +{
> + unsigned long val;
> + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + struct etmv4_config *config = &drvdata->config;
> +
> + val = config->ss_idx;
> + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> +}
> +
> +static ssize_t sshot_idx_store(struct device *dev,
> + struct device_attribute *attr,
> + const char *buf, size_t size)
> +{
> + unsigned long val;
> + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + struct etmv4_config *config = &drvdata->config;
> +
> + if (kstrtoul(buf, 16, &val))
> + return -EINVAL;
> + if (val >= drvdata->nr_ss_cmp)
> + return -EINVAL;
> +
> + spin_lock(&drvdata->spinlock);
> + config->ss_idx = val;
> + spin_unlock(&drvdata->spinlock);
> + return size;
> +}
> +static DEVICE_ATTR_RW(sshot_idx);
> +
> +static ssize_t sshot_ctrl_show(struct device *dev,
> + struct device_attribute *attr,
> + char *buf)
> +{
> + unsigned long val;
> + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + struct etmv4_config *config = &drvdata->config;
> +
> + spin_lock(&drvdata->spinlock);
> + val = config->ss_ctrl[config->ss_idx];
> + spin_unlock(&drvdata->spinlock);
> + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> +}
> +
> +static ssize_t sshot_ctrl_store(struct device *dev,
> + struct device_attribute *attr,
> + const char *buf, size_t size)
> +{
> + u8 idx;
> + unsigned long val;
> + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + struct etmv4_config *config = &drvdata->config;
> +
> + if (kstrtoul(buf, 16, &val))
> + return -EINVAL;
> +
> + spin_lock(&drvdata->spinlock);
> + idx = config->ss_idx;
> + config->ss_ctrl[idx] = val & GENMASK(24, 0);
> + /* must clear bit 31 in related status register on programming */
> + config->ss_status[idx] &= ~BIT(31);
Since function etm4_enable_hw() will clear ss_status's bit 31 when
program TRCSSCSRn, so is here redundant to clear bit 31?
> + spin_unlock(&drvdata->spinlock);
> + return size;
> +}
> +static DEVICE_ATTR_RW(sshot_ctrl);
> +
> +static ssize_t sshot_status_show(struct device *dev,
> + struct device_attribute *attr, char *buf)
> +{
> + unsigned long val;
> + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + struct etmv4_config *config = &drvdata->config;
> +
> + spin_lock(&drvdata->spinlock);
> + val = config->ss_status[config->ss_idx];
> + spin_unlock(&drvdata->spinlock);
> + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> +}
> +static DEVICE_ATTR_RO(sshot_status);
> +
> +static ssize_t sshot_pe_ctrl_show(struct device *dev,
> + struct device_attribute *attr,
> + char *buf)
> +{
> + unsigned long val;
> + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + struct etmv4_config *config = &drvdata->config;
> +
> + spin_lock(&drvdata->spinlock);
> + val = config->ss_pe_cmp[config->ss_idx];
> + spin_unlock(&drvdata->spinlock);
> + return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
> +}
> +
> +static ssize_t sshot_pe_ctrl_store(struct device *dev,
> + struct device_attribute *attr,
> + const char *buf, size_t size)
> +{
> + u8 idx;
> + unsigned long val;
> + struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
> + struct etmv4_config *config = &drvdata->config;
> +
> + if (kstrtoul(buf, 16, &val))
> + return -EINVAL;
> +
> + spin_lock(&drvdata->spinlock);
> + idx = config->ss_idx;
> + config->ss_ctrl[idx] = val & GENMASK(7, 0);
> + /* must clear bit 31 in related status register on programming */
> + config->ss_status[idx] &= ~BIT(31);
Same question for if it's redundant to clear bit 31?
Thanks,
Leo Yan
> + spin_unlock(&drvdata->spinlock);
> + return size;
> +}
> +static DEVICE_ATTR_RW(sshot_pe_ctrl);
> +
> static ssize_t ctxid_idx_show(struct device *dev,
> struct device_attribute *attr,
> char *buf)
> @@ -2169,6 +2287,10 @@ static struct attribute *coresight_etmv4_attrs[] = {
> &dev_attr_addr_exlevel_s_ns.attr,
> &dev_attr_addr_cmp_view.attr,
> &dev_attr_vinst_pe_cmp_start_stop.attr,
> + &dev_attr_sshot_idx.attr,
> + &dev_attr_sshot_ctrl.attr,
> + &dev_attr_sshot_pe_ctrl.attr,
> + &dev_attr_sshot_status.attr,
> &dev_attr_seq_idx.attr,
> &dev_attr_seq_state.attr,
> &dev_attr_seq_event.attr,
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
> index d8b078d0cc7f..fb7083218410 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.c
> @@ -149,6 +149,9 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
> drvdata->base + TRCRSCTLRn(i));
>
> for (i = 0; i < drvdata->nr_ss_cmp; i++) {
> + /* always clear status bit on restart if using single-shot */
> + if (config->ss_ctrl[i] || config->ss_pe_cmp[i])
> + config->ss_status[i] &= ~BIT(31);
> writel_relaxed(config->ss_ctrl[i],
> drvdata->base + TRCSSCCRn(i));
> writel_relaxed(config->ss_status[i],
> @@ -448,6 +451,9 @@ static void etm4_disable_hw(void *info)
> {
> u32 control;
> struct etmv4_drvdata *drvdata = info;
> + struct etmv4_config *config = &drvdata->config;
> + struct device *etm_dev = &drvdata->csdev->dev;
> + int i;
>
> CS_UNLOCK(drvdata->base);
>
> @@ -470,6 +476,18 @@ static void etm4_disable_hw(void *info)
> isb();
> writel_relaxed(control, drvdata->base + TRCPRGCTLR);
>
> + /* wait for TRCSTATR.PMSTABLE to go to '1' */
> + if (coresight_timeout(drvdata->base, TRCSTATR,
> + TRCSTATR_PMSTABLE_BIT, 1))
> + dev_err(etm_dev,
> + "timeout while waiting for PM stable Trace Status\n");
> +
> + /* read the status of the single shot comparators */
> + for (i = 0; i < drvdata->nr_ss_cmp; i++) {
> + config->ss_status[i] =
> + readl_relaxed(drvdata->base + TRCSSCSRn(i));
> + }
> +
> coresight_disclaim_device_unlocked(drvdata->base);
>
> CS_LOCK(drvdata->base);
> @@ -576,6 +594,7 @@ static void etm4_init_arch_data(void *info)
> u32 etmidr4;
> u32 etmidr5;
> struct etmv4_drvdata *drvdata = info;
> + int i;
>
> /* Make sure all registers are accessible */
> etm4_os_unlock(drvdata);
> @@ -699,9 +718,14 @@ static void etm4_init_arch_data(void *info)
> drvdata->nr_resource = BMVAL(etmidr4, 16, 19) + 1;
> /*
> * NUMSSCC, bits[23:20] the number of single-shot
> - * comparator control for tracing
> + * comparator control for tracing. Read any status regs as these
> + * also contain RO capability data.
> */
> drvdata->nr_ss_cmp = BMVAL(etmidr4, 20, 23);
> + for (i = 0; i < drvdata->nr_ss_cmp; i++) {
> + drvdata->config.ss_status[i] =
> + readl_relaxed(drvdata->base + TRCSSCSRn(i));
> + }
> /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
> drvdata->numcidc = BMVAL(etmidr4, 24, 27);
> /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
> index 60bc2fb5159b..be8b32ea1654 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x.h
> +++ b/drivers/hwtracing/coresight/coresight-etm4x.h
> @@ -175,6 +175,7 @@
> ETM_MODE_EXCL_USER)
>
> #define TRCSTATR_IDLE_BIT 0
> +#define TRCSTATR_PMSTABLE_BIT 1
> #define ETM_DEFAULT_ADDR_COMP 0
>
> /* PowerDown Control Register bits */
> @@ -226,6 +227,7 @@
> * @cntr_val: Sets or returns the value for a counter.
> * @res_idx: Resource index selector.
> * @res_ctrl: Controls the selection of the resources in the trace unit.
> + * @ss_idx: Single-shot index selector.
> * @ss_ctrl: Controls the corresponding single-shot comparator resource.
> * @ss_status: The status of the corresponding single-shot comparator.
> * @ss_pe_cmp: Selects the PE comparator inputs for Single-shot control.
> @@ -269,6 +271,7 @@ struct etmv4_config {
> u32 cntr_val[ETMv4_MAX_CNTR];
> u8 res_idx;
> u32 res_ctrl[ETM_MAX_RES_SEL];
> + u8 ss_idx;
> u32 ss_ctrl[ETM_MAX_SS_CMP];
> u32 ss_status[ETM_MAX_SS_CMP];
> u32 ss_pe_cmp[ETM_MAX_SS_CMP];
> --
> 2.17.1
>
> _______________________________________________
> CoreSight mailing list
> CoreSight@lists.linaro.org
> https://lists.linaro.org/mailman/listinfo/coresight
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* [PATCH 1/2] dt-bindings: clock: mediatek: add pericfg for MT8183
From: Chunfeng Yun @ 2019-08-28 5:55 UTC (permalink / raw)
To: Rob Herring, Stephen Boyd
Cc: Mark Rutland, devicetree, Ryder Lee, Weiyi Lu, Michael Turquette,
linux-kernel, linux-clk, Chunfeng Yun, Nicolas Boichat,
linux-mediatek, Matthias Brugger, Erin Lo, linux-arm-kernel
This patch adds binding of pericfg for MT8183.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
.../devicetree/bindings/arm/mediatek/mediatek,pericfg.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
index 4c7e478117a0..ecf027a9003a 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,pericfg.txt
@@ -14,6 +14,7 @@ Required Properties:
- "mediatek,mt7629-pericfg", "syscon"
- "mediatek,mt8135-pericfg", "syscon"
- "mediatek,mt8173-pericfg", "syscon"
+ - "mediatek,mt8183-pericfg", "syscon"
- #clock-cells: Must be 1
- #reset-cells: Must be 1
--
2.23.0
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* [PATCH 2/2] clk: mediatek: add pericfg clocks for MT8183
From: Chunfeng Yun @ 2019-08-28 5:55 UTC (permalink / raw)
To: Rob Herring, Stephen Boyd
Cc: Mark Rutland, devicetree, Ryder Lee, Weiyi Lu, Michael Turquette,
linux-kernel, linux-clk, Chunfeng Yun, Nicolas Boichat,
linux-mediatek, Matthias Brugger, Erin Lo, linux-arm-kernel
In-Reply-To: <1566971755-21217-1-git-send-email-chunfeng.yun@mediatek.com>
Add pericfg clocks for MT8183, it's used when support USB
remote wakeup
Cc: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
drivers/clk/mediatek/clk-mt8183.c | 35 ++++++++++++++++++++++++++
include/dt-bindings/clock/mt8183-clk.h | 4 +++
2 files changed, 39 insertions(+)
diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c
index 1aa5f4059251..b19221bad0c9 100644
--- a/drivers/clk/mediatek/clk-mt8183.c
+++ b/drivers/clk/mediatek/clk-mt8183.c
@@ -999,6 +999,25 @@ static const struct mtk_gate infra_clks[] = {
"msdc50_0_sel", 24),
};
+static const struct mtk_gate_regs peri_cg_regs = {
+ .set_ofs = 0x20c,
+ .clr_ofs = 0x20c,
+ .sta_ofs = 0x20c,
+};
+
+#define GATE_PERI(_id, _name, _parent, _shift) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &peri_cg_regs, \
+ .shift = _shift, \
+ .ops = &mtk_clk_gate_ops_no_setclr_inv, \
+}
+
+static const struct mtk_gate peri_clks[] = {
+ GATE_PERI(CLK_PERI_AXI, "periaxi", "axi_sel", 31),
+};
+
static const struct mtk_gate_regs apmixed_cg_regs = {
.set_ofs = 0x20,
.clr_ofs = 0x20,
@@ -1194,6 +1213,19 @@ static int clk_mt8183_infra_probe(struct platform_device *pdev)
return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
}
+static int clk_mt8183_peri_probe(struct platform_device *pdev)
+{
+ struct clk_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+
+ clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
+
+ mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
+ clk_data);
+
+ return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+
static int clk_mt8183_mcu_probe(struct platform_device *pdev)
{
struct clk_onecell_data *clk_data;
@@ -1223,6 +1255,9 @@ static const struct of_device_id of_match_clk_mt8183[] = {
}, {
.compatible = "mediatek,mt8183-infracfg",
.data = clk_mt8183_infra_probe,
+ }, {
+ .compatible = "mediatek,mt8183-pericfg",
+ .data = clk_mt8183_peri_probe,
}, {
.compatible = "mediatek,mt8183-mcucfg",
.data = clk_mt8183_mcu_probe,
diff --git a/include/dt-bindings/clock/mt8183-clk.h b/include/dt-bindings/clock/mt8183-clk.h
index 0046506eb24c..a7b470b0ec8a 100644
--- a/include/dt-bindings/clock/mt8183-clk.h
+++ b/include/dt-bindings/clock/mt8183-clk.h
@@ -284,6 +284,10 @@
#define CLK_INFRA_FBIST2FPC 100
#define CLK_INFRA_NR_CLK 101
+/* PERICFG */
+#define CLK_PERI_AXI 0
+#define CLK_PERI_NR_CLK 1
+
/* MFGCFG */
#define CLK_MFG_BG3D 0
#define CLK_MFG_NR_CLK 1
--
2.23.0
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* [PATCH 3/6] usb: mtu3: support ip-sleep wakeup for MT8183
From: Chunfeng Yun @ 2019-08-28 6:20 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring
Cc: Mark Rutland, devicetree, Mathias Nyman, linux-usb, linux-kernel,
Chunfeng Yun, linux-mediatek, Matthias Brugger, linux-arm-kernel
In-Reply-To: <1566973261-21677-1-git-send-email-chunfeng.yun@mediatek.com>
Support USB wakeup by ip-sleep mode for MT8183, it's similar to
MT8173
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
drivers/usb/mtu3/mtu3_host.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/mtu3/mtu3_host.c b/drivers/usb/mtu3/mtu3_host.c
index c871b94f3e6f..001b17aeb1eb 100644
--- a/drivers/usb/mtu3/mtu3_host.c
+++ b/drivers/usb/mtu3/mtu3_host.c
@@ -18,6 +18,12 @@
#include "mtu3.h"
#include "mtu3_dr.h"
+/* mt8183 etc */
+#define PERI_WK_CTRL0 0x20
+#define WC0_IS_C(x) (((x) & 0xf) << 28) /* cycle debounce */
+#define WC0_IS_EN BIT(12)
+#define WC0_IS_P BIT(6) /* polarity for ip sleep */
+
/* mt8173 etc */
#define PERI_WK_CTRL1 0x4
#define WC1_IS_C(x) (((x) & 0xf) << 26) /* cycle debounce */
@@ -30,7 +36,8 @@
#define SSC_SPM_INT_EN BIT(1)
enum ssusb_uwk_vers {
- SSUSB_UWK_V1 = 1,
+ SSUSB_UWK_V0 = 0,
+ SSUSB_UWK_V1,
SSUSB_UWK_V2,
};
@@ -43,6 +50,11 @@ static void ssusb_wakeup_ip_sleep_set(struct ssusb_mtk *ssusb, bool enable)
u32 reg, msk, val;
switch (ssusb->uwk_vers) {
+ case SSUSB_UWK_V0:
+ reg = ssusb->uwk_reg_base + PERI_WK_CTRL0;
+ msk = WC0_IS_EN | WC0_IS_C(0xf) | WC0_IS_P;
+ val = enable ? (WC0_IS_EN | WC0_IS_C(0x8)) : 0;
+ break;
case SSUSB_UWK_V1:
reg = ssusb->uwk_reg_base + PERI_WK_CTRL1;
msk = WC1_IS_EN | WC1_IS_C(0xf) | WC1_IS_P;
--
2.23.0
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* [PATCH 2/6] dt-bindings: usb: mtk-xhci: support USB wakeup for MT8183
From: Chunfeng Yun @ 2019-08-28 6:20 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring
Cc: Mark Rutland, devicetree, Mathias Nyman, linux-usb, linux-kernel,
Chunfeng Yun, linux-mediatek, Matthias Brugger, linux-arm-kernel
In-Reply-To: <1566973261-21677-1-git-send-email-chunfeng.yun@mediatek.com>
Support USB wakeup by ip-sleep mode for MT8183
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt
index 266c2d917a28..9a0a9eb0456f 100644
--- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt
+++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt
@@ -41,6 +41,7 @@ Optional properties:
"wakeup-source", and has two arguments:
- the first one : register base address of the glue layer in syscon;
- the second one : hardware version of the glue layer
+ - 0 : used by mt8183 etc
- 1 : used by mt8173 etc
- 2 : used by mt2712 etc
- mediatek,u3p-dis-msk : mask to disable u3ports, bit0 for u3port0,
--
2.23.0
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* [PATCH 4/6] usb: mtk-xhci: support ip-sleep wakeup for MT8183
From: Chunfeng Yun @ 2019-08-28 6:20 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring
Cc: Mark Rutland, devicetree, Mathias Nyman, linux-usb, linux-kernel,
Chunfeng Yun, linux-mediatek, Matthias Brugger, linux-arm-kernel
In-Reply-To: <1566973261-21677-1-git-send-email-chunfeng.yun@mediatek.com>
Support USB wakeup by ip-sleep mode for MT8183, it's similar to
MT8173
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
drivers/usb/host/xhci-mtk.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c
index 026fe18972d3..4b59f2978954 100644
--- a/drivers/usb/host/xhci-mtk.c
+++ b/drivers/usb/host/xhci-mtk.c
@@ -57,6 +57,12 @@
#define CTRL_U2_FORCE_PLL_STB BIT(28)
/* usb remote wakeup registers in syscon */
+/* mt8183 etc */
+#define PERI_WK_CTRL0 0x20
+#define WC0_IS_C(x) (((x) & 0xf) << 28) /* cycle debounce */
+#define WC0_IS_EN BIT(12)
+#define WC0_IS_P BIT(6) /* polarity for ip sleep */
+
/* mt8173 etc */
#define PERI_WK_CTRL1 0x4
#define WC1_IS_C(x) (((x) & 0xf) << 26) /* cycle debounce */
@@ -69,7 +75,8 @@
#define SSC_SPM_INT_EN BIT(1)
enum ssusb_uwk_vers {
- SSUSB_UWK_V1 = 1,
+ SSUSB_UWK_V0 = 0,
+ SSUSB_UWK_V1,
SSUSB_UWK_V2,
};
@@ -282,6 +289,11 @@ static void usb_wakeup_ip_sleep_set(struct xhci_hcd_mtk *mtk, bool enable)
u32 reg, msk, val;
switch (mtk->uwk_vers) {
+ case SSUSB_UWK_V0:
+ reg = mtk->uwk_reg_base + PERI_WK_CTRL0;
+ msk = WC0_IS_EN | WC0_IS_C(0xf) | WC0_IS_P;
+ val = enable ? (WC0_IS_EN | WC0_IS_C(0x8)) : 0;
+ break;
case SSUSB_UWK_V1:
reg = mtk->uwk_reg_base + PERI_WK_CTRL1;
msk = WC1_IS_EN | WC1_IS_C(0xf) | WC1_IS_P;
--
2.23.0
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* [PATCH 1/6] dt-bindings: usb: mtu3: support USB wakeup for MT8183
From: Chunfeng Yun @ 2019-08-28 6:20 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring
Cc: Mark Rutland, devicetree, Mathias Nyman, linux-usb, linux-kernel,
Chunfeng Yun, linux-mediatek, Matthias Brugger, linux-arm-kernel
In-Reply-To: <1566973261-21677-1-git-send-email-chunfeng.yun@mediatek.com>
Support USB wakeup by ip-sleep mode for MT8183
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
Documentation/devicetree/bindings/usb/mediatek,mtu3.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt b/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt
index 3382b5cb471d..ed954bedcd2f 100644
--- a/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt
+++ b/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt
@@ -48,6 +48,7 @@ Optional properties:
"wakeup-source", and has two arguments:
- the first one : register base address of the glue layer in syscon;
- the second one : hardware version of the glue layer
+ - 0 : used by mt8183 etc
- 1 : used by mt8173 etc
- 2 : used by mt2712 etc
- mediatek,u3p-dis-msk : mask to disable u3ports, bit0 for u3port0,
--
2.23.0
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* [PATCH 0/6] add support USB for MT8183
From: Chunfeng Yun @ 2019-08-28 6:20 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring
Cc: Mark Rutland, devicetree, Mathias Nyman, linux-usb, linux-kernel,
Chunfeng Yun, linux-mediatek, Matthias Brugger, linux-arm-kernel
This series support USB DRD controller and enable it's remote
wakeup functoin for MT8183, they depend on the following
series patches:
1. this series add support MT6358 PMIC
[v5,01/10] mfd: mt6397: clean up code
https://patchwork.kernel.org/patch/11110487/
2. this series add support pericfg syscon
[1/2] dt-bindings: clock: mediatek: add pericfg for MT8183
https://patchwork.kernel.org/patch/11117799/
Chunfeng Yun (6):
dt-bindings: usb: mtu3: support USB wakeup for MT8183
dt-bindings: usb: mtk-xhci: support USB wakeup for MT8183
usb: mtu3: support ip-sleep wakeup for MT8183
usb: mtk-xhci: support ip-sleep wakeup for MT8183
arm64: dts: mt8183: add usb and phy nodes
arm64: dts: mt8183: enable USB remote wakeup
.../bindings/usb/mediatek,mtk-xhci.txt | 1 +
.../devicetree/bindings/usb/mediatek,mtu3.txt | 1 +
arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 23 +++++++
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 63 +++++++++++++++++++
drivers/usb/host/xhci-mtk.c | 14 ++++-
drivers/usb/mtu3/mtu3_host.c | 14 ++++-
6 files changed, 114 insertions(+), 2 deletions(-)
--
2.23.0
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* [PATCH 5/6] arm64: dts: mt8183: add usb and phy nodes
From: Chunfeng Yun @ 2019-08-28 6:21 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring
Cc: Mark Rutland, devicetree, Mathias Nyman, linux-usb, linux-kernel,
Chunfeng Yun, linux-mediatek, Matthias Brugger, linux-arm-kernel
In-Reply-To: <1566973261-21677-1-git-send-email-chunfeng.yun@mediatek.com>
Add USB related nodes for MT8183, set it as host mode by default.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 22 +++++++++
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 55 +++++++++++++++++++++
2 files changed, 77 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
index d8e555cbb5d3..142ff52f0f42 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
@@ -6,7 +6,9 @@
*/
/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
#include "mt8183.dtsi"
+#include "mt6358.dtsi"
/ {
model = "MediaTek MT8183 evaluation board";
@@ -24,6 +26,16 @@
chosen {
stdout-path = "serial0:921600n8";
};
+
+ usb_vbus: regulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "p0_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&pio 42 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
};
&auxadc {
@@ -135,6 +147,16 @@
};
+&ssusb {
+ vusb33-supply = <&mt6358_vusb_reg>;
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usb_host {
+ status = "okay";
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index c2749c4631bc..28da334237c6 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/clock/mt8183-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/phy/phy.h>
#include "mt8183-pinfunc.h"
/ {
@@ -372,6 +373,35 @@
status = "disabled";
};
+ ssusb: usb@11201000 {
+ compatible = "mediatek,mt8183-mtu3", "mediatek,mtu3";
+ reg = <0 0x11201000 0 0x2e00>,
+ <0 0x11203e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
+ phys = <&u2port0 PHY_TYPE_USB2>,
+ <&u3port0 PHY_TYPE_USB3>;
+ clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
+ <&infracfg CLK_INFRA_USB>;
+ clock-names = "sys_ck", "ref_ck";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ usb_host: xhci@11200000 {
+ compatible = "mediatek,mt8183-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x11200000 0 0x1000>;
+ reg-names = "mac";
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
+ <&infracfg CLK_INFRA_USB>;
+ clock-names = "sys_ck", "ref_ck";
+ status = "disabled";
+ };
+ };
+
audiosys: syscon@11220000 {
compatible = "mediatek,mt8183-audiosys", "syscon";
reg = <0 0x11220000 0 0x1000>;
@@ -384,6 +414,31 @@
reg = <0 0x11f10000 0 0x1000>;
};
+ u3phy: usb-phy@11f40000 {
+ compatible = "mediatek,mt8183-tphy",
+ "mediatek,generic-tphy-v2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x11f40000 0x1000>;
+ status = "okay";
+
+ u2port0: usb-phy@0 {
+ reg = <0x0 0x700>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+
+ u3port0: usb-phy@0700 {
+ reg = <0x0700 0x900>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+ };
+
mfgcfg: syscon@13000000 {
compatible = "mediatek,mt8183-mfgcfg", "syscon";
reg = <0 0x13000000 0 0x1000>;
--
2.23.0
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* [PATCH 6/6] arm64: dts: mt8183: enable USB remote wakeup
From: Chunfeng Yun @ 2019-08-28 6:21 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring
Cc: Mark Rutland, devicetree, Mathias Nyman, linux-usb, linux-kernel,
Chunfeng Yun, linux-mediatek, Matthias Brugger, linux-arm-kernel
In-Reply-To: <1566973261-21677-1-git-send-email-chunfeng.yun@mediatek.com>
Enable USB remote wakeup for MT8183
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 1 +
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 8 ++++++++
2 files changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
index 142ff52f0f42..077256f3397b 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
@@ -150,6 +150,7 @@
&ssusb {
vusb33-supply = <&mt6358_vusb_reg>;
dr_mode = "host";
+ wakeup-source;
status = "okay";
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 28da334237c6..c20cc0e8c2b4 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -215,6 +215,13 @@
#clock-cells = <1>;
};
+ pericfg: syscon@10003000 {
+ compatible = "mediatek,mt8183-pericfg", "syscon";
+ reg = <0 0x10003000 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
pio: pinctrl@10005000 {
compatible = "mediatek,mt8183-pinctrl";
reg = <0 0x10005000 0 0x1000>,
@@ -384,6 +391,7 @@
clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
<&infracfg CLK_INFRA_USB>;
clock-names = "sys_ck", "ref_ck";
+ mediatek,syscon-wakeup = <&pericfg 0x400 0>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
--
2.23.0
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* Re: [PATCH net-next v2 2/3] dt-bindings: net: dsa: mt7530: Add support for port 5
From: René van Dorst @ 2019-08-28 6:35 UTC (permalink / raw)
To: Rob Herring
Cc: Andrew Lunn, Florian Fainelli, Frank Wunderlich, netdev,
Sean Wang, linux-mips, David S . Miller, devicetree,
linux-mediatek, John Crispin, Matthias Brugger, Vivien Didelot,
linux-arm-kernel
In-Reply-To: <20190827222251.GA30507@bogus>
Hi Rob,
Quoting Rob Herring <robh@kernel.org>:
> On Wed, Aug 21, 2019 at 04:45:46PM +0200, René van Dorst wrote:
>> MT7530 port 5 has many modes/configurations.
>> Update the documentation how to use port 5.
>>
>> Signed-off-by: René van Dorst <opensource@vdorst.com>
>> Cc: devicetree@vger.kernel.org
>> Cc: Rob Herring <robh@kernel.org>
>
>> v1->v2:
>> * Adding extra note about RGMII2 and gpio use.
>> rfc->v1:
>> * No change
>
> The changelog goes below the '---'
>
Thanks for the review,
I shall fix that.
>> ---
>> .../devicetree/bindings/net/dsa/mt7530.txt | 218 ++++++++++++++++++
>> 1 file changed, 218 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/net/dsa/mt7530.txt
>> b/Documentation/devicetree/bindings/net/dsa/mt7530.txt
>> index 47aa205ee0bd..43993aae3f9c 100644
>> --- a/Documentation/devicetree/bindings/net/dsa/mt7530.txt
>> +++ b/Documentation/devicetree/bindings/net/dsa/mt7530.txt
>> @@ -35,6 +35,42 @@ Required properties for the child nodes within
>> ports container:
>> - phy-mode: String, must be either "trgmii" or "rgmii" for port labeled
>> "cpu".
>>
>> +Port 5 of the switch is muxed between:
>> +1. GMAC5: GMAC5 can interface with another external MAC or PHY.
>> +2. PHY of port 0 or port 4: PHY interfaces with an external MAC
>> like 2nd GMAC
>> + of the SOC. Used in many setups where port 0/4 becomes the WAN port.
>> + Note: On a MT7621 SOC with integrated switch: 2nd GMAC can only
>> connected to
>> + GMAC5 when the gpios for RGMII2 (GPIO 22-33) are not used and not
>> + connected to external component!
>> +
>> +Port 5 modes/configurations:
>> +1. Port 5 is disabled and isolated: An external phy can interface
>> to the 2nd
>> + GMAC of the SOC.
>> + In the case of a build-in MT7530 switch, port 5 shares the
>> RGMII bus with 2nd
>> + GMAC and an optional external phy. Mind the GPIO/pinctl
>> settings of the SOC!
>> +2. Port 5 is muxed to PHY of port 0/4: Port 0/4 interfaces with 2nd GMAC.
>> + It is a simple MAC to PHY interface, port 5 needs to be setup
>> for xMII mode
>> + and RGMII delay.
>> +3. Port 5 is muxed to GMAC5 and can interface to an external phy.
>> + Port 5 becomes an extra switch port.
>> + Only works on platform where external phy TX<->RX lines are swapped.
>> + Like in the Ubiquiti ER-X-SFP.
>> +4. Port 5 is muxed to GMAC5 and interfaces with the 2nd GAMC as
>> 2nd CPU port.
>> + Currently a 2nd CPU port is not supported by DSA code.
>> +
>> +Depending on how the external PHY is wired:
>> +1. normal: The PHY can only connect to 2nd GMAC but not to the switch
>> +2. swapped: RGMII TX, RX are swapped; external phy interface with
>> the switch as
>> + a ethernet port. But can't interface to the 2nd GMAC.
>> +
>> +Based on the DT the port 5 mode is configured.
>> +
>> +Driver tries to lookup the phy-handle of the 2nd GMAC of the master device.
>> +When phy-handle matches PHY of port 0 or 4 then port 5 set-up as mode 2.
>> +phy-mode must be set, see also example 2 below!
>> + * mt7621: phy-mode = "rgmii-txid";
>> + * mt7623: phy-mode = "rgmii";
>> +
>> See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list
>> of additional
>> required, optional properties and how the integrated switch subnodes must
>> be specified.
>> @@ -94,3 +130,185 @@ Example:
>> };
>> };
>> };
>> +
>> +Example 2: MT7621: Port 4 is WAN port: 2nd GMAC -> Port 5 -> PHY port 4.
>> +
>> +ð {
>> + status = "okay";
>
> Don't show status in examples.
OK.
> This should show the complete node.
>
To be clear, I should take ethernet node from the mt7621.dtsi [0] or
mt7623.dtsi
[1] and insert the example below?, right?
Greats,
René
[0]:
https://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git/tree/drivers/staging/mt7621-dts/mt7621.dtsi#n397
[1]:
https://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next.git/tree/arch/arm/boot/dts/mt7623.dtsi#n1023
>> +
>> + gmac0: mac@0 {
>> + compatible = "mediatek,eth-mac";
>> + reg = <0>;
>> + phy-mode = "rgmii";
>> +
>> + fixed-link {
>> + speed = <1000>;
>> + full-duplex;
>> + pause;
>> + };
>> + };
>> +
>> + gmac1: mac@1 {
>> + compatible = "mediatek,eth-mac";
>> + reg = <1>;
>> + phy-mode = "rgmii-txid";
>> + phy-handle = <&phy4>;
>> + };
>> +
>> + mdio: mdio-bus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + /* Internal phy */
>> + phy4: ethernet-phy@4 {
>> + reg = <4>;
>> + };
>> +
>> + mt7530: switch@1f {
>> + compatible = "mediatek,mt7621";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + reg = <0x1f>;
>> + pinctrl-names = "default";
>> + mediatek,mcm;
>> +
>> + resets = <&rstctrl 2>;
>> + reset-names = "mcm";
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> + label = "lan0";
>> + };
>> +
>> + port@1 {
>> + reg = <1>;
>> + label = "lan1";
>> + };
>> +
>> + port@2 {
>> + reg = <2>;
>> + label = "lan2";
>> + };
>> +
>> + port@3 {
>> + reg = <3>;
>> + label = "lan3";
>> + };
>> +
>> +/* Commented out. Port 4 is handled by 2nd GMAC.
>> + port@4 {
>> + reg = <4>;
>> + label = "lan4";
>> + };
>> +*/
>> +
>> + cpu_port0: port@6 {
>> + reg = <6>;
>> + label = "cpu";
>> + ethernet = <&gmac0>;
>> + phy-mode = "rgmii";
>> +
>> + fixed-link {
>> + speed = <1000>;
>> + full-duplex;
>> + pause;
>> + };
>> + };
>> + };
>> + };
>> + };
>> +};
>> +
>> +Example 3: MT7621: Port 5 is connected to external PHY: Port 5 ->
>> external PHY.
>> +
>> +ð {
>> + status = "okay";
>> +
>> + gmac0: mac@0 {
>> + compatible = "mediatek,eth-mac";
>> + reg = <0>;
>> + phy-mode = "rgmii";
>> +
>> + fixed-link {
>> + speed = <1000>;
>> + full-duplex;
>> + pause;
>> + };
>> + };
>> +
>> + mdio: mdio-bus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + /* External phy */
>> + ephy5: ethernet-phy@7 {
>> + reg = <7>;
>> + };
>> +
>> + mt7530: switch@1f {
>> + compatible = "mediatek,mt7621";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + reg = <0x1f>;
>> + pinctrl-names = "default";
>> + mediatek,mcm;
>> +
>> + resets = <&rstctrl 2>;
>> + reset-names = "mcm";
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> + label = "lan0";
>> + };
>> +
>> + port@1 {
>> + reg = <1>;
>> + label = "lan1";
>> + };
>> +
>> + port@2 {
>> + reg = <2>;
>> + label = "lan2";
>> + };
>> +
>> + port@3 {
>> + reg = <3>;
>> + label = "lan3";
>> + };
>> +
>> + port@4 {
>> + reg = <4>;
>> + label = "lan4";
>> + };
>> +
>> + port@5 {
>> + reg = <5>;
>> + label = "lan5";
>> + phy-mode = "rgmii";
>> + phy-handle = <&ephy5>;
>> + };
>> +
>> + cpu_port0: port@6 {
>> + reg = <6>;
>> + label = "cpu";
>> + ethernet = <&gmac0>;
>> + phy-mode = "rgmii";
>> +
>> + fixed-link {
>> + speed = <1000>;
>> + full-duplex;
>> + pause;
>> + };
>> + };
>> + };
>> + };
>> + };
>> +};
>> --
>> 2.20.1
>>
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* [PATCH 2/5] crypto: mediatek: fix uninitialized value of gctx->textlen
From: Vic Wu @ 2019-08-28 6:37 UTC (permalink / raw)
To: Herbert Xu
Cc: Ryder Lee, linux-kernel, linux-mediatek, linux-crypto, Vic Wu,
David S . Miller, linux-arm-kernel
In-Reply-To: <20190828063716.22689-1-vic.wu@mediatek.com>
From: Ryder Lee <ryder.lee@mediatek.com>
Add a pre-computed text length to avoid uninitialized value in the check.
Fixes: e47270665b5f ("crypto: mediatek - Add empty messages check in GCM mode")
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Vic Wu <vic.wu@mediatek.com>
---
drivers/crypto/mediatek/mtk-aes.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/crypto/mediatek/mtk-aes.c b/drivers/crypto/mediatek/mtk-aes.c
index 43fcc8b5..425d7f3f 100644
--- a/drivers/crypto/mediatek/mtk-aes.c
+++ b/drivers/crypto/mediatek/mtk-aes.c
@@ -896,14 +896,11 @@ static int mtk_aes_gcm_start(struct mtk_cryp *cryp, struct mtk_aes_rec *aes)
aes->resume = mtk_aes_transfer_complete;
/* Compute total process length. */
aes->total = len + gctx->authsize;
- /* Compute text length. */
- gctx->textlen = req->cryptlen;
/* Hardware will append authenticated tag to output buffer */
scatterwalk_map_and_copy(tag, req->dst, len, gctx->authsize, 1);
} else {
aes->resume = mtk_aes_gcm_tag_verify;
aes->total = len;
- gctx->textlen = req->cryptlen - gctx->authsize;
}
return mtk_aes_gcm_dma(cryp, aes, req->src, req->dst, len);
@@ -915,19 +912,22 @@ static int mtk_aes_gcm_crypt(struct aead_request *req, u64 mode)
struct mtk_aes_gcm_ctx *gctx = mtk_aes_gcm_ctx_cast(ctx);
struct mtk_aes_reqctx *rctx = aead_request_ctx(req);
struct mtk_cryp *cryp;
+ bool enc = !!(mode & AES_FLAGS_ENCRYPT);
cryp = mtk_aes_find_dev(ctx);
if (!cryp)
return -ENODEV;
+ /* Compute text length. */
+ gctx->textlen = req->cryptlen - (enc ? 0 : gctx->authsize);
+
/* Empty messages are not supported yet */
if (!gctx->textlen && !req->assoclen)
return -EINVAL;
rctx->mode = AES_FLAGS_GCM | mode;
- return mtk_aes_handle_queue(cryp, !!(mode & AES_FLAGS_ENCRYPT),
- &req->base);
+ return mtk_aes_handle_queue(cryp, enc, &req->base);
}
/*
--
2.17.1
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* [PATCH 5/5] crypto: mediatek: fix incorrect crypto key setting
From: Vic Wu @ 2019-08-28 6:37 UTC (permalink / raw)
To: Herbert Xu
Cc: Ryder Lee, linux-kernel, linux-mediatek, linux-crypto, Vic Wu,
David S . Miller, linux-arm-kernel
In-Reply-To: <20190828063716.22689-1-vic.wu@mediatek.com>
Record crypto key to context during setkey and set the key to
transform state buffer in encrypt/decrypt process.
Signed-off-by: Vic Wu <vic.wu@mediatek.com>
---
drivers/crypto/mediatek/mtk-aes.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/crypto/mediatek/mtk-aes.c b/drivers/crypto/mediatek/mtk-aes.c
index 9eeb8b8d..05f21dc8 100644
--- a/drivers/crypto/mediatek/mtk-aes.c
+++ b/drivers/crypto/mediatek/mtk-aes.c
@@ -107,6 +107,7 @@ struct mtk_aes_reqctx {
struct mtk_aes_base_ctx {
struct mtk_cryp *cryp;
u32 keylen;
+ __le32 key[12];
__le32 keymode;
mtk_aes_fn start;
@@ -541,6 +542,8 @@ static int mtk_aes_handle_queue(struct mtk_cryp *cryp, u8 id,
backlog->complete(backlog, -EINPROGRESS);
ctx = crypto_tfm_ctx(areq->tfm);
+ /* Write key into state buffer */
+ memcpy(ctx->info.state, ctx->key, sizeof(ctx->key));
aes->areq = areq;
aes->ctx = ctx;
@@ -660,7 +663,7 @@ static int mtk_aes_setkey(struct crypto_ablkcipher *tfm,
}
ctx->keylen = SIZE_IN_WORDS(keylen);
- mtk_aes_write_state_le(ctx->info.state, (const u32 *)key, keylen);
+ mtk_aes_write_state_le(ctx->key, (const u32 *)key, keylen);
return 0;
}
@@ -1093,10 +1096,8 @@ static int mtk_aes_gcm_setkey(struct crypto_aead *aead, const u8 *key,
if (err)
goto out;
- /* Write key into state buffer */
- mtk_aes_write_state_le(ctx->info.state, (const u32 *)key, keylen);
- /* Write key(H) into state buffer */
- mtk_aes_write_state_be(ctx->info.state + ctx->keylen, data->hash,
+ mtk_aes_write_state_le(ctx->key, (const u32 *)key, keylen);
+ mtk_aes_write_state_be(ctx->key + ctx->keylen, data->hash,
AES_BLOCK_SIZE);
out:
kzfree(data);
--
2.17.1
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* [PATCH 1/5] crypto: mediatek: move mtk_aes_find_dev() to the right place
From: Vic Wu @ 2019-08-28 6:37 UTC (permalink / raw)
To: Herbert Xu
Cc: Ryder Lee, linux-kernel, linux-mediatek, linux-crypto, Vic Wu,
David S . Miller, linux-arm-kernel
From: Ryder Lee <ryder.lee@mediatek.com>
Move mtk_aes_find_dev() to right functions as nobody uses the
'cryp' under current flows.
We can also avoid duplicate checks here and there in this way.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Vic Wu <vic.wu@mediatek.com>
---
drivers/crypto/mediatek/mtk-aes.c | 39 +++++++++++--------------------
1 file changed, 14 insertions(+), 25 deletions(-)
diff --git a/drivers/crypto/mediatek/mtk-aes.c b/drivers/crypto/mediatek/mtk-aes.c
index 72e4549e..43fcc8b5 100644
--- a/drivers/crypto/mediatek/mtk-aes.c
+++ b/drivers/crypto/mediatek/mtk-aes.c
@@ -658,14 +658,19 @@ static int mtk_aes_setkey(struct crypto_ablkcipher *tfm,
static int mtk_aes_crypt(struct ablkcipher_request *req, u64 mode)
{
- struct mtk_aes_base_ctx *ctx;
+ struct crypto_ablkcipher *ablkcipher = crypto_ablkcipher_reqtfm(req);
+ struct mtk_aes_base_ctx *ctx = crypto_ablkcipher_ctx(ablkcipher);
struct mtk_aes_reqctx *rctx;
+ struct mtk_cryp *cryp;
+
+ cryp = mtk_aes_find_dev(ctx);
+ if (!cryp)
+ return -ENODEV;
- ctx = crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req));
rctx = ablkcipher_request_ctx(req);
rctx->mode = mode;
- return mtk_aes_handle_queue(ctx->cryp, !(mode & AES_FLAGS_ENCRYPT),
+ return mtk_aes_handle_queue(cryp, !(mode & AES_FLAGS_ENCRYPT),
&req->base);
}
@@ -702,13 +707,6 @@ static int mtk_aes_ctr_decrypt(struct ablkcipher_request *req)
static int mtk_aes_cra_init(struct crypto_tfm *tfm)
{
struct mtk_aes_ctx *ctx = crypto_tfm_ctx(tfm);
- struct mtk_cryp *cryp = NULL;
-
- cryp = mtk_aes_find_dev(&ctx->base);
- if (!cryp) {
- pr_err("can't find crypto device\n");
- return -ENODEV;
- }
tfm->crt_ablkcipher.reqsize = sizeof(struct mtk_aes_reqctx);
ctx->base.start = mtk_aes_start;
@@ -718,13 +716,6 @@ static int mtk_aes_cra_init(struct crypto_tfm *tfm)
static int mtk_aes_ctr_cra_init(struct crypto_tfm *tfm)
{
struct mtk_aes_ctx *ctx = crypto_tfm_ctx(tfm);
- struct mtk_cryp *cryp = NULL;
-
- cryp = mtk_aes_find_dev(&ctx->base);
- if (!cryp) {
- pr_err("can't find crypto device\n");
- return -ENODEV;
- }
tfm->crt_ablkcipher.reqsize = sizeof(struct mtk_aes_reqctx);
ctx->base.start = mtk_aes_ctr_start;
@@ -930,6 +921,11 @@ static int mtk_aes_gcm_crypt(struct aead_request *req, u64 mode)
struct mtk_aes_base_ctx *ctx = crypto_aead_ctx(crypto_aead_reqtfm(req));
struct mtk_aes_gcm_ctx *gctx = mtk_aes_gcm_ctx_cast(ctx);
struct mtk_aes_reqctx *rctx = aead_request_ctx(req);
+ struct mtk_cryp *cryp;
+
+ cryp = mtk_aes_find_dev(ctx);
+ if (!cryp)
+ return -ENODEV;
/* Empty messages are not supported yet */
if (!gctx->textlen && !req->assoclen)
@@ -937,7 +933,7 @@ static int mtk_aes_gcm_crypt(struct aead_request *req, u64 mode)
rctx->mode = AES_FLAGS_GCM | mode;
- return mtk_aes_handle_queue(ctx->cryp, !!(mode & AES_FLAGS_ENCRYPT),
+ return mtk_aes_handle_queue(cryp, !!(mode & AES_FLAGS_ENCRYPT),
&req->base);
}
@@ -1069,13 +1065,6 @@ static int mtk_aes_gcm_decrypt(struct aead_request *req)
static int mtk_aes_gcm_init(struct crypto_aead *aead)
{
struct mtk_aes_gcm_ctx *ctx = crypto_aead_ctx(aead);
- struct mtk_cryp *cryp = NULL;
-
- cryp = mtk_aes_find_dev(&ctx->base);
- if (!cryp) {
- pr_err("can't find crypto device\n");
- return -ENODEV;
- }
ctx->ctr = crypto_alloc_skcipher("ctr(aes)", 0,
CRYPTO_ALG_ASYNC);
--
2.17.1
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* [PATCH 3/5] crypto: mediatek: only treat EBUSY as transient if backlog
From: Vic Wu @ 2019-08-28 6:37 UTC (permalink / raw)
To: Herbert Xu
Cc: Ryder Lee, linux-kernel, linux-mediatek, linux-crypto, Vic Wu,
David S . Miller, linux-arm-kernel
In-Reply-To: <20190828063716.22689-1-vic.wu@mediatek.com>
From: Ryder Lee <ryder.lee@mediatek.com>
The driver was treating -EBUSY as indication of queueing to backlog
without checking that backlog is enabled for the request.
Fix it by checking request flags.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Vic Wu <vic.wu@mediatek.com>
---
drivers/crypto/mediatek/mtk-sha.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/crypto/mediatek/mtk-sha.c b/drivers/crypto/mediatek/mtk-sha.c
index 2226f12d..1ecef3b5 100644
--- a/drivers/crypto/mediatek/mtk-sha.c
+++ b/drivers/crypto/mediatek/mtk-sha.c
@@ -781,7 +781,9 @@ static int mtk_sha_finup(struct ahash_request *req)
ctx->flags |= SHA_FLAGS_FINUP;
err1 = mtk_sha_update(req);
- if (err1 == -EINPROGRESS || err1 == -EBUSY)
+ if (err1 == -EINPROGRESS ||
+ (err1 == -EBUSY && (ahash_request_flags(req) &
+ CRYPTO_TFM_REQ_MAY_BACKLOG)))
return err1;
/*
* final() has to be always called to cleanup resources
--
2.17.1
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* [PATCH 4/5] crypto: mediatek: add support to OFB/CFB mode
From: Vic Wu @ 2019-08-28 6:37 UTC (permalink / raw)
To: Herbert Xu
Cc: Ryder Lee, linux-kernel, linux-mediatek, linux-crypto, Vic Wu,
David S . Miller, linux-arm-kernel
In-Reply-To: <20190828063716.22689-1-vic.wu@mediatek.com>
From: Ryder Lee <ryder.lee@mediatek.com>
This patch adds support to OFB/CFB mode.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Vic Wu <vic.wu@mediatek.com>
---
drivers/crypto/mediatek/mtk-aes.c | 85 ++++++++++++++++++++++++++++---
1 file changed, 78 insertions(+), 7 deletions(-)
diff --git a/drivers/crypto/mediatek/mtk-aes.c b/drivers/crypto/mediatek/mtk-aes.c
index 425d7f3f..9eeb8b8d 100644
--- a/drivers/crypto/mediatek/mtk-aes.c
+++ b/drivers/crypto/mediatek/mtk-aes.c
@@ -25,7 +25,7 @@
#define AES_CT_CTRL_HDR cpu_to_le32(0x00220000)
-/* AES-CBC/ECB/CTR command token */
+/* AES-CBC/ECB/CTR/OFB/CFB command token */
#define AES_CMD0 cpu_to_le32(0x05000000)
#define AES_CMD1 cpu_to_le32(0x2d060000)
#define AES_CMD2 cpu_to_le32(0xe4a63806)
@@ -52,6 +52,8 @@
/* AES transform information word 1 fields */
#define AES_TFM_ECB cpu_to_le32(0x0 << 0)
#define AES_TFM_CBC cpu_to_le32(0x1 << 0)
+#define AES_TFM_OFB cpu_to_le32(0x4 << 0)
+#define AES_TFM_CFB128 cpu_to_le32(0x5 << 0)
#define AES_TFM_CTR_INIT cpu_to_le32(0x2 << 0) /* init counter to 1 */
#define AES_TFM_CTR_LOAD cpu_to_le32(0x6 << 0) /* load/reuse counter */
#define AES_TFM_3IV cpu_to_le32(0x7 << 5) /* using IV 0-2 */
@@ -60,13 +62,15 @@
#define AES_TFM_ENC_HASH cpu_to_le32(0x1 << 17)
/* AES flags */
-#define AES_FLAGS_CIPHER_MSK GENMASK(2, 0)
+#define AES_FLAGS_CIPHER_MSK GENMASK(4, 0)
#define AES_FLAGS_ECB BIT(0)
#define AES_FLAGS_CBC BIT(1)
#define AES_FLAGS_CTR BIT(2)
-#define AES_FLAGS_GCM BIT(3)
-#define AES_FLAGS_ENCRYPT BIT(4)
-#define AES_FLAGS_BUSY BIT(5)
+#define AES_FLAGS_OFB BIT(3)
+#define AES_FLAGS_CFB128 BIT(4)
+#define AES_FLAGS_GCM BIT(5)
+#define AES_FLAGS_ENCRYPT BIT(6)
+#define AES_FLAGS_BUSY BIT(7)
#define AES_AUTH_TAG_ERR cpu_to_le32(BIT(26))
@@ -412,7 +416,7 @@ exit:
return mtk_aes_complete(cryp, aes, -EINVAL);
}
-/* Initialize transform information of CBC/ECB/CTR mode */
+/* Initialize transform information of CBC/ECB/CTR/OFB/CFB mode */
static void mtk_aes_info_init(struct mtk_cryp *cryp, struct mtk_aes_rec *aes,
size_t len)
{
@@ -441,7 +445,12 @@ static void mtk_aes_info_init(struct mtk_cryp *cryp, struct mtk_aes_rec *aes,
case AES_FLAGS_CTR:
info->tfm[1] = AES_TFM_CTR_LOAD;
goto ctr;
-
+ case AES_FLAGS_OFB:
+ info->tfm[1] = AES_TFM_OFB;
+ break;
+ case AES_FLAGS_CFB128:
+ info->tfm[1] = AES_TFM_CFB128;
+ break;
default:
/* Should not happen... */
return;
@@ -704,6 +713,26 @@ static int mtk_aes_ctr_decrypt(struct ablkcipher_request *req)
return mtk_aes_crypt(req, AES_FLAGS_CTR);
}
+static int mtk_aes_ofb_encrypt(struct ablkcipher_request *req)
+{
+ return mtk_aes_crypt(req, AES_FLAGS_ENCRYPT | AES_FLAGS_OFB);
+}
+
+static int mtk_aes_ofb_decrypt(struct ablkcipher_request *req)
+{
+ return mtk_aes_crypt(req, AES_FLAGS_OFB);
+}
+
+static int mtk_aes_cfb_encrypt(struct ablkcipher_request *req)
+{
+ return mtk_aes_crypt(req, AES_FLAGS_ENCRYPT | AES_FLAGS_CFB128);
+}
+
+static int mtk_aes_cfb_decrypt(struct ablkcipher_request *req)
+{
+ return mtk_aes_crypt(req, AES_FLAGS_CFB128);
+}
+
static int mtk_aes_cra_init(struct crypto_tfm *tfm)
{
struct mtk_aes_ctx *ctx = crypto_tfm_ctx(tfm);
@@ -785,6 +814,48 @@ static struct crypto_alg aes_algs[] = {
.decrypt = mtk_aes_ctr_decrypt,
}
},
+{
+ .cra_name = "ofb(aes)",
+ .cra_driver_name = "ofb-aes-mtk",
+ .cra_priority = 400,
+ .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
+ CRYPTO_ALG_ASYNC,
+ .cra_init = mtk_aes_cra_init,
+ .cra_blocksize = 1,
+ .cra_ctxsize = sizeof(struct mtk_aes_ctx),
+ .cra_alignmask = 0xf,
+ .cra_type = &crypto_ablkcipher_type,
+ .cra_module = THIS_MODULE,
+ .cra_u.ablkcipher = {
+ .min_keysize = AES_MIN_KEY_SIZE,
+ .max_keysize = AES_MAX_KEY_SIZE,
+ .ivsize = AES_BLOCK_SIZE,
+ .setkey = mtk_aes_setkey,
+ .encrypt = mtk_aes_ofb_encrypt,
+ .decrypt = mtk_aes_ofb_decrypt,
+ }
+},
+{
+ .cra_name = "cfb(aes)",
+ .cra_driver_name = "cfb-aes-mtk",
+ .cra_priority = 400,
+ .cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
+ CRYPTO_ALG_ASYNC,
+ .cra_init = mtk_aes_cra_init,
+ .cra_blocksize = 1,
+ .cra_ctxsize = sizeof(struct mtk_aes_ctx),
+ .cra_alignmask = 0xf,
+ .cra_type = &crypto_ablkcipher_type,
+ .cra_module = THIS_MODULE,
+ .cra_u.ablkcipher = {
+ .min_keysize = AES_MIN_KEY_SIZE,
+ .max_keysize = AES_MAX_KEY_SIZE,
+ .ivsize = AES_BLOCK_SIZE,
+ .setkey = mtk_aes_setkey,
+ .encrypt = mtk_aes_cfb_encrypt,
+ .decrypt = mtk_aes_cfb_decrypt,
+ }
+},
};
static inline struct mtk_aes_gcm_ctx *
--
2.17.1
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^ permalink raw reply related
* Re: [PATCH v3 00/15] Improvements and fixes for mxsfb DRM driver
From: Robert Chiras @ 2019-08-28 6:49 UTC (permalink / raw)
To: stefan@agner.ch, Leonard Crestez
Cc: marex@denx.de, devicetree@vger.kernel.org, kernel@pengutronix.de,
airlied@linux.ie, shawnguo@kernel.org, agx@sigxcpu.org,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
robh+dt@kernel.org, dl-linux-imx, daniel@ffwll.ch,
mark.rutland@arm.com, festevam@gmail.com, s.hauer@pengutronix.de,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <VI1PR04MB70233374E91F85119FD21FD5EEA10@VI1PR04MB7023.eurprd04.prod.outlook.com>
Hi Leonard,
On Lu, 2019-08-26 at 19:19 +0000, Leonard Crestez wrote:
> On 26.08.2019 17:35, Stefan Agner wrote:
> >
> > On 2019-08-26 14:05, Guido Günther wrote:
> > >
> > > Hi,
> > > On Wed, Aug 21, 2019 at 01:15:40PM +0300, Robert Chiras wrote:
> > > >
> > > > This patch-set improves the use of eLCDIF block on iMX 8 SoCs
> > > > (like 8MQ, 8MM
> > > > and 8QXP). Following, are the new features added and fixes from
> > > > this
> > > > patch-set:
> > > I've applied this whole series on top of my NWL work and it looks
> > > good
> > > with a DSI panel. Applying the whole series also fixes an issue
> > > where
> > > after unblank the output was sometimes shifted about half a
> > > screen width
> > > to the right (which didn't happen with DCSS). So at least from
> > > the parts
> > > I could test:
> > >
> > > Tested-by: Guido Günther <agx@sigxcpu.org>
> > >
> > > for the whole thing.
> > Thanks for testing! What SoC did you use? I think it would be good
> > to
> > also give this a try on i.MX 7 or i.MX 6ULL before merging.
> I did a quick test on imx6sx-sdb and it seems that [PATCH 07/15]
> "drm/mxsfb: Fix the vblank events" causes a hang on boot, even
> without a
> panel.
>
> If I revert that particular patch it seems to be fine: the new pixel
> formats seem to work in modetest (checked with sii,43wvf1g panel).
Thanks for feedback. I tested this and, indeed there are issues on 6SX
with this particular patch. It seems that there is a race-condition
caused by the vblank_on call in enable and IRQ routine. Since this is
not happening on any of i.MX8 SoC, I suspect the axi clock usage.
I think I will just remove this patch from the patch-set and handle
this case separately.
>
> --
> Regards,
> Leonard
Regards,
Robert
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* Re: [PATCH 2/2] clk: mediatek: add pericfg clocks for MT8183
From: Weiyi Lu @ 2019-08-28 6:55 UTC (permalink / raw)
To: Chunfeng Yun
Cc: Mark Rutland, Nicolas Boichat, Ryder Lee, devicetree,
Stephen Boyd, Michael Turquette, linux-kernel, linux-clk,
Rob Herring, linux-mediatek, Matthias Brugger, Erin Lo,
linux-arm-kernel
In-Reply-To: <1566971755-21217-2-git-send-email-chunfeng.yun@mediatek.com>
On Wed, 2019-08-28 at 13:55 +0800, Chunfeng Yun wrote:
> Add pericfg clocks for MT8183, it's used when support USB
> remote wakeup
>
> Cc: Weiyi Lu <weiyi.lu@mediatek.com>
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
> drivers/clk/mediatek/clk-mt8183.c | 35 ++++++++++++++++++++++++++
> include/dt-bindings/clock/mt8183-clk.h | 4 +++
> 2 files changed, 39 insertions(+)
>
> diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c
> index 1aa5f4059251..b19221bad0c9 100644
> --- a/drivers/clk/mediatek/clk-mt8183.c
> +++ b/drivers/clk/mediatek/clk-mt8183.c
> @@ -999,6 +999,25 @@ static const struct mtk_gate infra_clks[] = {
> "msdc50_0_sel", 24),
> };
>
> +static const struct mtk_gate_regs peri_cg_regs = {
> + .set_ofs = 0x20c,
> + .clr_ofs = 0x20c,
> + .sta_ofs = 0x20c,
> +};
> +
> +#define GATE_PERI(_id, _name, _parent, _shift) { \
> + .id = _id, \
> + .name = _name, \
> + .parent_name = _parent, \
> + .regs = &peri_cg_regs, \
> + .shift = _shift, \
> + .ops = &mtk_clk_gate_ops_no_setclr_inv, \
> +}
Hi Chunfeng,
I suggest
#define GATE_PERI(_id, _name, _parent, _shift) \
GATE_MTK(_id, _name, _parent, &peri_cg_regs, _shift, \
&mtk_clk_gate_ops_no_setclr_inv)
> +
> +static const struct mtk_gate peri_clks[] = {
> + GATE_PERI(CLK_PERI_AXI, "periaxi", "axi_sel", 31),
> +};
> +
> static const struct mtk_gate_regs apmixed_cg_regs = {
> .set_ofs = 0x20,
> .clr_ofs = 0x20,
> @@ -1194,6 +1213,19 @@ static int clk_mt8183_infra_probe(struct platform_device *pdev)
> return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> }
>
> +static int clk_mt8183_peri_probe(struct platform_device *pdev)
> +{
> + struct clk_onecell_data *clk_data;
> + struct device_node *node = pdev->dev.of_node;
> +
> + clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
> +
> + mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
> + clk_data);
> +
> + return of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> +}
> +
> static int clk_mt8183_mcu_probe(struct platform_device *pdev)
> {
> struct clk_onecell_data *clk_data;
> @@ -1223,6 +1255,9 @@ static const struct of_device_id of_match_clk_mt8183[] = {
> }, {
> .compatible = "mediatek,mt8183-infracfg",
> .data = clk_mt8183_infra_probe,
> + }, {
> + .compatible = "mediatek,mt8183-pericfg",
> + .data = clk_mt8183_peri_probe,
> }, {
> .compatible = "mediatek,mt8183-mcucfg",
> .data = clk_mt8183_mcu_probe,
> diff --git a/include/dt-bindings/clock/mt8183-clk.h b/include/dt-bindings/clock/mt8183-clk.h
> index 0046506eb24c..a7b470b0ec8a 100644
> --- a/include/dt-bindings/clock/mt8183-clk.h
> +++ b/include/dt-bindings/clock/mt8183-clk.h
> @@ -284,6 +284,10 @@
> #define CLK_INFRA_FBIST2FPC 100
> #define CLK_INFRA_NR_CLK 101
>
> +/* PERICFG */
> +#define CLK_PERI_AXI 0
> +#define CLK_PERI_NR_CLK 1
> +
> /* MFGCFG */
> #define CLK_MFG_BG3D 0
> #define CLK_MFG_NR_CLK 1
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* Re: [PATCH 5/5] crypto: mediatek: fix incorrect crypto key setting
From: John Crispin @ 2019-08-28 7:03 UTC (permalink / raw)
To: Vic Wu, Herbert Xu
Cc: Ryder Lee, linux-kernel, linux-mediatek, linux-crypto,
David S . Miller, linux-arm-kernel
In-Reply-To: <20190828063716.22689-5-vic.wu@mediatek.com>
On 28/08/2019 08:37, Vic Wu wrote:
> Record crypto key to context during setkey and set the key to
> transform state buffer in encrypt/decrypt process.
>
> Signed-off-by: Vic Wu <vic.wu@mediatek.com>
Thanks for the fix !
Tested-by: John Crispin <john@phrozen.og>
> ---
> drivers/crypto/mediatek/mtk-aes.c | 11 ++++++-----
> 1 file changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/crypto/mediatek/mtk-aes.c b/drivers/crypto/mediatek/mtk-aes.c
> index 9eeb8b8d..05f21dc8 100644
> --- a/drivers/crypto/mediatek/mtk-aes.c
> +++ b/drivers/crypto/mediatek/mtk-aes.c
> @@ -107,6 +107,7 @@ struct mtk_aes_reqctx {
> struct mtk_aes_base_ctx {
> struct mtk_cryp *cryp;
> u32 keylen;
> + __le32 key[12];
> __le32 keymode;
>
> mtk_aes_fn start;
> @@ -541,6 +542,8 @@ static int mtk_aes_handle_queue(struct mtk_cryp *cryp, u8 id,
> backlog->complete(backlog, -EINPROGRESS);
>
> ctx = crypto_tfm_ctx(areq->tfm);
> + /* Write key into state buffer */
> + memcpy(ctx->info.state, ctx->key, sizeof(ctx->key));
>
> aes->areq = areq;
> aes->ctx = ctx;
> @@ -660,7 +663,7 @@ static int mtk_aes_setkey(struct crypto_ablkcipher *tfm,
> }
>
> ctx->keylen = SIZE_IN_WORDS(keylen);
> - mtk_aes_write_state_le(ctx->info.state, (const u32 *)key, keylen);
> + mtk_aes_write_state_le(ctx->key, (const u32 *)key, keylen);
>
> return 0;
> }
> @@ -1093,10 +1096,8 @@ static int mtk_aes_gcm_setkey(struct crypto_aead *aead, const u8 *key,
> if (err)
> goto out;
>
> - /* Write key into state buffer */
> - mtk_aes_write_state_le(ctx->info.state, (const u32 *)key, keylen);
> - /* Write key(H) into state buffer */
> - mtk_aes_write_state_be(ctx->info.state + ctx->keylen, data->hash,
> + mtk_aes_write_state_le(ctx->key, (const u32 *)key, keylen);
> + mtk_aes_write_state_be(ctx->key + ctx->keylen, data->hash,
> AES_BLOCK_SIZE);
> out:
> kzfree(data);
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* [PATCHv2 00/11] soc: ti: add OMAP PRM driver (for reset)
From: Tero Kristo @ 2019-08-28 7:19 UTC (permalink / raw)
To: ssantosh, linux-arm-kernel, linux-omap, robh+dt, p.zabel; +Cc: tony, devicetree
Hi,
V2 of the series mostly has comments fixed from Suman.
- Added a link between reset + clock drivers to sync up the state between
these; this is to avoid facing any timeout issues on either end due to
sequencing of events (Patch #5.) This has been implemented via TI only
private driver APIs, as at least I am not aware of anybody else needing
similar mechanism and it is pretty SoC architecture specific.
- Dropped any powerdomain related data for now as it is not used for
anything yet.
- Added checks against illegal reset IDs.
- Added checks for pdata validity during probe.
- Reset data is added for am4/omap5 SoCs.
- Some other minor tweaks.
This series depends on the clock driver changes [1] due to patch #5,
otherwise there will be build breakage.
Also, just as a background note, this driver has been implemented
under drivers/soc/ti due to the fact that I did not figure out any
better home for it. In its current form it would be suitable to
reside under drivers/reset, but there is a plan to extend this to
support powerdomain handling also (PRM stands for Power and Reset
Management.)
-Tero
[1] https://marc.info/?l=linux-clk&m=156697558331203&w=2
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
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