* [PATCH v7 0/6] Add MediaTek MUSB Controller Driver
From: min.guo @ 2019-08-30 8:20 UTC (permalink / raw)
To: Bin Liu, Rob Herring
Cc: Mark Rutland, devicetree, hdegoede, tony, Greg Kroah-Hartman,
linux-usb, linux-kernel, Matthias Brugger, Alan Stern, Min Guo,
chunfeng.yun, linux-mediatek, linux-arm-kernel
From: Min Guo <min.guo@mediatek.com>
These patches introduce the MediaTek MUSB controller driver.
The driver can be configured as Dual-Role Device (DRD),
Peripheral Only and Host Only modes. This has beed tested on
MT2701 with a variety of devices in host mode and with the
f_mass gadget driver in peripheral mode, plugging otg cables
in/out a lot of times in all possible imaginable plug orders.
changes in v7:
changes of dt-bindings and DTS:
1. Change compatible string
2. Change usb connector child node compatible as "gpio-usb-b-connector"
changes in v6:
changes of dt-bindings:
1. Modify usb connector child node
changes of DTS:
1. Modify usb connector child node
changes of driver:
1. Add of_platform_populate in probe to populate connector platform_devices
from device tree data
2. Replace extcon with usb role switch mechanism to support dual-role mode,
depends on [1]
3. Remove set vbus function
[1] [v6,09/10] usb: roles: add USB Type-B GPIO connector driver
https://patchwork.kernel.org/patch/10966361/
changes in v5:
changes of dt-bindings suggested by Rob:
1. Modify compatible as
- compatible : should be one of:
"mediatek,mt-2701"
...
followed by "mediatek,mtk-musb"
2. Add usb connector child node
changes of DTS:
1. Add usb connector child node
changes of driver suggested by Bin:
1. Replace musb_readb() with musb_clearb() to clear dma pending interrupts
2. Replace musb_readb() with musb_clearb() to clear common/tx/rx pending interrupts
3. Make musb_clearb/w() return the value of musb_readb/w()
changes in v4:
changes of dt-bindings suggested by Sergei:
1. String alignment
changes of driver suggested by Tony and Bin:
1. Add a new patch for set/get_toggle()
2. Add a new patch for noirq type of dma
3. Add a new patch musb_clearb/w()
4. Abondon patch "usb: musb: Delete the const attribute of addr parameter in readb/w/l hooks"
changes in v3:
changes of driver suggested by Bin:
1. Add a new patch for musb_readb/w/l() to remove const attribute
2. Use is_out as function parameter in set_toggle/get_toggle() hooks
3. Remove 'u8/u16 data' parameter in clearb/w() hooks
4. Remove musb_default_clearb/w()
5. Replace musb_readb/w() with musb_clearb/w() to clear pending interrupts
6. Add comments to clearb/w() hooks
7. Replace musb_save_toggle() with musb->io.get_toggle()
8. Replace musb_set_toggle() with musb->io.set_toggle()
changes in v2:
changes of dt-bindings suggested by Rob and Bin:
1. Modify DRC to DRD
2. Drop the "<soc-model>-musb" in compatible
3. Remove phy-names
4. Add space after comma in clock-names
dtsi:
1. Remove phy-names
changes of driver suggested by Bin:
1. Add a new patch for musb_set_toggle
2. Add summarize of MediaTek musb controller differences in the commit log
3. Abondon patch "usb: musb: Move musbhsdma macro definition to musb_dma.h"
4. Add "|| COMPILE_TEST" in Kconfig
5. Add musb_clearb() and musb_clearw() hooks
6. Add get_toggle() and set_toggle() hooks
7. Replace musb_readl() with musb_readw() to read 16bit toggle register
8. Move MediaTek's private toggle registers from musb_regs.h to mediatek.c
9. Create musbhs_dma_controller_create_noirq()
Min Guo (6):
dt-bindings: usb: musb: Add support for MediaTek musb controller
arm: dts: mt2701: Add usb2 device nodes
usb: musb: Add get/set toggle hooks
usb: musb: Add noirq type of dma create interface
usb: musb: Add musb_clearb/w() interface
usb: musb: Add support for MediaTek musb controller
.../devicetree/bindings/usb/mediatek,musb.txt | 55 ++
arch/arm/boot/dts/mt2701-evb.dts | 21 +
arch/arm/boot/dts/mt2701.dtsi | 33 ++
drivers/usb/musb/Kconfig | 9 +-
drivers/usb/musb/Makefile | 1 +
drivers/usb/musb/mediatek.c | 582 +++++++++++++++++++++
drivers/usb/musb/musb_core.c | 74 ++-
drivers/usb/musb/musb_core.h | 13 +-
drivers/usb/musb/musb_dma.h | 9 +
drivers/usb/musb/musb_host.c | 46 +-
drivers/usb/musb/musb_io.h | 12 +-
drivers/usb/musb/musbhsdma.c | 56 +-
drivers/usb/musb/sunxi.c | 4 +-
drivers/usb/musb/tusb6010.c | 2 +-
14 files changed, 845 insertions(+), 72 deletions(-)
create mode 100644 Documentation/devicetree/bindings/usb/mediatek,musb.txt
create mode 100644 drivers/usb/musb/mediatek.c
--
1.9.1
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^ permalink raw reply
* Re: [PATCH v5 1/2] dt-bindings: mailbox: add binding doc for the ARM SMC/HVC mailbox
From: Jassi Brar @ 2019-08-30 8:12 UTC (permalink / raw)
To: Peng Fan
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
f.fainelli@gmail.com, andre.przywara@arm.com,
linux-kernel@vger.kernel.org, robh+dt@kernel.org, dl-linux-imx,
sudeep.holla@arm.com, linux-arm-kernel@lists.infradead.org
In-Reply-To: <AM0PR04MB448133D1F4C887A82C679CEB88BD0@AM0PR04MB4481.eurprd04.prod.outlook.com>
On Fri, Aug 30, 2019 at 3:07 AM Peng Fan <peng.fan@nxp.com> wrote:
>
> > Subject: Re: [PATCH v5 1/2] dt-bindings: mailbox: add binding doc for the ARM
> > SMC/HVC mailbox
> >
> > On Fri, Aug 30, 2019 at 2:37 AM Peng Fan <peng.fan@nxp.com> wrote:
> > >
> > > Hi Jassi,
> > >
> > > > Subject: Re: [PATCH v5 1/2] dt-bindings: mailbox: add binding doc
> > > > for the ARM SMC/HVC mailbox
> > > >
> > > > On Fri, Aug 30, 2019 at 1:28 AM Peng Fan <peng.fan@nxp.com> wrote:
> > > >
> > > > > > > +examples:
> > > > > > > + - |
> > > > > > > + sram@910000 {
> > > > > > > + compatible = "mmio-sram";
> > > > > > > + reg = <0x0 0x93f000 0x0 0x1000>;
> > > > > > > + #address-cells = <1>;
> > > > > > > + #size-cells = <1>;
> > > > > > > + ranges = <0 0x0 0x93f000 0x1000>;
> > > > > > > +
> > > > > > > + cpu_scp_lpri: scp-shmem@0 {
> > > > > > > + compatible = "arm,scmi-shmem";
> > > > > > > + reg = <0x0 0x200>;
> > > > > > > + };
> > > > > > > +
> > > > > > > + cpu_scp_hpri: scp-shmem@200 {
> > > > > > > + compatible = "arm,scmi-shmem";
> > > > > > > + reg = <0x200 0x200>;
> > > > > > > + };
> > > > > > > + };
> > > > > > > +
> > > > > > > + firmware {
> > > > > > > + smc_mbox: mailbox {
> > > > > > > + #mbox-cells = <1>;
> > > > > > > + compatible = "arm,smc-mbox";
> > > > > > > + method = "smc";
> > > > > > > + arm,num-chans = <0x2>;
> > > > > > > + transports = "mem";
> > > > > > > + /* Optional */
> > > > > > > + arm,func-ids = <0xc20000fe>, <0xc20000ff>;
> > > > > > >
> > > > > > SMC/HVC is synchronously(block) running in "secure mode", i.e,
> > > > > > there can only be one instance running platform wide. Right?
> > > > >
> > > > > I think there could be channel for TEE, and channel for Linux.
> > > > > For virtualization case, there could be dedicated channel for each VM.
> > > > >
> > > > I am talking from Linux pov. Functions 0xfe and 0xff above, can't
> > > > both be active at the same time, right?
> > >
> > > If I get your point correctly,
> > > On UP, both could not be active. On SMP, tx/rx could be both active,
> > > anyway this depends on secure firmware and Linux firmware design.
> > >
> > > Do you have any suggestions about arm,func-ids here?
> > >
> > I was thinking if this is just an instruction, why can't each channel be
> > represented as a controller, i.e, have exactly one func-id per controller node.
> > Define as many controllers as you need channels ?
>
> I am ok, this could make driver code simpler. Something as below?
>
> smc_tx_mbox: tx_mbox {
> #mbox-cells = <0>;
> compatible = "arm,smc-mbox";
> method = "smc";
> transports = "mem";
> arm,func-id = <0xc20000fe>;
> };
>
> smc_rx_mbox: rx_mbox {
> #mbox-cells = <0>;
> compatible = "arm,smc-mbox";
> method = "smc";
> transports = "mem";
> arm,func-id = <0xc20000ff>;
> };
>
> firmware {
> scmi {
> compatible = "arm,scmi";
> mboxes = <&smc_tx_mbox>, <&smc_rx_mbox 1>;
> mbox-names = "tx", "rx";
> shmem = <&cpu_scp_lpri>, <&cpu_scp_hpri>;
> };
> };
>
Yes, the channel part is good.
But I am not convinced by the need to have SCMI specific "transport" mode.
thanks
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^ permalink raw reply
* Re: [PATCH] arm64: numa: check the node id before accessing node_to_cpumask_map
From: Yunsheng Lin @ 2019-08-30 8:08 UTC (permalink / raw)
To: Michal Hocko
Cc: tglx, anshuman.khandual, robin.murphy, linuxarm, linux-kernel,
rppt, cai, akpm, will, adobriyan, linux-arm-kernel
In-Reply-To: <20190830064421.GS28313@dhcp22.suse.cz>
On 2019/8/30 14:44, Michal Hocko wrote:
> On Fri 30-08-19 14:35:26, Yunsheng Lin wrote:
>> On 2019/8/30 13:55, Michal Hocko wrote:
>>> On Fri 30-08-19 10:26:31, Yunsheng Lin wrote:
>>>> Some buggy bios may not set the device' numa id, and dev_to_node
>>>> will return -1, which may cause global-out-of-bounds error
>>>> detected by KASAN.
>>>
>>> Why should we workaround a buggy bios like that? Is it so widespread and
>>> no BIOS update available? Also, why is this arm64 specific?
>>
>> For our case, there is BIOS update available. I just thought it might
>> be better to protect from this case when BIOS has not implemented the
>> device' numa id setting feature or the feature from BIOS has some bug.
>>
>> It is not arm64 specific, right now I only have arm64 board. If it is
>> ok to protect this from the buggy BIOS, maybe all other arch can be
>> changed too.
>
> If we are to really care then this should be consistent among
> architectures IMHO. But I am not really sure this is really worth it.
> The code is quite old and I do not really remember any reports.
It is only detected by enabling KASAN, the system seems to run fine without
any visible error if KASAN is disabled. Maybe there is why no report has
been seen?
Also according to Section 6.2.14 from ACPI spec 6.3 [1], the setting of proximity
domain is optional, as below:
This optional object is used to describe proximity domain
associations within a machine. _PXM evaluates to an integer
that identifies a device as belonging to a Proximity Domain
defined in the System Resource Affinity Table (SRAT).
Do you think it is ok to resend the fix with above clarification and below
log:
[ 42.970381] ==================================================================
[ 42.977595] BUG: KASAN: global-out-of-bounds in __bitmap_weight+0x48/0xb0
[ 42.984370] Read of size 8 at addr ffff20008cdf8790 by task kworker/0:1/13
[ 42.991230]
[ 42.992712] CPU: 0 PID: 13 Comm: kworker/0:1 Tainted: G O 5.2.0-rc4-g8bde06a-dirty #3
[ 43.001830] Hardware name: Huawei TaiShan 2280 V2/BC82AMDA, BIOS TA BIOS 2280-A CS V2.B050.01 08/08/2019
[ 43.011298] Workqueue: events work_for_cpu_fn
[ 43.015643] Call trace:
[ 43.018078] dump_backtrace+0x0/0x1e8
[ 43.021727] show_stack+0x14/0x20
[ 43.025031] dump_stack+0xc4/0xfc
[ 43.028335] print_address_description+0x178/0x270
[ 43.033113] __kasan_report+0x164/0x1b8
[ 43.036936] kasan_report+0xc/0x18
[ 43.040325] __asan_load8+0x84/0xa8
[ 43.043801] __bitmap_weight+0x48/0xb0
[ 43.047552] hclge_init_ae_dev+0x988/0x1e78 [hclge]
[ 43.052418] hnae3_register_ae_dev+0xcc/0x278 [hnae3]
[ 43.057467] hns3_probe+0xe0/0x120 [hns3]
[ 43.061464] local_pci_probe+0x74/0xf0
[ 43.065200] work_for_cpu_fn+0x2c/0x48
[ 43.068937] process_one_work+0x3c0/0x878
[ 43.072934] worker_thread+0x400/0x670
[ 43.076670] kthread+0x1b0/0x1b8
[ 43.079885] ret_from_fork+0x10/0x18
[ 43.083446]
[ 43.084925] The buggy address belongs to the variable:
[ 43.090052] numa_distance+0x30/0x40
[ 43.093613]
[ 43.095091] Memory state around the buggy address:
[ 43.099870] ffff20008cdf8680: fa fa fa fa 04 fa fa fa fa fa fa fa 00 00 fa fa
[ 43.107078] ffff20008cdf8700: fa fa fa fa 04 fa fa fa fa fa fa fa 00 fa fa fa
[ 43.114286] >ffff20008cdf8780: fa fa fa fa 00 00 00 00 00 00 00 00 fa fa fa fa
[ 43.121494] ^
[ 43.125230] ffff20008cdf8800: 01 fa fa fa fa fa fa fa 04 fa fa fa fa fa fa fa
[ 43.132439] ffff20008cdf8880: fa fa fa fa fa fa fa fa 00 00 fa fa fa fa fa fa
[ 43.139646] ==================================================================
>
>>>> This patch changes cpumask_of_node to return cpu_none_mask if the
>>>> node is not valid, and sync the cpumask_of_node between the
>>>> cpumask_of_node function in numa.h and numa.c.
>>>
>>> Why?
>>
>> When CONFIG_DEBUG_PER_CPU_MAPS is defined, the cpumask_of_node() in
>> numa.c is used, if not, the cpumask_of_node() in numa.h is used.
>>
>> I am not sure why there is difference between them, and it is there
>> when since the below commit:
>> 1a2db300348b ("arm64, numa: Add NUMA support for arm64 platforms.")
>>
>> I synced them to keep them consistent whether CONFIG_DEBUG_PER_CPU_MAPS
>> is defined.
>
> Such a change should be made in a separate patch with a full
> clarification/justification. From the above it is still not clear why
> this is needed though.
Ok.
How about:
Currently there are different implementations of cpumask_of_node() depend
on the arch, for example:
ia64:
#define cpumask_of_node(node) ((node) == -1 ? \
cpu_all_mask : \
&node_to_cpu_mask[node])
alpha:
static const struct cpumask *cpumask_of_node(int node)
{
int cpu;
if (node == NUMA_NO_NODE)
return cpu_all_mask;
cpumask_clear(&node_to_cpumask_map[node]);
for_each_online_cpu(cpu) {
if (cpu_to_node(cpu) == node)
cpumask_set_cpu(cpu, node_to_cpumask_map[node]);
}
return &node_to_cpumask_map[node];
}
Even for the same arch, there are two implementations depend on the
CONFIG_DEBUG_PER_CPU_MAPS configuration.
arm64/x86 without CONFIG_DEBUG_PER_CPU_MAPS:
static inline const struct cpumask *cpumask_of_node(int node)
{
return node_to_cpumask_map[node];
}
arm64/x86 with CONFIG_DEBUG_PER_CPU_MAPS:
const struct cpumask *cpumask_of_node(int node)
{
if (WARN_ON(node >= nr_node_ids))
return cpu_none_mask;
if (WARN_ON(node_to_cpumask_map[node] == NULL))
return cpu_online_mask;
return node_to_cpumask_map[node];
}
It seems the cpumask_of_node with CONFIG_DEBUG_PER_CPU_MAPS is used
to catch the erorr case and give a warning to user when node id is not
valid.
So in order to be consistent between different arch and with or
without CONFIG_DEBUG_PER_CPU_MAPS case:
node id has to be checked with the below case before returning
node_to_cpumask_map[node]:
1. if nr_node_ids < 0, return cpu_all_mask
2. if nr_node_ids >= nr_node_ids, return cpu_none_mask
3. if node_to_cpumask_map[node] is NULL, return cpu_online_mask
[1] https://uefi.org/sites/default/files/resources/ACPI_6_3_final_Jan30.pdf
>
>>>> Signed-off-by: Yunsheng Lin <linyunsheng@huawei.com>
>>>> ---
>>>> arch/arm64/include/asm/numa.h | 6 ++++++
>>>> arch/arm64/mm/numa.c | 2 +-
>>>> 2 files changed, 7 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/arch/arm64/include/asm/numa.h b/arch/arm64/include/asm/numa.h
>>>> index 626ad01..da891ed 100644
>>>> --- a/arch/arm64/include/asm/numa.h
>>>> +++ b/arch/arm64/include/asm/numa.h
>>>> @@ -25,6 +25,12 @@ const struct cpumask *cpumask_of_node(int node);
>>>> /* Returns a pointer to the cpumask of CPUs on Node 'node'. */
>>>> static inline const struct cpumask *cpumask_of_node(int node)
>>>> {
>>>> + if (node >= nr_node_ids || node < 0)
>>>> + return cpu_none_mask;
>>>> +
>>>> + if (!node_to_cpumask_map[node])
>>>> + return cpu_online_mask;
>>>> +
>>>> return node_to_cpumask_map[node];
>>>> }
>>>> #endif
>>>> diff --git a/arch/arm64/mm/numa.c b/arch/arm64/mm/numa.c
>>>> index 4f241cc..3846313 100644
>>>> --- a/arch/arm64/mm/numa.c
>>>> +++ b/arch/arm64/mm/numa.c
>>>> @@ -46,7 +46,7 @@ EXPORT_SYMBOL(node_to_cpumask_map);
>>>> */
>>>> const struct cpumask *cpumask_of_node(int node)
>>>> {
>>>> - if (WARN_ON(node >= nr_node_ids))
>>>> + if (WARN_ON(node >= nr_node_ids || node < 0))
>>>> return cpu_none_mask;
>>>>
>>>> if (WARN_ON(node_to_cpumask_map[node] == NULL))
>>>> --
>>>> 2.8.1
>>>
>
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* RE: [PATCH v5 1/2] dt-bindings: mailbox: add binding doc for the ARM SMC/HVC mailbox
From: Peng Fan @ 2019-08-30 8:07 UTC (permalink / raw)
To: Jassi Brar
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
f.fainelli@gmail.com, andre.przywara@arm.com,
linux-kernel@vger.kernel.org, robh+dt@kernel.org, dl-linux-imx,
sudeep.holla@arm.com, linux-arm-kernel@lists.infradead.org
In-Reply-To: <CABb+yY2SrMF8e1iLyLqb-rJyBx4ajA0hZ6D=LFtuMNtXYjgccA@mail.gmail.com>
> Subject: Re: [PATCH v5 1/2] dt-bindings: mailbox: add binding doc for the ARM
> SMC/HVC mailbox
>
> On Fri, Aug 30, 2019 at 2:37 AM Peng Fan <peng.fan@nxp.com> wrote:
> >
> > Hi Jassi,
> >
> > > Subject: Re: [PATCH v5 1/2] dt-bindings: mailbox: add binding doc
> > > for the ARM SMC/HVC mailbox
> > >
> > > On Fri, Aug 30, 2019 at 1:28 AM Peng Fan <peng.fan@nxp.com> wrote:
> > >
> > > > > > +examples:
> > > > > > + - |
> > > > > > + sram@910000 {
> > > > > > + compatible = "mmio-sram";
> > > > > > + reg = <0x0 0x93f000 0x0 0x1000>;
> > > > > > + #address-cells = <1>;
> > > > > > + #size-cells = <1>;
> > > > > > + ranges = <0 0x0 0x93f000 0x1000>;
> > > > > > +
> > > > > > + cpu_scp_lpri: scp-shmem@0 {
> > > > > > + compatible = "arm,scmi-shmem";
> > > > > > + reg = <0x0 0x200>;
> > > > > > + };
> > > > > > +
> > > > > > + cpu_scp_hpri: scp-shmem@200 {
> > > > > > + compatible = "arm,scmi-shmem";
> > > > > > + reg = <0x200 0x200>;
> > > > > > + };
> > > > > > + };
> > > > > > +
> > > > > > + firmware {
> > > > > > + smc_mbox: mailbox {
> > > > > > + #mbox-cells = <1>;
> > > > > > + compatible = "arm,smc-mbox";
> > > > > > + method = "smc";
> > > > > > + arm,num-chans = <0x2>;
> > > > > > + transports = "mem";
> > > > > > + /* Optional */
> > > > > > + arm,func-ids = <0xc20000fe>, <0xc20000ff>;
> > > > > >
> > > > > SMC/HVC is synchronously(block) running in "secure mode", i.e,
> > > > > there can only be one instance running platform wide. Right?
> > > >
> > > > I think there could be channel for TEE, and channel for Linux.
> > > > For virtualization case, there could be dedicated channel for each VM.
> > > >
> > > I am talking from Linux pov. Functions 0xfe and 0xff above, can't
> > > both be active at the same time, right?
> >
> > If I get your point correctly,
> > On UP, both could not be active. On SMP, tx/rx could be both active,
> > anyway this depends on secure firmware and Linux firmware design.
> >
> > Do you have any suggestions about arm,func-ids here?
> >
> I was thinking if this is just an instruction, why can't each channel be
> represented as a controller, i.e, have exactly one func-id per controller node.
> Define as many controllers as you need channels ?
I am ok, this could make driver code simpler. Something as below?
smc_tx_mbox: tx_mbox {
#mbox-cells = <0>;
compatible = "arm,smc-mbox";
method = "smc";
transports = "mem";
arm,func-id = <0xc20000fe>;
};
smc_rx_mbox: rx_mbox {
#mbox-cells = <0>;
compatible = "arm,smc-mbox";
method = "smc";
transports = "mem";
arm,func-id = <0xc20000ff>;
};
firmware {
scmi {
compatible = "arm,scmi";
mboxes = <&smc_tx_mbox>, <&smc_rx_mbox 1>;
mbox-names = "tx", "rx";
shmem = <&cpu_scp_lpri>, <&cpu_scp_hpri>;
};
};
Thanks,
Peng.
>
> -j
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* Re: [PATCH 1/2] mmc: sdhci-of-aspeed: Uphold clocks-on post-condition of set_clock()
From: Andrew Jeffery @ 2019-08-30 8:07 UTC (permalink / raw)
To: Ulf Hansson
Cc: linux-aspeed, linux-mmc, openbmc, Ryan Chen, Adrian Hunter,
Linux Kernel Mailing List, Joel Stanley, Linux ARM
In-Reply-To: <CAPDyKFrKXfB1F2dh63KrkCiKGbmbBWaAM16vJqtQncnF4YctQw@mail.gmail.com>
On Fri, 30 Aug 2019, at 17:31, Ulf Hansson wrote:
> On Fri, 30 Aug 2019 at 09:46, Andrew Jeffery <andrew@aj.id.au> wrote:
> >
> > The early-exit didn't seem to matter on the AST2500, but on the AST2600
> > the SD clock genuinely may not be running on entry to
> > aspeed_sdhci_set_clock(). Remove the early exit to ensure we always run
> > sdhci_enable_clk().
> >
> > Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> > ---
> > drivers/mmc/host/sdhci-of-aspeed.c | 3 ---
> > 1 file changed, 3 deletions(-)
> >
> > diff --git a/drivers/mmc/host/sdhci-of-aspeed.c b/drivers/mmc/host/sdhci-of-aspeed.c
> > index d5acb5afc50f..a9175ca85696 100644
> > --- a/drivers/mmc/host/sdhci-of-aspeed.c
> > +++ b/drivers/mmc/host/sdhci-of-aspeed.c
> > @@ -55,9 +55,6 @@ static void aspeed_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
> > int div;
> > u16 clk;
> >
> > - if (clock == host->clock)
> > - return;
> > -
> > sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
> >
> > if (clock == 0)
> > --
> > 2.20.1
> >
>
> Further down in aspeed_sdhci_set_clock() you should probably also
> remove the assignment of host->clock = clock, as that is already
> managed by sdhci_set_ios().
Ah, I'll fix that in a v2 once I have your thoughts on patch 2/2.
Thanks for the lightning quick feedback!
Andrew
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^ permalink raw reply
* Re: [PATCH 1/2] mmc: sdhci-of-aspeed: Uphold clocks-on post-condition of set_clock()
From: Ulf Hansson @ 2019-08-30 8:01 UTC (permalink / raw)
To: Andrew Jeffery
Cc: linux-aspeed, linux-mmc@vger.kernel.org, openbmc, Ryan Chen,
Adrian Hunter, Linux Kernel Mailing List, Joel Stanley, Linux ARM
In-Reply-To: <20190830074644.10936-2-andrew@aj.id.au>
On Fri, 30 Aug 2019 at 09:46, Andrew Jeffery <andrew@aj.id.au> wrote:
>
> The early-exit didn't seem to matter on the AST2500, but on the AST2600
> the SD clock genuinely may not be running on entry to
> aspeed_sdhci_set_clock(). Remove the early exit to ensure we always run
> sdhci_enable_clk().
>
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> ---
> drivers/mmc/host/sdhci-of-aspeed.c | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-of-aspeed.c b/drivers/mmc/host/sdhci-of-aspeed.c
> index d5acb5afc50f..a9175ca85696 100644
> --- a/drivers/mmc/host/sdhci-of-aspeed.c
> +++ b/drivers/mmc/host/sdhci-of-aspeed.c
> @@ -55,9 +55,6 @@ static void aspeed_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
> int div;
> u16 clk;
>
> - if (clock == host->clock)
> - return;
> -
> sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
>
> if (clock == 0)
> --
> 2.20.1
>
Further down in aspeed_sdhci_set_clock() you should probably also
remove the assignment of host->clock = clock, as that is already
managed by sdhci_set_ios().
Kind regards
Uffe
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^ permalink raw reply
* Re: [PATCH 2/2] drm/mediatek: Apply CMDQ control flow
From: CK Hu @ 2019-08-30 7:58 UTC (permalink / raw)
To: Bibby Hsieh
Cc: drinkcat, Yongqiang Niu, David Airlie, Daniel Vetter,
linux-kernel, dri-devel, tfiga, YT Shen, Thierry Reding,
linux-mediatek, Philipp Zabel, Matthias Brugger, linux-arm-kernel
In-Reply-To: <20190830074103.16671-3-bibby.hsieh@mediatek.com>
Hi, Bibby:
On Fri, 2019-08-30 at 15:41 +0800, Bibby Hsieh wrote:
> Unlike other SoCs, MT8183 does not have "shadow"
> registers for performaing an atomic video mode
> set or page flip at vblank/vsync.
>
> The CMDQ (Commend Queue) in MT8183 is used to help
> update all relevant display controller registers
> with critical time limation.
>
> Signed-off-by: YT Shen <yt.shen@mediatek.com>
> Signed-off-by: CK Hu <ck.hu@mediatek.com>
> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 190 +++++++++++++++++---
> drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 2 +
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 34 ++++
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 2 +
> drivers/gpu/drm/mediatek/mtk_drm_plane.c | 4 +
> 5 files changed, 206 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> index 092e502ed27b..329ca5a14c39 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> @@ -10,7 +10,9 @@
> #include <drm/drm_plane_helper.h>
> #include <drm/drm_probe_helper.h>
> #include <linux/clk.h>
> +#include <linux/of_address.h>
> #include <linux/pm_runtime.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
>
> #include "mtk_drm_drv.h"
> #include "mtk_drm_crtc.h"
> @@ -41,6 +43,10 @@ struct mtk_drm_crtc {
> unsigned int layer_nr;
> bool pending_planes;
> bool cursor_update;
> +
> + struct cmdq_client *cmdq_client;
> + u32 cmdq_event;
> +
> void __iomem *config_regs;
> const struct mtk_mmsys_reg_data *mmsys_reg_data;
> struct mtk_disp_mutex *mutex;
> @@ -57,6 +63,12 @@ struct mtk_crtc_state {
> unsigned int pending_width;
> unsigned int pending_height;
> unsigned int pending_vrefresh;
> + struct cmdq_pkt *cmdq_handle;
> +};
> +
> +struct mtk_cmdq_cb_data {
> + struct drm_crtc_state *state;
> + struct cmdq_pkt *cmdq_handle;
> };
>
> static inline struct mtk_drm_crtc *to_mtk_crtc(struct drm_crtc *c)
> @@ -208,6 +220,46 @@ static void mtk_crtc_ddp_clk_disable(struct mtk_drm_crtc *mtk_crtc)
> clk_disable_unprepare(mtk_crtc->ddp_comp[i]->clk);
> }
>
> +static void ddp_cmdq_cursor_cb(struct cmdq_cb_data data)
> +{
> +
> +#if IS_ENABLED(CONFIG_MTK_CMDQ)
I would like the whole ddp_cmdq_cursor_cb() and ddp_cmdq_cb() inside
this part.
> + struct mtk_cmdq_cb_data *cb_data = data.data;
> +
> + DRM_DEBUG_DRIVER("%s\n", __func__);
> +
> + cmdq_pkt_destroy(cb_data->cmdq_handle);
> + kfree(cb_data);
> +#endif
> +
> +}
> +
> +static void ddp_cmdq_cb(struct cmdq_cb_data data)
> +{
> +
> +#if IS_ENABLED(CONFIG_MTK_CMDQ)
> + struct mtk_cmdq_cb_data *cb_data = data.data;
> + struct drm_crtc_state *crtc_state = cb_data->state;
> + struct drm_atomic_state *atomic_state = crtc_state->state;
> + struct drm_crtc *crtc = crtc_state->crtc;
> + struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
> +
> + DRM_DEBUG_DRIVER("%s\n", __func__);
> +
> + if (mtk_crtc->pending_needs_vblank) {
> + /* cmdq_vblank_event must be read after cmdq_needs_event */
> + smp_rmb();
> +
> + mtk_drm_crtc_finish_page_flip(mtk_crtc);
> + mtk_crtc->pending_needs_vblank = false;
> + }
> + mtk_atomic_state_put_queue(atomic_state);
> + cmdq_pkt_destroy(cb_data->cmdq_handle);
> + kfree(cb_data);
> +#endif
> +
> +}
> +
> static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
> {
> struct drm_crtc *crtc = &mtk_crtc->base;
> @@ -283,7 +335,8 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
> if (prev == DDP_COMPONENT_OVL0)
> mtk_ddp_comp_bgclr_in_on(comp);
>
> - mtk_ddp_comp_config(comp, width, height, vrefresh, bpc);
> + mtk_ddp_comp_config(comp, width, height,
> + vrefresh, bpc, NULL);
> mtk_ddp_comp_start(comp);
> }
>
> @@ -303,7 +356,7 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
> } else
> local_layer = i;
> mtk_ddp_comp_layer_config(comp, local_layer,
> - plane_state);
> + plane_state, NULL);
> }
>
> return 0;
> @@ -361,7 +414,7 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
> if (state->pending_config) {
> mtk_ddp_comp_config(comp, state->pending_width,
> state->pending_height,
> - state->pending_vrefresh, 0);
> + state->pending_vrefresh, 0, NULL);
>
> state->pending_config = false;
> }
> @@ -381,7 +434,7 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
> local_layer = i;
>
> mtk_ddp_comp_layer_config(comp, local_layer,
> - plane_state);
> + plane_state, NULL);
> plane_state->pending.config = false;
> }
> }
> @@ -405,26 +458,69 @@ void mtk_drm_crtc_cursor_update(struct drm_crtc *crtc, struct drm_plane *plane,
> return;
>
> mutex_lock(&priv->hw_lock);
> - plane_helper_funcs->atomic_update(plane, plane_state);
> - for (i = 0; i < mtk_crtc->layer_nr; i++) {
> - struct drm_plane *plane = &mtk_crtc->planes[i];
> - struct mtk_plane_state *plane_state;
> + if (IS_ENABLED(CONFIG_MTK_CMDQ) && mtk_crtc->cmdq_client) {
> + struct mtk_crtc_state *mtk_crtc_state =
> + to_mtk_crtc_state(crtc->state);
> + struct mtk_cmdq_cb_data *cb_data;
> +
> + mtk_crtc_state->cmdq_handle =
> + cmdq_pkt_create(mtk_crtc->cmdq_client,
> + PAGE_SIZE);
> + cmdq_pkt_clear_event(mtk_crtc_state->cmdq_handle,
> + mtk_crtc->cmdq_event);
> + cmdq_pkt_wfe(mtk_crtc_state->cmdq_handle, mtk_crtc->cmdq_event);
> + plane_helper_funcs->atomic_update(plane, plane_state);
> + cb_data = kmalloc(sizeof(*cb_data), GFP_KERNEL);
> + cb_data->cmdq_handle = mtk_crtc_state->cmdq_handle;
> + cmdq_pkt_flush_async(mtk_crtc_state->cmdq_handle,
> + ddp_cmdq_cursor_cb, cb_data);
> + } else {
> + plane_helper_funcs->atomic_update(plane, plane_state);
>
> - plane_state = to_mtk_plane_state(plane->state);
> - if (plane_state->pending.dirty) {
> - plane_state->pending.config = true;
> - plane_state->pending.dirty = false;
> + for (i = 0; i < mtk_crtc->layer_nr; i++) {
> + struct drm_plane *plane = &mtk_crtc->planes[i];
> + struct mtk_plane_state *plane_state;
> +
> + plane_state = to_mtk_plane_state(plane->state);
> + if (plane_state->pending.dirty) {
> + plane_state->pending.config = true;
> + plane_state->pending.dirty = false;
> + }
> + }
> + mtk_crtc->pending_planes = true;
> + mtk_crtc->cursor_update = true;
> + if (priv->data->shadow_register) {
> + mtk_disp_mutex_acquire(mtk_crtc->mutex);
> + mtk_crtc_ddp_config(crtc);
> + mtk_disp_mutex_release(mtk_crtc->mutex);
> }
> }
> - mtk_crtc->pending_planes = true;
> - mtk_crtc->cursor_update = true;
> + mutex_unlock(&priv->hw_lock);
> +}
>
> - if (priv->data->shadow_register) {
> - mtk_disp_mutex_acquire(mtk_crtc->mutex);
> - mtk_crtc_ddp_config(crtc);
> - mtk_disp_mutex_release(mtk_crtc->mutex);
My idea for the control flow is:
1. In the end of mtk_drm_crtc_atomic_flush(), do something like shadow
register control,
if (priv->data->cmdq) {
/* abort cmd in queue */
/* Call mtk_crtc_ddp_config() to generate command */
/* send cmd to queue */
}
2. In mtk_crtc_ddp_config(), if cmdq is used, state->pending_config and
mtk_crtc->pending_planes would not be set to false. These two variable
would be set to false in cmdq callback.
Regards,
CK
> +void mtk_drm_crtc_plane_update(struct drm_crtc *crtc, struct drm_plane *plane,
> + struct mtk_plane_state *state)
> +{
> + struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
> + struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
> + struct drm_crtc_state *crtc_state = crtc->state;
> + struct mtk_crtc_state *mtk_crtc_state = to_mtk_crtc_state(crtc_state);
> + struct cmdq_pkt *cmdq_handle = mtk_crtc_state->cmdq_handle;
> + unsigned int comp_layer_nr = mtk_ddp_comp_layer_nr(comp);
> + unsigned int local_layer;
> + unsigned int plane_index = plane - mtk_crtc->planes;
> +
> + DRM_DEBUG_DRIVER("%s\n", __func__);
> + if (mtk_crtc->cmdq_client) {
> + if (plane_index >= comp_layer_nr) {
> + comp = mtk_crtc->ddp_comp[1];
> + local_layer = plane_index - comp_layer_nr;
> + } else {
> + local_layer = plane_index;
> + }
> + mtk_ddp_comp_layer_config(comp, local_layer, state,
> + cmdq_handle);
> }
> - mutex_unlock(&priv->hw_lock);
> }
>
> static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc,
> @@ -487,6 +583,15 @@ static void mtk_drm_crtc_atomic_begin(struct drm_crtc *crtc,
> WARN_ON(drm_crtc_vblank_get(crtc) != 0);
> mtk_crtc->event = state->base.event;
> state->base.event = NULL;
> + /* Make sure the above parameter is set before update */
> + smp_wmb();
> + mtk_crtc->pending_needs_vblank = true;
> + }
> + if (IS_ENABLED(CONFIG_MTK_CMDQ) && mtk_crtc->cmdq_client) {
> + state->cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client,
> + PAGE_SIZE);
> + cmdq_pkt_clear_event(state->cmdq_handle, mtk_crtc->cmdq_event);
> + cmdq_pkt_wfe(state->cmdq_handle, mtk_crtc->cmdq_event);
> }
> }
>
> @@ -494,13 +599,29 @@ static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
> struct drm_crtc_state *old_crtc_state)
> {
> struct drm_atomic_state *old_atomic_state = old_crtc_state->state;
> + struct drm_crtc_state *crtc_state = crtc->state;
> + struct mtk_crtc_state *state = to_mtk_crtc_state(crtc_state);
> + struct cmdq_pkt *cmdq_handle = state->cmdq_handle;
> struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
> struct mtk_drm_private *priv = crtc->dev->dev_private;
> + struct mtk_cmdq_cb_data *cb_data;
> unsigned int pending_planes = 0;
> int i;
>
> - if (mtk_crtc->event)
> - mtk_crtc->pending_needs_vblank = true;
> + DRM_DEBUG_DRIVER("[CRTC:%u] [STATE:%p(%p)->%p(%p)]\n", crtc->base.id,
> + old_crtc_state, old_crtc_state->state,
> + crtc_state, crtc_state->state);
> +
> + if (IS_ENABLED(CONFIG_MTK_CMDQ) && mtk_crtc->cmdq_client) {
> + drm_atomic_state_get(old_atomic_state);
> + cb_data = kmalloc(sizeof(*cb_data), GFP_KERNEL);
> + cb_data->state = old_crtc_state;
> + cb_data->cmdq_handle = cmdq_handle;
> + cmdq_pkt_flush_async(cmdq_handle, ddp_cmdq_cb, cb_data);
> +
> + return;
> + }
> +
> for (i = 0; i < mtk_crtc->layer_nr; i++) {
> struct drm_plane *plane = &mtk_crtc->planes[i];
> struct mtk_plane_state *plane_state;
> @@ -521,7 +642,8 @@ static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
>
> if (crtc->state->color_mgmt_changed)
> for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
> - mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
> + mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i],
> + crtc->state, NULL);
>
> if (priv->data->shadow_register) {
> mtk_disp_mutex_acquire(mtk_crtc->mutex);
> @@ -578,10 +700,13 @@ void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *comp)
> struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
> struct mtk_drm_private *priv = crtc->dev->dev_private;
>
> - if (!priv->data->shadow_register)
> - mtk_crtc_ddp_config(crtc);
> -
> - mtk_drm_finish_page_flip(mtk_crtc);
> + if (mtk_crtc->cmdq_client) {
> + drm_crtc_handle_vblank(crtc);
> + } else {
> + if (!priv->data->shadow_register)
> + mtk_crtc_ddp_config(crtc);
> + mtk_drm_finish_page_flip(mtk_crtc);
> + }
> }
>
> int mtk_drm_crtc_create(struct drm_device *drm_dev,
> @@ -678,5 +803,18 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, MTK_LUT_SIZE);
> priv->num_pipes++;
>
> + if (IS_ENABLED(CONFIG_MTK_CMDQ)) {
> + mtk_crtc->cmdq_client = cmdq_mbox_create(dev,
> + drm_crtc_index(&mtk_crtc->base), 2000);
> + of_property_read_u32_index(dev->of_node, "mediatek,gce-events",
> + drm_crtc_index(&mtk_crtc->base),
> + &mtk_crtc->cmdq_event);
> + if (IS_ERR(mtk_crtc->cmdq_client)) {
> + dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n",
> + drm_crtc_index(&mtk_crtc->base));
> + mtk_crtc->cmdq_client = NULL;
> + }
> + }
> +
> return 0;
> }
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> index 46e903be68ec..6b2423c88416 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> @@ -19,6 +19,8 @@ void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *comp);
> int mtk_drm_crtc_create(struct drm_device *drm_dev,
> const enum mtk_ddp_comp_id *path,
> unsigned int path_len);
> +void mtk_drm_crtc_plane_update(struct drm_crtc *crtc, struct drm_plane *plane,
> + struct mtk_plane_state *state);
> void mtk_drm_crtc_cursor_update(struct drm_crtc *crtc, struct drm_plane *plane,
> struct drm_plane_state *plane_state);
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 76416c1cbb28..056ebc6a8199 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -395,6 +395,40 @@ int mtk_ddp_comp_init(struct device *dev, struct device_node *node,
> if (IS_ERR(comp->clk))
> return PTR_ERR(comp->clk);
>
> + if (IS_ENABLED(CONFIG_MTK_CMDQ)) {
> + struct platform_device *comp_pdev;
> + struct resource res;
> + struct cmdq_client_reg *cmdq_reg;
> + int ret = 0;
> +
> + if (of_address_to_resource(node, 0, &res) != 0) {
> + dev_err(dev, "Missing reg in %s node\n",
> + node->full_name);
> + return -EINVAL;
> + }
> + comp->regs_pa = res.start;
> +
> + comp_pdev = of_find_device_by_node(node);
> + if (!comp_pdev) {
> + dev_warn(dev, "Waiting for component device %s\n",
> + node->full_name);
> + return -EPROBE_DEFER;
> + }
> +
> + cmdq_reg = kzalloc(sizeof(*cmdq_reg), GFP_KERNEL);
> + if (!cmdq_reg)
> + return -EINVAL;
> +
> + ret = cmdq_dev_get_client_reg(&comp_pdev->dev, cmdq_reg, 0);
> + if (ret != 0)
> + dev_dbg(&comp_pdev->dev,
> + "get mediatek,gce-client-reg fail!\n");
> + else
> + comp->subsys = cmdq_reg->subsys;
> +
> + kfree(cmdq_reg);
> + }
> +
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index 6bbc35f92815..0faec2dad5a3 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -99,6 +99,8 @@ struct mtk_ddp_comp {
> int irq;
> enum mtk_ddp_comp_id id;
> const struct mtk_ddp_comp_funcs *funcs;
> + resource_size_t regs_pa;
> + u8 subsys;
> };
>
> static inline void mtk_ddp_comp_config(struct mtk_ddp_comp *comp,
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.c b/drivers/gpu/drm/mediatek/mtk_drm_plane.c
> index 59dbdaf07425..ef46c0f43039 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_plane.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.c
> @@ -202,6 +202,8 @@ static void mtk_plane_atomic_update(struct drm_plane *plane,
> state->pending.height = drm_rect_height(&plane->state->dst);
> wmb(); /* Make sure the above parameters are set before update */
> state->pending.dirty = true;
> +
> + mtk_drm_crtc_plane_update(crtc, plane, state);
> }
>
> static void mtk_plane_atomic_disable(struct drm_plane *plane,
> @@ -212,6 +214,8 @@ static void mtk_plane_atomic_disable(struct drm_plane *plane,
> state->pending.enable = false;
> wmb(); /* Make sure the above parameter is set before update */
> state->pending.dirty = true;
> + /* Fetch CRTC from old plane state when disabling. */
> + mtk_drm_crtc_plane_update(old_state->crtc, plane, state);
> }
>
> static const struct drm_plane_helper_funcs mtk_plane_helper_funcs = {
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* Re: [RESEND PATCH 0/5] Add bluetooth support for Orange Pi 3
From: Marcel Holtmann @ 2019-08-30 7:53 UTC (permalink / raw)
To: megous
Cc: Mark Rutland, devicetree, Johan Hedberg, netdev, linux-kernel,
Maxime Ripard, linux-bluetooth, Chen-Yu Tsai, Rob Herring,
David S. Miller, linux-arm-kernel
In-Reply-To: <20190823103139.17687-1-megous@megous.com>
Hi Ondrej,
> (Resend to add missing lists, sorry for the noise.)
>
> This series implements bluetooth support for Xunlong Orange Pi 3 board.
>
> The board uses AP6256 WiFi/BT 5.0 chip.
>
> Summary of changes:
>
> - add more delay to let initialize the chip
> - let the kernel detect firmware file path
> - add new compatible and update dt-bindings
> - update Orange Pi 3 / H6 DTS
>
> Please take a look.
>
> thank you and regards,
> Ondrej Jirman
>
> Ondrej Jirman (5):
> dt-bindings: net: Add compatible for BCM4345C5 bluetooth device
> bluetooth: bcm: Add support for loading firmware for BCM4345C5
> bluetooth: hci_bcm: Give more time to come out of reset
> arm64: dts: allwinner: h6: Add pin configs for uart1
> arm64: dts: allwinner: orange-pi-3: Enable UART1 / Bluetooth
>
> .../bindings/net/broadcom-bluetooth.txt | 1 +
> .../dts/allwinner/sun50i-h6-orangepi-3.dts | 19 +++++++++++++++++++
> arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 ++++++++++
> drivers/bluetooth/btbcm.c | 3 +++
> drivers/bluetooth/hci_bcm.c | 3 ++-
> 5 files changed, 35 insertions(+), 1 deletion(-)
all 5 patches have been applied to bluetooth-next tree.
Regards
Marcel
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* Re: [PATCH v5 1/2] dt-bindings: mailbox: add binding doc for the ARM SMC/HVC mailbox
From: Jassi Brar @ 2019-08-30 7:52 UTC (permalink / raw)
To: Peng Fan
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
f.fainelli@gmail.com, andre.przywara@arm.com,
linux-kernel@vger.kernel.org, robh+dt@kernel.org, dl-linux-imx,
sudeep.holla@arm.com, linux-arm-kernel@lists.infradead.org
In-Reply-To: <AM0PR04MB448161C632722DF10989008088BD0@AM0PR04MB4481.eurprd04.prod.outlook.com>
On Fri, Aug 30, 2019 at 2:37 AM Peng Fan <peng.fan@nxp.com> wrote:
>
> Hi Jassi,
>
> > Subject: Re: [PATCH v5 1/2] dt-bindings: mailbox: add binding doc for the ARM
> > SMC/HVC mailbox
> >
> > On Fri, Aug 30, 2019 at 1:28 AM Peng Fan <peng.fan@nxp.com> wrote:
> >
> > > > > +examples:
> > > > > + - |
> > > > > + sram@910000 {
> > > > > + compatible = "mmio-sram";
> > > > > + reg = <0x0 0x93f000 0x0 0x1000>;
> > > > > + #address-cells = <1>;
> > > > > + #size-cells = <1>;
> > > > > + ranges = <0 0x0 0x93f000 0x1000>;
> > > > > +
> > > > > + cpu_scp_lpri: scp-shmem@0 {
> > > > > + compatible = "arm,scmi-shmem";
> > > > > + reg = <0x0 0x200>;
> > > > > + };
> > > > > +
> > > > > + cpu_scp_hpri: scp-shmem@200 {
> > > > > + compatible = "arm,scmi-shmem";
> > > > > + reg = <0x200 0x200>;
> > > > > + };
> > > > > + };
> > > > > +
> > > > > + firmware {
> > > > > + smc_mbox: mailbox {
> > > > > + #mbox-cells = <1>;
> > > > > + compatible = "arm,smc-mbox";
> > > > > + method = "smc";
> > > > > + arm,num-chans = <0x2>;
> > > > > + transports = "mem";
> > > > > + /* Optional */
> > > > > + arm,func-ids = <0xc20000fe>, <0xc20000ff>;
> > > > >
> > > > SMC/HVC is synchronously(block) running in "secure mode", i.e, there
> > > > can only be one instance running platform wide. Right?
> > >
> > > I think there could be channel for TEE, and channel for Linux.
> > > For virtualization case, there could be dedicated channel for each VM.
> > >
> > I am talking from Linux pov. Functions 0xfe and 0xff above, can't both be
> > active at the same time, right?
>
> If I get your point correctly,
> On UP, both could not be active. On SMP, tx/rx could be both active, anyway
> this depends on secure firmware and Linux firmware design.
>
> Do you have any suggestions about arm,func-ids here?
>
I was thinking if this is just an instruction, why can't each channel
be represented as a controller, i.e, have exactly one func-id per
controller node. Define as many controllers as you need channels ?
-j
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* Re: [PATCH v5 10/10] arm64: atomics: Use K constraint when toolchain appears to support it
From: Will Deacon @ 2019-08-30 7:52 UTC (permalink / raw)
To: Andrew Murray
Cc: mark.rutland, peterz, catalin.marinas, ndesaulniers,
Ard.Biesheuvel, natechancellor, robin.murphy, linux-arm-kernel
In-Reply-To: <20190830000803.GR14582@e119886-lin.cambridge.arm.com>
On Fri, Aug 30, 2019 at 01:08:03AM +0100, Andrew Murray wrote:
> On Thu, Aug 29, 2019 at 05:54:58PM +0100, Will Deacon wrote:
> > On Thu, Aug 29, 2019 at 04:48:34PM +0100, Will Deacon wrote:
> > > diff --git a/arch/arm64/include/asm/atomic_ll_sc.h b/arch/arm64/include/asm/atomic_ll_sc.h
> > > index 95091f72228b..7fa042f5444e 100644
> > > --- a/arch/arm64/include/asm/atomic_ll_sc.h
> > > +++ b/arch/arm64/include/asm/atomic_ll_sc.h
> > > @@ -23,6 +23,10 @@ asm_ops "\n" \
> > > #define __LL_SC_FALLBACK(asm_ops) asm_ops
> > > #endif
> > >
> > > +#ifndef CONFIG_CC_HAS_K_CONSTRAINT
> > > +#define K
> > > +#endif
> >
> > Bah, I need to use something like __stringify when the constraint is used
> > in order for this to get expanded properly. Updated diff below.
>
> I don't think the changes in your updated diff are required. We successfully
> combine 'asm_op' with the remainder of the assembly string without using
> __stringify, and this is no different to how the original patch combined
> 'constraint' with "r".
It's a hack: __stringify expands its arguments, so I figured I may as well
use that rather than do it manually with an extra macro.
> You can verify this by looking at the preprocessed .i files generated with
> something like:
>
> make ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- drivers/spi/spi-rockchip.i
>
> I see no difference (with GCC 7.3.1) between the original approach and your
> use of __stringify. Incidentally you end up with "K" "r" instead of "Kr" but
> it seems to have the desired effect (e.g. supress/emit out of range errors).
> I have a couple of macros that resolves this to "Kr" but I don't think it's
> necessary.
>
> Did you find that it didn't work without your changes? I found it hard to
> reproduce the out-of-range errors until I made the following change, I could
> then easily see the effect of changing the constraint:
>
> : "=&r" (result), "=&r" (tmp), "+Q" (v->counter) \
> - : #constraint "r" (i)); \
> + : #constraint) "r" (4294967295)); \
> }
Without the __stringify I get a compilation failure when building
kernel/panic.o because it tries to cmpxchg a 32-bit variable with -1
(PANIC_CPU_INVALID). Looking at panic.s, I see that constraint parameter
isn't being expanded. For example if I do:
#ifndef CONFIG_CC_HAS_K_CONSTRAINT
#define INVALID_CONSTRAINT
#else
#define INVALID_CONSTRAINT K
#endif
and then pass INVALID_CONSTRAINT to the generator macros, we'll end up
with INVALID_CONSTRAINT in the .s file and gas will barf.
The reason I didn't see this initially is because my silly testcase had
a typo and was using atomic_add instead of atomic_and.
Will
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* [PATCH 2/2] mmc: sdhci-of-aspeed: Allow max-frequency limitation of SDCLK
From: Andrew Jeffery @ 2019-08-30 7:46 UTC (permalink / raw)
To: linux-mmc
Cc: ulf.hansson, linux-aspeed, Andrew Jeffery, openbmc,
ryanchen.aspeed, adrian.hunter, linux-kernel, joel,
linux-arm-kernel
In-Reply-To: <20190830074644.10936-1-andrew@aj.id.au>
Add a get_max_clock() handler to sdhci-of-aspeed to report f_max as the
maximum clock rate if it is set. This enables artificial limitation of
the bus speed via max-frequency in the devicetree for e.g. the AST2600
evaluation board where I am seeing errors at 200MHz.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
drivers/mmc/host/sdhci-of-aspeed.c | 20 ++++++++++++++++++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/sdhci-of-aspeed.c b/drivers/mmc/host/sdhci-of-aspeed.c
index a9175ca85696..5cc00abcd71f 100644
--- a/drivers/mmc/host/sdhci-of-aspeed.c
+++ b/drivers/mmc/host/sdhci-of-aspeed.c
@@ -52,16 +52,24 @@ static void aspeed_sdc_configure_8bit_mode(struct aspeed_sdc *sdc,
static void aspeed_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
{
+ struct sdhci_pltfm_host *pltfm_host;
+ unsigned long parent;
int div;
u16 clk;
+ pltfm_host = sdhci_priv(host);
+ parent = clk_get_rate(pltfm_host->clk);
+
sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
if (clock == 0)
goto out;
+ if (WARN_ON(clock > host->max_clk))
+ clock = host->max_clk;
+
for (div = 1; div < 256; div *= 2) {
- if ((host->max_clk / div) <= clock)
+ if ((parent / div) <= clock)
break;
}
div >>= 1;
@@ -74,6 +82,14 @@ static void aspeed_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
host->clock = clock;
}
+static unsigned int aspeed_sdhci_get_max_clock(struct sdhci_host *host)
+{
+ if (host->mmc->f_max)
+ return host->mmc->f_max;
+
+ return sdhci_pltfm_clk_get_max_clock(host);
+}
+
static void aspeed_sdhci_set_bus_width(struct sdhci_host *host, int width)
{
struct sdhci_pltfm_host *pltfm_priv;
@@ -100,7 +116,7 @@ static void aspeed_sdhci_set_bus_width(struct sdhci_host *host, int width)
static const struct sdhci_ops aspeed_sdhci_ops = {
.set_clock = aspeed_sdhci_set_clock,
- .get_max_clock = sdhci_pltfm_clk_get_max_clock,
+ .get_max_clock = aspeed_sdhci_get_max_clock,
.set_bus_width = aspeed_sdhci_set_bus_width,
.get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
.reset = sdhci_reset,
--
2.20.1
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* [PATCH 1/2] mmc: sdhci-of-aspeed: Uphold clocks-on post-condition of set_clock()
From: Andrew Jeffery @ 2019-08-30 7:46 UTC (permalink / raw)
To: linux-mmc
Cc: ulf.hansson, linux-aspeed, Andrew Jeffery, openbmc,
ryanchen.aspeed, adrian.hunter, linux-kernel, joel,
linux-arm-kernel
In-Reply-To: <20190830074644.10936-1-andrew@aj.id.au>
The early-exit didn't seem to matter on the AST2500, but on the AST2600
the SD clock genuinely may not be running on entry to
aspeed_sdhci_set_clock(). Remove the early exit to ensure we always run
sdhci_enable_clk().
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
drivers/mmc/host/sdhci-of-aspeed.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/mmc/host/sdhci-of-aspeed.c b/drivers/mmc/host/sdhci-of-aspeed.c
index d5acb5afc50f..a9175ca85696 100644
--- a/drivers/mmc/host/sdhci-of-aspeed.c
+++ b/drivers/mmc/host/sdhci-of-aspeed.c
@@ -55,9 +55,6 @@ static void aspeed_sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
int div;
u16 clk;
- if (clock == host->clock)
- return;
-
sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
if (clock == 0)
--
2.20.1
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* [PATCH 0/2] mmc: sdhci-of-aspeed: Fixes for AST2600 eMMC support
From: Andrew Jeffery @ 2019-08-30 7:46 UTC (permalink / raw)
To: linux-mmc
Cc: ulf.hansson, linux-aspeed, Andrew Jeffery, openbmc,
ryanchen.aspeed, adrian.hunter, linux-kernel, joel,
linux-arm-kernel
Hello,
The ASPEED SDHCI driver patches sent previously were based on testing on the
AST2500. The SD controllers in the 2500 and 2600 had the same register layout
according to the documentation, so we added the necessary devicetree compatible
string at the same time.
Now that I've got access to 2600 hardware with an eMMC chip I have a couple of
patches that are fixes enabling support for it. I don't think the first patch
is too controversial - in some cases we weren't ensuring the clock was enabled
before returning from the set_clock() callback.
I'm a bit unsure about the second patch though which enables use of
max-frequency in the devicetree, it feels a bit hacky so I'm looking for any
suggestions on the approach.
Please review!
Andrew
Andrew Jeffery (2):
mmc: sdhci-of-aspeed: Uphold clocks-on post-condition of set_clock()
mmc: sdhci-of-aspeed: Allow max-frequency limitation of SDCLK
drivers/mmc/host/sdhci-of-aspeed.c | 21 +++++++++++++++++----
1 file changed, 17 insertions(+), 4 deletions(-)
--
2.20.1
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* [PATCH v3 7/7] arm64: dts: mt8183: tune disconnect threshold of u2phy
From: Chunfeng Yun @ 2019-08-30 7:40 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring
Cc: Mark Rutland, devicetree, Mathias Nyman, linux-usb, linux-kernel,
Chunfeng Yun, linux-mediatek, Matthias Brugger, linux-arm-kernel
In-Reply-To: <1567150854-30033-1-git-send-email-chunfeng.yun@mediatek.com>
Set DISCTH to max-15, replace the default value 8, due to
default disconnect threshold is lower than USB SPEC define
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v3: no changes
v2: new patch
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index dc3e859849c7..5168e345ea3f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -434,6 +434,7 @@
clocks = <&clk26m>;
clock-names = "ref";
#phy-cells = <1>;
+ mediatek,discth = <15>;
status = "okay";
};
--
2.23.0
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* [PATCH 1/2] drm/mediatek: Support CMDQ interface in ddp component
From: Bibby Hsieh @ 2019-08-30 7:41 UTC (permalink / raw)
To: David Airlie, Matthias Brugger, Daniel Vetter, dri-devel,
linux-mediatek
Cc: drinkcat, Bibby Hsieh, Yongqiang Niu, linux-kernel, tfiga, CK Hu,
Thierry Reding, Philipp Zabel, YT Shen, linux-arm-kernel
In-Reply-To: <20190830074103.16671-1-bibby.hsieh@mediatek.com>
The CMDQ (Command Queue) in MT8183 is used to help
update all relevant display controller registers
with critical time limation.
This patch add cmdq interface in ddp_comp interface,
let all ddp_comp interface can support cpu/cmdq function
at the same time.
Signed-off-by: YT Shen <yt.shen@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_disp_color.c | 7 +-
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 78 +++++++-------
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 66 ++++++------
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 110 ++++++++++++++------
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 53 ++++++----
5 files changed, 187 insertions(+), 127 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_color.c b/drivers/gpu/drm/mediatek/mtk_disp_color.c
index f33d98b356d6..c5d3e3cf8ad5 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_color.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_color.c
@@ -9,6 +9,7 @@
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
#include "mtk_drm_crtc.h"
#include "mtk_drm_ddp_comp.h"
@@ -45,12 +46,12 @@ static inline struct mtk_disp_color *comp_to_color(struct mtk_ddp_comp *comp)
static void mtk_color_config(struct mtk_ddp_comp *comp, unsigned int w,
unsigned int h, unsigned int vrefresh,
- unsigned int bpc)
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
{
struct mtk_disp_color *color = comp_to_color(comp);
- writel(w, comp->regs + DISP_COLOR_WIDTH(color));
- writel(h, comp->regs + DISP_COLOR_HEIGHT(color));
+ mtk_ddp_write(cmdq_pkt, w, comp, DISP_COLOR_WIDTH(color));
+ mtk_ddp_write(cmdq_pkt, h, comp, DISP_COLOR_HEIGHT(color));
}
static void mtk_color_start(struct mtk_ddp_comp *comp)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 94c80c215c6e..f11c785199d3 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -9,6 +9,7 @@
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
#include "mtk_drm_crtc.h"
#include "mtk_drm_ddp_comp.h"
@@ -120,14 +121,15 @@ static void mtk_ovl_stop(struct mtk_ddp_comp *comp)
static void mtk_ovl_config(struct mtk_ddp_comp *comp, unsigned int w,
unsigned int h, unsigned int vrefresh,
- unsigned int bpc)
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
{
if (w != 0 && h != 0)
- writel_relaxed(h << 16 | w, comp->regs + DISP_REG_OVL_ROI_SIZE);
- writel_relaxed(0x0, comp->regs + DISP_REG_OVL_ROI_BGCLR);
+ mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, comp,
+ DISP_REG_OVL_ROI_SIZE);
+ mtk_ddp_write_relaxed(cmdq_pkt, 0x0, comp, DISP_REG_OVL_ROI_BGCLR);
- writel(0x1, comp->regs + DISP_REG_OVL_RST);
- writel(0x0, comp->regs + DISP_REG_OVL_RST);
+ mtk_ddp_write(cmdq_pkt, 0x1, comp, DISP_REG_OVL_RST);
+ mtk_ddp_write(cmdq_pkt, 0x0, comp, DISP_REG_OVL_RST);
}
static unsigned int mtk_ovl_layer_nr(struct mtk_ddp_comp *comp)
@@ -137,7 +139,8 @@ static unsigned int mtk_ovl_layer_nr(struct mtk_ddp_comp *comp)
return ovl->data->layer_nr;
}
-static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx)
+static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx,
+ struct cmdq_pkt *cmdq_pkt)
{
unsigned int reg;
unsigned int gmc_thrshd_l;
@@ -145,8 +148,8 @@ static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx)
unsigned int gmc_value;
struct mtk_disp_ovl *ovl = comp_to_ovl(comp);
- writel(0x1, comp->regs + DISP_REG_OVL_RDMA_CTRL(idx));
-
+ mtk_ddp_write(cmdq_pkt, 0x1, comp,
+ DISP_REG_OVL_RDMA_CTRL(idx));
gmc_thrshd_l = GMC_THRESHOLD_LOW >>
(GMC_THRESHOLD_BITS - ovl->data->gmc_bits);
gmc_thrshd_h = GMC_THRESHOLD_HIGH >>
@@ -156,22 +159,19 @@ static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx)
else
gmc_value = gmc_thrshd_l | gmc_thrshd_l << 8 |
gmc_thrshd_h << 16 | gmc_thrshd_h << 24;
- writel(gmc_value, comp->regs + DISP_REG_OVL_RDMA_GMC(idx));
-
- reg = readl(comp->regs + DISP_REG_OVL_SRC_CON);
- reg = reg | BIT(idx);
- writel(reg, comp->regs + DISP_REG_OVL_SRC_CON);
+ mtk_ddp_write(cmdq_pkt, gmc_value,
+ comp, DISP_REG_OVL_RDMA_GMC(idx));
+ mtk_ddp_write_mask(cmdq_pkt, BIT(idx), comp,
+ DISP_REG_OVL_SRC_CON, BIT(idx));
}
-static void mtk_ovl_layer_off(struct mtk_ddp_comp *comp, unsigned int idx)
+static void mtk_ovl_layer_off(struct mtk_ddp_comp *comp, unsigned int idx,
+ struct cmdq_pkt *cmdq_pkt)
{
- unsigned int reg;
-
- reg = readl(comp->regs + DISP_REG_OVL_SRC_CON);
- reg = reg & ~BIT(idx);
- writel(reg, comp->regs + DISP_REG_OVL_SRC_CON);
-
- writel(0x0, comp->regs + DISP_REG_OVL_RDMA_CTRL(idx));
+ mtk_ddp_write_mask(cmdq_pkt, 0, comp,
+ DISP_REG_OVL_SRC_CON, BIT(idx));
+ mtk_ddp_write(cmdq_pkt, 0, comp,
+ DISP_REG_OVL_RDMA_CTRL(idx));
}
static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt)
@@ -211,7 +211,8 @@ static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, unsigned int fmt)
}
static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
- struct mtk_plane_state *state)
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt)
{
struct mtk_disp_ovl *ovl = comp_to_ovl(comp);
struct mtk_plane_pending_state *pending = &state->pending;
@@ -223,38 +224,37 @@ static void mtk_ovl_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
unsigned int con;
if (!pending->enable)
- mtk_ovl_layer_off(comp, idx);
+ mtk_ovl_layer_off(comp, idx, cmdq_pkt);
con = ovl_fmt_convert(ovl, fmt);
if (idx != 0)
con |= OVL_CON_AEN | OVL_CON_ALPHA;
- writel_relaxed(con, comp->regs + DISP_REG_OVL_CON(idx));
- writel_relaxed(pitch, comp->regs + DISP_REG_OVL_PITCH(idx));
- writel_relaxed(src_size, comp->regs + DISP_REG_OVL_SRC_SIZE(idx));
- writel_relaxed(offset, comp->regs + DISP_REG_OVL_OFFSET(idx));
- writel_relaxed(addr, comp->regs + DISP_REG_OVL_ADDR(ovl, idx));
+ mtk_ddp_write_relaxed(cmdq_pkt, con, comp,
+ DISP_REG_OVL_CON(idx));
+ mtk_ddp_write_relaxed(cmdq_pkt, pitch, comp,
+ DISP_REG_OVL_PITCH(idx));
+ mtk_ddp_write_relaxed(cmdq_pkt, src_size, comp,
+ DISP_REG_OVL_SRC_SIZE(idx));
+ mtk_ddp_write_relaxed(cmdq_pkt, offset, comp,
+ DISP_REG_OVL_OFFSET(idx));
+ mtk_ddp_write_relaxed(cmdq_pkt, addr, comp,
+ DISP_REG_OVL_ADDR(ovl, idx));
if (pending->enable)
- mtk_ovl_layer_on(comp, idx);
+ mtk_ovl_layer_on(comp, idx, cmdq_pkt);
}
static void mtk_ovl_bgclr_in_on(struct mtk_ddp_comp *comp)
{
- unsigned int reg;
-
- reg = readl(comp->regs + DISP_REG_OVL_DATAPATH_CON);
- reg = reg | OVL_BGCLR_SEL_IN;
- writel(reg, comp->regs + DISP_REG_OVL_DATAPATH_CON);
+ mtk_ddp_write_mask(NULL, OVL_BGCLR_SEL_IN, comp,
+ DISP_REG_OVL_DATAPATH_CON, OVL_BGCLR_SEL_IN);
}
static void mtk_ovl_bgclr_in_off(struct mtk_ddp_comp *comp)
{
- unsigned int reg;
-
- reg = readl(comp->regs + DISP_REG_OVL_DATAPATH_CON);
- reg = reg & ~OVL_BGCLR_SEL_IN;
- writel(reg, comp->regs + DISP_REG_OVL_DATAPATH_CON);
+ mtk_ddp_write_mask(NULL, 0, comp,
+ DISP_REG_OVL_DATAPATH_CON, OVL_BGCLR_SEL_IN);
}
static const struct mtk_ddp_comp_funcs mtk_disp_ovl_funcs = {
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 24945fec00b1..6df372dac3e3 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -9,6 +9,7 @@
#include <linux/of_device.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
#include "mtk_drm_crtc.h"
#include "mtk_drm_ddp_comp.h"
@@ -86,23 +87,14 @@ static irqreturn_t mtk_disp_rdma_irq_handler(int irq, void *dev_id)
return IRQ_HANDLED;
}
-static void rdma_update_bits(struct mtk_ddp_comp *comp, unsigned int reg,
- unsigned int mask, unsigned int val)
-{
- unsigned int tmp = readl(comp->regs + reg);
-
- tmp = (tmp & ~mask) | (val & mask);
- writel(tmp, comp->regs + reg);
-}
-
static void mtk_rdma_enable_vblank(struct mtk_ddp_comp *comp,
struct drm_crtc *crtc)
{
struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
rdma->crtc = crtc;
- rdma_update_bits(comp, DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT,
- RDMA_FRAME_END_INT);
+ mtk_ddp_write_mask(NULL, RDMA_FRAME_END_INT, comp,
+ DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT);
}
static void mtk_rdma_disable_vblank(struct mtk_ddp_comp *comp)
@@ -110,31 +102,35 @@ static void mtk_rdma_disable_vblank(struct mtk_ddp_comp *comp)
struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
rdma->crtc = NULL;
- rdma_update_bits(comp, DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT, 0);
+ mtk_ddp_write_mask(NULL, 0, comp,
+ DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT);
}
static void mtk_rdma_start(struct mtk_ddp_comp *comp)
{
- rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN,
- RDMA_ENGINE_EN);
+ mtk_ddp_write_mask(NULL, RDMA_ENGINE_EN, comp,
+ DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN);
}
static void mtk_rdma_stop(struct mtk_ddp_comp *comp)
{
- rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN, 0);
+ mtk_ddp_write_mask(NULL, 0, comp,
+ DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN);
}
static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
unsigned int height, unsigned int vrefresh,
- unsigned int bpc)
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
{
unsigned int threshold;
unsigned int reg;
struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
u32 rdma_fifo_size;
- rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xfff, width);
- rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_1, 0xfffff, height);
+ mtk_ddp_write_mask(cmdq_pkt, width, comp,
+ DISP_REG_RDMA_SIZE_CON_0, 0xfff);
+ mtk_ddp_write_mask(cmdq_pkt, height, comp,
+ DISP_REG_RDMA_SIZE_CON_1, 0xfffff);
if (rdma->fifo_size)
rdma_fifo_size = rdma->fifo_size;
@@ -151,7 +147,7 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width,
reg = RDMA_FIFO_UNDERFLOW_EN |
RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) |
RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);
- writel(reg, comp->regs + DISP_REG_RDMA_FIFO_CON);
+ mtk_ddp_write(cmdq_pkt, reg, comp, DISP_REG_RDMA_FIFO_CON);
}
static unsigned int rdma_fmt_convert(struct mtk_disp_rdma *rdma,
@@ -197,7 +193,8 @@ static unsigned int mtk_rdma_layer_nr(struct mtk_ddp_comp *comp)
}
static void mtk_rdma_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
- struct mtk_plane_state *state)
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt)
{
struct mtk_disp_rdma *rdma = comp_to_rdma(comp);
struct mtk_plane_pending_state *pending = &state->pending;
@@ -207,24 +204,27 @@ static void mtk_rdma_layer_config(struct mtk_ddp_comp *comp, unsigned int idx,
unsigned int con;
con = rdma_fmt_convert(rdma, fmt);
- writel_relaxed(con, comp->regs + DISP_RDMA_MEM_CON);
+ mtk_ddp_write_relaxed(cmdq_pkt, con, comp, DISP_RDMA_MEM_CON);
if (fmt == DRM_FORMAT_UYVY || fmt == DRM_FORMAT_YUYV) {
- rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0,
- RDMA_MATRIX_ENABLE, RDMA_MATRIX_ENABLE);
- rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0,
- RDMA_MATRIX_INT_MTX_SEL,
- RDMA_MATRIX_INT_MTX_BT601_to_RGB);
+ mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_ENABLE, comp,
+ DISP_REG_RDMA_SIZE_CON_0,
+ RDMA_MATRIX_ENABLE);
+ mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_INT_MTX_BT601_to_RGB,
+ comp, DISP_REG_RDMA_SIZE_CON_0,
+ RDMA_MATRIX_INT_MTX_SEL);
} else {
- rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0,
- RDMA_MATRIX_ENABLE, 0);
+ mtk_ddp_write_mask(cmdq_pkt, 0, comp,
+ DISP_REG_RDMA_SIZE_CON_0,
+ RDMA_MATRIX_ENABLE);
}
+ mtk_ddp_write_relaxed(cmdq_pkt, addr, comp, DISP_RDMA_MEM_START_ADDR);
+ mtk_ddp_write_relaxed(cmdq_pkt, pitch, comp, DISP_RDMA_MEM_SRC_PITCH);
+ mtk_ddp_write(cmdq_pkt, RDMA_MEM_GMC, comp,
+ DISP_RDMA_MEM_GMC_SETTING_0);
+ mtk_ddp_write_mask(cmdq_pkt, RDMA_MODE_MEMORY, comp,
+ DISP_REG_RDMA_GLOBAL_CON, RDMA_MODE_MEMORY);
- writel_relaxed(addr, comp->regs + DISP_RDMA_MEM_START_ADDR);
- writel_relaxed(pitch, comp->regs + DISP_RDMA_MEM_SRC_PITCH);
- writel(RDMA_MEM_GMC, comp->regs + DISP_RDMA_MEM_GMC_SETTING_0);
- rdma_update_bits(comp, DISP_REG_RDMA_GLOBAL_CON,
- RDMA_MODE_MEMORY, RDMA_MODE_MEMORY);
}
static const struct mtk_ddp_comp_funcs mtk_disp_rdma_funcs = {
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 8fea98578bc8..76416c1cbb28 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -13,6 +13,7 @@
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <drm/drmP.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
#include "mtk_drm_drv.h"
#include "mtk_drm_plane.h"
#include "mtk_drm_ddp_comp.h"
@@ -76,36 +77,76 @@
#define DITHER_ADD_LSHIFT_G(x) (((x) & 0x7) << 4)
#define DITHER_ADD_RSHIFT_G(x) (((x) & 0x7) << 0)
+void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value,
+ struct mtk_ddp_comp *comp, unsigned int offset)
+{
+ if (IS_ENABLED(CONFIG_MTK_CMDQ) && cmdq_pkt)
+ cmdq_pkt_write(cmdq_pkt, comp->subsys,
+ comp->regs_pa + offset, value);
+ else
+ writel(value, comp->regs + offset);
+}
+
+void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value,
+ struct mtk_ddp_comp *comp,
+ unsigned int offset)
+{
+ if (IS_ENABLED(CONFIG_MTK_CMDQ) && cmdq_pkt)
+ cmdq_pkt_write(cmdq_pkt, comp->subsys,
+ comp->regs_pa + offset, value);
+ else
+ writel_relaxed(value, comp->regs + offset);
+}
+
+void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt,
+ unsigned int value,
+ struct mtk_ddp_comp *comp,
+ unsigned int offset,
+ unsigned int mask)
+{
+ if (IS_ENABLED(CONFIG_MTK_CMDQ) && cmdq_pkt) {
+ cmdq_pkt_write_mask(cmdq_pkt, comp->subsys,
+ comp->regs_pa + offset, value, mask);
+ } else {
+ u32 tmp = readl(comp->regs + offset);
+
+ tmp = (tmp & ~mask) | (value & mask);
+ writel(tmp, comp->regs + offset);
+ }
+}
+
void mtk_dither_set(struct mtk_ddp_comp *comp, unsigned int bpc,
- unsigned int CFG)
+ unsigned int CFG, struct cmdq_pkt *cmdq_pkt)
{
/* If bpc equal to 0, the dithering function didn't be enabled */
if (bpc == 0)
return;
if (bpc >= MTK_MIN_BPC) {
- writel(0, comp->regs + DISP_DITHER_5);
- writel(0, comp->regs + DISP_DITHER_7);
- writel(DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
- DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
- DITHER_NEW_BIT_MODE,
- comp->regs + DISP_DITHER_15);
- writel(DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |
- DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |
- DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |
- DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
- comp->regs + DISP_DITHER_16);
- writel(DISP_DITHERING, comp->regs + CFG);
+ mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_5);
+ mtk_ddp_write(cmdq_pkt, 0, comp, DISP_DITHER_7);
+ mtk_ddp_write(cmdq_pkt,
+ DITHER_LSB_ERR_SHIFT_R(MTK_MAX_BPC - bpc) |
+ DITHER_ADD_LSHIFT_R(MTK_MAX_BPC - bpc) |
+ DITHER_NEW_BIT_MODE,
+ comp, DISP_DITHER_15);
+ mtk_ddp_write(cmdq_pkt,
+ DITHER_LSB_ERR_SHIFT_B(MTK_MAX_BPC - bpc) |
+ DITHER_ADD_LSHIFT_B(MTK_MAX_BPC - bpc) |
+ DITHER_LSB_ERR_SHIFT_G(MTK_MAX_BPC - bpc) |
+ DITHER_ADD_LSHIFT_G(MTK_MAX_BPC - bpc),
+ comp, DISP_DITHER_16);
+ mtk_ddp_write(cmdq_pkt, DISP_DITHERING, comp, CFG);
}
}
static void mtk_od_config(struct mtk_ddp_comp *comp, unsigned int w,
unsigned int h, unsigned int vrefresh,
- unsigned int bpc)
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
{
- writel(w << 16 | h, comp->regs + DISP_OD_SIZE);
- writel(OD_RELAYMODE, comp->regs + DISP_OD_CFG);
- mtk_dither_set(comp, bpc, DISP_OD_CFG);
+ mtk_ddp_write(cmdq_pkt, w << 16 | h, comp, DISP_OD_SIZE);
+ mtk_ddp_write(cmdq_pkt, OD_RELAYMODE, comp, DISP_OD_CFG);
+ mtk_dither_set(comp, bpc, DISP_OD_CFG, cmdq_pkt);
}
static void mtk_od_start(struct mtk_ddp_comp *comp)
@@ -120,9 +161,9 @@ static void mtk_ufoe_start(struct mtk_ddp_comp *comp)
static void mtk_aal_config(struct mtk_ddp_comp *comp, unsigned int w,
unsigned int h, unsigned int vrefresh,
- unsigned int bpc)
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
{
- writel(h << 16 | w, comp->regs + DISP_AAL_SIZE);
+ mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_AAL_SIZE);
}
static void mtk_aal_start(struct mtk_ddp_comp *comp)
@@ -137,10 +178,10 @@ static void mtk_aal_stop(struct mtk_ddp_comp *comp)
static void mtk_ccorr_config(struct mtk_ddp_comp *comp, unsigned int w,
unsigned int h, unsigned int vrefresh,
- unsigned int bpc)
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
{
- writel(h << 16 | w, comp->regs + DISP_CCORR_SIZE);
- writel(CCORR_RELAY_MODE, comp->regs + DISP_CCORR_CFG);
+ mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_CCORR_SIZE);
+ mtk_ddp_write(cmdq_pkt, CCORR_RELAY_MODE, comp, DISP_CCORR_CFG);
}
static void mtk_ccorr_start(struct mtk_ddp_comp *comp)
@@ -155,10 +196,10 @@ static void mtk_ccorr_stop(struct mtk_ddp_comp *comp)
static void mtk_dither_config(struct mtk_ddp_comp *comp, unsigned int w,
unsigned int h, unsigned int vrefresh,
- unsigned int bpc)
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
{
- writel(h << 16 | w, comp->regs + DISP_DITHER_SIZE);
- writel(DITHER_RELAY_MODE, comp->regs + DISP_DITHER_CFG);
+ mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_DITHER_SIZE);
+ mtk_ddp_write(cmdq_pkt, DITHER_RELAY_MODE, comp, DISP_DITHER_CFG);
}
static void mtk_dither_start(struct mtk_ddp_comp *comp)
@@ -173,10 +214,10 @@ static void mtk_dither_stop(struct mtk_ddp_comp *comp)
static void mtk_gamma_config(struct mtk_ddp_comp *comp, unsigned int w,
unsigned int h, unsigned int vrefresh,
- unsigned int bpc)
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
{
- writel(h << 16 | w, comp->regs + DISP_GAMMA_SIZE);
- mtk_dither_set(comp, bpc, DISP_GAMMA_CFG);
+ mtk_ddp_write(cmdq_pkt, h << 16 | w, comp, DISP_GAMMA_SIZE);
+ mtk_dither_set(comp, bpc, DISP_GAMMA_CFG, cmdq_pkt);
}
static void mtk_gamma_start(struct mtk_ddp_comp *comp)
@@ -190,24 +231,25 @@ static void mtk_gamma_stop(struct mtk_ddp_comp *comp)
}
static void mtk_gamma_set(struct mtk_ddp_comp *comp,
- struct drm_crtc_state *state)
+ struct drm_crtc_state *state,
+ struct cmdq_pkt *cmdq_pkt)
{
- unsigned int i, reg;
+ unsigned int i;
struct drm_color_lut *lut;
void __iomem *lut_base;
u32 word;
if (state->gamma_lut) {
- reg = readl(comp->regs + DISP_GAMMA_CFG);
- reg = reg | GAMMA_LUT_EN;
- writel(reg, comp->regs + DISP_GAMMA_CFG);
+ mtk_ddp_write_mask(cmdq_pkt, GAMMA_LUT_EN, comp,
+ DISP_GAMMA_CFG, GAMMA_LUT_EN);
lut_base = comp->regs + DISP_GAMMA_LUT;
lut = (struct drm_color_lut *)state->gamma_lut->data;
for (i = 0; i < MTK_LUT_SIZE; i++) {
word = (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) +
(((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) +
((lut[i].blue >> 6) & LUT_10BIT_MASK);
- writel(word, (lut_base + i * 4));
+ mtk_ddp_write(cmdq_pkt, word, comp,
+ (unsigned int)(lut_base + i * 4));
}
}
}
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 268d416081da..6bbc35f92815 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -69,21 +69,26 @@ enum mtk_ddp_comp_id {
};
struct mtk_ddp_comp;
-
+struct cmdq_pkt;
struct mtk_ddp_comp_funcs {
void (*config)(struct mtk_ddp_comp *comp, unsigned int w,
- unsigned int h, unsigned int vrefresh, unsigned int bpc);
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
void (*start)(struct mtk_ddp_comp *comp);
void (*stop)(struct mtk_ddp_comp *comp);
void (*enable_vblank)(struct mtk_ddp_comp *comp, struct drm_crtc *crtc);
void (*disable_vblank)(struct mtk_ddp_comp *comp);
unsigned int (*layer_nr)(struct mtk_ddp_comp *comp);
- void (*layer_on)(struct mtk_ddp_comp *comp, unsigned int idx);
- void (*layer_off)(struct mtk_ddp_comp *comp, unsigned int idx);
+ void (*layer_on)(struct mtk_ddp_comp *comp, unsigned int idx,
+ struct cmdq_pkt *cmdq_pkt);
+ void (*layer_off)(struct mtk_ddp_comp *comp, unsigned int idx,
+ struct cmdq_pkt *cmdq_pkt);
void (*layer_config)(struct mtk_ddp_comp *comp, unsigned int idx,
- struct mtk_plane_state *state);
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt);
void (*gamma_set)(struct mtk_ddp_comp *comp,
- struct drm_crtc_state *state);
+ struct drm_crtc_state *state,
+ struct cmdq_pkt *cmdq_pkt);
void (*bgclr_in_on)(struct mtk_ddp_comp *comp);
void (*bgclr_in_off)(struct mtk_ddp_comp *comp);
};
@@ -98,10 +103,11 @@ struct mtk_ddp_comp {
static inline void mtk_ddp_comp_config(struct mtk_ddp_comp *comp,
unsigned int w, unsigned int h,
- unsigned int vrefresh, unsigned int bpc)
+ unsigned int vrefresh, unsigned int bpc,
+ struct cmdq_pkt *cmdq_pkt)
{
if (comp->funcs && comp->funcs->config)
- comp->funcs->config(comp, w, h, vrefresh, bpc);
+ comp->funcs->config(comp, w, h, vrefresh, bpc, cmdq_pkt);
}
static inline void mtk_ddp_comp_start(struct mtk_ddp_comp *comp)
@@ -138,32 +144,36 @@ static inline unsigned int mtk_ddp_comp_layer_nr(struct mtk_ddp_comp *comp)
}
static inline void mtk_ddp_comp_layer_on(struct mtk_ddp_comp *comp,
- unsigned int idx)
+ unsigned int idx,
+ struct cmdq_pkt *cmdq_pkt)
{
if (comp->funcs && comp->funcs->layer_on)
- comp->funcs->layer_on(comp, idx);
+ comp->funcs->layer_on(comp, idx, cmdq_pkt);
}
static inline void mtk_ddp_comp_layer_off(struct mtk_ddp_comp *comp,
- unsigned int idx)
+ unsigned int idx,
+ struct cmdq_pkt *cmdq_pkt)
{
if (comp->funcs && comp->funcs->layer_off)
- comp->funcs->layer_off(comp, idx);
+ comp->funcs->layer_off(comp, idx, cmdq_pkt);
}
static inline void mtk_ddp_comp_layer_config(struct mtk_ddp_comp *comp,
unsigned int idx,
- struct mtk_plane_state *state)
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt)
{
if (comp->funcs && comp->funcs->layer_config)
- comp->funcs->layer_config(comp, idx, state);
+ comp->funcs->layer_config(comp, idx, state, cmdq_pkt);
}
static inline void mtk_ddp_gamma_set(struct mtk_ddp_comp *comp,
- struct drm_crtc_state *state)
+ struct drm_crtc_state *state,
+ struct cmdq_pkt *cmdq_pkt)
{
if (comp->funcs && comp->funcs->gamma_set)
- comp->funcs->gamma_set(comp, state);
+ comp->funcs->gamma_set(comp, state, cmdq_pkt);
}
static inline void mtk_ddp_comp_bgclr_in_on(struct mtk_ddp_comp *comp)
@@ -186,6 +196,13 @@ int mtk_ddp_comp_init(struct device *dev, struct device_node *comp_node,
int mtk_ddp_comp_register(struct drm_device *drm, struct mtk_ddp_comp *comp);
void mtk_ddp_comp_unregister(struct drm_device *drm, struct mtk_ddp_comp *comp);
void mtk_dither_set(struct mtk_ddp_comp *comp, unsigned int bpc,
- unsigned int CFG);
-
+ unsigned int CFG, struct cmdq_pkt *cmdq_pkt);
+enum mtk_ddp_comp_type mtk_ddp_comp_get_type(enum mtk_ddp_comp_id comp_id);
+void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value,
+ struct mtk_ddp_comp *comp, unsigned int offset);
+void mtk_ddp_write_relaxed(struct cmdq_pkt *cmdq_pkt, unsigned int value,
+ struct mtk_ddp_comp *comp, unsigned int offset);
+void mtk_ddp_write_mask(struct cmdq_pkt *cmdq_pkt, unsigned int value,
+ struct mtk_ddp_comp *comp, unsigned int offset,
+ unsigned int mask);
#endif /* MTK_DRM_DDP_COMP_H */
--
2.18.0
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* [PATCH v3 6/7] arm64: dts: mt8183: enable USB remote wakeup
From: Chunfeng Yun @ 2019-08-30 7:40 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring
Cc: Mark Rutland, devicetree, Mathias Nyman, linux-usb, linux-kernel,
Chunfeng Yun, linux-mediatek, Matthias Brugger, linux-arm-kernel
In-Reply-To: <1567150854-30033-1-git-send-email-chunfeng.yun@mediatek.com>
Enable USB remote wakeup for MT8183
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v3: remove '#reset-cells'
v2: no changes
---
arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 1 +
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 7 +++++++
2 files changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
index 142ff52f0f42..077256f3397b 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
@@ -150,6 +150,7 @@
&ssusb {
vusb33-supply = <&mt6358_vusb_reg>;
dr_mode = "host";
+ wakeup-source;
status = "okay";
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 28da334237c6..dc3e859849c7 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -215,6 +215,12 @@
#clock-cells = <1>;
};
+ pericfg: syscon@10003000 {
+ compatible = "mediatek,mt8183-pericfg", "syscon";
+ reg = <0 0x10003000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
pio: pinctrl@10005000 {
compatible = "mediatek,mt8183-pinctrl";
reg = <0 0x10005000 0 0x1000>,
@@ -384,6 +390,7 @@
clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
<&infracfg CLK_INFRA_USB>;
clock-names = "sys_ck", "ref_ck";
+ mediatek,syscon-wakeup = <&pericfg 0x400 0>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
--
2.23.0
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* [PATCH 2/2] drm/mediatek: Apply CMDQ control flow
From: Bibby Hsieh @ 2019-08-30 7:41 UTC (permalink / raw)
To: David Airlie, Matthias Brugger, Daniel Vetter, dri-devel,
linux-mediatek
Cc: drinkcat, Bibby Hsieh, Yongqiang Niu, linux-kernel, tfiga, CK Hu,
Thierry Reding, Philipp Zabel, YT Shen, linux-arm-kernel
In-Reply-To: <20190830074103.16671-1-bibby.hsieh@mediatek.com>
Unlike other SoCs, MT8183 does not have "shadow"
registers for performaing an atomic video mode
set or page flip at vblank/vsync.
The CMDQ (Commend Queue) in MT8183 is used to help
update all relevant display controller registers
with critical time limation.
Signed-off-by: YT Shen <yt.shen@mediatek.com>
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 190 +++++++++++++++++---
drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 2 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 34 ++++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 2 +
drivers/gpu/drm/mediatek/mtk_drm_plane.c | 4 +
5 files changed, 206 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index 092e502ed27b..329ca5a14c39 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -10,7 +10,9 @@
#include <drm/drm_plane_helper.h>
#include <drm/drm_probe_helper.h>
#include <linux/clk.h>
+#include <linux/of_address.h>
#include <linux/pm_runtime.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
#include "mtk_drm_drv.h"
#include "mtk_drm_crtc.h"
@@ -41,6 +43,10 @@ struct mtk_drm_crtc {
unsigned int layer_nr;
bool pending_planes;
bool cursor_update;
+
+ struct cmdq_client *cmdq_client;
+ u32 cmdq_event;
+
void __iomem *config_regs;
const struct mtk_mmsys_reg_data *mmsys_reg_data;
struct mtk_disp_mutex *mutex;
@@ -57,6 +63,12 @@ struct mtk_crtc_state {
unsigned int pending_width;
unsigned int pending_height;
unsigned int pending_vrefresh;
+ struct cmdq_pkt *cmdq_handle;
+};
+
+struct mtk_cmdq_cb_data {
+ struct drm_crtc_state *state;
+ struct cmdq_pkt *cmdq_handle;
};
static inline struct mtk_drm_crtc *to_mtk_crtc(struct drm_crtc *c)
@@ -208,6 +220,46 @@ static void mtk_crtc_ddp_clk_disable(struct mtk_drm_crtc *mtk_crtc)
clk_disable_unprepare(mtk_crtc->ddp_comp[i]->clk);
}
+static void ddp_cmdq_cursor_cb(struct cmdq_cb_data data)
+{
+
+#if IS_ENABLED(CONFIG_MTK_CMDQ)
+ struct mtk_cmdq_cb_data *cb_data = data.data;
+
+ DRM_DEBUG_DRIVER("%s\n", __func__);
+
+ cmdq_pkt_destroy(cb_data->cmdq_handle);
+ kfree(cb_data);
+#endif
+
+}
+
+static void ddp_cmdq_cb(struct cmdq_cb_data data)
+{
+
+#if IS_ENABLED(CONFIG_MTK_CMDQ)
+ struct mtk_cmdq_cb_data *cb_data = data.data;
+ struct drm_crtc_state *crtc_state = cb_data->state;
+ struct drm_atomic_state *atomic_state = crtc_state->state;
+ struct drm_crtc *crtc = crtc_state->crtc;
+ struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
+
+ DRM_DEBUG_DRIVER("%s\n", __func__);
+
+ if (mtk_crtc->pending_needs_vblank) {
+ /* cmdq_vblank_event must be read after cmdq_needs_event */
+ smp_rmb();
+
+ mtk_drm_crtc_finish_page_flip(mtk_crtc);
+ mtk_crtc->pending_needs_vblank = false;
+ }
+ mtk_atomic_state_put_queue(atomic_state);
+ cmdq_pkt_destroy(cb_data->cmdq_handle);
+ kfree(cb_data);
+#endif
+
+}
+
static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
{
struct drm_crtc *crtc = &mtk_crtc->base;
@@ -283,7 +335,8 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
if (prev == DDP_COMPONENT_OVL0)
mtk_ddp_comp_bgclr_in_on(comp);
- mtk_ddp_comp_config(comp, width, height, vrefresh, bpc);
+ mtk_ddp_comp_config(comp, width, height,
+ vrefresh, bpc, NULL);
mtk_ddp_comp_start(comp);
}
@@ -303,7 +356,7 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
} else
local_layer = i;
mtk_ddp_comp_layer_config(comp, local_layer,
- plane_state);
+ plane_state, NULL);
}
return 0;
@@ -361,7 +414,7 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
if (state->pending_config) {
mtk_ddp_comp_config(comp, state->pending_width,
state->pending_height,
- state->pending_vrefresh, 0);
+ state->pending_vrefresh, 0, NULL);
state->pending_config = false;
}
@@ -381,7 +434,7 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
local_layer = i;
mtk_ddp_comp_layer_config(comp, local_layer,
- plane_state);
+ plane_state, NULL);
plane_state->pending.config = false;
}
}
@@ -405,26 +458,69 @@ void mtk_drm_crtc_cursor_update(struct drm_crtc *crtc, struct drm_plane *plane,
return;
mutex_lock(&priv->hw_lock);
- plane_helper_funcs->atomic_update(plane, plane_state);
- for (i = 0; i < mtk_crtc->layer_nr; i++) {
- struct drm_plane *plane = &mtk_crtc->planes[i];
- struct mtk_plane_state *plane_state;
+ if (IS_ENABLED(CONFIG_MTK_CMDQ) && mtk_crtc->cmdq_client) {
+ struct mtk_crtc_state *mtk_crtc_state =
+ to_mtk_crtc_state(crtc->state);
+ struct mtk_cmdq_cb_data *cb_data;
+
+ mtk_crtc_state->cmdq_handle =
+ cmdq_pkt_create(mtk_crtc->cmdq_client,
+ PAGE_SIZE);
+ cmdq_pkt_clear_event(mtk_crtc_state->cmdq_handle,
+ mtk_crtc->cmdq_event);
+ cmdq_pkt_wfe(mtk_crtc_state->cmdq_handle, mtk_crtc->cmdq_event);
+ plane_helper_funcs->atomic_update(plane, plane_state);
+ cb_data = kmalloc(sizeof(*cb_data), GFP_KERNEL);
+ cb_data->cmdq_handle = mtk_crtc_state->cmdq_handle;
+ cmdq_pkt_flush_async(mtk_crtc_state->cmdq_handle,
+ ddp_cmdq_cursor_cb, cb_data);
+ } else {
+ plane_helper_funcs->atomic_update(plane, plane_state);
- plane_state = to_mtk_plane_state(plane->state);
- if (plane_state->pending.dirty) {
- plane_state->pending.config = true;
- plane_state->pending.dirty = false;
+ for (i = 0; i < mtk_crtc->layer_nr; i++) {
+ struct drm_plane *plane = &mtk_crtc->planes[i];
+ struct mtk_plane_state *plane_state;
+
+ plane_state = to_mtk_plane_state(plane->state);
+ if (plane_state->pending.dirty) {
+ plane_state->pending.config = true;
+ plane_state->pending.dirty = false;
+ }
+ }
+ mtk_crtc->pending_planes = true;
+ mtk_crtc->cursor_update = true;
+ if (priv->data->shadow_register) {
+ mtk_disp_mutex_acquire(mtk_crtc->mutex);
+ mtk_crtc_ddp_config(crtc);
+ mtk_disp_mutex_release(mtk_crtc->mutex);
}
}
- mtk_crtc->pending_planes = true;
- mtk_crtc->cursor_update = true;
+ mutex_unlock(&priv->hw_lock);
+}
- if (priv->data->shadow_register) {
- mtk_disp_mutex_acquire(mtk_crtc->mutex);
- mtk_crtc_ddp_config(crtc);
- mtk_disp_mutex_release(mtk_crtc->mutex);
+void mtk_drm_crtc_plane_update(struct drm_crtc *crtc, struct drm_plane *plane,
+ struct mtk_plane_state *state)
+{
+ struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
+ struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
+ struct drm_crtc_state *crtc_state = crtc->state;
+ struct mtk_crtc_state *mtk_crtc_state = to_mtk_crtc_state(crtc_state);
+ struct cmdq_pkt *cmdq_handle = mtk_crtc_state->cmdq_handle;
+ unsigned int comp_layer_nr = mtk_ddp_comp_layer_nr(comp);
+ unsigned int local_layer;
+ unsigned int plane_index = plane - mtk_crtc->planes;
+
+ DRM_DEBUG_DRIVER("%s\n", __func__);
+ if (mtk_crtc->cmdq_client) {
+ if (plane_index >= comp_layer_nr) {
+ comp = mtk_crtc->ddp_comp[1];
+ local_layer = plane_index - comp_layer_nr;
+ } else {
+ local_layer = plane_index;
+ }
+ mtk_ddp_comp_layer_config(comp, local_layer, state,
+ cmdq_handle);
}
- mutex_unlock(&priv->hw_lock);
}
static void mtk_drm_crtc_atomic_enable(struct drm_crtc *crtc,
@@ -487,6 +583,15 @@ static void mtk_drm_crtc_atomic_begin(struct drm_crtc *crtc,
WARN_ON(drm_crtc_vblank_get(crtc) != 0);
mtk_crtc->event = state->base.event;
state->base.event = NULL;
+ /* Make sure the above parameter is set before update */
+ smp_wmb();
+ mtk_crtc->pending_needs_vblank = true;
+ }
+ if (IS_ENABLED(CONFIG_MTK_CMDQ) && mtk_crtc->cmdq_client) {
+ state->cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client,
+ PAGE_SIZE);
+ cmdq_pkt_clear_event(state->cmdq_handle, mtk_crtc->cmdq_event);
+ cmdq_pkt_wfe(state->cmdq_handle, mtk_crtc->cmdq_event);
}
}
@@ -494,13 +599,29 @@ static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
struct drm_crtc_state *old_crtc_state)
{
struct drm_atomic_state *old_atomic_state = old_crtc_state->state;
+ struct drm_crtc_state *crtc_state = crtc->state;
+ struct mtk_crtc_state *state = to_mtk_crtc_state(crtc_state);
+ struct cmdq_pkt *cmdq_handle = state->cmdq_handle;
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
struct mtk_drm_private *priv = crtc->dev->dev_private;
+ struct mtk_cmdq_cb_data *cb_data;
unsigned int pending_planes = 0;
int i;
- if (mtk_crtc->event)
- mtk_crtc->pending_needs_vblank = true;
+ DRM_DEBUG_DRIVER("[CRTC:%u] [STATE:%p(%p)->%p(%p)]\n", crtc->base.id,
+ old_crtc_state, old_crtc_state->state,
+ crtc_state, crtc_state->state);
+
+ if (IS_ENABLED(CONFIG_MTK_CMDQ) && mtk_crtc->cmdq_client) {
+ drm_atomic_state_get(old_atomic_state);
+ cb_data = kmalloc(sizeof(*cb_data), GFP_KERNEL);
+ cb_data->state = old_crtc_state;
+ cb_data->cmdq_handle = cmdq_handle;
+ cmdq_pkt_flush_async(cmdq_handle, ddp_cmdq_cb, cb_data);
+
+ return;
+ }
+
for (i = 0; i < mtk_crtc->layer_nr; i++) {
struct drm_plane *plane = &mtk_crtc->planes[i];
struct mtk_plane_state *plane_state;
@@ -521,7 +642,8 @@ static void mtk_drm_crtc_atomic_flush(struct drm_crtc *crtc,
if (crtc->state->color_mgmt_changed)
for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
- mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
+ mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i],
+ crtc->state, NULL);
if (priv->data->shadow_register) {
mtk_disp_mutex_acquire(mtk_crtc->mutex);
@@ -578,10 +700,13 @@ void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *comp)
struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
struct mtk_drm_private *priv = crtc->dev->dev_private;
- if (!priv->data->shadow_register)
- mtk_crtc_ddp_config(crtc);
-
- mtk_drm_finish_page_flip(mtk_crtc);
+ if (mtk_crtc->cmdq_client) {
+ drm_crtc_handle_vblank(crtc);
+ } else {
+ if (!priv->data->shadow_register)
+ mtk_crtc_ddp_config(crtc);
+ mtk_drm_finish_page_flip(mtk_crtc);
+ }
}
int mtk_drm_crtc_create(struct drm_device *drm_dev,
@@ -678,5 +803,18 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, false, MTK_LUT_SIZE);
priv->num_pipes++;
+ if (IS_ENABLED(CONFIG_MTK_CMDQ)) {
+ mtk_crtc->cmdq_client = cmdq_mbox_create(dev,
+ drm_crtc_index(&mtk_crtc->base), 2000);
+ of_property_read_u32_index(dev->of_node, "mediatek,gce-events",
+ drm_crtc_index(&mtk_crtc->base),
+ &mtk_crtc->cmdq_event);
+ if (IS_ERR(mtk_crtc->cmdq_client)) {
+ dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n",
+ drm_crtc_index(&mtk_crtc->base));
+ mtk_crtc->cmdq_client = NULL;
+ }
+ }
+
return 0;
}
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
index 46e903be68ec..6b2423c88416 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
@@ -19,6 +19,8 @@ void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *comp);
int mtk_drm_crtc_create(struct drm_device *drm_dev,
const enum mtk_ddp_comp_id *path,
unsigned int path_len);
+void mtk_drm_crtc_plane_update(struct drm_crtc *crtc, struct drm_plane *plane,
+ struct mtk_plane_state *state);
void mtk_drm_crtc_cursor_update(struct drm_crtc *crtc, struct drm_plane *plane,
struct drm_plane_state *plane_state);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 76416c1cbb28..056ebc6a8199 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -395,6 +395,40 @@ int mtk_ddp_comp_init(struct device *dev, struct device_node *node,
if (IS_ERR(comp->clk))
return PTR_ERR(comp->clk);
+ if (IS_ENABLED(CONFIG_MTK_CMDQ)) {
+ struct platform_device *comp_pdev;
+ struct resource res;
+ struct cmdq_client_reg *cmdq_reg;
+ int ret = 0;
+
+ if (of_address_to_resource(node, 0, &res) != 0) {
+ dev_err(dev, "Missing reg in %s node\n",
+ node->full_name);
+ return -EINVAL;
+ }
+ comp->regs_pa = res.start;
+
+ comp_pdev = of_find_device_by_node(node);
+ if (!comp_pdev) {
+ dev_warn(dev, "Waiting for component device %s\n",
+ node->full_name);
+ return -EPROBE_DEFER;
+ }
+
+ cmdq_reg = kzalloc(sizeof(*cmdq_reg), GFP_KERNEL);
+ if (!cmdq_reg)
+ return -EINVAL;
+
+ ret = cmdq_dev_get_client_reg(&comp_pdev->dev, cmdq_reg, 0);
+ if (ret != 0)
+ dev_dbg(&comp_pdev->dev,
+ "get mediatek,gce-client-reg fail!\n");
+ else
+ comp->subsys = cmdq_reg->subsys;
+
+ kfree(cmdq_reg);
+ }
+
return 0;
}
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 6bbc35f92815..0faec2dad5a3 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -99,6 +99,8 @@ struct mtk_ddp_comp {
int irq;
enum mtk_ddp_comp_id id;
const struct mtk_ddp_comp_funcs *funcs;
+ resource_size_t regs_pa;
+ u8 subsys;
};
static inline void mtk_ddp_comp_config(struct mtk_ddp_comp *comp,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_plane.c b/drivers/gpu/drm/mediatek/mtk_drm_plane.c
index 59dbdaf07425..ef46c0f43039 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_plane.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_plane.c
@@ -202,6 +202,8 @@ static void mtk_plane_atomic_update(struct drm_plane *plane,
state->pending.height = drm_rect_height(&plane->state->dst);
wmb(); /* Make sure the above parameters are set before update */
state->pending.dirty = true;
+
+ mtk_drm_crtc_plane_update(crtc, plane, state);
}
static void mtk_plane_atomic_disable(struct drm_plane *plane,
@@ -212,6 +214,8 @@ static void mtk_plane_atomic_disable(struct drm_plane *plane,
state->pending.enable = false;
wmb(); /* Make sure the above parameter is set before update */
state->pending.dirty = true;
+ /* Fetch CRTC from old plane state when disabling. */
+ mtk_drm_crtc_plane_update(old_state->crtc, plane, state);
}
static const struct drm_plane_helper_funcs mtk_plane_helper_funcs = {
--
2.18.0
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^ permalink raw reply related
* [PATCH v3 5/7] arm64: dts: mt8183: add usb and phy nodes
From: Chunfeng Yun @ 2019-08-30 7:40 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring
Cc: Mark Rutland, devicetree, Mathias Nyman, linux-usb, linux-kernel,
Chunfeng Yun, linux-mediatek, Matthias Brugger, linux-arm-kernel
In-Reply-To: <1567150854-30033-1-git-send-email-chunfeng.yun@mediatek.com>
Add USB related nodes for MT8183, set it as host mode by default.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2~v3: no changes
---
arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 22 +++++++++
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 55 +++++++++++++++++++++
2 files changed, 77 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
index d8e555cbb5d3..142ff52f0f42 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts
@@ -6,7 +6,9 @@
*/
/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
#include "mt8183.dtsi"
+#include "mt6358.dtsi"
/ {
model = "MediaTek MT8183 evaluation board";
@@ -24,6 +26,16 @@
chosen {
stdout-path = "serial0:921600n8";
};
+
+ usb_vbus: regulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "p0_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&pio 42 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
};
&auxadc {
@@ -135,6 +147,16 @@
};
+&ssusb {
+ vusb33-supply = <&mt6358_vusb_reg>;
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usb_host {
+ status = "okay";
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index c2749c4631bc..28da334237c6 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/clock/mt8183-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/phy/phy.h>
#include "mt8183-pinfunc.h"
/ {
@@ -372,6 +373,35 @@
status = "disabled";
};
+ ssusb: usb@11201000 {
+ compatible = "mediatek,mt8183-mtu3", "mediatek,mtu3";
+ reg = <0 0x11201000 0 0x2e00>,
+ <0 0x11203e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
+ phys = <&u2port0 PHY_TYPE_USB2>,
+ <&u3port0 PHY_TYPE_USB3>;
+ clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
+ <&infracfg CLK_INFRA_USB>;
+ clock-names = "sys_ck", "ref_ck";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ usb_host: xhci@11200000 {
+ compatible = "mediatek,mt8183-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x11200000 0 0x1000>;
+ reg-names = "mac";
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>,
+ <&infracfg CLK_INFRA_USB>;
+ clock-names = "sys_ck", "ref_ck";
+ status = "disabled";
+ };
+ };
+
audiosys: syscon@11220000 {
compatible = "mediatek,mt8183-audiosys", "syscon";
reg = <0 0x11220000 0 0x1000>;
@@ -384,6 +414,31 @@
reg = <0 0x11f10000 0 0x1000>;
};
+ u3phy: usb-phy@11f40000 {
+ compatible = "mediatek,mt8183-tphy",
+ "mediatek,generic-tphy-v2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x11f40000 0x1000>;
+ status = "okay";
+
+ u2port0: usb-phy@0 {
+ reg = <0x0 0x700>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+
+ u3port0: usb-phy@0700 {
+ reg = <0x0700 0x900>;
+ clocks = <&clk26m>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ status = "okay";
+ };
+ };
+
mfgcfg: syscon@13000000 {
compatible = "mediatek,mt8183-mfgcfg", "syscon";
reg = <0 0x13000000 0 0x1000>;
--
2.23.0
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^ permalink raw reply related
* [PATCH v3 4/7] usb: mtk-xhci: support ip-sleep wakeup for MT8183
From: Chunfeng Yun @ 2019-08-30 7:40 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring
Cc: Mark Rutland, devicetree, Mathias Nyman, linux-usb, linux-kernel,
Chunfeng Yun, linux-mediatek, Matthias Brugger, linux-arm-kernel
In-Reply-To: <1567150854-30033-1-git-send-email-chunfeng.yun@mediatek.com>
Support USB wakeup by ip-sleep mode for MT8183, it's similar to
MT8173
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v3: change micros define
v2: no changes
---
drivers/usb/host/xhci-mtk.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c
index 026fe18972d3..9b30a868a7ab 100644
--- a/drivers/usb/host/xhci-mtk.c
+++ b/drivers/usb/host/xhci-mtk.c
@@ -57,6 +57,12 @@
#define CTRL_U2_FORCE_PLL_STB BIT(28)
/* usb remote wakeup registers in syscon */
+/* mt8183 etc */
+#define PERI_WK_CTRL0 0x20
+#define WC0_IS_C(x) (((x) & 0xf) << 28) /* cycle debounce */
+#define WC0_IS_P BIT(12) /* polarity */
+#define WC0_IS_EN BIT(6)
+
/* mt8173 etc */
#define PERI_WK_CTRL1 0x4
#define WC1_IS_C(x) (((x) & 0xf) << 26) /* cycle debounce */
@@ -69,7 +75,8 @@
#define SSC_SPM_INT_EN BIT(1)
enum ssusb_uwk_vers {
- SSUSB_UWK_V1 = 1,
+ SSUSB_UWK_V0 = 0,
+ SSUSB_UWK_V1,
SSUSB_UWK_V2,
};
@@ -282,6 +289,11 @@ static void usb_wakeup_ip_sleep_set(struct xhci_hcd_mtk *mtk, bool enable)
u32 reg, msk, val;
switch (mtk->uwk_vers) {
+ case SSUSB_UWK_V0:
+ reg = mtk->uwk_reg_base + PERI_WK_CTRL0;
+ msk = WC0_IS_EN | WC0_IS_C(0xf) | WC0_IS_P;
+ val = enable ? (WC0_IS_EN | WC0_IS_C(0x8)) : 0;
+ break;
case SSUSB_UWK_V1:
reg = mtk->uwk_reg_base + PERI_WK_CTRL1;
msk = WC1_IS_EN | WC1_IS_C(0xf) | WC1_IS_P;
--
2.23.0
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^ permalink raw reply related
* [PATCH v3 1/7] dt-bindings: usb: mtu3: support USB wakeup for MT8183
From: Chunfeng Yun @ 2019-08-30 7:40 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring
Cc: Mark Rutland, devicetree, Mathias Nyman, linux-usb, linux-kernel,
Chunfeng Yun, linux-mediatek, Matthias Brugger, linux-arm-kernel
In-Reply-To: <1567150854-30033-1-git-send-email-chunfeng.yun@mediatek.com>
Support USB wakeup by ip-sleep mode for MT8183
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2~v3: no changes
---
Documentation/devicetree/bindings/usb/mediatek,mtu3.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt b/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt
index 3382b5cb471d..ed954bedcd2f 100644
--- a/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt
+++ b/Documentation/devicetree/bindings/usb/mediatek,mtu3.txt
@@ -48,6 +48,7 @@ Optional properties:
"wakeup-source", and has two arguments:
- the first one : register base address of the glue layer in syscon;
- the second one : hardware version of the glue layer
+ - 0 : used by mt8183 etc
- 1 : used by mt8173 etc
- 2 : used by mt2712 etc
- mediatek,u3p-dis-msk : mask to disable u3ports, bit0 for u3port0,
--
2.23.0
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^ permalink raw reply related
* [PATCH 0/2] Support CMDQ interface and control flow
From: Bibby Hsieh @ 2019-08-30 7:41 UTC (permalink / raw)
To: David Airlie, Matthias Brugger, Daniel Vetter, dri-devel,
linux-mediatek
Cc: drinkcat, Bibby Hsieh, linux-kernel, tfiga, CK Hu, Thierry Reding,
Philipp Zabel, YT Shen, linux-arm-kernel
The CMDQ (Command Queue) in MT8183 is used to help
update all relevant display controller registers
with critical time limation.
These patched add CMDQ interface in ddp_comp interface
and add CMDQ control flow.
This patch depends on ptach:
drm/mediatek: fixup cursor moving unsmooth issue
(https://patchwork.kernel.org/cover/11123119/)
add drm support for MT8183
(https://patchwork.kernel.org/cover/11121519/)
support gce on mt8183 platform
(https://patchwork.kernel.org/cover/11120153/)
Bibby Hsieh (2):
drm/mediatek: Support CMDQ interface in ddp component
drm/mediatek: Apply CMDQ control flow
drivers/gpu/drm/mediatek/mtk_disp_color.c | 7 +-
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 78 ++++----
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 66 +++----
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 190 +++++++++++++++++---
drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 2 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 144 +++++++++++----
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 55 ++++--
drivers/gpu/drm/mediatek/mtk_drm_plane.c | 4 +
8 files changed, 393 insertions(+), 153 deletions(-)
--
2.18.0
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^ permalink raw reply
* [PATCH v3 3/7] usb: mtu3: support ip-sleep wakeup for MT8183
From: Chunfeng Yun @ 2019-08-30 7:40 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring
Cc: Mark Rutland, devicetree, Mathias Nyman, linux-usb, linux-kernel,
Chunfeng Yun, linux-mediatek, Matthias Brugger, linux-arm-kernel
In-Reply-To: <1567150854-30033-1-git-send-email-chunfeng.yun@mediatek.com>
Support USB wakeup by ip-sleep mode for MT8183, it's similar to
MT8173
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v3: changes micros define
v2: no changes
---
drivers/usb/mtu3/mtu3_host.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/mtu3/mtu3_host.c b/drivers/usb/mtu3/mtu3_host.c
index c871b94f3e6f..4f8208885ebd 100644
--- a/drivers/usb/mtu3/mtu3_host.c
+++ b/drivers/usb/mtu3/mtu3_host.c
@@ -18,6 +18,12 @@
#include "mtu3.h"
#include "mtu3_dr.h"
+/* mt8183 etc */
+#define PERI_WK_CTRL0 0x20
+#define WC0_IS_C(x) (((x) & 0xf) << 28) /* cycle debounce */
+#define WC0_IS_P BIT(12) /* polarity */
+#define WC0_IS_EN BIT(6)
+
/* mt8173 etc */
#define PERI_WK_CTRL1 0x4
#define WC1_IS_C(x) (((x) & 0xf) << 26) /* cycle debounce */
@@ -30,7 +36,8 @@
#define SSC_SPM_INT_EN BIT(1)
enum ssusb_uwk_vers {
- SSUSB_UWK_V1 = 1,
+ SSUSB_UWK_V0 = 0,
+ SSUSB_UWK_V1,
SSUSB_UWK_V2,
};
@@ -43,6 +50,11 @@ static void ssusb_wakeup_ip_sleep_set(struct ssusb_mtk *ssusb, bool enable)
u32 reg, msk, val;
switch (ssusb->uwk_vers) {
+ case SSUSB_UWK_V0:
+ reg = ssusb->uwk_reg_base + PERI_WK_CTRL0;
+ msk = WC0_IS_EN | WC0_IS_C(0xf) | WC0_IS_P;
+ val = enable ? (WC0_IS_EN | WC0_IS_C(0x8)) : 0;
+ break;
case SSUSB_UWK_V1:
reg = ssusb->uwk_reg_base + PERI_WK_CTRL1;
msk = WC1_IS_EN | WC1_IS_C(0xf) | WC1_IS_P;
--
2.23.0
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^ permalink raw reply related
* [PATCH v3 2/7] dt-bindings: usb: mtk-xhci: support USB wakeup for MT8183
From: Chunfeng Yun @ 2019-08-30 7:40 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring
Cc: Mark Rutland, devicetree, Mathias Nyman, linux-usb, linux-kernel,
Chunfeng Yun, linux-mediatek, Matthias Brugger, linux-arm-kernel
In-Reply-To: <1567150854-30033-1-git-send-email-chunfeng.yun@mediatek.com>
Support USB wakeup by ip-sleep mode for MT8183
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
v2~v3: no changes
---
Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt
index 266c2d917a28..9a0a9eb0456f 100644
--- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt
+++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt
@@ -41,6 +41,7 @@ Optional properties:
"wakeup-source", and has two arguments:
- the first one : register base address of the glue layer in syscon;
- the second one : hardware version of the glue layer
+ - 0 : used by mt8183 etc
- 1 : used by mt8173 etc
- 2 : used by mt2712 etc
- mediatek,u3p-dis-msk : mask to disable u3ports, bit0 for u3port0,
--
2.23.0
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^ permalink raw reply related
* [PATCH v3 0/7] add support USB for MT8183
From: Chunfeng Yun @ 2019-08-30 7:40 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring
Cc: Mark Rutland, devicetree, Mathias Nyman, linux-usb, linux-kernel,
Chunfeng Yun, linux-mediatek, Matthias Brugger, linux-arm-kernel
This series support USB DRD controller and enable it's remote
wakeup functoin for MT8183, they depend on the following
series patches:
1. this series add support MT6358 PMIC
[v5,01/10] mfd: mt6397: clean up code
https://patchwork.kernel.org/patch/11110487/
2. this series add support pericfg syscon
[v2,1/2] dt-bindings: clock: mediatek: add pericfg for MT8183
https://patchwork.kernel.org/patch/11118183/
3. add property mediatek,discth for tphy
[06/11] phy: phy-mtk-tphy: add a property for disconnect threshold
https://patchwork.kernel.org/patch/11110695/
v3 changes:
1. changes micros define
2. remove #reset-cell
3. update dependent series
v2 changes:
add patch [7/7]
Chunfeng Yun (7):
dt-bindings: usb: mtu3: support USB wakeup for MT8183
dt-bindings: usb: mtk-xhci: support USB wakeup for MT8183
usb: mtu3: support ip-sleep wakeup for MT8183
usb: mtk-xhci: support ip-sleep wakeup for MT8183
arm64: dts: mt8183: add usb and phy nodes
arm64: dts: mt8183: enable USB remote wakeup
arm64: dts: mt8183: tune disconnect threshold of u2phy
.../bindings/usb/mediatek,mtk-xhci.txt | 1 +
.../devicetree/bindings/usb/mediatek,mtu3.txt | 1 +
arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 23 +++++++
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 63 +++++++++++++++++++
drivers/usb/host/xhci-mtk.c | 14 ++++-
drivers/usb/mtu3/mtu3_host.c | 14 ++++-
6 files changed, 114 insertions(+), 2 deletions(-)
--
2.23.0
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* [PATCH 0/2] drm/mediatek: fixup cursor moving unsmooth issue
From: Bibby Hsieh @ 2019-08-30 7:38 UTC (permalink / raw)
To: David Airlie, Matthias Brugger, Daniel Vetter, dri-devel,
linux-mediatek
Cc: drinkcat, Bibby Hsieh, linux-kernel, tfiga, CK Hu, Thierry Reding,
Philipp Zabel, YT Shen, linux-arm-kernel
These patches can fixup cursor moving is not smooth when heavy load in
webgl.
Bibby Hsieh (2):
drm/mediatek: Only block updates to CRTCs that have a pending update
drm/mediatek: Bypass atomic helpers for cursor updates
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 53 +++++-
drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 2 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 214 ++++++++++++++++++++---
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 15 +-
drivers/gpu/drm/mediatek/mtk_drm_plane.c | 73 +++++++-
5 files changed, 330 insertions(+), 27 deletions(-)
--
2.18.0
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