* Re: [PATCH 1/3] ARM: omap2plus_defconfig: Fix missing video
From: Tony Lindgren @ 2019-09-06 16:17 UTC (permalink / raw)
To: Adam Ford
Cc: Mark Rutland, devicetree, Russell King, linux-kernel, Rob Herring,
Benoît Cousson, linux-omap, linux-arm-kernel
In-Reply-To: <20190828183351.822-1-aford173@gmail.com>
* Adam Ford <aford173@gmail.com> [190828 11:34]:
> When the panel-dpi driver was removed, the simple-panels driver
> was never enabled, so anyone who used the panel-dpi driver lost
> video, and those who used it inconjunction with simple-panels
> would have to manually enable CONFIG_DRM_PANEL_SIMPLE.
>
> This patch makes CONFIG_DRM_PANEL_SIMPLE a module in the same
> way the deprecated panel-dpi was.
>
> Fixes: 8bf4b1621178 ("drm/omap: Remove panel-dpi driver")
Applying all three into fixes. Not going to send out a pull
request for the fixes until next week so it may not land
until after the merge window starts. But looks like these
have been broken since 2018, so not super urgent.
Regards,
Tony
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* Re: [PATCH] rtc: meson: mark PM functions as __maybe_unused
From: Kevin Hilman @ 2019-09-06 16:56 UTC (permalink / raw)
To: Arnd Bergmann, Alessandro Zummo, Alexandre Belloni
Cc: linux-rtc, Arnd Bergmann, Neil Armstrong, linux-kernel,
linux-amlogic, linux-arm-kernel
In-Reply-To: <20190906152438.1533833-1-arnd@arndb.de>
Arnd Bergmann <arnd@arndb.de> writes:
> The meson_vrtc_set_wakeup_time() function is only used by
> the PM functions and causes a warning when they are disabled:
>
> drivers/rtc/rtc-meson-vrtc.c:32:13: error: unused function 'meson_vrtc_set_wakeup_time' [-Werror,-Wunused-function]
>
> Remove the #ifdef around the callers and add a __maybe_unused
> annotation as a more reliable way to avoid these warnings.
>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
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* Re: [PATCH V4 01/11] dt-bindings: firmware: imx-scu: new binding to parse clocks from device tree
From: Stephen Boyd @ 2019-09-06 16:56 UTC (permalink / raw)
To: Dong Aisheng, linux-clk
Cc: Dong Aisheng, devicetree, mturquette, Rob Herring, linux-imx,
kernel, fabio.estevam, shawnguo, linux-arm-kernel
In-Reply-To: <1566299605-15641-2-git-send-email-aisheng.dong@nxp.com>
Quoting Dong Aisheng (2019-08-20 04:13:15)
> There's a few limitations on the original one cell clock binding
> (#clock-cells = <1>) that we have to define some SW clock IDs for device
> tree to reference. This may cause troubles if we want to use common
> clock IDs for multi platforms support when the clock of those platforms
> are mostly the same.
> e.g. Current clock IDs name are defined with SS prefix.
>
> However the device may reside in different SS across CPUs, that means the
> SS prefix may not valid anymore for a new SoC. Furthermore, the device
> availability of those clocks may also vary a bit.
>
> For such situation, we want to eliminate the using of SW Clock IDs and
> change to use a more close to HW one instead.
> For SCU clocks usage, only two params required: Resource id + Clock Type.
> Both parameters are platform independent. So we could use two cells binding
> to pass those parameters,
>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Sascha Hauer <kernel@pengutronix.de>
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> ---
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
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* Re: [PATCH V4 02/11] dt-bindings: clock: imx-lpcg: add support to parse clocks from device tree
From: Stephen Boyd @ 2019-09-06 17:00 UTC (permalink / raw)
To: Dong Aisheng, linux-clk
Cc: Dong Aisheng, devicetree, mturquette, Rob Herring, linux-imx,
kernel, fabio.estevam, shawnguo, linux-arm-kernel
In-Reply-To: <1566299605-15641-3-git-send-email-aisheng.dong@nxp.com>
Quoting Dong Aisheng (2019-08-20 04:13:16)
> MX8QM and MX8QXP LPCG Clocks are mostly the same except they may reside
> in different subsystems across CPUs and also vary a bit on the availability.
>
> Same as SCU clock, we want to move the clock definition into device tree
> which can fully decouple the dependency of Clock ID definition from device
> tree and make us be able to write a fully generic lpcg clock driver.
>
> And we can also use the existence of clock nodes in device tree to address
> the device and clock availability differences across different SoCs.
>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Stephen Boyd <sboyd@kernel.org>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Sascha Hauer <kernel@pengutronix.de>
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> ---
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
> ChangeLog:
> v3->v4:
> * change bit-offset property to clock-indices
> * use constant macro to define clock indinces
> * drop hw-autogate property which is still not used by drivers
> v2->v3:
> * no changes
> v1->v2:
> * Update example
> * Add power domain property
> ---
> .../devicetree/bindings/clock/imx8qxp-lpcg.txt | 36 ++++++++++++++++++----
> include/dt-bindings/clock/imx8-lpcg.h | 14 +++++++++
> 2 files changed, 44 insertions(+), 6 deletions(-)
> create mode 100644 include/dt-bindings/clock/imx8-lpcg.h
>
> diff --git a/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt b/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt
> index 965cfa4..cad8fc4 100644
> --- a/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt
> +++ b/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt
> @@ -11,6 +11,21 @@ enabled by these control bits, it might still not be running based
> on the base resource.
>
> Required properties:
> +- compatible: Should be one of:
> + "fsl,imx8qxp-lpcg"
> + "fsl,imx8qm-lpcg" followed by "fsl,imx8qxp-lpcg".
> +- reg: Address and length of the register set.
> +- #clock-cells: Should be 1. One LPCG supports multiple clocks.
> +- clocks: Input parent clocks phandle array for each clock.
> +- clock-indices: An integer array indicating the bit offset for each clock.
> + Refer to <include/dt-bindings/clock/imx8-lpcg.h> for the
> + supported LPCG clock indices.
This is an interesting solution.
> +- clock-output-names: Shall be the corresponding names of the outputs.
> + NOTE this property must be specified in the same order
> + as the clock-indices property.
> +- power-domains: Should contain the power domain used by this clock.
> +
> +Legacy binding (DEPRECATED):
> - compatible: Should be one of:
> "fsl,imx8qxp-lpcg-adma",
> "fsl,imx8qxp-lpcg-conn",
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* [PATCH] arm64: dts: zii-ultra: fix ARM regulator states
From: Lucas Stach @ 2019-09-06 17:06 UTC (permalink / raw)
To: Shawn Guo; +Cc: Fabio Estevam, kernel, linux-arm-kernel, patchwork-lst
The GPIO controlled regulator for the ARM power supply is supplying
the higher voltage when the GPIO is driven high. This is opposite to
the similar regulator setup on the EVK board and is impacting stability
of the board as the ARM domain has been supplied with a too low voltage
when to faster OPPs are in use.
Fixes: 4a13b3bec3b4 (arm64: dts: imx: add Zii Ultra board support)
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi
index 7a1706f969f0..3faa652fdf20 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi
@@ -101,8 +101,8 @@
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1000000>;
gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
- states = <1000000 0x0
- 900000 0x1>;
+ states = <1000000 0x1
+ 900000 0x0>;
regulator-always-on;
};
};
--
2.20.1
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* Re: [PATCH V4 03/11] clk: imx: scu: add two cells binding support
From: Stephen Boyd @ 2019-09-06 17:06 UTC (permalink / raw)
To: Dong Aisheng, linux-clk
Cc: Dong Aisheng, mturquette, linux-imx, kernel, fabio.estevam,
shawnguo, linux-arm-kernel
In-Reply-To: <1566299605-15641-4-git-send-email-aisheng.dong@nxp.com>
Quoting Dong Aisheng (2019-08-20 04:13:17)
> diff --git a/drivers/clk/imx/clk-imx8qxp.c b/drivers/clk/imx/clk-imx8qxp.c
> index 5e2903e..1ad3f2a 100644
> --- a/drivers/clk/imx/clk-imx8qxp.c
> +++ b/drivers/clk/imx/clk-imx8qxp.c
> @@ -134,7 +134,12 @@ static int imx8qxp_clk_probe(struct platform_device *pdev)
> i, PTR_ERR(clks[i]));
> }
>
> - return of_clk_add_hw_provider(ccm_node, of_clk_hw_onecell_get, clk_data);
> + if (clock_cells == 2)
Can you just read this from the DT node again instead of having a global
variable called "clock_cells" for this?
> + ret = of_clk_add_hw_provider(ccm_node, imx_scu_of_clk_src_get, imx_scu_clks);
> + else
> + ret = of_clk_add_hw_provider(ccm_node, of_clk_hw_onecell_get, clk_data);
> +
> + return ret;
> }
>
> static const struct of_device_id imx8qxp_match[] = {
> diff --git a/drivers/clk/imx/clk-scu.c b/drivers/clk/imx/clk-scu.c
> index fbef740..48bfb08 100644
> --- a/drivers/clk/imx/clk-scu.c
> +++ b/drivers/clk/imx/clk-scu.c
> @@ -16,6 +19,21 @@
> #define IMX_SIP_SET_CPUFREQ 0x00
>
> static struct imx_sc_ipc *ccm_ipc_handle;
> +struct device_node *pd_np;
> +u32 clock_cells;
> +
> +struct imx_scu_clk_node {
> + const char *name;
> + u32 rsrc;
> + u8 clk_type;
> + const char * const *parents;
> + int num_parents;
> +
> + struct clk_hw *hw;
> + struct list_head node;
> +};
> +
> +struct list_head imx_scu_clks[IMX_SC_R_LAST];
>
> /*
> * struct clk_scu - Description of one SCU clock
> @@ -128,9 +146,29 @@ static inline struct clk_scu *to_clk_scu(struct clk_hw *hw)
> return container_of(hw, struct clk_scu, hw);
> }
>
> -int imx_clk_scu_init(void)
> +int imx_clk_scu_init(struct device_node *np)
> {
> - return imx_scu_get_handle(&ccm_ipc_handle);
> + struct platform_device *pd_dev;
> + int ret, i;
> +
> + ret = imx_scu_get_handle(&ccm_ipc_handle);
> + if (ret)
> + return ret;
> +
> + if (of_property_read_u32(np, "#clock-cells", &clock_cells))
> + return -EINVAL;
> +
> + if (clock_cells == 2) {
> + for (i = 0; i < IMX_SC_R_LAST; i++)
> + INIT_LIST_HEAD(&imx_scu_clks[i]);
> +
> + pd_np = of_find_compatible_node(NULL, NULL, "fsl,scu-pd");
> + pd_dev = of_find_device_by_node(pd_np);
> + if (!pd_dev || !device_is_bound(&pd_dev->dev))
> + return -EPROBE_DEFER;
Do you need to put some nodes here with of_node_put() one failure or
when they're done being used?
> + }
> +
> + return 0;
> }
>
> /*
> @@ -387,3 +425,99 @@ struct clk_hw *__imx_clk_scu(const char *name, const char * const *parents,
[...]
> +
> +struct clk_hw *imx_clk_scu_alloc_dev(const char *name,
> + const char * const *parents,
> + int num_parents, u32 rsrc_id, u8 clk_type)
> +{
> + struct imx_scu_clk_node clk = {
> + .name = name,
> + .rsrc = rsrc_id,
> + .clk_type = clk_type,
> + .parents = parents,
> + .num_parents = num_parents,
> + };
> + struct platform_device *pdev;
> + int ret;
> +
> + pdev = platform_device_alloc(name, PLATFORM_DEVID_NONE);
> + if (!pdev) {
> + pr_err("%s: failed to allocate scu clk dev rsrc %d type %d\n",
> + name, rsrc_id, clk_type);
> + return ERR_PTR(-ENOMEM);
> + }
> +
> + ret = platform_device_add_data(pdev, &clk, sizeof(clk));
> + if (ret) {
> + platform_device_put(pdev);
> + return ERR_PTR(-ENOMEM);
Why not ERR_PTR(ret)?
> + }
> +
> + pdev->driver_override = "imx-scu-clk";
> +
> + ret = imx_clk_scu_attach_pd(&pdev->dev, rsrc_id);
> + if (ret)
> + pr_warn("%s: failed to attached the power domain %d\n",
> + name, ret);
> +
> + platform_device_add(pdev);
> +
> + /* For API backwards compatiblilty, simply return NULL for success */
> + return NULL;
> +}
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* Re: [PATCH V4 04/11] clk: imx: scu: bypass cpu power domains
From: Stephen Boyd @ 2019-09-06 17:07 UTC (permalink / raw)
To: Dong Aisheng, linux-clk
Cc: Dong Aisheng, mturquette, linux-imx, kernel, fabio.estevam,
shawnguo, linux-arm-kernel
In-Reply-To: <1566299605-15641-5-git-send-email-aisheng.dong@nxp.com>
Quoting Dong Aisheng (2019-08-20 04:13:18)
> diff --git a/drivers/clk/imx/clk-scu.c b/drivers/clk/imx/clk-scu.c
> index 48bfb08..5f935b1 100644
> --- a/drivers/clk/imx/clk-scu.c
> +++ b/drivers/clk/imx/clk-scu.c
> @@ -479,6 +479,10 @@ static int imx_clk_scu_attach_pd(struct device *dev, u32 rsrc_id)
> .args[0] = rsrc_id,
> };
>
> + if ((rsrc_id == IMX_SC_R_A35) || (rsrc_id == IMX_SC_R_A53) ||
> + (rsrc_id == IMX_SC_R_A72))
Please drop the extra parenthesis. It makes it hard to read.
> + return 0;
> +
> return of_genpd_add_device(&genpdspec, dev);
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* Re: [PATCH V4 07/11] clk: imx: scu: add suspend/resume support
From: Stephen Boyd @ 2019-09-06 17:09 UTC (permalink / raw)
To: Dong Aisheng, linux-clk
Cc: Dong Aisheng, mturquette, linux-imx, kernel, fabio.estevam,
shawnguo, linux-arm-kernel
In-Reply-To: <1566299605-15641-8-git-send-email-aisheng.dong@nxp.com>
Quoting Dong Aisheng (2019-08-20 04:13:21)
> Clock state will be lost when its power domain is completely off
> during system suspend/resume. So we save and restore the state
> accordingly in suspend/resume callback.
And this doesn't need any coordination with other clks in the clk tree
right?
> diff --git a/drivers/clk/imx/clk-scu.c b/drivers/clk/imx/clk-scu.c
> index edc39d7..8d9cfa2 100644
> --- a/drivers/clk/imx/clk-scu.c
> +++ b/drivers/clk/imx/clk-scu.c
> @@ -46,6 +46,10 @@ struct clk_scu {
> struct clk_hw hw;
> u16 rsrc_id;
> u8 clk_type;
> +
> + /* for state save&restore */
> + bool is_enabled;
> + u32 rate;
> };
>
> /*
> @@ -425,6 +429,9 @@ struct clk_hw *__imx_clk_scu(struct device *dev, const char *name,
> hw = ERR_PTR(ret);
> }
>
> + if (dev)
> + dev_set_drvdata(dev, clk);
> +
> return hw;
> }
>
> @@ -481,10 +488,52 @@ static int imx_clk_scu_probe(struct platform_device *pdev)
> return 0;
> }
>
> +int __maybe_unused imx_clk_scu_suspend(struct device *dev)
static?
> +{
> + struct clk_scu *clk = dev_get_drvdata(dev);
> +
> + clk->rate = clk_hw_get_rate(&clk->hw);
> + clk->is_enabled = clk_hw_is_enabled(&clk->hw);
> +
> + if (clk->rate)
> + dev_dbg(dev, "save rate %d\n", clk->rate);
> +
> + if (clk->is_enabled)
> + dev_dbg(dev, "save enabled state\n");
> +
> + return 0;
> +}
> +
> +int __maybe_unused imx_clk_scu_resume(struct device *dev)
static?
> +{
> + struct clk_scu *clk = dev_get_drvdata(dev);
> + int ret = 0;
> +
> + if (clk->rate) {
> + ret = clk_scu_set_rate(&clk->hw, clk->rate, 0);
> + dev_dbg(dev, "restore rate %d %s\n", clk->rate,
> + !ret ? "success" : "failed");
> + }
> +
> + if (clk->is_enabled) {
> + ret = clk_scu_prepare(&clk->hw);
> + dev_dbg(dev, "restore enabled state %s\n",
> + !ret ? "success" : "failed");
> + }
> +
> + return ret;
> +}
> +
> +const struct dev_pm_ops imx_clk_scu_pm_ops = {
static?
> + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx_clk_scu_suspend,
> + imx_clk_scu_resume)
> +};
> +
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* Re: [PATCH V4 08/11] clk: imx: imx8qxp-lpcg: add parsing clocks from device tree
From: Stephen Boyd @ 2019-09-06 17:13 UTC (permalink / raw)
To: Dong Aisheng, linux-clk
Cc: Dong Aisheng, mturquette, linux-imx, kernel, fabio.estevam,
shawnguo, linux-arm-kernel
In-Reply-To: <1566299605-15641-9-git-send-email-aisheng.dong@nxp.com>
Quoting Dong Aisheng (2019-08-20 04:13:22)
> Add parsing clocks from device tree.
Please describe some more here.
> diff --git a/drivers/clk/imx/clk-imx8qxp-lpcg.c b/drivers/clk/imx/clk-imx8qxp-lpcg.c
> index c0aff7c..90326e5 100644
> --- a/drivers/clk/imx/clk-imx8qxp-lpcg.c
> +++ b/drivers/clk/imx/clk-imx8qxp-lpcg.c
> @@ -157,6 +158,101 @@ static const struct imx8qxp_ss_lpcg imx8qxp_ss_lsio = {
> .num_max = IMX_LSIO_LPCG_CLK_END,
> };
>
> +#define IMX_LPCG_MAX_CLKS 8
> +
> +static struct clk_hw *imx_lpcg_of_clk_src_get(struct of_phandle_args *clkspec,
> + void *data)
> +{
> + struct clk_hw_onecell_data *hw_data = data;
> + unsigned int idx = clkspec->args[0] / 4;
> +
> + if (idx >= hw_data->num) {
> + pr_err("%s: invalid index %u\n", __func__, idx);
> + return ERR_PTR(-EINVAL);
> + }
> +
> + return hw_data->hws[idx];
> +}
> +
> +static int imx_lpcg_parse_clks_from_dt(struct platform_device *pdev,
> + struct device_node *np)
> +{
> + const char *output_names[IMX_LPCG_MAX_CLKS];
> + const char *parent_names[IMX_LPCG_MAX_CLKS];
> + unsigned int bit_offset[IMX_LPCG_MAX_CLKS];
> + struct clk_hw_onecell_data *clk_data;
> + struct clk_hw **clk_hws;
> + struct resource *res;
> + void __iomem *base;
> + int count;
> + int idx;
> + int ret;
> + int i;
> +
> + if (!of_device_is_compatible(np, "fsl,imx8qxp-lpcg"))
> + return -EINVAL;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + count = of_property_count_u32_elems(np, "clock-indices");
> + if (count < 0) {
> + dev_err(&pdev->dev, "failed to count clocks\n");
> + return -EINVAL;
> + }
Is 'count' expected to be equal to IMX_LPCG_MAX_CLKS? Because later on
in this function we set the num of clks to the MAX instead of the count
from clock-indices.
> +
> + clk_data = devm_kzalloc(&pdev->dev, struct_size(clk_data, hws, IMX_LPCG_MAX_CLKS),
This line is too long.
> + GFP_KERNEL);
> + if (!clk_data)
> + return -ENOMEM;
> +
> + clk_data->num = IMX_LPCG_MAX_CLKS;
> + clk_hws = clk_data->hws;
> +
> + ret = of_property_read_u32_array(np, "clock-indices", bit_offset,
> + count);
> + if (ret < 0) {
> + dev_err(&pdev->dev, "failed to read clocks bit-offset\n");
This isn't called bit-offset anymore.
> + return -EINVAL;
> + }
> +
> + ret = of_clk_parent_fill(np, parent_names, count);
> + if (ret != count) {
> + dev_err(&pdev->dev, "failed to get clock parent names\n");
> + return -EINVAL;
return count?
> + }
> +
> + ret = of_property_read_string_array(np, "clock-output-names",
> + output_names, count);
> + if (ret != count) {
> + dev_err(&pdev->dev, "failed to read clock-output-names\n");
> + return -EINVAL;
> + }
> +
> + for (i = 0; i < count; i++) {
> + idx = bit_offset[i] / 4;
> + if (idx > IMX_LPCG_MAX_CLKS) {
> + dev_warn(&pdev->dev, "invalid bit offset of clock %d\n",
> + i);
> + return -EINVAL;
> + }
> +
> + clk_hws[idx] = imx_clk_lpcg_scu(output_names[i],
> + parent_names[i], 0, base,
> + bit_offset[i], false);
> + if (IS_ERR(clk_hws[idx])) {
> + dev_warn(&pdev->dev, "failed to register clock %d\n",
> + idx);
> + return -EINVAL;
> + }
> + }
> +
> + return devm_of_clk_add_hw_provider(&pdev->dev, imx_lpcg_of_clk_src_get,
> + clk_data);
If this fails does imx_clk_lpcg_scu() need to be unwound and unregister
clks?
> +}
> +
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* Re: [PATCH V4 11/11] clk: imx: lpcg: add suspend/resume support
From: Stephen Boyd @ 2019-09-06 17:14 UTC (permalink / raw)
To: Dong Aisheng, linux-clk
Cc: Dong Aisheng, mturquette, linux-imx, kernel, fabio.estevam,
shawnguo, linux-arm-kernel
In-Reply-To: <1566299605-15641-12-git-send-email-aisheng.dong@nxp.com>
Quoting Dong Aisheng (2019-08-20 04:13:25)
> diff --git a/drivers/clk/imx/clk-lpcg-scu.c b/drivers/clk/imx/clk-lpcg-scu.c
> index 3c092a0..4df0818 100644
> --- a/drivers/clk/imx/clk-lpcg-scu.c
> +++ b/drivers/clk/imx/clk-lpcg-scu.c
> @@ -33,6 +33,9 @@ struct clk_lpcg_scu {
> void __iomem *reg;
> u8 bit_idx;
> bool hw_gate;
> +
> + /* for state save&restore */
> + u32 state;
> };
>
> #define to_clk_lpcg_scu(_hw) container_of(_hw, struct clk_lpcg_scu, hw)
> @@ -112,5 +115,35 @@ struct clk_hw *__imx_clk_lpcg_scu(struct device *dev, const char *name,
> hw = ERR_PTR(ret);
> }
>
> + if (dev)
> + dev_set_drvdata(dev, clk);
> +
> return hw;
> }
> +
> +int __maybe_unused imx_clk_lpcg_scu_suspend(struct device *dev)
static?
> +{
> + struct clk_lpcg_scu *clk = dev_get_drvdata(dev);
> +
> + clk->state = readl_relaxed(clk->reg);
> + dev_dbg(dev, "save lpcg state 0x%x\n", clk->state);
> +
> + return 0;
> +}
> +
> +int __maybe_unused imx_clk_lpcg_scu_resume(struct device *dev)
static?
> +{
> + struct clk_lpcg_scu *clk = dev_get_drvdata(dev);
> +
> + /* FIXME: double write in case a failure */
What does this mean? Sometimes writes don't work unless the CPU issues
them twice?
> + writel(clk->state, clk->reg);
> + writel(clk->state, clk->reg);
> + dev_dbg(dev, "restore lpcg state 0x%x\n", clk->state);
> +
> + return 0;
> +}
> +
> +const struct dev_pm_ops imx_clk_lpcg_scu_pm_ops = {
> + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx_clk_lpcg_scu_suspend,
> + imx_clk_lpcg_scu_resume)
> +};
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* Re: [Xen-devel] [PATCH] ARM: xen: unexport HYPERVISOR_platform_op function
From: Andrew Cooper @ 2019-09-06 17:20 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Stefano Stabellini, Emil Velikov, Russell King, Denis Efremov,
linux-kernel@vger.kernel.org, Masahiro Yamada, Julien Grall,
xen-devel, Linux ARM
In-Reply-To: <CAK8P3a1qkMLW_Wnn-N0seUw4N5bPwTU7Dy7CwOWxzS6NTnTmiQ@mail.gmail.com>
On 06/09/2019 17:00, Arnd Bergmann wrote:
> On Fri, Sep 6, 2019 at 5:55 PM Andrew Cooper <andrew.cooper3@citrix.com> wrote:
>> On 06/09/2019 16:39, Arnd Bergmann wrote:
>>> HYPERVISOR_platform_op() is an inline function and should not
>>> be exported. Since commit 15bfc2348d54 ("modpost: check for
>>> static EXPORT_SYMBOL* functions"), this causes a warning:
>>>
>>> WARNING: "HYPERVISOR_platform_op" [vmlinux] is a static EXPORT_SYMBOL_GPL
>>>
>>> Remove the extraneous export.
>>>
>>> Fixes: 15bfc2348d54 ("modpost: check for static EXPORT_SYMBOL* functions")
>>> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
>> Something is wonky. That symbol is (/ really ought to be) in the
>> hypercall page and most definitely not inline.
>>
>> Which tree is that changeset from? I can't find the SHA.
> This is from linux-next, I think from the kbuild tree.
Thanks.
Julien/Stefano: Why are any of these hypercalls out-of-line? ARM
doesn't use the hypercall page, and there is no argument translation
(not even in arm32 as there are no 5-argument hypercalls declared).
They'd surely be easier to implement with a few static inlines and some
common code, than to try and replicate the x86 side hypercall_page
interface ?
~Andrew
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* Re: [PATCH] clk: imx: lpcg: write twice when writing lpcg regs
From: Stephen Boyd @ 2019-09-06 17:20 UTC (permalink / raw)
To: festevam@gmail.com, mturquette@baylibre.com,
s.hauer@pengutronix.de, shawnguo@kernel.org, Aisheng Dong,
Peng Fan
Cc: Peng Fan, Abel Vesa, Anson Huang, linux-kernel@vger.kernel.org,
dl-linux-imx, kernel@pengutronix.de, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, Jacky Bai
In-Reply-To: <1566936978-28519-1-git-send-email-peng.fan@nxp.com>
Quoting Peng Fan (2019-08-27 01:17:50)
> From: Peng Fan <peng.fan@nxp.com>
>
> There is hardware issue that:
> The output clock the LPCG cell will not turn back on as expected,
> even though a read of the IPG registers in the LPCG indicates that
> the clock should be enabled.
>
> The software workaround is to write twice to enable the LPCG clock
> output.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Does this need a Fixes tag?
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* Re: [PATCH V2 1/4] clk: imx: pll14xx: avoid glitch when set rate
From: Stephen Boyd @ 2019-09-06 17:21 UTC (permalink / raw)
To: festevam@gmail.com, mturquette@baylibre.com,
s.hauer@pengutronix.de, shawnguo@kernel.org, Peng Fan
Cc: Peng Fan, Abel Vesa, Anson Huang, linux-kernel@vger.kernel.org,
dl-linux-imx, kernel@pengutronix.de, Leonard Crestez,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
Jacky Bai
In-Reply-To: <1566855676-11510-1-git-send-email-peng.fan@nxp.com>
Quoting Peng Fan (2019-08-26 02:42:14)
> From: Peng Fan <peng.fan@nxp.com>
>
> According to PLL1443XA and PLL1416X spec,
> "When BYPASS is 0 and RESETB is changed from 0 to 1, FOUT starts to
> output unstable clock until lock time passes. PLL1416X/PLL1443XA may
> generate a glitch at FOUT."
>
> So set BYPASS when RESETB is changed from 0 to 1 to avoid glitch.
> In the end of set rate, BYPASS will be cleared.
>
> When prepare clock, also need to take care to avoid glitch. So
> we also follow Spec to set BYPASS before RESETB changed from 0 to 1.
> And add a check if the RESETB is already 0, directly return 0;
>
> Fixes: 8646d4dcc7fb ("clk: imx: Add PLLs driver for imx8mm soc")
> Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> ---
Please make cover letters for multi-patch series.
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* Re: [PATCH] clk: imx: pll14xx: Fix quick switch of S/K parameter
From: Stephen Boyd @ 2019-09-06 17:24 UTC (permalink / raw)
To: Leonard Crestez, Peng Fan, Shawn Guo
Cc: Dong Aisheng, Jacky Bai, Michael Turquette, linux-clk, linux-imx,
Viorel Suman, Fabio Estevam, Daniel Baluta, kernel,
linux-arm-kernel, Abel Vesa
In-Reply-To: <c3e86b5a832a14278e8ba670d51defc70ee78d84.1567590349.git.leonard.crestez@nxp.com>
Quoting Leonard Crestez (2019-09-04 02:49:18)
> The PLL14xx on imx8m can change the S and K parameter without requiring
> a reset and relock of the whole PLL.
>
> Fix clk_pll144xx_mp_change register reading and use it for pll1443 as
> well since no reset+relock is required on K changes either.
>
> Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
> ---
> drivers/clk/imx/clk-pll14xx.c | 40 +++++++----------------------------
> 1 file changed, 8 insertions(+), 32 deletions(-)
>
> The PLLs are currently table-based and none of the entries differ only
> in S/K so further work would be required to make use of this. The
> prospective user is audio doing tiny freq adjustments and there is no
> standard API for that.
sub-Hz adjustments?
>
> Lacking users is not a good reason to carry broken code around.
Maybe add a Fixes tag so if anyone wants to use it in LTS kernels there
might be a chance that they'll find this patch mention code they're
using.
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* Re: [PATCH] clk: spear: Make structure i2s_sclk_masks constant
From: Stephen Boyd @ 2019-09-06 17:27 UTC (permalink / raw)
To: Nishka Dasgupta, linux-arm-kernel, linux-clk, mturquette, vireshk
Cc: Nishka Dasgupta
In-Reply-To: <20190813085714.8079-1-nishkadg.linux@gmail.com>
Quoting Nishka Dasgupta (2019-08-13 01:57:14)
> Static structure i2s_sclk_masks, having type aux_clk_masks, is only used
> when it is passed as the sixth argument to function clk_register_aux().
> However, clk_register_aux() is defined with its sixth argument as const.
> Hence i2s_sclk_masks is not modified by clk_register_aux, which is also
> the only usage of the former. Therefore make i2s_sclk_masks constant as
> it is never modified.
> Issue found with Coccinelle.
>
> Signed-off-by: Nishka Dasgupta <nishkadg.linux@gmail.com>
> ---
Applied to clk-next
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* Re: [PATCH] clk: fix devm_platform_ioremap_resource.cocci warnings
From: Stephen Boyd @ 2019-09-06 17:30 UTC (permalink / raw)
To: Jonas Gorski, Julia Lawall
Cc: Florian Fainelli, Michael Turquette, Philippe Mathieu-Daud??,
linux-kernel, bcm-kernel-feedback-list, kbuild-all, linux-clk,
linux-arm-kernel
In-Reply-To: <alpine.DEB.2.21.1908081809160.2995@hadrien>
Quoting Julia Lawall (2019-08-08 09:10:53)
> From: kbuild test robot <lkp@intel.com>
>
> drivers/clk/bcm/clk-bcm63xx-gate.c:174:1-9: WARNING: Use devm_platform_ioremap_resource for hw -> regs
>
> Use devm_platform_ioremap_resource helper which wraps
> platform_get_resource() and devm_ioremap_resource() together.
>
> Generated by: scripts/coccinelle/api/devm_platform_ioremap_resource.cocci
>
> Fixes: 1c099779c1e2 ("clk: add BCM63XX gated clock controller driver")
> CC: Jonas Gorski <jonas.gorski@gmail.com>
> Signed-off-by: kbuild test robot <lkp@intel.com>
> Signed-off-by: Julia Lawall <julia.lawall@lip6.fr>
> ---
Applied to clk-next
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* Re: [PATCH v3 07/17] arm64, hibernate: move page handling function to new trans_pgd.c
From: Pavel Tatashin @ 2019-09-06 17:41 UTC (permalink / raw)
To: James Morse
Cc: Sasha Levin, Mark Rutland, Vladimir Murzin, Jonathan Corbet,
Marc Zyngier, Catalin Marinas, Bhupesh Sharma, kexec mailing list,
LKML, James Morris, linux-mm, Eric W. Biederman, Matthias Brugger,
will, Linux ARM
In-Reply-To: <f1db863a-de57-2d1a-6bec-6020b2130964@arm.com>
On Fri, Sep 6, 2019 at 11:18 AM James Morse <james.morse@arm.com> wrote:
>
> Hi Pavel,
>
> On 21/08/2019 19:31, Pavel Tatashin wrote:
> > Now, that we abstracted the required functions move them to a new home.
> > Later, we will generalize these function in order to be useful outside
> > of hibernation.
>
> > diff --git a/arch/arm64/mm/trans_pgd.c b/arch/arm64/mm/trans_pgd.c
> > new file mode 100644
> > index 000000000000..00b62d8640c2
> > --- /dev/null
> > +++ b/arch/arm64/mm/trans_pgd.c
> > @@ -0,0 +1,211 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +
> > +/*
> > + * Copyright (c) 2019, Microsoft Corporation.
> > + * Pavel Tatashin <patatash@linux.microsoft.com>
>
> Hmmm, while line-count isn't a useful metric: this file contains 41% of the code that was
> in hibernate.c, but has stripped the substantial copyright-pedigree that the hibernate
> code had built up over the years.
> (counting lines identified by 'cloc' as code, not comments or blank)
>
> If you are copying or moving a non trivial quantity of code, you need to preserve the
> copyright. Something like 'Derived from the arm64 hibernate support which has:'....
I will do that. The copyright thing was meant to appear in
"generalization" patch that comes later, where I unified most of the
code to be symmetric.
So, I will add it there, and also do the derived message that you suggested.
>
>
> > + */
> > +
> > +/*
> > + * Transitional tables are used during system transferring from one world to
> > + * another: such as during hibernate restore, and kexec reboots. During these
> > + * phases one cannot rely on page table not being overwritten.
>
> I think you need to mention that hibernate and kexec are rewriting memory, and may
> overwrite the live page tables, therefore ...
Will add, thank you.
Pasha
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* Re: [PATCH v4 3/4] dt-bindings: Add Qualcomm USB SuperSpeed PHY bindings
From: Bjorn Andersson @ 2019-09-06 18:25 UTC (permalink / raw)
To: Stephen Boyd
Cc: mark.rutland, robh, Jack Pham, devicetree, gregkh, linux-usb,
khasim.mohammed, linux-kernel, kishon, linux-arm-msm, andy.gross,
Jorge Ramirez, shawn.guo, linux-arm-kernel
In-Reply-To: <5d71edf5.1c69fb81.1f307.fdd6@mx.google.com>
On Thu 05 Sep 22:26 PDT 2019, Stephen Boyd wrote:
> Quoting Jack Pham (2019-09-05 10:58:02)
> > Hi Jorge, Bjorn,
> >
> > On Thu, Sep 05, 2019 at 09:18:57AM +0200, Jorge Ramirez wrote:
> > > On 9/4/19 01:34, Bjorn Andersson wrote:
> > > > On Tue 03 Sep 14:45 PDT 2019, Stephen Boyd wrote:
> > > >> that would need an of_regulator_get() sort of API that can get the
> > > >> regulator out of there? Or to make the connector into a struct device
> > > >> that can get the regulator out per some generic connector driver and
> > > >> then pass it through to the USB controller when it asks for it. Maybe
> > > >> try to prototype that out?
> > > >>
> > > >
> > > > The examples given in the DT bindings describes the connector as a child
> > > > of a PMIC, with of_graph somehow tying it to the various inputs. But in
> > > > these examples vbus is handled by implicitly inside the MFD, where
> > > > extcon is informed about the plug event they toggle vbus as well.
> > > >
> > > > In our case we have a extcon-usb-gpio to detect mode, which per Jorge's
> > > > proposal will trickle down to the PHY and become a regulator calls on
> > > > either some external regulator or more typically one of the chargers in
> > > > the system.
> >
> > Interesting you mention extcon-usb-gpio. I thought extcon at least from
> > bindings perspective is passé now. Maybe this is what you need (just
> > landed in usb-next):
> >
> > usb: common: add USB GPIO based connection detection driver
> > https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git/commit/?h=usb-next&id=4602f3bff2669012c1147eecfe74c121765f5c56
> >
> > dt-bindings: usb: add binding for USB GPIO based connection detection driver
> > https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git/commit/?h=usb-next&id=f651c73e71f53f65e9846677d79d8e120452b59f
> >
> > Fortunately this new driver might check the right boxes for you:
> > - usb connector binding
> > - ID detect GPIO
> > - vbus-supply regulator
> >
> > With that, I think you can also keep the connector subnode out of the
> > SSPHY node well, and similarly get rid of the vbus toggle handling from
> > the PHY driver.
> >
> > The big thing missing now is that this driver replaces extcon
> > completely, so we'll need handling in dwc3/dwc3-qcom to retrieve the
> > role switch state to know when host mode is entered. I saw this a while
> > back but don't think it got picked up:
> >
> > https://patchwork.kernel.org/patch/10909981/
> >
>
> Yes this looks like the approach that should be taken. One question
> though, is this a micro-b connector or a type-c connector on the board?
> I thought it was a type-c, so then this USB gpio based connection driver
> isn't an exact fit?
>
For this particular case it's a type c connector, but the port
controller is operated completely passively (and there's no PD or DP
involved), so the GPIO based approach seems like a good fit.
Regards,
Bjorn
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* [PATCH 0/9] crypto: add sun8i-ce driver for Allwinner crypto engine
From: Corentin Labbe @ 2019-09-06 18:45 UTC (permalink / raw)
To: davem, herbert, linux, mark.rutland, mripard, robh+dt, wens
Cc: devicetree, linux-kernel, linux-sunxi, Corentin Labbe,
linux-crypto, linux-arm-kernel
Hello
This patch serie adds support for the Allwinner crypto engine.
The Crypto Engine is the third generation of Allwinner cryptogaphic offloader.
The first generation is the Security System already handled by the
sun4i-ss driver.
The second is named also Security System and is present on A80 and A83T
SoCs, originaly this driver supported it also, but supporting both IP bringing
too much complexity and another driver (sun8i-ss) will came for it.
For the moment, the driver support only DES3/AES in ECB/CBC mode.
Patchs for CTR/CTS/XTS and RNGs will came later.
Regards
Corentin Labbe (9):
crypto: Add allwinner subdirectory
crypto: Add Allwinner sun8i-ce Crypto Engine
dt-bindings: crypto: Add DT bindings documentation for sun8i-ce Crypto
Engine
ARM: dts: sun8i: r40: add crypto engine node
ARM: dts: sun8i: h3: Add Crypto Engine node
ARM64: dts: allwinner: sun50i: Add Crypto Engine node on A64
ARM64: dts: allwinner: sun50i: Add crypto engine node on H5
ARM64: dts: allwinner: sun50i: Add Crypto Engine node on H6
sunxi_defconfig: add new crypto options
.../bindings/crypto/allwinner,sun8i-ce.yaml | 84 +++
MAINTAINERS | 6 +
arch/arm/boot/dts/sun8i-h3.dtsi | 11 +
arch/arm/boot/dts/sun8i-r40.dtsi | 11 +
arch/arm/configs/sunxi_defconfig | 2 +
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 11 +
arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 11 +
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 +
drivers/crypto/Kconfig | 2 +
drivers/crypto/Makefile | 1 +
drivers/crypto/allwinner/Kconfig | 32 +
drivers/crypto/allwinner/Makefile | 1 +
drivers/crypto/allwinner/sun8i-ce/Makefile | 2 +
.../allwinner/sun8i-ce/sun8i-ce-cipher.c | 390 +++++++++++
.../crypto/allwinner/sun8i-ce/sun8i-ce-core.c | 630 ++++++++++++++++++
drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h | 256 +++++++
16 files changed, 1460 insertions(+)
create mode 100644 Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.yaml
create mode 100644 drivers/crypto/allwinner/Kconfig
create mode 100644 drivers/crypto/allwinner/Makefile
create mode 100644 drivers/crypto/allwinner/sun8i-ce/Makefile
create mode 100644 drivers/crypto/allwinner/sun8i-ce/sun8i-ce-cipher.c
create mode 100644 drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
create mode 100644 drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h
--
2.21.0
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* [PATCH 1/9] crypto: Add allwinner subdirectory
From: Corentin Labbe @ 2019-09-06 18:45 UTC (permalink / raw)
To: davem, herbert, linux, mark.rutland, mripard, robh+dt, wens
Cc: devicetree, linux-kernel, linux-sunxi, Corentin Labbe,
linux-crypto, linux-arm-kernel
In-Reply-To: <20190906184551.17858-1-clabbe.montjoie@gmail.com>
Since a second Allwinner crypto driver will be added, it is better to
create a dedicated subdirectory.
Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
---
MAINTAINERS | 6 ++++++
drivers/crypto/Kconfig | 2 ++
drivers/crypto/Makefile | 1 +
drivers/crypto/allwinner/Kconfig | 6 ++++++
4 files changed, 15 insertions(+)
create mode 100644 drivers/crypto/allwinner/Kconfig
diff --git a/MAINTAINERS b/MAINTAINERS
index ee4e873c0f9a..d62ddf8ff262 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -681,6 +681,12 @@ L: linux-crypto@vger.kernel.org
S: Maintained
F: drivers/crypto/sunxi-ss/
+ALLWINNER CRYPTO ENGINE
+M: Corentin Labbe <clabbe.montjoie@gmail.com>
+L: linux-crypto@vger.kernel.org
+S: Maintained
+F: drivers/crypto/allwinner/
+
ALLWINNER VPU DRIVER
M: Maxime Ripard <mripard@kernel.org>
M: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 83271d944a96..fe90dd74797c 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -11,6 +11,8 @@ menuconfig CRYPTO_HW
if CRYPTO_HW
+source "drivers/crypto/allwinner/Kconfig"
+
config CRYPTO_DEV_PADLOCK
tristate "Support for VIA PadLock ACE"
depends on X86 && !UML
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index afc4753b5d28..90d60eff5ecc 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_CRYPTO_DEV_ALLWINNER) += allwinner/
obj-$(CONFIG_CRYPTO_DEV_ATMEL_AES) += atmel-aes.o
obj-$(CONFIG_CRYPTO_DEV_ATMEL_SHA) += atmel-sha.o
obj-$(CONFIG_CRYPTO_DEV_ATMEL_TDES) += atmel-tdes.o
diff --git a/drivers/crypto/allwinner/Kconfig b/drivers/crypto/allwinner/Kconfig
new file mode 100644
index 000000000000..0c8a99f7959d
--- /dev/null
+++ b/drivers/crypto/allwinner/Kconfig
@@ -0,0 +1,6 @@
+config CRYPTO_DEV_ALLWINNER
+ bool "Support for Allwinner cryptographic offloader"
+ depends on ARCH_SUNXI || COMPILE_TEST
+ default y if ARCH_SUNXI
+ help
+ Say Y here to get to see options for Allwinner hardware crypto devices
--
2.21.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH 3/9] dt-bindings: crypto: Add DT bindings documentation for sun8i-ce Crypto Engine
From: Corentin Labbe @ 2019-09-06 18:45 UTC (permalink / raw)
To: davem, herbert, linux, mark.rutland, mripard, robh+dt, wens
Cc: devicetree, linux-kernel, linux-sunxi, Corentin Labbe,
linux-crypto, linux-arm-kernel
In-Reply-To: <20190906184551.17858-1-clabbe.montjoie@gmail.com>
This patch adds documentation for Device-Tree bindings for the
Crypto Engine cryptographic accelerator driver.
Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
---
.../bindings/crypto/allwinner,sun8i-ce.yaml | 84 +++++++++++++++++++
1 file changed, 84 insertions(+)
create mode 100644 Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.yaml
diff --git a/Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.yaml b/Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.yaml
new file mode 100644
index 000000000000..bd8ccedd6059
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.yaml
@@ -0,0 +1,84 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/crypto/allwinner,sun8i-ce.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Allwinner Crypto Engine driver
+
+maintainers:
+ - Corentin Labbe <clabbe@baylibre.com>
+
+properties:
+ compatible:
+ oneOf:
+ - const: allwinner,sun8i-h3-crypto
+ - const: allwinner,sun8i-r40-crypto
+ - const: allwinner,sun50i-a64-crypto
+ - const: allwinner,sun50i-h5-crypto
+ - const: allwinner,sun50i-h6-crypto
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+if:
+ properties:
+ compatible:
+ contains:
+ const: allwinner,sun50i-h6-crypto
+then:
+ clocks:
+ items:
+ - description: Bus clock
+ - description: Module clock
+ - description: MBus clock
+
+ clock-names:
+ items:
+ - const: ahb
+ - const: mod
+ - const: mbus
+else:
+ clocks:
+ items:
+ - description: Bus clock
+ - description: Module clock
+
+ clock-names:
+ items:
+ - const: ahb
+ - const: mod
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ const: ahb
+
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/sun50i-a64-ccu.h>
+ #include <dt-bindings/reset/sun50i-a64-ccu.h>
+
+ crypto: crypto@1c15000 {
+ compatible = "allwinner,sun8i-h3-crypto";
+ reg = <0x01c15000 0x1000>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
+ clock-names = "ahb", "mod";
+ resets = <&ccu RST_BUS_CE>;
+ reset-names = "ahb";
+ };
+
--
2.21.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* [PATCH 2/9] crypto: Add Allwinner sun8i-ce Crypto Engine
From: Corentin Labbe @ 2019-09-06 18:45 UTC (permalink / raw)
To: davem, herbert, linux, mark.rutland, mripard, robh+dt, wens
Cc: devicetree, linux-kernel, linux-sunxi, Corentin Labbe,
linux-crypto, linux-arm-kernel
In-Reply-To: <20190906184551.17858-1-clabbe.montjoie@gmail.com>
The Crypto Engine is an hardware cryptographic offloader present
on all recent Allwinner SoCs H2+, H3, R40, A64, H5, H6
This driver supports AES cipher in CBC/ECB mode.
Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
---
drivers/crypto/allwinner/Kconfig | 26 +
drivers/crypto/allwinner/Makefile | 1 +
drivers/crypto/allwinner/sun8i-ce/Makefile | 2 +
.../allwinner/sun8i-ce/sun8i-ce-cipher.c | 390 +++++++++++
.../crypto/allwinner/sun8i-ce/sun8i-ce-core.c | 630 ++++++++++++++++++
drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h | 256 +++++++
6 files changed, 1305 insertions(+)
create mode 100644 drivers/crypto/allwinner/Makefile
create mode 100644 drivers/crypto/allwinner/sun8i-ce/Makefile
create mode 100644 drivers/crypto/allwinner/sun8i-ce/sun8i-ce-cipher.c
create mode 100644 drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
create mode 100644 drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h
diff --git a/drivers/crypto/allwinner/Kconfig b/drivers/crypto/allwinner/Kconfig
index 0c8a99f7959d..742a08b64c90 100644
--- a/drivers/crypto/allwinner/Kconfig
+++ b/drivers/crypto/allwinner/Kconfig
@@ -4,3 +4,29 @@ config CRYPTO_DEV_ALLWINNER
default y if ARCH_SUNXI
help
Say Y here to get to see options for Allwinner hardware crypto devices
+
+config CRYPTO_DEV_SUN8I_CE
+ tristate "Support for Allwinner Crypto Engine cryptographic offloader"
+ select CRYPTO_BLKCIPHER
+ select CRYPTO_ENGINE
+ select CRYPTO_ECB
+ select CRYPTO_CBC
+ select CRYPTO_AES
+ select CRYPTO_DES
+ depends on CRYPTO_DEV_ALLWINNER
+ help
+ Select y here for having support for the crypto Engine availlable on
+ Allwinner SoC H2+, H3, H5, H6, R40 and A64.
+ The Crypto Engine handle AES/3DES ciphers in ECB/CBC mode.
+
+ To compile this driver as a module, choose M here: the module
+ will be called sun8i-ce.
+
+config CRYPTO_DEV_SUN8I_CE_DEBUG
+ bool "Enabled sun8i-ce stats"
+ depends on CRYPTO_DEV_SUN8I_CE
+ depends on DEBUG_FS
+ help
+ Say y to enabled sun8i-ce debug stats.
+ This will create /sys/kernel/debug/sun8i-ce/stats for displaying
+ the number of requests per flow and per algorithm.
diff --git a/drivers/crypto/allwinner/Makefile b/drivers/crypto/allwinner/Makefile
new file mode 100644
index 000000000000..11f02db9ee06
--- /dev/null
+++ b/drivers/crypto/allwinner/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_CRYPTO_DEV_SUN8I_CE) += sun8i-ce/
diff --git a/drivers/crypto/allwinner/sun8i-ce/Makefile b/drivers/crypto/allwinner/sun8i-ce/Makefile
new file mode 100644
index 000000000000..08b68c3c1ca9
--- /dev/null
+++ b/drivers/crypto/allwinner/sun8i-ce/Makefile
@@ -0,0 +1,2 @@
+obj-$(CONFIG_CRYPTO_DEV_SUN8I_CE) += sun8i-ce.o
+sun8i-ce-y += sun8i-ce-core.o sun8i-ce-cipher.o
diff --git a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-cipher.c b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-cipher.c
new file mode 100644
index 000000000000..c22f0592f168
--- /dev/null
+++ b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-cipher.c
@@ -0,0 +1,390 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * sun8i-ce-cipher.c - hardware cryptographic offloader for
+ * Allwinner H3/A64/H5/H2+/H6/R40 SoC
+ *
+ * Copyright (C) 2016-2019 Corentin LABBE <clabbe.montjoie@gmail.com>
+ *
+ * This file add support for AES cipher with 128,192,256 bits keysize in
+ * CBC and ECB mode.
+ *
+ * You could find a link for the datasheet in Documentation/arm/sunxi/README
+ */
+
+#include <linux/crypto.h>
+#include <linux/dma-mapping.h>
+#include <linux/io.h>
+#include <crypto/scatterwalk.h>
+#include <crypto/internal/des.h>
+#include <crypto/internal/skcipher.h>
+#include "sun8i-ce.h"
+
+static int sun8i_ce_cipher(struct skcipher_request *areq)
+{
+ struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(areq);
+ struct sun8i_cipher_tfm_ctx *op = crypto_skcipher_ctx(tfm);
+ struct sun8i_ce_dev *ce = op->ce;
+ struct sun8i_cipher_req_ctx *rctx = skcipher_request_ctx(areq);
+ struct skcipher_alg *alg = crypto_skcipher_alg(tfm);
+ struct sun8i_ce_alg_template *algt;
+ struct sun8i_ce_flow *chan;
+ struct ce_task *cet;
+ struct scatterlist *sg;
+ bool need_fallback = false;
+ unsigned int todo, len, offset, ivsize;
+ void *backup_iv = NULL;
+ int flow, i;
+ int nr_sgs = 0;
+ int nr_sgd = 0;
+ int err = 0;
+
+ algt = container_of(alg, struct sun8i_ce_alg_template, alg.skcipher);
+
+ dev_dbg(ce->dev, "%s %s %u %x IV(%p %u) key=%u\n", __func__,
+ crypto_tfm_alg_name(areq->base.tfm),
+ areq->cryptlen,
+ rctx->op_dir, areq->iv, crypto_skcipher_ivsize(tfm),
+ op->keylen);
+
+ if (sg_nents(areq->src) > MAX_SG || sg_nents(areq->dst) > MAX_SG)
+ need_fallback = true;
+
+ if (areq->cryptlen < crypto_skcipher_ivsize(tfm))
+ need_fallback = true;
+
+ if (areq->cryptlen == 0)
+ need_fallback = true;
+ if (areq->cryptlen % algt->alg.skcipher.base.cra_blocksize)
+ need_fallback = true;
+
+ sg = areq->src;
+ while (sg && !need_fallback) {
+ if (sg->length % 4 || !IS_ALIGNED(sg->offset, sizeof(u32))) {
+ need_fallback = true;
+ break;
+ }
+ sg = sg_next(sg);
+ }
+ sg = areq->dst;
+ while (sg && !need_fallback) {
+ if (sg->length % 4 || !IS_ALIGNED(sg->offset, sizeof(u32))) {
+ need_fallback = true;
+ break;
+ }
+ sg = sg_next(sg);
+ }
+
+#ifdef CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG
+ algt->stat_req++;
+#endif
+
+ if (need_fallback) {
+ SYNC_SKCIPHER_REQUEST_ON_STACK(subreq, op->fallback_tfm);
+#ifdef CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG
+ algt->stat_fb++;
+#endif
+ skcipher_request_set_sync_tfm(subreq, op->fallback_tfm);
+ skcipher_request_set_callback(subreq, areq->base.flags, NULL,
+ NULL);
+ skcipher_request_set_crypt(subreq, areq->src, areq->dst,
+ areq->cryptlen, areq->iv);
+ if (rctx->op_dir & CE_DECRYPTION)
+ err = crypto_skcipher_decrypt(subreq);
+ else
+ err = crypto_skcipher_encrypt(subreq);
+ skcipher_request_zero(subreq);
+ return err;
+ }
+
+ flow = rctx->flow;
+
+ chan = &ce->chanlist[flow];
+ mutex_lock(&chan->lock);
+
+ cet = chan->tl;
+ memset(cet, 0, sizeof(struct ce_task));
+
+ cet->t_id = flow;
+ cet->t_common_ctl = ce->variant->alg_cipher[algt->ce_algo_id];
+ cet->t_common_ctl |= rctx->op_dir | CE_COMM_INT;
+ cet->t_dlen = areq->cryptlen / 4;
+ /* CTS and recent CE (H6) need length in bytes, in word otherwise */
+ if (ce->variant->model == CE_v2)
+ cet->t_dlen = areq->cryptlen;
+
+ cet->t_sym_ctl = ce->variant->op_mode[algt->ce_blockmode];
+ len = op->keylen;
+ switch (len) {
+ case 128 / 8:
+ cet->t_sym_ctl |= CE_AES_128BITS;
+ break;
+ case 192 / 8:
+ cet->t_sym_ctl |= CE_AES_192BITS;
+ break;
+ case 256 / 8:
+ cet->t_sym_ctl |= CE_AES_256BITS;
+ break;
+ }
+
+ cet->t_asym_ctl = 0;
+
+ chan->op_mode = ce->variant->op_mode[algt->ce_blockmode];
+ chan->op_dir = rctx->op_dir;
+ chan->method = ce->variant->alg_cipher[algt->ce_algo_id];
+ chan->keylen = op->keylen;
+
+ cet->t_key = dma_map_single(ce->dev, op->key, op->keylen,
+ DMA_TO_DEVICE);
+ if (dma_mapping_error(ce->dev, cet->t_key)) {
+ dev_err(ce->dev, "Cannot DMA MAP KEY\n");
+ err = -EFAULT;
+ goto theend;
+ }
+
+ ivsize = crypto_skcipher_ivsize(tfm);
+ if (areq->iv && crypto_skcipher_ivsize(tfm) > 0) {
+ chan->ivlen = ivsize;
+ chan->bounce_iv = kzalloc(ivsize, GFP_KERNEL | GFP_DMA);
+ if (!chan->bounce_iv) {
+ err = -ENOMEM;
+ goto theend_key;
+ }
+ if (rctx->op_dir & CE_DECRYPTION) {
+ backup_iv = kzalloc(ivsize, GFP_KERNEL);
+ if (!backup_iv) {
+ err = -ENOMEM;
+ goto theend_key;
+ }
+ offset = areq->cryptlen - ivsize;
+ scatterwalk_map_and_copy(backup_iv, areq->src, offset,
+ ivsize, 0);
+ }
+ memcpy(chan->bounce_iv, areq->iv, ivsize);
+ }
+
+ if (areq->src == areq->dst) {
+ nr_sgs = dma_map_sg(ce->dev, areq->src, sg_nents(areq->src),
+ DMA_BIDIRECTIONAL);
+ if (nr_sgs <= 0 || nr_sgs > MAX_SG) {
+ dev_err(ce->dev, "Invalid sg number %d\n", nr_sgs);
+ err = -EINVAL;
+ goto theend_iv;
+ }
+ nr_sgd = nr_sgs;
+ } else {
+ nr_sgs = dma_map_sg(ce->dev, areq->src, sg_nents(areq->src),
+ DMA_TO_DEVICE);
+ if (nr_sgs <= 0 || nr_sgs > MAX_SG) {
+ dev_err(ce->dev, "Invalid sg number %d\n", nr_sgs);
+ err = -EINVAL;
+ goto theend_iv;
+ }
+ nr_sgd = dma_map_sg(ce->dev, areq->dst, sg_nents(areq->dst),
+ DMA_FROM_DEVICE);
+ if (nr_sgd <= 0 || nr_sgd > MAX_SG) {
+ dev_err(ce->dev, "Invalid sg number %d\n", nr_sgd);
+ err = -EINVAL;
+ goto theend_sgs;
+ }
+ }
+
+ len = areq->cryptlen;
+ for_each_sg(areq->src, sg, nr_sgs, i) {
+ cet->t_src[i].addr = sg_dma_address(sg);
+ todo = min(len, sg_dma_len(sg));
+ cet->t_src[i].len = todo / 4;
+ dev_dbg(ce->dev, "%s total=%u SG(%d %u off=%d) todo=%u\n", __func__,
+ areq->cryptlen, i, cet->t_src[i].len, sg->offset, todo);
+ len -= todo;
+ }
+ if (len > 0)
+ dev_err(ce->dev, "remaining len %d\n", len);
+
+ len = areq->cryptlen;
+ for_each_sg(areq->dst, sg, nr_sgd, i) {
+ cet->t_dst[i].addr = sg_dma_address(sg);
+ todo = min(len, sg_dma_len(sg));
+ cet->t_dst[i].len = todo / 4;
+ dev_dbg(ce->dev, "%s total=%u SG(%d %u off=%d) todo=%u\n", __func__,
+ areq->cryptlen, i, cet->t_dst[i].len, sg->offset, todo);
+ len -= todo;
+ }
+ if (len > 0)
+ dev_err(ce->dev, "remaining len %d\n", len);
+
+ chan->timeout = areq->cryptlen;
+ err = sun8i_ce_run_task(ce, flow, "cipher");
+ if (err)
+ dev_err(ce->dev, "Error with len=%u\n", areq->cryptlen);
+
+theend_sgs:
+ if (areq->src == areq->dst) {
+ dma_unmap_sg(ce->dev, areq->src, nr_sgs, DMA_BIDIRECTIONAL);
+ } else {
+ if (nr_sgs > 0)
+ dma_unmap_sg(ce->dev, areq->src, nr_sgs, DMA_TO_DEVICE);
+ dma_unmap_sg(ce->dev, areq->dst, nr_sgd, DMA_FROM_DEVICE);
+ }
+
+theend_iv:
+ if (areq->iv && ivsize > 0) {
+ offset = areq->cryptlen - ivsize;
+ if (rctx->op_dir & CE_DECRYPTION) {
+ memcpy(areq->iv, backup_iv, ivsize);
+ kzfree(backup_iv);
+ } else {
+ scatterwalk_map_and_copy(areq->iv, areq->dst, offset,
+ ivsize, 0);
+ }
+ kfree(chan->bounce_iv);
+ }
+
+theend_key:
+ dma_unmap_single(ce->dev, cet->t_key, op->keylen, DMA_TO_DEVICE);
+
+theend:
+ mutex_unlock(&chan->lock);
+
+ return err;
+}
+
+static int handle_cipher_request(struct crypto_engine *engine, void *areq)
+{
+ int err;
+ struct skcipher_request *breq = container_of(areq, struct skcipher_request, base);
+
+ err = sun8i_ce_cipher(breq);
+ crypto_finalize_skcipher_request(engine, breq, err);
+
+ return 0;
+}
+
+int sun8i_ce_skdecrypt(struct skcipher_request *areq)
+{
+ struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(areq);
+ struct sun8i_cipher_tfm_ctx *op = crypto_skcipher_ctx(tfm);
+ struct sun8i_cipher_req_ctx *rctx = skcipher_request_ctx(areq);
+ int e = sun8i_ce_get_engine_number(op->ce);
+ struct crypto_engine *engine = op->ce->chanlist[e].engine;
+
+ rctx->op_dir = CE_DECRYPTION;
+ rctx->flow = e;
+
+ return crypto_transfer_skcipher_request_to_engine(engine, areq);
+}
+
+int sun8i_ce_skencrypt(struct skcipher_request *areq)
+{
+ struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(areq);
+ struct sun8i_cipher_tfm_ctx *op = crypto_skcipher_ctx(tfm);
+ struct sun8i_cipher_req_ctx *rctx = skcipher_request_ctx(areq);
+ int e = sun8i_ce_get_engine_number(op->ce);
+ struct crypto_engine *engine = op->ce->chanlist[e].engine;
+
+ rctx->op_dir = CE_ENCRYPTION;
+ rctx->flow = e;
+
+ return crypto_transfer_skcipher_request_to_engine(engine, areq);
+}
+
+int sun8i_ce_cipher_init(struct crypto_tfm *tfm)
+{
+ struct sun8i_cipher_tfm_ctx *op = crypto_tfm_ctx(tfm);
+ struct sun8i_ce_alg_template *algt;
+ const char *name = crypto_tfm_alg_name(tfm);
+ struct crypto_skcipher *sktfm = __crypto_skcipher_cast(tfm);
+ struct skcipher_alg *alg = crypto_skcipher_alg(sktfm);
+
+ memset(op, 0, sizeof(struct sun8i_cipher_tfm_ctx));
+
+ algt = container_of(alg, struct sun8i_ce_alg_template, alg.skcipher);
+ op->ce = algt->ce;
+
+ sktfm->reqsize = sizeof(struct sun8i_cipher_req_ctx);
+
+ op->fallback_tfm = crypto_alloc_sync_skcipher(name, 0, CRYPTO_ALG_NEED_FALLBACK);
+ if (IS_ERR(op->fallback_tfm)) {
+ dev_err(op->ce->dev, "ERROR: Cannot allocate fallback for %s %ld\n",
+ name, PTR_ERR(op->fallback_tfm));
+ return PTR_ERR(op->fallback_tfm);
+ }
+
+ dev_info(op->ce->dev, "Fallback is %s\n", crypto_tfm_alg_driver_name(crypto_skcipher_tfm(&op->fallback_tfm->base)));
+
+ op->enginectx.op.do_one_request = handle_cipher_request;
+ op->enginectx.op.prepare_request = NULL;
+ op->enginectx.op.unprepare_request = NULL;
+
+ return 0;
+}
+
+void sun8i_ce_cipher_exit(struct crypto_tfm *tfm)
+{
+ struct sun8i_cipher_tfm_ctx *op = crypto_tfm_ctx(tfm);
+
+ if (op->key) {
+ memzero_explicit(op->key, op->keylen);
+ kfree(op->key);
+ }
+ crypto_free_sync_skcipher(op->fallback_tfm);
+}
+
+int sun8i_ce_aes_setkey(struct crypto_skcipher *tfm, const u8 *key,
+ unsigned int keylen)
+{
+ struct sun8i_cipher_tfm_ctx *op = crypto_skcipher_ctx(tfm);
+ struct sun8i_ce_dev *ce = op->ce;
+
+ switch (keylen) {
+ case 128 / 8:
+ break;
+ case 192 / 8:
+ break;
+ case 256 / 8:
+ break;
+ default:
+ dev_dbg(ce->dev, "ERROR: Invalid keylen %u\n", keylen);
+ crypto_skcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
+ return -EINVAL;
+ }
+ if (op->key) {
+ memzero_explicit(op->key, op->keylen);
+ kfree(op->key);
+ }
+ op->keylen = keylen;
+ op->key = kmalloc(keylen, GFP_KERNEL | GFP_DMA);
+ if (!op->key)
+ return -ENOMEM;
+ memcpy(op->key, key, keylen);
+
+ crypto_sync_skcipher_clear_flags(op->fallback_tfm, CRYPTO_TFM_REQ_MASK);
+ crypto_sync_skcipher_set_flags(op->fallback_tfm, tfm->base.crt_flags & CRYPTO_TFM_REQ_MASK);
+
+ return crypto_sync_skcipher_setkey(op->fallback_tfm, key, keylen);
+}
+
+int sun8i_ce_des3_setkey(struct crypto_skcipher *tfm, const u8 *key,
+ unsigned int keylen)
+{
+ struct sun8i_cipher_tfm_ctx *op = crypto_skcipher_ctx(tfm);
+ int err;
+
+ err = verify_skcipher_des3_key(tfm, key);
+ if (err)
+ return err;
+
+ if (op->key) {
+ memzero_explicit(op->key, op->keylen);
+ kfree(op->key);
+ }
+ op->keylen = keylen;
+ op->key = kmalloc(keylen, GFP_KERNEL | GFP_DMA);
+ if (!op->key)
+ return -ENOMEM;
+ memcpy(op->key, key, keylen);
+
+ crypto_sync_skcipher_clear_flags(op->fallback_tfm, CRYPTO_TFM_REQ_MASK);
+ crypto_sync_skcipher_set_flags(op->fallback_tfm, tfm->base.crt_flags & CRYPTO_TFM_REQ_MASK);
+
+ return crypto_sync_skcipher_setkey(op->fallback_tfm, key, keylen);
+}
diff --git a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
new file mode 100644
index 000000000000..c609b9943296
--- /dev/null
+++ b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce-core.c
@@ -0,0 +1,630 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * sun8i-ce-core.c - hardware cryptographic offloader for
+ * Allwinner H3/A64/H5/H2+/H6/R40 SoC
+ *
+ * Copyright (C) 2015-2019 Corentin Labbe <clabbe.montjoie@gmail.com>
+ *
+ * Core file which registers crypto algorithms supported by the CryptoEngine.
+ *
+ * You could find a link for the datasheet in Documentation/arm/sunxi/README
+ */
+#include <linux/clk.h>
+#include <linux/crypto.h>
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+#include <crypto/internal/skcipher.h>
+
+#include "sun8i-ce.h"
+
+static const struct ce_variant ce_h3_variant = {
+ .alg_cipher = { CE_ID_NOTSUPP, CE_ALG_AES, CE_ALG_DES, CE_ALG_3DES,
+ CE_ID_NOTSUPP,
+ },
+ .op_mode = { CE_ID_NOTSUPP, CE_OP_ECB, CE_OP_CBC
+ },
+ .intreg = CE_ISR,
+ .maxflow = 4,
+ .ce_clks = {
+ { "ahb", 200000000 },
+ { "mod", 48000000 },
+ }
+};
+
+static const struct ce_variant ce_h5_variant = {
+ .alg_cipher = { CE_ID_NOTSUPP, CE_ALG_AES, CE_ALG_DES, CE_ALG_3DES,
+ CE_ID_NOTSUPP,
+ },
+ .op_mode = { CE_ID_NOTSUPP, CE_OP_ECB, CE_OP_CBC
+ },
+ .intreg = CE_ISR,
+ .maxflow = 4,
+ .ce_clks = {
+ { "ahb", 200000000 },
+ { "mod", 300000000 },
+ }
+};
+
+static const struct ce_variant ce_h6_variant = {
+ .alg_cipher = { CE_ID_NOTSUPP, CE_ALG_AES, CE_ALG_DES, CE_ALG_3DES,
+ CE_ALG_RAES,
+ },
+ .op_mode = { CE_ID_NOTSUPP, CE_OP_ECB, CE_OP_CBC
+ },
+ .model = CE_v2,
+ .intreg = CE_ISR,
+ .maxflow = 4,
+ .ce_clks = {
+ { "ahb", 200000000 },
+ { "mod", 300000000 },
+ { "mbus", 400000000 },
+ }
+};
+
+static const struct ce_variant ce_a64_variant = {
+ .alg_cipher = { CE_ID_NOTSUPP, CE_ALG_AES, CE_ALG_DES, CE_ALG_3DES,
+ CE_ID_NOTSUPP,
+ },
+ .op_mode = { CE_ID_NOTSUPP, CE_OP_ECB, CE_OP_CBC
+ },
+ .intreg = CE_ISR,
+ .maxflow = 4,
+ .ce_clks = {
+ { "ahb", 200000000 },
+ { "mod", 300000000 },
+ }
+};
+
+static const struct ce_variant ce_r40_variant = {
+ .alg_cipher = { CE_ID_NOTSUPP, CE_ALG_AES, CE_ALG_DES, CE_ALG_3DES,
+ CE_ID_NOTSUPP,
+ },
+ .op_mode = { CE_ID_NOTSUPP, CE_OP_ECB, CE_OP_CBC
+ },
+ .intreg = CE_ISR,
+ .maxflow = 4,
+ .ce_clks = {
+ { "ahb", 200000000 },
+ { "mod", 300000000 },
+ }
+};
+
+int sun8i_ce_get_engine_number(struct sun8i_ce_dev *ce)
+{
+ return atomic_inc_return(&ce->flow) % ce->variant->maxflow;
+}
+
+int sun8i_ce_run_task(struct sun8i_ce_dev *ce, int flow, const char *name)
+{
+ u32 v;
+ int err = 0;
+ struct ce_task *cet = ce->chanlist[flow].tl;
+
+ if (ce->chanlist[flow].bounce_iv) {
+ cet->t_iv = dma_map_single(ce->dev,
+ ce->chanlist[flow].bounce_iv,
+ ce->chanlist[flow].ivlen,
+ DMA_TO_DEVICE);
+ if (dma_mapping_error(ce->dev, cet->t_iv)) {
+ dev_err(ce->dev, "Cannot DMA MAP IV\n");
+ return -EFAULT;
+ }
+ }
+
+#ifdef CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG
+ ce->chanlist[flow].stat_req++;
+#endif
+
+ mutex_lock(&ce->mlock);
+
+ v = readl(ce->base + CE_ICR);
+ v |= 1 << flow;
+ writel(v, ce->base + CE_ICR);
+
+ reinit_completion(&ce->chanlist[flow].complete);
+ writel(ce->chanlist[flow].t_phy, ce->base + CE_TDQ);
+
+ ce->chanlist[flow].status = 0;
+ /* Be sure all data is written before enabling the task */
+ wmb();
+
+ v = 1 | (ce->chanlist[flow].tl->t_common_ctl & 0x7F) << 8;
+ writel(v, ce->base + CE_TLR);
+ mutex_unlock(&ce->mlock);
+
+ wait_for_completion_interruptible_timeout(&ce->chanlist[flow].complete,
+ msecs_to_jiffies(ce->chanlist[flow].timeout));
+
+ if (ce->chanlist[flow].status == 0) {
+ dev_err(ce->dev, "DMA timeout for %s\n", name);
+ err = -EFAULT;
+ }
+ /* No need to lock for this read, the channel is locked so
+ * nothing could modify the error value for this channel
+ */
+ v = readl(ce->base + CE_ESR);
+ if (v) {
+ v >>= (flow * 4);
+ v &= 0xFF;
+ if (v) {
+ dev_err(ce->dev, "CE ERROR: %x for flow %x\n", v, flow);
+ err = -EFAULT;
+ }
+ if (v & CE_ERR_ALGO_NOTSUP)
+ dev_err(ce->dev, "CE ERROR: algorithm not supported\n");
+ if (v & CE_ERR_DATALEN)
+ dev_err(ce->dev, "CE ERROR: data length error\n");
+ if (v & CE_ERR_KEYSRAM)
+ dev_err(ce->dev, "CE ERROR: keysram access error for AES\n");
+ if (v & CE_ERR_ADDR_INVALID)
+ dev_err(ce->dev, "CE ERROR: address invalid\n");
+ }
+
+ if (ce->chanlist[flow].bounce_iv) {
+ dma_unmap_single(ce->dev, cet->t_iv,
+ ce->chanlist[flow].ivlen,
+ DMA_TO_DEVICE);
+ }
+
+ return err;
+}
+
+static irqreturn_t ce_irq_handler(int irq, void *data)
+{
+ struct sun8i_ce_dev *ce = (struct sun8i_ce_dev *)data;
+ int flow = 0;
+ u32 p;
+
+ p = readl(ce->base + ce->variant->intreg);
+ for (flow = 0; flow < ce->variant->maxflow; flow++) {
+ if (p & (BIT(flow))) {
+ writel(BIT(flow), ce->base + ce->variant->intreg);
+ ce->chanlist[flow].status = 1;
+ complete(&ce->chanlist[flow].complete);
+ }
+ }
+
+ return IRQ_HANDLED;
+}
+
+static struct sun8i_ce_alg_template ce_algs[] = {
+{
+ .type = CRYPTO_ALG_TYPE_SKCIPHER,
+ .ce_algo_id = CE_ID_CIPHER_AES,
+ .ce_blockmode = CE_ID_OP_CBC,
+ .alg.skcipher = {
+ .base = {
+ .cra_name = "cbc(aes)",
+ .cra_driver_name = "cbc-aes-sun8i-ce",
+ .cra_priority = 400,
+ .cra_blocksize = AES_BLOCK_SIZE,
+ .cra_flags = CRYPTO_ALG_TYPE_SKCIPHER |
+ CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
+ .cra_ctxsize = sizeof(struct sun8i_cipher_tfm_ctx),
+ .cra_module = THIS_MODULE,
+ .cra_alignmask = 0xf,
+ .cra_init = sun8i_ce_cipher_init,
+ .cra_exit = sun8i_ce_cipher_exit,
+ },
+ .min_keysize = AES_MIN_KEY_SIZE,
+ .max_keysize = AES_MAX_KEY_SIZE,
+ .ivsize = AES_BLOCK_SIZE,
+ .setkey = sun8i_ce_aes_setkey,
+ .encrypt = sun8i_ce_skencrypt,
+ .decrypt = sun8i_ce_skdecrypt,
+ }
+},
+{
+ .type = CRYPTO_ALG_TYPE_SKCIPHER,
+ .ce_algo_id = CE_ID_CIPHER_AES,
+ .ce_blockmode = CE_ID_OP_ECB,
+ .alg.skcipher = {
+ .base = {
+ .cra_name = "ecb(aes)",
+ .cra_driver_name = "ecb-aes-sun8i-ce",
+ .cra_priority = 400,
+ .cra_blocksize = AES_BLOCK_SIZE,
+ .cra_flags = CRYPTO_ALG_TYPE_SKCIPHER |
+ CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
+ .cra_ctxsize = sizeof(struct sun8i_cipher_tfm_ctx),
+ .cra_module = THIS_MODULE,
+ .cra_alignmask = 0xf,
+ .cra_init = sun8i_ce_cipher_init,
+ .cra_exit = sun8i_ce_cipher_exit,
+ },
+ .min_keysize = AES_MIN_KEY_SIZE,
+ .max_keysize = AES_MAX_KEY_SIZE,
+ .setkey = sun8i_ce_aes_setkey,
+ .encrypt = sun8i_ce_skencrypt,
+ .decrypt = sun8i_ce_skdecrypt,
+ }
+},
+{
+ .type = CRYPTO_ALG_TYPE_SKCIPHER,
+ .ce_algo_id = CE_ID_CIPHER_DES3,
+ .ce_blockmode = CE_ID_OP_CBC,
+ .alg.skcipher = {
+ .base = {
+ .cra_name = "cbc(des3_ede)",
+ .cra_driver_name = "cbc-des3-sun8i-ce",
+ .cra_priority = 400,
+ .cra_blocksize = DES3_EDE_BLOCK_SIZE,
+ .cra_flags = CRYPTO_ALG_TYPE_SKCIPHER |
+ CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
+ .cra_ctxsize = sizeof(struct sun8i_cipher_tfm_ctx),
+ .cra_module = THIS_MODULE,
+ .cra_alignmask = 0xf,
+ .cra_init = sun8i_ce_cipher_init,
+ .cra_exit = sun8i_ce_cipher_exit,
+ },
+ .min_keysize = DES3_EDE_KEY_SIZE,
+ .max_keysize = DES3_EDE_KEY_SIZE,
+ .ivsize = DES3_EDE_BLOCK_SIZE,
+ .setkey = sun8i_ce_des3_setkey,
+ .encrypt = sun8i_ce_skencrypt,
+ .decrypt = sun8i_ce_skdecrypt,
+ }
+},
+{
+ .type = CRYPTO_ALG_TYPE_SKCIPHER,
+ .ce_algo_id = CE_ID_CIPHER_DES3,
+ .ce_blockmode = CE_ID_OP_ECB,
+ .alg.skcipher = {
+ .base = {
+ .cra_name = "ecb(des3_ede)",
+ .cra_driver_name = "ecb-des3-sun8i-ce",
+ .cra_priority = 400,
+ .cra_blocksize = DES3_EDE_BLOCK_SIZE,
+ .cra_flags = CRYPTO_ALG_TYPE_SKCIPHER |
+ CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
+ .cra_ctxsize = sizeof(struct sun8i_cipher_tfm_ctx),
+ .cra_module = THIS_MODULE,
+ .cra_alignmask = 0xf,
+ .cra_init = sun8i_ce_cipher_init,
+ .cra_exit = sun8i_ce_cipher_exit,
+ },
+ .min_keysize = DES3_EDE_KEY_SIZE,
+ .max_keysize = DES3_EDE_KEY_SIZE,
+ .setkey = sun8i_ce_des3_setkey,
+ .encrypt = sun8i_ce_skencrypt,
+ .decrypt = sun8i_ce_skdecrypt,
+ }
+},
+};
+
+#ifdef CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG
+static int sun8i_ce_dbgfs_read(struct seq_file *seq, void *v)
+{
+ struct sun8i_ce_dev *ce = seq->private;
+ int i;
+
+ for (i = 0; i < ce->variant->maxflow; i++)
+ seq_printf(seq, "Channel %d: req %lu\n", i, ce->chanlist[i].stat_req);
+
+ for (i = 0; i < ARRAY_SIZE(ce_algs); i++) {
+ if (!ce_algs[i].ce)
+ continue;
+ switch (ce_algs[i].type) {
+ case CRYPTO_ALG_TYPE_SKCIPHER:
+ seq_printf(seq, "%s %s %lu %lu\n",
+ ce_algs[i].alg.skcipher.base.cra_driver_name,
+ ce_algs[i].alg.skcipher.base.cra_name,
+ ce_algs[i].stat_req, ce_algs[i].stat_fb);
+ break;
+ }
+ }
+ return 0;
+}
+
+static int sun8i_ce_dbgfs_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, sun8i_ce_dbgfs_read, inode->i_private);
+}
+
+static const struct file_operations sun8i_ce_debugfs_fops = {
+ .owner = THIS_MODULE,
+ .open = sun8i_ce_dbgfs_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+};
+#endif
+
+static int sun8i_ce_probe(struct platform_device *pdev)
+{
+ struct resource *res;
+ u32 v;
+ int err, i, ce_method, id, irq;
+ unsigned long cr;
+ struct sun8i_ce_dev *ce;
+
+ if (!pdev->dev.of_node)
+ return -ENODEV;
+
+ ce = devm_kzalloc(&pdev->dev, sizeof(*ce), GFP_KERNEL);
+ if (!ce)
+ return -ENOMEM;
+
+ ce->variant = of_device_get_match_data(&pdev->dev);
+ if (!ce->variant) {
+ dev_err(&pdev->dev, "Missing Crypto Engine variant\n");
+ return -EINVAL;
+ }
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ ce->base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(ce->base)) {
+ err = PTR_ERR(ce->base);
+ dev_err(&pdev->dev, "Cannot request MMIO err=%d\n", err);
+ return err;
+ }
+
+ for (i = 0; i < CE_MAX_CLOCKS; i++) {
+ if (!ce->variant->ce_clks[i].name)
+ continue;
+ dev_info(&pdev->dev, "Get %s clock\n", ce->variant->ce_clks[i].name);
+ ce->ceclks[i] = devm_clk_get(&pdev->dev, ce->variant->ce_clks[i].name);
+ if (IS_ERR(ce->ceclks[i])) {
+ err = PTR_ERR(ce->ceclks[i]);
+ dev_err(&pdev->dev, "Cannot get %s CE clock err=%d\n",
+ ce->variant->ce_clks[i].name, err);
+ }
+ cr = clk_get_rate(ce->ceclks[i]);
+ if (ce->variant->ce_clks[i].freq) {
+ dev_info(&pdev->dev, "Set %s clock to %lu (%lu Mhz) from %lu (%lu Mhz)\n",
+ ce->variant->ce_clks[i].name,
+ ce->variant->ce_clks[i].freq,
+ ce->variant->ce_clks[i].freq / 1000000,
+ cr,
+ cr / 1000000);
+ err = clk_set_rate(ce->ceclks[i], ce->variant->ce_clks[i].freq);
+ if (err)
+ dev_err(&pdev->dev, "Fail to set %s clk speed to %lu\n",
+ ce->variant->ce_clks[i].name,
+ ce->variant->ce_clks[i].freq);
+ } else {
+ dev_info(&pdev->dev, "%s run at %lu\n",
+ ce->variant->ce_clks[i].name, cr);
+ }
+ err = clk_prepare_enable(ce->ceclks[i]);
+ if (err) {
+ dev_err(&pdev->dev, "Cannot prepare_enable %s\n",
+ ce->variant->ce_clks[i].name);
+ return err;
+ }
+ }
+
+ /* Get Non Secure IRQ */
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0) {
+ dev_err(ce->dev, "Cannot get NS IRQ\n");
+ return irq;
+ }
+
+ err = devm_request_irq(&pdev->dev, irq, ce_irq_handler, 0,
+ "sun8i-ce-ns", ce);
+ if (err < 0) {
+ dev_err(ce->dev, "Cannot request NS IRQ\n");
+ return err;
+ }
+
+ ce->reset = devm_reset_control_get_optional(&pdev->dev, "ahb");
+ if (IS_ERR(ce->reset)) {
+ if (PTR_ERR(ce->reset) == -EPROBE_DEFER)
+ return PTR_ERR(ce->reset);
+ dev_info(&pdev->dev, "No reset control found\n");
+ ce->reset = NULL;
+ }
+
+ err = reset_control_deassert(ce->reset);
+ if (err) {
+ dev_err(&pdev->dev, "Cannot deassert reset control\n");
+ goto error_clk;
+ }
+
+ v = readl(ce->base + CE_CTR);
+ v >>= 16;
+ v &= 0x07;
+ dev_info(&pdev->dev, "CE_NS Die ID %x\n", v);
+
+ ce->dev = &pdev->dev;
+ platform_set_drvdata(pdev, ce);
+
+ mutex_init(&ce->mlock);
+
+ ce->chanlist = devm_kcalloc(ce->dev, ce->variant->maxflow,
+ sizeof(struct sun8i_ce_flow), GFP_KERNEL);
+ if (!ce->chanlist) {
+ err = -ENOMEM;
+ goto error_flow;
+ }
+
+ for (i = 0; i < ce->variant->maxflow; i++) {
+ init_completion(&ce->chanlist[i].complete);
+ mutex_init(&ce->chanlist[i].lock);
+
+ ce->chanlist[i].engine = crypto_engine_alloc_init(ce->dev, true);
+ if (!ce->chanlist[i].engine) {
+ dev_err(ce->dev, "Cannot allocate engine\n");
+ i--;
+ goto error_engine;
+ }
+ err = crypto_engine_start(ce->chanlist[i].engine);
+ if (err) {
+ dev_err(ce->dev, "Cannot start engine\n");
+ goto error_engine;
+ }
+ ce->chanlist[i].tl = dma_alloc_coherent(ce->dev,
+ sizeof(struct ce_task),
+ &ce->chanlist[i].t_phy,
+ GFP_KERNEL);
+ if (!ce->chanlist[i].tl) {
+ dev_err(ce->dev, "Cannot get DMA memory for task %d\n",
+ i);
+ err = -ENOMEM;
+ goto error_engine;
+ }
+ }
+
+#ifdef CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG
+ ce->dbgfs_dir = debugfs_create_dir("sun8i-ce", NULL);
+ if (IS_ERR_OR_NULL(ce->dbgfs_dir)) {
+ dev_err(ce->dev, "Fail to create debugfs dir");
+ err = -ENOMEM;
+ goto error_engine;
+ }
+ ce->dbgfs_stats = debugfs_create_file("stats", 0444,
+ ce->dbgfs_dir, ce,
+ &sun8i_ce_debugfs_fops);
+ if (IS_ERR_OR_NULL(ce->dbgfs_stats)) {
+ dev_err(ce->dev, "Fail to create debugfs stat");
+ err = -ENOMEM;
+ goto error_debugfs;
+ }
+#endif
+ for (i = 0; i < ARRAY_SIZE(ce_algs); i++) {
+ ce_algs[i].ce = ce;
+ switch (ce_algs[i].type) {
+ case CRYPTO_ALG_TYPE_SKCIPHER:
+ id = ce_algs[i].ce_algo_id;
+ ce_method = ce->variant->alg_cipher[id];
+ if (ce_method == CE_ID_NOTSUPP) {
+ dev_info(ce->dev,
+ "DEBUG: Algo of %s not supported\n",
+ ce_algs[i].alg.skcipher.base.cra_name);
+ ce_algs[i].ce = NULL;
+ break;
+ }
+ id = ce_algs[i].ce_blockmode;
+ ce_method = ce->variant->op_mode[id];
+ if (ce_method == CE_ID_NOTSUPP) {
+ dev_info(ce->dev, "DEBUG: Blockmode of %s not supported\n",
+ ce_algs[i].alg.skcipher.base.cra_name);
+ ce_algs[i].ce = NULL;
+ break;
+ }
+ dev_info(ce->dev, "DEBUG: Register %s\n",
+ ce_algs[i].alg.skcipher.base.cra_name);
+ err = crypto_register_skcipher(&ce_algs[i].alg.skcipher);
+ if (err) {
+ dev_err(ce->dev, "Fail to register %s\n",
+ ce_algs[i].alg.skcipher.base.cra_name);
+ ce_algs[i].ce = NULL;
+ goto error_alg;
+ }
+ break;
+ default:
+ dev_err(ce->dev, "ERROR: tryed to register an unknown algo\n");
+ }
+ }
+
+ return 0;
+error_alg:
+ i--;
+ for (; i >= 0; i--) {
+ switch (ce_algs[i].type) {
+ case CRYPTO_ALG_TYPE_SKCIPHER:
+ if (ce_algs[i].ce)
+ crypto_unregister_skcipher(&ce_algs[i].alg.skcipher);
+ break;
+ }
+ }
+#ifdef CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG
+error_debugfs:
+ debugfs_remove_recursive(ce->dbgfs_dir);
+#endif
+ i = ce->variant->maxflow;
+error_engine:
+ while (i >= 0) {
+ crypto_engine_exit(ce->chanlist[i].engine);
+ if (ce->chanlist[i].tl)
+ dma_free_coherent(ce->dev, sizeof(struct ce_task),
+ ce->chanlist[i].tl,
+ ce->chanlist[i].t_phy);
+ i--;
+ }
+error_flow:
+ reset_control_assert(ce->reset);
+error_clk:
+ for (i = 0; i < CE_MAX_CLOCKS; i++)
+ clk_disable_unprepare(ce->ceclks[i]);
+ return err;
+}
+
+static int sun8i_ce_remove(struct platform_device *pdev)
+{
+ int i, timeout;
+ struct sun8i_ce_dev *ce = platform_get_drvdata(pdev);
+
+ for (i = 0; i < ARRAY_SIZE(ce_algs); i++) {
+ switch (ce_algs[i].type) {
+ case CRYPTO_ALG_TYPE_SKCIPHER:
+ if (ce_algs[i].ce) {
+ dev_dbg(ce->dev, "Unregister %d %s\n", i,
+ ce_algs[i].alg.skcipher.base.cra_name);
+ crypto_unregister_skcipher(&ce_algs[i].alg.skcipher);
+ }
+ break;
+ }
+ }
+
+#ifdef CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG
+ debugfs_remove_recursive(ce->dbgfs_dir);
+#endif
+
+ for (i = 0; i < ce->variant->maxflow; i++) {
+ crypto_engine_exit(ce->chanlist[i].engine);
+ timeout = 0;
+ while (mutex_is_locked(&ce->chanlist[i].lock) && timeout < 10) {
+ dev_info(ce->dev, "Wait for %d %d\n", i, timeout);
+ timeout++;
+ msleep(20);
+ }
+ dma_free_coherent(ce->dev, sizeof(struct ce_task),
+ ce->chanlist[i].tl,
+ ce->chanlist[i].t_phy);
+ }
+
+ reset_control_assert(ce->reset);
+ for (i = 0; i < CE_MAX_CLOCKS; i++)
+ clk_disable_unprepare(ce->ceclks[i]);
+ return 0;
+}
+
+static const struct of_device_id sun8i_ce_crypto_of_match_table[] = {
+ { .compatible = "allwinner,sun8i-h3-crypto",
+ .data = &ce_h3_variant },
+ { .compatible = "allwinner,sun50i-h5-crypto",
+ .data = &ce_h5_variant },
+ { .compatible = "allwinner,sun50i-h6-crypto",
+ .data = &ce_h6_variant },
+ { .compatible = "allwinner,sun50i-a64-crypto",
+ .data = &ce_a64_variant },
+ { .compatible = "allwinner,sun8i-r40-crypto",
+ .data = &ce_r40_variant },
+ {}
+};
+MODULE_DEVICE_TABLE(of, sun8i_ce_crypto_of_match_table);
+
+static struct platform_driver sun8i_ce_driver = {
+ .probe = sun8i_ce_probe,
+ .remove = sun8i_ce_remove,
+ .driver = {
+ .name = "sun8i-ce",
+ .of_match_table = sun8i_ce_crypto_of_match_table,
+ },
+};
+
+module_platform_driver(sun8i_ce_driver);
+
+MODULE_DESCRIPTION("Allwinner Crypto Engine cryptographic offloader");
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Corentin Labbe <clabbe.montjoie@gmail.com>");
diff --git a/drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h
new file mode 100644
index 000000000000..fe51f9569fa0
--- /dev/null
+++ b/drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h
@@ -0,0 +1,256 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * sun8i-ce.h - hardware cryptographic offloader for
+ * Allwinner H3/A64/H5/H2+/H6 SoC
+ *
+ * Copyright (C) 2016-2019 Corentin LABBE <clabbe.montjoie@gmail.com>
+ */
+#include <crypto/aes.h>
+#include <crypto/des.h>
+#include <crypto/engine.h>
+#include <crypto/skcipher.h>
+#include <linux/atomic.h>
+#include <linux/debugfs.h>
+#include <linux/crypto.h>
+
+#define MAX_SG 8
+
+#define CE_STD 0
+#define CE_v2 1
+
+#define CE_MAX_CLOCKS 3
+
+/* CE Registers */
+#define CE_TDQ 0x00
+#define CE_CTR 0x04
+#define CE_ICR 0x08
+#define CE_ISR 0x0C
+#define CE_TLR 0x10
+#define CE_TSR 0x14
+#define CE_ESR 0x18
+#define CE_CSSGR 0x1C
+#define CE_CDSGR 0x20
+#define CE_CSAR 0x24
+#define CE_CDAR 0x28
+#define CE_TPR 0x2C
+
+/* Used in struct ce_task */
+/* ce_task common */
+#define CE_ENCRYPTION 0
+#define CE_DECRYPTION BIT(8)
+
+#define CE_COMM_INT BIT(31)
+
+/* ce_task symmetric */
+#define CE_AES_128BITS 0
+#define CE_AES_192BITS 1
+#define CE_AES_256BITS 2
+
+#define CE_OP_ECB 0
+#define CE_OP_CBC (1 << 8)
+
+#define CE_ALG_AES 0
+#define CE_ALG_DES 1
+#define CE_ALG_3DES 2
+#define CE_ALG_RAES 48
+
+/* Used in ce_variant */
+#define CE_ID_NOTSUPP 0xFF
+
+#define CE_ID_CIPHER_AES 1
+#define CE_ID_CIPHER_DES 2
+#define CE_ID_CIPHER_DES3 3
+#define CE_ID_CIPHER_RAES 4
+#define CE_ID_CIPHER_MAX 5
+
+#define CE_ID_OP_ECB 1
+#define CE_ID_OP_CBC 2
+#define CE_ID_OP_MAX 3
+
+/* Used in CE registers */
+#define CE_ERR_ALGO_NOTSUP BIT(0)
+#define CE_ERR_DATALEN BIT(1)
+#define CE_ERR_KEYSRAM BIT(2)
+#define CE_ERR_ADDR_INVALID BIT(5)
+#define CE_ERR_KEYLADDER BIT(6)
+
+/*
+ * struct ce_clock - Describe clocks used by sun8i-ce
+ * @name: Name of clock needed by this variant
+ * @freq: Maximum frequency for each clock
+ */
+struct ce_clock {
+ const char *name;
+ unsigned long freq;
+};
+
+/*
+ * struct ce_variant - Describe CE capability for each variant hardware
+ * @alg_cipher: list of supported ciphers. for each CE_ID_ this will give the
+ * coresponding CE_ALG_XXX/SS_ALG_XXX value
+ * @op_mode: list of supported block modes
+ * @model: The minor variant CE_STD/CE_SS/CE_v2
+ * @intreg: reg offset for Interrupt register
+ * @maxflow: Numbers of flow for the current engine
+ */
+struct ce_variant {
+ char alg_cipher[CE_ID_CIPHER_MAX];
+ u32 op_mode[CE_ID_OP_MAX];
+ int model;
+ u32 intreg;
+ unsigned int maxflow;
+ struct ce_clock ce_clks[CE_MAX_CLOCKS];
+};
+
+struct sginfo {
+ u32 addr;
+ u32 len;
+} __packed;
+
+/*
+ * struct ce_task - CE Task descriptor
+ * The structure of this descriptor could be found in the datasheet
+ */
+struct ce_task {
+ u32 t_id;
+ u32 t_common_ctl;
+ u32 t_sym_ctl;
+ u32 t_asym_ctl;
+ u32 t_key;
+ u32 t_iv;
+ u32 t_ctr;
+ u32 t_dlen;
+ struct sginfo t_src[MAX_SG];
+ struct sginfo t_dst[MAX_SG];
+ u32 next;
+ u32 reserved[3];
+} __packed __aligned(8);
+
+/*
+ * struct sun8i_ce_flow - Information used by each flow
+ * @lock: lock protecting access of sun8i_ce_flow
+ * @engine: ptr to the crypto_engine for this flow
+ * @bounce_iv: buffer which contain the IV
+ * @ivlen: size of bounce_iv
+ * @keylen: keylen for this flow operation
+ * @complete: completion for the current task on this flow
+ * @status: set to 1 by interrupt if task is done
+ * @method: current method for flow
+ * @op_dir: direction (encrypt vs decrypt) of this flow
+ * @op_mode: op_mode for this flow
+ * @t_phy: Physical address of task
+ * @tl: pointer to the current ce_task for this flow
+ * @stat_req: number of request done by this flow
+ */
+struct sun8i_ce_flow {
+ struct mutex lock;
+ struct crypto_engine *engine;
+ void *bounce_iv;
+ unsigned int ivlen;
+ unsigned int keylen;
+ struct completion complete;
+ int status;
+ u32 method;
+ u32 op_dir;
+ u32 op_mode;
+ dma_addr_t t_phy;
+ int timeout;
+ struct ce_task *tl;
+#ifdef CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG
+ unsigned long stat_req;
+#endif
+};
+
+/*
+ * struct sun8i_ce_dev - main container for all this driver information
+ * @base: base address of SS/CE
+ * @ceclks: clocks used by SS/CE
+ * @reset: pointer to reset controller
+ * @dev: the platform device
+ * @mlock: Control access to device registers
+ * @chanlist: array of all flow
+ * @flow: flow to use in next request
+ * @variant: pointer to variant specific data
+ * @dbgfs_dir: Debugfs dentry for statistic directory
+ * @dbgfs_stats: Debugfs dentry for statistic counters
+ */
+struct sun8i_ce_dev {
+ void __iomem *base;
+ struct clk *ceclks[CE_MAX_CLOCKS];
+ struct reset_control *reset;
+ struct device *dev;
+ struct mutex mlock;
+ struct sun8i_ce_flow *chanlist;
+ atomic_t flow;
+ const struct ce_variant *variant;
+#ifdef CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG
+ struct dentry *dbgfs_dir;
+ struct dentry *dbgfs_stats;
+#endif
+};
+
+/*
+ * struct sun8i_cipher_req_ctx - context for a skcipher request
+ * @op_dir: direction (encrypt vs decrypt) for this request
+ * @flow: the flow to use for this request
+ */
+struct sun8i_cipher_req_ctx {
+ u32 op_dir;
+ int flow;
+};
+
+/*
+ * struct sun8i_cipher_tfm_ctx - context for a skcipher TFM
+ * @enginectx: crypto_engine used by this TFM
+ * @key: pointer to key data
+ * @keylen: len of the key
+ * @ce: pointer to the private data of driver handling this TFM
+ * @fallback_tfm: pointer to the fallback TFM
+ */
+struct sun8i_cipher_tfm_ctx {
+ struct crypto_engine_ctx enginectx;
+ u32 *key;
+ u32 keylen;
+ struct sun8i_ce_dev *ce;
+ struct crypto_sync_skcipher *fallback_tfm;
+};
+
+/*
+ * struct sun8i_ce_alg_template - crypto_alg template
+ * @type: the CRYPTO_ALG_TYPE for this template
+ * @ce_algo_id: the CE_ID for this template
+ * @ce_blockmode: the type of block operation CE_ID
+ * @ce: pointer to the sun8i_ce_dev structure associated with
+ * this template
+ * @alg: one of sub struct must be used
+ * @stat_req: number of request done on this template
+ * @stat_fb: total of all data len done on this template
+ */
+struct sun8i_ce_alg_template {
+ u32 type;
+ u32 ce_algo_id;
+ u32 ce_blockmode;
+ struct sun8i_ce_dev *ce;
+ union {
+ struct skcipher_alg skcipher;
+ } alg;
+#ifdef CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG
+ unsigned long stat_req;
+ unsigned long stat_fb;
+#endif
+};
+
+int sun8i_ce_enqueue(struct crypto_async_request *areq, u32 type);
+
+int sun8i_ce_aes_setkey(struct crypto_skcipher *tfm, const u8 *key,
+ unsigned int keylen);
+int sun8i_ce_des3_setkey(struct crypto_skcipher *tfm, const u8 *key,
+ unsigned int keylen);
+int sun8i_ce_cipher_init(struct crypto_tfm *tfm);
+void sun8i_ce_cipher_exit(struct crypto_tfm *tfm);
+int sun8i_ce_skdecrypt(struct skcipher_request *areq);
+int sun8i_ce_skencrypt(struct skcipher_request *areq);
+
+int sun8i_ce_get_engine_number(struct sun8i_ce_dev *ce);
+
+int sun8i_ce_run_task(struct sun8i_ce_dev *ce, int flow, const char *name);
--
2.21.0
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^ permalink raw reply related
* [PATCH 4/9] ARM: dts: sun8i: r40: add crypto engine node
From: Corentin Labbe @ 2019-09-06 18:45 UTC (permalink / raw)
To: davem, herbert, linux, mark.rutland, mripard, robh+dt, wens
Cc: devicetree, linux-kernel, linux-sunxi, Corentin Labbe,
linux-crypto, linux-arm-kernel
In-Reply-To: <20190906184551.17858-1-clabbe.montjoie@gmail.com>
The Crypto Engine is a hardware cryptographic offloader that supports
many algorithms.
It could be found on most Allwinner SoCs.
This patch enables the Crypto Engine on the Allwinner R40 SoC Device-tree.
Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
---
arch/arm/boot/dts/sun8i-r40.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi b/arch/arm/boot/dts/sun8i-r40.dtsi
index bde068111b85..7eb649cea163 100644
--- a/arch/arm/boot/dts/sun8i-r40.dtsi
+++ b/arch/arm/boot/dts/sun8i-r40.dtsi
@@ -266,6 +266,17 @@
#phy-cells = <1>;
};
+ crypto: crypto-engine@1c15000 {
+ compatible = "allwinner,sun8i-r40-crypto";
+ reg = <0x01c15000 0x1000>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
+ clock-names = "ahb", "mod";
+ resets = <&ccu RST_BUS_CE>;
+ reset-names = "ahb";
+ status = "okay";
+ };
+
ehci1: usb@1c19000 {
compatible = "allwinner,sun8i-r40-ehci", "generic-ehci";
reg = <0x01c19000 0x100>;
--
2.21.0
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* [PATCH 5/9] ARM: dts: sun8i: h3: Add Crypto Engine node
From: Corentin Labbe @ 2019-09-06 18:45 UTC (permalink / raw)
To: davem, herbert, linux, mark.rutland, mripard, robh+dt, wens
Cc: devicetree, linux-kernel, linux-sunxi, Corentin Labbe,
linux-crypto, linux-arm-kernel
In-Reply-To: <20190906184551.17858-1-clabbe.montjoie@gmail.com>
The Crypto Engine is a hardware cryptographic accelerator that supports
many algorithms.
It could be found on most Allwinner SoCs.
This patch enables the Crypto Engine on the Allwinner H3 SoC Device-tree.
Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
---
arch/arm/boot/dts/sun8i-h3.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index e37c30e811d3..873abe1b279b 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -153,6 +153,17 @@
allwinner,sram = <&ve_sram 1>;
};
+ crypto: crypto@1c15000 {
+ compatible = "allwinner,sun8i-h3-crypto";
+ reg = <0x01c15000 0x1000>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ce_ns";
+ resets = <&ccu RST_BUS_CE>;
+ reset-names = "ahb";
+ clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
+ clock-names = "ahb", "mod";
+ };
+
mali: gpu@1c40000 {
compatible = "allwinner,sun8i-h3-mali", "arm,mali-400";
reg = <0x01c40000 0x10000>;
--
2.21.0
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^ permalink raw reply related
* [PATCH 6/9] ARM64: dts: allwinner: sun50i: Add Crypto Engine node on A64
From: Corentin Labbe @ 2019-09-06 18:45 UTC (permalink / raw)
To: davem, herbert, linux, mark.rutland, mripard, robh+dt, wens
Cc: devicetree, linux-kernel, linux-sunxi, Corentin Labbe,
linux-crypto, linux-arm-kernel
In-Reply-To: <20190906184551.17858-1-clabbe.montjoie@gmail.com>
The Crypto Engine is a hardware cryptographic accelerator that supports
many algorithms.
It could be found on most Allwinner SoCs.
This patch enables the Crypto Engine on the Allwinner A64 SoC Device-tree.
Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 69128a6dfc46..c9e30d462ab1 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -487,6 +487,17 @@
reg = <0x1c14000 0x400>;
};
+ crypto: crypto@1c15000 {
+ compatible = "allwinner,sun50i-a64-crypto";
+ reg = <0x01c15000 0x1000>;
+ interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ce_ns";
+ resets = <&ccu RST_BUS_CE>;
+ reset-names = "ahb";
+ clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>;
+ clock-names = "ahb", "mod";
+ };
+
usb_otg: usb@1c19000 {
compatible = "allwinner,sun8i-a33-musb";
reg = <0x01c19000 0x0400>;
--
2.21.0
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