* Re: [PATCH v2 06/11] dt-bindings: arm: samsung: Convert Exynos Chipid bindings to json-schema
From: Rob Herring @ 2019-09-18 12:57 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: linux-rtc, Alessandro Zummo, Alexandre Belloni, linux-samsung-soc,
devicetree, linux-iio, linux-pm, linux-kernel, linux-arm-kernel,
Paweł Chmiel
In-Reply-To: <20190907092007.9946-6-krzk@kernel.org>
On Sat, 7 Sep 2019 11:20:02 +0200, Krzysztof Kozlowski wrote:
> Convert Samsung Exynos Chipid bindings to DT schema format using
> json-schema.
>
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---
> .../bindings/arm/samsung/exynos-chipid.txt | 12 ---------
> .../bindings/arm/samsung/exynos-chipid.yaml | 25 +++++++++++++++++++
> 2 files changed, 25 insertions(+), 12 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/arm/samsung/exynos-chipid.txt
> create mode 100644 Documentation/devicetree/bindings/arm/samsung/exynos-chipid.yaml
>
Applied, thanks.
Rob
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* Re: [PATCH v2 05/11] dt-bindings: arm: samsung: Document missing Exynos7 boards bindings
From: Rob Herring @ 2019-09-18 12:56 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: linux-rtc, Alessandro Zummo, Alexandre Belloni, linux-samsung-soc,
devicetree, linux-iio, linux-pm, linux-kernel, linux-arm-kernel,
Paweł Chmiel
In-Reply-To: <20190907092007.9946-5-krzk@kernel.org>
On Sat, 7 Sep 2019 11:20:01 +0200, Krzysztof Kozlowski wrote:
> Add missing documentation of ARMv8 Samsung Exynos7 SoC based boards
> bindings.
>
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---
> .../devicetree/bindings/arm/samsung/samsung-boards.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>
Applied, thanks.
Rob
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* Re: [PATCH v2 04/11] dt-bindings: arm: samsung: Document missing S5Pv210 boards bindings
From: Rob Herring @ 2019-09-18 12:56 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: linux-rtc, Alessandro Zummo, Alexandre Belloni, linux-samsung-soc,
devicetree, linux-iio, linux-pm, linux-kernel, linux-arm-kernel,
Paweł Chmiel
In-Reply-To: <20190907092007.9946-4-krzk@kernel.org>
On Sat, 7 Sep 2019 11:20:00 +0200, Krzysztof Kozlowski wrote:
> Add missing documentation of Samsung S5Pv210 SoC based boards bindings.
>
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---
> .../bindings/arm/samsung/samsung-boards.yaml | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
Applied, thanks.
Rob
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^ permalink raw reply
* Re: [PATCH v2 03/11] dt-bindings: arm: samsung: Convert Samsung board/soc bindings to json-schema
From: Rob Herring @ 2019-09-18 12:56 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: linux-rtc, Alessandro Zummo, Alexandre Belloni, linux-samsung-soc,
devicetree, linux-iio, linux-pm, linux-kernel, linux-arm-kernel,
Paweł Chmiel
In-Reply-To: <20190907092007.9946-3-krzk@kernel.org>
On Sat, 7 Sep 2019 11:19:59 +0200, Krzysztof Kozlowski wrote:
> Convert Samsung S5P and Exynos SoC bindings to DT schema format using
> json-schema. This is purely conversion of already documented bindings
> so it does not cover all of DTS in the Linux kernel (few S5P/Exynos and
> all S3C are missing).
>
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
>
> ---
>
> Changes since v1:
> 1. Make Google boards latest revision as const.
> 2. Split secure firmware into separate schema.
> ---
> .../bindings/arm/samsung/samsung-boards.txt | 83 ---------
> .../bindings/arm/samsung/samsung-boards.yaml | 165 ++++++++++++++++++
> .../arm/samsung/samsung-secure-firmware.yaml | 31 ++++
> 3 files changed, 196 insertions(+), 83 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
> create mode 100644 Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml
> create mode 100644 Documentation/devicetree/bindings/arm/samsung/samsung-secure-firmware.yaml
>
Applied, thanks.
Rob
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^ permalink raw reply
* Re: [PATCH v2 02/11] dt-bindings: power: syscon-poweroff: Convert bindings to json-schema
From: Rob Herring @ 2019-09-18 12:56 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: linux-rtc, Alessandro Zummo, Alexandre Belloni, linux-samsung-soc,
devicetree, linux-iio, linux-pm, linux-kernel, linux-arm-kernel,
Paweł Chmiel
In-Reply-To: <20190907092007.9946-2-krzk@kernel.org>
On Sat, 7 Sep 2019 11:19:58 +0200, Krzysztof Kozlowski wrote:
> Convert the Syscon poweroff bindings to DT schema format using
> json-schema.
>
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
>
> ---
>
> Changes since v1:
> 1. Remove unneeded maxItems from uint32 fields,
> 2. Simplify if-else-then.
> ---
> .../bindings/power/reset/syscon-poweroff.txt | 30 ----------
> .../bindings/power/reset/syscon-poweroff.yaml | 60 +++++++++++++++++++
> 2 files changed, 60 insertions(+), 30 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/power/reset/syscon-poweroff.txt
> create mode 100644 Documentation/devicetree/bindings/power/reset/syscon-poweroff.yaml
>
Applied, thanks.
Rob
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^ permalink raw reply
* Re: [PATCH v2 01/11] dt-bindings: power: syscon-reboot: Convert bindings to json-schema
From: Rob Herring @ 2019-09-18 12:55 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: linux-rtc, Alessandro Zummo, Alexandre Belloni, linux-samsung-soc,
devicetree, linux-iio, linux-pm, linux-kernel, linux-arm-kernel,
Paweł Chmiel
In-Reply-To: <20190907092007.9946-1-krzk@kernel.org>
On Sat, 7 Sep 2019 11:19:57 +0200, Krzysztof Kozlowski wrote:
> Convert the Syscon reboot bindings to DT schema format using
> json-schema.
>
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
>
> ---
>
> Changes since v1:
> 1. Remove unneeded maxItems from uint32 fields,
> 2. Simplify if-else-then.
> ---
> .../bindings/power/reset/syscon-reboot.txt | 30 ----------
> .../bindings/power/reset/syscon-reboot.yaml | 60 +++++++++++++++++++
> 2 files changed, 60 insertions(+), 30 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/power/reset/syscon-reboot.txt
> create mode 100644 Documentation/devicetree/bindings/power/reset/syscon-reboot.yaml
>
Applied, thanks.
Rob
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^ permalink raw reply
* Re: [PATCH v1 2/9] mfd: wm8994: Add support for MCLKn clock control
From: Charles Keepax @ 2019-09-18 12:54 UTC (permalink / raw)
To: Sylwester Nawrocki
Cc: devicetree, alsa-devel, linux-samsung-soc, b.zolnierkie, sbkim73,
patches, broonie, lgirdwood, krzk, robh+dt, lee.jones,
linux-arm-kernel, m.szyprowski
In-Reply-To: <49ef7282-3765-9149-285d-a4025417eb58@samsung.com>
On Wed, Sep 18, 2019 at 12:59:28PM +0200, Sylwester Nawrocki wrote:
> On 9/18/19 12:46, Sylwester Nawrocki wrote:
> > The WM1811/WM8994/WM8958 audio CODEC DT bindings specify two optional
> > clocks: "MCLK1", "MCLK2". Add code for getting those clocks in the MFD
> > part of the wm8994 driver so they can be further handled in the audio
> > CODEC part.
> >
> > Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
> > ---
> >
> > + wm8994->mclk[WM8994_MCLK1].id = "MCLK1";
> > + wm8994->mclk[WM8994_MCLK2].id = "MCLK2";
> > +
> > + ret = devm_clk_bulk_get_optional(wm8994->dev, ARRAY_SIZE(wm8994->mclk),
> > + wm8994->mclk);
> > + if (ret != 0)
> > + return ret;
Would be nice to print a message here as well, make it clear what
failed in the log. Apart from that minor nit:
Acked-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Thanks,
Charles
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* Re: [PATCH v1 1/9] ASoC: wm8994: Do not register inapplicable controls for WM1811
From: Charles Keepax @ 2019-09-18 12:51 UTC (permalink / raw)
To: Sylwester Nawrocki
Cc: devicetree, alsa-devel, linux-samsung-soc, b.zolnierkie, sbkim73,
patches, broonie, lgirdwood, krzk, robh+dt, linux-arm-kernel,
m.szyprowski
In-Reply-To: <20190918104634.15216-2-s.nawrocki@samsung.com>
On Wed, Sep 18, 2019 at 12:46:26PM +0200, Sylwester Nawrocki wrote:
> In case of WM1811 device there are currently being registered controls
> referring to registers not existing on that device.
> It has been noticed when getting values of "AIF1ADC2 Volume", "AIF1DAC2
> Volume" controls was failing during ALSA state restoring at boot time:
> "amixer: Mixer hw:0 load error: Device or resource busy"
>
> Reading some registers through I2C was failing with EBUSY error and indeed
> those registers were not available according to the datasheet.
>
> To fix this controls not available on WM1811 are moved to a separate array
> and registered only for WM8994 and WM8958.
>
> There are some further differences between WM8994 and WM1811, e.g. registers
> 603h, 604h, 605h, which are not covered in this patch.
>
> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
> ---
Acked-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Thanks,
Charles
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^ permalink raw reply
* Re: [PATCH v2 07/11] dt-bindings: arm: samsung: Convert Exynos PMU bindings to json-schema
From: Rob Herring @ 2019-09-18 12:43 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Mark Rutland, Alessandro Zummo, Alexandre Belloni,
Lars-Peter Clausen, devicetree, linux-iio, linux-pm,
Sebastian Reichel, linux-kernel, linux-samsung-soc, Kukjin Kim,
linux-arm-kernel, Peter Meerwald-Stadler, Hartmut Knaack,
linux-rtc, Jonathan Cameron, Paweł Chmiel
In-Reply-To: <20190907092007.9946-7-krzk@kernel.org>
On Sat, Sep 07, 2019 at 11:20:03AM +0200, Krzysztof Kozlowski wrote:
> Convert Samsung Exynos Power Management Unit (PMU) bindings to DT schema
> format using json-schema.
>
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
>
> ---
>
> Changes since v1:
> 1. Fix clock-names to match all elements against schema (any number of
> any clkoutN values).
> This currently fails:
> properties:clock-names:items: {'enum': ['clkout0', 'clkout1', 'clkout2',
> 'clkout3', 'clkout4', 'clkout5', 'clkout6', 'clkout7', 'clkout8',
> 'clkout9', 'clkout10', 'clkout11', 'clkout12', 'clkout13', 'clkout14',
> 'clkout15', 'clkout16']} is not of type 'array
>
> 2. Add syscon reboot and poweroff nodes.
> ---
> .../devicetree/bindings/arm/samsung/pmu.txt | 72 -----------
> .../devicetree/bindings/arm/samsung/pmu.yaml | 117 ++++++++++++++++++
> 2 files changed, 117 insertions(+), 72 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/arm/samsung/pmu.txt
> create mode 100644 Documentation/devicetree/bindings/arm/samsung/pmu.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
> deleted file mode 100644
> index 433bfd7593ac..000000000000
> --- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
> +++ /dev/null
> @@ -1,72 +0,0 @@
> -SAMSUNG Exynos SoC series PMU Registers
> -
> -Properties:
> - - compatible : should contain two values. First value must be one from following list:
> - - "samsung,exynos3250-pmu" - for Exynos3250 SoC,
> - - "samsung,exynos4210-pmu" - for Exynos4210 SoC,
> - - "samsung,exynos4412-pmu" - for Exynos4412 SoC,
> - - "samsung,exynos5250-pmu" - for Exynos5250 SoC,
> - - "samsung,exynos5260-pmu" - for Exynos5260 SoC.
> - - "samsung,exynos5410-pmu" - for Exynos5410 SoC,
> - - "samsung,exynos5420-pmu" - for Exynos5420 SoC.
> - - "samsung,exynos5433-pmu" - for Exynos5433 SoC.
> - - "samsung,exynos7-pmu" - for Exynos7 SoC.
> - second value must be always "syscon".
> -
> - - reg : offset and length of the register set.
> -
> - - #clock-cells : must be <1>, since PMU requires once cell as clock specifier.
> - The single specifier cell is used as index to list of clocks
> - provided by PMU, which is currently:
> - 0 : SoC clock output (CLKOUT pin)
> -
> - - clock-names : list of clock names for particular CLKOUT mux inputs in
> - following format:
> - "clkoutN", where N is a decimal number corresponding to
> - CLKOUT mux control bits value for given input, e.g.
> - "clkout0", "clkout7", "clkout15".
> -
> - - clocks : list of phandles and specifiers to all input clocks listed in
> - clock-names property.
> -
> -Optional properties:
> -
> -Some PMUs are capable of behaving as an interrupt controller (mostly
> -to wake up a suspended PMU). In which case, they can have the
> -following properties:
> -
> -- interrupt-controller: indicate that said PMU is an interrupt controller
> -
> -- #interrupt-cells: must be identical to the that of the parent interrupt
> - controller.
> -
> -
> -Optional nodes:
> -
> -- nodes defining the restart and poweroff syscon children
> -
> -
> -Example :
> -pmu_system_controller: system-controller@10040000 {
> - compatible = "samsung,exynos5250-pmu", "syscon";
> - reg = <0x10040000 0x5000>;
> - interrupt-controller;
> - #interrupt-cells = <3>;
> - interrupt-parent = <&gic>;
> - #clock-cells = <1>;
> - clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
> - "clkout4", "clkout8", "clkout9";
> - clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
> - <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
> - <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>,
> - <&clock CLK_XUSBXTI>;
> -};
> -
> -Example of clock consumer :
> -
> -usb3503: usb3503@8 {
> - /* ... */
> - clock-names = "refclk";
> - clocks = <&pmu_system_controller 0>;
> - /* ... */
> -};
> diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.yaml b/Documentation/devicetree/bindings/arm/samsung/pmu.yaml
> new file mode 100644
> index 000000000000..a5a02f8237fb
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/samsung/pmu.yaml
> @@ -0,0 +1,117 @@
> +# SPDX-License-Identifier: GPL-2.0
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/samsung/pmu.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Samsung Exynos SoC series Power Management Unit (PMU)
> +
> +maintainers:
> + - Krzysztof Kozlowski <krzk@kernel.org>
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - samsung,exynos3250-pmu
> + - samsung,exynos4210-pmu
> + - samsung,exynos4412-pmu
> + - samsung,exynos5250-pmu
> + - samsung,exynos5260-pmu
> + - samsung,exynos5410-pmu
> + - samsung,exynos5420-pmu
> + - samsung,exynos5433-pmu
> + - samsung,exynos7-pmu
> + - const: syscon
> +
> + reg:
> + maxItems: 1
> +
> + '#clock-cells':
> + const: 1
> +
> + clock-names:
> + description:
> + List of clock names for particular CLKOUT mux inputs
> + minItems: 1
> + maxItems: 32
> + items:
> + enum:
> + - clkout0
> + - clkout1
Looking at this again, instead of enum, we can just do:
pattern: '^clkout([0-9]|[12][0-9]|3[0-1])$'
> + - clkout2
> + - clkout3
> + - clkout4
> + - clkout5
> + - clkout6
> + - clkout7
> + - clkout8
> + - clkout9
> + - clkout10
> + - clkout11
> + - clkout12
> + - clkout13
> + - clkout14
> + - clkout15
> + - clkout16
> + - clkout17
> + - clkout18
> + - clkout19
> + - clkout20
> + - clkout21
> + - clkout22
> + - clkout23
> + - clkout24
> + - clkout25
> + - clkout26
> + - clkout27
> + - clkout28
> + - clkout29
> + - clkout30
> + - clkout31
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* Re: [PATCH 3/3] reset: add support for the Meson-A1 SoC Reset Controller
From: Neil Armstrong @ 2019-09-18 12:39 UTC (permalink / raw)
To: Xingyu Chen, Philipp Zabel, Kevin Hilman
Cc: Hanjie Lin, Jianxin Pan, linux-kernel, Rob Herring, linux-amlogic,
linux-arm-kernel, Jerome Brunet
In-Reply-To: <1568808749-1196-1-git-send-email-xingyu.chen@amlogic.com>
On 18/09/2019 14:12, Xingyu Chen wrote:
> The number of RESET registers and offset of RESET_LEVEL register for
> Meson-A1 are different from previous SoCs, In order to describe these
> differences, we introduce the struct meson_reset_param.
>
> Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
> Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com>
> ---
> drivers/reset/reset-meson.c | 35 ++++++++++++++++++++++++++++-------
> 1 file changed, 28 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/reset/reset-meson.c b/drivers/reset/reset-meson.c
> index 5242e06..d9541c1 100644
> --- a/drivers/reset/reset-meson.c
> +++ b/drivers/reset/reset-meson.c
> @@ -64,12 +64,16 @@
> #include <linux/types.h>
> #include <linux/of_device.h>
>
> -#define REG_COUNT 8
> #define BITS_PER_REG 32
> -#define LEVEL_OFFSET 0x7c
> +
> +struct meson_reset_param {
> + int reg_count;
> + int level_offset;
> +};
>
> struct meson_reset {
> void __iomem *reg_base;
> + const struct meson_reset_param *param;
> struct reset_controller_dev rcdev;
> spinlock_t lock;
> };
> @@ -95,10 +99,12 @@ static int meson_reset_level(struct reset_controller_dev *rcdev,
> container_of(rcdev, struct meson_reset, rcdev);
> unsigned int bank = id / BITS_PER_REG;
> unsigned int offset = id % BITS_PER_REG;
> - void __iomem *reg_addr = data->reg_base + LEVEL_OFFSET + (bank << 2);
> + void __iomem *reg_addr;
> unsigned long flags;
> u32 reg;
>
> + reg_addr = data->reg_base + data->param->level_offset + (bank << 2);
> +
> spin_lock_irqsave(&data->lock, flags);
>
> reg = readl(reg_addr);
> @@ -130,10 +136,21 @@ static const struct reset_control_ops meson_reset_ops = {
> .deassert = meson_reset_deassert,
> };
>
> +static const struct meson_reset_param meson8b_param = {
> + .reg_count = 8,
> + .level_offset = 0x7c,
> +};
> +
> +static const struct meson_reset_param meson_a1_param = {
> + .reg_count = 3,
> + .level_offset = 0x40,
> +};
> +
> static const struct of_device_id meson_reset_dt_ids[] = {
> - { .compatible = "amlogic,meson8b-reset" },
> - { .compatible = "amlogic,meson-gxbb-reset" },
> - { .compatible = "amlogic,meson-axg-reset" },
> + { .compatible = "amlogic,meson8b-reset", .data = &meson8b_param},
> + { .compatible = "amlogic,meson-gxbb-reset", .data = &meson8b_param},
> + { .compatible = "amlogic,meson-axg-reset", .data = &meson8b_param},
> + { .compatible = "amlogic,meson-a1-reset", .data = &meson_a1_param},
> { /* sentinel */ },
> };
>
> @@ -151,12 +168,16 @@ static int meson_reset_probe(struct platform_device *pdev)
> if (IS_ERR(data->reg_base))
> return PTR_ERR(data->reg_base);
>
> + data->param = of_device_get_match_data(&pdev->dev);
> + if (!data->param)
> + return -ENODEV;
> +
> platform_set_drvdata(pdev, data);
>
> spin_lock_init(&data->lock);
>
> data->rcdev.owner = THIS_MODULE;
> - data->rcdev.nr_resets = REG_COUNT * BITS_PER_REG;
> + data->rcdev.nr_resets = data->param->reg_count * BITS_PER_REG;
> data->rcdev.ops = &meson_reset_ops;
> data->rcdev.of_node = pdev->dev.of_node;
>
>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
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* Re: [PATCH 2/3] dt-bindings: reset: add bindings for the Meson-A1 SoC Reset Controller
From: Neil Armstrong @ 2019-09-18 12:39 UTC (permalink / raw)
To: Xingyu Chen, Philipp Zabel, Kevin Hilman
Cc: devicetree, Hanjie Lin, Jianxin Pan, linux-kernel, Rob Herring,
linux-amlogic, linux-arm-kernel, Jerome Brunet
In-Reply-To: <1568808746-1153-3-git-send-email-xingyu.chen@amlogic.com>
Hi,
On 18/09/2019 14:12, Xingyu Chen wrote:
> Add DT bindings for the Meson-A1 SoC Reset Controller include file,
> and also slightly update documentation.
>
> Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
> Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com>
> ---
> .../bindings/reset/amlogic,meson-reset.txt | 4 +-
The reset bindings has been moved to yaml, either rebase on linux-next or wait for v5.4-rc1 :
https://kernel.googlesource.com/pub/scm/linux/kernel/git/next/linux-next/+/refs/tags/next-20190917/Documentation/devicetree/bindings/reset/amlogic%2Cmeson-reset.yaml
Neil
> include/dt-bindings/reset/amlogic,meson-a1-reset.h | 59 ++++++++++++++++++++++
> 2 files changed, 61 insertions(+), 2 deletions(-)
> create mode 100644 include/dt-bindings/reset/amlogic,meson-a1-reset.h
>
> diff --git a/Documentation/devicetree/bindings/reset/amlogic,meson-reset.txt b/Documentation/devicetree/bindings/reset/amlogic,meson-reset.txt
> index 28ef6c2..011151a 100644
> --- a/Documentation/devicetree/bindings/reset/amlogic,meson-reset.txt
> +++ b/Documentation/devicetree/bindings/reset/amlogic,meson-reset.txt
> @@ -5,8 +5,8 @@ Please also refer to reset.txt in this directory for common reset
> controller binding usage.
>
> Required properties:
> -- compatible: Should be "amlogic,meson8b-reset", "amlogic,meson-gxbb-reset" or
> - "amlogic,meson-axg-reset".
> +- compatible: Should be "amlogic,meson8b-reset", "amlogic,meson-gxbb-reset",
> + "amlogic,meson-axg-reset" or "amlogic,meson-a1-reset".
> - reg: should contain the register address base
> - #reset-cells: 1, see below
>
> diff --git a/include/dt-bindings/reset/amlogic,meson-a1-reset.h b/include/dt-bindings/reset/amlogic,meson-a1-reset.h
> new file mode 100644
> index 00000000..8d76a47
> --- /dev/null
> +++ b/include/dt-bindings/reset/amlogic,meson-a1-reset.h
> @@ -0,0 +1,59 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> + *
> + * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
> + * Author: Xingyu Chen <xingyu.chen@amlogic.com>
> + *
> + */
> +
> +#ifndef _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H
> +#define _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H
> +
> +/* RESET0 */
> +#define RESET_AM2AXI_VAD 1
> +#define RESET_PSRAM 4
> +#define RESET_PAD_CTRL 5
> +#define RESET_TEMP_SENSOR 7
> +#define RESET_AM2AXI_DEV 8
> +#define RESET_SPICC_A 10
> +#define RESET_MSR_CLK 11
> +#define RESET_AUDIO 12
> +#define RESET_ANALOG_CTRL 13
> +#define RESET_SAR_ADC 14
> +#define RESET_AUDIO_VAD 15
> +#define RESET_CEC 16
> +#define RESET_PWM_EF 17
> +#define RESET_PWM_CD 18
> +#define RESET_PWM_AB 19
> +#define RESET_IR_CTRL 21
> +#define RESET_I2C_S_A 22
> +#define RESET_I2C_M_D 24
> +#define RESET_I2C_M_C 25
> +#define RESET_I2C_M_B 26
> +#define RESET_I2C_M_A 27
> +#define RESET_I2C_PROD_AHB 28
> +#define RESET_I2C_PROD 29
> +
> +/* RESET1 */
> +#define RESET_ACODEC 32
> +#define RESET_DMA 33
> +#define RESET_SD_EMMC_A 34
> +#define RESET_USBCTRL 36
> +#define RESET_USBPHY 38
> +#define RESET_RSA 42
> +#define RESET_DMC 43
> +#define RESET_IRQ_CTRL 45
> +#define RESET_NIC_VAD 47
> +#define RESET_NIC_AXI 48
> +#define RESET_RAMA 49
> +#define RESET_RAMB 50
> +#define RESET_ROM 53
> +#define RESET_SPIFC 54
> +#define RESET_GIC 55
> +#define RESET_UART_C 56
> +#define RESET_UART_B 57
> +#define RESET_UART_A 58
> +#define RESET_OSC_RING 59
> +
> +/* RESET2 Reserved */
> +
> +#endif
>
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* [PATCH] ARM: dts: vesnin: Add power_green led
From: Alexander Filippov @ 2019-09-18 12:38 UTC (permalink / raw)
To: linux-aspeed
Cc: Mark Rutland, devicetree, Andrew Jeffery, linux-kernel,
Alexander Filippov, Rob Herring, Joel Stanley, linux-arm-kernel
Adds a new power_green led to show the host state.
Signed-off-by: Alexander Filippov <a.filippov@yadro.com>
---
arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts b/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts
index a27c88d23056..affd2c8743b1 100644
--- a/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-opp-vesnin.dts
@@ -43,6 +43,10 @@
gpios = <&gpio ASPEED_GPIO(N, 1) GPIO_ACTIVE_LOW>;
};
+ power_green {
+ gpios = <&gpio ASPEED_GPIO(F, 1) GPIO_ACTIVE_LOW>;
+ };
+
id_blue {
gpios = <&gpio ASPEED_GPIO(O, 0) GPIO_ACTIVE_LOW>;
};
--
2.21.0
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* Re: [PATCH v2 08/11] dt-bindings: arm: samsung: Convert Exynos System Registers bindings to json-schema
From: Rob Herring @ 2019-09-18 12:36 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Mark Rutland, Alessandro Zummo, Alexandre Belloni,
Lars-Peter Clausen, devicetree, linux-iio, linux-pm,
Sebastian Reichel, linux-kernel, linux-samsung-soc, Kukjin Kim,
linux-arm-kernel, Peter Meerwald-Stadler, Hartmut Knaack,
linux-rtc, Jonathan Cameron, Paweł Chmiel
In-Reply-To: <20190907092007.9946-8-krzk@kernel.org>
On Sat, Sep 07, 2019 at 11:20:04AM +0200, Krzysztof Kozlowski wrote:
> Convert Samsung Exynos System Registers (SYSREG) bindings to DT schema
> format using json-schema.
>
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
>
> ---
>
> Example somehow fails:
> Documentation/devicetree/bindings/arm/samsung/pmu.example.dt.yaml:
> system-controller@10040000: compatible:0: 'samsung,exynos5250-pmu' is
> not one of ['samsung,exynos4-sysreg', 'samsung,exynos5-sysreg']
>
> It seems that PMU schema is applied to sysreq nodes (and vice-versa).
> ---
> .../bindings/arm/samsung/sysreg.txt | 19 -----------
> .../bindings/arm/samsung/sysreg.yaml | 33 +++++++++++++++++++
> 2 files changed, 33 insertions(+), 19 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/arm/samsung/sysreg.txt
> create mode 100644 Documentation/devicetree/bindings/arm/samsung/sysreg.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/samsung/sysreg.txt b/Documentation/devicetree/bindings/arm/samsung/sysreg.txt
> deleted file mode 100644
> index 4fced6e9d5e4..000000000000
> --- a/Documentation/devicetree/bindings/arm/samsung/sysreg.txt
> +++ /dev/null
> @@ -1,19 +0,0 @@
> -SAMSUNG S5P/Exynos SoC series System Registers (SYSREG)
> -
> -Properties:
> - - compatible : should contain two values. First value must be one from following list:
> - - "samsung,exynos4-sysreg" - for Exynos4 based SoCs,
> - - "samsung,exynos5-sysreg" - for Exynos5 based SoCs.
> - second value must be always "syscon".
> - - reg : offset and length of the register set.
> -
> -Example:
> - syscon@10010000 {
> - compatible = "samsung,exynos4-sysreg", "syscon";
> - reg = <0x10010000 0x400>;
> - };
> -
> - syscon@10050000 {
> - compatible = "samsung,exynos5-sysreg", "syscon";
> - reg = <0x10050000 0x5000>;
> - };
> diff --git a/Documentation/devicetree/bindings/arm/samsung/sysreg.yaml b/Documentation/devicetree/bindings/arm/samsung/sysreg.yaml
> new file mode 100644
> index 000000000000..a3d44646e441
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/samsung/sysreg.yaml
> @@ -0,0 +1,33 @@
> +# SPDX-License-Identifier: GPL-2.0
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/samsung/sysreg.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Samsung S5P/Exynos SoC series System Registers (SYSREG)
> +
> +maintainers:
> + - Krzysztof Kozlowski <krzk@kernel.org>
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - samsung,exynos4-sysreg
> + - samsung,exynos5-sysreg
> + - const: syscon
The problem is this will by default match any node with 'syscon'. You
have to add a custom 'select' entry. See the LVDS panel bindings for an
example.
I'd like to kill off 'syscon'...
> +
> + reg:
> + maxItems: 1
> +
> +examples:
> + - |
> + syscon@10010000 {
> + compatible = "samsung,exynos4-sysreg", "syscon";
> + reg = <0x10010000 0x400>;
> + };
> +
> + syscon@10050000 {
> + compatible = "samsung,exynos5-sysreg", "syscon";
> + reg = <0x10050000 0x5000>;
> + };
> --
> 2.17.1
>
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* Re: [PATCH] dt-bindings: memory-controllers: Convert Samsung Exynos SROM bindings to json-schema
From: Krzysztof Kozlowski @ 2019-09-18 12:25 UTC (permalink / raw)
To: Rob Herring
Cc: Mark Rutland, devicetree, linux-samsung-soc@vger.kernel.org,
linux-kernel@vger.kernel.org, Kukjin Kim, linux-arm-kernel
In-Reply-To: <5d7ba95e.1c69fb81.bba41.66c2@mx.google.com>
On Fri, 13 Sep 2019 at 16:36, Rob Herring <robh@kernel.org> wrote:
>
> On Sat, Sep 07, 2019 at 04:44:42PM +0200, Krzysztof Kozlowski wrote:
> > Convert Samsung Exynos SROM controller bindings to DT schema format
> > using json-schema.
> >
> > Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> > ---
> > .../memory-controllers/exynos-srom.txt | 79 ----------
> > .../memory-controllers/exynos-srom.yaml | 136 ++++++++++++++++++
> > 2 files changed, 136 insertions(+), 79 deletions(-)
> > delete mode 100644 Documentation/devicetree/bindings/memory-controllers/exynos-srom.txt
> > create mode 100644 Documentation/devicetree/bindings/memory-controllers/exynos-srom.yaml
>
>
> > diff --git a/Documentation/devicetree/bindings/memory-controllers/exynos-srom.yaml b/Documentation/devicetree/bindings/memory-controllers/exynos-srom.yaml
> > new file mode 100644
> > index 000000000000..9573bcfd68bf
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/memory-controllers/exynos-srom.yaml
> > @@ -0,0 +1,136 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/memory-controllers/exynos-srom.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Samsung Exynos SoC SROM Controller driver
> > +
> > +maintainers:
> > + - Krzysztof Kozlowski <krzk@kernel.org>
> > +
> > +description: |+
> > + The SROM controller can be used to attach external peripherals. In this case
> > + extra properties, describing the bus behind it, should be specified.
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - const: samsung,exynos4210-srom
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + "#address-cells":
> > + const: 2
> > +
> > + "#size-cells":
> > + const: 1
> > +
> > + ranges:
> > + description: |
> > + Reflects the memory layout with four integer values per bank. Format:
> > + <bank-number> 0 <parent address of bank> <size>
> > +
> > +patternProperties:
> > + "^.*@[0-9]+,[0-9]+$":
>
> How many chip selects? Can be a single digit?
Currently up to four banks, so I can limit the pattern.
>
> Also, these should be hex values.
Sure.
>
> > + type: object
> > + description:
> > + The actual device nodes should be added as subnodes to the SROMc node.
> > + These subnodes, in addition to regular device specification, should
> > + contain the following properties, describing configuration
> > + of the relevant SROM bank.
> > +
> > + properties:
> > + reg:
> > + description:
> > + Bank number, base address (relative to start of the bank) and size
> > + of the memory mapped for the device. Note that base address will be
> > + typically 0 as this is the start of the bank.
> > + maxItems: 1
> > +
> > + reg-io-width:
> > + allOf:
> > + - $ref: /schemas/types.yaml#/definitions/uint32
> > + - enum: [1, 2]
> > + description:
> > + Data width in bytes (1 or 2). If omitted, default of 1 is used.
> > +
> > + samsung,srom-page-mode:
> > + description:
> > + If page mode is set, 4 data page mode will be configured,
> > + else normal (1 data) page mode will be set.
> > + type: boolean
> > +
> > + samsung,srom-timing:
> > + allOf:
> > + - $ref: /schemas/types.yaml#/definitions/uint32-array
> > + - items:
> > + minItems: 6
> > + maxItems: 6
> > + description: |
> > + Array of 6 integers, specifying bank timings in the following order:
> > + Tacp, Tcah, Tcoh, Tacc, Tcos, Tacs.
> > + Each value is specified in cycles and has the following meaning
> > + and valid range:
> > + Tacp: Page mode access cycle at Page mode (0 - 15)
> > + Tcah: Address holding time after CSn (0 - 15)
> > + Tcoh: Chip selection hold on OEn (0 - 15)
> > + Tacc: Access cycle (0 - 31, the actual time is N + 1)
> > + Tcos: Chip selection set-up before OEn (0 - 15)
> > + Tacs: Address set-up before CSn (0 - 15)
> > +
> > + required:
> > + - reg
> > + - samsung,srom-timing
> > +
> > +required:
> > + - compatible
> > + - reg
> > +
> > +allOf:
> > + - if:
> > + anyOf:
> > + - required: [ "#address-cells" ]
> > + - required: [ ranges ]
> > + - required: [ "#size-cells" ]
> > + then:
> > + required:
> > + - "#address-cells"
> > + - ranges
> > + - "#size-cells"
>
> I don't think this is necessary as the core schema should take care of
> it. This can also be expressed using 'dependencies'.
I'll skip it then.
Best regards,
Krzysztof
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* [PATCH] counter: stm32-lptimer-cnt: fix a kernel-doc warning
From: Fabrice Gasnier @ 2019-09-18 12:22 UTC (permalink / raw)
To: vilhelm.gray
Cc: alexandre.torgue, linux-iio, linux-kernel, jic23, fabrice.gasnier,
linux-stm32, linux-arm-kernel
Fix the following warnings when documentation is built:
drivers/counter/stm32-lptimer-cnt.c:354: warning: cannot understand
function prototype: 'enum stm32_lptim_cnt_function'
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
---
drivers/counter/stm32-lptimer-cnt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/counter/stm32-lptimer-cnt.c b/drivers/counter/stm32-lptimer-cnt.c
index bbc930a..28b6364 100644
--- a/drivers/counter/stm32-lptimer-cnt.c
+++ b/drivers/counter/stm32-lptimer-cnt.c
@@ -347,7 +347,7 @@ static const struct iio_chan_spec stm32_lptim_cnt_channels = {
};
/**
- * stm32_lptim_cnt_function - enumerates stm32 LPTimer counter & encoder modes
+ * enum stm32_lptim_cnt_function - enumerates LPTimer counter & encoder modes
* @STM32_LPTIM_COUNTER_INCREASE: up count on IN1 rising, falling or both edges
* @STM32_LPTIM_ENCODER_BOTH_EDGE: count on both edges (IN1 & IN2 quadrature)
*/
--
2.7.4
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* [PATCH] counter: stm32-timer-cnt: fix a kernel-doc warning
From: Fabrice Gasnier @ 2019-09-18 12:22 UTC (permalink / raw)
To: vilhelm.gray
Cc: alexandre.torgue, linux-iio, linux-kernel, jic23, fabrice.gasnier,
linux-stm32, linux-arm-kernel
Fix the following warning when documentation is built:
drivers/counter/stm32-timer-cnt.c:37: warning: cannot understand function
prototype: 'enum stm32_count_function'
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
---
drivers/counter/stm32-timer-cnt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/counter/stm32-timer-cnt.c b/drivers/counter/stm32-timer-cnt.c
index 644ba18..e425dd1 100644
--- a/drivers/counter/stm32-timer-cnt.c
+++ b/drivers/counter/stm32-timer-cnt.c
@@ -28,7 +28,7 @@ struct stm32_timer_cnt {
};
/**
- * stm32_count_function - enumerates stm32 timer counter encoder modes
+ * enum stm32_count_function - enumerates stm32 timer counter encoder modes
* @STM32_COUNT_SLAVE_MODE_DISABLED: counts on internal clock when CEN=1
* @STM32_COUNT_ENCODER_MODE_1: counts TI1FP1 edges, depending on TI2FP2 level
* @STM32_COUNT_ENCODER_MODE_2: counts TI2FP2 edges, depending on TI1FP1 level
--
2.7.4
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* Re: [PATCH v2 7/7] counter: stm32-timer-cnt: Update count_read and count_write callbacks
From: Fabrice Gasnier @ 2019-09-18 12:16 UTC (permalink / raw)
To: William Breathitt Gray, jic23
Cc: alexandre.torgue, linux-iio, patrick.havelange, linux-kernel,
mcoquelin.stm32, linux-stm32, linux-arm-kernel
In-Reply-To: <327fe01b7ce4feb0fc3d854393691664a6a36b40.1568792697.git.vilhelm.gray@gmail.com>
On 9/18/19 9:52 AM, William Breathitt Gray wrote:
> The count_read and count_write callbacks pass unsigned long now.
>
> Cc: Fabrice Gasnier <fabrice.gasnier@st.com>
> Signed-off-by: William Breathitt Gray <vilhelm.gray@gmail.com>
Hi William,
I tested your series for STM32 timer and LPtimer drivers. Maybe you can
squash as suggested by Benjamin ?
With that, you can add my acked-by for the two STM32 drivers.
Thanks,
Fabrice
> ---
> drivers/counter/stm32-timer-cnt.c | 17 +++++------------
> 1 file changed, 5 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/counter/stm32-timer-cnt.c b/drivers/counter/stm32-timer-cnt.c
> index 644ba18a72ad..839083543323 100644
> --- a/drivers/counter/stm32-timer-cnt.c
> +++ b/drivers/counter/stm32-timer-cnt.c
> @@ -48,34 +48,27 @@ static enum counter_count_function stm32_count_functions[] = {
> };
>
> static int stm32_count_read(struct counter_device *counter,
> - struct counter_count *count,
> - struct counter_count_read_value *val)
> + struct counter_count *count, unsigned long *val)
> {
> struct stm32_timer_cnt *const priv = counter->priv;
> u32 cnt;
>
> regmap_read(priv->regmap, TIM_CNT, &cnt);
> - counter_count_read_value_set(val, COUNTER_COUNT_POSITION, &cnt);
> + *val = cnt;
>
> return 0;
> }
>
> static int stm32_count_write(struct counter_device *counter,
> struct counter_count *count,
> - struct counter_count_write_value *val)
> + const unsigned long val)
> {
> struct stm32_timer_cnt *const priv = counter->priv;
> - u32 cnt;
> - int err;
> -
> - err = counter_count_write_value_get(&cnt, COUNTER_COUNT_POSITION, val);
> - if (err)
> - return err;
>
> - if (cnt > priv->ceiling)
> + if (val > priv->ceiling)
> return -EINVAL;
>
> - return regmap_write(priv->regmap, TIM_CNT, cnt);
> + return regmap_write(priv->regmap, TIM_CNT, val);
> }
>
> static int stm32_count_function_get(struct counter_device *counter,
>
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* [PATCH 3/3] reset: add support for the Meson-A1 SoC Reset Controller
From: Xingyu Chen @ 2019-09-18 12:12 UTC (permalink / raw)
To: Philipp Zabel, Kevin Hilman
Cc: Hanjie Lin, Jianxin Pan, Neil Armstrong, linux-kernel,
Rob Herring, linux-arm-kernel, linux-amlogic, Xingyu Chen,
Jerome Brunet
The number of RESET registers and offset of RESET_LEVEL register for
Meson-A1 are different from previous SoCs, In order to describe these
differences, we introduce the struct meson_reset_param.
Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com>
---
drivers/reset/reset-meson.c | 35 ++++++++++++++++++++++++++++-------
1 file changed, 28 insertions(+), 7 deletions(-)
diff --git a/drivers/reset/reset-meson.c b/drivers/reset/reset-meson.c
index 5242e06..d9541c1 100644
--- a/drivers/reset/reset-meson.c
+++ b/drivers/reset/reset-meson.c
@@ -64,12 +64,16 @@
#include <linux/types.h>
#include <linux/of_device.h>
-#define REG_COUNT 8
#define BITS_PER_REG 32
-#define LEVEL_OFFSET 0x7c
+
+struct meson_reset_param {
+ int reg_count;
+ int level_offset;
+};
struct meson_reset {
void __iomem *reg_base;
+ const struct meson_reset_param *param;
struct reset_controller_dev rcdev;
spinlock_t lock;
};
@@ -95,10 +99,12 @@ static int meson_reset_level(struct reset_controller_dev *rcdev,
container_of(rcdev, struct meson_reset, rcdev);
unsigned int bank = id / BITS_PER_REG;
unsigned int offset = id % BITS_PER_REG;
- void __iomem *reg_addr = data->reg_base + LEVEL_OFFSET + (bank << 2);
+ void __iomem *reg_addr;
unsigned long flags;
u32 reg;
+ reg_addr = data->reg_base + data->param->level_offset + (bank << 2);
+
spin_lock_irqsave(&data->lock, flags);
reg = readl(reg_addr);
@@ -130,10 +136,21 @@ static const struct reset_control_ops meson_reset_ops = {
.deassert = meson_reset_deassert,
};
+static const struct meson_reset_param meson8b_param = {
+ .reg_count = 8,
+ .level_offset = 0x7c,
+};
+
+static const struct meson_reset_param meson_a1_param = {
+ .reg_count = 3,
+ .level_offset = 0x40,
+};
+
static const struct of_device_id meson_reset_dt_ids[] = {
- { .compatible = "amlogic,meson8b-reset" },
- { .compatible = "amlogic,meson-gxbb-reset" },
- { .compatible = "amlogic,meson-axg-reset" },
+ { .compatible = "amlogic,meson8b-reset", .data = &meson8b_param},
+ { .compatible = "amlogic,meson-gxbb-reset", .data = &meson8b_param},
+ { .compatible = "amlogic,meson-axg-reset", .data = &meson8b_param},
+ { .compatible = "amlogic,meson-a1-reset", .data = &meson_a1_param},
{ /* sentinel */ },
};
@@ -151,12 +168,16 @@ static int meson_reset_probe(struct platform_device *pdev)
if (IS_ERR(data->reg_base))
return PTR_ERR(data->reg_base);
+ data->param = of_device_get_match_data(&pdev->dev);
+ if (!data->param)
+ return -ENODEV;
+
platform_set_drvdata(pdev, data);
spin_lock_init(&data->lock);
data->rcdev.owner = THIS_MODULE;
- data->rcdev.nr_resets = REG_COUNT * BITS_PER_REG;
+ data->rcdev.nr_resets = data->param->reg_count * BITS_PER_REG;
data->rcdev.ops = &meson_reset_ops;
data->rcdev.of_node = pdev->dev.of_node;
--
2.7.4
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* [PATCH 2/3] dt-bindings: reset: add bindings for the Meson-A1 SoC Reset Controller
From: Xingyu Chen @ 2019-09-18 12:12 UTC (permalink / raw)
To: Philipp Zabel, Kevin Hilman
Cc: devicetree, Hanjie Lin, Jianxin Pan, Neil Armstrong, linux-kernel,
Rob Herring, linux-arm-kernel, linux-amlogic, Xingyu Chen,
Jerome Brunet
In-Reply-To: <1568808746-1153-1-git-send-email-xingyu.chen@amlogic.com>
Add DT bindings for the Meson-A1 SoC Reset Controller include file,
and also slightly update documentation.
Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com>
---
.../bindings/reset/amlogic,meson-reset.txt | 4 +-
include/dt-bindings/reset/amlogic,meson-a1-reset.h | 59 ++++++++++++++++++++++
2 files changed, 61 insertions(+), 2 deletions(-)
create mode 100644 include/dt-bindings/reset/amlogic,meson-a1-reset.h
diff --git a/Documentation/devicetree/bindings/reset/amlogic,meson-reset.txt b/Documentation/devicetree/bindings/reset/amlogic,meson-reset.txt
index 28ef6c2..011151a 100644
--- a/Documentation/devicetree/bindings/reset/amlogic,meson-reset.txt
+++ b/Documentation/devicetree/bindings/reset/amlogic,meson-reset.txt
@@ -5,8 +5,8 @@ Please also refer to reset.txt in this directory for common reset
controller binding usage.
Required properties:
-- compatible: Should be "amlogic,meson8b-reset", "amlogic,meson-gxbb-reset" or
- "amlogic,meson-axg-reset".
+- compatible: Should be "amlogic,meson8b-reset", "amlogic,meson-gxbb-reset",
+ "amlogic,meson-axg-reset" or "amlogic,meson-a1-reset".
- reg: should contain the register address base
- #reset-cells: 1, see below
diff --git a/include/dt-bindings/reset/amlogic,meson-a1-reset.h b/include/dt-bindings/reset/amlogic,meson-a1-reset.h
new file mode 100644
index 00000000..8d76a47
--- /dev/null
+++ b/include/dt-bindings/reset/amlogic,meson-a1-reset.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ * Author: Xingyu Chen <xingyu.chen@amlogic.com>
+ *
+ */
+
+#ifndef _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H
+#define _DT_BINDINGS_AMLOGIC_MESON_A1_RESET_H
+
+/* RESET0 */
+#define RESET_AM2AXI_VAD 1
+#define RESET_PSRAM 4
+#define RESET_PAD_CTRL 5
+#define RESET_TEMP_SENSOR 7
+#define RESET_AM2AXI_DEV 8
+#define RESET_SPICC_A 10
+#define RESET_MSR_CLK 11
+#define RESET_AUDIO 12
+#define RESET_ANALOG_CTRL 13
+#define RESET_SAR_ADC 14
+#define RESET_AUDIO_VAD 15
+#define RESET_CEC 16
+#define RESET_PWM_EF 17
+#define RESET_PWM_CD 18
+#define RESET_PWM_AB 19
+#define RESET_IR_CTRL 21
+#define RESET_I2C_S_A 22
+#define RESET_I2C_M_D 24
+#define RESET_I2C_M_C 25
+#define RESET_I2C_M_B 26
+#define RESET_I2C_M_A 27
+#define RESET_I2C_PROD_AHB 28
+#define RESET_I2C_PROD 29
+
+/* RESET1 */
+#define RESET_ACODEC 32
+#define RESET_DMA 33
+#define RESET_SD_EMMC_A 34
+#define RESET_USBCTRL 36
+#define RESET_USBPHY 38
+#define RESET_RSA 42
+#define RESET_DMC 43
+#define RESET_IRQ_CTRL 45
+#define RESET_NIC_VAD 47
+#define RESET_NIC_AXI 48
+#define RESET_RAMA 49
+#define RESET_RAMB 50
+#define RESET_ROM 53
+#define RESET_SPIFC 54
+#define RESET_GIC 55
+#define RESET_UART_C 56
+#define RESET_UART_B 57
+#define RESET_UART_A 58
+#define RESET_OSC_RING 59
+
+/* RESET2 Reserved */
+
+#endif
--
2.7.4
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* [PATCH 1/3] arm64: dts: meson: add reset controller for Meson-A1 SoC
From: Xingyu Chen @ 2019-09-18 12:12 UTC (permalink / raw)
To: Philipp Zabel, Kevin Hilman
Cc: devicetree, Hanjie Lin, Jianxin Pan, Neil Armstrong, linux-kernel,
Rob Herring, linux-arm-kernel, linux-amlogic, Xingyu Chen,
Jerome Brunet
In-Reply-To: <1568808746-1153-1-git-send-email-xingyu.chen@amlogic.com>
Add the reset controller device of Meson-A1 SoC family
Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com>
---
arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
index 7210ad0..1c588ab 100644
--- a/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-a1.dtsi
@@ -74,6 +74,12 @@
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>;
+ reset: reset-controller@0 {
+ compatible = "amlogic,meson-a1-reset";
+ reg = <0x0 0x0 0x0 0x8c>;
+ #reset-cells = <1>;
+ };
+
uart_AO: serial@1c00 {
compatible = "amlogic,meson-gx-uart",
"amlogic,meson-ao-uart";
--
2.7.4
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* [PATCH 0/3] reset: meson: add Meson-A1 SoC support
From: Xingyu Chen @ 2019-09-18 12:12 UTC (permalink / raw)
To: Philipp Zabel, Kevin Hilman
Cc: devicetree, Hanjie Lin, Jianxin Pan, Neil Armstrong, linux-kernel,
Rob Herring, linux-arm-kernel, linux-amlogic, Xingyu Chen,
Jerome Brunet
This patchset adds support for Meson-A1 SoC Reset Controller. A new struct
meson_reset_param is introduced to describe the register differences between
Meson-A1 and previous SoCs
This patchset is based on A1 DTBv4[1].
[1] https://lore.kernel.org/linux-amlogic/1568276370-54181-1-git-send-email-jianxin.pan@amlogic.com
Xingyu Chen (3):
arm64: dts: meson: add reset controller for Meson-A1 SoC
dt-bindings: reset: add bindings for the Meson-A1 SoC Reset Controller
reset: add support for the Meson-A1 SoC Reset Controller
.../bindings/reset/amlogic,meson-reset.txt | 4 +-
arch/arm64/boot/dts/amlogic/meson-a1.dtsi | 6 +++
drivers/reset/reset-meson.c | 35 ++++++++++---
include/dt-bindings/reset/amlogic,meson-a1-reset.h | 59 ++++++++++++++++++++++
4 files changed, 95 insertions(+), 9 deletions(-)
create mode 100644 include/dt-bindings/reset/amlogic,meson-a1-reset.h
--
2.7.4
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* [PATCH] media: dt-bindings: Fix building error for dt_binding_check
From: Pragnesh Patel @ 2019-09-18 12:01 UTC (permalink / raw)
To: mripard
Cc: Mark Rutland, devicetree, linux-kernel, Chen-Yu Tsai, Rob Herring,
linux-arm-kernel, Mauro Carvalho Chehab, Pragnesh Patel,
linux-media
$id doesn't match the actual filename, so update the $id
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
---
Documentation/devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml b/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml
index 27f38ee..5dd1cf49 100644
--- a/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml
+++ b/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-csi.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
-$id: http://devicetree.org/schemas/arm/allwinner,sun4i-a10-csi.yaml#
+$id: http://devicetree.org/schemas/media/allwinner,sun4i-a10-csi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner A10 CMOS Sensor Interface (CSI) Device Tree Bindings
--
2.7.4
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* Re: [RFC PATCH 2/2] dt-bindings: pwm: Convert Samsung PWM bindings to json-schema
From: Krzysztof Kozlowski @ 2019-09-18 11:53 UTC (permalink / raw)
To: Rob Herring
Cc: Mark Rutland, linux-pwm, linux-samsung-soc@vger.kernel.org,
Maciej Falkowski, devicetree, linux-kernel@vger.kernel.org,
Thierry Reding, linux-leds, linux-clk, linux-arm-kernel
In-Reply-To: <20190912175001.GA29884@bogus>
On Fri, 13 Sep 2019 at 16:36, Rob Herring <robh@kernel.org> wrote:
>
> On Mon, Sep 09, 2019 at 08:34:36PM +0200, Krzysztof Kozlowski wrote:
> > Convert Samsung PWM (S3C, S5P and Exynos SoCs) bindings to DT schema
> > format using json-schema.
> >
> > Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> > ---
> > .../devicetree/bindings/pwm/pwm-samsung.txt | 51 --------
> > .../devicetree/bindings/pwm/pwm-samsung.yaml | 111 ++++++++++++++++++
> > 2 files changed, 111 insertions(+), 51 deletions(-)
> > delete mode 100644 Documentation/devicetree/bindings/pwm/pwm-samsung.txt
> > create mode 100644 Documentation/devicetree/bindings/pwm/pwm-samsung.yaml
>
>
> > diff --git a/Documentation/devicetree/bindings/pwm/pwm-samsung.yaml b/Documentation/devicetree/bindings/pwm/pwm-samsung.yaml
> > new file mode 100644
> > index 000000000000..90fb467bcdd5
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pwm/pwm-samsung.yaml
> > @@ -0,0 +1,111 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/pwm/pwm-samsung.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Samsung SoC PWM timers
> > +
> > +maintainers:
> > + - Thierry Reding <thierry.reding@gmail.com>
> > + - Krzysztof Kozlowski <krzk@kernel.org>
> > +
> > +description: |+
> > + Samsung SoCs contain PWM timer blocks which can be used for system clock source
> > + and clock event timers, as well as to drive SoC outputs with PWM signal. Each
> > + PWM timer block provides 5 PWM channels (not all of them can drive physical
> > + outputs - see SoC and board manual).
> > +
> > + Be aware that the clocksource driver supports only uniprocessor systems.
> > +
> > +allOf:
> > + - $ref: pwm.yaml#
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - samsung,s3c2410-pwm # 16-bit, S3C24xx
> > + - samsung,s3c6400-pwm # 32-bit, S3C64xx
> > + - samsung,s5p6440-pwm # 32-bit, S5P64x0
> > + - samsung,s5pc100-pwm # 32-bit, S5PC100, S5PV210, Exynos4210 rev0 SoCs
> > + - samsung,exynos4210-pwm # 32-bit, Exynos
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + clocks:
> > + minItems: 1
> > + maxItems: 3
> > +
> > + clock-names:
> > + description: |
> > + Should contain all following required clock names:
> > + - "timers" - PWM base clock used to generate PWM signals,
> > + and any subset of following optional clock names:
> > + - "pwm-tclk0" - first external PWM clock source,
> > + - "pwm-tclk1" - second external PWM clock source.
> > + Note that not all IP variants allow using all external clock sources.
> > + Refer to SoC documentation to learn which clock source configurations
> > + are available.
> > + oneOf:
> > + - items:
> > + - const: "timers"
> > + - items:
> > + - const: "timers"
> > + - const: "pwm-tclk0"
> > + - items:
> > + - const: "timers"
> > + - const: "pwm-tclk1"
> > + - items:
> > + - const: "timers"
> > + - const: "pwm-tclk0"
> > + - const: "pwm-tclk1"
> > +
> > + interrupts:
> > + description:
> > + One interrupt per timer, starting at timer 0.
> > + minItems: 1
> > + maxItems: 5
> > +
> > + "#pwm-cells":
> > + description:
> > + The only third cell flag supported by this binding
> > + is PWM_POLARITY_INVERTED.
> > + const: 3
> > +
> > + samsung,pwm-outputs:
> > + description:
> > + A list of PWM channels used as PWM outputs on particular platform.
> > + It is an array of up to 5 elements being indices of PWM channels
> > + (from 0 to 4), the order does not matter.
> > + # TODO: Values should not repeat
>
> uniqueItems: true
>
> Though it looks like we have to enable that keyword. (As silently
> ignoring unknown keywords (such as typos) is 'feature' of json-schema,
> we explicitly list keywords we use.)
This works fine.
>
> > + allOf:
> > + - $ref: /schemas/types.yaml#/definitions/uint32-array
> > + # FIXME: min/max limit of items does not work
> > + - items:
> > + minItems: 1
> > + maxItems: 5
> > + - items:
> > + minimum: 0
> > + maximum: 4
>
> I think you want:
>
> minItems: 1
> maxItems: 2
> items:
> minimum: 0
> maximum: 4
This not. However I figured out it is not needed. Since these are
unique values from 0 to 4, then the size of array cannot be longer
than 5 or shorter than 1.
Best regards,
Krzysztof
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* Re: [PATCH v6 2/4] drm: dw-hdmi-i2s: Use fixed id for codec device
From: Cheng-yi Chiang @ 2019-09-18 11:52 UTC (permalink / raw)
To: Jerome Brunet
Cc: moderated list:SOUND - SOC LAYER / DYNAMIC AUDIO POWER MANAGEM...,
Heiko Stuebner, Neil Armstrong, David Airlie, dri-devel,
linux-kernel, Hans Verkuil, Andrzej Hajda, Laurent Pinchart,
Takashi Iwai, linux-rockchip, Dylan Reid, tzungbi, Jonas Karlman,
Liam Girdwood, Russell King, Mark Brown, Jaroslav Kysela,
linux-arm-kernel, Jernej Skrabec, Doug Anderson, Daniel Vetter
In-Reply-To: <1j7e663sfu.fsf@starbuckisacylon.baylibre.com>
On Wed, Sep 18, 2019 at 4:43 PM Jerome Brunet <jbrunet@baylibre.com> wrote:
>
>
> On Wed 18 Sep 2019 at 10:24, Cheng-Yi Chiang <cychiang@chromium.org> wrote:
>
> > The problem of using auto ID is that the device name will be like
> > hdmi-audio-codec.<id number>.auto.
> >
> > The number might be changed when there are other platform devices being
> > created before hdmi-audio-codec device.
> > Use a fixed name so machine driver can set codec name on the DAI link.
> >
> > Using the fixed name should be fine because there will only be one
> > hdmi-audio-codec device.
>
> While this is true all platforms we know of (I suppose), It might not be
> the case later on. I wonder if making such assumption is really
> desirable in a code which is used by quite a few different platforms.
>
> Instead of trying to predict what the device name will be, can't you just
> query it in your machine driver ? Using a device tree phandle maybe ?
>
> It is quite usual to set the dai links this way, "simple-card" is a good
> example of this.
>
Hi Jerome,
Thanks for the quick reply!
And thanks for pointing this out.
I found that
soc_component_to_node searches upward for one layer so it can find the
node which creates hdmi-audio-codec in runtime. This works even that
hdmi-audio-codec does not have its own node in dts.
I will change accordingly in v7.
Thanks!
> >
> > Fix the codec name in rockchip rk3288_hdmi_analog machine driver.
> >
> > Signed-off-by: Cheng-Yi Chiang <cychiang@chromium.org>
> > ---
> > drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c | 2 +-
> > sound/soc/rockchip/rk3288_hdmi_analog.c | 3 ++-
> > 2 files changed, 3 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c
> > index d7e65c869415..86bd482b9f94 100644
> > --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c
> > +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-i2s-audio.c
> > @@ -193,7 +193,7 @@ static int snd_dw_hdmi_probe(struct platform_device *pdev)
> >
> > memset(&pdevinfo, 0, sizeof(pdevinfo));
> > pdevinfo.parent = pdev->dev.parent;
> > - pdevinfo.id = PLATFORM_DEVID_AUTO;
> > + pdevinfo.id = PLATFORM_DEVID_NONE;
> > pdevinfo.name = HDMI_CODEC_DRV_NAME;
> > pdevinfo.data = &pdata;
> > pdevinfo.size_data = sizeof(pdata);
> > diff --git a/sound/soc/rockchip/rk3288_hdmi_analog.c b/sound/soc/rockchip/rk3288_hdmi_analog.c
> > index 767700c34ee2..8286025a8747 100644
> > --- a/sound/soc/rockchip/rk3288_hdmi_analog.c
> > +++ b/sound/soc/rockchip/rk3288_hdmi_analog.c
> > @@ -15,6 +15,7 @@
> > #include <linux/gpio.h>
> > #include <linux/of_gpio.h>
> > #include <sound/core.h>
> > +#include <sound/hdmi-codec.h>
> > #include <sound/jack.h>
> > #include <sound/pcm.h>
> > #include <sound/pcm_params.h>
> > @@ -142,7 +143,7 @@ static const struct snd_soc_ops rk_ops = {
> > SND_SOC_DAILINK_DEFS(audio,
> > DAILINK_COMP_ARRAY(COMP_EMPTY()),
> > DAILINK_COMP_ARRAY(COMP_CODEC(NULL, NULL),
> > - COMP_CODEC("hdmi-audio-codec.2.auto", "i2s-hifi")),
> > + COMP_CODEC(HDMI_CODEC_DRV_NAME, "i2s-hifi")),
> > DAILINK_COMP_ARRAY(COMP_EMPTY()));
> >
> > static struct snd_soc_dai_link rk_dailink = {
>
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* [PATCH v3] pinctrl: at91-pio4: implement .get_multiple and .set_multiple
From: Alexandre Belloni @ 2019-09-18 11:36 UTC (permalink / raw)
To: Linus Walleij
Cc: Alexandre Belloni, linux-kernel, linux-gpio, Ludovic Desroches,
Claudiu.Beznea, linux-arm-kernel
Implement .get_multiple and .set_multiple to allow reading or setting
multiple pins simultaneously. Pins in the same bank will all be switched at
the same time, improving synchronization and performances.
Keep the driver future proof by allowing its use on 64bits platforms if
they ever appear with this IP and we end up with a mismatch between
ATMEL_PIO_NPINS_PER_BANK and BITS_PER_LONG.
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com>
---
Changes in v3:
- Add ack from ludovic
- add comment and amend commit message to explain the ifdefd
drivers/pinctrl/pinctrl-at91-pio4.c | 62 +++++++++++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c
index d6de4d360cd4..e380202eb86a 100644
--- a/drivers/pinctrl/pinctrl-at91-pio4.c
+++ b/drivers/pinctrl/pinctrl-at91-pio4.c
@@ -328,6 +328,33 @@ static int atmel_gpio_get(struct gpio_chip *chip, unsigned offset)
return !!(reg & BIT(pin->line));
}
+static int atmel_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
+ unsigned long *bits)
+{
+ struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
+ unsigned int bank;
+
+ bitmap_zero(bits, atmel_pioctrl->npins);
+
+ for (bank = 0; bank < atmel_pioctrl->nbanks; bank++) {
+ unsigned int word = bank;
+ unsigned int offset = 0;
+ unsigned int reg;
+
+#if ATMEL_PIO_NPINS_PER_BANK != BITS_PER_LONG
+ word = BIT_WORD(bank * ATMEL_PIO_NPINS_PER_BANK);
+ offset = bank * ATMEL_PIO_NPINS_PER_BANK % BITS_PER_LONG;
+#endif
+ if (!mask[word])
+ continue;
+
+ reg = atmel_gpio_read(atmel_pioctrl, bank, ATMEL_PIO_PDSR);
+ bits[word] |= mask[word] & (reg << offset);
+ }
+
+ return 0;
+}
+
static int atmel_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
int value)
{
@@ -358,11 +385,46 @@ static void atmel_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
BIT(pin->line));
}
+static void atmel_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask,
+ unsigned long *bits)
+{
+ struct atmel_pioctrl *atmel_pioctrl = gpiochip_get_data(chip);
+ unsigned int bank;
+
+ for (bank = 0; bank < atmel_pioctrl->nbanks; bank++) {
+ unsigned int bitmask;
+ unsigned int word = bank;
+
+/*
+ * On a 64-bit platform, BITS_PER_LONG is 64 so it is necessary to iterate over
+ * two 32bit words to handle the whole bitmask
+ */
+#if ATMEL_PIO_NPINS_PER_BANK != BITS_PER_LONG
+ word = BIT_WORD(bank * ATMEL_PIO_NPINS_PER_BANK);
+#endif
+ if (!mask[word])
+ continue;
+
+ bitmask = mask[word] & bits[word];
+ atmel_gpio_write(atmel_pioctrl, bank, ATMEL_PIO_SODR, bitmask);
+
+ bitmask = mask[word] & ~bits[word];
+ atmel_gpio_write(atmel_pioctrl, bank, ATMEL_PIO_CODR, bitmask);
+
+#if ATMEL_PIO_NPINS_PER_BANK != BITS_PER_LONG
+ mask[word] >>= ATMEL_PIO_NPINS_PER_BANK;
+ bits[word] >>= ATMEL_PIO_NPINS_PER_BANK;
+#endif
+ }
+}
+
static struct gpio_chip atmel_gpio_chip = {
.direction_input = atmel_gpio_direction_input,
.get = atmel_gpio_get,
+ .get_multiple = atmel_gpio_get_multiple,
.direction_output = atmel_gpio_direction_output,
.set = atmel_gpio_set,
+ .set_multiple = atmel_gpio_set_multiple,
.to_irq = atmel_gpio_to_irq,
.base = 0,
};
--
2.21.0
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