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* RE: [RFC PATCH 18/18] net: wireguard - switch to crypto API for packet encryption
From: Pascal Van Leeuwen @ 2019-09-26  9:40 UTC (permalink / raw)
  To: Linus Torvalds, Ard Biesheuvel
  Cc: Jason A . Donenfeld, Catalin Marinas, Herbert Xu, Arnd Bergmann,
	Eric Biggers, Greg KH, Samuel Neves, Linux Crypto Mailing List,
	Andy Lutomirski, Marc Zyngier, Dan Carpenter, Will Deacon,
	David Miller, Linux ARM
In-Reply-To: <CAHk-=wjYsbxSiV_XKWV3BwGvau_hUvQiQHLOoc7vLUZt0Wqzfw@mail.gmail.com>

> >
> > Replace the chacha20poly1305() library calls with invocations of the
> > RFC7539 AEAD, as implemented by the generic chacha20poly1305 template.
> 
> Honestly, the other patches look fine to me from what I've seen (with
> the small note I had in a separate email for 11/18), but this one I
> consider just nasty, and a prime example of why people hate those
> crypto lookup routines.
> 
> Some of it is just the fundamental and pointless silly indirection,
> that just makes things harder to read, less efficient, and less
> straightforward.
> 
> That's exemplified by this part of the patch:
> 
> >  struct noise_symmetric_key {
> > -       u8 key[NOISE_SYMMETRIC_KEY_LEN];
> > +       struct crypto_aead *tfm;
> 
> which is just one of those "we know what we want and we just want to
> use it directly" things, and then the crypto indirection comes along
> and makes that simple inline allocation of a small constant size
> (afaik it is CHACHA20POLY1305_KEY_SIZE, which is 32) be another
> allocation entirely.
> 
> And it's some random odd non-typed thing too, so then you have that
> silly and stupid dynamic allocation using a name lookup:
> 
>    crypto_alloc_aead("rfc7539(chacha20,poly1305)", 0, CRYPTO_ALG_ASYNC);
> 
> to create what used to be (and should be) a simple allocation that was
> has a static type and was just part of the code.
> 
While I agree with the principle of first merging Wireguard without 
hooking it up to the Crypto API and doing the latter in a later,
separate patch, I DONT'T agree with your bashing of the Crypto API
or HW crypto acceleration in general.

Yes, I do agree  that if you need to do the occasional single crypto 
op for a fixed algorithm on a small amount of data then you should
just use a simple direct  library call. I'm all for a Zinc type 
library for that.
(and I believe Ard is actually actively making such changes already)

However, if you're doing bulk crypto like network packet processing
(as Wireguard does!) or disk/filesystem encryption, then that cipher
allocation only happens once every blue moon and the overhead for
that is totally *irrelevant* as it is amortized over many hours or 
days of runtime.

While I generally dislike this whole hype of storing stuff in
textual formats like XML and JSON and then wasting lots of CPU
cycles on parsing that, I've learned to appreciate the power of
these textual Crypto API templates, as they allow a hardware 
accelerator to advertise complex combined operations as single
atomic calls, amortizing the communication overhead between SW
and HW. It's actually very flexible and powerful!

> It also ends up doing other bad things, ie that packet-time
> 
> +       if (unlikely(crypto_aead_reqsize(key->tfm) > 0)) {
> +               req = aead_request_alloc(key->tfm, GFP_ATOMIC);
> +               if (!req)
> +                       return false;
> 
> thing that hopefully _is_ unlikely, but that's just more potential
> breakage from that whole async crypto interface.
> 
> This is what people do *not* want to do, and why people often don't
> like the crypto interfaces.
> 
Life is all about needing to do things you don't like to do ...
If you want the performance, you need to do the effort. That simple.
HW acceleration surely won't work from a naive synchronous interface.
(Same applies to running crypto in a separate thread on the CPU BTW!)

In any case, Wireguard bulk crypto *should* eventually run on top
of Crypto API such that it can leverage *existing* HW acceleration.
It would be incredibly silly not to do so, given the HW exists!

> And I'm still not convinced (a) ever makes sense - the overhead of any
> accelerator is just high enought that I doubt you'll have numbers -
> performance _or_ power.
> 
You shouldn't make such assertions if you obviously don't know what
you're talking about. Yes, there is significant overhead on the CPU
for doing lookaside crypto, but it's (usually) nothing compared to
doing the actual crypto itself on the CPU barring a few exceptions. 
(Notably AES-GCM or AES-CTR on ARM64 or x64 CPU's and *maybe* 
Chacha-Poly on recent Intel CPU's - but there's a *lot* more crypto 
being used out there than just AES-GCM and Chacha-Poly, not to 
mention a lot more less capable (embedded) CPU's running Linux)

For anything but those exceptions, we blow even the fastest Intel
server CPU's out of the water with our crypto accelerators.
(I can bore you with some figures actually measured with the
Crypto API on our HW, once I'm done optimizing the driver and I 
have some time to collect the results)

And in any case, for somewhat larger blocks/packets, the overhead
on the CPU would at least be such that it's less than what the CPU
would need to do the crypto itself - even if it's faster - such that
there is room there to do *other*, presumably more useful, work.

Then there's indeed the power consumption issue, which is complex
because crypto power != total system power so it depends too much on
the actual use case to make generic statements on it. So I'll leave
that with the remark that Intel server CPU's have to seriously
throttle down their clock if you start using AVX512 for crypto, just to
stay within their power budget, while we can do the same performance
(~200 Gbps) in just a few (~2) Watts on a similar technology node.
(excluding the CPU management overhead, but that surely won't consume
excessive power like AVX512)

> But even if you're right that it might be a power advantage on some
> platform, that wouldn't make it an advantage on other platforms. Maybe
> it could be done as a config option where you can opt in to the async
> interface when that makes sense - but not force the indirection and
> extra allocations when it doesn't. As a separate patch, something like
> that doesn't sound horrendous (and I think that's also an argument for
> doing that CPU->LE change as an independent change).
> 
Making it a switch sounds good to me though.

Regards,
Pascal van Leeuwen
Silicon IP Architect, Multi-Protocol Engines @ Verimatrix
www.insidesecure.com
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* Re: [PATCH v3 4/5] media: v4l2-ctrl: Add jpeg enc exif mode control
From: Hans Verkuil @ 2019-09-26  9:27 UTC (permalink / raw)
  To: Xia Jiang, Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
	Rick Chang
  Cc: devicetree, srv_heupstream, linux-kernel, Tomasz Figa,
	linux-mediatek, linux-media, linux-arm-kernel, Marek Szyprowski
In-Reply-To: <20190924074303.22713-5-xia.jiang@mediatek.com>

On 9/24/19 9:43 AM, Xia Jiang wrote:
> Add jpeg enc CID definition for exif mode control.
> 
> Signed-off-by: Xia Jiang <xia.jiang@mediatek.com>
> ---
> v3: new add patch for V4L2_CID_JPEG_ENABLE_EXIF
> ---
>  Documentation/media/uapi/v4l/ext-ctrls-jpeg.rst | 10 ++++++++++
>  drivers/media/v4l2-core/v4l2-ctrls.c            |  1 +
>  include/uapi/linux/v4l2-controls.h              |  2 ++
>  3 files changed, 13 insertions(+)
> 
> diff --git a/Documentation/media/uapi/v4l/ext-ctrls-jpeg.rst b/Documentation/media/uapi/v4l/ext-ctrls-jpeg.rst
> index 60ce3f949319..d44a539e2eb4 100644
> --- a/Documentation/media/uapi/v4l/ext-ctrls-jpeg.rst
> +++ b/Documentation/media/uapi/v4l/ext-ctrls-jpeg.rst
> @@ -109,5 +109,15 @@ JPEG Control IDs
>  
>  
>  
> +``V4L2_CID_JPEG_ENABLE_EXIF (integer)``
> +    ``V4L2_CID_JPEG_ENABLE_EXIF (integer)`` control determines JPEG
> +    encoder mode. Its value of 0 means JPEG mode, 1 means EXIF mode. If
> +    EXIF mode is enabled, the JPEG encoder will not write out SOI marker
> +    (start from 0xffd8) but write out from DQT marker(start from
> +    0xffdb). Software program can fill the EXIF content above the DQT
> +    marker to finish one EXIF JPEG.

I'm trying to understand what happens if this is set to 1. It looks like
the only difference is that the SOI marker (first two bytes) is not present,
but the compressed image starts directly with the DQT marker, right?

If that's the case, then I think it would make a lot more sense to support
the V4L2_CID_JPEG_ACTIVE_MARKER control and add the SOI to the active markers.

Regards,

	Hans

> +
> +
> +
>  For more details about JPEG specification, refer to :ref:`itu-t81`,
>  :ref:`jfif`, :ref:`w3c-jpeg-jfif`.
> diff --git a/drivers/media/v4l2-core/v4l2-ctrls.c b/drivers/media/v4l2-core/v4l2-ctrls.c
> index 371537dd8cd3..c96c10480ebd 100644
> --- a/drivers/media/v4l2-core/v4l2-ctrls.c
> +++ b/drivers/media/v4l2-core/v4l2-ctrls.c
> @@ -1025,6 +1025,7 @@ const char *v4l2_ctrl_get_name(u32 id)
>  	case V4L2_CID_JPEG_RESTART_INTERVAL:	return "Restart Interval";
>  	case V4L2_CID_JPEG_COMPRESSION_QUALITY:	return "Compression Quality";
>  	case V4L2_CID_JPEG_ACTIVE_MARKER:	return "Active Markers";
> +	case V4L2_CID_JPEG_ENABLE_EXIF:		return "Enable Exif";
>  
>  	/* Image source controls */
>  	/* Keep the order of the 'case's the same as in v4l2-controls.h! */
> diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h
> index a2669b79b294..da619f43de65 100644
> --- a/include/uapi/linux/v4l2-controls.h
> +++ b/include/uapi/linux/v4l2-controls.h
> @@ -1022,6 +1022,8 @@ enum v4l2_jpeg_chroma_subsampling {
>  #define	V4L2_JPEG_ACTIVE_MARKER_DQT		(1 << 17)
>  #define	V4L2_JPEG_ACTIVE_MARKER_DHT		(1 << 18)
>  
> +#define	V4L2_CID_JPEG_ENABLE_EXIF		(V4L2_CID_JPEG_CLASS_BASE + 5)
> +
>  
>  /* Image source controls */
>  #define V4L2_CID_IMAGE_SOURCE_CLASS_BASE	(V4L2_CTRL_CLASS_IMAGE_SOURCE | 0x900)
> 


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* Re: [PATCH 1/2] kselftest: add capability to skip chosen TARGETS
From: Cristian Marussi @ 2019-09-26  9:26 UTC (permalink / raw)
  To: Tim.Bird, linux-kselftest, linux-arm-kernel, shuah; +Cc: dave.martin
In-Reply-To: <ECADFF3FD767C149AD96A924E7EA6EAF977BD152@USCULXMSG01.am.sony.com>

Hi Tim

thanks for the review.

On 25/09/2019 21:20, Tim.Bird@sony.com wrote:
> Just a few nits inline below.
> 
>> -----Original Message-----
>> From: Cristian Marussi on Wednesday, September 25, 2019 3:24 AM
>>
>> Let the user specify an optional TARGETS skiplist through the new optional
>> SKIP_TARGETS Makefile variable.
>>
>> It is easier to skip at will a reduced and well defined list of possibly
> 
> It seems like there's a word missing.
> at will a -> at will using a
> 
>> problematic targets with SKIP_TARGETS then to provide a partially stripped
> 
> then -> than
> 
>> down list of good targets using the usual TARGETS variable.
>>
>> Signed-off-by: Cristian Marussi <cristian.marussi@arm.com>
>> ---
>>  tools/testing/selftests/Makefile | 4 ++++
>>  1 file changed, 4 insertions(+)
>>
>> diff --git a/tools/testing/selftests/Makefile
>> b/tools/testing/selftests/Makefile
>> index 25b43a8c2b15..103936faa46d 100644
>> --- a/tools/testing/selftests/Makefile
>> +++ b/tools/testing/selftests/Makefile
>> @@ -132,6 +132,10 @@ else
>>  		ARCH=$(ARCH) -C $(top_srcdir) headers_install
>>  endif
>>
>> +# User can optionally provide a TARGETS skiplist.
>> +SKIP_TARGETS ?=
>> +TARGETS := $(filter-out $(SKIP_TARGETS), $(TARGETS))
>> +
>>  all: khdr
>>  	@for TARGET in $(TARGETS); do		\
>>  		BUILD_TARGET=$$BUILD/$$TARGET;	\
>> --
>> 2.17.1
> 
> Great feature!  Thanks.
>  -- Tim
> 

I'll fix all in V2.

Thanks

Cristian


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* Re: [PATCH 1/2] kselftest: add capability to skip chosen TARGETS
From: Cristian Marussi @ 2019-09-26  9:24 UTC (permalink / raw)
  To: shuah, linux-kselftest, linux-arm-kernel; +Cc: dave.martin
In-Reply-To: <e8848069-124d-a236-30c9-b8915471db16@kernel.org>

On 25/09/2019 20:36, shuah wrote:
> On 9/25/19 7:24 AM, Cristian Marussi wrote:
>> Let the user specify an optional TARGETS skiplist through the new optional
>> SKIP_TARGETS Makefile variable.
>>
>> It is easier to skip at will a reduced and well defined list of possibly
>> problematic targets with SKIP_TARGETS then to provide a partially stripped
>> down list of good targets using the usual TARGETS variable.
>>
>> Signed-off-by: Cristian Marussi <cristian.marussi@arm.com>
>> ---
>>   tools/testing/selftests/Makefile | 4 ++++
>>   1 file changed, 4 insertions(+)
>>
>> diff --git a/tools/testing/selftests/Makefile b/tools/testing/selftests/Makefile
>> index 25b43a8c2b15..103936faa46d 100644
>> --- a/tools/testing/selftests/Makefile
>> +++ b/tools/testing/selftests/Makefile
>> @@ -132,6 +132,10 @@ else
>>   		ARCH=$(ARCH) -C $(top_srcdir) headers_install
>>   endif
>>   
>> +# User can optionally provide a TARGETS skiplist.
>> +SKIP_TARGETS ?=
>> +TARGETS := $(filter-out $(SKIP_TARGETS), $(TARGETS))
>> +
>>   all: khdr
>>   	@for TARGET in $(TARGETS); do		\
>>   		BUILD_TARGET=$$BUILD/$$TARGET;	\
>>
> 
> Thanks for doing this. This looks good to me. Would you like to
> update the documentation file?
> 

Thanks for the review Shuah, I'll add doc and fixes in V2
with a proper cover letter

Thanks

Cristian
> thanks,
> -- Shuah
> 


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* RE: [PATCH v9 1/3] arm64: cpufeature: introduce helper cpu_has_hw_af()
From: Justin He (Arm Technology China) @ 2019-09-26  9:23 UTC (permalink / raw)
  To: Catalin Marinas
  Cc: Mark Rutland, Kaly Xin (Arm Technology China), Ralph Campbell,
	Andrew Morton, Suzuki Poulose, Marc Zyngier, Anshuman Khandual,
	linux-kernel@vger.kernel.org, Matthew Wilcox, linux-mm@kvack.org,
	Jérôme Glisse, James Morse,
	linux-arm-kernel@lists.infradead.org, Punit Agrawal,
	hejianet@gmail.com, Thomas Gleixner, nd, Will Deacon,
	Alex Van Brunt, Kirill A. Shutemov, Robin Murphy
In-Reply-To: <20190925143820.GF7042@arrakis.emea.arm.com>

Hi Catalin

> -----Original Message-----
> From: Catalin Marinas <catalin.marinas@arm.com>
> Sent: 2019年9月25日 22:38
> To: Justin He (Arm Technology China) <Justin.He@arm.com>
> Cc: Will Deacon <will@kernel.org>; Mark Rutland
> <Mark.Rutland@arm.com>; James Morse <James.Morse@arm.com>; Marc
> Zyngier <maz@kernel.org>; Matthew Wilcox <willy@infradead.org>; Kirill A.
> Shutemov <kirill.shutemov@linux.intel.com>; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org; linux-
> mm@kvack.org; Suzuki Poulose <Suzuki.Poulose@arm.com>; Punit
> Agrawal <punitagrawal@gmail.com>; Anshuman Khandual
> <Anshuman.Khandual@arm.com>; Alex Van Brunt
> <avanbrunt@nvidia.com>; Robin Murphy <Robin.Murphy@arm.com>;
> Thomas Gleixner <tglx@linutronix.de>; Andrew Morton <akpm@linux-
> foundation.org>; Jérôme Glisse <jglisse@redhat.com>; Ralph Campbell
> <rcampbell@nvidia.com>; hejianet@gmail.com; Kaly Xin (Arm Technology
> China) <Kaly.Xin@arm.com>; nd <nd@arm.com>
> Subject: Re: [PATCH v9 1/3] arm64: cpufeature: introduce helper
> cpu_has_hw_af()
> 
> On Wed, Sep 25, 2019 at 10:59:20AM +0800, Jia He wrote:
> > We unconditionally set the HW_AFDBM capability and only enable it on
> > CPUs which really have the feature. But sometimes we need to know
> > whether this cpu has the capability of HW AF. So decouple AF from
> > DBM by new helper cpu_has_hw_af().
> >
> > Signed-off-by: Jia He <justin.he@arm.com>
> > Suggested-by: Suzuki Poulose <Suzuki.Poulose@arm.com>
> > Reported-by: kbuild test robot <lkp@intel.com>
> 
> Which bug did the kbuild robot actually report? I'd drop this line.
> 
This line is added due to [1]:
"If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>"

Yes, I know your concern, it is a little bit confusing. But I don't know
how to distinguish the case btw a) original bug report b) bug report
of my patch implementation? Thanks for any suggestion.

[1] https://www.lkml.org/lkml/2019/9/18/940


--
Cheers,
Justin (Jia He)


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* RE: [PATCH v1] ARM: Add support for Realtek SOC
From: James Tai @ 2019-09-26  9:21 UTC (permalink / raw)
  To: Andreas Färber, 'Masahiro Yamada',
	'Arnd Bergmann'
  Cc: 'Jason A . Donenfeld',
	linux-realtek-soc@lists.infradead.org,
	CY_Huang[黃鉦晏], 'Linus Walleij',
	'Stefan Agner', 'Benjamin Gaignard',
	Simon Hsu[徐文翰],
	'Mauro Carvalho Chehab',
	Tom Ting[丁郁庭],
	Jim Tsai [蔡維晉], Phinex Hung,
	Edward Wu[吳奕寬], 'Rob Herring',
	'Lorenzo Pieralisi', 'Russell King',
	'Mike Rapoport', YH_Hsieh[謝宇勳],
	TY_Chang[張子逸], 'Thierry Reding',
	'jamestai.sky@gmail.com',
	ZR_Chen[陳振榮], Hau, Yukuen,
	Jinn.Cheng[鄭才進],
	Chase Yen [顏呈育],
	Stanley Chang[昌育德], 'Doug Anderson',
	'Linux ARM', Eric Wang[王偉全], Adklei,
	Edgar Lee [李承諭], 'Ard Biesheuvel',
	PK.Chuang [莊博凱], 'Nicolas Pitre',
	'Nick Desaulniers',
	'linux-kernel@vger.kernel.org', 'Paul Burton',
	phelic
In-Reply-To: <4f5c99ddfbe0abadccf754e9ff282c39d8849b3f.camel@suse.de>

> Subject: Re: [PATCH v1] ARM: Add support for Realtek SOC
> 
> Hi James,
> 
> Am Mittwoch, den 25.09.2019, 06:43 +0000 schrieb James Tai:
> > From: "james.tai" <james.tai@realtek.com>
> >
> > This patch adds the basic machine file for the Realtek RTD16XX and
> > RTD13XX platform.
> >
> > Signed-off-by: james.tai <james.tai@realtek.com>
> > ---
> > Changes since last version:
> > 	- Add RTD13XX platform.
> > 	- Add PSCI support.
> > 	- Add ARCH_MULTI_V7 config.
> > 	- remove 'textofs-$(CONFIG_ARCH_REALTEK) := 0x00208000' from
> > 	  'arch/arm/Makefile'.
> > 	- remove map_io,init_time,init_machine and smp_init from machine
> > 	  descriptor.
> 
> Thanks for your patch. Please subscribe yourself and colleagues to the existing
> linux-realtek-soc@lists.infradead.org mailing list and make sure it is in CC for
> your patches:
> 
> http://lists.infradead.org/mailman/listinfo/linux-realtek-soc

Hi Andreas,

Thanks for your reply.

I can't open the URL. 
Please check this URL is correct.
http://lists.infradead.org/mailman/listinfo/linux-realtek-soc

> Further comments inline:
> 
> > ---
> >  arch/arm/Kconfig                |  2 ++
> >  arch/arm/Makefile               |  1 +
> >  arch/arm/mach-realtek/Kconfig   | 20 +++++++++++++
> >  arch/arm/mach-realtek/Makefile  |  3 ++
> > arch/arm/mach-realtek/platsmp.c | 51
> > +++++++++++++++++++++++++++++++++
> >  arch/arm/mach-realtek/platsmp.h |  6 ++++
> > arch/arm/mach-realtek/realtek.c | 43 +++++++++++++++++++++++++++
> >  7 files changed, 126 insertions(+)
> >  create mode 100644 arch/arm/mach-realtek/Kconfig  create mode
> 100644
> > arch/arm/mach-realtek/Makefile  create mode 100644
> > arch/arm/mach-realtek/platsmp.c  create mode 100644
> > arch/arm/mach-realtek/platsmp.h  create mode 100644
> > arch/arm/mach-realtek/realtek.c
> 
> As Arnd has already expressed, at least RTD13xx (if not also RTD16xx?) is a
> 64-bit SoC, and we already have code - contributed and maintained by me - for
> arch/arm64/. Please contribute to those efforts instead of building your own
> sandcastle in arch/arm/. In fact, your work collides with patches queued in my
> rtd129x-next branch for RTD1195, an actual 32-bit platform. Among other
> commits:

OK. I understand.

We want to open source for our platforms.
The newly platforms source code should be patch to rtd129x-next branch? 
These platforms is included arm64 and arm.

> https://github.com/afaerber/linux/commit/b43fa4f790183d46e2b2c7f5af34f3
> 010d315073
> 
> Those previous arm64 RTD129x and arm RTD1195 efforts were and are
> blocked by irqchip, which I don't see addressed in this single patch.
> 
> https://github.com/afaerber/linux/commits/rtd1295-next

What kind of irq issue did you have with the development.
For rtd129x platform, I can't find the irq mux driver in 'drivers/irqchip'.

> >
> > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index
> > 33b00579beff..1f7967c97267 100644
> > --- a/arch/arm/Kconfig
> > +++ b/arch/arm/Kconfig
> > @@ -793,6 +793,8 @@ source "arch/arm/mach-realview/Kconfig"
> >
> >  source "arch/arm/mach-rockchip/Kconfig"
> >
> > +source "arch/arm/mach-realtek/Kconfig"
> 
> Ordering wrong.

OK. Thank you.

> > +
> >  source "arch/arm/mach-s3c24xx/Kconfig"
> >
> >  source "arch/arm/mach-s3c64xx/Kconfig"
> > diff --git a/arch/arm/Makefile b/arch/arm/Makefile index
> > c3624ca6c0bc..560ae7d72aab 100644
> > --- a/arch/arm/Makefile
> > +++ b/arch/arm/Makefile
> > @@ -205,6 +205,7 @@ machine-$(CONFIG_ARCH_RDA)		+= rda
> >  machine-$(CONFIG_ARCH_REALVIEW)		+= realview
> >  machine-$(CONFIG_ARCH_ROCKCHIP)		+= rockchip
> >  machine-$(CONFIG_ARCH_RPC)		+= rpc
> > +machine-$(CONFIG_ARCH_REALTEK)		+= realtek
> 
> Ditto.
> 
> >  machine-$(CONFIG_ARCH_S3C24XX)		+= s3c24xx
> >  machine-$(CONFIG_ARCH_S3C64XX)		+= s3c64xx
> >  machine-$(CONFIG_ARCH_S5PV210)		+= s5pv210
> > diff --git a/arch/arm/mach-realtek/Kconfig b/arch/arm/mach-
> > realtek/Kconfig new file mode 100644 index 000000000000..a638f4322bb2
> > --- /dev/null
> > +++ b/arch/arm/mach-realtek/Kconfig
> > @@ -0,0 +1,20 @@
> > +# SPDX-License-Identifier: GPL-2.0-only menuconfig ARCH_REALTEK
> > +	bool "Realtek SoC Support"
> > +	depends on ARCH_MULTI_V7
> > +	help
> > +	  Support for Realtek rtd16xx & rtd13xx SoCs.
> > +
> > +if ARCH_REALTEK
> > +
> > +config ARCH_RTD13XX
> > +	bool "Enable support for RTD1319"
> > +	select ARM_GIC_V3
> > +	select ARM_PSCI
> > +
> > +config ARCH_RTD16XX
> > +	bool "Enable support for RTD1619"
> > +	select ARM_GIC_V3
> > +	select ARM_PSCI
> > +
> > +endif
> > diff --git a/arch/arm/mach-realtek/Makefile b/arch/arm/mach-
> > realtek/Makefile new file mode 100644 index 000000000000..9cdc1f1f2917
> > --- /dev/null
> > +++ b/arch/arm/mach-realtek/Makefile
> > @@ -0,0 +1,3 @@
> > +# SPDX-License-Identifier: GPL-2.0-only
> > +obj-$(CONFIG_ARCH_REALTEK) += realtek.o
> > +obj-$(CONFIG_SMP) += platsmp.o
> > diff --git a/arch/arm/mach-realtek/platsmp.c b/arch/arm/mach-
> > realtek/platsmp.c new file mode 100644 index
> > 000000000000..b3fc99447ad4
> > --- /dev/null
> > +++ b/arch/arm/mach-realtek/platsmp.c
> > @@ -0,0 +1,51 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (c) 2019 Realtek Semiconductor Corp.
> > + */
> > +
> > +#include <linux/init.h>
> > +#include <linux/delay.h>
> > +#include <linux/jiffies.h>
> > +#include <linux/io.h>
> > +#include <linux/memory.h>
> > +#include <linux/smp.h>
> > +#include <linux/of.h>
> > +#include <linux/arm-smccc.h>
> > +#include <asm/smp_plat.h>
> > +#include <asm/cacheflush.h>
> > +#include <asm/cp15.h>
> > +#include <asm/barrier.h>
> > +
> > +#define BL31_CMD 0x8400ff04
> > +#define BL31_DAT 0x00001619
> > +#define CORE_PWRDN_EN 0x1
> > +
> > +#define CPUPWRCTLR __ACCESS_CP15(c15, 0, c2, 7)
> > +
> > +#ifdef CONFIG_HOTPLUG_CPU
> > +
> > +static void rtk_cpu_die(unsigned int cpu) {
> > +	struct arm_smccc_res res;
> > +	unsigned int cpu_pwr_ctrl;
> > +
> > +	/* notify BL31 cpu hotplug */
> > +	arm_smccc_smc(BL31_CMD, BL31_DAT, 0, 0, 0, 0, 0, 0, &res);
> 
> BL31 is clearly for 64-bit only and will not work for RTD1195, so the naming is
> much too generic.

OK. I will modify naming in new version patch.

> > +	v7_exit_coherency_flush(louis);
> > +
> > +	cpu_pwr_ctrl = read_sysreg(CPUPWRCTLR);
> > +	cpu_pwr_ctrl |= CORE_PWRDN_EN;
> > +	write_sysreg(cpu_pwr_ctrl, CPUPWRCTLR);
> > +
> > +	dsb(sy);
> > +
> > +	for (;;)
> > +		wfi();
> > +}
> > +#endif
> > +
> > +struct smp_operations rtk_smp_ops __initdata = { #ifdef
> > +CONFIG_HOTPLUG_CPU
> > +	.cpu_die = rtk_cpu_die,
> > +#endif
> > +};
> > diff --git a/arch/arm/mach-realtek/platsmp.h b/arch/arm/mach-
> > realtek/platsmp.h new file mode 100644 index
> > 000000000000..c9c4d712369c
> > --- /dev/null
> > +++ b/arch/arm/mach-realtek/platsmp.h
> > @@ -0,0 +1,6 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (c) 2019 Realtek Semiconductor Corp.
> > + */
> > +
> > +extern struct smp_operations rtk_smp_ops;
> > diff --git a/arch/arm/mach-realtek/realtek.c b/arch/arm/mach-
> > realtek/realtek.c new file mode 100644 index
> > 000000000000..2692ac53f59b
> > --- /dev/null
> > +++ b/arch/arm/mach-realtek/realtek.c
> > @@ -0,0 +1,43 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (c) 2019 Realtek Semiconductor Corp.
> > + */
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/clocksource.h>
> > +#include <linux/kernel.h>
> > +#include <linux/init.h>
> > +#include <linux/irqchip.h>
> > +#include <linux/of_address.h>
> > +#include <linux/of_irq.h>
> > +#include <linux/of_platform.h>
> > +#include <linux/io.h>
> > +#include <linux/memblock.h>
> > +#include <linux/delay.h>
> > +#include <linux/clockchips.h>
> > +#include <asm/mach/arch.h>
> > +#include <asm/mach/map.h>
> > +#include <asm/system_misc.h>
> > +#include <asm/system_info.h>
> > +
> > +#include "platsmp.h"
> > +
> > +static const char *const rtd13xx_board_dt_compat[] = {
> > +	"realtek,rtd1319",
> > +	NULL,
> > +};
> > +
> > +static const char *const rtd16xx_board_dt_compat[] = {
> > +	"realtek,rtd1619",
> > +	NULL,
> > +};
> > +
> > +DT_MACHINE_START(RTD13XX, "Realtek rtd13xx platform")
> > +	.dt_compat = rtd13xx_board_dt_compat,
> > +	.smp = smp_ops(rtk_smp_ops),
> > +MACHINE_END
> > +
> > +DT_MACHINE_START(RTD16XX, "Realtek rtd16xx platform")
> > +	.dt_compat = rtd16xx_board_dt_compat,
> > +	.smp = smp_ops(rtk_smp_ops),
> > +MACHINE_END
> 
> I recall that 32-bit arm SMP can be selected via the DT and then does not need
> multiple such structs per SoC, in particular they don't differ at all and could use
> the default machine taking the text from the DT.
>
> Also note that whenever possible I personally have a preference for
> GPL-2.0-or-later and licensed my code that way whenever possible.

OK. I understand.

> Question: Why are you not just implementing the above CPU logic in TF-A
> BL31 and let Linux use the existing PSCI code paths? That will be the only
> upstream-accepted solution for arm64.

For rtd129x platform, We don't implement PSCI in BL31, 
but our newly platforms(rtd139x/rtd13xx/rtd16xx) already implement PSCI in BL31.

> Thanks,
> Andreas
> 
> --
> SUSE Software Solutions Germany GmbH
> Maxfeldstr. 5, 90409 Nürnberg, Germany
> GF: Felix Imendörffer
> HRB 247165 (AG München)
> 
> 
> ------Please consider the environment before printing this e-mail.
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^ permalink raw reply

* Re: [PATCH v4 1/8] dt-bindings: timer: Convert Exynos MCT bindings to json-schema
From: Krzysztof Kozlowski @ 2019-09-26  9:20 UTC (permalink / raw)
  To: Marek Szyprowski
  Cc: Mark Rutland, devicetree, linux-samsung-soc, Sylwester Nawrocki,
	Daniel Lezcano, linux-kernel, Rob Herring, Andrzej Hajda,
	Kukjin Kim, Thomas Gleixner, linux-arm-kernel
In-Reply-To: <aa4acd33-eff3-175f-b86a-459ba8c1d17c@samsung.com>

On Wed, Sep 25, 2019 at 03:40:52PM +0200, Marek Szyprowski wrote:
> Hi Krzysztof,
> 
> On 23.09.2019 18:14, Krzysztof Kozlowski wrote:
> > Convert Samsung Exynos Soc Multi Core Timer bindings to DT schema format
> > using json-schema.
> >
> > Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> >
> > ---
> >
> > Changes since v3:
> > 1. Use interrupts-extended instead of interrupts-map.
> >
> > Changes since v1:
> > 1. Indent example with four spaces (more readable),
> > 2. Rename nodes in example to timer,
> > 3. Remove mct-map subnode.
> > ---
> >   .../bindings/timer/samsung,exynos4210-mct.txt |  88 ------------
> >   .../timer/samsung,exynos4210-mct.yaml         | 125 ++++++++++++++++++
> >   2 files changed, 125 insertions(+), 88 deletions(-)
> >   delete mode 100644 Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
> >   create mode 100644 Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
> > deleted file mode 100644
> > index 8f78640ad64c..000000000000
> > --- a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
> > +++ /dev/null
> > @@ -1,88 +0,0 @@
> > -Samsung's Multi Core Timer (MCT)
> > -
> > -The Samsung's Multi Core Timer (MCT) module includes two main blocks, the
> > -global timer and CPU local timers. The global timer is a 64-bit free running
> > -up-counter and can generate 4 interrupts when the counter reaches one of the
> > -four preset counter values. The CPU local timers are 32-bit free running
> > -down-counters and generate an interrupt when the counter expires. There is
> > -one CPU local timer instantiated in MCT for every CPU in the system.
> > -
> > -Required properties:
> > -
> > -- compatible: should be "samsung,exynos4210-mct".
> > -  (a) "samsung,exynos4210-mct", for mct compatible with Exynos4210 mct.
> > -  (b) "samsung,exynos4412-mct", for mct compatible with Exynos4412 mct.
> > -
> > -- reg: base address of the mct controller and length of the address space
> > -  it occupies.
> > -
> > -- interrupts: the list of interrupts generated by the controller. The following
> > -  should be the order of the interrupts specified. The local timer interrupts
> > -  should be specified after the four global timer interrupts have been
> > -  specified.
> > -
> > -	0: Global Timer Interrupt 0
> > -	1: Global Timer Interrupt 1
> > -	2: Global Timer Interrupt 2
> > -	3: Global Timer Interrupt 3
> > -	4: Local Timer Interrupt 0
> > -	5: Local Timer Interrupt 1
> > -	6: ..
> > -	7: ..
> > -	i: Local Timer Interrupt n
> > -
> > -  For MCT block that uses a per-processor interrupt for local timers, such
> > -  as ones compatible with "samsung,exynos4412-mct", only one local timer
> > -  interrupt might be specified, meaning that all local timers use the same
> > -  per processor interrupt.
> > -
> > -Example 1: In this example, the IP contains two local timers, using separate
> > -	   interrupts, so two local timer interrupts have been specified,
> > -	   in addition to four global timer interrupts.
> > -
> > -	mct@10050000 {
> > -		compatible = "samsung,exynos4210-mct";
> > -		reg = <0x10050000 0x800>;
> > -		interrupts = <0 57 0>, <0 69 0>, <0 70 0>, <0 71 0>,
> > -			     <0 42 0>, <0 48 0>;
> > -	};
> > -
> > -Example 2: In this example, the timer interrupts are connected to two separate
> > -	   interrupt controllers. Hence, an interrupt-map is created to map
> > -	   the interrupts to the respective interrupt controllers.
> > -
> > -	mct@101c0000 {
> > -		compatible = "samsung,exynos4210-mct";
> > -		reg = <0x101C0000 0x800>;
> > -		interrupt-parent = <&mct_map>;
> > -		interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
> > -
> > -		mct_map: mct-map {
> > -			#interrupt-cells = <1>;
> > -			#address-cells = <0>;
> > -			#size-cells = <0>;
> > -			interrupt-map = <0 &gic 0 57 0>,
> > -					<1 &gic 0 69 0>,
> > -					<2 &combiner 12 6>,
> > -					<3 &combiner 12 7>,
> > -					<4 &gic 0 42 0>,
> > -					<5 &gic 0 48 0>;
> > -		};
> > -	};
> > -
> > -Example 3: In this example, the IP contains four local timers, but using
> > -	   a per-processor interrupt to handle them. Either all the local
> > -	   timer interrupts can be specified, with the same interrupt specifier
> > -	   value or just the first one.
> > -
> > -	mct@10050000 {
> > -		compatible = "samsung,exynos4412-mct";
> > -		reg = <0x10050000 0x800>;
> > -
> > -		/* Both ways are possible in this case. Either: */
> > -		interrupts = <0 57 0>, <0 69 0>, <0 70 0>, <0 71 0>,
> > -			     <0 42 0>;
> > -		/* or: */
> > -		interrupts = <0 57 0>, <0 69 0>, <0 70 0>, <0 71 0>,
> > -			     <0 42 0>, <0 42 0>, <0 42 0>, <0 42 0>;
> > -	};
> > diff --git a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml
> > new file mode 100644
> > index 000000000000..bff3f54a398f
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml
> > @@ -0,0 +1,125 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/timer/samsung,exynos4210-mct.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Samsung Exynos SoC Multi Core Timer (MCT)
> > +
> > +maintainers:
> > +  - Krzysztof Kozlowski <krzk@kernel.org>
> > +
> > +description: |+
> > +  The Samsung's Multi Core Timer (MCT) module includes two main blocks, the
> > +  global timer and CPU local timers. The global timer is a 64-bit free running
> > +  up-counter and can generate 4 interrupts when the counter reaches one of the
> > +  four preset counter values. The CPU local timers are 32-bit free running
> > +  down-counters and generate an interrupt when the counter expires. There is
> > +  one CPU local timer instantiated in MCT for every CPU in the system.
> > +
> > +properties:
> > +  compatible:
> > +    enum:
> > +      - samsung,exynos4210-mct
> > +      - samsung,exynos4412-mct
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  interrupts:
> > +    description: |
> > +      Interrupts should be put in specific order. This is, the local timer
> > +      interrupts should be specified after the four global timer interrupts
> > +      have been specified:
> > +      0: Global Timer Interrupt 0
> > +      1: Global Timer Interrupt 1
> > +      2: Global Timer Interrupt 2
> > +      3: Global Timer Interrupt 3
> > +      4: Local Timer Interrupt 0
> > +      5: Local Timer Interrupt 1
> > +      6: ..
> > +      7: ..
> > +      i: Local Timer Interrupt n
> > +      For MCT block that uses a per-processor interrupt for local timers, such
> > +      as ones compatible with "samsung,exynos4412-mct", only one local timer
> > +      interrupt might be specified, meaning that all local timers use the same
> > +      per processor interrupt.
> > +    minItems: 5               # 4 Global + 1 local
> > +    maxItems: 20              # 4 Global + 16 local
> > +
> > +  interrupts-extended:
> > +    description: |
> > +      If interrupts are coming from different controllers, this property
> > +      can be used instead of regular "interrupts" property.
> > +      The format is exactly the same as with "interrupts".
> > +      Interrupts should be put in specific order. This is, the local timer
> > +    minItems: 5               # 4 Global + 1 local
> > +    maxItems: 20              # 4 Global + 16 local
> > +
> > +required:
> > +  - compatible
> > +  - interrupts
> > +  - reg
> > +
> > +allOf:
> > +  - if:
> > +      not:
> > +        required:
> > +          - interrupts
> > +    then:
> > +      required:
> > +        - interrupts-extended
> > +
> > +examples:
> > +  - |
> > +    // In this example, the IP contains two local timers, using separate
> > +    // interrupts, so two local timer interrupts have been specified,
> > +    // in addition to four global timer interrupts.
> > +
> > +    timer@10050000 {
> > +        compatible = "samsung,exynos4210-mct";
> > +        reg = <0x10050000 0x800>;
> > +        interrupts = <0 57 0>, <0 69 0>, <0 70 0>, <0 71 0>,
> > +                     <0 42 0>, <0 48 0>;
> > +    };
> > +
> > +  - |
> > +    // In this example, the timer interrupts are connected to two separate
> > +    // interrupt controllers. Hence, an interrupts-extended is needed.
> > +
> > +    timer@101c0000 {
> > +        compatible = "samsung,exynos4210-mct";
> > +        reg = <0x101C0000 0x800>;
> > +        interrupts-extended = <&gic 0 57 0>,
> > +                              <&gic 0 69 0>,
> > +                              <&combiner 12 6>,
> > +                              <&combiner 12 7>,
> > +                              <&gic 0 42 0>,
> > +                              <&gic 0 48 0>;
> > +    };
> > +
> > +  - |
> > +    // In this example, the IP contains four local timers, but using
> > +    // a per-processor interrupt to handle them. Only one first local
> > +    // interrupt is specified.
> > +
> > +    timer@10050000 {
> > +        compatible = "samsung,exynos4412-mct";
> > +        reg = <0x10050000 0x800>;
> > +
> > +        interrupts = <0 57 0>, <0 69 0>, <0 70 0>, <0 71 0>,
> > +                     <0 42 0>;
> > +    };
> > +
> > +  - |
> > +    // In this example, the IP contains four local timers, but using
> > +    // a per-processor interrupt to handle them. All the local timer
> > +    // interrupts are specified.
> > +
> > +    timer@10050000 {
> > +        compatible = "samsung,exynos4412-mct";
> > +        reg = <0x10050000 0x800>;
> > +
> > +        interrupts = <0 57 0>, <0 69 0>, <0 70 0>, <0 71 0>,
> > +                     <0 42 0>, <0 42 0>, <0 42 0>, <0 42 0>;
> > +    };
> I would add "#include <dt-bindings/interrupt-controller/arm-gic.h>" and
> replace zeros with proper defines like GIC_SPI and GIC_PPI. The last two
> examples describes per-processor-interrupts, but have 0 in the specifier
> cell 0. I would also use proper IRQ_TYPE_LEVEL_HIGH at cell 3 instead
> of 0. I would also consider adding artificial 'interrupt-parent = &git'
> property to the 1st, 3rd and 4th examples to make it clear that they
> refer to ARM GIC bindings.

Makes sense, but how about doing this in separate patch? The example code
was like this amd this just converts the bindings so I think it is better
to reduce the amount of feature-like improvements.

Best regards,
Krzysztof


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^ permalink raw reply

* Re: [PATCH 2/3] soc: amlogic: Add support for Secure power domains controller
From: Jianxin Pan @ 2019-09-26  9:17 UTC (permalink / raw)
  To: Kevin Hilman, linux-amlogic
  Cc: devicetree, Hanjie Lin, Victor Wan, linux-pm, Martin Blumenstingl,
	Neil Armstrong, linux-kernel, Zhiqiang Liang, Rob Herring,
	Jian Hu, Xingyu Chen, linux-arm-kernel, Jerome Brunet
In-Reply-To: <7hh850t2wy.fsf@baylibre.com>

Hi Kevin,

Thanks for your review. Please see my comments below.


On 2019/9/26 6:41, Kevin Hilman wrote:
> Hi Jianxin,
> 
> Jianxin Pan <jianxin.pan@amlogic.com> writes:
> 
>> Add support for the Amlogic Secure Power controller. In A1/C1 series, power
>> control registers are in secure domain, and should be accessed by smc.
>>
>> Signed-off-by: Jianxin Pan <jianxin.pan@amlogic.com>
>> Signed-off-by: Zhiqiang Liang <zhiqiang.liang@amlogic.com>
> 
> Thanks for the new power domain driver.
> 
>> ---
>>  drivers/soc/amlogic/Kconfig             |  13 +++
>>  drivers/soc/amlogic/Makefile            |   1 +
>>  drivers/soc/amlogic/meson-secure-pwrc.c | 182 ++++++++++++++++++++++++++++++++
>>  3 files changed, 196 insertions(+)
>>  create mode 100644 drivers/soc/amlogic/meson-secure-pwrc.c
>>
>> diff --git a/drivers/soc/amlogic/Kconfig b/drivers/soc/amlogic/Kconfig
>> index bc2c912..6cb06e7 100644
>> --- a/drivers/soc/amlogic/Kconfig
>> +++ b/drivers/soc/amlogic/Kconfig
>> @@ -48,6 +48,19 @@ config MESON_EE_PM_DOMAINS
>>  	  Say yes to expose Amlogic Meson Everything-Else Power Domains as
>>  	  Generic Power Domains.
>>  
>> +config MESON_SECURE_PM_DOMAINS
>> +	bool "Amlogic Meson Secure Power Domains driver"
>> +	depends on ARCH_MESON || COMPILE_TEST
>> +	depends on PM && OF
>> +	depends on HAVE_ARM_SMCCC
>> +	default ARCH_MESON
>> +	select PM_GENERIC_DOMAINS
>> +	select PM_GENERIC_DOMAINS_OF
>> +	help
>> +	  Support for the power controller on Amlogic A1/C1 series.
>> +	  Say yes to expose Amlogic Meson Secure Power Domains as Generic
>> +	  Power Domains.
>> +
>>  config MESON_MX_SOCINFO
>>  	bool "Amlogic Meson MX SoC Information driver"
>>  	depends on ARCH_MESON || COMPILE_TEST
>> diff --git a/drivers/soc/amlogic/Makefile b/drivers/soc/amlogic/Makefile
>> index de79d044..7b8c5d3 100644
>> --- a/drivers/soc/amlogic/Makefile
>> +++ b/drivers/soc/amlogic/Makefile
>> @@ -5,3 +5,4 @@ obj-$(CONFIG_MESON_GX_SOCINFO) += meson-gx-socinfo.o
>>  obj-$(CONFIG_MESON_GX_PM_DOMAINS) += meson-gx-pwrc-vpu.o
>>  obj-$(CONFIG_MESON_MX_SOCINFO) += meson-mx-socinfo.o
>>  obj-$(CONFIG_MESON_EE_PM_DOMAINS) += meson-ee-pwrc.o
>> +obj-$(CONFIG_MESON_SECURE_PM_DOMAINS) += meson-secure-pwrc.o
>> diff --git a/drivers/soc/amlogic/meson-secure-pwrc.c b/drivers/soc/amlogic/meson-secure-pwrc.c
>> new file mode 100644
>> index 00000000..00c7232
>> --- /dev/null
>> +++ b/drivers/soc/amlogic/meson-secure-pwrc.c
>> @@ -0,0 +1,182 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
[...]
>> +
>> +static bool pwrc_secure_get_power(struct meson_secure_pwrc_domain *pwrc_domain)
>> +{
>> +	struct arm_smccc_res res;
>> +
>> +	arm_smccc_smc(SMC_PWRC_GET, pwrc_domain->index, 0,
>> +		      0, 0, 0, 0, 0, &res);
>> +
>> +	return res.a0 & 0x1;
> 
> Please use a #define with a readable name for this mask.
> The return type of this smc is bool. I will remove 0x1 mask in next version. 

Another question about smc:
In this driver, no share memory is needed, and I use arm_smccc_smc() directly.
Should I add secure-monitor = <&sm> in dtb and use meson_sm_call() from sm driver instead? 
>> +}
> 
> What does the return value for this function mean?  Does true mean
> "powered off" or "powered on">
The return vaule for SMC_PWRC_GET :
0 -> power on
1 -> power off> See the rename I just did on the ee-pwrc driver:
> https://lore.kernel.org/linux-amlogic/20190925213528.21515-2-khilman@kernel.org/
> I will follow and rename to _is_off() in the next verson.
>> +static int meson_secure_pwrc_off(struct generic_pm_domain *domain)
>> +{
>> +	struct arm_smccc_res res;
>> +	struct meson_secure_pwrc_domain *pwrc_domain =
[...]
>> +
>> +#define SEC_PD(__name, __flag)			\
>> +{						\
>> +	.name = #__name,			\
>> +	.index = PWRC_##__name##_ID,		\
>> +	.get_power = pwrc_secure_get_power,	\
>> +	.flags = __flag,			\
>> +}
>> +
>> +static struct meson_secure_pwrc_domain_desc a1_pwrc_domains[] = {
>> +	SEC_PD(DSPA,	0),
>> +	SEC_PD(DSPB,	0),
>> +	SEC_PD(UART,	GENPD_FLAG_ALWAYS_ON),
> 
> This flag should only be used for domains where there are no linux
> drivers.
> 
> Rather than using this flag, you need to add a 'power-domain' property
> to the uart driver in DT, and then update the meson_uart driver to use
> the runtime PM API so that the domain is enabled whenever the UART is in
> use.
PM_UART Power domain is shared by uart, msr, jtag and cec.
Uart should keep working in BL31, after kernel suspend and before kernel resume.
> 
>> +	SEC_PD(DMC,	GENPD_FLAG_ALWAYS_ON),
> 
> Please explain the need for ALWAYS_ON.
> 
PM_DMC is used for DDR PHY ana/dig and DMC. 
There is no linux drver for them, and it should be always on. 

I will add comments for all these always on domains.
>> +	SEC_PD(I2C,	0),
>> +	SEC_PD(PSRAM,	0),
>> +	SEC_PD(ACODEC,	0),
>> +	SEC_PD(AUDIO,	0),
>> +	SEC_PD(OTP,	0),
>> +	SEC_PD(DMA,	0),
>> +	SEC_PD(SD_EMMC,	0),
>> +	SEC_PD(RAMA,	0),
>> +	SEC_PD(RAMB,	GENPD_FLAG_ALWAYS_ON),
> 
> Please explain the need for ALWAYS_ON.
> 
In A1, SRAMB is used for bl31 ATF. 
>> +	SEC_PD(IR,	0),
>> +	SEC_PD(SPICC,	0),
>> +	SEC_PD(SPIFC,	0),
>> +	SEC_PD(USB,	0),
>> +	SEC_PD(NIC,	GENPD_FLAG_ALWAYS_ON),
> 
> Please explain the need for ALWAYS_ON.
> 
PD_NIC is used for NIC400, and should keep on.
>> +	SEC_PD(PDMIN,	0),
>> +	SEC_PD(RSA,	0),
>> +};
>> +
>> +static int meson_secure_pwrc_probe(struct platform_device *pdev)
>> +{
>> +	const struct meson_secure_pwrc_domain_data *match;
>> +	struct meson_secure_pwrc *pwrc;
>> +	int i;
[...]
>> +
>> +	return of_genpd_add_provider_onecell(pdev->dev.of_node, &pwrc->xlate);
>> +}
>> +
>> +static struct meson_secure_pwrc_domain_data meson_secure_a1_pwrc_data = {
>> +	.domains = a1_pwrc_domains,
>> +	.count = ARRAY_SIZE(a1_pwrc_domains),
>> +};
>> +
>> +static const struct of_device_id meson_secure_pwrc_match_table[] = {
>> +	{
>> +		.compatible = "amlogic,meson-a1-pwrc",
>> +		.data = &meson_secure_a1_pwrc_data,
>> +	},
>> +	{ }
> 
> as mentioned by Martin, please add the sentinel string here.  Helps for
> readability.
> 
OK, I will fix it. Thank you.
>> +};
>> +
>> +static struct platform_driver meson_secure_pwrc_driver = {
>> +	.probe = meson_secure_pwrc_probe,
>> +	.driver = {
>> +		.name		= "meson_secure_pwrc",
>> +		.of_match_table	= meson_secure_pwrc_match_table,
>> +	},
>> +};
>> +
>> +static int meson_secure_pwrc_init(void)
>> +{
>> +	return platform_driver_register(&meson_secure_pwrc_driver);
>> +}
>> +arch_initcall_sync(meson_secure_pwrc_init);
> 
> Please use builtin_platform_driver() or explain in detail why the
> initcall is needed.
> 
OK, I will use builtin_platform_driver instead.
> Thanks,
> 
> Kevin
> 
> .
> 


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* RE: [PATCH V9 1/2] dt-bindings: mailbox: add binding doc for the ARM SMC/HVC mailbox
From: Peng Fan @ 2019-09-26  9:15 UTC (permalink / raw)
  To: Andre Przywara
  Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
	f.fainelli@gmail.com, jassisinghbrar@gmail.com,
	linux-kernel@vger.kernel.org, robh+dt@kernel.org, dl-linux-imx,
	sudeep.holla@arm.com, linux-arm-kernel@lists.infradead.org
In-Reply-To: <20190925180901.11fe5165@donnerap.cambridge.arm.com>

Hi Andre,

> Subject: Re: [PATCH V9 1/2] dt-bindings: mailbox: add binding doc for the
> ARM SMC/HVC mailbox
> 
[...]
> > + supported  identifier are passed from consumers, or listed in the
> > + the arm,func-id
> 
>                 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> 		This is now obsolete.
> 
> The rest looks good to me, thanks for the changes!
> 
> Reviewed-by: Andre Przywara <andre.przywara@arm.com>

Thanks, I'll wait to see whether Rob and Jassi has some comments or not.

Then post out v10 to address your comments.

Thanks,
Peng.

> 
> Cheers,
> Andre.
> 
> > +  property as described below. The firmware can return one value in
> > + the first SMC result register, it is expected to be an error value,
> > + which shall be propagated to the mailbox client.
> > +
> > +  Any core which supports the SMC or HVC instruction can be used, as
> > + long  as a firmware component running in EL3 or EL2 is handling these
> calls.
> > +
> > +properties:
> > +  compatible:
> > +    oneOf:
> > +      - description:
> > +          For implementations using ARM SMC instruction.
> > +        const: arm,smc-mbox
> > +
> > +      - description:
> > +          For implementations using ARM HVC instruction.
> > +        const: arm,hvc-mbox
> > +
> > +  "#mbox-cells":
> > +    const: 0
> > +
> > +  arm,func-id:
> > +    description: |
> > +      An single 32-bit value specifying the function ID used by the
> mailbox.
> > +      The function ID follows the ARM SMC calling convention standard.
> > +    $ref: /schemas/types.yaml#/definitions/uint32
> > +
> > +required:
> > +  - compatible
> > +  - "#mbox-cells"
> > +  - arm,func-id
> > +
> > +examples:
> > +  - |
> > +    sram@93f000 {
> > +      compatible = "mmio-sram";
> > +      reg = <0x0 0x93f000 0x0 0x1000>;
> > +      #address-cells = <1>;
> > +      #size-cells = <1>;
> > +      ranges = <0x0 0x93f000 0x1000>;
> > +
> > +      cpu_scp_lpri: scp-shmem@0 {
> > +        compatible = "arm,scmi-shmem";
> > +        reg = <0x0 0x200>;
> > +      };
> > +    };
> > +
> > +    smc_tx_mbox: tx_mbox {
> > +      #mbox-cells = <0>;
> > +      compatible = "arm,smc-mbox";
> > +      arm,func-id = <0xc20000fe>;
> > +    };
> > +
> > +    firmware {
> > +      scmi {
> > +        compatible = "arm,scmi";
> > +        mboxes = <&smc_tx_mbox>;
> > +        mbox-names = "tx";
> > +        shmem = <&cpu_scp_lpri>;
> > +      };
> > +    };
> > +
> > +...


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* Re: [PATCH v2 2/2] soc: amlogic: ee-pwrc: ensure driver state maches HW state
From: Neil Armstrong @ 2019-09-26  9:05 UTC (permalink / raw)
  To: Kevin Hilman, linux-amlogic; +Cc: linux-arm-kernel, linux-pm
In-Reply-To: <20190925213528.21515-3-khilman@kernel.org>

On 25/09/2019 23:35, Kevin Hilman wrote:
> From: Kevin Hilman <khilman@baylibre.com>
> 
> During init, ensure that the driver on/off state as well as clock and
> reset state matches the hardware state.  Do this by always calling the
> drivers 'on' function, and then callling the 'off' function if the
> HW state was initially detected as off.
> 
> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
> ---
>  drivers/soc/amlogic/meson-ee-pwrc.c | 29 ++++++++---------------------
>  1 file changed, 8 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/soc/amlogic/meson-ee-pwrc.c b/drivers/soc/amlogic/meson-ee-pwrc.c
> index dcce8e694a07..2e8eee0dc166 100644
> --- a/drivers/soc/amlogic/meson-ee-pwrc.c
> +++ b/drivers/soc/amlogic/meson-ee-pwrc.c
> @@ -323,6 +323,8 @@ static int meson_ee_pwrc_init_domain(struct platform_device *pdev,
>  				     struct meson_ee_pwrc *pwrc,
>  				     struct meson_ee_pwrc_domain *dom)
>  {
> +	bool is_off;
> +
>  	dom->pwrc = pwrc;
>  	dom->num_rstc = dom->desc.reset_names_count;
>  	dom->num_clks = dom->desc.clk_names_count;
> @@ -356,27 +358,12 @@ static int meson_ee_pwrc_init_domain(struct platform_device *pdev,
>  	dom->base.power_on = meson_ee_pwrc_on;
>  	dom->base.power_off = meson_ee_pwrc_off;
>  
> -	/*
> -         * TOFIX: This is a special case for the VPU power domain, which can
> -	 * be enabled previously by the bootloader. In this case the VPU
> -         * pipeline may be functional but no driver maybe never attach
> -         * to this power domain, and if the domain is disabled it could
> -         * cause system errors. This is why the pm_domain_always_on_gov
> -         * is used here.
> -         * For the same reason, the clocks should be enabled in case
> -         * we need to power the domain off, otherwise the internal clocks
> -         * prepare/enable counters won't be in sync.
> -         */
> -	if (dom->num_clks && dom->desc.is_off && !dom->desc.is_off(dom)) {
> -		int ret = clk_bulk_prepare_enable(dom->num_clks, dom->clks);
> -		if (ret)
> -			return ret;
> -
> -		pm_genpd_init(&dom->base, &pm_domain_always_on_gov, false);
> -	} else
> -		pm_genpd_init(&dom->base, NULL,
> -			      (dom->desc.is_off ?
> -			       dom->desc.is_off(dom) : true));
> +	/* Ensure that driver state matches HW state */
> +	is_off = dom->desc.is_off ? dom->desc.is_off(dom) : true;
> +	meson_ee_pwrc_on(&dom->base);
> +	if (is_off)
> +		meson_ee_pwrc_off(&dom->base);
> +	pm_genpd_init(&dom->base, NULL, is_off);
>  
>  	return 0;
>  }
> 

I don't see what you are trying to solve except simplifying the code.

And the case is more that "matching the clock state" here, the
pm_domain_always_on_gov was is a real case when booting from the Amlogic
U-boot.

The display power domain is complex and as been half solved by using
"simple-framebuffer" on gx and is missing on g12a/g12b/sm1.

For example, Debian installer runs without the modules, but will use
the EFIfb set by U-Boot, but in this precise case :
- the DRM driver isn't loaded
- we can't hook this power domain with EFIfb

When *not* in EFIfb, we use simple-framebuffer on GX, using this
power domain, but it hasn't been copied to G12A.

Personally I'll leave this code until we really tested and checked all
uses cases, not only on the sei510/sei610 using mainline u-boot.

Neil

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* Re: [RFC PATCH 00/18] crypto: wireguard using the existing crypto API
From: Jason A. Donenfeld @ 2019-09-26  8:59 UTC (permalink / raw)
  To: Ard Biesheuvel
  Cc: Catalin Marinas, Herbert Xu, Arnd Bergmann, Eric Biggers, Greg KH,
	Samuel Neves, Will Deacon, Linux Crypto Mailing List,
	Andy Lutomirski, Marc Zyngier, Dan Carpenter, Linus Torvalds,
	David Miller, linux-arm-kernel
In-Reply-To: <20190925161255.1871-1-ard.biesheuvel@linaro.org>

 Hi Ard,

Thanks for taking the initiative on this. When I first discussed with
DaveM porting WireGuard to the crypto API and doing Zinc later
yesterday, I thought to myself, “I wonder if Ard might want to work on
this with me…” and sent you a message on IRC. It didn’t occur to me
that you were the one who had pushed this endeavor!

I must admit, though, I’m a bit surprised to see how it’s appearing.
When I wrote [1], I had really imagined postponing the goals of Zinc
entirely, and instead writing a small shim that calls into the
existing crypto API machinery. I imagined the series to look like
this:

1. Add blake2s generic as a crypto API shash object.
2. Add blake2s x86_64 as a crypto API shash object.
3. Add curve25519 generic as a crypto API dh object.
4. Add curve25519 x86_64 as a crypto API dh object.
5. Add curve25519 arm as a crypto API dh object.
6. The unmodified WireGuard commit.
7. A “cryptoapi.c” file for WireGuard that provides definitions of the
“just functions” approach of Zinc, but does so in terms of the crypto
API’s infrastructure, with global per-cpu lists and a few locks to
handle quick buffer and tfm reuse.

I wouldn’t expect (7) to be pretty, for the various reasons that most
people dislike the crypto API, but at least it would somewhat “work”,
not affect the general integrity of WireGuard, and provide a clear
path forward in an evolutionary manner for gradually, piecemeal,
swapping out pieces of that for a Zinc-like thing, however that winds
up appearing.

Instead what we’ve wound up with in this series is a Frankenstein’s
monster of Zinc, which appears to have basically the same goal as
Zinc, and even much of the same implementation just moved to a
different directory, but then skimps on making it actually work well
and introduces problems. (I’ll elucidate on some specific issues later
in this email so that we can get on the same page with regards to
security requirements for WireGuard.) I surmise from this Zinc-but-not
series is that what actually is going on here is mostly some kind of
power or leadership situation, which is what you’ve described to me
also at various other points and in person. I also recognize that I am
at least part way to blame for whatever dynamic there has stagnated
this process; let me try to rectify that:

A principle objection you’ve had is that Zinc moves to its own
directory, with its own name, and tries to segment itself off from the
rest of the crypto API’s infrastructure. You’ve always felt this
should be mixed in with the rest of the crypto API’s infrastructure
and directory structures in one way or another. Let’s do both of those
things – put this in a directory structure you find appropriate and
hook this into the rest of the crypto API’s infrastructure in a way
you find appropriate. I might disagree, which is why Zinc does things
the way it does, but I’m open to compromise and doing things more your
way.

Another objection you’ve had is that Zinc replaces many existing
implementations with its own. Martin wasn’t happy about that either.
So let’s not do that, and we’ll have some wholesale replacement of
implementations in future patchsets at future dates discussed and
benched and bikeshedded independently from this.

Finally, perhaps most importantly, Zinc’s been my design rather than
our design. Let’s do this together instead of me git-send-email(1)-ing
a v37.

If the process of doing that together will be fraught with difficulty,
I’m still open to the “7 patch series” with the ugly cryptoapi.c
approach, as described at the top. But I think if we start with Zinc
and whittle it down in accordance with the above, we’ll get something
mutually acceptable, and somewhat similar to this series, with a few
important exceptions, which illustrate some of the issues I see in
this RFC:

Issue 1) No fast implementations for the “it’s just functions” interface.

This is a deal breaker. I know you disagree here and perhaps think all
dynamic dispatch should be by loadable modules configured with
userspace policy and lots of function pointers and dynamically
composable DSL strings, as the current crypto API does it. But I think
a lot of other people agree with me here (and they’ve chimed in
before) that the branch predictor does things better, doesn’t have
Spectre issues, and is very simple to read and understand. For
reference, here’s what that kind of thing looks like: [2].

In this case, the relevance is that the handshake in WireGuard is
extremely performance sensitive, in order to fend off DoS. One of the
big design gambits in WireGuard is – can we make it 1-RTT to reduce
the complexity of the state machine, but keep the crypto efficient
enough that this is still safe to do from a DoS perspective. The
protocol succeeds at this goal, but in many ways, just by a hair when
at scale, and so I’m really quite loathe to decrease handshake
performance. Here’s where that matters specifically:

- Curve25519 does indeed always appear to be taking tiny 32 byte stack
inputs in WireGuard. However, your statement, “the fact that they
operate on small, fixed size buffers means that there is really no
point in providing alternative, SIMD based implementations of these,
and we can limit ourselves to generic C library version,” is just
plain wrong in this case. Curve25519 only ever operates on 32 byte
inputs, because these represent curve scalars and points. It’s not
like a block cipher where parallelism helps with larger inputs or
something. In this case, there are some pretty massive speed
improvements between the generic C implementations and the optimized
ones. Like huge. On both ARM and on Intel. And Curve25519 is the most
expensive operation in WireGuard, and each handshake message invokes a
few of them. (Aside - Something to look forward to: I’m in the process
of getting a formally verified x86_64 ADX implementation ready for
kernel usage, to replace our existing heavily-fuzzed one, which will
be cool.)

- Blake2s actually does benefit from the optimized code even for
relatively short inputs. While you might have been focused on the
super-super small inputs in noise.c, there are slightly larger ones in
cookie.c, and these are the most sensitive computations to make in
terms of DoS resistance; they’re on the “front lines” of the battle,
if you will. (Aside - Arguably WireGuard may have benefited from using
siphash with 128-bit outputs here, or calculated some security metrics
for DoS resistance in the face of forged 64-bit outputs or something,
or a different custom MAC, but hindsight is 20/20.)

- While 25519 and Blake2s are already in use, the optimized versions
of ChaPoly wind up being faster as well, even if it’s just hitting the
boring SSE code.

- On MIPS, the optimized versions of ChaPoly are a necessity. They’re
boring integer/scalar code, but they do things that the compiler
simply cannot do on the platform and we benefit immensely from it.

Taken together, we simply can’t skimp on the implementations available
on the handshake layer, so we’ll need to add some form of
implementation selection, whether it’s the method Zinc uses ([2]), or
something else we cook up together.

Issue 2) Linus’ objection to the async API invasion is more correct
than he realizes.

I could re-enumerate my objections to the API there, but I think we
all get it. It’s horrendous looking. Even the introduction of the
ivpad member (what on earth?) in the skb cb made me shutter. But
there’s actually another issue at play:

wg_noise_handshake_begin_session→derive_keys→symmetric_key_init is all
part of the handshake. We cannot afford to allocate a brand new crypto
object, parse the DSL string, connect all those function pointers,
etc. The allocations involved here aren’t really okay at all in that
path. That’s why the cryptoapi.c idea above involves just using a pool
of pre-allocated objects if we’re going to be using that API at all.
Also keep in mind that WireGuard instances sometimes have hundreds of
thousands of peers.

I’d recommend leaving this synchronous as it exists now, as Linus
suggested, and we can revisit that later down the road. There are a
number of improvements to the async API we could make down the line
that could make this viable in WireGuard. For example, I could imagine
decoupling the creation of the cipher object from its keys and
intermediate buffers, so that we could in fact allocate the cipher
objects with their DSLs globally in a safe way, while allowing the
keys and working buffers to come from elsewhere. This is deep plumbing
into the async API, but I think we could get there in time.

There’s also a degree of practicality: right now there is zero ChaPoly
async acceleration hardware anywhere that would fit into the crypto
API. At some point, it might come to exist and have incredible
performance, and then we’ll both feel very motivated to make this work
for WireGuard. But it might also not come to be (AES seems to have won
over most of the industry), in which case, why hassle?

Issue 3) WireGuard patch is out of date.

This is my fault, because I haven’t posted in a long time. There are
some important changes in the main WireGuard repo. I’ll roll another
patch soon for this so we have something recent to work off of. Sorry
about that.

Issue 4) FPU register batching?

When I introduced the simd_get/simd_put/simd_relax thing, people
seemed to think it was a good idea. My benchmarks of it showed
significant throughput improvements. Your patchset doesn’t have
anything similar to this. But on the other hand, last I spoke with the
x86 FPU guys, I thought they might actually be in the process of
making simd_get/put obsolete with some internal plumbing to make
restoration lazier. I’ll see tglx later today and will poke him about
this, as this might already be a non-issue.


So given the above, how would you like to proceed? My personal
preference would be to see you start with the Zinc patchset and rename
things and change the infrastructure to something that fits your
preferences, and we can see what that looks like. Less appealing would
be to do several iterations of you reworking Zinc from scratch and
going through the exercises all over again, but if you prefer that I
guess I could cope. Alternatively, maybe this is a lot to chew on, and
we should just throw caution into the wind, implement cryptoapi.c for
WireGuard (as described at the top), and add C functions to the crypto
API sometime later? This is what I had envisioned in [1].

And for the avoidance of doubt, or in case any of the above message
belied something different, I really am happy and relieved to have an
opportunity to work on this _with you_, and I am much more open than
before to compromise and finding practical solutions to the past
political issues. Also, if you’re into chat, we can always spec some
of the nitty-gritty aspects out over IRC or even the old-fashioned
telephone. Thanks again for pushing this forward.

Regards,
Jason

[1] https://lore.kernel.org/wireguard/CAHmME9pmfZAp5zd9BDLFc2fWUhtzZcjYZc2atTPTyNFFmEdHLg@mail.gmail.com/
[2] https://git.kernel.org/pub/scm/linux/kernel/git/zx2c4/linux.git/tree/lib/zinc/chacha20/chacha20-x86_64-glue.c?h=jd/wireguard#n54

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* Re: [PATCH 00/11] PCI dma-ranges parsing consolidation
From: Andrew Murray @ 2019-09-26  8:49 UTC (permalink / raw)
  To: Rob Herring
  Cc: Heiko Stuebner, Karthikeyan Mitran, linux-pci, Shawn Lin,
	Ryder Lee, Matthias Brugger, Thomas Petazzoni, Toan Le,
	Will Deacon, Lorenzo Pieralisi, Michal Simek, linux-rockchip,
	bcm-kernel-feedback-list, Linus Walleij, Ray Jui, Hou Zhiqiang,
	Simon Horman, linux-mediatek, Bjorn Helgaas, linux-arm-kernel,
	Scott Branden, Gustavo Pimentel, rfi, linux-renesas-soc,
	Tom Joseph, Jingoo Han, Ley Foon Tan
In-Reply-To: <20190924214630.12817-1-robh@kernel.org>

On Tue, Sep 24, 2019 at 04:46:19PM -0500, Rob Herring wrote:
> This series moves the DT 'dma-ranges' parsing into common helpers
> utilizing a resource list. In the process of doing this, I noticed
> several cases where pci_parse_request_of_pci_ranges() could be used so
> I converted those drivers first. The last 5 patches make the actual
> change to use the common 'dma_ranges' resource list. There's no
> (intended) functional change in this series though I'm also working on
> a separate series to improve the handling of 'dma-ranges' and dma
> masks.
> 
> pci-rcar-gen2 is the only remaining driver doing its own dma-ranges
> handling as it is still using the old ARM PCI functions. Looks like it
> is the last one (in drivers/pci/).

It also seems that pcie-tango is using of_pci_dma_range_parser_init
and so parsing dma-ranges. Though it's using the dma_ranges for a
slightly different purpose.

Thanks,

Andrew Murray

> 
> Compile tested only.
> 
> Rob
> 
> Rob Herring (11):
>   PCI: aardvark: Use pci_parse_request_of_pci_ranges()
>   PCI: altera: Use pci_parse_request_of_pci_ranges()
>   PCI: mediatek: Use pci_parse_request_of_pci_ranges()
>   PCI: versatile: Enable COMPILE_TEST
>   PCI: versatile: Use pci_parse_request_of_pci_ranges()
>   PCI: of: Add inbound resource parsing to helpers
>   PCI: ftpci100: Use inbound resources for setup
>   PCI: v3-semi: Use inbound resources for setup
>   PCI: xgene: Use inbound resources for setup
>   PCI: iproc: Use inbound resources for setup
>   PCI: rcar: Use inbound resources for setup
> 
>  drivers/pci/controller/Kconfig                |  2 +-
>  .../pci/controller/dwc/pcie-designware-host.c |  3 +-
>  drivers/pci/controller/pci-aardvark.c         | 58 ++---------------
>  drivers/pci/controller/pci-ftpci100.c         | 29 ++++-----
>  drivers/pci/controller/pci-host-common.c      |  2 +-
>  drivers/pci/controller/pci-v3-semi.c          | 40 +++++-------
>  drivers/pci/controller/pci-versatile.c        | 62 ++++--------------
>  drivers/pci/controller/pci-xgene.c            | 33 ++++------
>  drivers/pci/controller/pcie-altera.c          | 38 +----------
>  drivers/pci/controller/pcie-cadence-host.c    |  2 +-
>  drivers/pci/controller/pcie-iproc-platform.c  |  1 +
>  drivers/pci/controller/pcie-iproc.c           | 63 +++----------------
>  drivers/pci/controller/pcie-mediatek.c        | 47 +++++---------
>  drivers/pci/controller/pcie-mobiveil.c        |  4 +-
>  drivers/pci/controller/pcie-rcar.c            | 48 ++++++--------
>  drivers/pci/controller/pcie-rockchip-host.c   |  3 +-
>  drivers/pci/controller/pcie-xilinx-nwl.c      |  2 +-
>  drivers/pci/controller/pcie-xilinx.c          |  2 +-
>  drivers/pci/of.c                              | 44 ++++++++++++-
>  drivers/pci/pci.h                             |  8 ++-
>  include/linux/pci.h                           |  2 +
>  21 files changed, 162 insertions(+), 331 deletions(-)
> 
> --
> 2.20.1
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

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^ permalink raw reply

* Re: [PATCH 11/11] PCI: rcar: Use inbound resources for setup
From: Andrew Murray @ 2019-09-26  8:47 UTC (permalink / raw)
  To: Rob Herring
  Cc: Bjorn Helgaas, linux-pci, Lorenzo Pieralisi, linux-arm-kernel,
	Simon Horman
In-Reply-To: <20190924214630.12817-12-robh@kernel.org>

On Tue, Sep 24, 2019 at 04:46:30PM -0500, Rob Herring wrote:
> Now that the helpers provide the inbound resources in the host bridge
> 'dma_ranges' resource list, convert Renesas R-Car PCIe host bridge to
> use the resource list to setup the inbound addresses.
> 
> Cc: Simon Horman <horms@verge.net.au>
> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Signed-off-by: Rob Herring <robh@kernel.org>
> ---
>  drivers/pci/controller/pcie-rcar.c | 45 +++++++++++-------------------
>  1 file changed, 16 insertions(+), 29 deletions(-)
> 
> diff --git a/drivers/pci/controller/pcie-rcar.c b/drivers/pci/controller/pcie-rcar.c
> index b8d6e86a5539..453c931aaf77 100644
> --- a/drivers/pci/controller/pcie-rcar.c
> +++ b/drivers/pci/controller/pcie-rcar.c
> @@ -1014,16 +1014,16 @@ static int rcar_pcie_get_resources(struct rcar_pcie *pcie)
>  }
>  
>  static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie,
> -				    struct of_pci_range *range,
> +				    struct resource_entry *entry,
>  				    int *index)
>  {
> -	u64 restype = range->flags;
> -	u64 cpu_addr = range->cpu_addr;
> -	u64 cpu_end = range->cpu_addr + range->size;
> -	u64 pci_addr = range->pci_addr;
> +	u64 restype = entry->res->flags;
> +	u64 cpu_addr = entry->res->start;
> +	u64 cpu_end = entry->res->end;
> +	u64 pci_addr = entry->res->start - entry->offset;
>  	u32 flags = LAM_64BIT | LAR_ENABLE;
>  	u64 mask;
> -	u64 size;
> +	u64 size = resource_size(entry->res);
>  	int idx = *index;
>  
>  	if (restype & IORESOURCE_PREFETCH)
> @@ -1037,9 +1037,7 @@ static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie,
>  		unsigned long nr_zeros = __ffs64(cpu_addr);
>  		u64 alignment = 1ULL << nr_zeros;
>  
> -		size = min(range->size, alignment);
> -	} else {
> -		size = range->size;
> +		size = min(size, alignment);
>  	}

AFAICT the (if cpu_addr > 0) is here because the result of __ffs64 is undefined
if no bits are set (according to the comment). However by removing the else
statement we no longer guarantee that nr_zeros is defined.

>  	/* Hardware supports max 4GiB inbound region */
>  	size = min(size, 1ULL << 32);
> @@ -1078,30 +1076,19 @@ static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie,
>  	return 0;
>  }
>  
> -static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie *pcie,
> -					  struct device_node *np)
> +static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie *pcie)
>  {
> -	struct of_pci_range range;
> -	struct of_pci_range_parser parser;
> -	int index = 0;
> -	int err;
> -
> -	if (of_pci_dma_range_parser_init(&parser, np))
> -		return -EINVAL;
> -
> -	/* Get the dma-ranges from DT */
> -	for_each_of_pci_range(&parser, &range) {
> -		u64 end = range.cpu_addr + range.size - 1;
> -
> -		dev_dbg(pcie->dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n",
> -			range.flags, range.cpu_addr, end, range.pci_addr);
> +	struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
> +	struct resource_entry *entry;
> +	int index = 0, err = 0;
>  
> -		err = rcar_pcie_inbound_ranges(pcie, &range, &index);
> +	resource_list_for_each_entry(entry, &bridge->dma_ranges) {
> +		err = rcar_pcie_inbound_ranges(pcie, entry, &index);
>  		if (err)
> -			return err;
> +			break;
>  	}
>  
> -	return 0;
> +	return err;
>  }
>  
>  static const struct of_device_id rcar_pcie_of_match[] = {
> @@ -1162,7 +1149,7 @@ static int rcar_pcie_probe(struct platform_device *pdev)
>  		goto err_unmap_msi_irqs;
>  	}
>  
> -	err = rcar_pcie_parse_map_dma_ranges(pcie, dev->of_node);
> +	err = rcar_pcie_parse_map_dma_ranges(pcie);
>  	if (err)
>  		goto err_clk_disable;
>  
> -- 
> 2.20.1
> 

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^ permalink raw reply

* Re: [PATCH 10/11] PCI: iproc: Use inbound resources for setup
From: Andrew Murray @ 2019-09-26  8:39 UTC (permalink / raw)
  To: Rob Herring
  Cc: Lorenzo Pieralisi, Scott Branden, linux-pci,
	bcm-kernel-feedback-list, Ray Jui, Bjorn Helgaas,
	linux-arm-kernel
In-Reply-To: <20190924214630.12817-11-robh@kernel.org>

On Tue, Sep 24, 2019 at 04:46:29PM -0500, Rob Herring wrote:
> Now that the helpers provide the inbound resources in the host bridge
> 'dma_ranges' resource list, convert Broadcom iProc host bridge to use
> the resource list to setup the inbound addresses.
> 
> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Cc: Ray Jui <rjui@broadcom.com>
> Cc: Scott Branden <sbranden@broadcom.com>
> Cc: bcm-kernel-feedback-list@broadcom.com
> Signed-off-by: Rob Herring <robh@kernel.org>

Reviewed-by: Andrew Murray <andrew.murray@arm.com>

> ---
>  drivers/pci/controller/pcie-iproc.c | 63 ++++-------------------------
>  1 file changed, 8 insertions(+), 55 deletions(-)
> 
> diff --git a/drivers/pci/controller/pcie-iproc.c b/drivers/pci/controller/pcie-iproc.c
> index 2d457bfdaf66..9ed181050308 100644
> --- a/drivers/pci/controller/pcie-iproc.c
> +++ b/drivers/pci/controller/pcie-iproc.c
> @@ -1122,15 +1122,15 @@ static int iproc_pcie_ib_write(struct iproc_pcie *pcie, int region_idx,
>  }
>  
>  static int iproc_pcie_setup_ib(struct iproc_pcie *pcie,
> -			       struct of_pci_range *range,
> +			       struct resource_entry *entry,
>  			       enum iproc_pcie_ib_map_type type)
>  {
>  	struct device *dev = pcie->dev;
>  	struct iproc_pcie_ib *ib = &pcie->ib;
>  	int ret;
>  	unsigned int region_idx, size_idx;
> -	u64 axi_addr = range->cpu_addr, pci_addr = range->pci_addr;
> -	resource_size_t size = range->size;
> +	u64 axi_addr = entry->res->start, pci_addr = entry->res->start - entry->offset;
> +	resource_size_t size = resource_size(entry->res);
>  
>  	/* iterate through all IARR mapping regions */
>  	for (region_idx = 0; region_idx < ib->nr_regions; region_idx++) {
> @@ -1182,66 +1182,19 @@ static int iproc_pcie_setup_ib(struct iproc_pcie *pcie,
>  	return ret;
>  }
>  
> -static int iproc_pcie_add_dma_range(struct device *dev,
> -				    struct list_head *resources,
> -				    struct of_pci_range *range)
> -{
> -	struct resource *res;
> -	struct resource_entry *entry, *tmp;
> -	struct list_head *head = resources;
> -
> -	res = devm_kzalloc(dev, sizeof(struct resource), GFP_KERNEL);
> -	if (!res)
> -		return -ENOMEM;
> -
> -	resource_list_for_each_entry(tmp, resources) {
> -		if (tmp->res->start < range->cpu_addr)
> -			head = &tmp->node;
> -	}
> -
> -	res->start = range->cpu_addr;
> -	res->end = res->start + range->size - 1;
> -
> -	entry = resource_list_create_entry(res, 0);
> -	if (!entry)
> -		return -ENOMEM;
> -
> -	entry->offset = res->start - range->cpu_addr;
> -	resource_list_add(entry, head);
> -
> -	return 0;
> -}
> -
>  static int iproc_pcie_map_dma_ranges(struct iproc_pcie *pcie)
>  {
>  	struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
> -	struct of_pci_range range;
> -	struct of_pci_range_parser parser;
> -	int ret;
> -	LIST_HEAD(resources);
> +	struct resource_entry *entry;
> +	int ret = 0;
>  
> -	/* Get the dma-ranges from DT */
> -	ret = of_pci_dma_range_parser_init(&parser, pcie->dev->of_node);
> -	if (ret)
> -		return ret;
> -
> -	for_each_of_pci_range(&parser, &range) {
> -		ret = iproc_pcie_add_dma_range(pcie->dev,
> -					       &resources,
> -					       &range);
> -		if (ret)
> -			goto out;
> +	resource_list_for_each_entry(entry, &host->dma_ranges) {
>  		/* Each range entry corresponds to an inbound mapping region */
> -		ret = iproc_pcie_setup_ib(pcie, &range, IPROC_PCIE_IB_MAP_MEM);
> +		ret = iproc_pcie_setup_ib(pcie, entry, IPROC_PCIE_IB_MAP_MEM);
>  		if (ret)
> -			goto out;
> +			break;
>  	}
>  
> -	list_splice_init(&resources, &host->dma_ranges);
> -
> -	return 0;
> -out:
> -	pci_free_resource_list(&resources);
>  	return ret;
>  }
>  
> -- 
> 2.20.1
> 

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^ permalink raw reply

* Re: [PATCH 09/11] PCI: xgene: Use inbound resources for setup
From: Andrew Murray @ 2019-09-26  8:39 UTC (permalink / raw)
  To: Rob Herring
  Cc: Bjorn Helgaas, linux-pci, Toan Le, Lorenzo Pieralisi,
	linux-arm-kernel
In-Reply-To: <20190924214630.12817-10-robh@kernel.org>

On Tue, Sep 24, 2019 at 04:46:28PM -0500, Rob Herring wrote:
> Now that the helpers provide the inbound resources in the host bridge
> 'dma_ranges' resource list, convert the Xgene host bridge to use the
> resource list to setup the inbound addresses.
> 
> Cc: Toan Le <toan@os.amperecomputing.com>
> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Signed-off-by: Rob Herring <robh@kernel.org>

Reviewed-by: Andrew Murray <andrew.murray@arm.com>

> ---
>  drivers/pci/controller/pci-xgene.c | 32 ++++++++++--------------------
>  1 file changed, 10 insertions(+), 22 deletions(-)
> 
> diff --git a/drivers/pci/controller/pci-xgene.c b/drivers/pci/controller/pci-xgene.c
> index 11f27c42c06a..09c913b12ebc 100644
> --- a/drivers/pci/controller/pci-xgene.c
> +++ b/drivers/pci/controller/pci-xgene.c
> @@ -485,27 +485,27 @@ static int xgene_pcie_select_ib_reg(u8 *ib_reg_mask, u64 size)
>  }
>  
>  static void xgene_pcie_setup_ib_reg(struct xgene_pcie_port *port,
> -				    struct of_pci_range *range, u8 *ib_reg_mask)
> +				    struct resource_entry *entry, u8 *ib_reg_mask)
>  {
>  	void __iomem *cfg_base = port->cfg_base;
>  	struct device *dev = port->dev;
>  	void *bar_addr;
>  	u32 pim_reg;
> -	u64 cpu_addr = range->cpu_addr;
> -	u64 pci_addr = range->pci_addr;
> -	u64 size = range->size;
> +	u64 cpu_addr = entry->res->start;
> +	u64 pci_addr = cpu_addr - entry->offset;
> +	u64 size = resource_size(entry->res);
>  	u64 mask = ~(size - 1) | EN_REG;
>  	u32 flags = PCI_BASE_ADDRESS_MEM_TYPE_64;
>  	u32 bar_low;
>  	int region;
>  
> -	region = xgene_pcie_select_ib_reg(ib_reg_mask, range->size);
> +	region = xgene_pcie_select_ib_reg(ib_reg_mask, size);
>  	if (region < 0) {
>  		dev_warn(dev, "invalid pcie dma-range config\n");
>  		return;
>  	}
>  
> -	if (range->flags & IORESOURCE_PREFETCH)
> +	if (entry->res->flags & IORESOURCE_PREFETCH)
>  		flags |= PCI_BASE_ADDRESS_MEM_PREFETCH;
>  
>  	bar_low = pcie_bar_low_val((u32)cpu_addr, flags);
> @@ -536,25 +536,13 @@ static void xgene_pcie_setup_ib_reg(struct xgene_pcie_port *port,
>  
>  static int xgene_pcie_parse_map_dma_ranges(struct xgene_pcie_port *port)
>  {
> -	struct device_node *np = port->node;
> -	struct of_pci_range range;
> -	struct of_pci_range_parser parser;
> -	struct device *dev = port->dev;
> +	struct pci_host_bridge *bridge = pci_host_bridge_from_priv(port);
> +	struct resource_entry *entry;
>  	u8 ib_reg_mask = 0;
>  
> -	if (of_pci_dma_range_parser_init(&parser, np)) {
> -		dev_err(dev, "missing dma-ranges property\n");
> -		return -EINVAL;
> -	}
> -
> -	/* Get the dma-ranges from DT */
> -	for_each_of_pci_range(&parser, &range) {
> -		u64 end = range.cpu_addr + range.size - 1;
> +	resource_list_for_each_entry(entry, &bridge->dma_ranges)
> +		xgene_pcie_setup_ib_reg(port, entry, &ib_reg_mask);
>  
> -		dev_dbg(dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n",
> -			range.flags, range.cpu_addr, end, range.pci_addr);
> -		xgene_pcie_setup_ib_reg(port, &range, &ib_reg_mask);
> -	}
>  	return 0;
>  }
>  
> -- 
> 2.20.1
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

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^ permalink raw reply

* Re: [PATCH 08/11] PCI: v3-semi: Use inbound resources for setup
From: Andrew Murray @ 2019-09-26  8:39 UTC (permalink / raw)
  To: Rob Herring
  Cc: Bjorn Helgaas, linux-pci, Linus Walleij, Lorenzo Pieralisi,
	linux-arm-kernel
In-Reply-To: <20190924214630.12817-9-robh@kernel.org>

On Tue, Sep 24, 2019 at 04:46:27PM -0500, Rob Herring wrote:
> Now that the helpers provide the inbound resources in the host bridge
> 'dma_ranges' resource list, convert the v3-semi host bridge to use
> the resource list to setup the inbound addresses.
> 
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Signed-off-by: Rob Herring <robh@kernel.org>

Reviewed-by: Andrew Murray <andrew.murray@arm.com>

> ---
>  drivers/pci/controller/pci-v3-semi.c | 38 ++++++++++++----------------
>  1 file changed, 16 insertions(+), 22 deletions(-)
> 
> diff --git a/drivers/pci/controller/pci-v3-semi.c b/drivers/pci/controller/pci-v3-semi.c
> index 090df766faf9..122b695da591 100644
> --- a/drivers/pci/controller/pci-v3-semi.c
> +++ b/drivers/pci/controller/pci-v3-semi.c
> @@ -613,28 +613,30 @@ static int v3_pci_setup_resource(struct v3_pci *v3,
>  }
>  
>  static int v3_get_dma_range_config(struct v3_pci *v3,
> -				   struct of_pci_range *range,
> +				   struct resource_entry *entry,
>  				   u32 *pci_base, u32 *pci_map)
>  {
>  	struct device *dev = v3->dev;
> -	u64 cpu_end = range->cpu_addr + range->size - 1;
> -	u64 pci_end = range->pci_addr + range->size - 1;
> +	u64 cpu_addr = entry->res->start;
> +	u64 cpu_end = entry->res->end;
> +	u64 pci_end = cpu_end - entry->offset;
> +	u64 pci_addr = entry->res->start - entry->offset;
>  	u32 val;
>  
> -	if (range->pci_addr & ~V3_PCI_BASE_M_ADR_BASE) {
> +	if (pci_addr & ~V3_PCI_BASE_M_ADR_BASE) {
>  		dev_err(dev, "illegal range, only PCI bits 31..20 allowed\n");
>  		return -EINVAL;
>  	}
> -	val = ((u32)range->pci_addr) & V3_PCI_BASE_M_ADR_BASE;
> +	val = ((u32)pci_addr) & V3_PCI_BASE_M_ADR_BASE;
>  	*pci_base = val;
>  
> -	if (range->cpu_addr & ~V3_PCI_MAP_M_MAP_ADR) {
> +	if (cpu_addr & ~V3_PCI_MAP_M_MAP_ADR) {
>  		dev_err(dev, "illegal range, only CPU bits 31..20 allowed\n");
>  		return -EINVAL;
>  	}
> -	val = ((u32)range->cpu_addr) & V3_PCI_MAP_M_MAP_ADR;
> +	val = ((u32)cpu_addr) & V3_PCI_MAP_M_MAP_ADR;
>  
> -	switch (range->size) {
> +	switch (resource_size(entry->res)) {
>  	case SZ_1M:
>  		val |= V3_LB_BASE_ADR_SIZE_1MB;
>  		break;
> @@ -682,8 +684,8 @@ static int v3_get_dma_range_config(struct v3_pci *v3,
>  	dev_dbg(dev,
>  		"DMA MEM CPU: 0x%016llx -> 0x%016llx => "
>  		"PCI: 0x%016llx -> 0x%016llx base %08x map %08x\n",
> -		range->cpu_addr, cpu_end,
> -		range->pci_addr, pci_end,
> +		cpu_addr, cpu_end,
> +		pci_addr, pci_end,
>  		*pci_base, *pci_map);
>  
>  	return 0;
> @@ -692,24 +694,16 @@ static int v3_get_dma_range_config(struct v3_pci *v3,
>  static int v3_pci_parse_map_dma_ranges(struct v3_pci *v3,
>  				       struct device_node *np)
>  {
> -	struct of_pci_range range;
> -	struct of_pci_range_parser parser;
> +	struct pci_host_bridge *bridge = pci_host_bridge_from_priv(v3);
>  	struct device *dev = v3->dev;
> +	struct resource_entry *entry;
>  	int i = 0;
>  
> -	if (of_pci_dma_range_parser_init(&parser, np)) {
> -		dev_err(dev, "missing dma-ranges property\n");
> -		return -EINVAL;
> -	}
> -
> -	/*
> -	 * Get the dma-ranges from the device tree
> -	 */
> -	for_each_of_pci_range(&parser, &range) {
> +	resource_list_for_each_entry(entry, &bridge->dma_ranges) {
>  		int ret;
>  		u32 pci_base, pci_map;
>  
> -		ret = v3_get_dma_range_config(v3, &range, &pci_base, &pci_map);
> +		ret = v3_get_dma_range_config(v3, entry, &pci_base, &pci_map);
>  		if (ret)
>  			return ret;
>  
> -- 
> 2.20.1
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

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^ permalink raw reply

* Re: [PATCH 07/11] PCI: ftpci100: Use inbound resources for setup
From: Andrew Murray @ 2019-09-26  8:39 UTC (permalink / raw)
  To: Rob Herring; +Cc: Bjorn Helgaas, linux-pci, Lorenzo Pieralisi, linux-arm-kernel
In-Reply-To: <20190924214630.12817-8-robh@kernel.org>

On Tue, Sep 24, 2019 at 04:46:26PM -0500, Rob Herring wrote:
> Now that the helpers provide the inbound resources in the host bridge
> 'dma_ranges' resource list, convert Faraday ftpci100 host bridge to use
> the resource list to setup the inbound addresses.
> 
> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Signed-off-by: Rob Herring <robh@kernel.org>
> ---

Reviewed-by: Andrew Murray <andrew.murray@arm.com>

>  drivers/pci/controller/pci-ftpci100.c | 26 +++++++++-----------------
>  1 file changed, 9 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/pci/controller/pci-ftpci100.c b/drivers/pci/controller/pci-ftpci100.c
> index 3e07a8203736..e37a33ad77d9 100644
> --- a/drivers/pci/controller/pci-ftpci100.c
> +++ b/drivers/pci/controller/pci-ftpci100.c
> @@ -375,12 +375,11 @@ static int faraday_pci_setup_cascaded_irq(struct faraday_pci *p)
>  	return 0;
>  }
>  
> -static int faraday_pci_parse_map_dma_ranges(struct faraday_pci *p,
> -					    struct device_node *np)
> +static int faraday_pci_parse_map_dma_ranges(struct faraday_pci *p)
>  {
> -	struct of_pci_range range;
> -	struct of_pci_range_parser parser;
>  	struct device *dev = p->dev;
> +	struct pci_host_bridge *bridge = pci_host_bridge_from_priv(p);
> +	struct resource_entry *entry;
>  	u32 confreg[3] = {
>  		FARADAY_PCI_MEM1_BASE_SIZE,
>  		FARADAY_PCI_MEM2_BASE_SIZE,
> @@ -389,19 +388,12 @@ static int faraday_pci_parse_map_dma_ranges(struct faraday_pci *p,
>  	int i = 0;
>  	u32 val;
>  
> -	if (of_pci_dma_range_parser_init(&parser, np)) {
> -		dev_err(dev, "missing dma-ranges property\n");
> -		return -EINVAL;
> -	}
> -
> -	/*
> -	 * Get the dma-ranges from the device tree
> -	 */
> -	for_each_of_pci_range(&parser, &range) {
> -		u64 end = range.pci_addr + range.size - 1;
> +	resource_list_for_each_entry(entry, &bridge->dma_ranges) {
> +		u64 pci_addr = entry->res->start - entry->offset;
> +		u64 end = entry->res->end - entry->offset;
>  		int ret;
>  
> -		ret = faraday_res_to_memcfg(range.pci_addr, range.size, &val);
> +		ret = faraday_res_to_memcfg(pci_addr, resource_size(entry->res), &val);
>  		if (ret) {
>  			dev_err(dev,
>  				"DMA range %d: illegal MEM resource size\n", i);
> @@ -409,7 +401,7 @@ static int faraday_pci_parse_map_dma_ranges(struct faraday_pci *p,
>  		}
>  
>  		dev_info(dev, "DMA MEM%d BASE: 0x%016llx -> 0x%016llx config %08x\n",
> -			 i + 1, range.pci_addr, end, val);
> +			 i + 1, pci_addr, end, val);
>  		if (i <= 2) {
>  			faraday_raw_pci_write_config(p, 0, 0, confreg[i],
>  						     4, val);
> @@ -566,7 +558,7 @@ static int faraday_pci_probe(struct platform_device *pdev)
>  			cur_bus_speed = PCI_SPEED_66MHz;
>  	}
>  
> -	ret = faraday_pci_parse_map_dma_ranges(p, dev->of_node);
> +	ret = faraday_pci_parse_map_dma_ranges(p);
>  	if (ret)
>  		return ret;
>  
> -- 
> 2.20.1
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

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^ permalink raw reply

* Re: [PATCH 4/4] arm64: Remove gettimeofday.S
From: Catalin Marinas @ 2019-09-26  8:34 UTC (permalink / raw)
  To: Vincenzo Frascino
  Cc: ard.biesheuvel, ndesaulniers, linux-kernel, tglx, will,
	linux-arm-kernel
In-Reply-To: <20190926060353.54894-5-vincenzo.frascino@arm.com>

On Thu, Sep 26, 2019 at 07:03:53AM +0100, Vincenzo Frascino wrote:
> gettimeofday.S was originally removed with the introduction of the
> support for Unified vDSOs in arm64 and replaced with the C
> implementation.
> 
> The file seems again present in the repository due to a side effect of
> rebase.
> 
> Remove the file again.
> 
> Cc: Will Deacon <will@kernel.org>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> 
> Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>

Nitpick: don't leave a space between the Cc and the Sob lines, it all
comes as a single block.

Acked-by: Catalin Marinas <catalin.marinas@arm.com>

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^ permalink raw reply

* Re: [PATCH 3/4] arm64: vdso32: Fix compilation warning
From: Catalin Marinas @ 2019-09-26  8:32 UTC (permalink / raw)
  To: Vincenzo Frascino
  Cc: ard.biesheuvel, ndesaulniers, linux-kernel, tglx, will,
	linux-arm-kernel
In-Reply-To: <20190926060353.54894-4-vincenzo.frascino@arm.com>

On Thu, Sep 26, 2019 at 07:03:52AM +0100, Vincenzo Frascino wrote:
> diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h
> index b61b50bf68b1..b1c8c43234c5 100644
> --- a/arch/arm64/include/asm/memory.h
> +++ b/arch/arm64/include/asm/memory.h
> @@ -228,11 +228,16 @@ static inline unsigned long kaslr_offset(void)
>  #define __tag_get(addr)		0
>  #endif /* CONFIG_KASAN_SW_TAGS */
>  
> +#ifdef __aarch64__
>  static inline const void *__tag_set(const void *addr, u8 tag)
>  {
>  	u64 __addr = (u64)addr & ~__tag_shifted(0xff);
>  	return (const void *)(__addr | __tag_shifted(tag));
>  }
> +#else
> +/* Unused in 32 bit mode */
> +#define __tag_set(addr, tag) 0
> +#endif

I'm fine with this as a temporary workaround (or hack). But please add a
better comment on what the 32-bit mode is about - the compat vDSO.

-- 
Catalin

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* Re: [PATCH 2/4] arm64: vdso32: Detect binutils support for dmb ishld
From: Catalin Marinas @ 2019-09-26  8:30 UTC (permalink / raw)
  To: Vincenzo Frascino
  Cc: ard.biesheuvel, ndesaulniers, linux-kernel, tglx, will,
	linux-arm-kernel
In-Reply-To: <20190926060353.54894-3-vincenzo.frascino@arm.com>

On Thu, Sep 26, 2019 at 07:03:51AM +0100, Vincenzo Frascino wrote:
> diff --git a/arch/arm64/include/asm/vdso/compat_barrier.h b/arch/arm64/include/asm/vdso/compat_barrier.h
> index fb60a88b5ed4..3fd8fd6d8fc2 100644
> --- a/arch/arm64/include/asm/vdso/compat_barrier.h
> +++ b/arch/arm64/include/asm/vdso/compat_barrier.h
> @@ -20,7 +20,7 @@
>  
>  #define dmb(option) __asm__ __volatile__ ("dmb " #option : : : "memory")
>  
> -#if __LINUX_ARM_ARCH__ >= 8
> +#if __LINUX_ARM_ARCH__ >= 8 && defined(CONFIG_AS_DMB_ISHLD)
>  #define aarch32_smp_mb()	dmb(ish)
>  #define aarch32_smp_rmb()	dmb(ishld)
>  #define aarch32_smp_wmb()	dmb(ishst)
> diff --git a/arch/arm64/kernel/vdso32/Makefile b/arch/arm64/kernel/vdso32/Makefile
> index 1fba0776ed40..1a3299d901b1 100644
> --- a/arch/arm64/kernel/vdso32/Makefile
> +++ b/arch/arm64/kernel/vdso32/Makefile
> @@ -55,6 +55,9 @@ endif
>  VDSO_CAFLAGS += -fPIC -fno-builtin -fno-stack-protector
>  VDSO_CAFLAGS += -DDISABLE_BRANCH_PROFILING
>  
> +# Check for binutils support for dmb ishld
> +dmbinstr := $(call as-instr,dmb ishld,-DCONFIG_AS_DMB_ISHLD=1)

Is this check for the compat gas or the native one? Looking at
scripts/Kbuild.include, as-instr uses CC but you'd need a COMPATCC here
instead.

I may have missed something but I don't think this fixes the issue
Will's issue since he reported the problem with an old compat binutils.

-- 
Catalin

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* Re: [PATCH 06/11] PCI: of: Add inbound resource parsing to helpers
From: Andrew Murray @ 2019-09-26  8:29 UTC (permalink / raw)
  To: Rob Herring
  Cc: Heiko Stuebner, Karthikeyan Mitran, linux-pci, Linus Walleij,
	Ryder Lee, Thomas Petazzoni, Toan Le, Will Deacon,
	Lorenzo Pieralisi, Michal Simek, linux-rockchip,
	bcm-kernel-feedback-list, Shawn Lin, Ray Jui, Hou Zhiqiang,
	Simon Horman, linux-mediatek, Bjorn Helgaas, linux-arm-kernel,
	Scott Branden, Jingoo Han, rfi, linux-renesas-soc, Tom Joseph,
	Gustavo Pimentel, Ley Foon Tan
In-Reply-To: <20190924214630.12817-7-robh@kernel.org>

On Tue, Sep 24, 2019 at 04:46:25PM -0500, Rob Herring wrote:
> Extend devm_of_pci_get_host_bridge_resources() and
> pci_parse_request_of_pci_ranges() helpers to also parse the inbound
> addresses from DT 'dma-ranges' and populate a resource list with the
> translated addresses. This will help ensure 'dma-ranges' is always
> parsed in a consistent way.
> 
> Cc: Jingoo Han <jingoohan1@gmail.com>
> Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Cc: Bjorn Helgaas <bhelgaas@google.com>
> Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Linus Walleij <linus.walleij@linaro.org>
> Cc: Toan Le <toan@os.amperecomputing.com>
> Cc: Ley Foon Tan <lftan@altera.com>
> Cc: Tom Joseph <tjoseph@cadence.com>
> Cc: Ray Jui <rjui@broadcom.com>
> Cc: Scott Branden <sbranden@broadcom.com>
> Cc: bcm-kernel-feedback-list@broadcom.com
> Cc: Ryder Lee <ryder.lee@mediatek.com>
> Cc: Karthikeyan Mitran <m.karthikeyan@mobiveil.co.in>
> Cc: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
> Cc: Simon Horman <horms@verge.net.au>
> Cc: Shawn Lin <shawn.lin@rock-chips.com>
> Cc: Heiko Stuebner <heiko@sntech.de>
> Cc: Michal Simek <michal.simek@xilinx.com>
> Cc: rfi@lists.rocketboards.org
> Cc: linux-mediatek@lists.infradead.org
> Cc: linux-renesas-soc@vger.kernel.org
> Cc: linux-rockchip@lists.infradead.org
> Signed-off-by: Rob Herring <robh@kernel.org>
> ---

Reviewed-by: Andrew Murray <andrew.murray@arm.com>

>  .../pci/controller/dwc/pcie-designware-host.c |  3 +-
>  drivers/pci/controller/pci-aardvark.c         |  2 +-
>  drivers/pci/controller/pci-ftpci100.c         |  3 +-
>  drivers/pci/controller/pci-host-common.c      |  2 +-
>  drivers/pci/controller/pci-v3-semi.c          |  2 +-
>  drivers/pci/controller/pci-versatile.c        |  2 +-
>  drivers/pci/controller/pci-xgene.c            |  1 +
>  drivers/pci/controller/pcie-altera.c          |  2 +-
>  drivers/pci/controller/pcie-cadence-host.c    |  2 +-
>  drivers/pci/controller/pcie-iproc-platform.c  |  1 +
>  drivers/pci/controller/pcie-mediatek.c        |  2 +-
>  drivers/pci/controller/pcie-mobiveil.c        |  4 +-
>  drivers/pci/controller/pcie-rcar.c            |  3 +-
>  drivers/pci/controller/pcie-rockchip-host.c   |  3 +-
>  drivers/pci/controller/pcie-xilinx-nwl.c      |  2 +-
>  drivers/pci/controller/pcie-xilinx.c          |  2 +-
>  drivers/pci/of.c                              | 44 ++++++++++++++++++-
>  drivers/pci/pci.h                             |  8 +++-
>  include/linux/pci.h                           |  2 +
>  19 files changed, 72 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index f93252d0da5b..0743ae64bb0f 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -342,7 +342,8 @@ int dw_pcie_host_init(struct pcie_port *pp)
>  		return -ENOMEM;
>  
>  	ret = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff,
> -					&bridge->windows, &pp->io_base);
> +					&bridge->windows, &bridge->dma_ranges,
> +					&pp->io_base);
>  	if (ret)
>  		return ret;
>  
> diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
> index ff3af3d34028..c00b391529f3 100644
> --- a/drivers/pci/controller/pci-aardvark.c
> +++ b/drivers/pci/controller/pci-aardvark.c
> @@ -940,7 +940,7 @@ static int advk_pcie_probe(struct platform_device *pdev)
>  	}
>  
>  	ret = pci_parse_request_of_pci_ranges(dev, &pcie->resources,
> -					      &bus);
> +					      &bridge->dma_ranges, &bus);
>  	if (ret) {
>  		dev_err(dev, "Failed to parse resources\n");
>  		return ret;
> diff --git a/drivers/pci/controller/pci-ftpci100.c b/drivers/pci/controller/pci-ftpci100.c
> index bf5ece5d9291..3e07a8203736 100644
> --- a/drivers/pci/controller/pci-ftpci100.c
> +++ b/drivers/pci/controller/pci-ftpci100.c
> @@ -481,7 +481,8 @@ static int faraday_pci_probe(struct platform_device *pdev)
>  		return PTR_ERR(p->base);
>  
>  	ret = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff,
> -						    &res, &io_base);
> +						    &res, &host->dma_ranges,
> +						    &io_base);
>  	if (ret)
>  		return ret;
>  
> diff --git a/drivers/pci/controller/pci-host-common.c b/drivers/pci/controller/pci-host-common.c
> index c742881b5061..183381c19ee8 100644
> --- a/drivers/pci/controller/pci-host-common.c
> +++ b/drivers/pci/controller/pci-host-common.c
> @@ -27,7 +27,7 @@ static struct pci_config_window *gen_pci_init(struct device *dev,
>  	struct pci_config_window *cfg;
>  
>  	/* Parse our PCI ranges and request their resources */
> -	err = pci_parse_request_of_pci_ranges(dev, resources, &bus_range);
> +	err = pci_parse_request_of_pci_ranges(dev, resources, NULL, &bus_range);
>  	if (err)
>  		return ERR_PTR(err);
>  
> diff --git a/drivers/pci/controller/pci-v3-semi.c b/drivers/pci/controller/pci-v3-semi.c
> index d219404bad92..090df766faf9 100644
> --- a/drivers/pci/controller/pci-v3-semi.c
> +++ b/drivers/pci/controller/pci-v3-semi.c
> @@ -794,7 +794,7 @@ static int v3_pci_probe(struct platform_device *pdev)
>  		return PTR_ERR(v3->config_base);
>  
>  	ret = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff, &res,
> -						    &io_base);
> +						    &host->dma_ranges, &io_base);
>  	if (ret)
>  		return ret;
>  
> diff --git a/drivers/pci/controller/pci-versatile.c b/drivers/pci/controller/pci-versatile.c
> index 237b1abb26f2..211159f54b4a 100644
> --- a/drivers/pci/controller/pci-versatile.c
> +++ b/drivers/pci/controller/pci-versatile.c
> @@ -93,7 +93,7 @@ static int versatile_pci_probe(struct platform_device *pdev)
>  	if (IS_ERR(versatile_cfg_base[1]))
>  		return PTR_ERR(versatile_cfg_base[1]);
>  
> -	ret = pci_parse_request_of_pci_ranges(dev, &pci_res, NULL);
> +	ret = pci_parse_request_of_pci_ranges(dev, &pci_res, NULL, NULL);
>  	if (ret)
>  		return ret;
>  
> diff --git a/drivers/pci/controller/pci-xgene.c b/drivers/pci/controller/pci-xgene.c
> index ffda3e8b4742..11f27c42c06a 100644
> --- a/drivers/pci/controller/pci-xgene.c
> +++ b/drivers/pci/controller/pci-xgene.c
> @@ -635,6 +635,7 @@ static int xgene_pcie_probe(struct platform_device *pdev)
>  		return ret;
>  
>  	ret = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff, &res,
> +						    &bridge->dma_ranges,
>  						    &iobase);
>  	if (ret)
>  		return ret;
> diff --git a/drivers/pci/controller/pcie-altera.c b/drivers/pci/controller/pcie-altera.c
> index 2ed00babff5a..fde6a3b16fb9 100644
> --- a/drivers/pci/controller/pcie-altera.c
> +++ b/drivers/pci/controller/pcie-altera.c
> @@ -801,7 +801,7 @@ static int altera_pcie_probe(struct platform_device *pdev)
>  	}
>  
>  	ret = pci_parse_request_of_pci_ranges(dev, &pcie->resources,
> -					      NULL);
> +					      &bridge->dma_ranges, NULL);
>  	if (ret) {
>  		dev_err(dev, "Failed add resources\n");
>  		return ret;
> diff --git a/drivers/pci/controller/pcie-cadence-host.c b/drivers/pci/controller/pcie-cadence-host.c
> index 97e251090b4f..a8f7a6284c3e 100644
> --- a/drivers/pci/controller/pcie-cadence-host.c
> +++ b/drivers/pci/controller/pcie-cadence-host.c
> @@ -211,7 +211,7 @@ static int cdns_pcie_host_init(struct device *dev,
>  	int err;
>  
>  	/* Parse our PCI ranges and request their resources */
> -	err = pci_parse_request_of_pci_ranges(dev, resources, &bus_range);
> +	err = pci_parse_request_of_pci_ranges(dev, resources, NULL, &bus_range);
>  	if (err)
>  		return err;
>  
> diff --git a/drivers/pci/controller/pcie-iproc-platform.c b/drivers/pci/controller/pcie-iproc-platform.c
> index 5a3550b6bb29..62eee2d17f43 100644
> --- a/drivers/pci/controller/pcie-iproc-platform.c
> +++ b/drivers/pci/controller/pcie-iproc-platform.c
> @@ -101,6 +101,7 @@ static int iproc_pcie_pltfm_probe(struct platform_device *pdev)
>  	}
>  
>  	ret = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff, &resources,
> +						    &bridge->dma_ranges,
>  						    &iobase);
>  	if (ret) {
>  		dev_err(dev, "unable to get PCI host bridge resources\n");
> diff --git a/drivers/pci/controller/pcie-mediatek.c b/drivers/pci/controller/pcie-mediatek.c
> index cea4112b5309..f3996eed152d 100644
> --- a/drivers/pci/controller/pcie-mediatek.c
> +++ b/drivers/pci/controller/pcie-mediatek.c
> @@ -1032,7 +1032,7 @@ static int mtk_pcie_setup(struct mtk_pcie *pcie)
>  	int err;
>  
>  	err = pci_parse_request_of_pci_ranges(dev, windows,
> -					      &bus);
> +					      &host->dma_ranges, &bus);
>  	if (err)
>  		return err;
>  
> diff --git a/drivers/pci/controller/pcie-mobiveil.c b/drivers/pci/controller/pcie-mobiveil.c
> index 672e633601c7..93064faaa656 100644
> --- a/drivers/pci/controller/pcie-mobiveil.c
> +++ b/drivers/pci/controller/pcie-mobiveil.c
> @@ -875,7 +875,9 @@ static int mobiveil_pcie_probe(struct platform_device *pdev)
>  
>  	/* parse the host bridge base addresses from the device tree file */
>  	ret = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff,
> -						    &pcie->resources, &iobase);
> +						    &pcie->resources,
> +						    &bridge->dma_ranges,
> +						    &iobase);
>  	if (ret) {
>  		dev_err(dev, "Getting bridge resources failed\n");
>  		return ret;
> diff --git a/drivers/pci/controller/pcie-rcar.c b/drivers/pci/controller/pcie-rcar.c
> index f6a669a9af41..b8d6e86a5539 100644
> --- a/drivers/pci/controller/pcie-rcar.c
> +++ b/drivers/pci/controller/pcie-rcar.c
> @@ -1138,7 +1138,8 @@ static int rcar_pcie_probe(struct platform_device *pdev)
>  	pcie->dev = dev;
>  	platform_set_drvdata(pdev, pcie);
>  
> -	err = pci_parse_request_of_pci_ranges(dev, &pcie->resources, NULL);
> +	err = pci_parse_request_of_pci_ranges(dev, &pcie->resources,
> +					      &bridge->dma_ranges, NULL);
>  	if (err)
>  		goto err_free_bridge;
>  
> diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/controller/pcie-rockchip-host.c
> index 8d20f1793a61..093b816b9dc9 100644
> --- a/drivers/pci/controller/pcie-rockchip-host.c
> +++ b/drivers/pci/controller/pcie-rockchip-host.c
> @@ -996,7 +996,8 @@ static int rockchip_pcie_probe(struct platform_device *pdev)
>  		goto err_deinit_port;
>  
>  	err = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff,
> -						    &res, &io_base);
> +						    &res, &bridge->dma_ranges,
> +						    &io_base);
>  	if (err)
>  		goto err_remove_irq_domain;
>  
> diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c
> index 45c0f344ccd1..5c9132a02d15 100644
> --- a/drivers/pci/controller/pcie-xilinx-nwl.c
> +++ b/drivers/pci/controller/pcie-xilinx-nwl.c
> @@ -846,7 +846,7 @@ static int nwl_pcie_probe(struct platform_device *pdev)
>  	}
>  
>  	err = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff, &res,
> -						    &iobase);
> +						    &bridge->dma_ranges, &iobase);
>  	if (err) {
>  		dev_err(dev, "Getting bridge resources failed\n");
>  		return err;
> diff --git a/drivers/pci/controller/pcie-xilinx.c b/drivers/pci/controller/pcie-xilinx.c
> index 5bf3af3b28e6..a95faca30291 100644
> --- a/drivers/pci/controller/pcie-xilinx.c
> +++ b/drivers/pci/controller/pcie-xilinx.c
> @@ -648,7 +648,7 @@ static int xilinx_pcie_probe(struct platform_device *pdev)
>  	}
>  
>  	err = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff, &res,
> -						    &iobase);
> +						    &bridge->dma_ranges, &iobase);
>  	if (err) {
>  		dev_err(dev, "Getting bridge resources failed\n");
>  		return err;
> diff --git a/drivers/pci/of.c b/drivers/pci/of.c
> index bc7b27a28795..8d31e078461f 100644
> --- a/drivers/pci/of.c
> +++ b/drivers/pci/of.c
> @@ -257,7 +257,9 @@ EXPORT_SYMBOL_GPL(of_pci_check_probe_only);
>   */
>  int devm_of_pci_get_host_bridge_resources(struct device *dev,
>  			unsigned char busno, unsigned char bus_max,
> -			struct list_head *resources, resource_size_t *io_base)
> +			struct list_head *resources,
> +			struct list_head *ib_resources,
> +			resource_size_t *io_base)
>  {
>  	struct device_node *dev_node = dev->of_node;
>  	struct resource *res, tmp_res;
> @@ -340,6 +342,42 @@ int devm_of_pci_get_host_bridge_resources(struct device *dev,
>  		pci_add_resource_offset(resources, res,	res->start - range.pci_addr);
>  	}
>  
> +	/* Check for dma-ranges property */
> +	if (!ib_resources)
> +		return 0;
> +	err = of_pci_dma_range_parser_init(&parser, dev_node);
> +	if (err)
> +		return 0;
> +
> +	dev_dbg(dev, "Parsing dma-ranges property...\n");
> +	for_each_of_pci_range(&parser, &range) {
> +		/*
> +		 * If we failed translation or got a zero-sized region
> +		 * then skip this range
> +		 */
> +		if (((range.flags & IORESOURCE_TYPE_BITS) != IORESOURCE_MEM) ||
> +		    range.cpu_addr == OF_BAD_ADDR || range.size == 0)
> +			continue;
> +
> +		dev_info(dev, "IB MEM %#010llx..%#010llx -> %#010llx\n",
> +			 range.cpu_addr,
> +			 range.cpu_addr + range.size - 1, range.pci_addr);
> +
> +
> +		err = of_pci_range_to_resource(&range, dev_node, &tmp_res);
> +		if (err)
> +			continue;
> +
> +		res = devm_kmemdup(dev, &tmp_res, sizeof(tmp_res), GFP_KERNEL);
> +		if (!res) {
> +			err = -ENOMEM;
> +			goto failed;
> +		}
> +
> +		pci_add_resource_offset(ib_resources, res,
> +					res->start - range.pci_addr);
> +	}
> +
>  	return 0;
>  
>  failed:
> @@ -482,6 +520,7 @@ EXPORT_SYMBOL_GPL(of_irq_parse_and_map_pci);
>  
>  int pci_parse_request_of_pci_ranges(struct device *dev,
>  				    struct list_head *resources,
> +				    struct list_head *ib_resources,
>  				    struct resource **bus_range)
>  {
>  	int err, res_valid = 0;
> @@ -489,8 +528,9 @@ int pci_parse_request_of_pci_ranges(struct device *dev,
>  	struct resource_entry *win, *tmp;
>  
>  	INIT_LIST_HEAD(resources);
> +	INIT_LIST_HEAD(ib_resources);
>  	err = devm_of_pci_get_host_bridge_resources(dev, 0, 0xff, resources,
> -						    &iobase);
> +						    ib_resources, &iobase);
>  	if (err)
>  		return err;
>  
> diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
> index d22d1b807701..790458953c54 100644
> --- a/drivers/pci/pci.h
> +++ b/drivers/pci/pci.h
> @@ -582,11 +582,15 @@ of_pci_get_max_link_speed(struct device_node *node)
>  #if defined(CONFIG_OF_ADDRESS)
>  int devm_of_pci_get_host_bridge_resources(struct device *dev,
>  			unsigned char busno, unsigned char bus_max,
> -			struct list_head *resources, resource_size_t *io_base);
> +			struct list_head *resources,
> +			struct list_head *ib_resources,
> +			resource_size_t *io_base);
>  #else
>  static inline int devm_of_pci_get_host_bridge_resources(struct device *dev,
>  			unsigned char busno, unsigned char bus_max,
> -			struct list_head *resources, resource_size_t *io_base)
> +			struct list_head *resources,
> +			struct list_head *ib_resources,
> +			resource_size_t *io_base);
>  {
>  	return -EINVAL;
>  }
> diff --git a/include/linux/pci.h b/include/linux/pci.h
> index 82e4cd1b7ac3..d57389b86f92 100644
> --- a/include/linux/pci.h
> +++ b/include/linux/pci.h
> @@ -2312,6 +2312,7 @@ void pci_release_bus_of_node(struct pci_bus *bus);
>  struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
>  int pci_parse_request_of_pci_ranges(struct device *dev,
>  				    struct list_head *resources,
> +				    struct list_head *ib_resources,
>  				    struct resource **bus_range);
>  
>  /* Arch may override this (weak) */
> @@ -2326,6 +2327,7 @@ static inline struct irq_domain *
>  pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
>  static inline int pci_parse_request_of_pci_ranges(struct device *dev,
>  						  struct list_head *resources,
> +						  struct list_head *ib_resources,
>  						  struct resource **bus_range)
>  {
>  	return -EINVAL;
> -- 
> 2.20.1
> 
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

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* [PATCH v2 3/3] drm/rockchip: Add support 10bit yuv format
From: Sandy Huang @ 2019-09-26  8:24 UTC (permalink / raw)
  To: dri-devel, Sandy Huang, Heiko Stübner, David Airlie,
	Daniel Vetter
  Cc: linux-rockchip, maarten.lankhorst, linux-kernel, linux-arm-kernel
In-Reply-To: <1569486289-152061-1-git-send-email-hjc@rock-chips.com>

Add support 10bit yuv format display for rockchip some socs,
include:
    RK3288/RK3228/RK3328/RK3368/RK3399

Signed-off-by: Sandy Huang <hjc@rock-chips.com>
---
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 16 ++++++++++++++++
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h |  1 +
 drivers/gpu/drm/rockchip/rockchip_vop_reg.c |  2 ++
 3 files changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index ce74218..4b87d88 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -249,6 +249,21 @@ static bool has_rb_swapped(uint32_t format)
 	}
 }
 
+static bool is_10bit_yuv(uint32_t format)
+{
+	switch (format) {
+	case DRM_FORMAT_NV12_10:
+	case DRM_FORMAT_NV21_10:
+	case DRM_FORMAT_NV16_10:
+	case DRM_FORMAT_NV61_10:
+	case DRM_FORMAT_NV24_10:
+	case DRM_FORMAT_NV42_10:
+		return true;
+	default:
+		return false;
+	}
+}
+
 static u32 rockchip_vop_get_offset(struct drm_plane_state *state, u8 plane)
 {
 	const struct drm_format_info *info;
@@ -913,6 +928,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
 		dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
 		VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4));
 		VOP_WIN_SET(vop, win, uv_mst, dma_addr);
+		VOP_WIN_SET(vop, win, fmt_10, is_10bit_yuv(fb->format->format));
 
 		for (i = 0; i < NUM_YUV2YUV_COEFFICIENTS; i++) {
 			VOP_WIN_YUV2YUV_COEFFICIENT_SET(vop,
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
index 2149a889..adc2b0b5 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
@@ -133,6 +133,7 @@ struct vop_win_phy {
 	struct vop_reg gate;
 	struct vop_reg format;
 	struct vop_reg rb_swap;
+	struct vop_reg fmt_10;
 	struct vop_reg act_info;
 	struct vop_reg dsp_info;
 	struct vop_reg dsp_st;
diff --git a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
index d1494be..732e535 100644
--- a/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
+++ b/drivers/gpu/drm/rockchip/rockchip_vop_reg.c
@@ -544,6 +544,7 @@ static const struct vop_win_phy rk3288_win01_data = {
 	.nformats = ARRAY_SIZE(formats_win_full),
 	.enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
 	.format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
+	.fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 4),
 	.rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
 	.act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
 	.dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
@@ -674,6 +675,7 @@ static const struct vop_win_phy rk3368_win01_data = {
 	.nformats = ARRAY_SIZE(formats_win_full),
 	.enable = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 0),
 	.format = VOP_REG(RK3368_WIN0_CTRL0, 0x7, 1),
+	.fmt_10 = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 4),
 	.rb_swap = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 12),
 	.x_mir_en = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 21),
 	.y_mir_en = VOP_REG(RK3368_WIN0_CTRL0, 0x1, 22),
-- 
2.7.4




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* [PATCH v2 2/3] drm/rockchip: Add rockchip_vop_get_offset to get offset
From: Sandy Huang @ 2019-09-26  8:24 UTC (permalink / raw)
  To: dri-devel, Sandy Huang, Heiko Stübner, David Airlie,
	Daniel Vetter
  Cc: linux-rockchip, maarten.lankhorst, linux-kernel, linux-arm-kernel
In-Reply-To: <1569486289-152061-1-git-send-email-hjc@rock-chips.com>

Add rockchip_vop_get_offset to get offset, this can compatible legacy
and block_h/w format describe.

Signed-off-by: Sandy Huang <hjc@rock-chips.com>
---
 drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 61 ++++++++++++++++++++++++-----
 1 file changed, 52 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 2f821c5..ce74218 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -249,6 +249,56 @@ static bool has_rb_swapped(uint32_t format)
 	}
 }
 
+static u32 rockchip_vop_get_offset(struct drm_plane_state *state, u8 plane)
+{
+	const struct drm_format_info *info;
+	struct drm_rect *src = &state->src;
+	struct drm_framebuffer *fb = state->fb;
+	u32 format = fb->format->format;
+	u8 h_div = 1, v_div = 1;
+	u32 block_w, block_h, block_size, block_start_y, num_hblocks;
+	u32 sample_x, sample_y;
+	u32 offset;
+
+	info = drm_format_info(format);
+	if (!info || plane >= info->num_planes)
+		return 0;
+
+	if (plane > 0) {
+		h_div = fb->format->hsub;
+		v_div = fb->format->vsub;
+	}
+
+	switch (format) {
+	case DRM_FORMAT_NV12_10:
+	case DRM_FORMAT_NV21_10:
+	case DRM_FORMAT_NV16_10:
+	case DRM_FORMAT_NV61_10:
+	case DRM_FORMAT_NV24_10:
+	case DRM_FORMAT_NV42_10:
+		block_w = drm_format_info_block_width(fb->format, plane);
+		block_h = drm_format_info_block_height(fb->format, plane);
+		block_size = fb->format->char_per_block[plane];
+
+		sample_x = (src->x1 >> 16) / h_div;
+		sample_y = (src->y1 >> 16) / v_div;
+		block_start_y = (sample_y / block_h) * block_h;
+		num_hblocks = sample_x / block_w;
+
+		offset = fb->pitches[plane] * block_start_y;
+		offset += block_size * num_hblocks;
+
+		break;
+	default:
+		offset = (src->x1 >> 16) * fb->format->cpp[plane] / h_div;
+		offset += (src->y1 >> 16) * fb->pitches[plane] / v_div;
+
+		break;
+	}
+
+	return offset;
+}
+
 static enum vop_data_format vop_convert_format(uint32_t format)
 {
 	switch (format) {
@@ -832,8 +882,7 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
 	dsp_sty = dest->y1 + crtc->mode.vtotal - crtc->mode.vsync_start;
 	dsp_st = dsp_sty << 16 | (dsp_stx & 0xffff);
 
-	offset = (src->x1 >> 16) * fb->format->cpp[0];
-	offset += (src->y1 >> 16) * fb->pitches[0];
+	offset = rockchip_vop_get_offset(state, 0);
 	dma_addr = rk_obj->dma_addr + offset + fb->offsets[0];
 
 	/*
@@ -857,16 +906,10 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
 		    (state->rotation & DRM_MODE_REFLECT_X) ? 1 : 0);
 
 	if (is_yuv) {
-		int hsub = fb->format->hsub;
-		int vsub = fb->format->vsub;
-		int bpp = fb->format->cpp[1];
-
 		uv_obj = fb->obj[1];
 		rk_uv_obj = to_rockchip_obj(uv_obj);
 
-		offset = (src->x1 >> 16) * bpp / hsub;
-		offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
-
+		offset = rockchip_vop_get_offset(state, 1);
 		dma_addr = rk_uv_obj->dma_addr + offset + fb->offsets[1];
 		VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4));
 		VOP_WIN_SET(vop, win, uv_mst, dma_addr);
-- 
2.7.4




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* Re: [PATCH 04/11] PCI: versatile: Enable COMPILE_TEST
From: Andrew Murray @ 2019-09-26  8:12 UTC (permalink / raw)
  To: Rob Herring; +Cc: Bjorn Helgaas, linux-pci, Lorenzo Pieralisi, linux-arm-kernel
In-Reply-To: <20190924214630.12817-5-robh@kernel.org>

On Tue, Sep 24, 2019 at 04:46:23PM -0500, Rob Herring wrote:
> Since commit a574795bc383 ("PCI: generic,versatile: Remove unused
> pci_sys_data structures") the build dependency on ARM is gone, so let's
> enable COMPILE_TEST for versatile.
> 
> Signed-off-by: Rob Herring <robh@kernel.org>

Reviewed-by: Andrew Murray <andrew.murray@arm.com>

> ---
>  drivers/pci/controller/Kconfig | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig
> index fe9f9f13ce11..14836229357e 100644
> --- a/drivers/pci/controller/Kconfig
> +++ b/drivers/pci/controller/Kconfig
> @@ -135,7 +135,7 @@ config PCI_V3_SEMI
>  
>  config PCI_VERSATILE
>  	bool "ARM Versatile PB PCI controller"
> -	depends on ARCH_VERSATILE
> +	depends on ARCH_VERSATILE || COMPILE_TEST
>  
>  config PCIE_IPROC
>  	tristate
> -- 
> 2.20.1
> 
> 
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> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

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* Re: [PATCH 1/4] arm64: vdso32: Introduce COMPAT_CC_IS_GCC
From: Catalin Marinas @ 2019-09-26  8:06 UTC (permalink / raw)
  To: Vincenzo Frascino
  Cc: ard.biesheuvel, ndesaulniers, linux-kernel, tglx, will,
	linux-arm-kernel
In-Reply-To: <20190926060353.54894-2-vincenzo.frascino@arm.com>

On Thu, Sep 26, 2019 at 07:03:50AM +0100, Vincenzo Frascino wrote:
> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> index 37c610963eee..afe8c948b493 100644
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -110,7 +110,7 @@ config ARM64
>  	select GENERIC_STRNLEN_USER
>  	select GENERIC_TIME_VSYSCALL
>  	select GENERIC_GETTIMEOFDAY
> -	select GENERIC_COMPAT_VDSO if (!CPU_BIG_ENDIAN && COMPAT)
> +	select GENERIC_COMPAT_VDSO if (!CPU_BIG_ENDIAN && COMPAT && COMPAT_CC_IS_GCC)
>  	select HANDLE_DOMAIN_IRQ
>  	select HARDIRQS_SW_RESEND
>  	select HAVE_PCI
> @@ -313,6 +313,9 @@ config KASAN_SHADOW_OFFSET
>  	default 0xeffffff900000000 if ARM64_VA_BITS_36 && KASAN_SW_TAGS
>  	default 0xffffffffffffffff
>  
> +config COMPAT_CC_IS_GCC
> +	def_bool $(success,$(CROSS_COMPILE_COMPAT)gcc --version | head -n 1 | grep -q arm)

Nitpick: I prefer COMPATCC instead of COMPAT_CC for consistency with
HOSTCC.

Now, could we not generate a COMPATCC in the Makefile and use
$(COMPATCC) here instead of $(CROSS_COMPILE_COMPAT)gcc? It really
doesn't make sense to check that gcc is gcc.

A next step would be to check that COMPATCC can actually generate 32-bit
objects. But it's not essential at this stage.

> diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile
> index 84a3d502c5a5..34f53eb11878 100644
> --- a/arch/arm64/Makefile
> +++ b/arch/arm64/Makefile
> @@ -54,19 +54,8 @@ $(warning Detected assembler with broken .inst; disassembly will be unreliable)
>  endif
>  
>  ifeq ($(CONFIG_GENERIC_COMPAT_VDSO), y)
> -  CROSS_COMPILE_COMPAT ?= $(CONFIG_CROSS_COMPILE_COMPAT_VDSO:"%"=%)
> -
> -  ifeq ($(CONFIG_CC_IS_CLANG), y)
> -    $(warning CROSS_COMPILE_COMPAT is clang, the compat vDSO will not be built)
> -  else ifeq ($(strip $(CROSS_COMPILE_COMPAT)),)
> -    $(warning CROSS_COMPILE_COMPAT not defined or empty, the compat vDSO will not be built)
> -  else ifeq ($(shell which $(CROSS_COMPILE_COMPAT)gcc 2> /dev/null),)
> -    $(error $(CROSS_COMPILE_COMPAT)gcc not found, check CROSS_COMPILE_COMPAT)
> -  else
> -    export CROSS_COMPILE_COMPAT
> -    export CONFIG_COMPAT_VDSO := y
> -    compat_vdso := -DCONFIG_COMPAT_VDSO=1
> -  endif
> +  export CONFIG_COMPAT_VDSO := y
> +  compat_vdso := -DCONFIG_COMPAT_VDSO=1
>  endif

Has CONFIG_CROSS_COMPILE_COMPAT_VDSO actually been removed from
lib/vdso/Kconfig? (I haven't checked the subsequent patches).

-- 
Catalin

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