* Re: [PATCH v7 11/11] media: platform: Add jpeg dec/enc feature
From: Tomasz Figa @ 2020-05-20 19:40 UTC (permalink / raw)
To: Xia Jiang
Cc: devicetree, srv_heupstream, Rick Chang, linux-kernel,
Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, linux-mediatek, Marek Szyprowski, linux-arm-kernel,
linux-media
In-Reply-To: <1589020095.24163.150.camel@mhfsdcap03>
Hi Xia,
On Sat, May 09, 2020 at 06:28:15PM +0800, Xia Jiang wrote:
> On Fri, 2020-05-01 at 17:37 +0000, Tomasz Figa wrote:
> > Hi Xia,
> >
> > On Thu, Apr 16, 2020 at 12:03:15PM +0800, Xia Jiang wrote:
> > > On Fri, 2020-03-06 at 20:23 +0900, Tomasz Figa wrote:
> > > > Hi Xia,
> > > >
> > > > On Tue, Mar 03, 2020 at 08:34:46PM +0800, Xia Jiang wrote:
> > > > > Add mtk jpeg encode v4l2 driver based on jpeg decode, because that jpeg
> > > > > decode and encode have great similarities with function operation.
> > > >
> > > > Thank you for the patch. Please see my comments inline.
> > >
> > > Dear Tomasz,
> > >
> > > Thank you for your reply. I have followed your advice and submited v8
> > > version patch.
> > >
> > > Please check my reply below.
> Dear Tomasz,
> I have some confuse about your advice, please check my reply below.
Sorry for the late reply again. Please see my reply inline.
> > [snip]
> > > >
> > > > >
> > > > > - switch (s->target) {
> > > > > - case V4L2_SEL_TGT_COMPOSE:
> > > > > - s->r.left = 0;
> > > > > - s->r.top = 0;
> > > > > - ctx->out_q.w = s->r.width;
> > > > > - ctx->out_q.h = s->r.height;
> > > > > - break;
> > > > > - default:
> > > > > - return -EINVAL;
> > > > > + switch (s->target) {
> > > > > + case V4L2_SEL_TGT_CROP:
> > > > > + s->r.left = 0;
> > > > > + s->r.top = 0;
> > > > > + ctx->out_q.w = s->r.width;
> > > > > + ctx->out_q.h = s->r.height;
> > > >
> > > > What happens if the userspace provides a value bigger than current format?
> > > we need get the min value of userspace value and current value,changed
> > > it like this:
> > > ctx->out_q.w = min(s->r.width, ctx->out_q.w);
> > > ctx->out_q.h = min(s->r.height,ctx->out_q.h);
> >
> > Since ctx->out_q is modified by this function, wouldn't that cause
> > problems if S_SELECTION was called two times, first with a smaller
> > rectangle and then with a bigger one? We should store the active crop
> > and format separately and use the latter for min().
> Add a member variable(struct v4l2_rect) in out_q structure for storing
> the active crop, like this:
> s->r.width = min(s->r.width, ctx->out_q.w);
> s->r.height = min(s->r.height,ctx->out_q.h);
> ctx->out_q.rect.width = s->r.width;
> ctx->out_q.rect.height = s->r.height;
> Is that ok?
Yes. I'd call it crop_rect and it can be simplified further into:
ct->out_q.crop_rect = s->r;
> >
> > [snip]
> > > > >
> > > > > while ((vb = mtk_jpeg_buf_remove(ctx, q->type)))
> > > > > v4l2_m2m_buf_done(vb, VB2_BUF_STATE_ERROR);
> > > > > @@ -772,6 +1011,45 @@ static int mtk_jpeg_set_dec_dst(struct mtk_jpeg_ctx *ctx,
> > > > > return 0;
> > > > > }
> > > > >
> > > > > +static void mtk_jpeg_set_enc_dst(struct mtk_jpeg_ctx *ctx, void __iomem *base,
> > > > > + struct vb2_buffer *dst_buf,
> > > > > + struct mtk_jpeg_enc_bs *bs)
> > > > > +{
> > > > > + bs->dma_addr = vb2_dma_contig_plane_dma_addr(dst_buf, 0);
> > > > > + bs->dma_addr_offset = ctx->enable_exif ? MTK_JPEG_DEFAULT_EXIF_SIZE : 0;
> > > >
> > > > Could you explain what is the meaning of the dma_addr_offset and where the
> > > > default EXIF size comes from? Also, how is the encoder output affected by
> > > > the enable_exif flag?
> > > If enabled the exif mode, the real output will be filled at the locaiton
> > > of dst_addr+ dma_addr_offset(exif size).The dma_addr_offset will be
> > > filled by the application.
> > > The default exif size is setted as constant value 64k according to the
> > > spec.(Exif metadata are restricted in size to 64kB in JPEG images
> > > because according to the specification this information must be
> > > contained within a signed JPEG APP1 segment)
> >
> > Okay, thanks. Then it sounds like MTK_JPEG_MAX_EXIF_SIZE could be a more
> > appropriate name.
> >
> > [snip]
> > > > > +}
> > > > > +
> > > > > static void mtk_jpeg_device_run(void *priv)
> > > > > {
> > > > > struct mtk_jpeg_ctx *ctx = priv;
> > > > > @@ -782,6 +1060,8 @@ static void mtk_jpeg_device_run(void *priv)
> > > > > struct mtk_jpeg_src_buf *jpeg_src_buf;
> > > > > struct mtk_jpeg_bs bs;
> > > > > struct mtk_jpeg_fb fb;
> > > > > + struct mtk_jpeg_enc_bs enc_bs;
> > > > > + struct mtk_jpeg_enc_fb enc_fb;
> > > > > int i;
> > > > >
> > > > > src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
> > > > > @@ -792,30 +1072,47 @@ static void mtk_jpeg_device_run(void *priv)
> > > > > for (i = 0; i < dst_buf->vb2_buf.num_planes; i++)
> > > > > vb2_set_plane_payload(&dst_buf->vb2_buf, i, 0);
> > > > > buf_state = VB2_BUF_STATE_DONE;
> > > >
> > > > About existing code, but we may want to explain this.
> > > > What is this last frame handling above for?
> > > if the user gives us a empty buffer(means it is the last frame),the
> > > driver will not encode and done the buffer to the user.
> > >
> >
> > An empty buffer is not a valid way of signaling a last frame in V4L2. In
> > general, I'm not sure there is such a thing in JPEG, because all frames
> > are separate from each other and we always expect 1 input buffer and 1
> > output buffer for one frame. We might want to remove the special
> > handling in a follow up patch.
> How does application to end jpeg operation in motion jpeg if we remove
> this? I tryed to end with the condition that the input number equals
> output number in UT, and is ok.
That's correct. The operation ends when the number of CAPTURE buffers
dequeued is the same as the number of OUTPUT buffers queued.
> >
> > > > > - goto dec_end;
> > > > > + goto device_run_end;
> > > > > }
> > > > >
> > > > > - if (mtk_jpeg_check_resolution_change(ctx, &jpeg_src_buf->dec_param)) {
> > > > > - mtk_jpeg_queue_src_chg_event(ctx);
> > > > > - ctx->state = MTK_JPEG_SOURCE_CHANGE;
> > > > > - v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx);
> > > > > - return;
> > > > > - }
> > > > > + if (jpeg->mode == MTK_JPEG_ENC) {
> > > > > + spin_lock_irqsave(&jpeg->hw_lock, flags);
> > > > > + mtk_jpeg_enc_reset(jpeg->reg_base);
> > > >
> > > > Why do we need to reset every frame?
> > > We do this operation is to ensure that all registers are cleared.
> > > It's safer from the hardware point of view.
> >
> > Wouldn't this only waste power? If we reset the hardware after powering
> > up, the only registers that could change would be changed by the driver
> > itself. The driver should program all registers properly when starting
> > next frame anyway, so such a reset shouldn't be necessary.
> I confirmed with hardware designer again that we need to reset every
> frame. If we do not do like this, unexpected mistakes may occur.
Okay, thanks for double checking. Please add a comment to the code that it
is a hardware requirement.
> >
> > > >
> > > > > +
> > > > > + mtk_jpeg_set_enc_dst(ctx, jpeg->reg_base, &dst_buf->vb2_buf,
> > > > > + &enc_bs);
> > > > > + mtk_jpeg_set_enc_src(ctx, jpeg->reg_base, &src_buf->vb2_buf,
> > > > > + &enc_fb);
> > > > > + mtk_jpeg_enc_set_ctrl_cfg(jpeg->reg_base, ctx->enable_exif,
> > > > > + ctx->enc_quality,
> > > > > + ctx->restart_interval);
> > > > > +
> > > > > + mtk_jpeg_enc_start(jpeg->reg_base);
> > > > > + } else {
> > > > > + if (mtk_jpeg_check_resolution_change
> > > > > + (ctx, &jpeg_src_buf->dec_param)) {
> > > > > + mtk_jpeg_queue_src_chg_event(ctx);
> > > > > + ctx->state = MTK_JPEG_SOURCE_CHANGE;
> > > > > + v4l2_m2m_job_finish(jpeg->m2m_dev, ctx->fh.m2m_ctx);
> > > >
> > > > This is a bit strange. Resolution change should be signaled when the
> > > > hardware attempted to decode a frame and detected a different resolution
> > > > than current. It shouldn't be necessary for the userspace to queue a pair
> > > > of buffers to signal it, as with the current code.
> > > If the the resolution is bigger than current, the current buffer will
> > > not be enough for the changed resolution.Shouldn't it tell the userspace
> > > to queue new buffer and stream on again?
> >
> > The V4L2 decode flow is as follows:
> > - application configures and starts only the OUTPUT queue,
> > - application queues an OUTPUT buffer with a frame worth of bitstream,
> > - decoder parses the bitstream headers, detects CAPTURE format and
> > signals the source change event,
> > - application reads CAPTURE format and configures and starts the
> > CAPTURE queue,
> > - application queues a CAPTURE buffer,
> > - decoder decodes the image to the queued buffer.
> >
> > In case of subsequent (dynamic) resolution change:
> > - application queues an OUTPUT buffer and a CAPTURE buffer,
> > - decoder parses the bitstream, notices resolution change, updates
> > CAPTURE format and signals the source change event, refusing to
> > continue the decoding until the application acknowledges it,
> > - application either reallocates its CAPTURE buffers or confirms that
> > the existing buffers are fine and acknowledges resolution change,
> > - decoding continues.
> >
> > For more details, please check the interface specification:
> > https://www.kernel.org/doc/html/latest/media/uapi/v4l/dev-decoder.html
> >
> I tryed to move this operation from device_run() to
> mtk_jpeg_dec_buf_queue(),but have a problem in motion jpeg.For example,I
> queued three buffers continuously,the third buffer has resolution
> change(bigger than the second buffer),but the capture buffer used in
> device run didn't changed.
> How do we handle this case?
Sorry, I think I misread the driver code. It looks like there is a code
that parses the JPEG header from the source buffer called from
mtk_jpeg_dec_buf_queue() and that is the moment the driver detects the new
resolution. Then it only signals the event once all the previously queued
frames have been decoded, i.e. when the first new resolution frame gets to
device_run(). I think the current code should be fine then. Sorry for
confusion again!
> > [snip]
> > > > > - ret = video_register_device(jpeg->dec_vdev, VFL_TYPE_GRABBER, 3);
> > > > > + ret = video_register_device(jpeg->vfd_jpeg, VFL_TYPE_GRABBER, -1);
> > > >
> > > > FYI the type changed to VFL_TYPE_VIDEO recently.
> > > I changed VFL_TYPE_GRABBER to VFL_TYPE_VIDEO,but builded fail.
> >
> > What kernel version are you building with?
> I build it with the latest kernel 5.7,but builed fail again.
That's strange. There is no VFL_TYPE_GRABBER in 5.7 anymore:
https://elixir.bootlin.com/linux/v5.7-rc6/source/include/media/v4l2-dev.h#L24
Best regards,
Tomasz
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* Re: [PATCH] dt-bindings: input: touchscreen: edt-ft5x06: change reg property
From: Heiko Stübner @ 2020-05-20 18:41 UTC (permalink / raw)
To: Dmitry Torokhov
Cc: devicetree, linux-kernel, linux-rockchip, robh+dt, linux-input,
Johan Jonker, linux-arm-kernel
In-Reply-To: <20200520171324.GS89269@dtor-ws>
Hi Dmitry,
Am Mittwoch, 20. Mai 2020, 19:13:24 CEST schrieb Dmitry Torokhov:
> Hi Johan,
>
> On Wed, May 20, 2020 at 09:33:27AM +0200, Johan Jonker wrote:
> > A test with the command below gives this error:
> >
> > arch/arm/boot/dts/rk3188-bqedison2qc.dt.yaml:
> > touchscreen@3e: reg:0:0: 56 was expected
> >
> > The touchscreen chip on 'rk3188-bqedison2qc' and other BQ models
> > was shipped with different addresses then the binding currently allows.
> > Change the reg property that any address will pass.
> >
> > make ARCH=arm dtbs_check
> > DT_SCHEMA_FILES=Documentation/devicetree/bindings/input/touchscreen/
> > edt-ft5x06.yaml
> >
> > Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> > ---
> > Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.yaml | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.yaml b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.yaml
> > index 383d64a91..baa8e8f7e 100644
> > --- a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.yaml
> > +++ b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.yaml
> > @@ -42,7 +42,7 @@ properties:
> > - focaltech,ft6236
> >
> > reg:
> > - const: 0x38
> > + maxItems: 1
>
> Should we have a list of valid addresses instead of allowing any
> address? Controllers usually have only a couple of addresses that they
> support.
from what I've read, the fdt touchscreen controllers are just a generic
cpu with device-specific (or better panel-specific) firmware, which seems
to include the address as well - so it looks to be variable.
But of course that is only 2nd hand knowledge for me ;-)
But also, the i2c address is something you cannot really mess up,
either it is correct and your touchscreen works, or it isn't and and
adding entries to this list every time a new address variant pops up
feels clumsy.
Heiko
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* [PATCH v3 2/2] arm64: vdso: Fix CFI directives in sigreturn trampoline
From: Will Deacon @ 2020-05-20 17:55 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Will Deacon, Tamas Zsoldos, Mark Brown, kernel-team, Dave Martin,
Daniel Kiss
In-Reply-To: <20200520175539.28464-1-will@kernel.org>
Daniel reports that the .cfi_startproc is misplaced for the sigreturn
trampoline, which causes LLVM's unwinder to misbehave:
| I run into this with LLVM’s unwinder.
| This combination was always broken.
This prompted Dave to question our use of CFI directives more generally,
and I ended up going down a rabbit hole trying to figure out how this
very poorly documented stuff gets used.
Move the CFI directives so that the "mysterious NOP" is included in
the .cfi_{start,end}proc block and add a bunch of comments so that I
can save myself another headache in future.
Cc: Tamas Zsoldos <tamas.zsoldos@arm.com>
Reported-by: Dave Martin <dave.martin@arm.com>
Reported-by: Daniel Kiss <daniel.kiss@arm.com>
Signed-off-by: Will Deacon <will@kernel.org>
---
arch/arm64/kernel/vdso/sigreturn.S | 44 +++++++++++++++++++++++-----
arch/arm64/kernel/vdso32/sigreturn.S | 3 ++
2 files changed, 40 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/kernel/vdso/sigreturn.S b/arch/arm64/kernel/vdso/sigreturn.S
index 0c921130002a..620a3ef837b7 100644
--- a/arch/arm64/kernel/vdso/sigreturn.S
+++ b/arch/arm64/kernel/vdso/sigreturn.S
@@ -1,7 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Sigreturn trampoline for returning from a signal when the SA_RESTORER
- * flag is not set.
+ * flag is not set. It serves primarily as a hall of shame for crappy
+ * unwinders and features an exciting but mysterious NOP instruction.
+ *
+ * It's also fragile as hell, so please think twice before changing anything
+ * in here.
*
* Copyright (C) 2012 ARM Limited
*
@@ -14,7 +18,38 @@
.text
- nop
+/* Ensure that the mysterious NOP can be associated with a function. */
+ .cfi_startproc
+
+/*
+ * .cfi_signal_frame causes the corresponding Frame Description Entry in the
+ * .eh_frame section to be annotated as a signal frame. This allows DWARF
+ * unwinders (e.g. libstdc++) to implement _Unwind_GetIPInfo(), which permits
+ * unwinding out of the signal trampoline without the need for the mysterious
+ * NOP.
+ */
+ .cfi_signal_frame
+
+/*
+ * Tell the unwinder where to locate the frame record linking back to the
+ * interrupted context. We don't provide unwind info for registers other
+ * than the frame pointer and the link register here; in practice, this
+ * is sufficient for unwinding in C/C++ based runtimes and the values in
+ * the sigcontext may have been modified by this point anyway. Debuggers
+ * already have baked-in strategies for attempting to unwind out of signals.
+ */
+ .cfi_def_cfa x29, 0
+ .cfi_offset x29, 0 * 8
+ .cfi_offset x30, 1 * 8
+
+/*
+ * This mysterious NOP is required for some unwinders (e.g. libc++) that
+ * unconditionally subtract one from the result of _Unwind_GetIP() in order to
+ * identify the calling function.
+ * Hack borrowed from arch/powerpc/kernel/vdso64/sigtramp.S.
+ */
+ nop // Mysterious NOP
+
/*
* GDB relies on being able to identify the sigreturn instruction sequence to
* unwind from signal handlers. We cannot, therefore, use SYM_FUNC_START()
@@ -23,11 +58,6 @@
* is perfectly fine.
*/
SYM_CODE_START(__kernel_rt_sigreturn)
- .cfi_startproc
- .cfi_signal_frame
- .cfi_def_cfa x29, 0
- .cfi_offset x29, 0 * 8
- .cfi_offset x30, 1 * 8
mov x8, #__NR_rt_sigreturn
svc #0
.cfi_endproc
diff --git a/arch/arm64/kernel/vdso32/sigreturn.S b/arch/arm64/kernel/vdso32/sigreturn.S
index b36d4e2267a3..b0091064c3d6 100644
--- a/arch/arm64/kernel/vdso32/sigreturn.S
+++ b/arch/arm64/kernel/vdso32/sigreturn.S
@@ -3,6 +3,9 @@
* This file provides both A32 and T32 versions, in accordance with the
* arm sigreturn code.
*
+ * Please read the comments in arch/arm64/kernel/vdso/sigreturn.S to
+ * understand some of the craziness in here.
+ *
* Copyright (C) 2018 ARM Limited
*/
--
2.26.2.761.g0e0b3e54be-goog
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* [PATCH v3 0/2] arm64 sigreturn unwinding fixes
From: Will Deacon @ 2020-05-20 17:55 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Will Deacon, Tamas Zsoldos, Mark Brown, kernel-team, Dave Martin,
Daniel Kiss
Hi folks,
Here is v3 of my attempt at fixing the vdso sigreturn code for unwinders.
Previous versions are available here:
v1: https://lore.kernel.org/r/20200519121818.14511-1-will@kernel.org
v2: https://lore.kernel.org/r/20200519162821.16857-1-will@kernel.org
Changes since v2 include:
* Fix the .cfi directives to identify the link register correctly
* Even more comments
Daniel, please can you give this a spin with the LLVM unwinder? It should work
this time.
Cheers,
Will
Cc: Dave Martin <dave.martin@arm.com>
Cc: Tamas Zsoldos <tamas.zsoldos@arm.com>
Cc: Daniel Kiss <daniel.kiss@arm.com>
Cc: Mark Brown <broonie@kernel.org>
Cc: <kernel-team@android.com>
--->8
Will Deacon (2):
arm64: vdso: Don't prefix sigreturn trampoline with a BTI C
instruction
arm64: vdso: Fix CFI directives in sigreturn trampoline
arch/arm64/include/asm/linkage.h | 6 ++--
arch/arm64/kernel/vdso/sigreturn.S | 51 ++++++++++++++++++++++++----
arch/arm64/kernel/vdso32/sigreturn.S | 19 ++++++-----
3 files changed, 58 insertions(+), 18 deletions(-)
--
2.26.2.761.g0e0b3e54be-goog
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* [PATCH v3 1/2] arm64: vdso: Don't prefix sigreturn trampoline with a BTI C instruction
From: Will Deacon @ 2020-05-20 17:55 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Will Deacon, Tamas Zsoldos, Mark Brown, kernel-team, Dave Martin,
Daniel Kiss
In-Reply-To: <20200520175539.28464-1-will@kernel.org>
For better or worse, GDB relies on the exact instruction sequence in the
VDSO sigreturn trampoline in order to unwind from signals correctly.
Commit c91db232da48 ("arm64: vdso: Convert to modern assembler annotations")
unfortunately added a BTI C instruction to the start of __kernel_rt_sigreturn,
which breaks this check. Thankfully, it's also not required, since the
trampoline is called from a RET instruction when returning from the signal
handler
Remove the unnecessary BTI C instruction from __kernel_rt_sigreturn,
and do the same for the 32-bit VDSO as well for good measure.
Cc: Daniel Kiss <daniel.kiss@arm.com>
Cc: Tamas Zsoldos <tamas.zsoldos@arm.com>
Reviewed-by: Dave Martin <dave.martin@arm.com>
Reviewed-by: Mark Brown <broonie@kernel.org>
Fixes: c91db232da48 ("arm64: vdso: Convert to modern assembler annotations")
Signed-off-by: Will Deacon <will@kernel.org>
---
arch/arm64/include/asm/linkage.h | 6 +++---
arch/arm64/kernel/vdso/sigreturn.S | 11 +++++++++--
arch/arm64/kernel/vdso32/sigreturn.S | 16 ++++++++--------
3 files changed, 20 insertions(+), 13 deletions(-)
diff --git a/arch/arm64/include/asm/linkage.h b/arch/arm64/include/asm/linkage.h
index b5a7998a6b2a..81fefd2a1d02 100644
--- a/arch/arm64/include/asm/linkage.h
+++ b/arch/arm64/include/asm/linkage.h
@@ -15,9 +15,9 @@
#define BTI_J hint 36 ;
/*
- * When using in-kernel BTI we need to ensure that assembly functions
- * have suitable annotations. Override SYM_FUNC_START to insert a BTI
- * landing pad at the start of everything.
+ * When using in-kernel BTI we need to ensure that PCS-conformant assembly
+ * functions have suitable annotations. Override SYM_FUNC_START to insert
+ * a BTI landing pad at the start of everything.
*/
#define SYM_FUNC_START(name) \
SYM_START(name, SYM_L_GLOBAL, SYM_A_ALIGN) \
diff --git a/arch/arm64/kernel/vdso/sigreturn.S b/arch/arm64/kernel/vdso/sigreturn.S
index 3fb13b81f780..0c921130002a 100644
--- a/arch/arm64/kernel/vdso/sigreturn.S
+++ b/arch/arm64/kernel/vdso/sigreturn.S
@@ -15,7 +15,14 @@
.text
nop
-SYM_FUNC_START(__kernel_rt_sigreturn)
+/*
+ * GDB relies on being able to identify the sigreturn instruction sequence to
+ * unwind from signal handlers. We cannot, therefore, use SYM_FUNC_START()
+ * here, as it will emit a BTI C instruction and break the unwinder. Thankfully,
+ * this function is only ever called from a RET and so omitting the landing pad
+ * is perfectly fine.
+ */
+SYM_CODE_START(__kernel_rt_sigreturn)
.cfi_startproc
.cfi_signal_frame
.cfi_def_cfa x29, 0
@@ -24,6 +31,6 @@ SYM_FUNC_START(__kernel_rt_sigreturn)
mov x8, #__NR_rt_sigreturn
svc #0
.cfi_endproc
-SYM_FUNC_END(__kernel_rt_sigreturn)
+SYM_CODE_END(__kernel_rt_sigreturn)
emit_aarch64_feature_1_and
diff --git a/arch/arm64/kernel/vdso32/sigreturn.S b/arch/arm64/kernel/vdso32/sigreturn.S
index 620524969696..b36d4e2267a3 100644
--- a/arch/arm64/kernel/vdso32/sigreturn.S
+++ b/arch/arm64/kernel/vdso32/sigreturn.S
@@ -17,39 +17,39 @@
.save {r0-r15}
.pad #COMPAT_SIGFRAME_REGS_OFFSET
nop
-SYM_FUNC_START(__kernel_sigreturn_arm)
+SYM_CODE_START(__kernel_sigreturn_arm)
mov r7, #__NR_compat_sigreturn
svc #0
.fnend
-SYM_FUNC_END(__kernel_sigreturn_arm)
+SYM_CODE_END(__kernel_sigreturn_arm)
.fnstart
.save {r0-r15}
.pad #COMPAT_RT_SIGFRAME_REGS_OFFSET
nop
-SYM_FUNC_START(__kernel_rt_sigreturn_arm)
+SYM_CODE_START(__kernel_rt_sigreturn_arm)
mov r7, #__NR_compat_rt_sigreturn
svc #0
.fnend
-SYM_FUNC_END(__kernel_rt_sigreturn_arm)
+SYM_CODE_END(__kernel_rt_sigreturn_arm)
.thumb
.fnstart
.save {r0-r15}
.pad #COMPAT_SIGFRAME_REGS_OFFSET
nop
-SYM_FUNC_START(__kernel_sigreturn_thumb)
+SYM_CODE_START(__kernel_sigreturn_thumb)
mov r7, #__NR_compat_sigreturn
svc #0
.fnend
-SYM_FUNC_END(__kernel_sigreturn_thumb)
+SYM_CODE_END(__kernel_sigreturn_thumb)
.fnstart
.save {r0-r15}
.pad #COMPAT_RT_SIGFRAME_REGS_OFFSET
nop
-SYM_FUNC_START(__kernel_rt_sigreturn_thumb)
+SYM_CODE_START(__kernel_rt_sigreturn_thumb)
mov r7, #__NR_compat_rt_sigreturn
svc #0
.fnend
-SYM_FUNC_END(__kernel_rt_sigreturn_thumb)
+SYM_CODE_END(__kernel_rt_sigreturn_thumb)
--
2.26.2.761.g0e0b3e54be-goog
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^ permalink raw reply related
* Re: [PATCH v5] ACPI/IORT: Fix PMCG node single ID mapping handling
From: Will Deacon @ 2020-05-20 17:54 UTC (permalink / raw)
To: Tuan Phan
Cc: Lorenzo Pieralisi, catalin.marinas, Sudeep Holla,
Rafael J. Wysocki, Robin Murphy, Shameer Kolothum, linux-kernel,
linux-acpi, Hanjun Guo, patches, Will Deacon, linux-arm-kernel,
Len Brown
In-Reply-To: <1589994787-28637-1-git-send-email-tuanphan@os.amperecomputing.com>
On Wed, 20 May 2020 10:13:07 -0700, Tuan Phan wrote:
> An IORT PMCG node can have no ID mapping if its overflow interrupt is
> wire based therefore the code that parses the PMCG node can not assume
> the node will always have a single mapping present at index 0.
>
> Fix iort_get_id_mapping_index() by checking for an overflow interrupt
> and mapping count.
>
> [...]
Applied to arm64 (for-next/acpi), thanks!
[1/1] ACPI/IORT: Fix PMCG node single ID mapping handling
https://git.kernel.org/arm64/c/50c8ab8d9fbf
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev
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^ permalink raw reply
* Re: [PATCH V3] arm64/cpufeature: Validate hypervisor capabilities during CPU hotplug
From: Will Deacon @ 2020-05-20 17:54 UTC (permalink / raw)
To: Anshuman Khandual, linux-arm-kernel
Cc: catalin.marinas, Will Deacon, linux-kernel, Marc Zyngier, kvmarm
In-Reply-To: <1589248647-22925-1-git-send-email-anshuman.khandual@arm.com>
On Tue, 12 May 2020 07:27:27 +0530, Anshuman Khandual wrote:
> This validates hypervisor capabilities like VMID width, IPA range for any
> hot plug CPU against system finalized values. KVM's view of the IPA space
> is used while allowing a given CPU to come up. While here, it factors out
> get_vmid_bits() for general use.
>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Marc Zyngier <maz@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: James Morse <james.morse@arm.com>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: kvmarm@lists.cs.columbia.edu
> Cc: linux-kernel@vger.kernel.org
Applied to arm64 (for-next/cpufeature), thanks!
[1/1] arm64/cpufeature: Validate hypervisor capabilities during CPU hotplug
https://git.kernel.org/arm64/c/c73433fc630c
But please note that I made some changes to verify_hyp_capabilities() so
that it's (a) static and (b) uses IS_ENABLED to avoid the dummy function
definition. I also extended the IS_ENABLED_check so that it doesn't
conflict with the KVM kconfig changes from Fuad. Please shout if you think
I'm still missing something.
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev
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^ permalink raw reply
* Re: [PATCH V2] arm64/cpufeature: Drop open encodings while extracting parange
From: Will Deacon @ 2020-05-20 17:54 UTC (permalink / raw)
To: Anshuman Khandual, linux-arm-kernel
Cc: catalin.marinas, Will Deacon, kvmarm, Marc Zyngier, linux-kernel
In-Reply-To: <1589360614-1164-1-git-send-email-anshuman.khandual@arm.com>
On Wed, 13 May 2020 14:33:34 +0530, Anshuman Khandual wrote:
> Currently there are multiple instances of parange feature width mask open
> encodings while fetching it's value. Even the width mask value (0x7) itself
> is not accurate. It should be (0xf) per ID_AA64MMFR0_EL1.PARange[3:0] as in
> ARM ARM (0487F.a). Replace them with cpuid_feature_extract_unsigned_field()
> which can extract given standard feature (4 bits width i.e 0xf mask) field.
>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Marc Zyngier <maz@kernel.org>
> Cc: James Morse <james.morse@arm.com>
> Cc: kvmarm@lists.cs.columbia.edu
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
Applied to arm64 (for-next/cpufeature), thanks!
[1/1] arm64/cpufeature: Drop open encodings while extracting parange
https://git.kernel.org/arm64/c/f73531f0257f
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev
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^ permalink raw reply
* Re: [PATCH v11] arm64: dts: qcom: sc7180: Add WCN3990 WLAN module device node
From: Sibi Sankar @ 2020-05-20 17:50 UTC (permalink / raw)
To: Rakesh Pillai
Cc: linux-kernel-owner, devicetree, linux-kernel, linux-arm-kernel,
linux-arm-msm
In-Reply-To: <1589946996-31264-1-git-send-email-pillair@codeaurora.org>
On 2020-05-20 09:26, Rakesh Pillai wrote:
> Add device node for the ath10k SNOC platform driver probe
> and add resources required for WCN3990 on sc7180 soc.
>
> Signed-off-by: Rakesh Pillai <pillair@codeaurora.org>
> ---
> Changes from v10:
> - Corrected the position of wifi node, as per address
> - Removed the wlan_fw_mem from reserved memory, since
> its already added as reserved memory in board DT file.
Reviewed-by: Sibi Sankar <sibis@codeaurora.org>
> ---
> arch/arm64/boot/dts/qcom/sc7180-idp.dts | 7 +++++++
> arch/arm64/boot/dts/qcom/sc7180.dtsi | 22 ++++++++++++++++++++++
> 2 files changed, 29 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts
> b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
> index 4e9149d..38b102e 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts
> +++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts
> @@ -389,6 +389,13 @@
> };
> };
>
> +&wifi {
> + status = "okay";
> + wifi-firmware {
> + iommus = <&apps_smmu 0xc2 0x1>;
> + };
> +};
> +
> /* PINCTRL - additions to nodes defined in sc7180.dtsi */
>
> &qspi_clk {
> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> index 6b12c60..da79f8f 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> @@ -2811,6 +2811,28 @@
>
> #freq-domain-cells = <1>;
> };
> +
> + wifi: wifi@18800000 {
> + compatible = "qcom,wcn3990-wifi";
> + reg = <0 0x18800000 0 0x800000>;
> + reg-names = "membase";
> + iommus = <&apps_smmu 0xc0 0x1>;
> + interrupts =
> + <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >,
> + <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >,
> + <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >,
> + <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >,
> + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >,
> + <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >,
> + <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >,
> + <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >,
> + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >,
> + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >,
> + <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>,
> + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>;
> + memory-region = <&wlan_mem>;
> + status = "disabled";
> + };
> };
>
> thermal-zones {
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project.
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^ permalink raw reply
* Re: [PATCH v5] ACPI/IORT: Fix PMCG node single ID mapping handling
From: Will Deacon @ 2020-05-20 17:43 UTC (permalink / raw)
To: Lorenzo Pieralisi
Cc: Hanjun Guo, Tuan Phan, Rafael J. Wysocki, linux-kernel,
Shameer Kolothum, linux-acpi, Sudeep Holla, patches, Robin Murphy,
linux-arm-kernel, Len Brown
In-Reply-To: <20200520172736.GA10693@e121166-lin.cambridge.arm.com>
On Wed, May 20, 2020 at 06:27:36PM +0100, Lorenzo Pieralisi wrote:
> On Wed, May 20, 2020 at 10:13:07AM -0700, Tuan Phan wrote:
> > An IORT PMCG node can have no ID mapping if its overflow interrupt is
> > wire based therefore the code that parses the PMCG node can not assume
> > the node will always have a single mapping present at index 0.
> >
> > Fix iort_get_id_mapping_index() by checking for an overflow interrupt
> > and mapping count.
> >
> > Fixes: 24e516049360 ("ACPI/IORT: Add support for PMCG")
> >
> > Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> > Reviewed-by: Hanjun Guo <guoahanjun@huawei.com>
> > Signed-off-by: Tuan Phan <tuanphan@os.amperecomputing.com>
> > ---
> > v1 -> v2:
> > - Use pmcg node to detect wired base overflow interrupt.
> >
> > v2 -> v3:
> > - Address Hanjun and Robin's comments.
> >
> > v3 -> v4:
> > - Update the title and description as mentioned by Lorenzo.
> >
> > v4 -> v5:
> > - Remove period in the title and commit references.
> >
> > drivers/acpi/arm64/iort.c | 5 +++++
>
> Hi Will,
>
> is there a chance we can get this patch into v5.8 ? I understand
> we are very late in the cycle but I wanted to ask (it applies cleanly
> to for-next/acpi).
Sorry, Lorenzo -- I didn't notice that this had been Acked already. I was
waiting for somebody to chime in! I'll queue it ASAP for 5.8.
Will
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^ permalink raw reply
* Re: arm64: Register modification during syscall entry/exit stop
From: Will Deacon @ 2020-05-20 17:41 UTC (permalink / raw)
To: Keno Fischer
Cc: Catalin Marinas, Kyle Huey, Oleg Nesterov, linux-arm-kernel,
Linux Kernel Mailing List
In-Reply-To: <CABV8kRzYzBrdzC1_opmmdpW63N2htfOsAUZ+RjiSDsy=SJW6Yg@mail.gmail.com>
Hi Keno,
On Tue, May 19, 2020 at 04:37:34AM -0400, Keno Fischer wrote:
> > Yes, we inherited this from ARM and I think strace relies on it. In
> > hindsight, it is a little odd, although x7 is a parameter register in the
> > PCS and so it won't be live on entry to a system call.
>
> I'm not familiar with the PCS acronym, but I assume you mean the
> calling convention? You have more faith in userspace than I do ;). For
> example, cursory googling brought up this arm64 syscall definition in musl:
>
> https://github.com/bminor/musl/blob/593caa456309714402ca4cb77c3770f4c24da9da/arch/aarch64/syscall_arch.h
Hmm, does that actually result in the SVC instruction getting inlined? I
think that's quite dangerous, since we document that we can trash the SVE
register state on a system call, for example. I'm also surprised that
the register variables are honoured by compilers if that inlining can occur.
> The constraints on those asm blocks allow the compiler to assume that
> x7 is preserved across the syscall. If a ptracer accidentally modified it
> (which is easy to do in the situations that I mentioned), it could
> absolutely cause incorrect execution of the userspace program.
>
> > Although the examples you've
> > listed above are interesting, I don't see why x7 is important in any of
> > them (and we only support up to 6 system call arguments).
>
> It's not so much that x7 is important, it's that lying to the ptracer is
> problematic, because it might remember that lie and act on it later.
> I did run into exactly this problem, where my ptracer accidentally
> changed the value of x7 and caused incorrect execution in the tracee
> (now that incorrect execution happened to be an assertion, because
> my application is paranoid about these kinds of issues, but it was
> incorrect nevertheless)
>
> If it would be helpful, I can code up the syscall entry -> signal trap example
> ptracer to have a concrete example.
I guess I'm more interested in situations where the compiler thinks x7 is
live, yet we clobber it.
Will
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^ permalink raw reply
* Re: [PATCH] arm64/cpufeature: Move BUG_ON() inside get_arm64_ftr_reg()
From: Will Deacon @ 2020-05-20 17:39 UTC (permalink / raw)
To: Catalin Marinas
Cc: mark.rutland, Suzuki K Poulose, Anshuman Khandual, linux-kernel,
Mark Brown, linux-arm-kernel
In-Reply-To: <20200520154711.GD18302@gaia>
On Wed, May 20, 2020 at 04:47:11PM +0100, Catalin Marinas wrote:
> On Wed, May 20, 2020 at 01:20:13PM +0100, Will Deacon wrote:
> > On Wed, May 20, 2020 at 06:52:54AM +0530, Anshuman Khandual wrote:
> > > There is no way to proceed when requested register could not be searched in
> > > arm64_ftr_reg[]. Requesting for a non present register would be an error as
> > > well. Hence lets just BUG_ON() when the search fails in get_arm64_ftr_reg()
> > > rather than checking for return value and doing the same in some individual
> > > callers.
> > >
> > > But there are some callers that dont BUG_ON() upon search failure. It adds
> > > an argument 'failsafe' that provides required switch between callers based
> > > on whether they could proceed or not.
> > >
> > > Cc: Catalin Marinas <catalin.marinas@arm.com>
> > > Cc: Will Deacon <will@kernel.org>
> > > Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> > > Cc: Mark Brown <broonie@kernel.org>
> > > Cc: linux-arm-kernel@lists.infradead.org
> > > Cc: linux-kernel@vger.kernel.org
> > >
> > > Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> > > ---
> > > Applies on next-20200518 that has recent cpufeature changes from Will.
> > >
> > > arch/arm64/kernel/cpufeature.c | 26 +++++++++++++-------------
> > > 1 file changed, 13 insertions(+), 13 deletions(-)
> > >
> > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> > > index bc5048f152c1..62767cc540c3 100644
> > > --- a/arch/arm64/kernel/cpufeature.c
> > > +++ b/arch/arm64/kernel/cpufeature.c
> > > @@ -557,7 +557,7 @@ static int search_cmp_ftr_reg(const void *id, const void *regp)
> > > * - NULL on failure. It is upto the caller to decide
> > > * the impact of a failure.
> > > */
> > > -static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
> > > +static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id, bool failsafe)
> >
> > Generally, I'm not a big fan of boolean arguments because they are really
> > opaque at the callsite. It also seems bogus to me that we don't trust the
> > caller to pass a valid sys_id, but we trust it to get "failsafe" right,
> > which seems to mean "I promise to check the result isn't NULL before
> > dereferencing it."
> >
> > So I don't see how this patch improves anything. I'd actually be more
> > inclined to stick a WARN() in get_arm64_ftr_reg() when it returns NULL and
> > have the callers handle NULL by returning early, getting rid of all the
> > BUG_ONs in here. Sure, the system might end up in a funny state, but we
> > WARN()d about it and tried to keep going (and Linus has some strong opinions
> > on this too).
>
> Such WARN can be triggered by the user via emulate_sys_reg(), so we
> can't really have it in get_arm64_ftr_reg() without a 'failsafe' option.
Ah yes, that would be bad. In which case, I don't think the existing code
should change.
Will
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^ permalink raw reply
* Re: Clarification on necessary barriers before generating IPI
From: Linu Cherian @ 2020-05-20 17:37 UTC (permalink / raw)
To: Will Deacon; +Cc: maz, Linu Cherian, linux-arm-kernel
In-Reply-To: <20200520090317.GD24293@willie-the-truck>
Hi Will,
On Wed, May 20, 2020 at 2:33 PM Will Deacon <will@kernel.org> wrote:
>
> On Wed, May 20, 2020 at 02:23:25PM +0530, Linu Cherian wrote:
> > On Wed, May 20, 2020 at 1:59 PM Will Deacon <will@kernel.org> wrote:
> > >
> > > On Wed, May 20, 2020 at 01:38:24PM +0530, Linu Cherian wrote:
> > > > How is it ensured that system register write using msr instruction(gic_send_sgi)
> > > > doesnt get reordered before the stores to IPI call processing
> > > > list(call_single_queue in kernel/smp.c), so that IPI is guaranteed to
> > > > be generated after the stores get completed.
> > >
> > > I think the flow is:
> > >
> > > <store to memory>
> > > DSB ST
> >
> > Dont we need an extra ISB here to ensure that the subsequent MSR SGI1R doesnt
> > get executed before <store to memory> and DSB ST ?
> >
> > This is on the assumption that DSB ST doesnt enforce the ordering of MSR SGI1R.
>
> I don't think that's a valid assumption. The architecture says:
>
> | A DSB instruction executed by a PE, PEe, completes when [...] all explicit
> | memory accesses of the required access types appearing in program order
> | before the DSB are complete for the set of observers in the required
> | shareability domain.
>
> and:
>
> | In addition, no instruction that appears in program order after the DSB
> | instruction can alter any state of the system or perform any part of its
> | functionality until the DSB completes other than:
> |
> | * Being fetched from memory and decoded.
> | * Reading the general-purpose, SIMD and floating-point, Special-purpose, or
> | System registers that are directly or indirectly read without causing
> | side-effects.
>
Thats clear. Thanks.
> Are you seeing a problem in practice?
>
Just came across this code, while trying to debug something related.
Will let you know if i have further followup.
> Will
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^ permalink raw reply
* Re: [PATCH v4 06/11] net: ethernet: mtk-eth-mac: new driver
From: Bartosz Golaszewski @ 2020-05-20 17:34 UTC (permalink / raw)
To: Arnd Bergmann, Stephane Le Provost, Pedro Tsai, Andrew Perepech
Cc: Edwin Peer, DTML, Bartosz Golaszewski, Networking, Sean Wang,
linux-kernel@vger.kernel.org, David S . Miller, Fabien Parent,
Rob Herring, moderated list:ARM/Mediatek SoC..., John Crispin,
Matthias Brugger, Jakub Kicinski, Mark Lee, Linux ARM,
Heiner Kallweit
In-Reply-To: <CAK8P3a3jhrQ3p1JsqMNMOOnfo9t=rAPWaOAwAdDuFMh7wUtZQw@mail.gmail.com>
śr., 20 maj 2020 o 16:37 Arnd Bergmann <arnd@arndb.de> napisał(a):
>
> On Wed, May 20, 2020 at 1:25 PM Bartosz Golaszewski <brgl@bgdev.pl> wrote:
> >
> > From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> >
> > This adds the driver for the MediaTek Ethernet MAC used on the MT8* SoC
> > family. For now we only support full-duplex.
> >
> > Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
>
> Looks much better, thanks for addressing my feedback. A few more things
> about this version:
>
> > ---
> > drivers/net/ethernet/mediatek/Kconfig | 6 +
> > drivers/net/ethernet/mediatek/Makefile | 1 +
> > drivers/net/ethernet/mediatek/mtk_eth_mac.c | 1668 +++++++++++++++++++
> > 3 files changed, 1675 insertions(+)
> > create mode 100644 drivers/net/ethernet/mediatek/mtk_eth_mac.c
> >
> > diff --git a/drivers/net/ethernet/mediatek/Kconfig b/drivers/net/ethernet/mediatek/Kconfig
> > index 5079b8090f16..5c3793076765 100644
> > --- a/drivers/net/ethernet/mediatek/Kconfig
> > +++ b/drivers/net/ethernet/mediatek/Kconfig
> > @@ -14,4 +14,10 @@ config NET_MEDIATEK_SOC
> > This driver supports the gigabit ethernet MACs in the
> > MediaTek SoC family.
> >
> > +config NET_MEDIATEK_MAC
> > + tristate "MediaTek Ethernet MAC support"
> > + select PHYLIB
> > + help
> > + This driver supports the ethernet IP on MediaTek MT85** SoCs.
>
> I just noticed how the naming of NET_MEDIATEK_MAC and NET_MEDIATEK_SOC
> for two different drivers doing the same thing is really confusing.
>
> Maybe someone can come up with a better name, such as one
> based on the soc it first showed up in.
>
This has been discussed under one of the previous submissions.
MediaTek wants to use this IP on future designs as well and it's
already used on multiple SoCs so they want the name to be generic. I
also argued that this is a driver strongly tied to a specific
platform(s) so if someone wants to compile it - they probably know
what they're doing.
That being said: I verified with MediaTek and the name of the IP I can
use is "star" so they proposed "mtk-star-eth". I would personally
maybe go with "mtk-star-mac". How about those two?
> > + struct mtk_mac_ring_desc *desc = &ring->descs[ring->head];
> > + unsigned int status;
> > +
> > + status = desc->status;
> > +
> > + ring->skbs[ring->head] = desc_data->skb;
> > + ring->dma_addrs[ring->head] = desc_data->dma_addr;
> > + desc->data_ptr = desc_data->dma_addr;
> > +
> > + status |= desc_data->len;
> > + if (flags)
> > + status |= flags;
> > + desc->status = status;
> > +
> > + /* Flush previous modifications before ownership change. */
> > + dma_wmb();
> > + desc->status &= ~MTK_MAC_DESC_BIT_COWN;
>
> You still do the read-modify-write on the word here, which is
> expensive on uncached memory. You have read the value already,
> so better use an assignment rather than &=, or (better)
> READ_ONCE() and WRITE_ONCE() to prevent the compiler
> from adding further accesses.
>
Will do.
>
> > +static void mtk_mac_lock(struct mtk_mac_priv *priv)
> > +{
> > + spin_lock_bh(&priv->lock);
> > +}
> > +
> > +static void mtk_mac_unlock(struct mtk_mac_priv *priv)
> > +{
> > + spin_unlock_bh(&priv->lock);
> > +}
>
> I think open-coding the locks would make this more readable,
> and let you use spin_lock() instead of spin_lock_bh() in
> those functions that are already in softirq context.
>
Will do.
> > +static void mtk_mac_intr_enable_tx(struct mtk_mac_priv *priv)
> > +{
> > + regmap_update_bits(priv->regs, MTK_MAC_REG_INT_MASK,
> > + MTK_MAC_BIT_INT_STS_TNTC, 0);
> > +}
> > +static void mtk_mac_intr_enable_rx(struct mtk_mac_priv *priv)
> > +{
> > + regmap_update_bits(priv->regs, MTK_MAC_REG_INT_MASK,
> > + MTK_MAC_BIT_INT_STS_FNRC, 0);
> > +}
>
> These imply reading the irq mask register and then writing it again,
> which is much more expensive than just writing it. It's also not
> atomic since the regmap does not use a lock.
>
> I don't think you actually need to enable/disable rx and tx separately,
> but if you do, then writing to the Ack register as I suggested instead
> of updating the mask would let you do this.
>
> > +/* All processing for TX and RX happens in the napi poll callback. */
> > +static irqreturn_t mtk_mac_handle_irq(int irq, void *data)
> > +{
> > + struct mtk_mac_priv *priv;
> > + struct net_device *ndev;
> > + bool need_napi = false;
> > + unsigned int status;
> > +
> > + ndev = data;
> > + priv = netdev_priv(ndev);
> > +
> > + if (netif_running(ndev)) {
> > + status = mtk_mac_intr_read(priv);
> > +
> > + if (status & MTK_MAC_BIT_INT_STS_TNTC) {
> > + mtk_mac_intr_disable_tx(priv);
> > + need_napi = true;
> > + }
> > +
> > + if (status & MTK_MAC_BIT_INT_STS_FNRC) {
> > + mtk_mac_intr_disable_rx(priv);
> > + need_napi = true;
> > + }
>
> I think you mixed up the rx and tx bits here: when you get
> an rx interrupt, that one is already blocked until it gets
> acked and you just need to disable tx until the end of the
> poll function.
>
> However, I suspect that the overhead of turning them off
> is higher than what you can save, and simply ignoring
> the mask with
>
> if (status & (MTK_MAC_BIT_INT_STS_FNRC | MTK_MAC_BIT_INT_STS_TNTC))
> napi_schedule(&priv->napi);
>
> would be simpler and faster.
>
> + /* One of the counters reached 0x8000000 - update stats and
> > + * reset all counters.
> > + */
> > + if (unlikely(status & MTK_MAC_REG_INT_STS_MIB_CNT_TH)) {
> > + mtk_mac_intr_disable_stats(priv);
> > + schedule_work(&priv->stats_work);
> > + }
> > + befor
> > + mtk_mac_intr_ack_all(priv);
>
> The ack here needs to be dropped, otherwise you can get further
> interrupts before the bottom half has had a chance to run.
>
My thinking was this: if I mask the relevant interrupt (TX/RX
complete) and ack it right away, the status bit will be asserted on
the next packet received/sent but the process won't get interrupted
and when I unmask it, it will fire right away and I won't have to
recheck the status register. I noticed that if I ack it at the end of
napi poll callback, I end up missing certain TX complete interrupts
and end up seeing a lot of retransmissions even if I reread the status
register. I'm not yet sure where this race happens.
> You might be lucky because you had already disabled the individual
> bits earlier, but I don't think that was intentional here.
>
> > +static int mtk_mac_netdev_start_xmit(struct sk_buff *skb,
> > + struct net_device *ndev)
> > +{
> > + struct mtk_mac_priv *priv = netdev_priv(ndev);
> > + struct mtk_mac_ring *ring = &priv->tx_ring;
> > + struct device *dev = mtk_mac_get_dev(priv);
> > + struct mtk_mac_ring_desc_data desc_data;
> > +
> > + desc_data.dma_addr = mtk_mac_dma_map_tx(priv, skb);
> > + if (dma_mapping_error(dev, desc_data.dma_addr))
> > + goto err_drop_packet;
> > +
> > + desc_data.skb = skb;
> > + desc_data.len = skb->len;
> > +
> > + mtk_mac_lock(priv);
> > +
> > + mtk_mac_ring_push_head_tx(ring, &desc_data);
> > +
> > + netdev_sent_queue(ndev, skb->len);
> > +
> > + if (mtk_mac_ring_full(ring))
> > + netif_stop_queue(ndev);
> > +
> > + mtk_mac_unlock(priv);
> > +
> > + mtk_mac_dma_resume_tx(priv);
>
> mtk_mac_dma_resume_tx() is an expensive read-modify-write
> on an mmio register, so it would make sense to defer it based
> on netdev_xmit_more(). (I had missed this in the previous
> review)
>
Thanks for bringing it to my attention, I'll see about using it.
> > +static void mtk_mac_tx_complete_all(struct mtk_mac_priv *priv)
> > +{
> > + struct mtk_mac_ring *ring = &priv->tx_ring;
> > + struct net_device *ndev = priv->ndev;
> > + int ret, pkts_compl, bytes_compl;
> > + bool wake = false;
> > +
> > + mtk_mac_lock(priv);
> > +
> > + for (pkts_compl = 0, bytes_compl = 0;;
> > + pkts_compl++, bytes_compl += ret, wake = true) {
> > + if (!mtk_mac_ring_descs_available(ring))
> > + break;
> > +
> > + ret = mtk_mac_tx_complete_one(priv);
> > + if (ret < 0)
> > + break;
> > + }
> > +
> > + netdev_completed_queue(ndev, pkts_compl, bytes_compl);
> > +
> > + if (wake && netif_queue_stopped(ndev))
> > + netif_wake_queue(ndev);
> > +
> > + mtk_mac_intr_enable_tx(priv);
>
> No need to ack the interrupt here if napi is still active. Just
> ack both rx and tx when calling napi_complete().
>
> Some drivers actually use the napi budget for both rx and tx:
> if you have more than 'budget' completed tx frames, return
> early from this function and skip the napi_complete even
> when less than 'budget' rx frames have arrived.
>
IIRC Jakub said that the most seen approach is to free all TX descs
and receive up to budget packets, so this is what I did. I think it
makes the most sense.
Best regards,
Bartosz
> This way you get more fairness between devices and
> can run for longer with irqs disabled as long as either rx
> or tx is busy.
>
> Arnd
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^ permalink raw reply
* Re: [PATCH v5] ACPI/IORT: Fix PMCG node single ID mapping handling
From: Lorenzo Pieralisi @ 2020-05-20 17:27 UTC (permalink / raw)
To: Tuan Phan, will
Cc: Hanjun Guo, Rafael J. Wysocki, linux-kernel, Shameer Kolothum,
linux-acpi, Sudeep Holla, patches, Robin Murphy, linux-arm-kernel,
Len Brown
In-Reply-To: <1589994787-28637-1-git-send-email-tuanphan@os.amperecomputing.com>
On Wed, May 20, 2020 at 10:13:07AM -0700, Tuan Phan wrote:
> An IORT PMCG node can have no ID mapping if its overflow interrupt is
> wire based therefore the code that parses the PMCG node can not assume
> the node will always have a single mapping present at index 0.
>
> Fix iort_get_id_mapping_index() by checking for an overflow interrupt
> and mapping count.
>
> Fixes: 24e516049360 ("ACPI/IORT: Add support for PMCG")
>
> Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Reviewed-by: Hanjun Guo <guoahanjun@huawei.com>
> Signed-off-by: Tuan Phan <tuanphan@os.amperecomputing.com>
> ---
> v1 -> v2:
> - Use pmcg node to detect wired base overflow interrupt.
>
> v2 -> v3:
> - Address Hanjun and Robin's comments.
>
> v3 -> v4:
> - Update the title and description as mentioned by Lorenzo.
>
> v4 -> v5:
> - Remove period in the title and commit references.
>
> drivers/acpi/arm64/iort.c | 5 +++++
Hi Will,
is there a chance we can get this patch into v5.8 ? I understand
we are very late in the cycle but I wanted to ask (it applies cleanly
to for-next/acpi).
Thanks !
Lorenzo
> 1 file changed, 5 insertions(+)
>
> diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c
> index ed3d2d1..12bb70e 100644
> --- a/drivers/acpi/arm64/iort.c
> +++ b/drivers/acpi/arm64/iort.c
> @@ -414,6 +414,7 @@ static struct acpi_iort_node *iort_node_get_id(struct acpi_iort_node *node,
> static int iort_get_id_mapping_index(struct acpi_iort_node *node)
> {
> struct acpi_iort_smmu_v3 *smmu;
> + struct acpi_iort_pmcg *pmcg;
>
> switch (node->type) {
> case ACPI_IORT_NODE_SMMU_V3:
> @@ -441,6 +442,10 @@ static int iort_get_id_mapping_index(struct acpi_iort_node *node)
>
> return smmu->id_mapping_index;
> case ACPI_IORT_NODE_PMCG:
> + pmcg = (struct acpi_iort_pmcg *)node->node_data;
> + if (pmcg->overflow_gsiv || node->mapping_count == 0)
> + return -EINVAL;
> +
> return 0;
> default:
> return -EINVAL;
> --
> 2.7.4
>
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^ permalink raw reply
* Re: [PATCH] dt-bindings: input: touchscreen: edt-ft5x06: change reg property
From: Dmitry Torokhov @ 2020-05-20 17:13 UTC (permalink / raw)
To: Johan Jonker
Cc: devicetree, heiko, linux-kernel, linux-rockchip, robh+dt,
linux-input, linux-arm-kernel
In-Reply-To: <20200520073327.6016-1-jbx6244@gmail.com>
Hi Johan,
On Wed, May 20, 2020 at 09:33:27AM +0200, Johan Jonker wrote:
> A test with the command below gives this error:
>
> arch/arm/boot/dts/rk3188-bqedison2qc.dt.yaml:
> touchscreen@3e: reg:0:0: 56 was expected
>
> The touchscreen chip on 'rk3188-bqedison2qc' and other BQ models
> was shipped with different addresses then the binding currently allows.
> Change the reg property that any address will pass.
>
> make ARCH=arm dtbs_check
> DT_SCHEMA_FILES=Documentation/devicetree/bindings/input/touchscreen/
> edt-ft5x06.yaml
>
> Signed-off-by: Johan Jonker <jbx6244@gmail.com>
> ---
> Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.yaml | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.yaml b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.yaml
> index 383d64a91..baa8e8f7e 100644
> --- a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.yaml
> +++ b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.yaml
> @@ -42,7 +42,7 @@ properties:
> - focaltech,ft6236
>
> reg:
> - const: 0x38
> + maxItems: 1
Should we have a list of valid addresses instead of allowing any
address? Controllers usually have only a couple of addresses that they
support.
Thanks.
--
Dmitry
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^ permalink raw reply
* [PATCH v5] ACPI/IORT: Fix PMCG node single ID mapping handling
From: Tuan Phan @ 2020-05-20 17:13 UTC (permalink / raw)
Cc: Lorenzo Pieralisi, Robin Murphy, Hanjun Guo, Rafael J. Wysocki,
linux-kernel, Shameer Kolothum, linux-acpi, Sudeep Holla, patches,
Will Deacon, linux-arm-kernel, Len Brown
An IORT PMCG node can have no ID mapping if its overflow interrupt is
wire based therefore the code that parses the PMCG node can not assume
the node will always have a single mapping present at index 0.
Fix iort_get_id_mapping_index() by checking for an overflow interrupt
and mapping count.
Fixes: 24e516049360 ("ACPI/IORT: Add support for PMCG")
Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Hanjun Guo <guoahanjun@huawei.com>
Signed-off-by: Tuan Phan <tuanphan@os.amperecomputing.com>
---
v1 -> v2:
- Use pmcg node to detect wired base overflow interrupt.
v2 -> v3:
- Address Hanjun and Robin's comments.
v3 -> v4:
- Update the title and description as mentioned by Lorenzo.
v4 -> v5:
- Remove period in the title and commit references.
drivers/acpi/arm64/iort.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c
index ed3d2d1..12bb70e 100644
--- a/drivers/acpi/arm64/iort.c
+++ b/drivers/acpi/arm64/iort.c
@@ -414,6 +414,7 @@ static struct acpi_iort_node *iort_node_get_id(struct acpi_iort_node *node,
static int iort_get_id_mapping_index(struct acpi_iort_node *node)
{
struct acpi_iort_smmu_v3 *smmu;
+ struct acpi_iort_pmcg *pmcg;
switch (node->type) {
case ACPI_IORT_NODE_SMMU_V3:
@@ -441,6 +442,10 @@ static int iort_get_id_mapping_index(struct acpi_iort_node *node)
return smmu->id_mapping_index;
case ACPI_IORT_NODE_PMCG:
+ pmcg = (struct acpi_iort_pmcg *)node->node_data;
+ if (pmcg->overflow_gsiv || node->mapping_count == 0)
+ return -EINVAL;
+
return 0;
default:
return -EINVAL;
--
2.7.4
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^ permalink raw reply related
* [PATCH] media: cedrus: Add support for additional output formats
From: Jernej Skrabec @ 2020-05-20 17:14 UTC (permalink / raw)
To: mripard, paul.kocialkowski
Cc: devel, gregkh, linux-kernel, wens, hverkuil-cisco, mchehab,
linux-arm-kernel, linux-media
If VPU supports untiled output, it actually supports several different
YUV 4:2:0 layouts, namely NV12, NV21, YUV420 and YVU420.
Add support for all of them.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/staging/media/sunxi/cedrus/cedrus_hw.c | 18 +++++++++++++++++-
.../staging/media/sunxi/cedrus/cedrus_video.c | 18 ++++++++++++++++++
2 files changed, 35 insertions(+), 1 deletion(-)
diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c
index daf5f244f93b..c119fd8c4b92 100644
--- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c
+++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c
@@ -83,9 +83,25 @@ void cedrus_dst_format_set(struct cedrus_dev *dev,
switch (fmt->pixelformat) {
case V4L2_PIX_FMT_NV12:
+ case V4L2_PIX_FMT_NV21:
+ case V4L2_PIX_FMT_YUV420:
+ case V4L2_PIX_FMT_YVU420:
chroma_size = ALIGN(width, 16) * ALIGN(height, 16) / 2;
- reg = VE_PRIMARY_OUT_FMT_NV12;
+ switch (fmt->pixelformat) {
+ case V4L2_PIX_FMT_NV12:
+ reg = VE_PRIMARY_OUT_FMT_NV12;
+ break;
+ case V4L2_PIX_FMT_NV21:
+ reg = VE_PRIMARY_OUT_FMT_NV21;
+ break;
+ case V4L2_PIX_FMT_YUV420:
+ reg = VE_PRIMARY_OUT_FMT_YU12;
+ break;
+ case V4L2_PIX_FMT_YVU420:
+ reg = VE_PRIMARY_OUT_FMT_YV12;
+ break;
+ }
cedrus_write(dev, VE_PRIMARY_OUT_FMT, reg);
reg = chroma_size / 2;
diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_video.c b/drivers/staging/media/sunxi/cedrus/cedrus_video.c
index 15cf1f10221b..016021d71df2 100644
--- a/drivers/staging/media/sunxi/cedrus/cedrus_video.c
+++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.c
@@ -55,6 +55,21 @@ static struct cedrus_format cedrus_formats[] = {
.directions = CEDRUS_DECODE_DST,
.capabilities = CEDRUS_CAPABILITY_UNTILED,
},
+ {
+ .pixelformat = V4L2_PIX_FMT_NV21,
+ .directions = CEDRUS_DECODE_DST,
+ .capabilities = CEDRUS_CAPABILITY_UNTILED,
+ },
+ {
+ .pixelformat = V4L2_PIX_FMT_YUV420,
+ .directions = CEDRUS_DECODE_DST,
+ .capabilities = CEDRUS_CAPABILITY_UNTILED,
+ },
+ {
+ .pixelformat = V4L2_PIX_FMT_YVU420,
+ .directions = CEDRUS_DECODE_DST,
+ .capabilities = CEDRUS_CAPABILITY_UNTILED,
+ },
};
#define CEDRUS_FORMATS_COUNT ARRAY_SIZE(cedrus_formats)
@@ -130,6 +145,9 @@ void cedrus_prepare_format(struct v4l2_pix_format *pix_fmt)
break;
case V4L2_PIX_FMT_NV12:
+ case V4L2_PIX_FMT_NV21:
+ case V4L2_PIX_FMT_YUV420:
+ case V4L2_PIX_FMT_YVU420:
/* 16-aligned stride. */
bytesperline = ALIGN(width, 16);
--
2.26.2
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^ permalink raw reply related
* Re: clock_gettime64 vdso bug on 32-bit arm, rpi-4
From: Rich Felker @ 2020-05-20 17:09 UTC (permalink / raw)
To: Szabolcs Nagy
Cc: nd, Arnd Bergmann, Stephen Boyd, Will Deacon,
Russell King - ARM Linux, Linux Kernel Mailing List,
Adhemerval Zanella, Thomas Gleixner, Vincenzo Frascino,
Jack Schmidt, Linux ARM
In-Reply-To: <20200520160810.GM1079@brightrain.aerifal.cx>
On Wed, May 20, 2020 at 12:08:10PM -0400, Rich Felker wrote:
> On Wed, May 20, 2020 at 04:41:29PM +0100, Szabolcs Nagy wrote:
> > The 05/19/2020 22:31, Arnd Bergmann wrote:
> > > On Tue, May 19, 2020 at 10:24 PM Adhemerval Zanella
> > > <adhemerval.zanella@linaro.org> wrote:
> > > > On 19/05/2020 16:54, Arnd Bergmann wrote:
> > > > > Jack Schmidt reported a bug for the arm32 clock_gettimeofday64 vdso call last
> > > > > month: https://github.com/richfelker/musl-cross-make/issues/96 and
> > > > > https://github.com/raspberrypi/linux/issues/3579
> > > > >
> > > > > As Will Deacon pointed out, this was never reported on the mailing list,
> > > > > so I'll try to summarize what we know, so this can hopefully be resolved soon.
> > > > >
> > > > > - This happened reproducibly on Linux-5.6 on a 32-bit Raspberry Pi patched
> > > > > kernel running on a 64-bit Raspberry Pi 4b (bcm2711) when calling
> > > > > clock_gettime64(CLOCK_REALTIME)
> > > >
> > > > Does it happen with other clocks as well?
> > >
> > > Unclear.
> > >
> > > > > - The kernel tree is at https://github.com/raspberrypi/linux/, but I could
> > > > > see no relevant changes compared to a mainline kernel.
> > > >
> > > > Is this bug reproducible with mainline kernel or mainline kernel can't be
> > > > booted on bcm2711?
> > >
> > > Mainline linux-5.6 should boot on that machine but might not have
> > > all the other features, so I think users tend to use the raspberry pi
> > > kernel sources for now.
> > >
> > > > > - From the report, I see that the returned time value is larger than the
> > > > > expected time, by 3.4 to 14.5 million seconds in four samples, my
> > > > > guess is that a random number gets added in at some point.
> > > >
> > > > What kind code are you using to reproduce it? It is threaded or issue
> > > > clock_gettime from signal handlers?
> > >
> > > The reproducer is very simple without threads or signals,
> > > see the start of https://github.com/richfelker/musl-cross-make/issues/96
> > >
> > > It does rely on calling into the musl wrapper, not the direct vdso
> > > call.
> > >
> > > > > - From other sources, I found that the Raspberry Pi clocksource runs
> > > > > at 54 MHz, with a mask value of 0xffffffffffffff. From these numbers
> > > > > I would expect that reading a completely random hardware register
> > > > > value would result in an offset up to 1.33 billion seconds, which is
> > > > > around factor 100 more than the error we see, though similar.
> > > > >
> > > > > - The test case calls the musl clock_gettime() function, which falls back to
> > > > > the clock_gettime64() syscall on kernels prior to 5.5, or to the 32-bit
> > > > > clock_gettime() prior to Linux-5.1. As reported in the bug, Linux-4.19 does
> > > > > not show the bug.
> > > > >
> > > > > - The behavior was not reproduced on the same user space in qemu,
> > > > > though I cannot tell whether the exact same kernel binary was used.
> > > > >
> > > > > - glibc-2.31 calls the same clock_gettime64() vdso function on arm to
> > > > > implement clock_gettime(), but earlier versions did not. I have not
> > > > > seen any reports of this bug, which could be explained by users
> > > > > generally being on older versions.
> > > > >
> > > > > - As far as I can tell, there are no reports of this bug from other users,
> > > > > and so far nobody could reproduce it.
> >
> > note: i could not reproduce it in qemu-system with these configs:
> >
> > qemu-system-aarch64 + arm64 kernel + compat vdso
> > qemu-system-aarch64 + kvm accel (on cortex-a72) + 32bit arm kernel
> > qemu-system-arm + cpu max + 32bit arm kernel
> >
> > so i think it's something specific to that user's setup
> > (maybe rpi hw bug or gcc miscompiled the vdso or something
> > with that particular linux, i built my own linux 5.6 because
> > i did not know the exact kernel version where the bug was seen)
> >
> > i don't have access to rpi (or other cortex-a53 where i
> > can install my own kernel) so this is as far as i got.
>
> If we have a binary of the kernel that's known to be failing on the
> hardware, it would be useful to dump its vdso and examine the
> disassembly to see if it was miscompiled.
OK, OP posted it and I think we've solved this. See
https://github.com/richfelker/musl-cross-make/issues/96#issuecomment-631604410
And my analysis:
<@dalias> see what i just found on the tracker
<@dalias> patch_vdso/vdso_nullpatch_one in arch/arm/kernel/vdso.c patches out the time32 functions in this case
<@dalias> but not the time64 one
<@dalias> this looks like a real kernel bug that's not hw-specific except breaking on all hardware where the patching-out is needed
<@dalias> we could possibly work around it by refusing to use the time64 vdso unless the time32 one is also present
<@dalias> yep
<@dalias> so i think we've solved this. the kernel thought it wasnt using vdso anymore because it patched it out
<@dalias> but it forgot to patch out the time64 one
<@dalias> so it stopped updating the data needed for vdso to work
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* Re: [PATCH v5 1/4] rcu/kasan: record and print call_rcu() call stack
From: Andrey Konovalov @ 2020-05-20 17:08 UTC (permalink / raw)
To: Walter Wu
Cc: wsd_upstream, Paul E . McKenney, Linux Memory Management List,
Lai Jiangshan, Josh Triplett, kasan-dev, LKML, Joel Fernandes,
linux-mediatek, Alexander Potapenko, Linux ARM, Matthias Brugger,
Andrey Ryabinin, Andrew Morton, Dmitry Vyukov, Mathieu Desnoyers
In-Reply-To: <20200520123434.3888-1-walter-zh.wu@mediatek.com>
On Wed, May 20, 2020 at 2:34 PM Walter Wu <walter-zh.wu@mediatek.com> wrote:
>
> This feature will record the last two call_rcu() call stacks and
> prints up to 2 call_rcu() call stacks in KASAN report.
>
> When call_rcu() is called, we store the call_rcu() call stack into
> slub alloc meta-data, so that the KASAN report can print rcu stack.
>
> [1]https://bugzilla.kernel.org/show_bug.cgi?id=198437
> [2]https://groups.google.com/forum/#!searchin/kasan-dev/better$20stack$20traces$20for$20rcu%7Csort:date/kasan-dev/KQsjT_88hDE/7rNUZprRBgAJ
>
> Signed-off-by: Walter Wu <walter-zh.wu@mediatek.com>
> Suggested-by: Dmitry Vyukov <dvyukov@google.com>
> Acked-by: Paul E. McKenney <paulmck@kernel.org>
> Cc: Andrey Ryabinin <aryabinin@virtuozzo.com>
> Cc: Dmitry Vyukov <dvyukov@google.com>
> Cc: Alexander Potapenko <glider@google.com>
> Cc: Andrew Morton <akpm@linux-foundation.org>
> Cc: Josh Triplett <josh@joshtriplett.org>
> Cc: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
> Cc: Lai Jiangshan <jiangshanlai@gmail.com>
> Cc: Joel Fernandes <joel@joelfernandes.org>
> Cc: Andrey Konovalov <andreyknvl@google.com>
> ---
> include/linux/kasan.h | 2 ++
> kernel/rcu/tree.c | 2 ++
> mm/kasan/common.c | 4 ++--
> mm/kasan/generic.c | 21 +++++++++++++++++++++
> mm/kasan/kasan.h | 10 ++++++++++
> mm/kasan/report.c | 24 ++++++++++++++++++++++++
> 6 files changed, 61 insertions(+), 2 deletions(-)
>
> diff --git a/include/linux/kasan.h b/include/linux/kasan.h
> index 31314ca7c635..23b7ee00572d 100644
> --- a/include/linux/kasan.h
> +++ b/include/linux/kasan.h
> @@ -174,11 +174,13 @@ static inline size_t kasan_metadata_size(struct kmem_cache *cache) { return 0; }
>
> void kasan_cache_shrink(struct kmem_cache *cache);
> void kasan_cache_shutdown(struct kmem_cache *cache);
> +void kasan_record_aux_stack(void *ptr);
>
> #else /* CONFIG_KASAN_GENERIC */
>
> static inline void kasan_cache_shrink(struct kmem_cache *cache) {}
> static inline void kasan_cache_shutdown(struct kmem_cache *cache) {}
> +static inline void kasan_record_aux_stack(void *ptr) {}
>
> #endif /* CONFIG_KASAN_GENERIC */
>
> diff --git a/kernel/rcu/tree.c b/kernel/rcu/tree.c
> index 06548e2ebb72..36a4ff7f320b 100644
> --- a/kernel/rcu/tree.c
> +++ b/kernel/rcu/tree.c
> @@ -57,6 +57,7 @@
> #include <linux/slab.h>
> #include <linux/sched/isolation.h>
> #include <linux/sched/clock.h>
> +#include <linux/kasan.h>
> #include "../time/tick-internal.h"
>
> #include "tree.h"
> @@ -2668,6 +2669,7 @@ __call_rcu(struct rcu_head *head, rcu_callback_t func)
> head->func = func;
> head->next = NULL;
> local_irq_save(flags);
> + kasan_record_aux_stack(head);
> rdp = this_cpu_ptr(&rcu_data);
>
> /* Add the callback to our list. */
> diff --git a/mm/kasan/common.c b/mm/kasan/common.c
> index 2906358e42f0..8bc618289bb1 100644
> --- a/mm/kasan/common.c
> +++ b/mm/kasan/common.c
> @@ -41,7 +41,7 @@
> #include "kasan.h"
> #include "../slab.h"
>
> -static inline depot_stack_handle_t save_stack(gfp_t flags)
> +depot_stack_handle_t kasan_save_stack(gfp_t flags)
> {
> unsigned long entries[KASAN_STACK_DEPTH];
> unsigned int nr_entries;
> @@ -54,7 +54,7 @@ static inline depot_stack_handle_t save_stack(gfp_t flags)
> static inline void set_track(struct kasan_track *track, gfp_t flags)
> {
> track->pid = current->pid;
> - track->stack = save_stack(flags);
> + track->stack = kasan_save_stack(flags);
> }
>
> void kasan_enable_current(void)
> diff --git a/mm/kasan/generic.c b/mm/kasan/generic.c
> index 56ff8885fe2e..8acf48882ba2 100644
> --- a/mm/kasan/generic.c
> +++ b/mm/kasan/generic.c
> @@ -325,3 +325,24 @@ DEFINE_ASAN_SET_SHADOW(f2);
> DEFINE_ASAN_SET_SHADOW(f3);
> DEFINE_ASAN_SET_SHADOW(f5);
> DEFINE_ASAN_SET_SHADOW(f8);
> +
> +void kasan_record_aux_stack(void *addr)
> +{
> + struct page *page = kasan_addr_to_page(addr);
> + struct kmem_cache *cache;
> + struct kasan_alloc_meta *alloc_info;
> + void *object;
> +
> + if (!(page && PageSlab(page)))
> + return;
> +
> + cache = page->slab_cache;
> + object = nearest_obj(cache, page, addr);
> + alloc_info = get_alloc_info(cache, object);
> +
> + /*
> + * record the last two call_rcu() call stacks.
> + */
> + alloc_info->aux_stack[1] = alloc_info->aux_stack[0];
> + alloc_info->aux_stack[0] = kasan_save_stack(GFP_NOWAIT);
> +}
> diff --git a/mm/kasan/kasan.h b/mm/kasan/kasan.h
> index e8f37199d885..a7391bc83070 100644
> --- a/mm/kasan/kasan.h
> +++ b/mm/kasan/kasan.h
> @@ -104,7 +104,15 @@ struct kasan_track {
>
> struct kasan_alloc_meta {
> struct kasan_track alloc_track;
> +#ifdef CONFIG_KASAN_GENERIC
> + /*
> + * call_rcu() call stack is stored into struct kasan_alloc_meta.
> + * The free stack is stored into struct kasan_free_meta.
> + */
> + depot_stack_handle_t aux_stack[2];
> +#else
> struct kasan_track free_track[KASAN_NR_FREE_STACKS];
> +#endif
> #ifdef CONFIG_KASAN_SW_TAGS_IDENTIFY
> u8 free_pointer_tag[KASAN_NR_FREE_STACKS];
> u8 free_track_idx;
> @@ -159,6 +167,8 @@ void kasan_report_invalid_free(void *object, unsigned long ip);
>
> struct page *kasan_addr_to_page(const void *addr);
>
> +depot_stack_handle_t kasan_save_stack(gfp_t flags);
> +
> #if defined(CONFIG_KASAN_GENERIC) && \
> (defined(CONFIG_SLAB) || defined(CONFIG_SLUB))
> void quarantine_put(struct kasan_free_meta *info, struct kmem_cache *cache);
> diff --git a/mm/kasan/report.c b/mm/kasan/report.c
> index 80f23c9da6b0..29a801d5cd74 100644
> --- a/mm/kasan/report.c
> +++ b/mm/kasan/report.c
> @@ -105,6 +105,17 @@ static void end_report(unsigned long *flags)
> kasan_enable_current();
> }
>
> +#ifdef CONFIG_KASAN_GENERIC
> +static void print_stack(depot_stack_handle_t stack)
> +{
> + unsigned long *entries;
> + unsigned int nr_entries;
> +
> + nr_entries = stack_depot_fetch(stack, &entries);
> + stack_trace_print(entries, nr_entries, 0);
> +}
> +#endif
The idea of moving it here was to reuse print_stack() in print_track() :)
> +
> static void print_track(struct kasan_track *track, const char *prefix)
> {
> pr_err("%s by task %u:\n", prefix, track->pid);
> @@ -192,6 +203,19 @@ static void describe_object(struct kmem_cache *cache, void *object,
> free_track = kasan_get_free_track(cache, object, tag);
> print_track(free_track, "Freed");
> pr_err("\n");
> +
> +#ifdef CONFIG_KASAN_GENERIC
> + if (alloc_info->aux_stack[0]) {
> + pr_err("Last call_rcu():\n");
> + print_stack(alloc_info->aux_stack[0]);
> + pr_err("\n");
> + }
> + if (alloc_info->aux_stack[1]) {
> + pr_err("Second to last call_rcu():\n");
> + print_stack(alloc_info->aux_stack[1]);
> + pr_err("\n");
> + }
> +#endif
> }
>
> describe_object_addr(cache, object, addr);
> --
> 2.18.0
>
> --
> You received this message because you are subscribed to the Google Groups "kasan-dev" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to kasan-dev+unsubscribe@googlegroups.com.
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* Re: [RFC PATCH v3 2/2] arm64: tlb: Use the TLBI RANGE feature in arm64
From: Catalin Marinas @ 2020-05-20 17:08 UTC (permalink / raw)
To: Zhenyu Ye
Cc: linux-arch, suzuki.poulose, maz, linux-kernel, xiexiangyou,
steven.price, zhangshaokun, linux-mm, arm, prime.zeng, guohanjun,
olof, kuhn.chenqun, will, linux-arm-kernel
In-Reply-To: <54468aae-dbb1-66bd-c633-82fc75936206@huawei.com>
On Mon, May 18, 2020 at 08:21:02PM +0800, Zhenyu Ye wrote:
> On 2020/5/14 23:28, Catalin Marinas wrote:
> > On Tue, Apr 14, 2020 at 07:28:35PM +0800, Zhenyu Ye wrote:
> >> + }
> >> + scale++;
> >> + range_size >>= TLB_RANGE_MASK_SHIFT;
> >> + }
> >
> > So, you start from scale 0 and increment it until you reach the maximum.
> > I think (haven't done the maths on paper) you could also start from the
> > top with something like scale = ilog2(range_size) / 5. Not sure it's
> > significantly better though, maybe avoiding the loop 3 times if your
> > range is 2MB (which happens with huge pages).
>
> This optimization is only effective when the range is a multiple of 256KB
> (when the page size is 4KB), and I'm worried about the performance
> of ilog2(). I traced the __flush_tlb_range() last year and found that in
> most cases the range is less than 256K (see details in [1]).
THP or hugetlbfs would exercise bigger strides but I guess it depends on
the use-case. ilog2() should be reduced to a few instructions on arm64
AFAICT (haven't tried but it should use the CLZ instruction).
> > Anyway, I think it would be more efficient if we combine the
> > __flush_tlb_range() and the _directly one into the same function with a
> > single loop for both. For example, if the stride is 2MB already, we can
> > handle this with a single classic TLBI without all the calculations for
> > the range operation. The hardware may also handle this better since the
> > software already told it there can be only one entry in that 2MB range.
> > So each loop iteration could figure which operation to use based on
> > cpucaps, TLBI range ops, stride and reduce range_size accordingly.
>
> Summarize your suggestion in one sentence: use 'stride' to optimize the
> preformance of TLBI. This can also be done by dividing into two functions,
> and this should indeed be taken into account in the TLBI RANGE feature.
>
> But if we figure which operation to use based on cpucaps in each loop
> iteration, then cpus_have_const_cap() will be called frequently, which
> may affect performance of TLBI. In my opinion, we should do as few
> judgments as possible in the loop, so judge the cpucaps outside the
> loop maybe a good choice.
cpus_have_const_cap() is a static label, so should be patched with a
branch or nop. My point was that in the classic __flush_tlb_range()
loop, instead of an addr += stride we could have something more dynamic
depending on whether the CPU supports range TLBI ops or not. But we
would indeed have more (static) branches in the loop, so possibly some
performance degradation.
If the code looks ok, I'd favour this and we can look at the
optimisation later. But I can't really tell how the code would look
without attempting to merge the two.
Anyway, a first step would be to to add the the range and stride to the
decision (i.e. (end-start)/stride > 1) before jumping to the range
operations. You can avoid the additional checks in the new TLBI
functions since we know we have at least two (huge)pages.
--
Catalin
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^ permalink raw reply
* Re: [PATCH v4] ACPI/IORT: Fix PMCG node single ID mapping handling.
From: Tuan Phan @ 2020-05-20 17:07 UTC (permalink / raw)
To: Lorenzo Pieralisi
Cc: Hanjun Guo, Neil Leeder, Tuan Phan, Rafael J. Wysocki,
linux-kernel, Shameer Kolothum, linux-acpi, Sudeep Holla, patches,
Robin Murphy, linux-arm-kernel, Len Brown
In-Reply-To: <20200520125813.GA6906@e121166-lin.cambridge.arm.com>
> On May 20, 2020, at 5:58 AM, Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> wrote:
>
> On Fri, May 15, 2020 at 12:24:46PM -0700, Tuan Phan wrote:
>> An IORT PMCG node can have no ID mapping if its overflow interrupt is
>> wire based therefore the code that parses the PMCG node can not assume
>> the node will always have a single mapping present at index 0.
>>
>> Fix iort_get_id_mapping_index() by checking for an overflow interrupt
>> and mapping count.
>>
>> Fixes: 24e516049360 ("ACPI/IORT: Add support for PMCG").
>
> Remove these periods in the $SUBJECT and commit references, I
> don't know why you keep adding them.
>
> Anyway - I don't know if it is too late for v5.8 but this patch
> is ready to be merged (minus the nits I have just mentioned).
Thanks, will fix it.
>
> Lorenzo
>
>> Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
>> Reviewed-by: Hanjun Guo <guoahanjun@huawei.com>
>> Signed-off-by: Tuan Phan <tuanphan@os.amperecomputing.com>
>> ---
>> v1 -> v2:
>> - Use pmcg node to detect wired base overflow interrupt.
>>
>> v2 -> v3:
>> - Address Hanjun and Robin's comments.
>>
>> v3 -> v4:
>> - Update the title and description as mentioned by Lorenzo.
>>
>> drivers/acpi/arm64/iort.c | 5 +++++
>> 1 file changed, 5 insertions(+)
>>
>> diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c
>> index ed3d2d1..12bb70e 100644
>> --- a/drivers/acpi/arm64/iort.c
>> +++ b/drivers/acpi/arm64/iort.c
>> @@ -414,6 +414,7 @@ static struct acpi_iort_node *iort_node_get_id(struct acpi_iort_node *node,
>> static int iort_get_id_mapping_index(struct acpi_iort_node *node)
>> {
>> struct acpi_iort_smmu_v3 *smmu;
>> + struct acpi_iort_pmcg *pmcg;
>>
>> switch (node->type) {
>> case ACPI_IORT_NODE_SMMU_V3:
>> @@ -441,6 +442,10 @@ static int iort_get_id_mapping_index(struct acpi_iort_node *node)
>>
>> return smmu->id_mapping_index;
>> case ACPI_IORT_NODE_PMCG:
>> + pmcg = (struct acpi_iort_pmcg *)node->node_data;
>> + if (pmcg->overflow_gsiv || node->mapping_count == 0)
>> + return -EINVAL;
>> +
>> return 0;
>> default:
>> return -EINVAL;
>> --
>> 2.7.4
>>
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^ permalink raw reply
* Re: [PATCH v1 2/6] arm/smmu: Add auxiliary domain support for arm-smmuv2
From: Rob Clark @ 2020-05-20 16:35 UTC (permalink / raw)
To: Will Deacon, Rob Clark, linux-arm-msm, Linux Kernel Mailing List,
list@263.net:IOMMU DRIVERS <iommu@lists.linux-foundation.org>, Joerg Roedel <joro@8bytes.org>, ,
Robin Murphy,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
In-Reply-To: <20200520151312.GB31730@jcrouse1-lnx.qualcomm.com>
On Wed, May 20, 2020 at 8:13 AM Jordan Crouse <jcrouse@codeaurora.org> wrote:
>
> On Wed, May 20, 2020 at 01:57:01PM +0100, Will Deacon wrote:
> > On Mon, May 18, 2020 at 08:50:27AM -0700, Rob Clark wrote:
> > > On Mon, May 18, 2020 at 8:18 AM Will Deacon <will@kernel.org> wrote:
> > > > On Wed, Mar 18, 2020 at 04:43:07PM -0700, Rob Clark wrote:
> > > > > We do in fact need live domain switching, that is really the whole
> > > > > point. The GPU CP (command processor/parser) is directly updating
> > > > > TTBR0 and triggering TLB flush, asynchronously from the CPU.
> > > > >
> > > > > And I think the answer about ASID is easy (on current hw).. it must be zero[*].
> > > >
> > > > Using ASID zero is really bad, because it means that you will end up sharing
> > > > TLB entries with whichever device is using context bank 0.
> > > >
> > > > Is the SMMU only used by the GPU in your SoC?
> > > >
> > >
> > > yes, the snapdragon SoCs have two SMMU instances, one used by the GPU,
> > > where ASID0/cb0 is the gpu itself, and another cb is the GMU
> > > (basically power control for the gpu), and the second SMMU is
> > > everything else.
> >
> > Right, in which case I'm starting to think that we should treat this GPU
> > SMMU instance specially. Give it its own compatible string (looks like you
> > need this for HUPCFG anyway) and hook in via arm_smmu_impl_init(). You can
> > then set IO_PGTABLE_QUIRK_ARM_TTBR1 when talking to the io-pgtable code
> > without having to add a domain attribute.
>
> If we did this via a special GPU SMMU instance then we could also create and
> register a dummy TTBR0 instance along with the TTBR1 instance and then we
> wouldn't need to worry about the aux domains at all.
>
> > With that. you'll need to find a way to allow the GPU driver to call into
> > your own hooks for getting at the TTBR0 tables -- given that you're
> > programming these in the hardware, I don't think it makes sense to expose
> > that in the IOMMU API, since most devices won't be able to do anything with
> > that data. Perhaps you could install a couple of function pointers
> > (subdomain_alloc/subdomain_free) in the GPU device when you see it appear
> > from the SMMU driver? Alternatively, you could make an io_pgtable_cfg
> > available so that the GPU driver can interface with io-pgtable directly.
>
> I don't want to speak for Rob but I think that this is the same direction we've
> landed on. If we use the implementation specific code to initialize the base
> pagetables then the GPU driver can use io-pgtable directly. We can easily
> construct an io_pgtable_cfg. This feature will only be available for opt-in
> GPU targets that will have a known configuration.
Agreed about using io-pgtable helpers directly.. the gpu's use-case is
pretty far different from anything normal/sane, and I don't think it
is worth designing some generic iommu interfaces with precisely one
user[*]. We just need enough in arm-smmu(/-impl) to bootstrap things
when we power up the gpu.
BR,
-R
[*] all the other gpu's that I've seen so far, even if they sit behind
an iommu, they have their own internal mmu
> The only gotcha is TLB maintenance but Rob and I have ideas about coordinating
> with the GPU hardware (which has to do a TLBIALL during a switch anyway) and we
> can always use the iommu_tlb_flush_all() hammer from software if we really need
> it. It might take a bit of thought, but it is doable.
>
> > Yes, it's ugly, but I don't think it's worth trying to abstract this.
>
> I'm not sure how ugly it is. I've always operated under the assumption that the
> GPU SMMU was special (though it had generic registers) just because of where it
> was and how it it was used. In the long run baking in a implementation specific
> solution would probably be preferable to lots of domain attributes and aux
> domains that would never be used except by us.
>
> > Thoughts? It's taken me a long time to figure out what's going on here,
> > so sorry if it feels like I'm leading you round the houses.
>
> I'll hack on this and try to get something in place. It might be dumber on the
> GPU side than we would like but it would at least spur some more conversation.
>
> Jordan
>
> > Will
>
> --
> The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
> a Linux Foundation Collaborative Project
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^ permalink raw reply
* Re: Re: [RFC PATCH] i2c: at91: Fix pinmux after devm_gpiod_get() for bus recovery
From: Wolfram Sang @ 2020-05-20 16:27 UTC (permalink / raw)
To: Codrin.Ciubotariu
Cc: alan, kamel.bouhara, alexandre.belloni, linus.walleij,
linux-kernel, linux-gpio, Ludovic.Desroches, linux-i2c, linux,
linux-arm-kernel
In-Reply-To: <c7a35978-03dd-3c73-6e7d-15ed40b5c57c@microchip.com>
[-- Attachment #1.1: Type: text/plain, Size: 853 bytes --]
> > This will do for 5.7. For 5.8 or 5.9, I can imagine to take the two
> > pinctrl_state pointers into bus_recovery_info and handle all this in the
> > core. I will try this later this week if noone is super-eager to try it
> > out before.
> >
>
> By 'all this' you mean to move the entire function in the core, right?
> Having just these two pointers bus_recinovery_info won't help much. I
> can try it, if you haven't already started...
I mean to add those two pointers to bus_recinovery_info and if they are
populated, then the I2C core is doing the necessary magic (or maybe just
the pinctrl handle and assume the states have fixed names?). Russell
just sent patches to add it to the PXA driver, so we could now double
check how much could be factored out.
I haven't started yet, let's keep in touch who started first :)
[-- Attachment #1.2: signature.asc --]
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* [PATCH v6 19/19] mtd: spi-nor: micron-st: allow using MT35XU512ABA in Octal DTR mode
From: Pratyush Yadav @ 2020-05-20 16:30 UTC (permalink / raw)
To: Tudor Ambarus, Miquel Raynal, Richard Weinberger,
Vignesh Raghavendra, Mark Brown, Nicolas Ferre, Alexandre Belloni,
Ludovic Desroches, Matthias Brugger, linux-mtd, linux-kernel,
linux-spi, linux-arm-kernel, linux-mediatek
Cc: Mason Yang, Boris Brezillon, Sekhar Nori, Pratyush Yadav
In-Reply-To: <20200520163053.24357-1-p.yadav@ti.com>
Since this flash doesn't have a Profile 1.0 table, the Octal DTR
capabilities are enabled in the post SFDP fixup, along with the 8D-8D-8D
fast read settings.
Enable Octal DTR mode with 20 dummy cycles to allow running at the
maximum supported frequency of 200Mhz.
The flash supports the soft reset sequence. So, add the flag in the
flash's info.
Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
---
drivers/mtd/spi-nor/micron-st.c | 112 +++++++++++++++++++++++++++++++-
1 file changed, 111 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
index 3dca5b9af3b6..3414c44a5c96 100644
--- a/drivers/mtd/spi-nor/micron-st.c
+++ b/drivers/mtd/spi-nor/micron-st.c
@@ -8,10 +8,120 @@
#include "core.h"
+#define SPINOR_OP_MT_DTR_RD 0xfd /* Fast Read opcode in DTR mode */
+#define SPINOR_OP_MT_RD_ANY_REG 0x85 /* Read volatile register */
+#define SPINOR_OP_MT_WR_ANY_REG 0x81 /* Write volatile register */
+#define SPINOR_REG_MT_CFR0V 0x00 /* For setting octal DTR mode */
+#define SPINOR_REG_MT_CFR1V 0x01 /* For setting dummy cycles */
+#define SPINOR_MT_DTR_NO_DQS 0xc7 /* Enable Octal DTR without DQS. */
+#define SPINOR_MT_EXSPI 0xff /* Enable Extended SPI (default) */
+
+static int spi_nor_micron_octal_dtr_enable(struct spi_nor *nor, bool enable)
+{
+ struct spi_mem_op op;
+ u8 *buf = nor->bouncebuf;
+ u8 addr_width;
+ int ret;
+
+ if (enable)
+ addr_width = 3;
+ else
+ addr_width = 4;
+
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ return ret;
+
+ if (enable)
+ *buf = SPINOR_MT_DTR_NO_DQS;
+ else
+ *buf = SPINOR_MT_EXSPI;
+ op = (struct spi_mem_op)
+ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 1),
+ SPI_MEM_OP_ADDR(addr_width, SPINOR_REG_MT_CFR0V, 1),
+ SPI_MEM_OP_NO_DUMMY,
+ SPI_MEM_OP_DATA_OUT(1, buf, 1));
+
+ if (!enable)
+ spi_nor_spimem_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR);
+
+ ret = spi_mem_exec_op(nor->spimem, &op);
+ if (ret) {
+ dev_err(nor->dev, "Failed to enable octal DTR mode\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int mt35xu512aba_setup(struct spi_nor *nor,
+ const struct spi_nor_hwcaps *hwcaps)
+{
+ struct spi_mem_op op;
+ u8 *buf = nor->bouncebuf;
+ u8 addr_width = 3;
+ int ret;
+
+ if (!nor->spimem) {
+ dev_err(nor->dev,
+ "operation not supported for non-spimem drivers\n");
+ return -ENOTSUPP;
+ }
+
+ /* Set dummy cycles for Fast Read to the default of 20. */
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ return ret;
+
+ *buf = 20;
+ op = (struct spi_mem_op)
+ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MT_WR_ANY_REG, 1),
+ SPI_MEM_OP_ADDR(addr_width, SPINOR_REG_MT_CFR1V, 1),
+ SPI_MEM_OP_NO_DUMMY,
+ SPI_MEM_OP_DATA_OUT(1, buf, 1));
+ ret = spi_mem_exec_op(nor->spimem, &op);
+ if (ret)
+ return ret;
+
+ ret = spi_nor_wait_till_ready(nor);
+ if (ret)
+ return ret;
+
+
+ return spi_nor_default_setup(nor, hwcaps);
+}
+
+static void mt35xu512aba_default_init(struct spi_nor *nor)
+{
+ nor->params->octal_dtr_enable = spi_nor_micron_octal_dtr_enable;
+ nor->params->setup = mt35xu512aba_setup;
+}
+
+static void mt35xu512aba_post_sfdp_fixup(struct spi_nor *nor)
+{
+ /* Set the Fast Read settings. */
+ nor->params->hwcaps.mask |= SNOR_HWCAPS_READ_8_8_8_DTR;
+ spi_nor_set_read_settings(&nor->params->reads[SNOR_CMD_READ_8_8_8_DTR],
+ 0, 20, SPINOR_OP_MT_DTR_RD,
+ SNOR_PROTO_8_8_8_DTR);
+
+ nor->params->hwcaps.mask |= SNOR_HWCAPS_PP_8_8_8_DTR;
+
+ nor->cmd_ext_type = SPI_NOR_EXT_REPEAT;
+ nor->params->rdsr_dummy = 8;
+ nor->params->rdsr_addr_nbytes = 0;
+}
+
+static struct spi_nor_fixups mt35xu512aba_fixups = {
+ .default_init = mt35xu512aba_default_init,
+ .post_sfdp = mt35xu512aba_post_sfdp_fixup,
+};
+
static const struct flash_info micron_parts[] = {
{ "mt35xu512aba", INFO(0x2c5b1a, 0, 128 * 1024, 512,
SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ |
- SPI_NOR_4B_OPCODES) },
+ SPI_NOR_4B_OPCODES | SPI_NOR_OCTAL_DTR_READ)
+ .fixups = &mt35xu512aba_fixups},
{ "mt35xu02g", INFO(0x2c5b1c, 0, 128 * 1024, 2048,
SECT_4K | USE_FSR | SPI_NOR_OCTAL_READ |
SPI_NOR_4B_OPCODES) },
--
2.26.2
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