* Re: [PATCH v5 09/19] mtd: spi-nor: sfdp: parse xSPI Profile 1.0 table
From: masonccyang @ 2020-05-21 8:09 UTC (permalink / raw)
To: Pratyush Yadav
Cc: Alexandre Belloni, Vignesh Raghavendra, Tudor Ambarus, juliensu,
Richard Weinberger, Mark Brown, Sekhar Nori, linux-kernel,
linux-spi, Ludovic Desroches, Boris Brezillon, linux-mediatek,
Miquel Raynal, Matthias Brugger, linux-mtd, linux-arm-kernel
In-Reply-To: <20200520103728.jtbslowdfrv3o5yz@ti.com>
Hi Pratyush,
> >
> > > > > +/**
> > > > > + * spi_nor_parse_profile1() - parse the xSPI Profile 1.0 table
> > > > > + * @nor: pointer to a 'struct spi_nor'
> > > > > + * @param_header: pointer to the 'struct
sfdp_parameter_header'
> > > > describing
> > > > > + * the 4-Byte Address Instruction Table length and
version.
> > > > > + * @params: pointer to the 'struct
spi_nor_flash_parameter' to
> > be.
> > > > > + *
> > > > > + * Return: 0 on success, -errno otherwise.
> > > > > + */
> > > > > +static int spi_nor_parse_profile1(struct spi_nor *nor,
> > > > > + const struct sfdp_parameter_header
*profile1_header,
> > > > > + struct spi_nor_flash_parameter *params)
> > > > > +{
> > > > > + u32 *table, opcode, addr;
> > > > > + size_t len;
> > > > > + int ret, i;
> > > > > +
> > > > > + len = profile1_header->length * sizeof(*table);
> > > > > + table = kmalloc(len, GFP_KERNEL);
> > > > > + if (!table)
> > > > > + return -ENOMEM;
> > > > > +
> > > > > + addr = SFDP_PARAM_HEADER_PTP(profile1_header);
> > > > > + ret = spi_nor_read_sfdp(nor, addr, len, table);
> > > > > + if (ret)
> > > > > + goto out;
> > > > > +
> > > > > + /* Fix endianness of the table DWORDs. */
> > > > > + for (i = 0; i < profile1_header->length; i++)
> > > > > + table[i] = le32_to_cpu(table[i]);
> > > > > +
> > > > > + /* Get 8D-8D-8D fast read opcode and dummy cycles. */
> > > > > + opcode = FIELD_GET(PROFILE1_DWORD1_RD_FAST_CMD, table[0]);
> > > > > +
> > > > > + /*
> > > > > + * Update the fast read settings. We set the default dummy
> > cycles to
> > > > 20
> > > > > + * here. Flashes can change this value if they need to when
> > enabling
> > > > > + * octal mode.
> > > > > + */
> > > > > +
spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_8_8_8_DTR],
> > > > > + 0, 20, opcode,
> > > > > + SNOR_PROTO_8_8_8_DTR);
> > > > > +
> > > >
> > > >
> > > > I thought we have a agreement that only do parse here, no other
read
> > > > parameters setting.
> > >
> > > Yes, and I considered it. But it didn't make much sense to me to
> > > introduce an extra member in struct spi_nor just to make this call
in
> > > some other function later.
> > >
> > > Why exactly do you think doing this here is bad? The way I see it,
we
> > > avoid carrying around an extra member in spi_nor and this also
allows
> > > flashes to change the read settings easily in a post-sfdp hook. The
> > > 4bait parsing function does something similar.
> >
> > I think it's not a question for good or bad.
> >
> > 4bait parsing function parse the 4-Byte Address Instruction Table
> > and set up read/pp parameters there for sure.
> >
> > Here we give the function name spi_nor_parse_profile1() but also
>
> But the function that parses 4bait table is also called
> spi_nor_parse_4bait().
>
> > do others setting that has nothing to do with it,
>
> Why has setting read opcode and dummy cycles got nothing to do with it?
> The purpose of the Profile 1.0 table is to tell us the Read Fast command
> and dummy cycles, among other things. I think it _does_ have something
> to do with it.
As you know I mean this function just do parse parameter of profile 1
table
and keep these value data for later usage.
A device supports xSPI profile table could work in either 8S-8S-8S or
8D-8D-8D mode.
It seems to setup these parameters somewhere out here is betters.
>
> Just like the 4bait table tells us the 4-byte opcodes and we set them up
> in our data structures, the profile 1.0 table tells us the 8D read
> opcode and dummy cycles, and we set them up in our data structures.
>
> > it seems not good for SW module design.
> > oh, it's my humble opinion.
> >
> > >
> > > What are the benefits of doing it otherwise?
> >
> > For other Octal Flash like mx25*
>
> I mean from a design perspective. How does it make the code better, or
> the job of people who need to read/change it easier?
yes, agreed.
I also need to patch for 8S-8S-8S mode, not only 8D-8D-8D mode.
That's why we have some discussions.
thanks & best regards,
Mason
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^ permalink raw reply
* Re: [PATCH v2 3/4] arm64: cpufeature: Modify address authentication cpufeature to exact
From: Amit Kachhap @ 2020-05-21 8:09 UTC (permalink / raw)
To: Suzuki K Poulose, catalin.marinas
Cc: mark.rutland, keescook, kristina.martsenko, broonie, james.morse,
Vincenzo.Frascino, will, dave.martin, linux-arm-kernel
In-Reply-To: <0c3c9c2d-e3a5-4b1f-5ff2-c4e21570ae47@arm.com>
Hi Suzuki,
On 5/20/20 6:50 PM, Suzuki K Poulose wrote:
> On 05/13/2020 04:42 PM, Amit Kachhap wrote:
>>
>>
>> On 5/12/20 11:03 PM, Catalin Marinas wrote:
>>> On Fri, May 08, 2020 at 09:51:53PM +0530, Amit Kachhap wrote:
>>>> On 5/6/20 10:43 PM, Catalin Marinas wrote:
>>>>> On Tue, Apr 14, 2020 at 11:01:53AM +0530, Amit Daniel Kachhap wrote:
>>>>>> This patch modifies the address authentication cpufeature type to
>>>>>> EXACT
>>>>>> from earlier LOWER_SAFE as the different configurations added for
>>>>>> Armv8.6
>>>>>> enhanced PAC have different behaviour and there is no tunable to
>>>>>> enable the
>>>>>> lower safe versions. The safe value is set as 0.
>>>>>>
>>>>>> After this change, if there is any variation in configurations in
>>>>>> secondary
>>>>>> cpus from boot cpu then those cpus are marked tainted. The KVM
>>>>>> guests may
>>>>>> completely disable address authentication if there is any such
>>>>>> variations
>>>>>> detected.
>>>>>>
>>>>>> Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com>
>>>>>> ---
>>>>>> arch/arm64/kernel/cpufeature.c | 4 ++--
>>>>>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>>>>>
>>>>>> diff --git a/arch/arm64/kernel/cpufeature.c
>>>>>> b/arch/arm64/kernel/cpufeature.c
>>>>>> index 08795025409c..599b03df2f93 100644
>>>>>> --- a/arch/arm64/kernel/cpufeature.c
>>>>>> +++ b/arch/arm64/kernel/cpufeature.c
>>>>>> @@ -154,9 +154,9 @@ static const struct arm64_ftr_bits
>>>>>> ftr_id_aa64isar1[] = {
>>>>>> ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
>>>>>> ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
>>>>>> ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
>>>>>> ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
>>>>>> ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
>>>>>> - FTR_STRICT, FTR_LOWER_SAFE,
>>>>>> ID_AA64ISAR1_API_SHIFT, 4, 0),
>>>>>> + FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_API_SHIFT, 4, 0),
>>>>>> ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
>>>>>> - FTR_STRICT, FTR_LOWER_SAFE,
>>>>>> ID_AA64ISAR1_APA_SHIFT, 4, 0),
>>>>>> + FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_APA_SHIFT, 4, 0),
>>>>>> ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE,
>>>>>> ID_AA64ISAR1_DPB_SHIFT, 4, 0),
>>>>>> ARM64_FTR_END,
>>>>>
>>>>> Is this sufficient? If we have the boot CPU already enabling the
>>>>> ptrauth
>>>>> and we get a secondary CPU with a different ISAR1 field that
>>>>> matches the
>>>>> address auth in cpufeature.c, we still allow it to boot. We no longer
>>>>> report the feature to the user system_supports_address_auth() is true
>>>>> while system_supports_generic_auth() would be false as it checks the
>>>>> sanitised feature registers.
>>>>
>>>> Yes agreed. Generic authentication also needs EXACT cpufeature type.
>>>
>>> I'm still not sure that's sufficient. If we boot the primary CPU with
>>> ptrauth as detected in proc.S, we consider this a boot feature so all
>>> secondary CPUs must have it. Subsequent CPUs are currently checked via
>>> the arm64_features[] definitions and we allow them to boot if the ID is
>>> at least that of the boot CPU. How does this interact with the above
>>> FTR_EXACT changes?
>>
>> Unfortunately FTR_EXACT does not effect the bootflow directly but marks
>> the cpu TAINTED and goes ahead.
>>
>>>
>>> My concern is that we boot with PAC enabled on all CPUs but because of
>>> the FTR_EXACT, the sanitised ID registers no longer report the feature.
>>>
>>
>> You are right that PAC is enabled in hardware but un-reported to user
>> in this case.
>>
>> The issue here is in feature_matches() which only validates with the
>> entry->min_field_value. If we can modify this value to boot cpu value
>> for FTR_EXACT type then this cpu will fail to online.
>> May be we can introduce a new structure or make arm64_feature[]
>> writable for this.
>>
>> Something like below code.
>
> The has_cpuid_feature() is for features with "FTR_LOWER_SAFE". Hacking
> it to support EXACT doesn't look ideal. You may simply add your own
> "matches()" for ptr-auth.
Yes it is reasonable to have separate match() function. I was thinking
of adding some generic match function for FTR_EXACT to be used by other
similar cpufeatures.
>
> something like :
>
> static bool
> has_addr_auth(const struct arm64_cpu_capabilities *entry, int scope)
> {
> static int boot_cpu_auth;
I suppose that is this new match() has to be used for both AUTH_ARCH and
AUTH_IMP_DEF then we may need 2 such static variables.
> int local_cpu_auth;
> u64 isar1;
>
> /* We don't expect to be called with SCOPE_SYSTEM */
> WARN_ON(scope == SCOPE_SYSTEM);
> isar1 = read_sysreg_s(SYS_ID_AA64ISAR1_EL1);
> local_cpu_auth = cpuid_feature_extract_unsigned_field(isar1,
> entry->shift);
>
> /*
> * The ptr-auth feature levels are not intercompatible with
> * lower levels. Hence we must match all the CPUs with that
> * of the boot CPU. So cache the level of boot CPU and compare
> * it against the secondary CPUs.
> */
> if (scope & SCOPE_BOOT_CPU) {
> boot_cpu_auth = local_cpu_auth;
> return boot_cpu_auth > 0;
May be,
return boot_cpu_auth >= entry->min_field_value
> } else if (scope & SCOPE_LOCAL_CPU) {
> return local_cpu_auth == boot_cpu_auth;
> }
> }
>
> Suzuki
Thanks,
Amit Daniel
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^ permalink raw reply
* Re: [PATCH v4 0/7] firmware: smccc: Add basic SMCCC v1.2 + ARCH_SOC_ID support
From: Sudeep Holla @ 2020-05-21 8:05 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Mark Rutland, Lorenzo Pieralisi, Catalin Marinas,
linux-kernel@vger.kernel.org, Steven Price, harb, Will Deacon,
Linux ARM
In-Reply-To: <CAK8P3a1h1MR4Mq2sSV_FDUodrfaKRFtyOuOOGPWAbPYbzjc4YQ@mail.gmail.com>
On Thu, May 21, 2020 at 09:34:10AM +0200, Arnd Bergmann wrote:
> On Thu, May 21, 2020 at 9:07 AM Sudeep Holla <sudeep.holla@arm.com> wrote:
> >
> > On Wed, May 20, 2020 at 11:54:16PM +0200, Arnd Bergmann wrote:
> > > On Wed, May 20, 2020 at 11:29 PM Will Deacon <will@kernel.org> wrote:
> > > >
> > > > On Mon, 18 May 2020 10:12:15 +0100, Sudeep Holla wrote:
> > > > > This patch series adds support for SMCCCv1.2 ARCH_SOC_ID.
> > > > > This doesn't add other changes added in SMCCC v1.2 yet. They will
> > > > > follow these soon along with its first user SPCI/PSA-FF.
> > > > >
> > > > > This is tested using upstream TF-A + the patch[3] fixing the original
> > > > > implementation there.
> > > > >
> > > > > [...]
> > > >
> > > > Applied to arm64 (for-next/smccc), thanks!
> > > >
> > > > [1/7] firmware: smccc: Add HAVE_ARM_SMCCC_DISCOVERY to identify SMCCC v1.1 and above
> > > > https://git.kernel.org/arm64/c/e5bfb21d98b6
> > > > [2/7] firmware: smccc: Update link to latest SMCCC specification
> > > > https://git.kernel.org/arm64/c/15c704ab6244
> > > > [3/7] firmware: smccc: Add the definition for SMCCCv1.2 version/error codes
> > > > https://git.kernel.org/arm64/c/0441bfe7f00a
> > > > [4/7] firmware: smccc: Drop smccc_version enum and use ARM_SMCCC_VERSION_1_x instead
> > > > https://git.kernel.org/arm64/c/ad5a57dfe434
> > > > [5/7] firmware: smccc: Refactor SMCCC specific bits into separate file
> > > > https://git.kernel.org/arm64/c/f2ae97062a48
> > > > [6/7] firmware: smccc: Add function to fetch SMCCC version
> > > > https://git.kernel.org/arm64/c/a4fb17465182
> > > > [7/7] firmware: smccc: Add ARCH_SOC_ID support
> > > > https://git.kernel.org/arm64/c/ce6488f0ce09
> > > >
> > > > Arnd -- Sudeep's reply to you about the sysfs groups seemed reasonable to me,
> > > > but please shout if you'd rather I dropped this in order to pursue an
> > > > alternative approach.
> > >
> > > I missed the reply earlier, thanks for pointing me to it again.
> > >
> > > I'm not entirely convinced, but don't revert it for now because of that,
> > > I assume we can find a solution.
> > >
> >
> > I liked your idea of making this generic and hardcode values if required
> > for other drivers. I will take a look at that/
> >
> > > However, please have a look at the build failure report for patch 5
> > > and fix it if you can see what went wrong.
> > >
> >
> > Any pointers for that failure ? I seem to have missed them. I pushed
> > branch couple of times to my tree but got build success both times.
> > Any specific config or compilers ?
>
> See below for the reply from the 0day build bot to your email. It seems it
> was not sent to the mailing list, but you were on Cc. Looking at it now,
> the fix should be trivial.
>
Ah, clang it is. I must start building with clang regularly.
Thanks for pointing it out. Somehow few of these kbuild-bot emails
has been marked junk last few days. Sorry for the noise.
--
Regards,
Sudeep
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^ permalink raw reply
* Re: Possible race while masking IRQ on Allwinner A20
From: Marc Zyngier @ 2020-05-21 8:02 UTC (permalink / raw)
To: Maxime Ripard
Cc: Marc Dorval, Chen-Yu Tsai, Thomas Gleixner,
Jérôme Pouiller, linux-arm-kernel
In-Reply-To: <20200521072634.6ig7jcuy5tmvmojf@gilmour.lan>
Hi Maxime, Jérôme,
On 2020-05-21 08:26, Maxime Ripard wrote:
> Hi!
>
> Adding Thomas and Marc in Cc.
>
> On Tue, May 19, 2020 at 10:59:26AM +0200, Jérôme Pouiller wrote:
>> I have some trouble with integration of the wfx driver[1] on Allwinner
>> A20 platform.
>>
>> The chip WF200 is connected to the SDIO bus. At the beginning, I tried
>> to use the IRQ provided by the SDIO bus. However, I have noticed I
>> received some IRQs twice. Since the IRQ line is multiplexed with the
>> data line, it is not very clear if it is a bug, or if the SDIO device
>> has to support that.
>>
>> The chip WF200 allows to use a dedicated line for the IRQ (aka
>> "Out-Of-Band" IRQ). So I have enabled this feature with a edge
>> triggered
>> IRQ. However, I missed some IRQs. Indeed, it seems that Allwinner use
>> a
>> 32KHz clock to sample the IRQs. It is not fast enough for us. I think
>> it
>> explains why we miss some IRQs (using the attribute
>> "input-debounce"[2],
>> I tried to enable the 24Mhz clock, but without success).
>
> Without success as in you couldn't make it use the 24MHz clock, or
> using it
> didn't change anything?
>
> But yeah, missing an edge interrupt is bound to happen at some point,
> and a
> level interrupt is going to be more reliable (especially if you can't
> recover
> from a missed interrupt).
>
>> Nevermind, I tried to use a level triggered IRQ (and my request is on
>> this part). As you can see in the wfx driver (in bus_sdio.c and
>> bh.c),
>> I use a threaded IRQ for that. Unfortunately, I receive some IRQs
>> twice.
>> I traced the problem, I get:
>>
>> QSGRenderThread-981 [000] d.h. 247.485524: irq_handler_entry:
>> irq=80 name=wfx
>> QSGRenderThread-981 [000] d.h. 247.485547: irq_handler_exit:
>> irq=80 ret=handled
>> QSGRenderThread-981 [000] d.h. 247.485600: irq_handler_entry:
>> irq=80 name=wfx
>> QSGRenderThread-981 [000] d.h. 247.485606: irq_handler_exit:
>> irq=80 ret=handled
>> irq/80-wfx-260 [001] .... 247.485828: io_read32: CONTROL:
>> 0000f046
>> irq/80-wfx-260 [001] .... 247.486072: io_read32: CONTROL:
>> 0000f046
>> kworker/1:1H-116 [001] .... 247.486214: io_read: QUEUE: 8b 00
>> 84 18 00 00 00 00 01 00 15 82 2b 48 01 1e 88 42 30 00 08 6b d7 c3 53
>> e0 28 80 88 67 32 af ... (192 bytes)
>> kworker/1:1H-116 [001] .... 247.493097: io_read: QUEUE: 00 00
>> 00 00 00 00 00 00 06 06 00 6a 3f 95 00 60 00 00 00 00 08 62 00 00 01
>> 00 5e 00 00 07 28 80 ... (192 bytes)
>> [...]
>>
>> On this trace, we can see:
>> - the hard IRQ handler
>> - the IRQ acknowledge from the thread irq/80-wfx-260
>> - the access to the data from kworker/1:1H-116
>>
>> As far as I understand, the first call to the IRQ handler (at
>> 247.485524) should mask the IRQ 80. So, the second IRQ (at 247.485600)
>> should not happen and the thread irq/80 should be triggered only once.
>>
>> Do you have any idea of what is going wrong with this IRQ?
>
> That's pretty weird indeed. My first guess was that you weren't using
> IRQF_ONESHOT, but it looks like you are. My next lead would be to see
> if the
> mask / unmask hooks in the pinctrl driver are properly called (and
> actually do
> what they are supposed to do). I'm not sure we have any in-tree user of
> a
> threaded IRQ attached to the pinctrl driver, so it might have been
> broken for
> quite some time.
What is certainly puzzling is that this driver doesn't seem to use
threaded IRQs at all. Instead, it uses its own workqueue that seems
to bypass the core IRQ subsystem altogether. So any guarantee we'd
expect goes at of the window.
It is also pretty unclear to me how whether the HW supports switch
from edge to level signalling. The request_irq() call definitely asks
for edge, and I don't know how you'd instruct the HW to change its
signalling method (in general, it isn't possible).
Thanks,
M.
--
Jazz is not dead. It just smells funny...
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^ permalink raw reply
* Re: [PATCH v4 0/7] firmware: smccc: Add basic SMCCC v1.2 + ARCH_SOC_ID support
From: Will Deacon @ 2020-05-21 7:57 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Mark Rutland, Lorenzo Pieralisi, Catalin Marinas,
linux-kernel@vger.kernel.org, Steven Price, harb, Sudeep Holla,
Linux ARM
In-Reply-To: <CAK8P3a1h1MR4Mq2sSV_FDUodrfaKRFtyOuOOGPWAbPYbzjc4YQ@mail.gmail.com>
On Thu, May 21, 2020 at 09:34:10AM +0200, Arnd Bergmann wrote:
> On Thu, May 21, 2020 at 9:07 AM Sudeep Holla <sudeep.holla@arm.com> wrote:
> > On Wed, May 20, 2020 at 11:54:16PM +0200, Arnd Bergmann wrote:
> > > On Wed, May 20, 2020 at 11:29 PM Will Deacon <will@kernel.org> wrote:
> > > > Applied to arm64 (for-next/smccc), thanks!
> > > >
> > > > Arnd -- Sudeep's reply to you about the sysfs groups seemed reasonable to me,
> > > > but please shout if you'd rather I dropped this in order to pursue an
> > > > alternative approach.
> > >
> > > I missed the reply earlier, thanks for pointing me to it again.
D'oh, I took your silence as "no objections". Oh well!
> > > I'm not entirely convinced, but don't revert it for now because of that,
> > > I assume we can find a solution.
Ok, cheers. It's on a separate branch so it's easy enough to drop if
necessary (i.e. no reverts needed). Sudeep -- please send any extra patches
on top of the branch.
> > I liked your idea of making this generic and hardcode values if required
> > for other drivers. I will take a look at that/
> >
> > > However, please have a look at the build failure report for patch 5
> > > and fix it if you can see what went wrong.
> > >
> >
> > Any pointers for that failure ? I seem to have missed them. I pushed
> > branch couple of times to my tree but got build success both times.
> > Any specific config or compilers ?
>
> See below for the reply from the 0day build bot to your email. It seems it
> was not sent to the mailing list, but you were on Cc. Looking at it now,
> the fix should be trivial.
[...]
> >> drivers/firmware/smccc/smccc.c:14:13: warning: no previous prototype for function 'arm_smccc_version_init' [-Wmissing-prototypes]
> void __init arm_smccc_version_init(u32 version, enum arm_smccc_conduit conduit)
> ^
> drivers/firmware/smccc/smccc.c:14:1: note: declare 'static' if the
> function is not intended to be used outside of this translation unit
> void __init arm_smccc_version_init(u32 version, enum arm_smccc_conduit conduit)
I saw that when I applied the patches, but since the function is called from
another compilation unit (psci/psci.o), I just ignored it as we have loads
of these already and it only screams if you build with W=1.
Will
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^ permalink raw reply
* Re: [PATCH 2/2] ARM: Allow either FLATMEM or SPARSEMEM on the multiplatform build
From: Arnd Bergmann @ 2020-05-21 7:47 UTC (permalink / raw)
To: Florian Fainelli
Cc: Doug Berger, Stephen Boyd, Kevin Cernekee,
Russell King - ARM Linux admin, Mike Rapoport, Gregory Fong,
Linux ARM
In-Reply-To: <6d7c3b4f-dde2-95a8-8d36-03ba957aa133@gmail.com>
On Thu, May 21, 2020 at 4:45 AM Florian Fainelli <f.fainelli@gmail.com> wrote:
> On 5/19/2020 1:42 PM, Arnd Bergmann wrote:
> > On Tue, May 19, 2020 at 6:54 PM Russell King - ARM Linux admin <linux@armlinux.org.uk> wrote:
> >
> > I checked the datasheet: ep93xx has four chip-selects, each of them
> > with their own 256MB memory area. Most boards we support use only
> > the last chipselect, but those that have more than one would waste
> > up to 2MB per additional memory chip, which is not nice but doesn't
> > make it a hard requirement as long as the kernel can fit into the first one.
> >
> > However, the chips has a second problem: depending on the
> > specific memory configuration, only every other 2/4/8MB within
> > that range may actually be used, so the mem_map[] array would
> > double its size in practice and (worse) the kernel would likely
> > not fit into the first section without sparsemem.
> >
> > This means we should indeed treat it as a requirement for ep93xx.
>
> That is already captured with the select ARCH_SPARSEMEM_ENABLE or the
> ARCH_EP93XX entry.
Yes, we just need to keep it that way when ep93xx eventually
becomes part of the ARCH_MULTI_V4T configuration.
> Should we just make it possible for multi platform users to override the
> memory model in their configuration file and later we just default
> ARCH_MULTI_V7 to sparsemem?
I think there are three steps:
1. make the memory model user-selectable for all multiplatform kernels
to allow sparsemem
2. change the defconfig files for platforms that would likely benefit
(multi_v7_defconfig, exynos_defconfig, imx_v6_v7_defconfig, ...)
3. change the default for ARCH_MULTI_V7, or alternatively for
configurations that include platforms that usually want it.
My preference would be to have the first two in v5.8, but leave
the third one for a later time, depending on who needs it.
I notice that the changelog text does not give a particular
example of platforms with very sparse memory maps. It
might help to have more background there. Among the platforms
I see, it seems fairly rare to have any RAM above the 4GB
boundary on ARMv7 based chips: keystone2, r-car, and
highbank would be the main examples I can think of, but I
don't know if they have large holes in the memory map.
Arnd
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^ permalink raw reply
* Re: [PATCH v13 5/6] rtc: mt6397: Add support for the MediaTek MT6358 RTC
From: Lee Jones @ 2020-05-21 7:47 UTC (permalink / raw)
To: Matthias Brugger
Cc: linux-rtc, Alessandro Zummo, Alexandre Belloni, drinkcat,
srv_heupstream, Frank Wunderlich, Josef Friedl, Ran Bi, Sean Wang,
Sebastian Reichel, linux-kernel, Richard Fontana, devicetree,
Rob Herring, linux-mediatek, linux-arm-kernel, linux-pm,
Thomas Gleixner, Eddie Huang, Hsin-Hsiung Wang
In-Reply-To: <27c107b3-6ea8-e6f9-697c-7c3c4479008c@gmail.com>
On Sat, 16 May 2020, Matthias Brugger wrote:
> Hi Lee,
>
> On 21/04/2020 05:00, Hsin-Hsiung Wang wrote:
> > From: Ran Bi <ran.bi@mediatek.com>
> >
> > This add support for the MediaTek MT6358 RTC. Driver using
> > compatible data to store different RTC_WRTGR address offset.
> > This replace RTC_WRTGR to RTC_WRTGR_MT6323 in mt6323-poweroff
> > driver which only needed by armv7 CPU without ATF.
> >
> > Signed-off-by: Ran Bi <ran.bi@mediatek.com>
> > Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
> > Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
> > Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
> > Acked-by: Sebastian Reichel <sre@kernel.org>
> > Reviewed-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
>
> We have Acked-by from rtc and reset drivers maintainers. Are you OK to take them
> through your mfd branch?
>
> Are you planning to queue them for v5.8?
>
> Just asking because if so I'd queue patch 6 through my tree.
Yes, please take patch 6.
--
Lee Jones [李琼斯]
Linaro Services Technical Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
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^ permalink raw reply
* Re: [PATCH v4 0/7] firmware: smccc: Add basic SMCCC v1.2 + ARCH_SOC_ID support
From: Arnd Bergmann @ 2020-05-21 7:34 UTC (permalink / raw)
To: Sudeep Holla
Cc: Mark Rutland, Lorenzo Pieralisi, Catalin Marinas,
linux-kernel@vger.kernel.org, Steven Price, harb, Will Deacon,
Linux ARM
In-Reply-To: <20200521070629.GB1131@bogus>
On Thu, May 21, 2020 at 9:07 AM Sudeep Holla <sudeep.holla@arm.com> wrote:
>
> On Wed, May 20, 2020 at 11:54:16PM +0200, Arnd Bergmann wrote:
> > On Wed, May 20, 2020 at 11:29 PM Will Deacon <will@kernel.org> wrote:
> > >
> > > On Mon, 18 May 2020 10:12:15 +0100, Sudeep Holla wrote:
> > > > This patch series adds support for SMCCCv1.2 ARCH_SOC_ID.
> > > > This doesn't add other changes added in SMCCC v1.2 yet. They will
> > > > follow these soon along with its first user SPCI/PSA-FF.
> > > >
> > > > This is tested using upstream TF-A + the patch[3] fixing the original
> > > > implementation there.
> > > >
> > > > [...]
> > >
> > > Applied to arm64 (for-next/smccc), thanks!
> > >
> > > [1/7] firmware: smccc: Add HAVE_ARM_SMCCC_DISCOVERY to identify SMCCC v1.1 and above
> > > https://git.kernel.org/arm64/c/e5bfb21d98b6
> > > [2/7] firmware: smccc: Update link to latest SMCCC specification
> > > https://git.kernel.org/arm64/c/15c704ab6244
> > > [3/7] firmware: smccc: Add the definition for SMCCCv1.2 version/error codes
> > > https://git.kernel.org/arm64/c/0441bfe7f00a
> > > [4/7] firmware: smccc: Drop smccc_version enum and use ARM_SMCCC_VERSION_1_x instead
> > > https://git.kernel.org/arm64/c/ad5a57dfe434
> > > [5/7] firmware: smccc: Refactor SMCCC specific bits into separate file
> > > https://git.kernel.org/arm64/c/f2ae97062a48
> > > [6/7] firmware: smccc: Add function to fetch SMCCC version
> > > https://git.kernel.org/arm64/c/a4fb17465182
> > > [7/7] firmware: smccc: Add ARCH_SOC_ID support
> > > https://git.kernel.org/arm64/c/ce6488f0ce09
> > >
> > > Arnd -- Sudeep's reply to you about the sysfs groups seemed reasonable to me,
> > > but please shout if you'd rather I dropped this in order to pursue an
> > > alternative approach.
> >
> > I missed the reply earlier, thanks for pointing me to it again.
> >
> > I'm not entirely convinced, but don't revert it for now because of that,
> > I assume we can find a solution.
> >
>
> I liked your idea of making this generic and hardcode values if required
> for other drivers. I will take a look at that/
>
> > However, please have a look at the build failure report for patch 5
> > and fix it if you can see what went wrong.
> >
>
> Any pointers for that failure ? I seem to have missed them. I pushed
> branch couple of times to my tree but got build success both times.
> Any specific config or compilers ?
See below for the reply from the 0day build bot to your email. It seems it
was not sent to the mailing list, but you were on Cc. Looking at it now,
the fix should be trivial.
Arnd
8<---
I love your patch! Perhaps something to improve:
[auto build test WARNING on soc/for-next]
[also build test WARNING on arm64/for-next/core linus/master v5.7-rc6
next-20200519]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url: https://github.com/0day-ci/linux/commits/Sudeep-Holla/firmware-smccc-Add-basic-SMCCC-v1-2-ARCH_SOC_ID-support/20200518-171401
base: https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git for-next
config: arm64-randconfig-r026-20200519 (attached as .config)
compiler: clang version 11.0.0 (https://github.com/llvm/llvm-project
135b877874fae96b4372c8a3fbfaa8ff44ff86e3)
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross
-O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install arm64 cross compiling tool for clang build
# apt-get install binutils-aarch64-linux-gnu
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=arm64
If you fix the issue, kindly add following tag as appropriate
Reported-by: kbuild test robot <lkp@intel.com>
All warnings (new ones prefixed by >>, old ones prefixed by <<):
>> drivers/firmware/smccc/smccc.c:14:13: warning: no previous prototype for function 'arm_smccc_version_init' [-Wmissing-prototypes]
void __init arm_smccc_version_init(u32 version, enum arm_smccc_conduit conduit)
^
drivers/firmware/smccc/smccc.c:14:1: note: declare 'static' if the
function is not intended to be used outside of this translation unit
void __init arm_smccc_version_init(u32 version, enum arm_smccc_conduit conduit)
^
static
1 warning generated.
vim +/arm_smccc_version_init +14 drivers/firmware/smccc/smccc.c
13
> 14 void __init arm_smccc_version_init(u32 version, enum
arm_smccc_conduit conduit)
15 {
16 smccc_version = version;
17 smccc_conduit = conduit;
18 }
19
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^ permalink raw reply
* Re: Possible race while masking IRQ on Allwinner A20
From: Maxime Ripard @ 2020-05-21 7:26 UTC (permalink / raw)
To: Jérôme Pouiller
Cc: Marc Zyngier, Marc Dorval, Thomas Gleixner, Chen-Yu Tsai,
linux-arm-kernel
In-Reply-To: <11042983.UNsANRFJuY@pc-42>
[-- Attachment #1.1: Type: text/plain, Size: 3258 bytes --]
Hi!
Adding Thomas and Marc in Cc.
On Tue, May 19, 2020 at 10:59:26AM +0200, Jérôme Pouiller wrote:
> I have some trouble with integration of the wfx driver[1] on Allwinner
> A20 platform.
>
> The chip WF200 is connected to the SDIO bus. At the beginning, I tried
> to use the IRQ provided by the SDIO bus. However, I have noticed I
> received some IRQs twice. Since the IRQ line is multiplexed with the
> data line, it is not very clear if it is a bug, or if the SDIO device
> has to support that.
>
> The chip WF200 allows to use a dedicated line for the IRQ (aka
> "Out-Of-Band" IRQ). So I have enabled this feature with a edge triggered
> IRQ. However, I missed some IRQs. Indeed, it seems that Allwinner use a
> 32KHz clock to sample the IRQs. It is not fast enough for us. I think it
> explains why we miss some IRQs (using the attribute "input-debounce"[2],
> I tried to enable the 24Mhz clock, but without success).
Without success as in you couldn't make it use the 24MHz clock, or using it
didn't change anything?
But yeah, missing an edge interrupt is bound to happen at some point, and a
level interrupt is going to be more reliable (especially if you can't recover
from a missed interrupt).
> Nevermind, I tried to use a level triggered IRQ (and my request is on
> this part). As you can see in the wfx driver (in bus_sdio.c and bh.c),
> I use a threaded IRQ for that. Unfortunately, I receive some IRQs twice.
> I traced the problem, I get:
>
> QSGRenderThread-981 [000] d.h. 247.485524: irq_handler_entry: irq=80 name=wfx
> QSGRenderThread-981 [000] d.h. 247.485547: irq_handler_exit: irq=80 ret=handled
> QSGRenderThread-981 [000] d.h. 247.485600: irq_handler_entry: irq=80 name=wfx
> QSGRenderThread-981 [000] d.h. 247.485606: irq_handler_exit: irq=80 ret=handled
> irq/80-wfx-260 [001] .... 247.485828: io_read32: CONTROL: 0000f046
> irq/80-wfx-260 [001] .... 247.486072: io_read32: CONTROL: 0000f046
> kworker/1:1H-116 [001] .... 247.486214: io_read: QUEUE: 8b 00 84 18 00 00 00 00 01 00 15 82 2b 48 01 1e 88 42 30 00 08 6b d7 c3 53 e0 28 80 88 67 32 af ... (192 bytes)
> kworker/1:1H-116 [001] .... 247.493097: io_read: QUEUE: 00 00 00 00 00 00 00 00 06 06 00 6a 3f 95 00 60 00 00 00 00 08 62 00 00 01 00 5e 00 00 07 28 80 ... (192 bytes)
> [...]
>
> On this trace, we can see:
> - the hard IRQ handler
> - the IRQ acknowledge from the thread irq/80-wfx-260
> - the access to the data from kworker/1:1H-116
>
> As far as I understand, the first call to the IRQ handler (at
> 247.485524) should mask the IRQ 80. So, the second IRQ (at 247.485600)
> should not happen and the thread irq/80 should be triggered only once.
>
> Do you have any idea of what is going wrong with this IRQ?
That's pretty weird indeed. My first guess was that you weren't using
IRQF_ONESHOT, but it looks like you are. My next lead would be to see if the
mask / unmask hooks in the pinctrl driver are properly called (and actually do
what they are supposed to do). I'm not sure we have any in-tree user of a
threaded IRQ attached to the pinctrl driver, so it might have been broken for
quite some time.
Maxime
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^ permalink raw reply
* Re: [PATCH v2 1/3] ARM: pxa: remove Compulab pxa2xx boards
From: Arnd Bergmann @ 2020-05-21 7:26 UTC (permalink / raw)
To: Mike Rapoport
Cc: linux-mtd, Boris Brezillon, Robert Jarzmik, Linux ARM,
Miquel Raynal
In-Reply-To: <20200521071213.GI1118872@kernel.org>
On Thu, May 21, 2020 at 9:12 AM Mike Rapoport <rppt@kernel.org> wrote:
>
> On Wed, May 20, 2020 at 05:21:51PM +0200, Arnd Bergmann wrote:
> > On Wed, May 20, 2020 at 12:21 PM Robert Jarzmik <robert.jarzmik@free.fr> wrote:
> > >
> > > As these boards have no more users nor testers, and patching them has
> > > become a burden, be that because of the PCI part or the MTD NAND
> > > support, let's remove them.
> > >
> > > The cm-x300 will for now remain and represent Compulab boards at its
> > > best in the PXA department.
>
> I think this series missed the cm-x270 NAND driver, so this could be
> PATCH 4/3 (not even compile tested).
>
> From 56a11987f82ef8b32b25dfc17b849f9bbbf03e4d Mon Sep 17 00:00:00 2001
> From: Mike Rapoport <rppt@linux.ibm.com>
> Date: Thu, 21 May 2020 10:09:47 +0300
> Subject: [PATCH] mtd: rawnand: remove CM-X270 NAND driver
>
> The cm-x270 board have been removed and theres is no point to keep this
> driver.
>
> Signed-off-by: Mike Rapoport <rppt@linux.ibm.com>
Thanks! Removing that driver was actually how the discussion started,
so we definitely want to do that. Boris earlier patch "mtd: rawnand: Get
rid of the cmx270 driver" did it by changing the board file, now your
patch is the right thing to do, and we should remember to do the same
for mbxfb.
Arnd
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^ permalink raw reply
* Re: [PATCH v2 1/3] ARM: pxa: remove Compulab pxa2xx boards
From: Mike Rapoport @ 2020-05-21 7:12 UTC (permalink / raw)
To: Arnd Bergmann
Cc: linux-mtd, Boris Brezillon, Robert Jarzmik, Linux ARM,
Miquel Raynal
In-Reply-To: <CAK8P3a2+auSWBROZR-hobM_qSWtKiG1DRYP3Y7uvbCy_ZLy+gg@mail.gmail.com>
On Wed, May 20, 2020 at 05:21:51PM +0200, Arnd Bergmann wrote:
> On Wed, May 20, 2020 at 12:21 PM Robert Jarzmik <robert.jarzmik@free.fr> wrote:
> >
> > As these boards have no more users nor testers, and patching them has
> > become a burden, be that because of the PCI part or the MTD NAND
> > support, let's remove them.
> >
> > The cm-x300 will for now remain and represent Compulab boards at its
> > best in the PXA department.
I think this series missed the cm-x270 NAND driver, so this could be
PATCH 4/3 (not even compile tested).
From 56a11987f82ef8b32b25dfc17b849f9bbbf03e4d Mon Sep 17 00:00:00 2001
From: Mike Rapoport <rppt@linux.ibm.com>
Date: Thu, 21 May 2020 10:09:47 +0300
Subject: [PATCH] mtd: rawnand: remove CM-X270 NAND driver
The cm-x270 board have been removed and theres is no point to keep this
driver.
Signed-off-by: Mike Rapoport <rppt@linux.ibm.com>
---
drivers/mtd/nand/raw/Kconfig | 4 -
drivers/mtd/nand/raw/Makefile | 1 -
drivers/mtd/nand/raw/cmx270_nand.c | 236 -----------------------------
3 files changed, 241 deletions(-)
delete mode 100644 drivers/mtd/nand/raw/cmx270_nand.c
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index a80a46bb5b8b..9b08a58ae88e 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -213,10 +213,6 @@ config MTD_NAND_MLC_LPC32XX
Please check the actual NAND chip connected and its support
by the MLC NAND controller.
-config MTD_NAND_CM_X270
- tristate "CM-X270 modules NAND controller"
- depends on MACH_ARMCORE
-
config MTD_NAND_PASEMI
tristate "PA Semi PWRficient NAND controller"
depends on PPC_PASEMI
diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile
index 2d136b158fb7..a817052286c7 100644
--- a/drivers/mtd/nand/raw/Makefile
+++ b/drivers/mtd/nand/raw/Makefile
@@ -25,7 +25,6 @@ obj-$(CONFIG_MTD_NAND_GPIO) += gpio.o
omap2_nand-objs := omap2.o
obj-$(CONFIG_MTD_NAND_OMAP2) += omap2_nand.o
obj-$(CONFIG_MTD_NAND_OMAP_BCH_BUILD) += omap_elm.o
-obj-$(CONFIG_MTD_NAND_CM_X270) += cmx270_nand.o
obj-$(CONFIG_MTD_NAND_MARVELL) += marvell_nand.o
obj-$(CONFIG_MTD_NAND_TMIO) += tmio_nand.o
obj-$(CONFIG_MTD_NAND_PLATFORM) += plat_nand.o
diff --git a/drivers/mtd/nand/raw/cmx270_nand.c b/drivers/mtd/nand/raw/cmx270_nand.c
deleted file mode 100644
index 045b6175ae79..000000000000
--- a/drivers/mtd/nand/raw/cmx270_nand.c
+++ /dev/null
@@ -1,236 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2006 Compulab, Ltd.
- * Mike Rapoport <mike@compulab.co.il>
- *
- * Derived from drivers/mtd/nand/h1910.c (removed in v3.10)
- * Copyright (C) 2002 Marius Gröger (mag@sysgo.de)
- * Copyright (c) 2001 Thomas Gleixner (gleixner@autronix.de)
- *
- * Overview:
- * This is a device driver for the NAND flash device found on the
- * CM-X270 board.
- */
-
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/partitions.h>
-#include <linux/slab.h>
-#include <linux/gpio.h>
-#include <linux/module.h>
-
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/mach-types.h>
-
-#include <mach/pxa2xx-regs.h>
-
-#define GPIO_NAND_CS (11)
-#define GPIO_NAND_RB (89)
-
-/* MTD structure for CM-X270 board */
-static struct mtd_info *cmx270_nand_mtd;
-
-/* remaped IO address of the device */
-static void __iomem *cmx270_nand_io;
-
-/*
- * Define static partitions for flash device
- */
-static const struct mtd_partition partition_info[] = {
- [0] = {
- .name = "cmx270-0",
- .offset = 0,
- .size = MTDPART_SIZ_FULL
- }
-};
-#define NUM_PARTITIONS (ARRAY_SIZE(partition_info))
-
-static u_char cmx270_read_byte(struct nand_chip *this)
-{
- return (readl(this->legacy.IO_ADDR_R) >> 16);
-}
-
-static void cmx270_write_buf(struct nand_chip *this, const u_char *buf,
- int len)
-{
- int i;
-
- for (i=0; i<len; i++)
- writel((*buf++ << 16), this->legacy.IO_ADDR_W);
-}
-
-static void cmx270_read_buf(struct nand_chip *this, u_char *buf, int len)
-{
- int i;
-
- for (i=0; i<len; i++)
- *buf++ = readl(this->legacy.IO_ADDR_R) >> 16;
-}
-
-static inline void nand_cs_on(void)
-{
- gpio_set_value(GPIO_NAND_CS, 0);
-}
-
-static void nand_cs_off(void)
-{
- dsb();
-
- gpio_set_value(GPIO_NAND_CS, 1);
-}
-
-/*
- * hardware specific access to control-lines
- */
-static void cmx270_hwcontrol(struct nand_chip *this, int dat,
- unsigned int ctrl)
-{
- unsigned int nandaddr = (unsigned int)this->legacy.IO_ADDR_W;
-
- dsb();
-
- if (ctrl & NAND_CTRL_CHANGE) {
- if ( ctrl & NAND_ALE )
- nandaddr |= (1 << 3);
- else
- nandaddr &= ~(1 << 3);
- if ( ctrl & NAND_CLE )
- nandaddr |= (1 << 2);
- else
- nandaddr &= ~(1 << 2);
- if ( ctrl & NAND_NCE )
- nand_cs_on();
- else
- nand_cs_off();
- }
-
- dsb();
- this->legacy.IO_ADDR_W = (void __iomem*)nandaddr;
- if (dat != NAND_CMD_NONE)
- writel((dat << 16), this->legacy.IO_ADDR_W);
-
- dsb();
-}
-
-/*
- * read device ready pin
- */
-static int cmx270_device_ready(struct nand_chip *this)
-{
- dsb();
-
- return (gpio_get_value(GPIO_NAND_RB));
-}
-
-/*
- * Main initialization routine
- */
-static int __init cmx270_init(void)
-{
- struct nand_chip *this;
- int ret;
-
- if (!(machine_is_armcore() && cpu_is_pxa27x()))
- return -ENODEV;
-
- ret = gpio_request(GPIO_NAND_CS, "NAND CS");
- if (ret) {
- pr_warn("CM-X270: failed to request NAND CS gpio\n");
- return ret;
- }
-
- gpio_direction_output(GPIO_NAND_CS, 1);
-
- ret = gpio_request(GPIO_NAND_RB, "NAND R/B");
- if (ret) {
- pr_warn("CM-X270: failed to request NAND R/B gpio\n");
- goto err_gpio_request;
- }
-
- gpio_direction_input(GPIO_NAND_RB);
-
- /* Allocate memory for MTD device structure and private data */
- this = kzalloc(sizeof(struct nand_chip), GFP_KERNEL);
- if (!this) {
- ret = -ENOMEM;
- goto err_kzalloc;
- }
-
- cmx270_nand_io = ioremap(PXA_CS1_PHYS, 12);
- if (!cmx270_nand_io) {
- pr_debug("Unable to ioremap NAND device\n");
- ret = -EINVAL;
- goto err_ioremap;
- }
-
- cmx270_nand_mtd = nand_to_mtd(this);
-
- /* Link the private data with the MTD structure */
- cmx270_nand_mtd->owner = THIS_MODULE;
-
- /* insert callbacks */
- this->legacy.IO_ADDR_R = cmx270_nand_io;
- this->legacy.IO_ADDR_W = cmx270_nand_io;
- this->legacy.cmd_ctrl = cmx270_hwcontrol;
- this->legacy.dev_ready = cmx270_device_ready;
-
- /* 15 us command delay time */
- this->legacy.chip_delay = 20;
- this->ecc.mode = NAND_ECC_SOFT;
- this->ecc.algo = NAND_ECC_HAMMING;
-
- /* read/write functions */
- this->legacy.read_byte = cmx270_read_byte;
- this->legacy.read_buf = cmx270_read_buf;
- this->legacy.write_buf = cmx270_write_buf;
-
- /* Scan to find existence of the device */
- ret = nand_scan(this, 1);
- if (ret) {
- pr_notice("No NAND device\n");
- goto err_scan;
- }
-
- /* Register the partitions */
- ret = mtd_device_register(cmx270_nand_mtd, partition_info,
- NUM_PARTITIONS);
- if (ret)
- goto err_scan;
-
- /* Return happy */
- return 0;
-
-err_scan:
- iounmap(cmx270_nand_io);
-err_ioremap:
- kfree(this);
-err_kzalloc:
- gpio_free(GPIO_NAND_RB);
-err_gpio_request:
- gpio_free(GPIO_NAND_CS);
-
- return ret;
-
-}
-module_init(cmx270_init);
-
-/*
- * Clean up routine
- */
-static void __exit cmx270_cleanup(void)
-{
- /* Release resources, unregister device */
- nand_release(mtd_to_nand(cmx270_nand_mtd));
-
- gpio_free(GPIO_NAND_RB);
- gpio_free(GPIO_NAND_CS);
-
- iounmap(cmx270_nand_io);
-
- kfree(mtd_to_nand(cmx270_nand_mtd));
-}
-module_exit(cmx270_cleanup);
-
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR("Mike Rapoport <mike@compulab.co.il>");
-MODULE_DESCRIPTION("NAND flash driver for Compulab CM-X270 Module");
--
2.25.2
> > Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
>
> Acked-by: Arnd Bergmann <arnd@arndb.de>
>
> Should we take the series through the soc tree? If so, please
> send them to soc@kernel.org if there are no objections;
> or along with other patches you might have in the pull requests.
>
> Arnd
--
Sincerely yours,
Mike.
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^ permalink raw reply related
* [PATCH] i2c: stm32f7: Fix runtime PM imbalance in stm32f7_i2c_unreg_slave
From: Dinghao Liu @ 2020-05-21 7:08 UTC (permalink / raw)
To: dinghao.liu, kjlu
Cc: Alexandre Torgue, linux-kernel, Pierre-Yves MORDRET, linux-i2c,
Maxime Coquelin, linux-stm32, linux-arm-kernel
pm_runtime_get_sync() increments the runtime PM usage counter even
the call returns an error code. Thus a pairing decrement is needed
on the error handling path to keep the counter balanced.
Signed-off-by: Dinghao Liu <dinghao.liu@zju.edu.cn>
---
drivers/i2c/busses/i2c-stm32f7.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/i2c/busses/i2c-stm32f7.c b/drivers/i2c/busses/i2c-stm32f7.c
index 330ffed011e0..6f5f0fa68385 100644
--- a/drivers/i2c/busses/i2c-stm32f7.c
+++ b/drivers/i2c/busses/i2c-stm32f7.c
@@ -1837,8 +1837,10 @@ static int stm32f7_i2c_unreg_slave(struct i2c_client *slave)
WARN_ON(!i2c_dev->slave[id]);
ret = pm_runtime_get_sync(i2c_dev->dev);
- if (ret < 0)
+ if (ret < 0) {
+ pm_runtime_put_autosuspend(i2c_dev->dev);
return ret;
+ }
if (id == 0) {
mask = STM32F7_I2C_OAR1_OA1EN;
--
2.17.1
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^ permalink raw reply related
* Re: [PATCH v4 7/7] firmware: smccc: Add ARCH_SOC_ID support
From: Sudeep Holla @ 2020-05-21 7:07 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Mark Rutland, Lorenzo Pieralisi, Catalin Marinas,
linux-kernel@vger.kernel.org, Steven Price, harb, Sudeep Holla,
Will Deacon, Linux ARM
In-Reply-To: <CAK8P3a3bOEL5wYFc1Fjg1vAT51NumzO0iUSroHQLSUt8WpZL7g@mail.gmail.com>
On Wed, May 20, 2020 at 11:51:47PM +0200, Arnd Bergmann wrote:
> On Mon, May 18, 2020 at 1:55 PM Sudeep Holla <sudeep.holla@arm.com> wrote:
> >
> > On Mon, May 18, 2020 at 11:30:21AM +0200, Arnd Bergmann wrote:
> > > On Mon, May 18, 2020 at 11:12 AM Sudeep Holla <sudeep.holla@arm.com> wrote:
> > >
> > > > +static ssize_t
> > > > +jep106_cont_bank_code_show(struct device *dev, struct device_attribute *attr,
> > > > + char *buf)
> > > > +{
> > > > + return sprintf(buf, "0x%02x\n", JEP106_BANK_CONT_CODE(soc_id_version));
> > > > +}
> > > > +
> > > > +static DEVICE_ATTR_RO(jep106_cont_bank_code);
> > > > +
> > > > +static ssize_t
> > > > +jep106_identification_code_show(struct device *dev,
> > > > + struct device_attribute *attr, char *buf)
> > > > +{
> > > > + return sprintf(buf, "0x%02x\n", JEP106_ID_CODE(soc_id_version));
> > > > +}
> > >
> > > I think we should try hard to avoid nonstandard attributes for the soc device.
> > >
> >
> > I agree with that in general but this is bit different for below mentioned
> > reason.
> >
> > > Did you run into a problem with finding one of the existing attributes
> > > that can be used to hold the fields?
> > >
> >
> > Not really! The 2 JEP106 codes can be used to derive the manufacturer which
> > could match one of the existing attributes. However doing so might require
> > importing the huge JEP106 list as it needs to be maintained and updated
> > in the kernel. Also that approach will have the compatibility issue and
> > that is the reason for introducing these attributes representing raw
> > values for userspace.
>
> I was thinking they codes could just be part of the normal strings rather
> than get translated. Can you give an example what they would look like
> with your current code?
>
Sure. Couple of example:
Cont Code Identifier Manufacturer
0 0x1 AMD
0 0x0e Freescale (Motorola)
4 0x3b ARM
I initially thought of value like "jep106-0-1" for AMD "jep-4-3b" for
ARM,..etc for the standard attribute family or machine. But I was not
convinced fully on that approach as it will be deviation from normal
values in those attributes. Further this represents the vendor name
rather than the family or machine.
> If you think they should be standard attributes, how about adding them
> to the default list, and hardcoding them in the other soc device drivers
> based on the information we have available there?
>
That may be possible, I can take a look at the existing drivers and
check if that is feasible(which I think should be). Thanks for that
suggestion.
--
Regards,
Sudeep
[1] https://github.com/skottler/memtest86/blob/master/jedec_id.h
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^ permalink raw reply
* Re: [PATCH v4 0/7] firmware: smccc: Add basic SMCCC v1.2 + ARCH_SOC_ID support
From: Sudeep Holla @ 2020-05-21 7:07 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Mark Rutland, Lorenzo Pieralisi, Catalin Marinas,
linux-kernel@vger.kernel.org, Steven Price, harb, Sudeep Holla,
Will Deacon, Linux ARM
In-Reply-To: <CAK8P3a0bx2eOFSqM7ihNkJBWU_KKSh0vGJZZdvpkH=1nppingw@mail.gmail.com>
On Wed, May 20, 2020 at 11:54:16PM +0200, Arnd Bergmann wrote:
> On Wed, May 20, 2020 at 11:29 PM Will Deacon <will@kernel.org> wrote:
> >
> > On Mon, 18 May 2020 10:12:15 +0100, Sudeep Holla wrote:
> > > This patch series adds support for SMCCCv1.2 ARCH_SOC_ID.
> > > This doesn't add other changes added in SMCCC v1.2 yet. They will
> > > follow these soon along with its first user SPCI/PSA-FF.
> > >
> > > This is tested using upstream TF-A + the patch[3] fixing the original
> > > implementation there.
> > >
> > > [...]
> >
> > Applied to arm64 (for-next/smccc), thanks!
> >
> > [1/7] firmware: smccc: Add HAVE_ARM_SMCCC_DISCOVERY to identify SMCCC v1.1 and above
> > https://git.kernel.org/arm64/c/e5bfb21d98b6
> > [2/7] firmware: smccc: Update link to latest SMCCC specification
> > https://git.kernel.org/arm64/c/15c704ab6244
> > [3/7] firmware: smccc: Add the definition for SMCCCv1.2 version/error codes
> > https://git.kernel.org/arm64/c/0441bfe7f00a
> > [4/7] firmware: smccc: Drop smccc_version enum and use ARM_SMCCC_VERSION_1_x instead
> > https://git.kernel.org/arm64/c/ad5a57dfe434
> > [5/7] firmware: smccc: Refactor SMCCC specific bits into separate file
> > https://git.kernel.org/arm64/c/f2ae97062a48
> > [6/7] firmware: smccc: Add function to fetch SMCCC version
> > https://git.kernel.org/arm64/c/a4fb17465182
> > [7/7] firmware: smccc: Add ARCH_SOC_ID support
> > https://git.kernel.org/arm64/c/ce6488f0ce09
> >
> > Arnd -- Sudeep's reply to you about the sysfs groups seemed reasonable to me,
> > but please shout if you'd rather I dropped this in order to pursue an
> > alternative approach.
>
> I missed the reply earlier, thanks for pointing me to it again.
>
> I'm not entirely convinced, but don't revert it for now because of that,
> I assume we can find a solution.
>
I liked your idea of making this generic and hardcode values if required
for other drivers. I will take a look at that/
> However, please have a look at the build failure report for patch 5
> and fix it if you can see what went wrong.
>
Any pointers for that failure ? I seem to have missed them. I pushed
branch couple of times to my tree but got build success both times.
Any specific config or compilers ?
--
Regards,
Sudeep
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^ permalink raw reply
* [PATCH] i2c: stm32f7: Fix runtime PM imbalance in stm32f7_i2c_reg_slave
From: Dinghao Liu @ 2020-05-21 7:05 UTC (permalink / raw)
To: dinghao.liu, kjlu
Cc: Alexandre Torgue, linux-kernel, Pierre-Yves MORDRET, linux-i2c,
Maxime Coquelin, linux-stm32, linux-arm-kernel
pm_runtime_get_sync() increments the runtime PM usage counter even
the call returns an error code. Thus a pairing decrement is needed
on the error handling path to keep the counter balanced.
Signed-off-by: Dinghao Liu <dinghao.liu@zju.edu.cn>
---
drivers/i2c/busses/i2c-stm32f7.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/i2c/busses/i2c-stm32f7.c b/drivers/i2c/busses/i2c-stm32f7.c
index 330ffed011e0..602cf35649c8 100644
--- a/drivers/i2c/busses/i2c-stm32f7.c
+++ b/drivers/i2c/busses/i2c-stm32f7.c
@@ -1767,8 +1767,10 @@ static int stm32f7_i2c_reg_slave(struct i2c_client *slave)
return ret;
ret = pm_runtime_get_sync(dev);
- if (ret < 0)
+ if (ret < 0) {
+ pm_runtime_put_autosuspend(dev);
return ret;
+ }
if (!stm32f7_i2c_is_slave_registered(i2c_dev))
stm32f7_i2c_enable_wakeup(i2c_dev, true);
--
2.17.1
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* [PATCH v2 2/2] arm64: dts: imx8mn-ddr4-evk: correct ldo1/ldo2 voltage range
From: Robin Gong @ 2020-05-21 14:17 UTC (permalink / raw)
To: robh+dt, shawnguo, s.hauer, festevam, anson.huang, peng.fan
Cc: devicetree, linux-imx, linux-arm-kernel, kernel, linux-kernel
In-Reply-To: <1590070674-23027-1-git-send-email-yibin.gong@nxp.com>
Correct ldo1 voltage range from wrong high group(3.0v~3.3v) to low group
(1.6v~1.9v) because the ldo1 should be 1.8v. Actually, two voltage groups
have been supported at bd718x7-regulator driver, hence, just corrrect the
voltage range to 1.6v~3.3v. For ldo2@0.8v, correct voltage range too.
Otherwise, ldo1 would be kept @3.0v and ldo2@0.9v which violate i.mx8mn
datasheet as the below warning log in kernel:
[ 0.995524] LDO1: Bringing 1800000uV into 3000000-3000000uV
[ 0.999196] LDO2: Bringing 800000uV into 900000-900000uV
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
index d07e0e6..a1e5483 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
@@ -113,7 +113,7 @@
ldo1_reg: LDO1 {
regulator-name = "LDO1";
- regulator-min-microvolt = <3000000>;
+ regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
@@ -121,7 +121,7 @@
ldo2_reg: LDO2 {
regulator-name = "LDO2";
- regulator-min-microvolt = <900000>;
+ regulator-min-microvolt = <800000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
regulator-always-on;
--
2.7.4
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^ permalink raw reply related
* [PATCH v2 1/2] arm64: dts: imx8mm-evk: correct ldo1/ldo2 voltage range
From: Robin Gong @ 2020-05-21 14:17 UTC (permalink / raw)
To: robh+dt, shawnguo, s.hauer, festevam, anson.huang, peng.fan
Cc: devicetree, linux-imx, linux-arm-kernel, kernel, linux-kernel
Correct ldo1 voltage range from wrong high group(3.0v~3.3v) to low group
(1.6v~1.9v) because the ldo1 should be 1.8v. Actually, two voltage groups
have been supported at bd718x7-regulator driver, hence, just corrrect the
voltage range to 1.6v~3.3v. For ldo2@0.8v, correct voltage range too.
Otherwise, ldo1 would be kept @3.0v and ldo2@0.9v which violate i.mx8mm
datasheet as the below warning log in kernel:
[ 0.995524] LDO1: Bringing 1800000uV into 3000000-3000000uV
[ 0.999196] LDO2: Bringing 800000uV into 900000-900000uV
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
index e5ec832..0f1d7f8 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
@@ -208,7 +208,7 @@
ldo1_reg: LDO1 {
regulator-name = "LDO1";
- regulator-min-microvolt = <3000000>;
+ regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
@@ -216,7 +216,7 @@
ldo2_reg: LDO2 {
regulator-name = "LDO2";
- regulator-min-microvolt = <900000>;
+ regulator-min-microvolt = <800000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
regulator-always-on;
--
2.7.4
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^ permalink raw reply related
* RE: [PATCH v1 2/2] arm64: dts: imx8mn-ddr4-evk: correct ldo1/ldo2 voltage range
From: Robin Gong @ 2020-05-21 6:05 UTC (permalink / raw)
To: Peng Fan, robh+dt@kernel.org, shawnguo@kernel.org,
s.hauer@pengutronix.de, festevam@gmail.com, Anson Huang
Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
dl-linux-imx, kernel@pengutronix.de, linux-kernel@vger.kernel.org
In-Reply-To: <DB6PR0402MB2760907E5DE55EBA3BE38D9B88B70@DB6PR0402MB2760.eurprd04.prod.outlook.com>
2020/05/21 14:02 Peng Fan <peng.fan@nxp.com> wrote:
> > Subject: [PATCH v1 2/2] arm64: dts: imx8mn-ddr4-evk: correct ldo1/ldo2
> > voltage range
> >
> > Correct ldo1 voltage range from wrong high group(3.0v~3.3v) to low
> > group
> > (1.6v~1.9v) because the ldo1 should be 1.8v. Actually, two voltage
> > groups have been supported at bd718x7-regulator driver, hence, just
> > corrrect the voltage range to 1.6v~3.3v. For ldo2@0.8v, correct voltage range
> too.
> > Otherwise, ldo1 would be kept @3.0v and ldo2@0.9v which violate
> > i.mx8mm datasheet as the below warning log in kernel:
> >
> > [ 0.995524] LDO1: Bringing 1800000uV into 3000000-3000000uV
> > [ 0.999196] LDO2: Bringing 800000uV into 900000-900000uV
> >
> > Signed-off-by: Robin Gong <yibin.gong@nxp.com>
> > ---
> > arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts | 4 ++--
> > arch/arm64/boot/dts/freescale/imx8mn-evk.dts | 9 +++++++++
> > 2 files changed, 11 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
> > b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
> > index d07e0e6..a1e5483 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
> > +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
> > @@ -113,7 +113,7 @@
> >
> > ldo1_reg: LDO1 {
> > regulator-name = "LDO1";
> > - regulator-min-microvolt = <3000000>;
> > + regulator-min-microvolt = <1600000>;
> > regulator-max-microvolt = <3300000>;
> > regulator-boot-on;
> > regulator-always-on;
> > @@ -121,7 +121,7 @@
> >
> > ldo2_reg: LDO2 {
> > regulator-name = "LDO2";
> > - regulator-min-microvolt = <900000>;
> > + regulator-min-microvolt = <800000>;
> > regulator-max-microvolt = <900000>;
> > regulator-boot-on;
> > regulator-always-on;
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts
> > b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts
> > index 61f3519..117ff4b 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts
> > +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts
> > @@ -13,6 +13,15 @@
> > compatible = "fsl,imx8mn-evk", "fsl,imx8mn"; };
> >
> > +&ecspi1 {
> > + status = "okay";
> > +spidev0: spi@0 {
> > + compatible = "ge,achc";
> > + reg = <0>;
> > + spi-max-frequency = <1000000>;
> > + };
> > +};
> > +
>
> This was added by mistake?
Sorry, will send out v2.
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* RE: [PATCH v1 2/2] arm64: dts: imx8mn-ddr4-evk: correct ldo1/ldo2 voltage range
From: Peng Fan @ 2020-05-21 6:02 UTC (permalink / raw)
To: Robin Gong, robh+dt@kernel.org, shawnguo@kernel.org,
s.hauer@pengutronix.de, festevam@gmail.com, Anson Huang
Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
dl-linux-imx, kernel@pengutronix.de, linux-kernel@vger.kernel.org
In-Reply-To: <1590060368-2282-2-git-send-email-yibin.gong@nxp.com>
> Subject: [PATCH v1 2/2] arm64: dts: imx8mn-ddr4-evk: correct ldo1/ldo2
> voltage range
>
> Correct ldo1 voltage range from wrong high group(3.0v~3.3v) to low group
> (1.6v~1.9v) because the ldo1 should be 1.8v. Actually, two voltage groups
> have been supported at bd718x7-regulator driver, hence, just corrrect the
> voltage range to 1.6v~3.3v. For ldo2@0.8v, correct voltage range too.
> Otherwise, ldo1 would be kept @3.0v and ldo2@0.9v which violate i.mx8mm
> datasheet as the below warning log in kernel:
>
> [ 0.995524] LDO1: Bringing 1800000uV into 3000000-3000000uV
> [ 0.999196] LDO2: Bringing 800000uV into 900000-900000uV
>
> Signed-off-by: Robin Gong <yibin.gong@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts | 4 ++--
> arch/arm64/boot/dts/freescale/imx8mn-evk.dts | 9 +++++++++
> 2 files changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
> b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
> index d07e0e6..a1e5483 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
> @@ -113,7 +113,7 @@
>
> ldo1_reg: LDO1 {
> regulator-name = "LDO1";
> - regulator-min-microvolt = <3000000>;
> + regulator-min-microvolt = <1600000>;
> regulator-max-microvolt = <3300000>;
> regulator-boot-on;
> regulator-always-on;
> @@ -121,7 +121,7 @@
>
> ldo2_reg: LDO2 {
> regulator-name = "LDO2";
> - regulator-min-microvolt = <900000>;
> + regulator-min-microvolt = <800000>;
> regulator-max-microvolt = <900000>;
> regulator-boot-on;
> regulator-always-on;
> diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts
> b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts
> index 61f3519..117ff4b 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts
> @@ -13,6 +13,15 @@
> compatible = "fsl,imx8mn-evk", "fsl,imx8mn"; };
>
> +&ecspi1 {
> + status = "okay";
> +spidev0: spi@0 {
> + compatible = "ge,achc";
> + reg = <0>;
> + spi-max-frequency = <1000000>;
> + };
> +};
> +
This was added by mistake?
Regards,
Peng.
> &A53_0 {
> /delete-property/operating-points-v2;
> };
> --
> 2.7.4
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^ permalink raw reply
* RE: [PATCH 2/2] perf/imx_ddr: Add stop counter support for i.MX8MP
From: Joakim Zhang @ 2020-05-21 4:57 UTC (permalink / raw)
To: Will Deacon
Cc: mark.rutland@arm.com, robin.murphy@arm.com, dl-linux-imx,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <20200520075140.GB23818@willie-the-truck>
> -----Original Message-----
> From: Will Deacon <will@kernel.org>
> Sent: 2020年5月20日 15:52
> To: Joakim Zhang <qiangqing.zhang@nxp.com>
> Cc: mark.rutland@arm.com; robin.murphy@arm.com; dl-linux-imx
> <linux-imx@nxp.com>; linux-arm-kernel@lists.infradead.org
> Subject: Re: [PATCH 2/2] perf/imx_ddr: Add stop counter support for i.MX8MP
>
> On Thu, Apr 16, 2020 at 09:51:13AM +0000, Joakim Zhang wrote:
> > Any comments about this issue? Thanks a lot!
>
> You didn't really answer any of my questions, so I don't really know what to do
> with this.
>
> - The locking appears to be broken. Your solution was to remove it
> entirely.
>
> - It appears to be a user visible change and you haven't explained how it
> continues to work with old userspace
>
> - Perf core is not aware of you stopping counters and you haven't said why
> that's not an issue.
>
> While these issues are outstanding, I cannot merge the patch. Sorry.
Hi Will,
You are really kind. Sorry for that, sometimes I am not quite understand what you want. I send out this patch, just want to talk with you to find a better solution, you could provide profession opinion.
Actually new SoC has a hardware change:
Old SoC:
Counter0 is a special counter, only count cycles. Counter1-3 are event counters. When counter0 overflow, it will lock all counters and generate an interrupt. In ddr_perf_irq_handler(), disable counter0 then all counter1-3 will stop at the same time, update all counters' count, then enable counter0 that all counters would count again. You can see that when enable counter0 it would clear overflow bit, but counter1-3 are free-running, need not clear it. Do/while() from ddr_perf_event_update() can handle counter1-3 overflow case.
MX8MP:
Almost is same with old SoC, the only different is that, counter1-3 are not free-running now. Like counter0, when counter1-3 are overflow, they would stop counting unless clear their overflow bit. Counter0 overflow occurs at least 4 times as often as other counters, so I want to re-enable counter1-3 then they can re-count again, to ensure that counter1-3 will not lose data. The key is that I need clear counter1-3 in counter0 irq handler.
The count updating would happen at irq handler or perf core(read callback). I add a spinlock to avoid updating counter1-3 while clearing counter1-3, but I am not sure if it needs. Looking forward to your feedbacks, please point out my mistakes. Thanks a lot.
Best Regards,
Joakim Zhang
> Will
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^ permalink raw reply
* Re: [PATCH 2/6] soc: ti: omap-prm: Add basic power domain support
From: kbuild test robot @ 2020-05-21 4:53 UTC (permalink / raw)
To: Tony Lindgren, linux-omap
Cc: Rob Herring, kbuild-all, devicetree, linux-kernel,
Andrew F . Davis, Tero Kristo, Santosh Shilimkar, Suman Anna,
linux-arm-kernel
In-Reply-To: <20200520211334.61814-3-tony@atomide.com>
[-- Attachment #1: Type: text/plain, Size: 2779 bytes --]
Hi Tony,
I love your patch! Perhaps something to improve:
[auto build test WARNING on omap/for-next]
[also build test WARNING on robh/for-next keystone/next v5.7-rc6 next-20200519]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url: https://github.com/0day-ci/linux/commits/Tony-Lindgren/Add-initial-genpd-support-for-omap-PRM-driver/20200521-063328
base: https://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap.git for-next
config: arm-defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arm
If you fix the issue, kindly add following tag as appropriate
Reported-by: kbuild test robot <lkp@intel.com>
All warnings (new ones prefixed by >>, old ones prefixed by <<):
drivers/soc/ti/omap_prm.c: In function 'omap_prm_domain_detach_dev':
>> drivers/soc/ti/omap_prm.c:347:26: warning: variable 'prmd' set but not used [-Wunused-but-set-variable]
347 | struct omap_prm_domain *prmd;
| ^~~~
At top level:
drivers/soc/ti/omap_prm.c:123:21: warning: 'omap_prm_onoff_noauto' defined but not used [-Wunused-const-variable=]
123 | omap_prm_domain_map omap_prm_onoff_noauto = {
| ^~~~~~~~~~~~~~~~~~~~~
drivers/soc/ti/omap_prm.c:115:21: warning: 'omap_prm_nooff' defined but not used [-Wunused-const-variable=]
115 | omap_prm_domain_map omap_prm_nooff = {
| ^~~~~~~~~~~~~~
drivers/soc/ti/omap_prm.c:107:21: warning: 'omap_prm_noinact' defined but not used [-Wunused-const-variable=]
107 | omap_prm_domain_map omap_prm_noinact = {
| ^~~~~~~~~~~~~~~~
drivers/soc/ti/omap_prm.c:99:21: warning: 'omap_prm_all' defined but not used [-Wunused-const-variable=]
99 | omap_prm_domain_map omap_prm_all = {
| ^~~~~~~~~~~~
vim +/prmd +347 drivers/soc/ti/omap_prm.c
342
343 static void omap_prm_domain_detach_dev(struct generic_pm_domain *domain,
344 struct device *dev)
345 {
346 struct generic_pm_domain_data *genpd_data;
> 347 struct omap_prm_domain *prmd;
348
349 prmd = genpd_to_prm_domain(domain);
350
351 genpd_data = dev_gpd_data(dev);
352 genpd_data->data = NULL;
353 }
354
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 50472 bytes --]
[-- Attachment #3: Type: text/plain, Size: 176 bytes --]
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^ permalink raw reply
* Re: [PATCH][v2] iommu: arm-smmu-v3: Copy SMMU table for kdump kernel
From: Prabhakar Kushwaha @ 2020-05-21 3:58 UTC (permalink / raw)
To: Bjorn Helgaas
Cc: Kuppuswamy Sathyanarayanan, Ganapatrao Prabhakerrao Kulkarni,
Myron Stowe, Vijay Mohan Pandarathil, Marc Zyngier,
Bhupesh Sharma, kexec mailing list, Robin Murphy, linux-pci,
Prabhakar Kushwaha, Will Deacon, linux-arm-kernel
In-Reply-To: <20200519232229.GA395123@bjorn-Precision-5520>
Hi Bjorn,
On Wed, May 20, 2020 at 4:52 AM Bjorn Helgaas <helgaas@kernel.org> wrote:
>
> [+cc Sathy, Vijay, Myron]
>
> On Thu, May 14, 2020 at 12:47:02PM +0530, Prabhakar Kushwaha wrote:
> > On Wed, May 13, 2020 at 3:33 AM Bjorn Helgaas <helgaas@kernel.org> wrote:
> > > On Mon, May 11, 2020 at 07:46:06PM -0700, Prabhakar Kushwaha wrote:
> > > > An SMMU Stream table is created by the primary kernel. This table is
> > > > used by the SMMU to perform address translations for device-originated
> > > > transactions. Any crash (if happened) launches the kdump kernel which
> > > > re-creates the SMMU Stream table. New transactions will be translated
> > > > via this new table..
> > > >
> > > > There are scenarios, where devices are still having old pending
> > > > transactions (configured in the primary kernel). These transactions
> > > > come in-between Stream table creation and device-driver probe.
> > > > As new stream table does not have entry for older transactions,
> > > > it will be aborted by SMMU.
> > > >
> > > > Similar observations were found with PCIe-Intel 82576 Gigabit
> > > > Network card. It sends old Memory Read transaction in kdump kernel.
> > > > Transactions configured for older Stream table entries, that do not
> > > > exist any longer in the new table, will cause a PCIe Completion Abort.
> > >
> > > That sounds like exactly what we want, doesn't it?
> > >
> > > Or do you *want* DMA from the previous kernel to complete? That will
> > > read or scribble on something, but maybe that's not terrible as long
> > > as it's not memory used by the kdump kernel.
> >
> > Yes, Abort should happen. But it should happen in context of driver.
> > But current abort is happening because of SMMU and no driver/pcie
> > setup present at this moment.
>
> I don't understand what you mean by "in context of driver." The whole
> problem is that we can't control *when* the abort happens, so it may
> happen in *any* context. It may happen when a NIC receives a packet
> or at some other unpredictable time.
>
> > Solution of this issue should be at 2 place
> > a) SMMU level: I still believe, this patch has potential to overcome
> > issue till finally driver's probe takeover.
> > b) Device level: Even if something goes wrong. Driver/device should
> > able to recover.
> >
> > > > Returned PCIe completion abort further leads to AER Errors from APEI
> > > > Generic Hardware Error Source (GHES) with completion timeout.
> > > > A network device hang is observed even after continuous
> > > > reset/recovery from driver, Hence device is no more usable.
> > >
> > > The fact that the device is no longer usable is definitely a problem.
> > > But in principle we *should* be able to recover from these errors. If
> > > we could recover and reliably use the device after the error, that
> > > seems like it would be a more robust solution that having to add
> > > special cases in every IOMMU driver.
> > >
> > > If you have details about this sort of error, I'd like to try to fix
> > > it because we want to recover from that sort of error in normal
> > > (non-crash) situations as well.
> > >
> > Completion abort case should be gracefully handled. And device should
> > always remain usable.
> >
> > There are 2 scenario which I am testing with Ethernet card PCIe-Intel
> > 82576 Gigabit Network card.
> >
> > I) Crash testing using kdump root file system: De-facto scenario
> > - kdump file system does not have Ethernet driver
> > - A lot of AER prints [1], making it impossible to work on shell
> > of kdump root file system.
>
> In this case, I think report_error_detected() is deciding that because
> the device has no driver, we can't do anything. The flow is like
> this:
>
> aer_recover_work_func # aer_recover_work
> kfifo_get(aer_recover_ring, entry)
> dev = pci_get_domain_bus_and_slot
> cper_print_aer(dev, ...)
> pci_err("AER: aer_status:")
> pci_err("AER: [14] CmpltTO")
> pci_err("AER: aer_layer=")
> if (AER_NONFATAL)
> pcie_do_recovery(dev, pci_channel_io_normal)
> status = CAN_RECOVER
> pci_walk_bus(report_normal_detected)
> report_error_detected
> if (!dev->driver)
> vote = NO_AER_DRIVER
> pci_info("can't recover (no error_detected callback)")
> *result = merge_result(*, NO_AER_DRIVER)
> # always NO_AER_DRIVER
> status is now NO_AER_DRIVER
>
> So pcie_do_recovery() does not call .report_mmio_enabled() or .slot_reset(),
> and status is not RECOVERED, so it skips .resume().
>
> I don't remember the history there, but if a device has no driver and
> the device generates errors, it seems like we ought to be able to
> reset it.
>
But how to reset the device considering there is no driver.
Hypothetically, this case should be taken care by PCIe subsystem to
perform reset at PCIe level.
> We should be able to field one (or a few) AER errors, reset the
> device, and you should be able to use the shell in the kdump kernel.
>
here kdump shell is usable only problem is a "lot of AER Errors". One
cannot see what they are typing.
> > - Note kdump shell allows to use makedumpfile, vmcore-dmesg applications.
> >
> > II) Crash testing using default root file system: Specific case to
> > test Ethernet driver in second kernel
> > - Default root file system have Ethernet driver
> > - AER error comes even before the driver probe starts.
> > - Driver does reset Ethernet card as part of probe but no success.
> > - AER also tries to recover. but no success. [2]
> > - I also tries to remove AER errors by using "pci=noaer" bootargs
> > and commenting ghes_handle_aer() from GHES driver..
> > than different set of errors come which also never able to recover [3]
> >
Please suggest your view on this case. Here driver is preset.
(driver/net/ethernet/intel/igb/igb_main.c)
In this case AER errors starts even before driver probe starts.
After probe, driver does the device reset with no success and even AER
recovery does not work.
Problem mentioned in case I and II goes away if do pci_reset_function
during enumeration phase of kdump kernel.
can we thought of doing pci_reset_function for all devices in kdump
kernel or device specific quirk.
--pk
> > As per my understanding, possible solutions are
> > - Copy SMMU table i.e. this patch
> > OR
> > - Doing pci_reset_function() during enumeration phase.
> > I also tried clearing "M" bit using pci_clear_master during
> > enumeration but it did not help. Because driver re-set M bit causing
> > same AER error again.
> >
> >
> > -pk
> >
> > ---------------------------------------------------------------------------------------------------------------------------
> > [1] with bootargs having pci=noaer
> >
> > [ 22.494648] {4}[Hardware Error]: Hardware error from APEI Generic
> > Hardware Error Source: 1
> > [ 22.512773] {4}[Hardware Error]: event severity: recoverable
> > [ 22.518419] {4}[Hardware Error]: Error 0, type: recoverable
> > [ 22.544804] {4}[Hardware Error]: section_type: PCIe error
> > [ 22.550363] {4}[Hardware Error]: port_type: 0, PCIe end point
> > [ 22.556268] {4}[Hardware Error]: version: 3.0
> > [ 22.560785] {4}[Hardware Error]: command: 0x0507, status: 0x4010
> > [ 22.576852] {4}[Hardware Error]: device_id: 0000:09:00.1
> > [ 22.582323] {4}[Hardware Error]: slot: 0
> > [ 22.586406] {4}[Hardware Error]: secondary_bus: 0x00
> > [ 22.591530] {4}[Hardware Error]: vendor_id: 0x8086, device_id: 0x10c9
> > [ 22.608900] {4}[Hardware Error]: class_code: 000002
> > [ 22.613938] {4}[Hardware Error]: serial number: 0xff1b4580, 0x90e2baff
> > [ 22.803534] pci 0000:09:00.1: AER: aer_status: 0x00004000,
> > aer_mask: 0x00000000
> > [ 22.810838] pci 0000:09:00.1: AER: [14] CmpltTO (First)
> > [ 22.817613] pci 0000:09:00.1: AER: aer_layer=Transaction Layer,
> > aer_agent=Requester ID
> > [ 22.847374] pci 0000:09:00.1: AER: aer_uncor_severity: 0x00062011
> > [ 22.866161] mpt3sas_cm0: 63 BIT PCI BUS DMA ADDRESSING SUPPORTED,
> > total mem (8153768 kB)
> > [ 22.946178] pci 0000:09:00.0: AER: can't recover (no error_detected callback)
> > [ 22.995142] pci 0000:09:00.1: AER: can't recover (no error_detected callback)
> > [ 23.002300] pcieport 0000:00:09.0: AER: device recovery failed
> > [ 23.027607] pci 0000:09:00.1: AER: aer_status: 0x00004000,
> > aer_mask: 0x00000000
> > [ 23.044109] pci 0000:09:00.1: AER: [14] CmpltTO (First)
> > [ 23.060713] pci 0000:09:00.1: AER: aer_layer=Transaction Layer,
> > aer_agent=Requester ID
> > [ 23.068616] pci 0000:09:00.1: AER: aer_uncor_severity: 0x00062011
> > [ 23.122056] pci 0000:09:00.0: AER: can't recover (no error_detected callback)
> >
> >
> > ----------------------------------------------------------------------------------------------------------------------------
> > [2] Normal bootargs.
> >
> > [ 54.252454] {6}[Hardware Error]: Hardware error from APEI Generic
> > Hardware Error Source: 1
> > [ 54.265827] {6}[Hardware Error]: event severity: recoverable
> > [ 54.271473] {6}[Hardware Error]: Error 0, type: recoverable
> > [ 54.281605] {6}[Hardware Error]: section_type: PCIe error
> > [ 54.287163] {6}[Hardware Error]: port_type: 0, PCIe end point
> > [ 54.296955] {6}[Hardware Error]: version: 3.0
> > [ 54.301471] {6}[Hardware Error]: command: 0x0507, status: 0x4010
> > [ 54.312520] {6}[Hardware Error]: device_id: 0000:09:00.1
> > [ 54.317991] {6}[Hardware Error]: slot: 0
> > [ 54.322074] {6}[Hardware Error]: secondary_bus: 0x00
> > [ 54.327197] {6}[Hardware Error]: vendor_id: 0x8086, device_id: 0x10c9
> > [ 54.333797] {6}[Hardware Error]: class_code: 000002
> > [ 54.351312] {6}[Hardware Error]: serial number: 0xff1b4580, 0x90e2baff
> > [ 54.358001] AER: AER recover: Buffer overflow when recovering AER
> > for 0000:09:00:1
> > [ 54.376852] pcieport 0000:00:09.0: AER: device recovery successful
> > [ 54.383034] igb 0000:09:00.1: AER: aer_status: 0x00004000,
> > aer_mask: 0x00000000
> > [ 54.390348] igb 0000:09:00.1: AER: [14] CmpltTO (First)
> > [ 54.397144] igb 0000:09:00.1: AER: aer_layer=Transaction Layer,
> > aer_agent=Requester ID
> > [ 54.409555] igb 0000:09:00.1: AER: aer_uncor_severity: 0x00062011
> > [ 54.551370] AER: AER recover: Buffer overflow when recovering AER
> > for 0000:09:00:1
> > [ 54.705214] AER: AER recover: Buffer overflow when recovering AER
> > for 0000:09:00:1
> > [ 54.758703] AER: AER recover: Buffer overflow when recovering AER
> > for 0000:09:00:1
> > [ 54.865445] AER: AER recover: Buffer overflow when recovering AER
> > for 0000:09:00:1
> > [ 54.888751] pcieport 0000:00:09.0: AER: device recovery successful
> > [ 54.894933] igb 0000:09:00.1: AER: aer_status: 0x00004000,
> > aer_mask: 0x00000000
> > [ 54.902228] igb 0000:09:00.1: AER: [14] CmpltTO (First)
> > [ 54.916059] igb 0000:09:00.1: AER: aer_layer=Transaction Layer,
> > aer_agent=Requester ID
> > [ 54.923972] igb 0000:09:00.1: AER: aer_uncor_severity: 0x00062011
> > [ 55.057272] AER: AER recover: Buffer overflow when recovering AER
> > for 0000:09:00:1
> > [ 274.571401] AER: AER recover: Buffer overflow when recovering AER
> > for 0000:09:00:1
> > [ 274.686138] AER: AER recover: Buffer overflow when recovering AER
> > for 0000:09:00:1
> > [ 274.786134] AER: AER recover: Buffer overflow when recovering AER
> > for 0000:09:00:1
> > [ 274.886141] AER: AER recover: Buffer overflow when recovering AER
> > for 0000:09:00:1
> > [ 397.792897] Workqueue: events aer_recover_work_func
> > [ 397.797760] Call trace:
> > [ 397.800199] __switch_to+0xcc/0x108
> > [ 397.803675] __schedule+0x2c0/0x700
> > [ 397.807150] schedule+0x58/0xe8
> > [ 397.810283] schedule_preempt_disabled+0x18/0x28
> > [ 397.810788] AER: AER recover: Buffer overflow when recovering AER
> > for 0000:09:00:1
> > [ 397.814887] __mutex_lock.isra.9+0x288/0x5c8
> > [ 397.814890] __mutex_lock_slowpath+0x1c/0x28
> > [ 397.830962] mutex_lock+0x4c/0x68
> > [ 397.834264] report_slot_reset+0x30/0xa0
> > [ 397.838178] pci_walk_bus+0x68/0xc0
> > [ 397.841653] pcie_do_recovery+0xe8/0x248
> > [ 397.845562] aer_recover_work_func+0x100/0x138
> > [ 397.849995] process_one_work+0x1bc/0x458
> > [ 397.853991] worker_thread+0x150/0x500
> > [ 397.857727] kthread+0x114/0x118
> > [ 397.860945] ret_from_fork+0x10/0x18
> > [ 397.864525] INFO: task kworker/223:2:2939 blocked for more than 122 seconds.
> > [ 397.871564] Not tainted 5.7.0-rc3+ #68
> > [ 397.875819] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs"
> > disables this message.
> > [ 397.883638] kworker/223:2 D 0 2939 2 0x00000228
> > [ 397.889121] Workqueue: ipv6_addrconf addrconf_verify_work
> > [ 397.894505] Call trace:
> > [ 397.896940] __switch_to+0xcc/0x108
> > [ 397.900419] __schedule+0x2c0/0x700
> > [ 397.903894] schedule+0x58/0xe8
> > [ 397.907023] schedule_preempt_disabled+0x18/0x28
> > [ 397.910798] AER: AER recover: Buffer overflow when recovering AER
> > for 0000:09:00:1
> > [ 397.911630] __mutex_lock.isra.9+0x288/0x5c8
> > [ 397.923440] __mutex_lock_slowpath+0x1c/0x28
> > [ 397.927696] mutex_lock+0x4c/0x68
> > [ 397.931005] rtnl_lock+0x24/0x30
> > [ 397.934220] addrconf_verify_work+0x18/0x30
> > [ 397.938394] process_one_work+0x1bc/0x458
> > [ 397.942390] worker_thread+0x150/0x500
> > [ 397.946126] kthread+0x114/0x118
> > [ 397.949345] ret_from_fork+0x10/0x18
> >
> > ---------------------------------------------------------------------------------------------------------------------------------
> > [3] with bootargs as pci=noaer and comment ghes_halder_aer() from AER driver
> >
> > [ 69.037035] igb 0000:09:00.1 enp9s0f1: Reset adapter
> > [ 69.348446] {9}[Hardware Error]: Hardware error from APEI Generic
> > Hardware Error Source: 0
> > [ 69.356698] {9}[Hardware Error]: It has been corrected by h/w and
> > requires no further action
> > [ 69.365121] {9}[Hardware Error]: event severity: corrected
> > [ 69.370593] {9}[Hardware Error]: Error 0, type: corrected
> > [ 69.376064] {9}[Hardware Error]: section_type: PCIe error
> > [ 69.381623] {9}[Hardware Error]: port_type: 4, root port
> > [ 69.387094] {9}[Hardware Error]: version: 3.0
> > [ 69.391611] {9}[Hardware Error]: command: 0x0106, status: 0x4010
> > [ 69.397777] {9}[Hardware Error]: device_id: 0000:00:09.0
> > [ 69.403248] {9}[Hardware Error]: slot: 0
> > [ 69.407331] {9}[Hardware Error]: secondary_bus: 0x09
> > [ 69.412455] {9}[Hardware Error]: vendor_id: 0x177d, device_id: 0xaf84
> > [ 69.419055] {9}[Hardware Error]: class_code: 000406
> > [ 69.424093] {9}[Hardware Error]: bridge: secondary_status:
> > 0x6000, control: 0x0002
> > [ 72.118132] igb 0000:09:00.1 enp9s0f1: igb: enp9s0f1 NIC Link is Up
> > 1000 Mbps Full Duplex, Flow Control: RX
> > [ 73.995068] igb 0000:09:00.1: Detected Tx Unit Hang
> > [ 73.995068] Tx Queue <2>
> > [ 73.995068] TDH <0>
> > [ 73.995068] TDT <1>
> > [ 73.995068] next_to_use <1>
> > [ 73.995068] next_to_clean <0>
> > [ 73.995068] buffer_info[next_to_clean]
> > [ 73.995068] time_stamp <ffff9c1a>
> > [ 73.995068] next_to_watch <0000000097d42934>
> > [ 73.995068] jiffies <ffff9cd0>
> > [ 73.995068] desc.status <168000>
> > [ 75.987323] igb 0000:09:00.1: Detected Tx Unit Hang
> > [ 75.987323] Tx Queue <2>
> > [ 75.987323] TDH <0>
> > [ 75.987323] TDT <1>
> > [ 75.987323] next_to_use <1>
> > [ 75.987323] next_to_clean <0>
> > [ 75.987323] buffer_info[next_to_clean]
> > [ 75.987323] time_stamp <ffff9c1a>
> > [ 75.987323] next_to_watch <0000000097d42934>
> > [ 75.987323] jiffies <ffff9d98>
> > [ 75.987323] desc.status <168000>
> > [ 77.952661] {10}[Hardware Error]: Hardware error from APEI Generic
> > Hardware Error Source: 1
> > [ 77.971790] {10}[Hardware Error]: event severity: recoverable
> > [ 77.977522] {10}[Hardware Error]: Error 0, type: recoverable
> > [ 77.983254] {10}[Hardware Error]: section_type: PCIe error
> > [ 77.999930] {10}[Hardware Error]: port_type: 0, PCIe end point
> > [ 78.005922] {10}[Hardware Error]: version: 3.0
> > [ 78.010526] {10}[Hardware Error]: command: 0x0507, status: 0x4010
> > [ 78.016779] {10}[Hardware Error]: device_id: 0000:09:00.1
> > [ 78.033107] {10}[Hardware Error]: slot: 0
> > [ 78.037276] {10}[Hardware Error]: secondary_bus: 0x00
> > [ 78.066253] {10}[Hardware Error]: vendor_id: 0x8086, device_id: 0x10c9
> > [ 78.072940] {10}[Hardware Error]: class_code: 000002
> > [ 78.078064] {10}[Hardware Error]: serial number: 0xff1b4580, 0x90e2baff
> > [ 78.096202] igb 0000:09:00.1: Detected Tx Unit Hang
> > [ 78.096202] Tx Queue <2>
> > [ 78.096202] TDH <0>
> > [ 78.096202] TDT <1>
> > [ 78.096202] next_to_use <1>
> > [ 78.096202] next_to_clean <0>
> > [ 78.096202] buffer_info[next_to_clean]
> > [ 78.096202] time_stamp <ffff9c1a>
> > [ 78.096202] next_to_watch <0000000097d42934>
> > [ 78.096202] jiffies <ffff9e6a>
> > [ 78.096202] desc.status <168000>
> > [ 79.587406] {11}[Hardware Error]: Hardware error from APEI Generic
> > Hardware Error Source: 0
> > [ 79.595744] {11}[Hardware Error]: It has been corrected by h/w and
> > requires no further action
> > [ 79.604254] {11}[Hardware Error]: event severity: corrected
> > [ 79.609813] {11}[Hardware Error]: Error 0, type: corrected
> > [ 79.615371] {11}[Hardware Error]: section_type: PCIe error
> > [ 79.621016] {11}[Hardware Error]: port_type: 4, root port
> > [ 79.626574] {11}[Hardware Error]: version: 3.0
> > [ 79.631177] {11}[Hardware Error]: command: 0x0106, status: 0x4010
> > [ 79.637430] {11}[Hardware Error]: device_id: 0000:00:09.0
> > [ 79.642988] {11}[Hardware Error]: slot: 0
> > [ 79.647157] {11}[Hardware Error]: secondary_bus: 0x09
> > [ 79.652368] {11}[Hardware Error]: vendor_id: 0x177d, device_id: 0xaf84
> > [ 79.659055] {11}[Hardware Error]: class_code: 000406
> > [ 79.664180] {11}[Hardware Error]: bridge: secondary_status:
> > 0x6000, control: 0x0002
> > [ 79.987052] igb 0000:09:00.1: Detected Tx Unit Hang
> > [ 79.987052] Tx Queue <2>
> > [ 79.987052] TDH <0>
> > [ 79.987052] TDT <1>
> > [ 79.987052] next_to_use <1>
> > [ 79.987052] next_to_clean <0>
> > [ 79.987052] buffer_info[next_to_clean]
> > [ 79.987052] time_stamp <ffff9c1a>
> > [ 79.987052] next_to_watch <0000000097d42934>
> > [ 79.987052] jiffies <ffff9f28>
> > [ 79.987052] desc.status <168000>
> > [ 79.987056] igb 0000:09:00.1: Detected Tx Unit Hang
> > [ 79.987056] Tx Queue <3>
> > [ 79.987056] TDH <0>
> > [ 79.987056] TDT <1>
> > [ 79.987056] next_to_use <1>
> > [ 79.987056] next_to_clean <0>
> > [ 79.987056] buffer_info[next_to_clean]
> > [ 79.987056] time_stamp <ffff9e43>
> > [ 79.987056] next_to_watch <000000008da33deb>
> > [ 79.987056] jiffies <ffff9f28>
> > [ 79.987056] desc.status <514000>
> > [ 81.986688] igb 0000:09:00.1 enp9s0f1: Reset adapter
> > [ 81.986842] igb 0000:09:00.1: Detected Tx Unit Hang
> > [ 81.986842] Tx Queue <2>
> > [ 81.986842] TDH <0>
> > [ 81.986842] TDT <1>
> > [ 81.986842] next_to_use <1>
> > [ 81.986842] next_to_clean <0>
> > [ 81.986842] buffer_info[next_to_clean]
> > [ 81.986842] time_stamp <ffff9c1a>
> > [ 81.986842] next_to_watch <0000000097d42934>
> > [ 81.986842] jiffies <ffff9ff0>
> > [ 81.986842] desc.status <168000>
> > [ 81.986844] igb 0000:09:00.1: Detected Tx Unit Hang
> > [ 81.986844] Tx Queue <3>
> > [ 81.986844] TDH <0>
> > [ 81.986844] TDT <1>
> > [ 81.986844] next_to_use <1>
> > [ 81.986844] next_to_clean <0>
> > [ 81.986844] buffer_info[next_to_clean]
> > [ 81.986844] time_stamp <ffff9e43>
> > [ 81.986844] next_to_watch <000000008da33deb>
> > [ 81.986844] jiffies <ffff9ff0>
> > [ 81.986844] desc.status <514000>
> > [ 85.346515] {12}[Hardware Error]: Hardware error from APEI Generic
> > Hardware Error Source: 0
> > [ 85.354854] {12}[Hardware Error]: It has been corrected by h/w and
> > requires no further action
> > [ 85.363365] {12}[Hardware Error]: event severity: corrected
> > [ 85.368924] {12}[Hardware Error]: Error 0, type: corrected
> > [ 85.374483] {12}[Hardware Error]: section_type: PCIe error
> > [ 85.380129] {12}[Hardware Error]: port_type: 0, PCIe end point
> > [ 85.386121] {12}[Hardware Error]: version: 3.0
> > [ 85.390725] {12}[Hardware Error]: command: 0x0507, status: 0x0010
> > [ 85.396980] {12}[Hardware Error]: device_id: 0000:09:00.0
> > [ 85.402540] {12}[Hardware Error]: slot: 0
> > [ 85.406710] {12}[Hardware Error]: secondary_bus: 0x00
> > [ 85.411921] {12}[Hardware Error]: vendor_id: 0x8086, device_id: 0x10c9
> > [ 85.418609] {12}[Hardware Error]: class_code: 000002
> > [ 85.423733] {12}[Hardware Error]: serial number: 0xff1b4580, 0x90e2baff
> > [ 85.826695] igb 0000:09:00.1 enp9s0f1: igb: enp9s0f1 NIC Link is Up
> > 1000 Mbps Full Duplex, Flow Control: RX
> >
> >
> >
> >
> >
> > > > So, If we are in a kdump kernel try to copy SMMU Stream table from
> > > > primary/old kernel to preserve the mappings until the device driver
> > > > takes over.
> > > >
> > > > Signed-off-by: Prabhakar Kushwaha <pkushwaha@marvell.com>
> > > > ---
> > > > Changes for v2: Used memremap in-place of ioremap
> > > >
> > > > V2 patch has been sanity tested.
> > > >
> > > > V1 patch has been tested with
> > > > A) PCIe-Intel 82576 Gigabit Network card in following
> > > > configurations with "no AER error". Each iteration has
> > > > been tested on both Suse kdump rfs And default Centos distro rfs.
> > > >
> > > > 1) with 2 level stream table
> > > > ----------------------------------------------------
> > > > SMMU | Normal Ping | Flood Ping
> > > > -----------------------------------------------------
> > > > Default Operation | 100 times | 10 times
> > > > -----------------------------------------------------
> > > > IOMMU bypass | 41 times | 10 times
> > > > -----------------------------------------------------
> > > >
> > > > 2) with Linear stream table.
> > > > -----------------------------------------------------
> > > > SMMU | Normal Ping | Flood Ping
> > > > ------------------------------------------------------
> > > > Default Operation | 100 times | 10 times
> > > > ------------------------------------------------------
> > > > IOMMU bypass | 55 times | 10 times
> > > > -------------------------------------------------------
> > > >
> > > > B) This patch is also tested with Micron Technology Inc 9200 PRO NVMe
> > > > SSD card with 2 level stream table using "fio" in mixed read/write and
> > > > only read configurations. It is tested for both Default Operation and
> > > > IOMMU bypass mode for minimum 10 iterations across Centos kdump rfs and
> > > > default Centos ditstro rfs.
> > > >
> > > > This patch is not full proof solution. Issue can still come
> > > > from the point device is discovered and driver probe called.
> > > > This patch has reduced window of scenario from "SMMU Stream table
> > > > creation - device-driver" to "device discovery - device-driver".
> > > > Usually, device discovery to device-driver is very small time. So
> > > > the probability is very low.
> > > >
> > > > Note: device-discovery will overwrite existing stream table entries
> > > > with both SMMU stage as by-pass.
> > > >
> > > >
> > > > drivers/iommu/arm-smmu-v3.c | 36 +++++++++++++++++++++++++++++++++++-
> > > > 1 file changed, 35 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
> > > > index 82508730feb7..d492d92c2dd7 100644
> > > > --- a/drivers/iommu/arm-smmu-v3.c
> > > > +++ b/drivers/iommu/arm-smmu-v3.c
> > > > @@ -1847,7 +1847,13 @@ static void arm_smmu_write_strtab_ent(struct arm_smmu_master *master, u32 sid,
> > > > break;
> > > > case STRTAB_STE_0_CFG_S1_TRANS:
> > > > case STRTAB_STE_0_CFG_S2_TRANS:
> > > > - ste_live = true;
> > > > + /*
> > > > + * As kdump kernel copy STE table from previous
> > > > + * kernel. It still may have valid stream table entries.
> > > > + * Forcing entry as false to allow overwrite.
> > > > + */
> > > > + if (!is_kdump_kernel())
> > > > + ste_live = true;
> > > > break;
> > > > case STRTAB_STE_0_CFG_ABORT:
> > > > BUG_ON(!disable_bypass);
> > > > @@ -3264,6 +3270,9 @@ static int arm_smmu_init_l1_strtab(struct arm_smmu_device *smmu)
> > > > return -ENOMEM;
> > > > }
> > > >
> > > > + if (is_kdump_kernel())
> > > > + return 0;
> > > > +
> > > > for (i = 0; i < cfg->num_l1_ents; ++i) {
> > > > arm_smmu_write_strtab_l1_desc(strtab, &cfg->l1_desc[i]);
> > > > strtab += STRTAB_L1_DESC_DWORDS << 3;
> > > > @@ -3272,6 +3281,23 @@ static int arm_smmu_init_l1_strtab(struct arm_smmu_device *smmu)
> > > > return 0;
> > > > }
> > > >
> > > > +static void arm_smmu_copy_table(struct arm_smmu_device *smmu,
> > > > + struct arm_smmu_strtab_cfg *cfg, u32 size)
> > > > +{
> > > > + struct arm_smmu_strtab_cfg rdcfg;
> > > > +
> > > > + rdcfg.strtab_dma = readq_relaxed(smmu->base + ARM_SMMU_STRTAB_BASE);
> > > > + rdcfg.strtab_base_cfg = readq_relaxed(smmu->base
> > > > + + ARM_SMMU_STRTAB_BASE_CFG);
> > > > +
> > > > + rdcfg.strtab_dma &= STRTAB_BASE_ADDR_MASK;
> > > > + rdcfg.strtab = memremap(rdcfg.strtab_dma, size, MEMREMAP_WB);
> > > > +
> > > > + memcpy_fromio(cfg->strtab, rdcfg.strtab, size);
> > > > +
> > > > + cfg->strtab_base_cfg = rdcfg.strtab_base_cfg;
> > > > +}
> > > > +
> > > > static int arm_smmu_init_strtab_2lvl(struct arm_smmu_device *smmu)
> > > > {
> > > > void *strtab;
> > > > @@ -3307,6 +3333,9 @@ static int arm_smmu_init_strtab_2lvl(struct arm_smmu_device *smmu)
> > > > reg |= FIELD_PREP(STRTAB_BASE_CFG_SPLIT, STRTAB_SPLIT);
> > > > cfg->strtab_base_cfg = reg;
> > > >
> > > > + if (is_kdump_kernel())
> > > > + arm_smmu_copy_table(smmu, cfg, l1size);
> > > > +
> > > > return arm_smmu_init_l1_strtab(smmu);
> > > > }
> > > >
> > > > @@ -3334,6 +3363,11 @@ static int arm_smmu_init_strtab_linear(struct arm_smmu_device *smmu)
> > > > reg |= FIELD_PREP(STRTAB_BASE_CFG_LOG2SIZE, smmu->sid_bits);
> > > > cfg->strtab_base_cfg = reg;
> > > >
> > > > + if (is_kdump_kernel()) {
> > > > + arm_smmu_copy_table(smmu, cfg, size);
> > > > + return 0;
> > > > + }
> > > > +
> > > > arm_smmu_init_bypass_stes(strtab, cfg->num_l1_ents);
> > > > return 0;
> > > > }
> > > > --
> > > > 2.18.2
> > > >
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^ permalink raw reply
* Re: [PATCH v3 4/4] PCI: cadence: Use "dma-ranges" instead of "cdns,no-bar-match-nbits" property
From: Kishon Vijay Abraham I @ 2020-05-21 3:30 UTC (permalink / raw)
To: Rob Herring
Cc: devicetree, Lorenzo Pieralisi, PCI, linux-kernel@vger.kernel.org,
Tom Joseph, Bjorn Helgaas, Robin Murphy,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
In-Reply-To: <CAL_JsqJ1Om2CX5e1y32bzeiuv4fAdyFpZ88a346g4Q+jq_Ldcg@mail.gmail.com>
Hi Rob,
On 5/19/2020 10:41 PM, Rob Herring wrote:
> On Fri, May 8, 2020 at 7:07 AM Kishon Vijay Abraham I <kishon@ti.com> wrote:
>>
>> Cadence PCIe core driver (host mode) uses "cdns,no-bar-match-nbits"
>> property to configure the number of bits passed through from PCIe
>> address to internal address in Inbound Address Translation register.
>> This only used the NO MATCH BAR.
>>
>> However standard PCI dt-binding already defines "dma-ranges" to
>> describe the address ranges accessible by PCIe controller. Add support
>> in Cadence PCIe host driver to parse dma-ranges and configure the
>> inbound regions for BAR0, BAR1 and NO MATCH BAR. Cadence IP specifies
>> maximum size for BAR0 as 256GB, maximum size for BAR1 as 2 GB, so if
>> the dma-ranges specifies a size larger than the maximum allowed, the
>> driver will split and configure the BARs.
>
> Would be useful to know what your dma-ranges contains now.
>
>
>> Legacy device tree binding compatibility is maintained by retaining
>> support for "cdns,no-bar-match-nbits".
>>
>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>> ---
>> .../controller/cadence/pcie-cadence-host.c | 141 ++++++++++++++++--
>> drivers/pci/controller/cadence/pcie-cadence.h | 17 ++-
>> 2 files changed, 141 insertions(+), 17 deletions(-)
>>
>> diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
>> index 6ecebb79057a..2485ecd8434d 100644
>> --- a/drivers/pci/controller/cadence/pcie-cadence-host.c
>> +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
>> @@ -11,6 +11,12 @@
>>
>> #include "pcie-cadence.h"
>>
>> +static u64 cdns_rp_bar_max_size[] = {
>> + [RP_BAR0] = _ULL(128 * SZ_2G),
>> + [RP_BAR1] = SZ_2G,
>> + [RP_NO_BAR] = SZ_64T,
>> +};
>> +
>> void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn,
>> int where)
>> {
>> @@ -106,6 +112,117 @@ static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc)
>> return 0;
>> }
>>
>> +static void cdns_pcie_host_bar_ib_config(struct cdns_pcie_rc *rc,
>> + enum cdns_pcie_rp_bar bar,
>> + u64 cpu_addr, u32 aperture)
>> +{
>> + struct cdns_pcie *pcie = &rc->pcie;
>> + u32 addr0, addr1;
>> +
>> + addr0 = CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS(aperture) |
>> + (lower_32_bits(cpu_addr) & GENMASK(31, 8));
>> + addr1 = upper_32_bits(cpu_addr);
>> + cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_RP_BAR_ADDR0(bar), addr0);
>> + cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar), addr1);
>> +}
>> +
>> +static int cdns_pcie_host_bar_config(struct cdns_pcie_rc *rc,
>> + struct resource_entry *entry,
>> + enum cdns_pcie_rp_bar *index)
>> +{
>> + u64 cpu_addr, pci_addr, size, winsize;
>> + struct cdns_pcie *pcie = &rc->pcie;
>> + struct device *dev = pcie->dev;
>> + enum cdns_pcie_rp_bar bar;
>> + unsigned long flags;
>> + u32 aperture;
>> + u32 value;
>> +
>> + cpu_addr = entry->res->start;
>> + flags = entry->res->flags;
>> + pci_addr = entry->res->start - entry->offset;
>> + size = resource_size(entry->res);
>> + bar = *index;
>> +
>> + if (entry->offset) {
>> + dev_err(dev, "Cannot map PCI addr: %llx to CPU addr: %llx\n",
>> + pci_addr, cpu_addr);
>
> Would be a bit more clear to say PCI addr must equal CPU addr.
>
>> + return -EINVAL;
>> + }
>> +
>> + value = cdns_pcie_readl(pcie, CDNS_PCIE_LM_RC_BAR_CFG);
>> + while (size > 0) {
>> + if (bar > RP_NO_BAR) {
>> + dev_err(dev, "Failed to map inbound regions!\n");
>> + return -EINVAL;
>> + }
>> +
>> + winsize = size;
>> + if (size > cdns_rp_bar_max_size[bar])
>> + winsize = cdns_rp_bar_max_size[bar];
>> +
>> + aperture = ilog2(winsize);
>> +
>> + cdns_pcie_host_bar_ib_config(rc, bar, cpu_addr, aperture);
>> +
>> + if (bar == RP_NO_BAR)
>> + break;
>> +
>> + if (winsize + cpu_addr >= SZ_4G) {
>> + if (!(flags & IORESOURCE_PREFETCH))
>> + value |= LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar);
>> + value |= LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar);
>> + } else {
>> + if (!(flags & IORESOURCE_PREFETCH))
>> + value |= LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar);
>> + value |= LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar);
>> + }
>> +
>> + value |= LM_RC_BAR_CFG_APERTURE(bar, aperture);
>> +
>> + size -= winsize;
>> + cpu_addr += winsize;
>> + bar++;
>> + }
>> + cdns_pcie_writel(pcie, CDNS_PCIE_LM_RC_BAR_CFG, value);
>> + *index = bar;
>> +
>> + return 0;
>> +}
>> +
>> +static int cdns_pcie_host_map_dma_ranges(struct cdns_pcie_rc *rc)
>> +{
>> + enum cdns_pcie_rp_bar bar = RP_BAR0;
>> + struct cdns_pcie *pcie = &rc->pcie;
>> + struct device *dev = pcie->dev;
>> + struct device_node *np = dev->of_node;
>> + struct pci_host_bridge *bridge;
>> + struct resource_entry *entry;
>> + u32 no_bar_nbits = 32;
>> + int err;
>> +
>> + bridge = pci_host_bridge_from_priv(rc);
>> + if (!bridge)
>> + return -ENOMEM;
>> +
>> + if (list_empty(&bridge->dma_ranges)) {
>> + of_property_read_u32(np, "cdns,no-bar-match-nbits",
>> + &no_bar_nbits);
>> + cdns_pcie_host_bar_ib_config(rc, RP_NO_BAR, 0x0, no_bar_nbits);
>> + return 0;
>> + }
>> +
>> + resource_list_for_each_entry(entry, &bridge->dma_ranges) {
>> + err = cdns_pcie_host_bar_config(rc, entry, &bar);
>
> Seems like this should have some better logic to pick which BAR to
> use. Something like find the biggest region and then find the smallest
> BAR that it fits in. Then get the next biggest...
Okay, I'll change this something like for each region, find the smallest BAR
that it fits in and if there is no BAR big enough to hold the region, split the
region to see if can be fitted using multiple BARs. I don't see the purpose of
finding the biggest region first since at all times we'll only use the smallest
BAR to fit.
Thanks
Kishon
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^ permalink raw reply
* Re: [PATCH v14 03/11] soc: mediatek: Add basic_clk_name to scp_power_data
From: Weiyi Lu @ 2020-05-21 3:28 UTC (permalink / raw)
To: Enric Balletbo i Serra
Cc: James Liao, Nicolas Boichat, srv_heupstream, Rob Herring,
Enric Balletbo Serra, linux-kernel, Fan Chen, linux-mediatek,
Sascha Hauer, Matthias Brugger, linux-arm-kernel
In-Reply-To: <c510cc46-3285-fa53-b2e1-0420b0bfb61c@collabora.com>
On Mon, 2020-05-18 at 19:52 +0200, Enric Balletbo i Serra wrote:
> Hi Weiyi,
>
> On 15/5/20 5:35, Weiyi Lu wrote:
> > On Mon, 2020-05-11 at 14:02 +0800, Weiyi Lu wrote:
> >> On Wed, 2020-05-06 at 23:01 +0200, Enric Balletbo i Serra wrote:
> >>> Hi Weiyi,
> >>>
> >>> Thank you for your patch.
> >>>
> >>> On 6/5/20 10:15, Weiyi Lu wrote:
> >>>> Try to stop extending the clk_id or clk_names if there are
> >>>> more and more new BASIC clocks. To get its own clocks by the
> >>>> basic_clk_name of each power domain.
> >>>> And then use basic_clk_name strings for all compatibles, instead of
> >>>> mixing clk_id and clk_name.
> >>>>
> >>>> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> >>>> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
> >>>> ---
> >>>> drivers/soc/mediatek/mtk-scpsys.c | 134 ++++++++++++--------------------------
> >>>> 1 file changed, 41 insertions(+), 93 deletions(-)
> >>>>
> >>>> diff --git a/drivers/soc/mediatek/mtk-scpsys.c b/drivers/soc/mediatek/mtk-scpsys.c
> >>>> index f669d37..c9c3cf7 100644
> >>>> --- a/drivers/soc/mediatek/mtk-scpsys.c
> >>>> +++ b/drivers/soc/mediatek/mtk-scpsys.c
> >>>> @@ -78,34 +78,6 @@
> >>>> #define PWR_STATUS_HIF1 BIT(26) /* MT7622 */
> >>>> #define PWR_STATUS_WB BIT(27) /* MT7622 */
> >>>>
> >>>> -enum clk_id {
> >>>> - CLK_NONE,
> >>>> - CLK_MM,
> >>>> - CLK_MFG,
> >>>> - CLK_VENC,
> >>>> - CLK_VENC_LT,
> >>>> - CLK_ETHIF,
> >>>> - CLK_VDEC,
> >>>> - CLK_HIFSEL,
> >>>> - CLK_JPGDEC,
> >>>> - CLK_AUDIO,
> >>>> - CLK_MAX,
> >>>> -};
> >>>> -
> >>>> -static const char * const clk_names[] = {
> >>>> - NULL,
> >>>> - "mm",
> >>>> - "mfg",
> >>>> - "venc",
> >>>> - "venc_lt",
> >>>> - "ethif",
> >>>> - "vdec",
> >>>> - "hif_sel",
> >>>> - "jpgdec",
> >>>> - "audio",
> >>>> - NULL,
> >>>> -};
> >>>> -
> >>>> #define MAX_CLKS 3
> >>>>
> >>>> /**
> >>>> @@ -116,7 +88,7 @@ enum clk_id {
> >>>> * @sram_pdn_bits: The mask for sram power control bits.
> >>>> * @sram_pdn_ack_bits: The mask for sram power control acked bits.
> >>>> * @bus_prot_mask: The mask for single step bus protection.
> >>>> - * @clk_id: The basic clocks required by this power domain.
> >>>> + * @basic_clk_name: The basic clocks required by this power domain.
> >>>> * @caps: The flag for active wake-up action.
> >>>> */
> >>>> struct scp_domain_data {
> >>>> @@ -126,7 +98,7 @@ struct scp_domain_data {
> >>>> u32 sram_pdn_bits;
> >>>> u32 sram_pdn_ack_bits;
> >>>> u32 bus_prot_mask;
> >>>> - enum clk_id clk_id[MAX_CLKS];
> >>>> + const char *basic_clk_name[MAX_CLKS];
> >>>
> >>> I only reviewed v13, so sorry if this was already discussed. I am wondering if
> >>> would be better take advantage of the devm_clk_bulk_get() function instead of
> >>> kind of reimplementing the same, something like this
> >>>
> >>> const struct clk_bulk_data *basic_clocks;
> >>>
> >>
> >> I thought it should be const struct clk_bulk_data
> >> basic_clocks[MAX_CLKS]; instead of const struct clk_bulk_data
> >> *basic_clocks; in struct scp_domain_data data type
> >>
> >>>> u8 caps;
> >>>> };
> >>>>
> >>>> @@ -411,12 +383,19 @@ static int scpsys_power_off(struct generic_pm_domain *genpd)
> >>>> return ret;
> >>>> }
> >>>>
> >>>> -static void init_clks(struct platform_device *pdev, struct clk **clk)
> >>>> +static int init_basic_clks(struct platform_device *pdev, struct clk **clk,
> >>>> + const char * const *name)
> >>>> {
> >>>> int i;
> >>>>
> >>>> - for (i = CLK_NONE + 1; i < CLK_MAX; i++)
> >>>> - clk[i] = devm_clk_get(&pdev->dev, clk_names[i]);
> >>>> + for (i = 0; i < MAX_CLKS && name[i]; i++) {
> >>>> + clk[i] = devm_clk_get(&pdev->dev, name[i]);
> >>>> +
> >>>> + if (IS_ERR(clk[i]))
> >>>> + return PTR_ERR(clk[i]);
> >>>> + }
> >>>
> >>> You will be able to remove this function, see below ...
> >>>
> >>>> +
> >>>> + return 0;
> >>>> }
> >>>>
> >>>> static struct scp *init_scp(struct platform_device *pdev,
> >>>> @@ -426,9 +405,8 @@ static struct scp *init_scp(struct platform_device *pdev,
> >>>> {
> >>>> struct genpd_onecell_data *pd_data;
> >>>> struct resource *res;
> >>>> - int i, j;
> >>>> + int i, ret;
> >>>> struct scp *scp;
> >>>> - struct clk *clk[CLK_MAX];
> >>>>
> >>>> scp = devm_kzalloc(&pdev->dev, sizeof(*scp), GFP_KERNEL);
> >>>> if (!scp)
> >>>> @@ -481,8 +459,6 @@ static struct scp *init_scp(struct platform_device *pdev,
> >>>>
> >>>> pd_data->num_domains = num;
> >>>>
> >>>> - init_clks(pdev, clk);
> >>>> -
> >>>> for (i = 0; i < num; i++) {
> >>>> struct scp_domain *scpd = &scp->domains[i];
> >>>> struct generic_pm_domain *genpd = &scpd->genpd;
> >>>> @@ -493,17 +469,9 @@ static struct scp *init_scp(struct platform_device *pdev,
> >>>>
> >>>> scpd->data = data;
> >>>>
> >>>> - for (j = 0; j < MAX_CLKS && data->clk_id[j]; j++) {
> >>>> - struct clk *c = clk[data->clk_id[j]];
> >>>> -
> >>>> - if (IS_ERR(c)) {
> >>>> - dev_err(&pdev->dev, "%s: clk unavailable\n",
> >>>> - data->name);
> >>>> - return ERR_CAST(c);
> >>>> - }
> >>>> -
> >>>> - scpd->clk[j] = c;
> >>>> - }
> >>>> + ret = init_basic_clks(pdev, scpd->clk, data->basic_clk_name);
> >>>> + if (ret)
> >>>> + return ERR_PTR(ret);
> >>>
> >>> Just call:
> >>>
> >>> ret = devm_clk_bulk_get(&pdev->dev, ARRAY_SIZE(basic_clocks),
> >>> data->basic_clocks);
> >>> if (ret)
> >>> return ERR_PTR(ret);
> >>>
> >>>>
> >>>> genpd->name = data->name;
> >>>> genpd->power_off = scpsys_power_off;
> >>>> @@ -560,7 +528,6 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> >>>> .ctl_offs = SPM_CONN_PWR_CON,
> >>>> .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_CONN_M |
> >>>> MT2701_TOP_AXI_PROT_EN_CONN_S,
> >>>> - .clk_id = {CLK_NONE},
> >>>> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> >>>> },
> >>>> [MT2701_POWER_DOMAIN_DISP] = {
> >>>> @@ -568,7 +535,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> >>>> .sta_mask = PWR_STATUS_DISP,
> >>>> .ctl_offs = SPM_DIS_PWR_CON,
> >>>> .sram_pdn_bits = GENMASK(11, 8),
> >>>> - .clk_id = {CLK_MM},
> >>>> + .basic_clk_name = {"mm"},
> >>>
> >>> .basic_clocks[] = {
> >>> { .id = "mm" },
> >>> };
> >>>
> >>
> >> Those basic clocks without given a name (name: null) would get incorrect
> >> clock via clk_bulk_get(...) due to
> >>
> >> /**
> >> * of_parse_clkspec() - Parse a DT clock specifier for a given device
> >> node
> >> * @np: device node to parse clock specifier from
> >> * @index: index of phandle to parse clock out of. If index < 0, @name
> >> is used
> >> * @name: clock name to find and parse. If name is NULL, the index is
> >> used
> >>
> >> And the index is 0 here in this callstack
> >>
> >> I guess something need to be improved before we use the clk_bulk_ APIs.
> >>
> >
> > Hi Enric,
> >
> > According to the result above, is it necessary to change the APIs or
> > maybe I should send the next version v15 first to fix other problems you
> > mentioned? Many thanks.
> >
>
> It is fine to send a next version without changing the APIs, it depends on the
> extra work if you are fine with the change. To be honest I didn't see the
> problem above but I think can be fixed.
>
> Cheers,
> Enric
>
Hi Enric,
Got it, I'll send a next version without changing the APIs.
And please let me explain it again.
If anything wrong, feel free to correct me.
First, the clock mapping in the dts
e.g.
clocks = <&topckgen CLK_TOP_MUX_AUD_INTBUS>, <= index 0
<&infracfg CLK_INFRA_AUDIO>,
<&infracfg CLK_INFRA_AUDIO_26M_BCLK>,
<&topckgen CLK_TOP_MUX_MFG>,
<&topckgen CLK_TOP_MUX_MM>;
clock-names = "audio",
"audio1",
"audio2",
"mfg",
"mm";
And then, in struct scp_domain_data data structure we might need to use
const struct clk_bulk_data basic_clocks[MAX_CLKS]; rather than const
struct clk_bulk_data *basic_clocks;
So what
.basic_clocks = {
{ .id = "mm" },
};
is certainly like below
.basic_clocks = {
{ .id = "mm" },
{ .id = null },
{ .id = null },
};
And using devm_clk_bulk_get(...); to get the clock resource will result
in
basic_clocks = {
{ .id = "mm", . clk = <&topckgen CLK_TOP_MUX_MM>},
{ .id = null, . clk = <&topckgen CLK_TOP_MUX_AUD_INTBUS>},
{ .id = null, . clk = <&topckgen CLK_TOP_MUX_AUD_INTBUS>},
};
I thought it's incorrect for my usage inside the mtk-scpsys.c
and currently how devm_clk_bulk_get(...) will get the clock resource is
by API of_parse_clksepc()
/**
* of_parse_clkspec() - Parse a DT clock specifier for a given device
node
* @np: device node to parse clock specifier from
* @index: index of phandle to parse clock out of. If index < 0, @name
is used
* @name: clock name to find and parse. If name is NULL, the index is
used
And for clocks without given a name first(id=null), will use the index 0
to get the clock. In this example, the index 0 will map to <&topckgen
CLK_TOP_MUX_AUD_INTBUS>
If we ignore the problem and use clk_bulk_prepare()/_enable() to control
the clock, so far, clk_bulk_enable will traverse all the iterator and
enable the unexpected clocks without check if the clock id(name) is
valid or not.
Right now, I'm not sure why of_parse_clkspec() assume to use the index 0
if the name is NULL. I might need some time to dig it out. If you have
some information about this part, please share it to me. Many thanks.
>
> >>
> >>>> .bus_prot_mask = MT2701_TOP_AXI_PROT_EN_MM_M0,
> >>>> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> >>>> },
> >>>> @@ -578,7 +545,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> >>>> .ctl_offs = SPM_MFG_PWR_CON,
> >>>> .sram_pdn_bits = GENMASK(11, 8),
> >>>> .sram_pdn_ack_bits = GENMASK(12, 12),
> >>>> - .clk_id = {CLK_MFG},
> >>>> + .basic_clk_name = {"mfg"},
> >>>
> >>> .basic_clocks[] = {
> >>> { .id = "mfg" },
> >>> };
> >>>
> >>>> .caps = MTK_SCPD_ACTIVE_WAKEUP,
> >>>> },
> >>>> [MT2701_POWER_DOMAIN_VDEC] = {
> >>>> @@ -587,7 +554,7 @@ static void mtk_register_power_domains(struct platform_device *pdev,
> >>>> .ctl_offs = SPM_VDE_PWR_CON,
> >>>> .sram_pdn_bits = GENMASK(11, 8),
> >>>> .sram_pdn_ack_bits = GENMASK(12, 12),
> >>>> - .clk_id = {CLK_MM},
> >>>> + .basic_clk_name = {"mm"},
> >>>
> >>> ...
> >>>
> >>> [snip]
> >>
> >>
> >
>
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
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* [PATCH v1 2/2] arm64: dts: imx8mn-ddr4-evk: correct ldo1/ldo2 voltage range
From: Robin Gong @ 2020-05-21 11:26 UTC (permalink / raw)
To: robh+dt, shawnguo, s.hauer, festevam, Anson.Huang
Cc: linux-arm-kernel, devicetree, linux-imx, kernel, linux-kernel
In-Reply-To: <1590060368-2282-1-git-send-email-yibin.gong@nxp.com>
Correct ldo1 voltage range from wrong high group(3.0v~3.3v) to low group
(1.6v~1.9v) because the ldo1 should be 1.8v. Actually, two voltage groups
have been supported at bd718x7-regulator driver, hence, just corrrect the
voltage range to 1.6v~3.3v. For ldo2@0.8v, correct voltage range too.
Otherwise, ldo1 would be kept @3.0v and ldo2@0.9v which violate i.mx8mm
datasheet as the below warning log in kernel:
[ 0.995524] LDO1: Bringing 1800000uV into 3000000-3000000uV
[ 0.999196] LDO2: Bringing 800000uV into 900000-900000uV
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts | 4 ++--
arch/arm64/boot/dts/freescale/imx8mn-evk.dts | 9 +++++++++
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
index d07e0e6..a1e5483 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
@@ -113,7 +113,7 @@
ldo1_reg: LDO1 {
regulator-name = "LDO1";
- regulator-min-microvolt = <3000000>;
+ regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
@@ -121,7 +121,7 @@
ldo2_reg: LDO2 {
regulator-name = "LDO2";
- regulator-min-microvolt = <900000>;
+ regulator-min-microvolt = <800000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
regulator-always-on;
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts
index 61f3519..117ff4b 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dts
@@ -13,6 +13,15 @@
compatible = "fsl,imx8mn-evk", "fsl,imx8mn";
};
+&ecspi1 {
+ status = "okay";
+spidev0: spi@0 {
+ compatible = "ge,achc";
+ reg = <0>;
+ spi-max-frequency = <1000000>;
+ };
+};
+
&A53_0 {
/delete-property/operating-points-v2;
};
--
2.7.4
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