* Re: [PATCH 1/2] regmap: provide helpers for simple bit operations
From: Mark Brown @ 2020-05-28 13:29 UTC (permalink / raw)
To: Bartosz Golaszewski
Cc: Stephane Le Provost, Bartosz Golaszewski, netdev, Sean Wang,
linux-kernel, Mark Lee, Fabien Parent, Pedro Tsai, linux-mediatek,
Andrew Perepech, John Crispin, Matthias Brugger, Jakub Kicinski,
David S . Miller, linux-arm-kernel
In-Reply-To: <20200528123459.21168-2-brgl@bgdev.pl>
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On Thu, May 28, 2020 at 02:34:58PM +0200, Bartosz Golaszewski wrote:
> This adds three new macros for simple bit operations: set_bits,
> clear_bits and test_bits.
Why macros and not static inlines?
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* Re: [PATCH v3 04/20] arm64: dts: arm: vexpress: Move fixed devices out of bus node
From: André Przywara @ 2020-05-28 13:30 UTC (permalink / raw)
To: Guenter Roeck
Cc: Mark Rutland, Rob Herring, Lorenzo Pieralisi, devicetree,
Liviu Dudau, Sudeep Holla, linux-arm-kernel
In-Reply-To: <20200528024810.GA232303@roeck-us.net>
On 28/05/2020 03:48, Guenter Roeck wrote:
Hi Guenter,
> On Wed, May 13, 2020 at 11:30:00AM +0100, Andre Przywara wrote:
>> The devicetree compiler complains when DT nodes without a reg property
>> live inside a (simple) bus node:
>> Warning (simple_bus_reg): Node /bus@8000000/motherboard-bus/refclk32khz
>> missing or empty reg/ranges property
>>
>> Move the fixed clocks, the fixed regulator, the leds and the config bus
>> subtree to the root node, since they do not depend on any busses.
>>
>> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
>
> This patch results in tracebacks when booting the vexpress-a15 machine
> with vexpress-v2p-ca15-tc1 devicetree file in qemu. Reverting it as well
> as the subsequent patches affecting the same file (to avoid revert
> conflicts) fixes the problem.
Many thanks for the heads up! I was able to reproduce it here. On the
first glance it looks like the UART is probed before the clocks now,
because the traversal of the changed DT leads to a different probe
order. I will look into how to fix this.
Cheers,
Andre
>
> Guenter
>
> ---
> [ 12.744248] ------------[ cut here ]------------
> [ 12.744562] WARNING: CPU: 0 PID: 20 at drivers/tty/serial/serial_core.c:471 uart_get_baud_rate+0x100/0x154
> [ 12.744607] Modules linked in:
> [ 12.744785] CPU: 0 PID: 20 Comm: kworker/0:1 Not tainted 5.7.0-rc7-next-20200526 #1
> [ 12.744818] Hardware name: ARM-Versatile Express
> [ 12.745021] Workqueue: events amba_deferred_retry_func
> [ 12.745155] [<c0312484>] (unwind_backtrace) from [<c030c490>] (show_stack+0x10/0x14)
> [ 12.745206] [<c030c490>] (show_stack) from [<c0880f04>] (dump_stack+0xc8/0xdc)
> [ 12.745239] [<c0880f04>] (dump_stack) from [<c0346e44>] (__warn+0xdc/0xf4)
> [ 12.745270] [<c0346e44>] (__warn) from [<c0346f0c>] (warn_slowpath_fmt+0xb0/0xb8)
> [ 12.745302] [<c0346f0c>] (warn_slowpath_fmt) from [<c0a6b16c>] (uart_get_baud_rate+0x100/0x154)
> [ 12.745336] [<c0a6b16c>] (uart_get_baud_rate) from [<c0a7f5ac>] (pl011_set_termios+0x48/0x32c)
> [ 12.745367] [<c0a7f5ac>] (pl011_set_termios) from [<c0a6bbbc>] (uart_set_options+0x124/0x164)
> [ 12.745404] [<c0a6bbbc>] (uart_set_options) from [<c1b8c804>] (pl011_console_setup+0x214/0x230)
> [ 12.745438] [<c1b8c804>] (pl011_console_setup) from [<c03ab0d8>] (try_enable_new_console+0x98/0x138)
> [ 12.745469] [<c03ab0d8>] (try_enable_new_console) from [<c03acc64>] (register_console+0xe8/0x304)
> [ 12.745499] [<c03acc64>] (register_console) from [<c0a6c88c>] (uart_add_one_port+0x4c0/0x504)
> [ 12.745529] [<c0a6c88c>] (uart_add_one_port) from [<c0a80404>] (pl011_register_port+0x5c/0xac)
> [ 12.745568] [<c0a80404>] (pl011_register_port) from [<c097f5a0>] (amba_probe+0x9c/0x110)
> [ 12.745602] [<c097f5a0>] (amba_probe) from [<c0b57e84>] (really_probe+0x218/0x348)
> [ 12.745632] [<c0b57e84>] (really_probe) from [<c0b580c0>] (driver_probe_device+0x5c/0xb4)
> [ 12.745662] [<c0b580c0>] (driver_probe_device) from [<c0b55ff4>] (bus_for_each_drv+0x58/0xb8)
> [ 12.745692] [<c0b55ff4>] (bus_for_each_drv) from [<c0b57bf8>] (__device_attach+0xd4/0x140)
> [ 12.745721] [<c0b57bf8>] (__device_attach) from [<c0b56eb0>] (bus_probe_device+0x88/0x90)
> [ 12.745751] [<c0b56eb0>] (bus_probe_device) from [<c0b53234>] (device_add+0x3d4/0x6e8)
> [ 12.745782] [<c0b53234>] (device_add) from [<c097f664>] (amba_device_try_add+0x50/0x2d4)
> [ 12.745812] [<c097f664>] (amba_device_try_add) from [<c097f924>] (amba_deferred_retry+0x3c/0x98)
> [ 12.745847] [<c097f924>] (amba_deferred_retry) from [<c097f988>] (amba_deferred_retry_func+0x8/0x40)
> [ 12.745881] [<c097f988>] (amba_deferred_retry_func) from [<c0365b6c>] (process_one_work+0x2b8/0x6e8)
> [ 12.745912] [<c0365b6c>] (process_one_work) from [<c0365fe0>] (worker_thread+0x44/0x540)
> [ 12.745942] [<c0365fe0>] (worker_thread) from [<c036d810>] (kthread+0x16c/0x178)
> [ 12.745973] [<c036d810>] (kthread) from [<c03001a8>] (ret_from_fork+0x14/0x2c)
> [ 12.746041] Exception stack(0xc73abfb0 to 0xc73abff8)
> [ 12.746181] bfa0: 00000000 00000000 00000000 00000000
> [ 12.746302] bfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
> [ 12.746397] bfe0: 00000000 00000000 00000000 00000000 00000013 00000000
> [ 12.746651] ---[ end trace 2a3f61da56bd8a49 ]---
>
> ---
> # bad: [b0523c7b1c9d0edcd6c0fe6d2cb558a9ad5c60a8] Add linux-next specific files for 20200526
> # good: [9cb1fd0efd195590b828b9b865421ad345a4a145] Linux 5.7-rc7
> git bisect start 'next-20200526' 'v5.7-rc7'
> # bad: [0c7351ad83670964e48cb9a098ad732c1ecbf804] Merge remote-tracking branch 'crypto/master'
> git bisect bad 0c7351ad83670964e48cb9a098ad732c1ecbf804
> # bad: [42e11d9b4682229fa7187d129758b8c382f8cd5d] Merge remote-tracking branch 'jc_docs/docs-next'
> git bisect bad 42e11d9b4682229fa7187d129758b8c382f8cd5d
> # bad: [ab6f501559e9efa687c711a781243cf6651a82d3] Merge remote-tracking branch 'm68k/for-next'
> git bisect bad ab6f501559e9efa687c711a781243cf6651a82d3
> # bad: [44aaa516ca63b3ab2da8ae81e9c6a58656e6acb5] Merge branch 'arm/drivers' into for-next
> git bisect bad 44aaa516ca63b3ab2da8ae81e9c6a58656e6acb5
> # good: [1cb00f8c3b36e6ae026fb58d1cd2ccd78b81aa9f] Merge tag 'qcom-arm64-for-5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt
> git bisect good 1cb00f8c3b36e6ae026fb58d1cd2ccd78b81aa9f
> # bad: [ed0c25932fbfafdfe37e9633dee21770d3c5a306] Merge branch 'arm/defconfig' into for-next
> git bisect bad ed0c25932fbfafdfe37e9633dee21770d3c5a306
> # bad: [9eddc06a3bc79402f50176703237ed045ae77b16] Merge branch 'mmp/fixes' into arm/dt
> git bisect bad 9eddc06a3bc79402f50176703237ed045ae77b16
> # bad: [87b990ab62722a8a3cb0691107971ab1bd7bddb5] Merge tag 'mvebu-dt64-5.8-1' of git://git.infradead.org/linux-mvebu into arm/dt
> git bisect bad 87b990ab62722a8a3cb0691107971ab1bd7bddb5
> # bad: [94cc3f1baabac5e5c4dcc6c2f070353f8315d0ee] arm64: dts: juno: Fix SCPI shared mem node name
> git bisect bad 94cc3f1baabac5e5c4dcc6c2f070353f8315d0ee
> # bad: [a78aee9e434932a500db36cc6d88daeff3745e9f] arm64: dts: juno: Fix GIC child nodes
> git bisect bad a78aee9e434932a500db36cc6d88daeff3745e9f
> # bad: [feebdc3f7950d7e44e914e821f6c04e58e292c74] arm64: dts: fvp: Move fixed clocks out of bus node
> git bisect bad feebdc3f7950d7e44e914e821f6c04e58e292c74
> # good: [849bfc3dfc13cde6ec04fbcf32af553ded9f7ec3] arm64: dts: fvp: Move fixed devices out of bus node
> git bisect good 849bfc3dfc13cde6ec04fbcf32af553ded9f7ec3
> # bad: [d9258898ad49cbb46caffe23af0d4f0b766e67a2] arm64: dts: vexpress: Move fixed devices out of bus node
> git bisect bad d9258898ad49cbb46caffe23af0d4f0b766e67a2
> # first bad commit: [d9258898ad49cbb46caffe23af0d4f0b766e67a2] arm64: dts: vexpress: Move fixed devices out of bus node
>
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* Re: [PATCH 1/2] regmap: provide helpers for simple bit operations
From: Bartosz Golaszewski @ 2020-05-28 13:32 UTC (permalink / raw)
To: Mark Brown
Cc: Stephane Le Provost, Bartosz Golaszewski, netdev, Sean Wang,
Linux Kernel Mailing List, Mark Lee, Fabien Parent, Pedro Tsai,
moderated list:ARM/Mediatek SoC..., Andrew Perepech, John Crispin,
Matthias Brugger, Jakub Kicinski, David S . Miller, Linux ARM
In-Reply-To: <20200528132938.GC3606@sirena.org.uk>
czw., 28 maj 2020 o 15:29 Mark Brown <broonie@kernel.org> napisał(a):
>
> On Thu, May 28, 2020 at 02:34:58PM +0200, Bartosz Golaszewski wrote:
>
> > This adds three new macros for simple bit operations: set_bits,
> > clear_bits and test_bits.
>
> Why macros and not static inlines?
The existing regmap_update_bits_*() helpers are macros too, so I tried
to stay consistent. Any reason why they are macros and not static
inlines? If there's none, then why not convert them too? Otherwise
we'd have a static inline expanding a macro which in turn is calling a
function (regmap_update_bits_base()).
Bartosz
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* Re: [PATCH v4 3/4] dmaengine: mediatek-cqdma: fix compatible
From: Matthias Brugger @ 2020-05-28 13:39 UTC (permalink / raw)
To: EastL, Sean Wang
Cc: mark.rutland, devicetree, wsd_upstream, linux-kernel, vkoul,
robh+dt, linux-mediatek, dmaengine, linux-arm-kernel
In-Reply-To: <1590659832-31476-4-git-send-email-EastL.Lee@mediatek.com>
On 28/05/2020 11:57, EastL wrote:
> This patch fixes mediatek-cqdma compatible to common.
>
> Signed-off-by: EastL <EastL.Lee@mediatek.com>
> ---
> drivers/dma/mediatek/mtk-cqdma.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/dma/mediatek/mtk-cqdma.c b/drivers/dma/mediatek/mtk-cqdma.c
> index 905bbcb..bca7118 100644
> --- a/drivers/dma/mediatek/mtk-cqdma.c
> +++ b/drivers/dma/mediatek/mtk-cqdma.c
> @@ -544,7 +544,7 @@ static void mtk_cqdma_hw_deinit(struct mtk_cqdma_device *cqdma)
> }
>
> static const struct of_device_id mtk_cqdma_match[] = {
> - { .compatible = "mediatek,mt6765-cqdma" },
> + { .compatible = "mediatek,cqdma" },
We can't just delete and old compatible. If other cqdma IP blocks are the same
as mt6795, we should instead add entries in the binding description with
fallback compatible. For example for mt6779 the DTS would look like this:
compatible = "mediatek,mt6779-cqdma", "mediatek,mt6765-cqdma";
This way we the kernel will take care to bind the device against the driver with
mt7665-cqdma, but leaves us the posibillity to add any changes to the driver in
the future if we find some bugs/features for mt6779 that are not present in mt6765.
Regards,
Matthias
> { /* sentinel */ }
> };
> MODULE_DEVICE_TABLE(of, mtk_cqdma_match);
>
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* Re: [PATCH v2 3/6] prctl.2: Add PR_SPEC_DISABLE_NOEXEC for SPECULATION_CTRL prctls
From: Waiman Long @ 2020-05-28 13:45 UTC (permalink / raw)
To: Dave Martin, Michael Kerrisk
Cc: linux-arch, linux-man, Thomas Gleixner, linux-arm-kernel
In-Reply-To: <1590614258-24728-4-git-send-email-Dave.Martin@arm.com>
On 5/27/20 5:17 PM, Dave Martin wrote:
> Add the PR_SPEC_DISABLE_NOEXEC mode added in Linux 5.1
> for the PR_SPEC_STORE_BYPASS "misfeature" of
> PR_SET_SPECULATION_CTRL and PR_GET_SPECULATION_CTRL.
>
> Signed-off-by: Dave Martin <Dave.Martin@arm.com>
> Cc: Waiman Long <longman@redhat.com>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> ---
> man2/prctl.2 | 22 ++++++++++++++++++++--
> 1 file changed, 20 insertions(+), 2 deletions(-)
>
> diff --git a/man2/prctl.2 b/man2/prctl.2
> index b6fb51c..cab9915 100644
> --- a/man2/prctl.2
> +++ b/man2/prctl.2
> @@ -1187,6 +1187,12 @@ The speculation feature is disabled, mitigation is enabled.
> Same as
> .B PR_SPEC_DISABLE
> but cannot be undone.
> +.TP
> +.BR PR_SPEC_DISABLE_NOEXEC " (since Linux 5.1)"
> +Same as
> +.BR PR_SPEC_DISABLE ,
> +but but the state will be cleared on
> +.BR execve (2).
> .RE
> .IP
> If all bits are 0,
> @@ -1251,6 +1257,17 @@ with the same value for
> .I arg2
> will fail with the error
> .BR EPERM .
> +.\" commit 71368af9027f18fe5d1c6f372cfdff7e4bde8b48
> +.TP
> +.BR PR_SPEC_DISABLE_NOEXEC " (since Linux 5.1)"
> +Same as
> +.BR PR_SPEC_DISABLE ,
> +but but the state will be cleared on
> +.BR execve (2).
> +Currently only supported for
> +.I arg2
> +equal to
> +.B PR_SPEC_STORE_BYPASS.
> .RE
> .IP
> Any unsupported value in
> @@ -1899,11 +1916,12 @@ was
> .BR PR_SET_SPECULATION_CTRL
> and
> .IR arg3
> -is neither
> +is not
> .BR PR_SPEC_ENABLE ,
> .BR PR_SPEC_DISABLE ,
> +.BR PR_SPEC_FORCE_DISABLE ,
> nor
> -.BR PR_SPEC_FORCE_DISABLE .
> +.BR PR_SPEC_DISABLE_NOEXEC .
> .SH VERSIONS
> The
> .BR prctl ()
Acked-by: Waiman Long <longman@redhat.com>
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* Re: [PATCH] ARM: omap2: drop broken broadcast timer hack
From: Tony Lindgren @ 2020-05-28 13:46 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Rob Herring, Grygorii Strashko, Geert Uytterhoeven, Lokesh Vutla,
Keerthy, Santosh Shilimkar, linux-kernel, Tero Kristo, arm,
Olof Johansson, linux-omap, afzal mohammed, linux-arm-kernel
In-Reply-To: <20200528091923.2951100-1-arnd@arndb.de>
* Arnd Bergmann <arnd@arndb.de> [200528 09:20]:
> The OMAP4 timer code had a special hack for using the broadcast timer
> without SMP. Since the dmtimer is now gone, this also needs to be dropped
> to avoid a link failure for non-SMP AM43xx configurations:
>
> kernel/time/tick-broadcast.o: in function `tick_device_uses_broadcast':
> tick-broadcast.c:(.text+0x130): undefined reference to `tick_broadcast'
Hmm this sounds like a regression though. Isn't this needed for using
the ARM local timers on non-SMP SoC, so a separate timer from dmtimer?
I've probably removed something accidentally to cause this.
Regards,
Tony
> Fixes: 2ee04b88547a ("ARM: OMAP2+: Drop old timer code for dmtimer and 32k counter")
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> ---
> arch/arm/mach-omap2/Kconfig | 1 -
> arch/arm/mach-omap2/timer.c | 6 ------
> 2 files changed, 7 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
> index ca74473f01df..ec4450a5c296 100644
> --- a/arch/arm/mach-omap2/Kconfig
> +++ b/arch/arm/mach-omap2/Kconfig
> @@ -67,7 +67,6 @@ config SOC_AM43XX
> select ARM_GIC
> select MACH_OMAP_GENERIC
> select HAVE_ARM_SCU
> - select GENERIC_CLOCKEVENTS_BROADCAST
> select HAVE_ARM_TWD
> select ARM_ERRATA_754322
> select ARM_ERRATA_775420
> diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
> index 2d4ea386fc38..786336ee27ef 100644
> --- a/arch/arm/mach-omap2/timer.c
> +++ b/arch/arm/mach-omap2/timer.c
> @@ -46,12 +46,6 @@ void set_cntfreq(void)
> omap_smc1(OMAP5_DRA7_MON_SET_CNTFRQ_INDEX, arch_timer_freq);
> }
>
> -#if !defined(CONFIG_SMP) && defined(CONFIG_GENERIC_CLOCKEVENTS_BROADCAST)
> -void tick_broadcast(const struct cpumask *mask)
> -{
> -}
> -#endif
> -
> #if defined(CONFIG_SOC_OMAP5) || defined(CONFIG_SOC_DRA7XX)
>
> /*
> --
> 2.26.2
>
>
> _______________________________________________
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> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
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* Re: [PATCH 1/2] regmap: provide helpers for simple bit operations
From: Mark Brown @ 2020-05-28 13:48 UTC (permalink / raw)
To: Bartosz Golaszewski
Cc: Stephane Le Provost, Bartosz Golaszewski, netdev, Sean Wang,
Linux Kernel Mailing List, Mark Lee, Fabien Parent, Pedro Tsai,
moderated list:ARM/Mediatek SoC..., Andrew Perepech, John Crispin,
Matthias Brugger, Jakub Kicinski, David S . Miller, Linux ARM
In-Reply-To: <CAMRc=MejeXv6vd5iRW_EB3XqBtdCWDcV=4BOCDDFd4D0-y9LUA@mail.gmail.com>
[-- Attachment #1.1: Type: text/plain, Size: 613 bytes --]
On Thu, May 28, 2020 at 03:32:40PM +0200, Bartosz Golaszewski wrote:
> czw., 28 maj 2020 o 15:29 Mark Brown <broonie@kernel.org> napisał(a):
> > Why macros and not static inlines?
> The existing regmap_update_bits_*() helpers are macros too, so I tried
> to stay consistent. Any reason why they are macros and not static
> inlines? If there's none, then why not convert them too? Otherwise
> we'd have a static inline expanding a macro which in turn is calling a
> function (regmap_update_bits_base()).
Not really, I think it was just that they're argument tables. It'd be
good to convert them.
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* Re: [PATCH] ARM: omap2: drop broken broadcast timer hack
From: Tony Lindgren @ 2020-05-28 13:50 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Rob Herring, Grygorii Strashko, Geert Uytterhoeven, Lokesh Vutla,
Keerthy, Santosh Shilimkar, linux-kernel, Tero Kristo, arm,
Olof Johansson, linux-omap, afzal mohammed, linux-arm-kernel
In-Reply-To: <20200528134621.GN37466@atomide.com>
* Tony Lindgren <tony@atomide.com> [200528 13:47]:
> * Arnd Bergmann <arnd@arndb.de> [200528 09:20]:
> > The OMAP4 timer code had a special hack for using the broadcast timer
> > without SMP. Since the dmtimer is now gone, this also needs to be dropped
> > to avoid a link failure for non-SMP AM43xx configurations:
> >
> > kernel/time/tick-broadcast.o: in function `tick_device_uses_broadcast':
> > tick-broadcast.c:(.text+0x130): undefined reference to `tick_broadcast'
>
> Hmm this sounds like a regression though. Isn't this needed for using
> the ARM local timers on non-SMP SoC, so a separate timer from dmtimer?
>
> I've probably removed something accidentally to cause this.
Sounds like arch/arm/mach-omap2/Makefile change needs to be removed
to always still build in timer.o. And probably timer.c needs back
the ifdef for CONFIG_SOC_HAS_REALTIME_COUNTER.
I'll take a look today.
Regards,
Tony
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* Re: [PATCH net-next] dt-bindings: net: rename the bindings document for MediaTek STAR MAC
From: Bartosz Golaszewski @ 2020-05-28 13:50 UTC (permalink / raw)
To: Bartosz Golaszewski
Cc: linux-devicetree, Stephane Le Provost, netdev, LKML,
Fabien Parent, Rob Herring, linux-mediatek, Andrew Perepech,
Pedro Tsai, Matthias Brugger, Jakub Kicinski, David S . Miller,
arm-soc
In-Reply-To: <20200528132743.9221-1-brgl@bgdev.pl>
czw., 28 maj 2020 o 15:27 Bartosz Golaszewski <brgl@bgdev.pl> napisał(a):
>
> From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
>
> The driver itself was renamed before getting merged into mainline, but
> the binding document kept the old name. This makes both names consistent.
>
> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
> ---
> .../net/{mediatek,eth-mac.yaml => mediatek,star-emac.yaml} | 0
> 1 file changed, 0 insertions(+), 0 deletions(-)
> rename Documentation/devicetree/bindings/net/{mediatek,eth-mac.yaml => mediatek,star-emac.yaml} (100%)
>
> diff --git a/Documentation/devicetree/bindings/net/mediatek,eth-mac.yaml b/Documentation/devicetree/bindings/net/mediatek,star-emac.yaml
> similarity index 100%
> rename from Documentation/devicetree/bindings/net/mediatek,eth-mac.yaml
> rename to Documentation/devicetree/bindings/net/mediatek,star-emac.yaml
> --
> 2.26.1
>
-ETOOEARLY David please don't apply this - the id field needs to be
updated too. I'll send a v2.
Bartosz
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^ permalink raw reply
* Re: [PATCH 1/2] regmap: provide helpers for simple bit operations
From: Bartosz Golaszewski @ 2020-05-28 13:57 UTC (permalink / raw)
To: Mark Brown
Cc: Stephane Le Provost, Bartosz Golaszewski, netdev, Sean Wang,
Linux Kernel Mailing List, Mark Lee, Fabien Parent, Pedro Tsai,
moderated list:ARM/Mediatek SoC..., Andrew Perepech, John Crispin,
Matthias Brugger, Jakub Kicinski, David S . Miller, Linux ARM
In-Reply-To: <20200528134802.GE3606@sirena.org.uk>
czw., 28 maj 2020 o 15:48 Mark Brown <broonie@kernel.org> napisał(a):
>
> On Thu, May 28, 2020 at 03:32:40PM +0200, Bartosz Golaszewski wrote:
> > czw., 28 maj 2020 o 15:29 Mark Brown <broonie@kernel.org> napisał(a):
>
> > > Why macros and not static inlines?
>
> > The existing regmap_update_bits_*() helpers are macros too, so I tried
> > to stay consistent. Any reason why they are macros and not static
> > inlines? If there's none, then why not convert them too? Otherwise
> > we'd have a static inline expanding a macro which in turn is calling a
> > function (regmap_update_bits_base()).
>
> Not really, I think it was just that they're argument tables. It'd be
> good to convert them.
Ok. So I'm seeing there are a lot of macros in regmap.h that could
become static inlines but given the amount of regmap users: how about
we do it separately and in the meantime I'll just modify this series
to use static inlines?
Bartosz
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^ permalink raw reply
* Re: [PATCH 1/2] regmap: provide helpers for simple bit operations
From: Mark Brown @ 2020-05-28 13:58 UTC (permalink / raw)
To: Bartosz Golaszewski
Cc: Stephane Le Provost, Bartosz Golaszewski, netdev, Sean Wang,
Linux Kernel Mailing List, Mark Lee, Fabien Parent, Pedro Tsai,
moderated list:ARM/Mediatek SoC..., Andrew Perepech, John Crispin,
Matthias Brugger, Jakub Kicinski, David S . Miller, Linux ARM
In-Reply-To: <CAMRc=MdL5dkJ+BPzvYXTnLQ_sGtU_7n=8jeSa5=hf8u9Pm+0FQ@mail.gmail.com>
[-- Attachment #1.1: Type: text/plain, Size: 314 bytes --]
On Thu, May 28, 2020 at 03:57:24PM +0200, Bartosz Golaszewski wrote:
> Ok. So I'm seeing there are a lot of macros in regmap.h that could
> become static inlines but given the amount of regmap users: how about
> we do it separately and in the meantime I'll just modify this series
> to use static inlines?
Sure.
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
[-- Attachment #2: Type: text/plain, Size: 176 bytes --]
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^ permalink raw reply
* [PATCH net-next v2] dt-bindings: net: rename the bindings document for MediaTek STAR EMAC
From: Bartosz Golaszewski @ 2020-05-28 13:59 UTC (permalink / raw)
To: David S . Miller, Jakub Kicinski, Rob Herring, Matthias Brugger
Cc: devicetree, Stephane Le Provost, Bartosz Golaszewski, netdev,
linux-kernel, Fabien Parent, linux-mediatek, Andrew Perepech,
Pedro Tsai, linux-arm-kernel
From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
The driver itself was renamed before getting merged into mainline, but
the binding document kept the old name. This makes both names consistent.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
---
v1 -> v2:
- update the id field as well
.../net/{mediatek,eth-mac.yaml => mediatek,star-emac.yaml} | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
rename Documentation/devicetree/bindings/net/{mediatek,eth-mac.yaml => mediatek,star-emac.yaml} (96%)
diff --git a/Documentation/devicetree/bindings/net/mediatek,eth-mac.yaml b/Documentation/devicetree/bindings/net/mediatek,star-emac.yaml
similarity index 96%
rename from Documentation/devicetree/bindings/net/mediatek,eth-mac.yaml
rename to Documentation/devicetree/bindings/net/mediatek,star-emac.yaml
index f85d91a9d6e5..aea88e621792 100644
--- a/Documentation/devicetree/bindings/net/mediatek,eth-mac.yaml
+++ b/Documentation/devicetree/bindings/net/mediatek,star-emac.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
-$id: http://devicetree.org/schemas/net/mediatek,eth-mac.yaml#
+$id: http://devicetree.org/schemas/net/mediatek,star-emac.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek STAR Ethernet MAC Controller
--
2.26.1
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^ permalink raw reply related
* Re: [PATCH v6 02/18] mtd: rawnand: Create a new enumeration to describe OOB placement
From: Miquel Raynal @ 2020-05-28 14:10 UTC (permalink / raw)
To: Boris Brezillon
Cc: Mark Rutland, devicetree, Vignesh Raghavendra, Tudor Ambarus,
Julien Su, Richard Weinberger, Weijie Gao, Paul Cercueil,
Rob Herring, linux-mtd, Thomas Petazzoni, Mason Yang,
Chuanhong Guo, linux-arm-kernel
In-Reply-To: <20200528140852.51f19794@collabora.com>
Boris Brezillon <boris.brezillon@collabora.com> wrote on Thu, 28 May
2020 14:08:52 +0200:
> On Thu, 28 May 2020 13:30:57 +0200
> Miquel Raynal <miquel.raynal@bootlin.com> wrote:
>
> In the subject s/OOB placement/ECC placement/
That's a leftover. Fixed in patch 2 and 3.
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^ permalink raw reply
* Re: [PATCH v4 4/4] dmaengine: mediatek-cqdma: add dma mask for capability
From: Matthias Brugger @ 2020-05-28 14:10 UTC (permalink / raw)
To: EastL, Sean Wang
Cc: mark.rutland, devicetree, wsd_upstream, linux-kernel, vkoul,
robh+dt, linux-mediatek, dmaengine, linux-arm-kernel
In-Reply-To: <1590659832-31476-5-git-send-email-EastL.Lee@mediatek.com>
On 28/05/2020 11:57, EastL wrote:
> This patch add dma mask for capability.
>
> Change-Id: I31f4622f9541d769702029532e5f5f185815dda2
No Change-Id in the commit message please.
> Signed-off-by: EastL <EastL.Lee@mediatek.com>
> ---
> drivers/dma/mediatek/mtk-cqdma.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/drivers/dma/mediatek/mtk-cqdma.c b/drivers/dma/mediatek/mtk-cqdma.c
> index bca7118..1805a76 100644
> --- a/drivers/dma/mediatek/mtk-cqdma.c
> +++ b/drivers/dma/mediatek/mtk-cqdma.c
> @@ -117,6 +117,7 @@ struct mtk_cqdma_vchan {
> * @clk: The clock that device internal is using
> * @dma_requests: The number of VCs the device supports to
> * @dma_channels: The number of PCs the device supports to
> + * @dma_mask: A mask for DMA capability
> * @vc: The pointer to all available VCs
> * @pc: The pointer to all the underlying PCs
> */
> @@ -126,6 +127,7 @@ struct mtk_cqdma_device {
>
> u32 dma_requests;
> u32 dma_channels;
> + u32 dma_mask;
> struct mtk_cqdma_vchan *vc;
> struct mtk_cqdma_pchan **pc;
> };
> @@ -549,6 +551,7 @@ static void mtk_cqdma_hw_deinit(struct mtk_cqdma_device *cqdma)
> };
> MODULE_DEVICE_TABLE(of, mtk_cqdma_match);
>
> +static u64 cqdma_dmamask;
> static int mtk_cqdma_probe(struct platform_device *pdev)
> {
> struct mtk_cqdma_device *cqdma;
> @@ -607,6 +610,16 @@ static int mtk_cqdma_probe(struct platform_device *pdev)
> cqdma->dma_channels = MTK_CQDMA_NR_PCHANS;
> }
>
> + if (pdev->dev.of_node && of_property_read_u32(pdev->dev.of_node,
> + "dma-channel-mask",
> + &cqdma->dma_mask)) {
I'd prefer:
if (pdev->dev.of_node)
ret = of_property_read_u32(pdev->dev.of_node,
"dma-channel-mask",
&cqdma->dma_mask))
if (ret) {
dev_warn(&pdev->dev,
"Using 0 as missing dma-channel-mask
property\n");
cqdma->dma_mask = 0;
}
> + dev_info(&pdev->dev,
> + "Using 0 as missing dma-channel-mask property\n");
dev_warn should be OK.
> + } else {
> + cqdma_dmamask = DMA_BIT_MASK(cqdma->dma_mask);
> + pdev->dev.dma_mask = &cqdma_dmamask;
if (dma_set_mask(&pdev->dev,
DMA_BIT_MASK(cqdma->dma_mask)) {
/* error out */
}
> + }
> +
> cqdma->pc = devm_kcalloc(&pdev->dev, cqdma->dma_channels,
> sizeof(*cqdma->pc), GFP_KERNEL);
> if (!cqdma->pc)
>
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^ permalink raw reply
* Re: [PATCH v6 03/18] mtd: rawnand: Separate the ECC engine type and the OOB placement
From: Boris Brezillon @ 2020-05-28 14:14 UTC (permalink / raw)
To: Miquel Raynal
Cc: Mark Rutland, devicetree, Vignesh Raghavendra, Tudor Ambarus,
Julien Su, Richard Weinberger, Weijie Gao, Paul Cercueil,
Rob Herring, linux-mtd, Thomas Petazzoni, Mason Yang,
Chuanhong Guo, linux-arm-kernel
In-Reply-To: <20200528113113.9166-4-miquel.raynal@bootlin.com>
On Thu, 28 May 2020 13:30:58 +0200
Miquel Raynal <miquel.raynal@bootlin.com> wrote:
> The use of "syndrome" placement should not be encoded in the ECC
> engine mode/type.
>
> Create a "placement" field in NAND chip and change all occurrences of
> the NAND_ECC_HW_SYNDROME enumeration to be just NAND_ECC_HW and
> possibly a placement entry like NAND_ECC_PLACEMENT_INTERLEAVED.
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
I'm not a big fan of the extra indentation level you add to the davinci
driver, but I can live with it.
> ---
> arch/arm/mach-davinci/board-dm355-leopard.c | 3 +-
> drivers/mtd/nand/raw/cafe_nand.c | 3 +-
> drivers/mtd/nand/raw/davinci_nand.c | 5 +-
> drivers/mtd/nand/raw/denali.c | 3 +-
> drivers/mtd/nand/raw/diskonchip.c | 3 +-
> drivers/mtd/nand/raw/lpc32xx_slc.c | 3 +-
> drivers/mtd/nand/raw/nand_base.c | 109 +++++++++++---------
> drivers/mtd/nand/raw/r852.c | 3 +-
> include/linux/mtd/rawnand.h | 6 +-
> include/linux/platform_data/mtd-davinci.h | 1 +
> 10 files changed, 81 insertions(+), 58 deletions(-)
>
> diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c
> index b9e9950dd300..4c8a592754ac 100644
> --- a/arch/arm/mach-davinci/board-dm355-leopard.c
> +++ b/arch/arm/mach-davinci/board-dm355-leopard.c
> @@ -76,7 +76,8 @@ static struct davinci_nand_pdata davinci_nand_data = {
> .mask_chipsel = BIT(14),
> .parts = davinci_nand_partitions,
> .nr_parts = ARRAY_SIZE(davinci_nand_partitions),
> - .ecc_mode = NAND_ECC_HW_SYNDROME,
> + .ecc_mode = NAND_HW_ECC_ENGINE,
> + .ecc_placement = NAND_ECC_PLACEMENT_INTERLEAVED,
> .ecc_bits = 4,
> .bbt_options = NAND_BBT_USE_FLASH,
> };
> diff --git a/drivers/mtd/nand/raw/cafe_nand.c b/drivers/mtd/nand/raw/cafe_nand.c
> index 92173790f20b..2bf8ab542e38 100644
> --- a/drivers/mtd/nand/raw/cafe_nand.c
> +++ b/drivers/mtd/nand/raw/cafe_nand.c
> @@ -629,7 +629,8 @@ static int cafe_nand_attach_chip(struct nand_chip *chip)
> goto out_free_dma;
> }
>
> - cafe->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
> + cafe->nand.ecc.mode = NAND_ECC_HW;
> + cafe->nand.ecc.placement = NAND_ECC_PLACEMENT_INTERLEAVED;
> cafe->nand.ecc.size = mtd->writesize;
> cafe->nand.ecc.bytes = 14;
> cafe->nand.ecc.strength = 4;
> diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/davinci_nand.c
> index d975a62caaa5..2e5d6c113b56 100644
> --- a/drivers/mtd/nand/raw/davinci_nand.c
> +++ b/drivers/mtd/nand/raw/davinci_nand.c
> @@ -168,7 +168,7 @@ static int nand_davinci_correct_1bit(struct nand_chip *chip, u_char *dat,
> /*
> * 4-bit hardware ECC ... context maintained over entire AEMIF
> *
> - * This is a syndrome engine, but we avoid NAND_ECC_HW_SYNDROME
> + * This is a syndrome engine, but we avoid NAND_ECC_PLACEMENT_INTERLEAVED
> * since that forces use of a problematic "infix OOB" layout.
> * Among other things, it trashes manufacturer bad block markers.
> * Also, and specific to this hardware, it ECC-protects the "prepad"
> @@ -851,6 +851,7 @@ static int nand_davinci_probe(struct platform_device *pdev)
>
> /* Use board-specific ECC config */
> info->chip.ecc.mode = pdata->ecc_mode;
> + info->chip.ecc.placement = pdata->ecc_placement;
>
> spin_lock_irq(&davinci_nand_lock);
>
> @@ -897,7 +898,7 @@ static int nand_davinci_remove(struct platform_device *pdev)
> int ret;
>
> spin_lock_irq(&davinci_nand_lock);
> - if (info->chip.ecc.mode == NAND_ECC_HW_SYNDROME)
> + if (info->chip.ecc.placement == NAND_ECC_PLACEMENT_INTERLEAVED)
> ecc4_busy = false;
> spin_unlock_irq(&davinci_nand_lock);
>
> diff --git a/drivers/mtd/nand/raw/denali.c b/drivers/mtd/nand/raw/denali.c
> index 4e6e1578aa2d..514a97ea4450 100644
> --- a/drivers/mtd/nand/raw/denali.c
> +++ b/drivers/mtd/nand/raw/denali.c
> @@ -1237,7 +1237,8 @@ int denali_chip_init(struct denali_controller *denali,
> chip->bbt_options |= NAND_BBT_USE_FLASH;
> chip->bbt_options |= NAND_BBT_NO_OOB;
> chip->options |= NAND_NO_SUBPAGE_WRITE;
> - chip->ecc.mode = NAND_ECC_HW_SYNDROME;
> + chip->ecc.mode = NAND_ECC_HW;
> + chip->ecc.placement = NAND_ECC_PLACEMENT_INTERLEAVED;
> chip->ecc.read_page = denali_read_page;
> chip->ecc.write_page = denali_write_page;
> chip->ecc.read_page_raw = denali_read_page_raw;
> diff --git a/drivers/mtd/nand/raw/diskonchip.c b/drivers/mtd/nand/raw/diskonchip.c
> index 43721863a0d8..40360352136b 100644
> --- a/drivers/mtd/nand/raw/diskonchip.c
> +++ b/drivers/mtd/nand/raw/diskonchip.c
> @@ -1456,7 +1456,8 @@ static int __init doc_probe(unsigned long physadr)
> nand->ecc.calculate = doc200x_calculate_ecc;
> nand->ecc.correct = doc200x_correct_data;
>
> - nand->ecc.mode = NAND_ECC_HW_SYNDROME;
> + nand->ecc.mode = NAND_ECC_HW;
> + nand->ecc.placement = NAND_ECC_PLACEMENT_INTERLEAVED;
> nand->ecc.size = 512;
> nand->ecc.bytes = 6;
> nand->ecc.strength = 2;
> diff --git a/drivers/mtd/nand/raw/lpc32xx_slc.c b/drivers/mtd/nand/raw/lpc32xx_slc.c
> index b151fd000815..ccb189c8e343 100644
> --- a/drivers/mtd/nand/raw/lpc32xx_slc.c
> +++ b/drivers/mtd/nand/raw/lpc32xx_slc.c
> @@ -881,7 +881,8 @@ static int lpc32xx_nand_probe(struct platform_device *pdev)
> platform_set_drvdata(pdev, host);
>
> /* NAND callbacks for LPC32xx SLC hardware */
> - chip->ecc.mode = NAND_ECC_HW_SYNDROME;
> + chip->ecc.mode = NAND_ECC_HW;
> + chip->ecc.placement = NAND_ECC_PLACEMENT_INTERLEAVED;
> chip->legacy.read_byte = lpc32xx_nand_read_byte;
> chip->legacy.read_buf = lpc32xx_nand_read_buf;
> chip->legacy.write_buf = lpc32xx_nand_write_buf;
> diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
> index 4d2d444f9db9..9fbd2a474b62 100644
> --- a/drivers/mtd/nand/raw/nand_base.c
> +++ b/drivers/mtd/nand/raw/nand_base.c
> @@ -5772,61 +5772,74 @@ static int nand_scan_tail(struct nand_chip *chip)
>
> switch (ecc->mode) {
> case NAND_ECC_HW:
> - /* Use standard hwecc read page function? */
> - if (!ecc->read_page)
> - ecc->read_page = nand_read_page_hwecc;
> - if (!ecc->write_page)
> - ecc->write_page = nand_write_page_hwecc;
> - if (!ecc->read_page_raw)
> - ecc->read_page_raw = nand_read_page_raw;
> - if (!ecc->write_page_raw)
> - ecc->write_page_raw = nand_write_page_raw;
> - if (!ecc->read_oob)
> - ecc->read_oob = nand_read_oob_std;
> - if (!ecc->write_oob)
> - ecc->write_oob = nand_write_oob_std;
> - if (!ecc->read_subpage)
> - ecc->read_subpage = nand_read_subpage;
> - if (!ecc->write_subpage && ecc->hwctl && ecc->calculate)
> - ecc->write_subpage = nand_write_subpage_hwecc;
> - fallthrough;
> - case NAND_ECC_HW_SYNDROME:
> - if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
> - (!ecc->read_page ||
> - ecc->read_page == nand_read_page_hwecc ||
> - !ecc->write_page ||
> - ecc->write_page == nand_write_page_hwecc)) {
> - WARN(1, "No ECC functions supplied; hardware ECC not possible\n");
> - ret = -EINVAL;
> - goto err_nand_manuf_cleanup;
> - }
> - /* Use standard syndrome read/write page function? */
> - if (!ecc->read_page)
> - ecc->read_page = nand_read_page_syndrome;
> - if (!ecc->write_page)
> - ecc->write_page = nand_write_page_syndrome;
> - if (!ecc->read_page_raw)
> - ecc->read_page_raw = nand_read_page_raw_syndrome;
> - if (!ecc->write_page_raw)
> - ecc->write_page_raw = nand_write_page_raw_syndrome;
> - if (!ecc->read_oob)
> - ecc->read_oob = nand_read_oob_syndrome;
> - if (!ecc->write_oob)
> - ecc->write_oob = nand_write_oob_syndrome;
> + switch (ecc->placement) {
> + case NAND_ECC_PLACEMENT_UNKNOWN:
> + case NAND_ECC_PLACEMENT_OOB:
> + /* Use standard hwecc read page function? */
> + if (!ecc->read_page)
> + ecc->read_page = nand_read_page_hwecc;
> + if (!ecc->write_page)
> + ecc->write_page = nand_write_page_hwecc;
> + if (!ecc->read_page_raw)
> + ecc->read_page_raw = nand_read_page_raw;
> + if (!ecc->write_page_raw)
> + ecc->write_page_raw = nand_write_page_raw;
> + if (!ecc->read_oob)
> + ecc->read_oob = nand_read_oob_std;
> + if (!ecc->write_oob)
> + ecc->write_oob = nand_write_oob_std;
> + if (!ecc->read_subpage)
> + ecc->read_subpage = nand_read_subpage;
> + if (!ecc->write_subpage && ecc->hwctl && ecc->calculate)
> + ecc->write_subpage = nand_write_subpage_hwecc;
> + fallthrough;
>
> - if (mtd->writesize >= ecc->size) {
> - if (!ecc->strength) {
> - WARN(1, "Driver must set ecc.strength when using hardware ECC\n");
> + case NAND_ECC_PLACEMENT_INTERLEAVED:
> + if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
> + (!ecc->read_page ||
> + ecc->read_page == nand_read_page_hwecc ||
> + !ecc->write_page ||
> + ecc->write_page == nand_write_page_hwecc)) {
> + WARN(1, "No ECC functions supplied; hardware ECC not possible\n");
> ret = -EINVAL;
> goto err_nand_manuf_cleanup;
> }
> + /* Use standard syndrome read/write page function? */
> + if (!ecc->read_page)
> + ecc->read_page = nand_read_page_syndrome;
> + if (!ecc->write_page)
> + ecc->write_page = nand_write_page_syndrome;
> + if (!ecc->read_page_raw)
> + ecc->read_page_raw = nand_read_page_raw_syndrome;
> + if (!ecc->write_page_raw)
> + ecc->write_page_raw = nand_write_page_raw_syndrome;
> + if (!ecc->read_oob)
> + ecc->read_oob = nand_read_oob_syndrome;
> + if (!ecc->write_oob)
> + ecc->write_oob = nand_write_oob_syndrome;
> +
> + if (mtd->writesize >= ecc->size) {
> + if (!ecc->strength) {
> + WARN(1, "Driver must set ecc.strength when using hardware ECC\n");
> + ret = -EINVAL;
> + goto err_nand_manuf_cleanup;
> + }
> + break;
> + }
> + pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
> + ecc->size, mtd->writesize);
> + ecc->mode = NAND_ECC_SOFT;
> + ecc->algo = NAND_ECC_HAMMING;
> break;
> +
> + default:
> + pr_warn("Invalid NAND_ECC_PLACEMENT %d\n",
> + ecc->placement);
> + ret = -EINVAL;
> + goto err_nand_manuf_cleanup;
> }
> - pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
> - ecc->size, mtd->writesize);
> - ecc->mode = NAND_ECC_SOFT;
> - ecc->algo = NAND_ECC_HAMMING;
> fallthrough;
> +
> case NAND_ECC_SOFT:
> ret = nand_set_ecc_soft_ops(chip);
> if (ret) {
> diff --git a/drivers/mtd/nand/raw/r852.c b/drivers/mtd/nand/raw/r852.c
> index f865e3a47b01..f0988cda4479 100644
> --- a/drivers/mtd/nand/raw/r852.c
> +++ b/drivers/mtd/nand/raw/r852.c
> @@ -859,7 +859,8 @@ static int r852_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
> chip->legacy.write_buf = r852_write_buf;
>
> /* ecc */
> - chip->ecc.mode = NAND_ECC_HW_SYNDROME;
> + chip->ecc.mode = NAND_ECC_HW;
> + chip->ecc.placement = NAND_ECC_PLACEMENT_INTERLEAVED;
> chip->ecc.size = R852_DMA_LEN;
> chip->ecc.bytes = SM_OOB_SIZE;
> chip->ecc.strength = 2;
> diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h
> index 5e014807e050..f6ffd174abb7 100644
> --- a/include/linux/mtd/rawnand.h
> +++ b/include/linux/mtd/rawnand.h
> @@ -325,6 +325,7 @@ static const struct nand_ecc_caps __name = { \
> /**
> * struct nand_ecc_ctrl - Control structure for ECC
> * @mode: ECC mode
> + * @placement: OOB bytes placement
> * @algo: ECC algorithm
> * @steps: number of ECC steps per page
> * @size: data bytes per ECC step
> @@ -352,7 +353,7 @@ static const struct nand_ecc_caps __name = { \
> * controller and always return contiguous in-band and
> * out-of-band data even if they're not stored
> * contiguously on the NAND chip (e.g.
> - * NAND_ECC_HW_SYNDROME interleaves in-band and
> + * NAND_ECC_PLACEMENT_INTERLEAVED interleaves in-band and
> * out-of-band data).
> * @write_page_raw: function to write a raw page without ECC. This function
> * should hide the specific layout used by the ECC
> @@ -360,7 +361,7 @@ static const struct nand_ecc_caps __name = { \
> * in-band and out-of-band data. ECC controller is
> * responsible for doing the appropriate transformations
> * to adapt to its specific layout (e.g.
> - * NAND_ECC_HW_SYNDROME interleaves in-band and
> + * NAND_ECC_PLACEMENT_INTERLEAVED interleaves in-band and
> * out-of-band data).
> * @read_page: function to read a page according to the ECC generator
> * requirements; returns maximum number of bitflips corrected in
> @@ -377,6 +378,7 @@ static const struct nand_ecc_caps __name = { \
> */
> struct nand_ecc_ctrl {
> enum nand_ecc_mode mode;
> + enum nand_ecc_placement placement;
> enum nand_ecc_algo algo;
> int steps;
> int size;
> diff --git a/include/linux/platform_data/mtd-davinci.h b/include/linux/platform_data/mtd-davinci.h
> index 03e92c71b3fa..3383101c233b 100644
> --- a/include/linux/platform_data/mtd-davinci.h
> +++ b/include/linux/platform_data/mtd-davinci.h
> @@ -69,6 +69,7 @@ struct davinci_nand_pdata { /* platform_data */
> * using it with large page chips.
> */
> enum nand_ecc_mode ecc_mode;
> + enum nand_ecc_placement ecc_placement;
> u8 ecc_bits;
>
> /* e.g. NAND_BUSWIDTH_16 */
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^ permalink raw reply
* Re: [PATCH v6 04/18] mtd: rawnand: Create a helper to retrieve the ECC placement
From: Boris Brezillon @ 2020-05-28 14:22 UTC (permalink / raw)
To: Miquel Raynal
Cc: Mark Rutland, devicetree, Vignesh Raghavendra, Tudor Ambarus,
Julien Su, Richard Weinberger, Weijie Gao, Paul Cercueil,
Rob Herring, linux-mtd, Thomas Petazzoni, Mason Yang,
Chuanhong Guo, linux-arm-kernel
In-Reply-To: <20200528113113.9166-5-miquel.raynal@bootlin.com>
On Thu, 28 May 2020 13:30:59 +0200
Miquel Raynal <miquel.raynal@bootlin.com> wrote:
> Use it from nand_dt_init() to initialize the ECC structure.
>
> This allows the deprecation of the hw_syndrome ECC mode.
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
> ---
> drivers/mtd/nand/raw/nand_base.c | 29 +++++++++++++++++++++++++++++
> 1 file changed, 29 insertions(+)
>
> diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
> index 9fbd2a474b62..fd0bfe9bf7ae 100644
> --- a/drivers/mtd/nand/raw/nand_base.c
> +++ b/drivers/mtd/nand/raw/nand_base.c
> @@ -5047,6 +5047,34 @@ static int of_get_nand_ecc_mode(struct device_node *np)
> return -ENODEV;
> }
>
> +enum nand_ecc_placement of_get_nand_ecc_placement(struct device_node *np)
> +{
> + enum nand_ecc_placement placement;
> + const char *pm;
> + int err;
> +
> + err = of_property_read_string(np, "nand-ecc-placement", &pm);
> + if (!err) {
> + for (placement = NAND_ECC_PLACEMENT_INTERLEAVED;
> + placement < ARRAY_SIZE(nand_ecc_placement); placement++) {
> + if (!strcasecmp(pm, nand_ecc_placement[placement]))
> + return placement;
> + }
> + }
> +
> + /*
> + * For backward compatibility we support few obsoleted values that don't
> + * have their mappings into the nand_ecc_placement enum anymore.
> + */
> + err = of_property_read_string(np, "nand-ecc-mode", &pm);
> + if (!err) {
> + if (!strcasecmp(pm, "hw_syndrome"))
> + return NAND_ECC_PLACEMENT_INTERLEAVED;
> + }
> +
> + return NAND_ECC_PLACEMENT_UNKNOWN;
> +}
> +
> static const char * const nand_ecc_algos[] = {
> [NAND_ECC_HAMMING] = "hamming",
> [NAND_ECC_BCH] = "bch",
> @@ -5143,6 +5171,7 @@ static int nand_dt_init(struct nand_chip *chip)
>
> ecc_mode = of_get_nand_ecc_mode(dn);
> ecc_algo = of_get_nand_ecc_algo(dn);
> + chip->ecc.placement = of_get_nand_ecc_placement(dn);
> ecc_strength = of_get_nand_ecc_strength(dn);
> ecc_step = of_get_nand_ecc_step_size(dn);
>
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^ permalink raw reply
* [PATCH v2 0/2] regmap: provide simple bitops and use them in a driver
From: Bartosz Golaszewski @ 2020-05-28 14:22 UTC (permalink / raw)
To: John Crispin, Sean Wang, Mark Lee, David S . Miller,
Jakub Kicinski, Matthias Brugger, Mark Brown
Cc: Stephane Le Provost, Bartosz Golaszewski, netdev, linux-kernel,
Fabien Parent, linux-mediatek, Andrew Perepech, Pedro Tsai,
linux-arm-kernel
From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
I noticed that oftentimes I use regmap_update_bits() for simple bit
setting or clearing. In this case the fourth argument is superfluous as
it's always 0 or equal to the mask argument.
This series proposes to add simple bit operations for setting, clearing
and testing specific bits with regmap.
The second patch uses all three in a driver that got recently picked into
the net-next tree.
The patches obviously target different trees so - if you're ok with
the change itself - I propose you pick the first one into your regmap
tree for v5.8 and then I'll resend the second patch to add the first
user for these macros for v5.9.
v1 -> v2:
- convert the new macros to static inline functions
Bartosz Golaszewski (2):
regmap: provide helpers for simple bit operations
net: ethernet: mtk-star-emac: use regmap bitops
drivers/base/regmap/regmap.c | 22 +++++
drivers/net/ethernet/mediatek/mtk_star_emac.c | 80 ++++++++-----------
include/linux/regmap.h | 36 +++++++++
3 files changed, 93 insertions(+), 45 deletions(-)
--
2.26.1
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^ permalink raw reply
* [PATCH v2 1/2] regmap: provide helpers for simple bit operations
From: Bartosz Golaszewski @ 2020-05-28 14:22 UTC (permalink / raw)
To: John Crispin, Sean Wang, Mark Lee, David S . Miller,
Jakub Kicinski, Matthias Brugger, Mark Brown
Cc: Stephane Le Provost, Bartosz Golaszewski, netdev, linux-kernel,
Fabien Parent, linux-mediatek, Andrew Perepech, Pedro Tsai,
linux-arm-kernel
In-Reply-To: <20200528142241.20466-1-brgl@bgdev.pl>
From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
In many instances regmap_update_bits() is used for simple bit setting
and clearing. In these cases the last argument is redundant and we can
hide it with a static inline function.
This adds three new helpers for simple bit operations: set_bits,
clear_bits and test_bits.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
---
drivers/base/regmap/regmap.c | 22 ++++++++++++++++++++++
include/linux/regmap.h | 36 ++++++++++++++++++++++++++++++++++++
2 files changed, 58 insertions(+)
diff --git a/drivers/base/regmap/regmap.c b/drivers/base/regmap/regmap.c
index 59f911e57719..30f659e0b4e4 100644
--- a/drivers/base/regmap/regmap.c
+++ b/drivers/base/regmap/regmap.c
@@ -2936,6 +2936,28 @@ int regmap_update_bits_base(struct regmap *map, unsigned int reg,
}
EXPORT_SYMBOL_GPL(regmap_update_bits_base);
+/**
+ * regmap_test_bits() - Check if all specified bits are set in a register.
+ *
+ * @map: Register map to operate on
+ * @reg: Register to read from
+ * @bits: Bits to test
+ *
+ * Returns -1 if the underlying regmap_read() fails, 0 if at least one of the
+ * tested bits is not set and 1 if all tested bits are set.
+ */
+int regmap_test_bits(struct regmap *map, unsigned int reg, unsigned int bits)
+{
+ unsigned int val, ret;
+
+ ret = regmap_read(map, reg, &val);
+ if (ret)
+ return ret;
+
+ return (val & bits) == bits ? 1 : 0;
+}
+EXPORT_SYMBOL_GPL(regmap_test_bits);
+
void regmap_async_complete_cb(struct regmap_async *async, int ret)
{
struct regmap *map = async->map;
diff --git a/include/linux/regmap.h b/include/linux/regmap.h
index 40b07168fd8e..ddf0baff195d 100644
--- a/include/linux/regmap.h
+++ b/include/linux/regmap.h
@@ -1111,6 +1111,21 @@ bool regmap_reg_in_ranges(unsigned int reg,
const struct regmap_range *ranges,
unsigned int nranges);
+static inline int regmap_set_bits(struct regmap *map,
+ unsigned int reg, unsigned int bits)
+{
+ return regmap_update_bits_base(map, reg, bits, bits,
+ NULL, false, false);
+}
+
+static inline int regmap_clear_bits(struct regmap *map,
+ unsigned int reg, unsigned int bits)
+{
+ return regmap_update_bits_base(map, reg, bits, 0, NULL, false, false);
+}
+
+int regmap_test_bits(struct regmap *map, unsigned int reg, unsigned int bits);
+
/**
* struct reg_field - Description of an register field
*
@@ -1410,6 +1425,27 @@ static inline int regmap_update_bits_base(struct regmap *map, unsigned int reg,
return -EINVAL;
}
+static inline int regmap_set_bits(struct regmap *map,
+ unsigned int reg, unsigned int bits)
+{
+ WARN_ONCE(1, "regmap API is disabled");
+ return -EINVAL;
+}
+
+static inline int regmap_clear_bits(struct regmap *map,
+ unsigned int reg, unsigned int bits)
+{
+ WARN_ONCE(1, "regmap API is disabled");
+ return -EINVAL;
+}
+
+static inline int regmap_test_bits(struct regmap *map,
+ unsigned int reg, unsigned int bits)
+{
+ WARN_ONCE(1, "regmap API is disabled");
+ return -EINVAL;
+}
+
static inline int regmap_field_update_bits_base(struct regmap_field *field,
unsigned int mask, unsigned int val,
bool *change, bool async, bool force)
--
2.26.1
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^ permalink raw reply related
* [PATCH v2 2/2] net: ethernet: mtk-star-emac: use regmap bitops
From: Bartosz Golaszewski @ 2020-05-28 14:22 UTC (permalink / raw)
To: John Crispin, Sean Wang, Mark Lee, David S . Miller,
Jakub Kicinski, Matthias Brugger, Mark Brown
Cc: Stephane Le Provost, Bartosz Golaszewski, netdev, linux-kernel,
Fabien Parent, linux-mediatek, Andrew Perepech, Pedro Tsai,
linux-arm-kernel
In-Reply-To: <20200528142241.20466-1-brgl@bgdev.pl>
From: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Shrink the code visually by replacing regmap_update_bits() with
appropriate regmap bit operations where applicable.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
---
drivers/net/ethernet/mediatek/mtk_star_emac.c | 80 ++++++++-----------
1 file changed, 35 insertions(+), 45 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_star_emac.c b/drivers/net/ethernet/mediatek/mtk_star_emac.c
index 8596ca0e60eb..326ac792a4a0 100644
--- a/drivers/net/ethernet/mediatek/mtk_star_emac.c
+++ b/drivers/net/ethernet/mediatek/mtk_star_emac.c
@@ -413,8 +413,8 @@ static void mtk_star_dma_unmap_tx(struct mtk_star_priv *priv,
static void mtk_star_nic_disable_pd(struct mtk_star_priv *priv)
{
- regmap_update_bits(priv->regs, MTK_STAR_REG_MAC_CFG,
- MTK_STAR_BIT_MAC_CFG_NIC_PD, 0);
+ regmap_clear_bits(priv->regs, MTK_STAR_REG_MAC_CFG,
+ MTK_STAR_BIT_MAC_CFG_NIC_PD);
}
/* Unmask the three interrupts we care about, mask all others. */
@@ -434,41 +434,38 @@ static void mtk_star_intr_disable(struct mtk_star_priv *priv)
static void mtk_star_intr_enable_tx(struct mtk_star_priv *priv)
{
- regmap_update_bits(priv->regs, MTK_STAR_REG_INT_MASK,
- MTK_STAR_BIT_INT_STS_TNTC, 0);
+ regmap_clear_bits(priv->regs, MTK_STAR_REG_INT_MASK,
+ MTK_STAR_BIT_INT_STS_TNTC);
}
static void mtk_star_intr_enable_rx(struct mtk_star_priv *priv)
{
- regmap_update_bits(priv->regs, MTK_STAR_REG_INT_MASK,
- MTK_STAR_BIT_INT_STS_FNRC, 0);
+ regmap_clear_bits(priv->regs, MTK_STAR_REG_INT_MASK,
+ MTK_STAR_BIT_INT_STS_FNRC);
}
static void mtk_star_intr_enable_stats(struct mtk_star_priv *priv)
{
- regmap_update_bits(priv->regs, MTK_STAR_REG_INT_MASK,
- MTK_STAR_REG_INT_STS_MIB_CNT_TH, 0);
+ regmap_clear_bits(priv->regs, MTK_STAR_REG_INT_MASK,
+ MTK_STAR_REG_INT_STS_MIB_CNT_TH);
}
static void mtk_star_intr_disable_tx(struct mtk_star_priv *priv)
{
- regmap_update_bits(priv->regs, MTK_STAR_REG_INT_MASK,
- MTK_STAR_BIT_INT_STS_TNTC,
- MTK_STAR_BIT_INT_STS_TNTC);
+ regmap_set_bits(priv->regs, MTK_STAR_REG_INT_MASK,
+ MTK_STAR_BIT_INT_STS_TNTC);
}
static void mtk_star_intr_disable_rx(struct mtk_star_priv *priv)
{
- regmap_update_bits(priv->regs, MTK_STAR_REG_INT_MASK,
- MTK_STAR_BIT_INT_STS_FNRC,
- MTK_STAR_BIT_INT_STS_FNRC);
+ regmap_set_bits(priv->regs, MTK_STAR_REG_INT_MASK,
+ MTK_STAR_BIT_INT_STS_FNRC);
}
static void mtk_star_intr_disable_stats(struct mtk_star_priv *priv)
{
- regmap_update_bits(priv->regs, MTK_STAR_REG_INT_MASK,
- MTK_STAR_REG_INT_STS_MIB_CNT_TH,
- MTK_STAR_REG_INT_STS_MIB_CNT_TH);
+ regmap_set_bits(priv->regs, MTK_STAR_REG_INT_MASK,
+ MTK_STAR_REG_INT_STS_MIB_CNT_TH);
}
static unsigned int mtk_star_intr_read(struct mtk_star_priv *priv)
@@ -524,12 +521,10 @@ static void mtk_star_dma_init(struct mtk_star_priv *priv)
static void mtk_star_dma_start(struct mtk_star_priv *priv)
{
- regmap_update_bits(priv->regs, MTK_STAR_REG_TX_DMA_CTRL,
- MTK_STAR_BIT_TX_DMA_CTRL_START,
- MTK_STAR_BIT_TX_DMA_CTRL_START);
- regmap_update_bits(priv->regs, MTK_STAR_REG_RX_DMA_CTRL,
- MTK_STAR_BIT_RX_DMA_CTRL_START,
- MTK_STAR_BIT_RX_DMA_CTRL_START);
+ regmap_set_bits(priv->regs, MTK_STAR_REG_TX_DMA_CTRL,
+ MTK_STAR_BIT_TX_DMA_CTRL_START);
+ regmap_set_bits(priv->regs, MTK_STAR_REG_RX_DMA_CTRL,
+ MTK_STAR_BIT_RX_DMA_CTRL_START);
}
static void mtk_star_dma_stop(struct mtk_star_priv *priv)
@@ -553,16 +548,14 @@ static void mtk_star_dma_disable(struct mtk_star_priv *priv)
static void mtk_star_dma_resume_rx(struct mtk_star_priv *priv)
{
- regmap_update_bits(priv->regs, MTK_STAR_REG_RX_DMA_CTRL,
- MTK_STAR_BIT_RX_DMA_CTRL_RESUME,
- MTK_STAR_BIT_RX_DMA_CTRL_RESUME);
+ regmap_set_bits(priv->regs, MTK_STAR_REG_RX_DMA_CTRL,
+ MTK_STAR_BIT_RX_DMA_CTRL_RESUME);
}
static void mtk_star_dma_resume_tx(struct mtk_star_priv *priv)
{
- regmap_update_bits(priv->regs, MTK_STAR_REG_TX_DMA_CTRL,
- MTK_STAR_BIT_TX_DMA_CTRL_RESUME,
- MTK_STAR_BIT_TX_DMA_CTRL_RESUME);
+ regmap_set_bits(priv->regs, MTK_STAR_REG_TX_DMA_CTRL,
+ MTK_STAR_BIT_TX_DMA_CTRL_RESUME);
}
static void mtk_star_set_mac_addr(struct net_device *ndev)
@@ -845,8 +838,8 @@ static int mtk_star_hash_wait_ok(struct mtk_star_priv *priv)
return ret;
/* Check the BIST_OK bit. */
- regmap_read(priv->regs, MTK_STAR_REG_HASH_CTRL, &val);
- if (!(val & MTK_STAR_BIT_HASH_CTRL_BIST_OK))
+ if (!regmap_test_bits(priv->regs, MTK_STAR_REG_HASH_CTRL,
+ MTK_STAR_BIT_HASH_CTRL_BIST_OK))
return -EIO;
return 0;
@@ -880,12 +873,10 @@ static int mtk_star_reset_hash_table(struct mtk_star_priv *priv)
if (ret)
return ret;
- regmap_update_bits(priv->regs, MTK_STAR_REG_HASH_CTRL,
- MTK_STAR_BIT_HASH_CTRL_BIST_EN,
- MTK_STAR_BIT_HASH_CTRL_BIST_EN);
- regmap_update_bits(priv->regs, MTK_STAR_REG_TEST1,
- MTK_STAR_BIT_TEST1_RST_HASH_MBIST,
- MTK_STAR_BIT_TEST1_RST_HASH_MBIST);
+ regmap_set_bits(priv->regs, MTK_STAR_REG_HASH_CTRL,
+ MTK_STAR_BIT_HASH_CTRL_BIST_EN);
+ regmap_set_bits(priv->regs, MTK_STAR_REG_TEST1,
+ MTK_STAR_BIT_TEST1_RST_HASH_MBIST);
return mtk_star_hash_wait_ok(priv);
}
@@ -1016,13 +1007,13 @@ static int mtk_star_enable(struct net_device *ndev)
return ret;
/* Setup the hashing algorithm */
- regmap_update_bits(priv->regs, MTK_STAR_REG_ARL_CFG,
- MTK_STAR_BIT_ARL_CFG_HASH_ALG |
- MTK_STAR_BIT_ARL_CFG_MISC_MODE, 0);
+ regmap_clear_bits(priv->regs, MTK_STAR_REG_ARL_CFG,
+ MTK_STAR_BIT_ARL_CFG_HASH_ALG |
+ MTK_STAR_BIT_ARL_CFG_MISC_MODE);
/* Don't strip VLAN tags */
- regmap_update_bits(priv->regs, MTK_STAR_REG_MAC_CFG,
- MTK_STAR_BIT_MAC_CFG_VLAN_STRIP, 0);
+ regmap_clear_bits(priv->regs, MTK_STAR_REG_MAC_CFG,
+ MTK_STAR_BIT_MAC_CFG_VLAN_STRIP);
/* Setup DMA */
mtk_star_dma_init(priv);
@@ -1204,9 +1195,8 @@ static void mtk_star_set_rx_mode(struct net_device *ndev)
int ret;
if (ndev->flags & IFF_PROMISC) {
- regmap_update_bits(priv->regs, MTK_STAR_REG_ARL_CFG,
- MTK_STAR_BIT_ARL_CFG_MISC_MODE,
- MTK_STAR_BIT_ARL_CFG_MISC_MODE);
+ regmap_set_bits(priv->regs, MTK_STAR_REG_ARL_CFG,
+ MTK_STAR_BIT_ARL_CFG_MISC_MODE);
} else if (netdev_mc_count(ndev) > MTK_STAR_HASHTABLE_MC_LIMIT ||
ndev->flags & IFF_ALLMULTI) {
for (i = 0; i < MTK_STAR_HASHTABLE_SIZE_MAX; i++) {
--
2.26.1
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^ permalink raw reply related
* Re: [PATCH v6 05/18] mtd: rawnand: Add a kernel doc to the ECC algorithm enumeration
From: Boris Brezillon @ 2020-05-28 14:26 UTC (permalink / raw)
To: Miquel Raynal
Cc: Mark Rutland, devicetree, Vignesh Raghavendra, Tudor Ambarus,
Julien Su, Richard Weinberger, Weijie Gao, Paul Cercueil,
Rob Herring, linux-mtd, Thomas Petazzoni, Mason Yang,
Chuanhong Guo, linux-arm-kernel
In-Reply-To: <20200528113113.9166-6-miquel.raynal@bootlin.com>
On Thu, 28 May 2020 13:31:00 +0200
Miquel Raynal <miquel.raynal@bootlin.com> wrote:
> Before moving it to the generic raw NAND core, ensure the enumeration
> is properly described.
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
> ---
> include/linux/mtd/rawnand.h | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h
> index f6ffd174abb7..6699ec7f4d40 100644
> --- a/include/linux/mtd/rawnand.h
> +++ b/include/linux/mtd/rawnand.h
> @@ -106,6 +106,13 @@ enum nand_ecc_placement {
> NAND_ECC_PLACEMENT_INTERLEAVED,
> };
>
> +/**
> + * enum nand_ecc_algo - NAND ECC algorithm
> + * @NAND_ECC_UNKNOWN: Unknown algorithm
> + * @NAND_ECC_HAMMING: Hamming algorithm
> + * @NAND_ECC_BCH: Bose-Chaudhuri-Hocquenghem algorithm
> + * @NAND_ECC_RS: Reed-Solomon algorithm
> + */
> enum nand_ecc_algo {
> NAND_ECC_UNKNOWN,
> NAND_ECC_HAMMING,
_______________________________________________
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^ permalink raw reply
* Re: [PATCH v6 06/18] mtd: rawnand: Rename the ECC algorithm enumeration items
From: Boris Brezillon @ 2020-05-28 14:26 UTC (permalink / raw)
To: Miquel Raynal
Cc: Mark Rutland, devicetree, Vignesh Raghavendra, Tudor Ambarus,
Julien Su, Richard Weinberger, Weijie Gao, Paul Cercueil,
Rob Herring, linux-mtd, Thomas Petazzoni, Mason Yang,
Chuanhong Guo, linux-arm-kernel
In-Reply-To: <20200528113113.9166-7-miquel.raynal@bootlin.com>
On Thu, 28 May 2020 13:31:01 +0200
Miquel Raynal <miquel.raynal@bootlin.com> wrote:
> NAND_ECC_ is not a meaningful prefix, use NAND_ECC_ALGO_ instead.
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
> ---
> drivers/mtd/nand/raw/ams-delta.c | 2 +-
> drivers/mtd/nand/raw/arasan-nand-controller.c | 2 +-
> drivers/mtd/nand/raw/atmel/nand-controller.c | 2 +-
> drivers/mtd/nand/raw/au1550nd.c | 2 +-
> drivers/mtd/nand/raw/brcmnand/brcmnand.c | 12 ++++-----
> drivers/mtd/nand/raw/davinci_nand.c | 8 +++---
> drivers/mtd/nand/raw/fsl_elbc_nand.c | 2 +-
> drivers/mtd/nand/raw/fsl_ifc_nand.c | 2 +-
> drivers/mtd/nand/raw/fsl_upm.c | 2 +-
> drivers/mtd/nand/raw/fsmc_nand.c | 2 +-
> drivers/mtd/nand/raw/gpio.c | 2 +-
> drivers/mtd/nand/raw/marvell_nand.c | 10 +++----
> drivers/mtd/nand/raw/mpc5121_nfc.c | 2 +-
> drivers/mtd/nand/raw/mxc_nand.c | 2 +-
> drivers/mtd/nand/raw/nand_base.c | 26 +++++++++----------
> drivers/mtd/nand/raw/nand_micron.c | 2 +-
> drivers/mtd/nand/raw/nandsim.c | 4 +--
> drivers/mtd/nand/raw/omap2.c | 2 +-
> drivers/mtd/nand/raw/orion_nand.c | 2 +-
> drivers/mtd/nand/raw/pasemi_nand.c | 2 +-
> drivers/mtd/nand/raw/plat_nand.c | 2 +-
> drivers/mtd/nand/raw/s3c2410.c | 4 +--
> drivers/mtd/nand/raw/sh_flctl.c | 2 +-
> drivers/mtd/nand/raw/socrates_nand.c | 2 +-
> drivers/mtd/nand/raw/tango_nand.c | 2 +-
> drivers/mtd/nand/raw/tegra_nand.c | 20 +++++++-------
> drivers/mtd/nand/raw/xway_nand.c | 2 +-
> include/linux/mtd/rawnand.h | 16 ++++++------
> 28 files changed, 70 insertions(+), 70 deletions(-)
>
> diff --git a/drivers/mtd/nand/raw/ams-delta.c b/drivers/mtd/nand/raw/ams-delta.c
> index 3711e7a0436c..72a44b2411c1 100644
> --- a/drivers/mtd/nand/raw/ams-delta.c
> +++ b/drivers/mtd/nand/raw/ams-delta.c
> @@ -261,7 +261,7 @@ static int gpio_nand_probe(struct platform_device *pdev)
> }
>
> this->ecc.mode = NAND_ECC_SOFT;
> - this->ecc.algo = NAND_ECC_HAMMING;
> + this->ecc.algo = NAND_ECC_ALGO_HAMMING;
>
> platform_set_drvdata(pdev, priv);
>
> diff --git a/drivers/mtd/nand/raw/arasan-nand-controller.c b/drivers/mtd/nand/raw/arasan-nand-controller.c
> index 7141dcccba3c..076736351bc6 100644
> --- a/drivers/mtd/nand/raw/arasan-nand-controller.c
> +++ b/drivers/mtd/nand/raw/arasan-nand-controller.c
> @@ -983,7 +983,7 @@ static int anfc_init_hw_ecc_controller(struct arasan_nfc *nfc,
> mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
>
> ecc->steps = mtd->writesize / ecc->size;
> - ecc->algo = NAND_ECC_BCH;
> + ecc->algo = NAND_ECC_ALGO_BCH;
> anand->ecc_bits = bch_gf_mag * ecc->strength;
> ecc->bytes = DIV_ROUND_UP(anand->ecc_bits, 8);
> anand->ecc_total = DIV_ROUND_UP(anand->ecc_bits * ecc->steps, 8);
> diff --git a/drivers/mtd/nand/raw/atmel/nand-controller.c b/drivers/mtd/nand/raw/atmel/nand-controller.c
> index 46a3724a788e..d9839461e460 100644
> --- a/drivers/mtd/nand/raw/atmel/nand-controller.c
> +++ b/drivers/mtd/nand/raw/atmel/nand-controller.c
> @@ -1099,7 +1099,7 @@ static int atmel_nand_pmecc_init(struct nand_chip *chip)
> if (IS_ERR(nand->pmecc))
> return PTR_ERR(nand->pmecc);
>
> - chip->ecc.algo = NAND_ECC_BCH;
> + chip->ecc.algo = NAND_ECC_ALGO_BCH;
> chip->ecc.size = req.ecc.sectorsize;
> chip->ecc.bytes = req.ecc.bytes / req.ecc.nsectors;
> chip->ecc.strength = req.ecc.strength;
> diff --git a/drivers/mtd/nand/raw/au1550nd.c b/drivers/mtd/nand/raw/au1550nd.c
> index f7b4f421b2b0..e9140bf5cbac 100644
> --- a/drivers/mtd/nand/raw/au1550nd.c
> +++ b/drivers/mtd/nand/raw/au1550nd.c
> @@ -295,7 +295,7 @@ static int au1550nd_probe(struct platform_device *pdev)
> ctx->controller.ops = &au1550nd_ops;
> this->controller = &ctx->controller;
> this->ecc.mode = NAND_ECC_SOFT;
> - this->ecc.algo = NAND_ECC_HAMMING;
> + this->ecc.algo = NAND_ECC_ALGO_HAMMING;
>
> if (pd->devwidth)
> this->options |= NAND_BUSWIDTH_16;
> diff --git a/drivers/mtd/nand/raw/brcmnand/brcmnand.c b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
> index 4a0a7053fb7a..2a9f2ff89fe7 100644
> --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
> +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
> @@ -2545,17 +2545,17 @@ static int brcmnand_setup_dev(struct brcmnand_host *host)
> return -EINVAL;
> }
>
> - if (chip->ecc.algo == NAND_ECC_UNKNOWN) {
> + if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN) {
> if (chip->ecc.strength == 1 && chip->ecc.size == 512)
> /* Default to Hamming for 1-bit ECC, if unspecified */
> - chip->ecc.algo = NAND_ECC_HAMMING;
> + chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
> else
> /* Otherwise, BCH */
> - chip->ecc.algo = NAND_ECC_BCH;
> + chip->ecc.algo = NAND_ECC_ALGO_BCH;
> }
>
> - if (chip->ecc.algo == NAND_ECC_HAMMING && (chip->ecc.strength != 1 ||
> - chip->ecc.size != 512)) {
> + if (chip->ecc.algo == NAND_ECC_ALGO_HAMMING &&
> + (chip->ecc.strength != 1 || chip->ecc.size != 512)) {
> dev_err(ctrl->dev, "invalid Hamming params: %d bits per %d bytes\n",
> chip->ecc.strength, chip->ecc.size);
> return -EINVAL;
> @@ -2574,7 +2574,7 @@ static int brcmnand_setup_dev(struct brcmnand_host *host)
>
> switch (chip->ecc.size) {
> case 512:
> - if (chip->ecc.algo == NAND_ECC_HAMMING)
> + if (chip->ecc.algo == NAND_ECC_ALGO_HAMMING)
> cfg->ecc_level = 15;
> else
> cfg->ecc_level = chip->ecc.strength;
> diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/davinci_nand.c
> index 2e5d6c113b56..3640c7e45e15 100644
> --- a/drivers/mtd/nand/raw/davinci_nand.c
> +++ b/drivers/mtd/nand/raw/davinci_nand.c
> @@ -593,11 +593,11 @@ static int davinci_nand_attach_chip(struct nand_chip *chip)
> pdata->ecc_bits = 0;
> /*
> * This driver expects Hamming based ECC when ecc_mode is set
> - * to NAND_ECC_SOFT. Force ecc.algo to NAND_ECC_HAMMING to
> + * to NAND_ECC_SOFT. Force ecc.algo to NAND_ECC_ALGO_HAMMING to
> * avoid adding an extra ->ecc_algo field to
> * davinci_nand_pdata.
> */
> - info->chip.ecc.algo = NAND_ECC_HAMMING;
> + info->chip.ecc.algo = NAND_ECC_ALGO_HAMMING;
> break;
> case NAND_ECC_HW:
> if (pdata->ecc_bits == 4) {
> @@ -629,7 +629,7 @@ static int davinci_nand_attach_chip(struct nand_chip *chip)
> info->chip.ecc.hwctl = nand_davinci_hwctl_4bit;
> info->chip.ecc.bytes = 10;
> info->chip.ecc.options = NAND_ECC_GENERIC_ERASED_CHECK;
> - info->chip.ecc.algo = NAND_ECC_BCH;
> + info->chip.ecc.algo = NAND_ECC_ALGO_BCH;
>
> /*
> * Update ECC layout if needed ... for 1-bit HW ECC, the
> @@ -656,7 +656,7 @@ static int davinci_nand_attach_chip(struct nand_chip *chip)
> info->chip.ecc.correct = nand_davinci_correct_1bit;
> info->chip.ecc.hwctl = nand_davinci_hwctl_1bit;
> info->chip.ecc.bytes = 3;
> - info->chip.ecc.algo = NAND_ECC_HAMMING;
> + info->chip.ecc.algo = NAND_ECC_ALGO_HAMMING;
> }
> info->chip.ecc.size = 512;
> info->chip.ecc.strength = pdata->ecc_bits;
> diff --git a/drivers/mtd/nand/raw/fsl_elbc_nand.c b/drivers/mtd/nand/raw/fsl_elbc_nand.c
> index 088692b2e27a..da89389faaae 100644
> --- a/drivers/mtd/nand/raw/fsl_elbc_nand.c
> +++ b/drivers/mtd/nand/raw/fsl_elbc_nand.c
> @@ -748,7 +748,7 @@ static int fsl_elbc_attach_chip(struct nand_chip *chip)
> } else {
> /* otherwise fall back to default software ECC */
> chip->ecc.mode = NAND_ECC_SOFT;
> - chip->ecc.algo = NAND_ECC_HAMMING;
> + chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
> }
> break;
>
> diff --git a/drivers/mtd/nand/raw/fsl_ifc_nand.c b/drivers/mtd/nand/raw/fsl_ifc_nand.c
> index 00ae7a910b03..b2ae759dd14e 100644
> --- a/drivers/mtd/nand/raw/fsl_ifc_nand.c
> +++ b/drivers/mtd/nand/raw/fsl_ifc_nand.c
> @@ -926,7 +926,7 @@ static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
> }
> } else {
> chip->ecc.mode = NAND_ECC_SOFT;
> - chip->ecc.algo = NAND_ECC_HAMMING;
> + chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
> }
>
> ret = fsl_ifc_sram_init(priv);
> diff --git a/drivers/mtd/nand/raw/fsl_upm.c b/drivers/mtd/nand/raw/fsl_upm.c
> index 627deb26db51..49592b7e03a3 100644
> --- a/drivers/mtd/nand/raw/fsl_upm.c
> +++ b/drivers/mtd/nand/raw/fsl_upm.c
> @@ -164,7 +164,7 @@ static int fun_chip_init(struct fsl_upm_nand *fun,
> fun->chip.legacy.read_buf = fun_read_buf;
> fun->chip.legacy.write_buf = fun_write_buf;
> fun->chip.ecc.mode = NAND_ECC_SOFT;
> - fun->chip.ecc.algo = NAND_ECC_HAMMING;
> + fun->chip.ecc.algo = NAND_ECC_ALGO_HAMMING;
> if (fun->mchip_count > 1)
> fun->chip.legacy.select_chip = fun_select_chip;
>
> diff --git a/drivers/mtd/nand/raw/fsmc_nand.c b/drivers/mtd/nand/raw/fsmc_nand.c
> index 3909752b14c5..ced570987e85 100644
> --- a/drivers/mtd/nand/raw/fsmc_nand.c
> +++ b/drivers/mtd/nand/raw/fsmc_nand.c
> @@ -911,7 +911,7 @@ static int fsmc_nand_attach_chip(struct nand_chip *nand)
> break;
>
> case NAND_ECC_SOFT:
> - if (nand->ecc.algo == NAND_ECC_BCH) {
> + if (nand->ecc.algo == NAND_ECC_ALGO_BCH) {
> dev_info(host->dev,
> "Using 4-bit SW BCH ECC scheme\n");
> break;
> diff --git a/drivers/mtd/nand/raw/gpio.c b/drivers/mtd/nand/raw/gpio.c
> index 938077e5c6a9..667807c7100b 100644
> --- a/drivers/mtd/nand/raw/gpio.c
> +++ b/drivers/mtd/nand/raw/gpio.c
> @@ -276,7 +276,7 @@ static int gpio_nand_probe(struct platform_device *pdev)
> nand_set_flash_node(chip, pdev->dev.of_node);
> chip->legacy.IO_ADDR_W = chip->legacy.IO_ADDR_R;
> chip->ecc.mode = NAND_ECC_SOFT;
> - chip->ecc.algo = NAND_ECC_HAMMING;
> + chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
> chip->options = gpiomtd->plat.options;
> chip->legacy.chip_delay = gpiomtd->plat.chip_delay;
> chip->legacy.cmd_ctrl = gpio_nand_cmd_ctrl;
> diff --git a/drivers/mtd/nand/raw/marvell_nand.c b/drivers/mtd/nand/raw/marvell_nand.c
> index 260a0430313e..3969cca7d925 100644
> --- a/drivers/mtd/nand/raw/marvell_nand.c
> +++ b/drivers/mtd/nand/raw/marvell_nand.c
> @@ -780,7 +780,7 @@ static void marvell_nfc_enable_hw_ecc(struct nand_chip *chip)
> * When enabling BCH, set threshold to 0 to always know the
> * number of corrected bitflips.
> */
> - if (chip->ecc.algo == NAND_ECC_BCH)
> + if (chip->ecc.algo == NAND_ECC_ALGO_BCH)
> writel_relaxed(NDECCCTRL_BCH_EN, nfc->regs + NDECCCTRL);
> }
> }
> @@ -792,7 +792,7 @@ static void marvell_nfc_disable_hw_ecc(struct nand_chip *chip)
>
> if (ndcr & NDCR_ECC_EN) {
> writel_relaxed(ndcr & ~NDCR_ECC_EN, nfc->regs + NDCR);
> - if (chip->ecc.algo == NAND_ECC_BCH)
> + if (chip->ecc.algo == NAND_ECC_ALGO_BCH)
> writel_relaxed(0, nfc->regs + NDECCCTRL);
> }
> }
> @@ -966,7 +966,7 @@ static int marvell_nfc_hw_ecc_check_bitflips(struct nand_chip *chip,
> if (ndsr & NDSR_CORERR) {
> writel_relaxed(ndsr, nfc->regs + NDSR);
>
> - if (chip->ecc.algo == NAND_ECC_BCH)
> + if (chip->ecc.algo == NAND_ECC_ALGO_BCH)
> bf = NDSR_ERRCNT(ndsr);
> else
> bf = 1;
> @@ -2215,7 +2215,7 @@ static int marvell_nand_hw_ecc_controller_init(struct mtd_info *mtd,
> ecc->size = l->data_bytes;
>
> if (ecc->strength == 1) {
> - chip->ecc.algo = NAND_ECC_HAMMING;
> + chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
> ecc->read_page_raw = marvell_nfc_hw_ecc_hmg_read_page_raw;
> ecc->read_page = marvell_nfc_hw_ecc_hmg_read_page;
> ecc->read_oob_raw = marvell_nfc_hw_ecc_hmg_read_oob_raw;
> @@ -2225,7 +2225,7 @@ static int marvell_nand_hw_ecc_controller_init(struct mtd_info *mtd,
> ecc->write_oob_raw = marvell_nfc_hw_ecc_hmg_write_oob_raw;
> ecc->write_oob = ecc->write_oob_raw;
> } else {
> - chip->ecc.algo = NAND_ECC_BCH;
> + chip->ecc.algo = NAND_ECC_ALGO_BCH;
> ecc->strength = 16;
> ecc->read_page_raw = marvell_nfc_hw_ecc_bch_read_page_raw;
> ecc->read_page = marvell_nfc_hw_ecc_bch_read_page;
> diff --git a/drivers/mtd/nand/raw/mpc5121_nfc.c b/drivers/mtd/nand/raw/mpc5121_nfc.c
> index 18ecb096a32d..a67eded226db 100644
> --- a/drivers/mtd/nand/raw/mpc5121_nfc.c
> +++ b/drivers/mtd/nand/raw/mpc5121_nfc.c
> @@ -689,7 +689,7 @@ static int mpc5121_nfc_probe(struct platform_device *op)
> chip->legacy.get_features = nand_get_set_features_notsupp;
> chip->bbt_options = NAND_BBT_USE_FLASH;
> chip->ecc.mode = NAND_ECC_SOFT;
> - chip->ecc.algo = NAND_ECC_HAMMING;
> + chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
>
> /* Support external chip-select logic on ADS5121 board */
> if (of_machine_is_compatible("fsl,mpc5121ads")) {
> diff --git a/drivers/mtd/nand/raw/mxc_nand.c b/drivers/mtd/nand/raw/mxc_nand.c
> index 09dacb83cb5a..c2e9759cfba8 100644
> --- a/drivers/mtd/nand/raw/mxc_nand.c
> +++ b/drivers/mtd/nand/raw/mxc_nand.c
> @@ -1846,7 +1846,7 @@ static int mxcnd_probe(struct platform_device *pdev)
> this->ecc.mode = NAND_ECC_HW;
> } else {
> this->ecc.mode = NAND_ECC_SOFT;
> - this->ecc.algo = NAND_ECC_HAMMING;
> + this->ecc.algo = NAND_ECC_ALGO_HAMMING;
> }
>
> /* NAND bus width determines access functions used by upper layer */
> diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
> index fd0bfe9bf7ae..4cf53b9dddee 100644
> --- a/drivers/mtd/nand/raw/nand_base.c
> +++ b/drivers/mtd/nand/raw/nand_base.c
> @@ -5076,9 +5076,9 @@ enum nand_ecc_placement of_get_nand_ecc_placement(struct device_node *np)
> }
>
> static const char * const nand_ecc_algos[] = {
> - [NAND_ECC_HAMMING] = "hamming",
> - [NAND_ECC_BCH] = "bch",
> - [NAND_ECC_RS] = "rs",
> + [NAND_ECC_ALGO_HAMMING] = "hamming",
> + [NAND_ECC_ALGO_BCH] = "bch",
> + [NAND_ECC_ALGO_RS] = "rs",
> };
>
> static enum nand_ecc_algo of_get_nand_ecc_algo(struct device_node *np)
> @@ -5089,7 +5089,7 @@ static enum nand_ecc_algo of_get_nand_ecc_algo(struct device_node *np)
>
> err = of_property_read_string(np, "nand-ecc-algo", &pm);
> if (!err) {
> - for (ecc_algo = NAND_ECC_HAMMING;
> + for (ecc_algo = NAND_ECC_ALGO_HAMMING;
> ecc_algo < ARRAY_SIZE(nand_ecc_algos);
> ecc_algo++) {
> if (!strcasecmp(pm, nand_ecc_algos[ecc_algo]))
> @@ -5104,12 +5104,12 @@ static enum nand_ecc_algo of_get_nand_ecc_algo(struct device_node *np)
> err = of_property_read_string(np, "nand-ecc-mode", &pm);
> if (!err) {
> if (!strcasecmp(pm, "soft"))
> - return NAND_ECC_HAMMING;
> + return NAND_ECC_ALGO_HAMMING;
> else if (!strcasecmp(pm, "soft_bch"))
> - return NAND_ECC_BCH;
> + return NAND_ECC_ALGO_BCH;
> }
>
> - return NAND_ECC_UNKNOWN;
> + return NAND_ECC_ALGO_UNKNOWN;
> }
>
> static int of_get_nand_ecc_step_size(struct device_node *np)
> @@ -5178,7 +5178,7 @@ static int nand_dt_init(struct nand_chip *chip)
> if (ecc_mode >= 0)
> chip->ecc.mode = ecc_mode;
>
> - if (ecc_algo != NAND_ECC_UNKNOWN)
> + if (ecc_algo != NAND_ECC_ALGO_UNKNOWN)
> chip->ecc.algo = ecc_algo;
>
> if (ecc_strength >= 0)
> @@ -5302,7 +5302,7 @@ static int nand_set_ecc_soft_ops(struct nand_chip *chip)
> return -EINVAL;
>
> switch (ecc->algo) {
> - case NAND_ECC_HAMMING:
> + case NAND_ECC_ALGO_HAMMING:
> ecc->calculate = nand_calculate_ecc;
> ecc->correct = nand_correct_data;
> ecc->read_page = nand_read_page_swecc;
> @@ -5323,7 +5323,7 @@ static int nand_set_ecc_soft_ops(struct nand_chip *chip)
> ecc->options |= NAND_ECC_SOFT_HAMMING_SM_ORDER;
>
> return 0;
> - case NAND_ECC_BCH:
> + case NAND_ECC_ALGO_BCH:
> if (!mtd_nand_has_bch()) {
> WARN(1, "CONFIG_MTD_NAND_ECC_SW_BCH not enabled\n");
> return -EINVAL;
> @@ -5763,7 +5763,7 @@ static int nand_scan_tail(struct nand_chip *chip)
> * If no default placement scheme is given, select an appropriate one.
> */
> if (!mtd->ooblayout &&
> - !(ecc->mode == NAND_ECC_SOFT && ecc->algo == NAND_ECC_BCH)) {
> + !(ecc->mode == NAND_ECC_SOFT && ecc->algo == NAND_ECC_ALGO_BCH)) {
> switch (mtd->oobsize) {
> case 8:
> case 16:
> @@ -5858,7 +5858,7 @@ static int nand_scan_tail(struct nand_chip *chip)
> pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
> ecc->size, mtd->writesize);
> ecc->mode = NAND_ECC_SOFT;
> - ecc->algo = NAND_ECC_HAMMING;
> + ecc->algo = NAND_ECC_ALGO_HAMMING;
> break;
>
> default:
> @@ -6124,7 +6124,7 @@ EXPORT_SYMBOL(nand_scan_with_ids);
> void nand_cleanup(struct nand_chip *chip)
> {
> if (chip->ecc.mode == NAND_ECC_SOFT &&
> - chip->ecc.algo == NAND_ECC_BCH)
> + chip->ecc.algo == NAND_ECC_ALGO_BCH)
> nand_bch_free((struct nand_bch_control *)chip->ecc.priv);
>
> nanddev_cleanup(&chip->base);
> diff --git a/drivers/mtd/nand/raw/nand_micron.c b/drivers/mtd/nand/raw/nand_micron.c
> index 3589b4fce0d4..a43b4d17bc69 100644
> --- a/drivers/mtd/nand/raw/nand_micron.c
> +++ b/drivers/mtd/nand/raw/nand_micron.c
> @@ -543,7 +543,7 @@ static int micron_nand_init(struct nand_chip *chip)
> chip->ecc.bytes = chip->base.eccreq.strength * 2;
> chip->ecc.size = 512;
> chip->ecc.strength = chip->base.eccreq.strength;
> - chip->ecc.algo = NAND_ECC_BCH;
> + chip->ecc.algo = NAND_ECC_ALGO_BCH;
> chip->ecc.read_page = micron_nand_read_page_on_die_ecc;
> chip->ecc.write_page = micron_nand_write_page_on_die_ecc;
>
> diff --git a/drivers/mtd/nand/raw/nandsim.c b/drivers/mtd/nand/raw/nandsim.c
> index 0a5cb77966cc..9bcf1b9d4987 100644
> --- a/drivers/mtd/nand/raw/nandsim.c
> +++ b/drivers/mtd/nand/raw/nandsim.c
> @@ -2235,7 +2235,7 @@ static int ns_attach_chip(struct nand_chip *chip)
> }
>
> chip->ecc.mode = NAND_ECC_SOFT;
> - chip->ecc.algo = NAND_ECC_BCH;
> + chip->ecc.algo = NAND_ECC_ALGO_BCH;
> chip->ecc.size = 512;
> chip->ecc.strength = bch;
> chip->ecc.bytes = eccbytes;
> @@ -2275,7 +2275,7 @@ static int __init ns_init_module(void)
> nand_set_controller_data(chip, (void *)ns);
>
> chip->ecc.mode = NAND_ECC_SOFT;
> - chip->ecc.algo = NAND_ECC_HAMMING;
> + chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
> /* The NAND_SKIP_BBTSCAN option is necessary for 'overridesize' */
> /* and 'badblocks' parameters to work */
> chip->options |= NAND_SKIP_BBTSCAN;
> diff --git a/drivers/mtd/nand/raw/omap2.c b/drivers/mtd/nand/raw/omap2.c
> index eb7fcfd9276b..967ddbda1c48 100644
> --- a/drivers/mtd/nand/raw/omap2.c
> +++ b/drivers/mtd/nand/raw/omap2.c
> @@ -2011,7 +2011,7 @@ static int omap_nand_attach_chip(struct nand_chip *chip)
> */
> if (info->ecc_opt == OMAP_ECC_HAM1_CODE_SW) {
> chip->ecc.mode = NAND_ECC_SOFT;
> - chip->ecc.algo = NAND_ECC_HAMMING;
> + chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
> return 0;
> }
>
> diff --git a/drivers/mtd/nand/raw/orion_nand.c b/drivers/mtd/nand/raw/orion_nand.c
> index 880b54ca1b41..7a5cfa3d883f 100644
> --- a/drivers/mtd/nand/raw/orion_nand.c
> +++ b/drivers/mtd/nand/raw/orion_nand.c
> @@ -140,7 +140,7 @@ static int __init orion_nand_probe(struct platform_device *pdev)
> nc->legacy.cmd_ctrl = orion_nand_cmd_ctrl;
> nc->legacy.read_buf = orion_nand_read_buf;
> nc->ecc.mode = NAND_ECC_SOFT;
> - nc->ecc.algo = NAND_ECC_HAMMING;
> + nc->ecc.algo = NAND_ECC_ALGO_HAMMING;
>
> if (board->chip_delay)
> nc->legacy.chip_delay = board->chip_delay;
> diff --git a/drivers/mtd/nand/raw/pasemi_nand.c b/drivers/mtd/nand/raw/pasemi_nand.c
> index d8eca8c3fdcd..3eddc284614d 100644
> --- a/drivers/mtd/nand/raw/pasemi_nand.c
> +++ b/drivers/mtd/nand/raw/pasemi_nand.c
> @@ -133,7 +133,7 @@ static int pasemi_nand_probe(struct platform_device *ofdev)
> chip->legacy.write_buf = pasemi_write_buf;
> chip->legacy.chip_delay = 0;
> chip->ecc.mode = NAND_ECC_SOFT;
> - chip->ecc.algo = NAND_ECC_HAMMING;
> + chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
>
> /* Enable the following for a flash based bad block table */
> chip->bbt_options = NAND_BBT_USE_FLASH;
> diff --git a/drivers/mtd/nand/raw/plat_nand.c b/drivers/mtd/nand/raw/plat_nand.c
> index 556182f26057..dbc089c8872f 100644
> --- a/drivers/mtd/nand/raw/plat_nand.c
> +++ b/drivers/mtd/nand/raw/plat_nand.c
> @@ -67,7 +67,7 @@ static int plat_nand_probe(struct platform_device *pdev)
> data->chip.bbt_options |= pdata->chip.bbt_options;
>
> data->chip.ecc.mode = NAND_ECC_SOFT;
> - data->chip.ecc.algo = NAND_ECC_HAMMING;
> + data->chip.ecc.algo = NAND_ECC_ALGO_HAMMING;
>
> platform_set_drvdata(pdev, data);
>
> diff --git a/drivers/mtd/nand/raw/s3c2410.c b/drivers/mtd/nand/raw/s3c2410.c
> index f86dff311464..dfe5a0f07385 100644
> --- a/drivers/mtd/nand/raw/s3c2410.c
> +++ b/drivers/mtd/nand/raw/s3c2410.c
> @@ -938,11 +938,11 @@ static int s3c2410_nand_attach_chip(struct nand_chip *chip)
> case NAND_ECC_SOFT:
> /*
> * This driver expects Hamming based ECC when ecc_mode is set
> - * to NAND_ECC_SOFT. Force ecc.algo to NAND_ECC_HAMMING to
> + * to NAND_ECC_SOFT. Force ecc.algo to NAND_ECC_ALGO_HAMMING to
> * avoid adding an extra ecc_algo field to
> * s3c2410_platform_nand.
> */
> - chip->ecc.algo = NAND_ECC_HAMMING;
> + chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
> dev_info(info->device, "soft ECC\n");
> break;
>
> diff --git a/drivers/mtd/nand/raw/sh_flctl.c b/drivers/mtd/nand/raw/sh_flctl.c
> index a661b8bb2dd5..9dbd6fdbe264 100644
> --- a/drivers/mtd/nand/raw/sh_flctl.c
> +++ b/drivers/mtd/nand/raw/sh_flctl.c
> @@ -1045,7 +1045,7 @@ static int flctl_chip_attach_chip(struct nand_chip *chip)
> flctl->flcmncr_base |= _4ECCEN;
> } else {
> chip->ecc.mode = NAND_ECC_SOFT;
> - chip->ecc.algo = NAND_ECC_HAMMING;
> + chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
> }
>
> return 0;
> diff --git a/drivers/mtd/nand/raw/socrates_nand.c b/drivers/mtd/nand/raw/socrates_nand.c
> index 243b34cfbc1b..72a3a7f98282 100644
> --- a/drivers/mtd/nand/raw/socrates_nand.c
> +++ b/drivers/mtd/nand/raw/socrates_nand.c
> @@ -154,7 +154,7 @@ static int socrates_nand_probe(struct platform_device *ofdev)
> nand_chip->legacy.dev_ready = socrates_nand_device_ready;
>
> nand_chip->ecc.mode = NAND_ECC_SOFT; /* enable ECC */
> - nand_chip->ecc.algo = NAND_ECC_HAMMING;
> + nand_chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
>
> /* TODO: I have no idea what real delay is. */
> nand_chip->legacy.chip_delay = 20; /* 20us command delay time */
> diff --git a/drivers/mtd/nand/raw/tango_nand.c b/drivers/mtd/nand/raw/tango_nand.c
> index 246871e01027..2154b6f860dd 100644
> --- a/drivers/mtd/nand/raw/tango_nand.c
> +++ b/drivers/mtd/nand/raw/tango_nand.c
> @@ -512,7 +512,7 @@ static int tango_attach_chip(struct nand_chip *chip)
> struct nand_ecc_ctrl *ecc = &chip->ecc;
>
> ecc->mode = NAND_ECC_HW;
> - ecc->algo = NAND_ECC_BCH;
> + ecc->algo = NAND_ECC_ALGO_BCH;
> ecc->bytes = DIV_ROUND_UP(ecc->strength * FIELD_ORDER, BITS_PER_BYTE);
>
> ecc->read_page_raw = tango_read_page_raw;
> diff --git a/drivers/mtd/nand/raw/tegra_nand.c b/drivers/mtd/nand/raw/tegra_nand.c
> index f9d046b2cd3b..e2e13effc8a6 100644
> --- a/drivers/mtd/nand/raw/tegra_nand.c
> +++ b/drivers/mtd/nand/raw/tegra_nand.c
> @@ -479,7 +479,7 @@ static void tegra_nand_hw_ecc(struct tegra_nand_controller *ctrl,
> {
> struct tegra_nand_chip *nand = to_tegra_chip(chip);
>
> - if (chip->ecc.algo == NAND_ECC_BCH && enable)
> + if (chip->ecc.algo == NAND_ECC_ALGO_BCH && enable)
> writel_relaxed(nand->bch_config, ctrl->regs + BCH_CONFIG);
> else
> writel_relaxed(0, ctrl->regs + BCH_CONFIG);
> @@ -877,7 +877,7 @@ static int tegra_nand_select_strength(struct nand_chip *chip, int oobsize)
> int strength_len, bits_per_step;
>
> switch (chip->ecc.algo) {
> - case NAND_ECC_RS:
> + case NAND_ECC_ALGO_RS:
> bits_per_step = BITS_PER_STEP_RS;
> if (chip->options & NAND_IS_BOOT_MEDIUM) {
> strength = rs_strength_bootable;
> @@ -887,7 +887,7 @@ static int tegra_nand_select_strength(struct nand_chip *chip, int oobsize)
> strength_len = ARRAY_SIZE(rs_strength);
> }
> break;
> - case NAND_ECC_BCH:
> + case NAND_ECC_ALGO_BCH:
> bits_per_step = BITS_PER_STEP_BCH;
> if (chip->options & NAND_IS_BOOT_MEDIUM) {
> strength = bch_strength_bootable;
> @@ -935,14 +935,14 @@ static int tegra_nand_attach_chip(struct nand_chip *chip)
> if (chip->options & NAND_BUSWIDTH_16)
> nand->config |= CONFIG_BUS_WIDTH_16;
>
> - if (chip->ecc.algo == NAND_ECC_UNKNOWN) {
> + if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN) {
> if (mtd->writesize < 2048)
> - chip->ecc.algo = NAND_ECC_RS;
> + chip->ecc.algo = NAND_ECC_ALGO_RS;
> else
> - chip->ecc.algo = NAND_ECC_BCH;
> + chip->ecc.algo = NAND_ECC_ALGO_BCH;
> }
>
> - if (chip->ecc.algo == NAND_ECC_BCH && mtd->writesize < 2048) {
> + if (chip->ecc.algo == NAND_ECC_ALGO_BCH && mtd->writesize < 2048) {
> dev_err(ctrl->dev, "BCH supports 2K or 4K page size only\n");
> return -EINVAL;
> }
> @@ -963,7 +963,7 @@ static int tegra_nand_attach_chip(struct nand_chip *chip)
> CONFIG_SKIP_SPARE_SIZE_4;
>
> switch (chip->ecc.algo) {
> - case NAND_ECC_RS:
> + case NAND_ECC_ALGO_RS:
> bits_per_step = BITS_PER_STEP_RS * chip->ecc.strength;
> mtd_set_ooblayout(mtd, &tegra_nand_oob_rs_ops);
> nand->config_ecc |= CONFIG_HW_ECC | CONFIG_ECC_SEL |
> @@ -984,7 +984,7 @@ static int tegra_nand_attach_chip(struct nand_chip *chip)
> return -EINVAL;
> }
> break;
> - case NAND_ECC_BCH:
> + case NAND_ECC_ALGO_BCH:
> bits_per_step = BITS_PER_STEP_BCH * chip->ecc.strength;
> mtd_set_ooblayout(mtd, &tegra_nand_oob_bch_ops);
> nand->bch_config = BCH_ENABLE;
> @@ -1013,7 +1013,7 @@ static int tegra_nand_attach_chip(struct nand_chip *chip)
> }
>
> dev_info(ctrl->dev, "Using %s with strength %d per 512 byte step\n",
> - chip->ecc.algo == NAND_ECC_BCH ? "BCH" : "RS",
> + chip->ecc.algo == NAND_ECC_ALGO_BCH ? "BCH" : "RS",
> chip->ecc.strength);
>
> chip->ecc.bytes = DIV_ROUND_UP(bits_per_step, BITS_PER_BYTE);
> diff --git a/drivers/mtd/nand/raw/xway_nand.c b/drivers/mtd/nand/raw/xway_nand.c
> index 94bfba994326..909072e82a68 100644
> --- a/drivers/mtd/nand/raw/xway_nand.c
> +++ b/drivers/mtd/nand/raw/xway_nand.c
> @@ -181,7 +181,7 @@ static int xway_nand_probe(struct platform_device *pdev)
> data->chip.legacy.chip_delay = 30;
>
> data->chip.ecc.mode = NAND_ECC_SOFT;
> - data->chip.ecc.algo = NAND_ECC_HAMMING;
> + data->chip.ecc.algo = NAND_ECC_ALGO_HAMMING;
>
> platform_set_drvdata(pdev, data);
> nand_set_controller_data(&data->chip, data);
> diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h
> index 6699ec7f4d40..8d040312c301 100644
> --- a/include/linux/mtd/rawnand.h
> +++ b/include/linux/mtd/rawnand.h
> @@ -108,16 +108,16 @@ enum nand_ecc_placement {
>
> /**
> * enum nand_ecc_algo - NAND ECC algorithm
> - * @NAND_ECC_UNKNOWN: Unknown algorithm
> - * @NAND_ECC_HAMMING: Hamming algorithm
> - * @NAND_ECC_BCH: Bose-Chaudhuri-Hocquenghem algorithm
> - * @NAND_ECC_RS: Reed-Solomon algorithm
> + * @NAND_ECC_ALGO_UNKNOWN: Unknown algorithm
> + * @NAND_ECC_ALGO_HAMMING: Hamming algorithm
> + * @NAND_ECC_ALGO_BCH: Bose-Chaudhuri-Hocquenghem algorithm
> + * @NAND_ECC_ALGO_RS: Reed-Solomon algorithm
> */
> enum nand_ecc_algo {
> - NAND_ECC_UNKNOWN,
> - NAND_ECC_HAMMING,
> - NAND_ECC_BCH,
> - NAND_ECC_RS,
> + NAND_ECC_ALGO_UNKNOWN,
> + NAND_ECC_ALGO_HAMMING,
> + NAND_ECC_ALGO_BCH,
> + NAND_ECC_ALGO_RS,
> };
>
> /*
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^ permalink raw reply
* Re: [PATCH v6 08/18] mtd: rawnand: Use the new ECC engine type enumeration
From: Boris Brezillon @ 2020-05-28 14:31 UTC (permalink / raw)
To: Miquel Raynal
Cc: Mark Rutland, devicetree, Vignesh Raghavendra, Tudor Ambarus,
Julien Su, Richard Weinberger, Weijie Gao, Paul Cercueil,
Rob Herring, linux-mtd, Thomas Petazzoni, Mason Yang,
Chuanhong Guo, linux-arm-kernel
In-Reply-To: <20200528113113.9166-9-miquel.raynal@bootlin.com>
On Thu, 28 May 2020 13:31:03 +0200
Miquel Raynal <miquel.raynal@bootlin.com> wrote:
> Mechanical switch from the legacy "mode" enumeration to the new
> "engine type" enumeration in drivers and board files.
>
> The device tree parsing is also updated to return the new enumeration
> from the old strings.
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
I didn't check all the changes, but I'm fine with the approach
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
> diff --git a/include/linux/platform_data/mtd-davinci.h b/include/linux/platform_data/mtd-davinci.h
> index 3383101c233b..dd474dd44848 100644
> --- a/include/linux/platform_data/mtd-davinci.h
> +++ b/include/linux/platform_data/mtd-davinci.h
> @@ -60,16 +60,16 @@ struct davinci_nand_pdata { /* platform_data */
> struct mtd_partition *parts;
> unsigned nr_parts;
>
> - /* none == NAND_ECC_NONE (strongly *not* advised!!)
> - * soft == NAND_ECC_SOFT
> - * else == NAND_ECC_HW, according to ecc_bits
> + /* none == NAND_ECC_ENGINE_TYPE_NONE (strongly *not* advised!!)
> + * soft == NAND_ECC_ENGINE_TYPE_SOFT
> + * else == NAND_ECC_ENGINE_TYPE_ON_HOST, according to ecc_bits
> *
> * All DaVinci-family chips support 1-bit hardware ECC.
> * Newer ones also support 4-bit ECC, but are awkward
> * using it with large page chips.
> */
> - enum nand_ecc_mode ecc_mode;
> - enum nand_ecc_placement ecc_placement;
> + enum nand_ecc_engine_type engine_type;
> + enum nand_ecc_placement ecc_placement;
Nitpick: if you want to use a space instead of tab, it should be done in
patch 3.
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^ permalink raw reply
* [PATCH] PCI: aardvark: Don't touch PCIe registers if no card connected
From: Pali Rohár @ 2020-05-28 14:31 UTC (permalink / raw)
To: Thomas Petazzoni, Lorenzo Pieralisi, Andrew Murray, Bjorn Helgaas,
Marek Behún, Remi Pommarel, Tomasz Maciej Nowak, Xogium
Cc: linux-pci, linux-kernel, linux-arm-kernel
When there is no PCIe card connected and advk_pcie_rd_conf() or
advk_pcie_wr_conf() is called for PCI bus which doesn't belong to emulated
root bridge, the aardvark driver throws the following error message:
advk-pcie d0070000.pcie: config read/write timed out
Obviously accessing PCIe registers of disconnected card is not possible.
Extend check in advk_pcie_valid_device() function for validating
availability of PCIe bus. If PCIe link is down, then the device is marked
as Not Found and the driver does not try to access these registers.
Signed-off-by: Pali Rohár <pali@kernel.org>
---
drivers/pci/controller/pci-aardvark.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c
index 90ff291c24f0..53a4cfd7d377 100644
--- a/drivers/pci/controller/pci-aardvark.c
+++ b/drivers/pci/controller/pci-aardvark.c
@@ -644,6 +644,9 @@ static bool advk_pcie_valid_device(struct advk_pcie *pcie, struct pci_bus *bus,
if ((bus->number == pcie->root_bus_nr) && PCI_SLOT(devfn) != 0)
return false;
+ if (bus->number != pcie->root_bus_nr && !advk_pcie_link_up(pcie))
+ return false;
+
return true;
}
--
2.20.1
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^ permalink raw reply related
* Re: [PATCH v6 14/18] mtd: nand: Add more parameters to the nand_ecc_props structure
From: Boris Brezillon @ 2020-05-28 14:34 UTC (permalink / raw)
To: Miquel Raynal
Cc: Mark Rutland, devicetree, Vignesh Raghavendra, Tudor Ambarus,
Julien Su, Richard Weinberger, Weijie Gao, Paul Cercueil,
Rob Herring, linux-mtd, Thomas Petazzoni, Mason Yang,
Chuanhong Guo, linux-arm-kernel
In-Reply-To: <20200528113113.9166-15-miquel.raynal@bootlin.com>
On Thu, 28 May 2020 13:31:09 +0200
Miquel Raynal <miquel.raynal@bootlin.com> wrote:
> Prepare the migration to the generic ECC framework by adding more
> fields to the nand_ecc_props structure which will be used widely to
> describe different kind of ECC properties.
>
> Doing this imposes to move the engine type, ECC placement and
> algorithm enumerations in a shared place: nand.h.
>
> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
> ---
> include/linux/mtd/nand.h | 52 +++++++++++++++++++++++++++++++++++++
> include/linux/mtd/rawnand.h | 44 -------------------------------
> 2 files changed, 52 insertions(+), 44 deletions(-)
>
> diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
> index 6add464fd18b..2e9af24936cd 100644
> --- a/include/linux/mtd/nand.h
> +++ b/include/linux/mtd/nand.h
> @@ -127,14 +127,66 @@ struct nand_page_io_req {
> int mode;
> };
>
> +/**
> + * enum nand_ecc_engine_type - NAND ECC engine type
> + * @NAND_ECC_ENGINE_TYPE_INVALID: Invalid value
> + * @NAND_ECC_ENGINE_TYPE_NONE: No ECC correction
> + * @NAND_ECC_ENGINE_TYPE_SOFT: Software ECC correction
> + * @NAND_ECC_ENGINE_TYPE_ON_HOST: On host hardware ECC correction
> + * @NAND_ECC_ENGINE_TYPE_ON_DIE: On chip hardware ECC correction
> + */
> +enum nand_ecc_engine_type {
> + NAND_ECC_ENGINE_TYPE_INVALID,
> + NAND_ECC_ENGINE_TYPE_NONE,
> + NAND_ECC_ENGINE_TYPE_SOFT,
> + NAND_ECC_ENGINE_TYPE_ON_HOST,
> + NAND_ECC_ENGINE_TYPE_ON_DIE,
> +};
> +
> +/**
> + * enum nand_ecc_placement - NAND ECC bytes placement
> + * @NAND_ECC_PLACEMENT_UNKNOWN: The actual position of the ECC bytes is unknown
> + * @NAND_ECC_PLACEMENT_OOB: The ECC bytes are located in the OOB area
> + * @NAND_ECC_PLACEMENT_INTERLEAVED: Syndrome layout, there are ECC bytes
> + * interleaved with regular data in the main
> + * area
> + */
> +enum nand_ecc_placement {
> + NAND_ECC_PLACEMENT_UNKNOWN,
> + NAND_ECC_PLACEMENT_OOB,
> + NAND_ECC_PLACEMENT_INTERLEAVED,
> +};
> +
> +/**
> + * enum nand_ecc_algo - NAND ECC algorithm
> + * @NAND_ECC_ALGO_UNKNOWN: Unknown algorithm
> + * @NAND_ECC_ALGO_HAMMING: Hamming algorithm
> + * @NAND_ECC_ALGO_BCH: Bose-Chaudhuri-Hocquenghem algorithm
> + * @NAND_ECC_ALGO_RS: Reed-Solomon algorithm
> + */
> +enum nand_ecc_algo {
> + NAND_ECC_ALGO_UNKNOWN,
> + NAND_ECC_ALGO_HAMMING,
> + NAND_ECC_ALGO_BCH,
> + NAND_ECC_ALGO_RS,
> +};
> +
> /**
> * struct nand_ecc_props - NAND ECC properties
> + * @engine_type: ECC engine type
> + * @placement: OOB placement (if relevant)
> + * @algo: ECC algorithm (if relevant)
> * @strength: ECC strength
> * @step_size: Number of bytes per step
> + * @flags: Misc properties
I'd like to hear more about that one. What is this about? I'd rather
not add a field if it's not needed.
> */
> struct nand_ecc_props {
> + enum nand_ecc_engine_type engine_type;
> + enum nand_ecc_placement placement;
> + enum nand_ecc_algo algo;
> unsigned int strength;
> unsigned int step_size;
> + unsigned int flags;
> };
>
> #define NAND_ECCREQ(str, stp) { .strength = (str), .step_size = (stp) }
> diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h
> index c3411a08ce61..8f7f1cce3b4b 100644
> --- a/include/linux/mtd/rawnand.h
> +++ b/include/linux/mtd/rawnand.h
> @@ -92,50 +92,6 @@ enum nand_ecc_mode {
> NAND_ECC_ON_DIE,
> };
>
> -/**
> - * enum nand_ecc_engine_type - NAND ECC engine type
> - * @NAND_ECC_ENGINE_TYPE_INVALID: Invalid value
> - * @NAND_ECC_ENGINE_TYPE_NONE: No ECC correction
> - * @NAND_ECC_ENGINE_TYPE_SOFT: Software ECC correction
> - * @NAND_ECC_ENGINE_TYPE_ON_HOST: On host hardware ECC correction
> - * @NAND_ECC_ENGINE_TYPE_ON_DIE: On chip hardware ECC correction
> - */
> -enum nand_ecc_engine_type {
> - NAND_ECC_ENGINE_TYPE_INVALID,
> - NAND_ECC_ENGINE_TYPE_NONE,
> - NAND_ECC_ENGINE_TYPE_SOFT,
> - NAND_ECC_ENGINE_TYPE_ON_HOST,
> - NAND_ECC_ENGINE_TYPE_ON_DIE,
> -};
> -
> -/**
> - * enum nand_ecc_placement - NAND ECC bytes placement
> - * @NAND_ECC_PLACEMENT_UNKNOWN: The actual position of the ECC bytes is unknown
> - * @NAND_ECC_PLACEMENT_OOB: The ECC bytes are located in the OOB area
> - * @NAND_ECC_PLACEMENT_INTERLEAVED: Syndrome layout, there are ECC bytes
> - * interleaved with regular data in the main
> - * area
> - */
> -enum nand_ecc_placement {
> - NAND_ECC_PLACEMENT_UNKNOWN,
> - NAND_ECC_PLACEMENT_OOB,
> - NAND_ECC_PLACEMENT_INTERLEAVED,
> -};
> -
> -/**
> - * enum nand_ecc_algo - NAND ECC algorithm
> - * @NAND_ECC_ALGO_UNKNOWN: Unknown algorithm
> - * @NAND_ECC_ALGO_HAMMING: Hamming algorithm
> - * @NAND_ECC_ALGO_BCH: Bose-Chaudhuri-Hocquenghem algorithm
> - * @NAND_ECC_ALGO_RS: Reed-Solomon algorithm
> - */
> -enum nand_ecc_algo {
> - NAND_ECC_ALGO_UNKNOWN,
> - NAND_ECC_ALGO_HAMMING,
> - NAND_ECC_ALGO_BCH,
> - NAND_ECC_ALGO_RS,
> -};
> -
> /*
> * Constants for Hardware ECC
> */
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* Re: [PATCH 07/21] drm/hisilicon/kirin: Use GEM CMA object functions
From: Emil Velikov @ 2020-05-28 14:34 UTC (permalink / raw)
To: Thomas Zimmermann
Cc: alexandre.belloni, linux-aspeed, Neil Armstrong, Dave Airlie,
Liviu Dudau, ML dri-devel, Paul Cercueil, Laurent Pinchart,
Mihail Atanassov, Sam Ravnborg, Marek Vašut, khilman,
Alexey Brodkin, Xinwei Kong, Xinliang Liu, ludovic.desroches,
Tomi Valkeinen, james qian wang (Arm Technology China),
NXP Linux Team, joel, Alexandre Torgue, Chen Feng, Sascha Hauer,
Alison Wang, Jyri Sarha, Chen-Yu Tsai, Vincent Abriou, LAKML,
Maxime Coquelin, bbrezillon, andrew, Philippe Cornu,
Yannick Fertre, Kieran Bingham, Sascha Hauer, Rongrong Zou,
Shawn Guo
In-Reply-To: <ccee78e2-8930-2de6-0b7c-0f1ad1e636f8@suse.de>
On Mon, 25 May 2020 at 13:41, Thomas Zimmermann <tzimmermann@suse.de> wrote:
>
> Hi Emil
>
> Am 22.05.20 um 20:11 schrieb Emil Velikov:
> > Hi Thomas,
> >
> > On Fri, 22 May 2020 at 14:53, Thomas Zimmermann <tzimmermann@suse.de> wrote:
> >>
> >> The kirin driver uses the default implementation for CMA functions; except
> >> for the .dumb_create callback. The __DRM_GEM_CMA_DRIVER_OPS macro now sets
> >> these defaults and .dumb_create in struct drm_driver. All remaining
> >> operations are provided by CMA GEM object functions.
> >>
> >> Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
> >> ---
> >> drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c | 12 +-----------
> >> 1 file changed, 1 insertion(+), 11 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
> >> index c339e632522a9..b1ffd7d43e562 100644
> >> --- a/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
> >> +++ b/drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c
> >> @@ -921,17 +921,7 @@ DEFINE_DRM_GEM_CMA_FOPS(ade_fops);
> >> static struct drm_driver ade_driver = {
> >> .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
> >> .fops = &ade_fops,
> >> - .gem_free_object_unlocked = drm_gem_cma_free_object,
> >> - .gem_vm_ops = &drm_gem_cma_vm_ops,
> >> - .dumb_create = drm_gem_cma_dumb_create_internal,
> >
> > This doesn't seem right. The _internal documentation explicitly says
> > that this should _not_ be used as .dumb_create. Instead drivers should
> > use it to implement their callback.
> >
> > Since it yields the same result as drm_gem_cma_dumb_create we can use
> > the default macro below.
>
> I noticed this and thought that the driver authors probably had their
> reasons. Changing the driver to the default macro is probably still a
> good idea.
>
To be on the _extra_ safe side might want to keep that separate patch
explicitly CC-ing the author/reviewers of the offending commit.
Although as said before - it's your call, I'm fine either way.
HTH
Emil
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