* [GIT PULL 3/3] arm64: dts: samsung: dts for v5.19
From: Krzysztof Kozlowski @ 2022-04-20 7:21 UTC (permalink / raw)
To: Olof Johansson, Arnd Bergmann, arm, soc
Cc: Krzysztof Kozlowski, linux-arm-kernel, linux-samsung-soc,
linux-kernel, Alim Akhtar, Krzysztof Kozlowski
In-Reply-To: <20220420072152.11696-1-krzysztof.kozlowski@linaro.org>
The following changes since commit 3123109284176b1532874591f7c81f3837bbdc17:
Linux 5.18-rc1 (2022-04-03 14:08:21 -0700)
are available in the Git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git tags/samsung-dt64-5.19
for you to fetch changes up to 22cbcb8f4a17c194d208f686fc3ea37fc860bd71:
arm64: dts: tesla: add a specific compatible to MCT on FSD (2022-04-04 18:53:08 +0200)
----------------------------------------------------------------
Samsung DTS ARM64 changes for v5.19
1. Cleanup: move aliases of board-related features to board in
Exynos850.
2. Add specific compatibles to Multi Core Timer to allow stricter DT
schema matching.
----------------------------------------------------------------
Krzysztof Kozlowski (3):
arm64: dts: exynos: move aliases to board in Exynos850
arm64: dts: exynos: add a specific compatible to MCT
arm64: dts: tesla: add a specific compatible to MCT on FSD
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 3 ++-
arch/arm64/boot/dts/exynos/exynos850-e850-96.dts | 5 +++++
arch/arm64/boot/dts/exynos/exynos850.dtsi | 19 ++-----------------
arch/arm64/boot/dts/tesla/fsd.dtsi | 2 +-
4 files changed, 10 insertions(+), 19 deletions(-)
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [GIT PULL 2/3] ARM: dts: samsung: dts for v5.19
From: Krzysztof Kozlowski @ 2022-04-20 7:21 UTC (permalink / raw)
To: Olof Johansson, Arnd Bergmann, arm, soc
Cc: Krzysztof Kozlowski, linux-arm-kernel, linux-samsung-soc,
linux-kernel, Alim Akhtar, Krzysztof Kozlowski
In-Reply-To: <20220420072152.11696-1-krzysztof.kozlowski@linaro.org>
The following changes since commit 3123109284176b1532874591f7c81f3837bbdc17:
Linux 5.18-rc1 (2022-04-03 14:08:21 -0700)
are available in the Git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git tags/samsung-dt-5.19
for you to fetch changes up to 9e916fb9bc3d16066286f19fc9c51d26a6aec6bd:
ARM: dts: s5pv210: align DMA channels with dtschema (2022-04-09 18:50:05 +0200)
----------------------------------------------------------------
Samsung DTS ARM changes for v5.19
1. Several DT schema related changes to make DTBs passing schema checks:
EHCI/OHCI/DMA/Ethernet node names, DMA channels order, USB-like
compatibles.
2. Add specific compatibles to Multi Core Timer to allow stricter DT
schema matching.
3. Cleanup from deprecated bindings:
- Remove deprecated unit-address workaround for Exynos5422 Odroid XU3
LPDDR3 memory timings.
- Do not use unit-address (and SFR region) in Exynos5250 MIPI phy in
favor of syscon node (unit-address deprecated in 2016).
- Use standard generic PHYs for EHCI/OHCI device in S5PV210.
4. Fix inverted SPI CS (thus blank panel) on S5PV210 Aries boards.
5. Correct Bluetooth interupt name on S5PV210 Aries boards.
----------------------------------------------------------------
Jonathan Bakker (4):
ARM: dts: s5pv210: Remove spi-cs-high on panel in Aries
ARM: dts: s5pv210: Correct interrupt name for bluetooth in Aries
ARM: dts: s5pv210: Adjust memory reg entries to match spec
ARM: dts: s5pv210: Adjust DMA node names to match spec
Krzysztof Kozlowski (7):
ARM: dts: exynos: remove deprecated unit address for LPDDR3 timings on Odroid
ARM: dts: exynos: add a specific compatible to MCT
ARM: dts: exynos: drop deprecated SFR region from MIPI phy
ARM: dts: exynos: align EHCI/OHCI nodes with dtschema on Exynos4
ARM: dts: s5pv210: align EHCI/OHCI nodes with dtschema
ARM: dts: s5pv210: Use standard arrays of generic PHYs for EHCI/OHCI device
ARM: dts: s5pv210: align DMA channels with dtschema
Oleksij Rempel (2):
ARM: dts: exynos: fix ethernet node name for different odroid boards
ARM: dts: exynos: fix compatible strings for Ethernet USB devices
arch/arm/boot/dts/exynos3250.dtsi | 3 +-
arch/arm/boot/dts/exynos4.dtsi | 4 +--
arch/arm/boot/dts/exynos4412-odroidu3.dts | 4 +--
arch/arm/boot/dts/exynos4412-odroidx.dts | 8 ++---
arch/arm/boot/dts/exynos5250.dtsi | 8 ++---
arch/arm/boot/dts/exynos5260.dtsi | 3 +-
arch/arm/boot/dts/exynos5410-odroidxu.dts | 4 +--
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 7 ++---
arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts | 6 ++--
arch/arm/boot/dts/exynos5422-odroidxu3.dts | 6 ++--
arch/arm/boot/dts/exynos54xx.dtsi | 3 +-
arch/arm/boot/dts/s5pv210-aquila.dts | 3 +-
arch/arm/boot/dts/s5pv210-aries.dtsi | 11 ++++---
arch/arm/boot/dts/s5pv210-goni.dts | 6 ++--
arch/arm/boot/dts/s5pv210.dtsi | 40 ++++++++++---------------
15 files changed, 52 insertions(+), 64 deletions(-)
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH] ARM: dts: aspeed: Adding Jabil Rubypass BMC
From: David Wang @ 2022-04-20 6:55 UTC (permalink / raw)
To: robh+dt, mark.rutland, joel, devicetree, linux-arm-kernel,
linux-aspeed, linux-kernel
Cc: David Wang
The initial introduction of the jabil server with AST2600 BMC SoC.
Signed-off-by: David Wang <David_Wang6097@jabil.com>
---
.../boot/dts/aspeed-bmc-jabil-rubypass.dts | 383 ++++++++++++++++++
1 file changed, 383 insertions(+)
create mode 100644 arch/arm/boot/dts/aspeed-bmc-jabil-rubypass.dts
diff --git a/arch/arm/boot/dts/aspeed-bmc-jabil-rubypass.dts b/arch/arm/boot/dts/aspeed-bmc-jabil-rubypass.dts
new file mode 100644
index 000000000000..80763ff48b2a
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-bmc-jabil-rubypass.dts
@@ -0,0 +1,383 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/dts-v1/;
+
+#include "aspeed-g6.dtsi"
+#include <dt-bindings/gpio/aspeed-gpio.h>
+
+/ {
+ model = "Jabil Boy";
+ compatible = "aspeed,ast2600";
+
+ aliases {
+ serial4 = &uart5;
+ };
+
+ chosen {
+ bootargs = "console=ttyS4,115200n8";
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x80000000>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ identify {
+ default-state = "off";
+ gpios = <&gpio0 ASPEED_GPIO(B, 7) GPIO_ACTIVE_LOW>;
+ };
+
+ status_amber {
+ default-state = "off";
+ gpios = <&gpio0 ASPEED_GPIO(G, 3) GPIO_ACTIVE_LOW>;
+ };
+
+ status_green {
+ default-state = "keep";
+ gpios = <&gpio0 ASPEED_GPIO(G, 2) GPIO_ACTIVE_LOW>;
+ };
+
+ status_susack {
+ default-state = "off";
+ gpios = <&gpio0 ASPEED_GPIO(V, 6) GPIO_ACTIVE_LOW>;
+ };
+
+ fan1_fault{
+ default-state = "off";
+ gpios = <&gpio3_71 0 GPIO_ACTIVE_HIGH>;
+ };
+ fan2_fault{
+ default-state = "off"
+ };
+ fan3_fault{
+ default-state = "off";
+ gpios = <&gpio3_71 2 GPIO_ACTIVE_HIGH>;
+ };
+ fan4_fault{
+ default-state = "off";
+ gpios = <&gpio3_71 3 GPIO_ACTIVE_HIGH>;
+ };
+ fan5_fault{
+ default-state = "off";
+ gpios = <&gpio3_71 4 GPIO_ACTIVE_HIGH>;
+ };
+ fan6_fault{
+ default-state = "off";
+ gpios = <&gpio3_71 5 GPIO_ACTIVE_HIGH>;
+ };
+
+ power_amber {
+ default-state = "off";
+ gpios = <&gpio0 ASPEED_GPIO(Y, 0) GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&mdio0 {
+ status = "okay";
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+};
+
+&mdio1 {
+ status = "okay";
+
+ ethphy1: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+};
+
+&mdio2 {
+ status = "okay";
+
+ ethphy2: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+};
+
+&mdio3 {
+ status = "okay";
+
+ ethphy3: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+};
+
+&mac0 {
+ status = "okay";
+
+ phy-mode = "rgmii-rxid";
+ phy-handle = <ðphy0>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgmii1_default>;
+};
+
+
+&mac1 {
+ status = "okay";
+
+ phy-mode = "rgmii-rxid";
+ phy-handle = <ðphy1>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgmii2_default>;
+};
+
+&mac2 {
+ status = "okay";
+
+ phy-mode = "rgmii";
+ phy-handle = <ðphy2>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgmii3_default>;
+};
+
+&mac3 {
+ status = "okay";
+
+ phy-mode = "rgmii";
+ phy-handle = <ðphy3>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_rgmii4_default>;
+};
+
+&emmc_controller {
+ status = "okay";
+};
+
+&emmc {
+ non-removable;
+ bus-width = <4>;
+ max-frequency = <100000000>;
+ clk-phase-mmc-hs200 = <9>, <225>;
+};
+
+&rtc {
+ status = "okay";
+};
+
+&fmc {
+ status = "okay";
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "bmc";
+ spi-max-frequency = <50000000>;
+#include "openbmc-flash-layout-128.dtsi"
+ };
+};
+
+&spi1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1_default>;
+
+ flash@0 {
+ status = "okay";
+ m25p,fast-read;
+ label = "pnor";
+ spi-max-frequency = <100000000>;
+ };
+};
+
+&uart1 {
+ status = "okay";
+ pinctrl-0 = <&pinctrl_txd1_default
+ &pinctrl_rxd1_default
+ &pinctrl_nrts1_default
+ &pinctrl_ndtr1_default
+ &pinctrl_ndsr1_default
+ &pinctrl_ncts1_default
+ &pinctrl_ndcd1_default
+ &pinctrl_nri1_default>;
+};
+
+&uart2 {
+ status = "okay";
+ pinctrl-0 = <&pinctrl_txd2_default
+ &pinctrl_rxd2_default
+ &pinctrl_nrts2_default
+ &pinctrl_ndtr2_default
+ &pinctrl_ndsr2_default
+ &pinctrl_ncts2_default
+ &pinctrl_ndcd2_default
+ &pinctrl_nri2_default>;
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&uart4 {
+ status = "okay";
+};
+
+
+&uart5 {
+ // Workaround for A0
+ compatible = "snps,dw-apb-uart";
+};
+
+&i2c0 {
+ status = "okay";
+
+ temp@2e {
+ compatible = "adi,adt7490";
+ reg = <0x2e>;
+ };
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c3 {
+ multi-master;
+ status = "okay";
+
+ gpio@70 {
+ compatible = "nxp,pca9538";
+ reg = <0x70>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <ASPEED_GPIO(O, 7) IRQ_TYPE_EDGE_FALLING>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names =
+ "FAN1_PRSNT_N", "FAN2_PRSNT_N", "FAN3_PRSNT_N", "FAN4_PRSNT_N",
+ "FAN5_PRSNT_N", "FAN6_PRSNT_N", "FANCTRL1_FANFAIL_N", "FANCTRL2_FANFAIL_N";
+ };
+
+ gpio3_71:gpio@71 {
+ compatible = "nxp,pca9538";
+ reg = <0x71>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names =
+ "LED_FAN1_FAULT", "LED_FAN2_FAULT", "LED_FAN3_FAULT", "LED_FAN4_FAULT",
+ "LED_FAN5_FAULT", "LED_FAN6_FAULT", "PU_U12_IO6", "PU_U12_IO7";
+ };
+};
+
+&i2c4 {
+ status = "okay";
+};
+
+&i2c5 {
+ status = "okay";
+};
+
+&i2c6 {
+ status = "okay";
+};
+
+&i2c7 {
+ status = "okay";
+};
+
+&i2c8 {
+ status = "okay";
+};
+
+&i2c9 {
+ status = "okay";
+};
+
+&i2c12 {
+ status = "okay";
+};
+
+&i2c13 {
+ status = "okay";
+};
+
+&i2c14 {
+ status = "okay";
+};
+
+&i2c15 {
+ status = "okay";
+};
+
+&fsim0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&uhci {
+ status = "okay";
+};
+
+&sdc {
+ status = "okay";
+};
+
+&gpio0 {
+ status = "okay";
+ /* Enable GPIOP0 and GPIOP2 pass-through by default */
+ /* pinctrl-names = "pass-through"; */
+ /* pinctrl-0 = <&pinctrl_thru0_default */
+ /* &pinctrl_thru1_default>; */
+
+ gpio-line-names =
+ /*A0-A7*/ "SMB_DCSCM_I2C2_R_SCL","SMB_DCSCM_I2C2_R_SDA","TP_GPIOA2","TP_GPIOA3","SMB_CPU_PIROM_R_SCL","SMB_CPU_PIROM_R_SDA","SMB_IPMB_STBY_LVC3_R_SCL","SMB_IPMB_STBY_LVC3_R_SDA",
+ /*B0-B7*/ "NCSI_BMC_I210_NCSI_PRSNT_N","NMI_OUT","IRQ_SMB3_M2_ALERT_N","FM_SPD_SWITCH_CTRL_N","RGMII_BMC_RMM4_LVC3_R_MDC","RGMII_BMC_RMM4_LVC3_R_MDIO","FM_BMC_BMCINIT_R","FP_ID_LED_N",
+ /*C0-C7*/ "","RMII_BMC_I210_TXEN_R","RMII_BMC_I210_TXD0_R","RMII_BMC_I210_TXD1_R","","","CLK_50M_BMC_MAC3_NCSI","",
+ /*D0-D7*/ "RMII_BMC_I210_RXD0","RMII_BMC_I210_RXD1","RMII_BMC_I210_CRSDV","RMII_BMC_I210_RXER","","RMII_BMC_OCP3_A_TXEN_R","RMII_BMC_OCP3_A_TXD0_R","RMII_BMC_OCP3_A_TXD1_R",
+ /*E0-E7*/ "","","CLK_50M_BMC_MAC4_NCSI","","RMII_BMC_OCP3_A_RXD0","RMII_BMC_OCP3_A_RXD1","RMII_BMC_OCP3_A_CRSDV","RMII_BMC_OCP3_A_RXER",
+ /*F0-F7*/ "","","","","","","ID_BUTTON","PS_PWROK",
+ /*G0-G7*/ "FM_SMB_BMC_NVME_LVC3_ALERT_N","RST_BMC_I2C_M2_R_N","FP_LED_STATUS_GREEN_N","FP_LED_STATUS_AMBER_N","FM_FORCE_BMC_UPDATE_N","FM_BMC_CRASHLOG_TRIG_N","FM_BMC_CPU_FBRK_OUT_R_N","DBP_PRESENT_IN_R2_N",
+ /*H0-H7*/ "SGPIO_BMC_FPGA_CLK_R","SGPIO_BMC_FPGA_LD_R_N","SGPIO_BMC_FPGA_DOUT_R","SGPIO_BMC_FPGA_DIN","PLTRST_N","CPU_CATERR","PCH_BMC_THERMTRIP","FM_CPU1_CATERR_N",
+ /*I0-I7*/ "JTAG_ASD_NTRST_R_N","JTAG_ASD_TDI_R","JTAG_ASD_TCK_R","JTAG_ASD_TMS_R","JTAG_ASD_TDO","FM_BMC_PWRBTN_OUT_R_N","FM_BMC_PWR_BTN_PTHRU_N","TP_FM_BMC_PCH_SCI_R_N",
+ /*J0-J7*/ "SMB_CHASSENSOR_STBY_LVC3_SCL","SMB_CHASSENSOR_STBY_LVC3_SDA","SMB_FPGA_REG_R_SCL","SMB_FPGA_REG_R_SDA","SMB_DCSCM_I2C12_R_SCL","SMB_DCSCM_I2C12_R_SDA","SMB_BMC_FAN_STBY_LVC3_R_SCL","SMB_BMC_FAN_STBY_LVC3_R_SDA",
+ /*K0-K7*/ "SMB_HSBP_STBY_LVC3_R_SCL","SMB_HSBP_STBY_LVC3_R_SDA","SMB_SMLINK0_STBY_LVC3_R2_SCL","SMB_SMLINK0_STBY_LVC3_R2_SDA","SMB_TEMPSENSOR_STBY_LVC3_R_SCL","SMB_TEMPSENSOR_STBY_LVC3_R_SDA","SMB_PMBUS_SML1_STBY_LVC3_R_SCL","SMB_PMBUS_SML1_STBY_LVC3_R_SDA",
+ /*L0-L7*/ "SMB_PCIE_STBY_LVC3_R_SCL","SMB_PCIE_STBY_LVC3_R_SDA","SMB_HOST_STBY_BMC_LVC3_R_SCL","SMB_HOST_STBY_BMC_LVC3_R_SDA","PREQ_N","TCK_MUX_SEL","","",
+ /*M0-M7*/ "TP_SPA_CTS_N","TP_SPA_DCD_N","TP_SPA_DSR_N","PU_SPA_RI_N","TP_SPA_DTR_N","TP_SPA_RTS_N","SPA_SOUT","SPA_SIN",
+ /*N0-N7*/ "TP_SPB_CTS_N","TP_SPB_DCD_N","TP_SPB_DSR_N","PU_SPB_RI_N","TP_SPB_DTR_N","TP_SPB_RTS_N","UART_BMC_TXD2","UART_BMC_RXD2",
+ /*O0-O7*/ "BMC_FPGA_GPIO_0","BMC_FPGA_GPIO_1","BMC_FPGA_GPIO_2","BMC_FPGA_GPIO_3","FM_BMC_PCH_SPARE_R","FM_CPU1_DISABLE_COD_N","NMI_BUTTON","PDB_PCA9538_INT_N",
+ /*P0-P7*/ "RESET_BUTTON","RESET_OUT","POWER_BUTTON","POWER_OUT","","","DISPLAYPORT_MUX_AUX_R_SEL","BMC_HBLED_N",
+ /*Q0-Q7*/ "TP_BMC_FAN1_A_TACH","TP_BMC_FAN1_B_TACH","TP_BMC_FAN2_A_TACH","TP_BMC_FAN2_B_TACH","TP_BMC_FAN3_A_TACH","TP_BMC_FAN3_B_TACH","TP_BMC_FAN4_A_TACH","TP_BMC_FAN4_B_TACH",
+ /*R0-R7*/ "","","","","","FPGA_JTAG_MUX_SEL","DISPLAYPORT_MUX_R_OE","DISPLAYPORT_MUX_DX_R_SEL",
+ /*S0-S7*/ "RST_BMC_PCIE_MUX_N","BMC_RST_RTCRST_R","PRDY_N","FM_FLASH_SECURITY_STRAP","RST_IPMB_SWITCH_R_N","A_P3V_BAT_SCALED_EN","REMOTE_DEBUG_ENABLE","FM_PCHHOT_N",
+ /*T0-T7*/ "GND","GND","GND","GND","GND","GND","GND","GND",
+ /*U0-U7*/ "GND","GND","GND","GND","GND","GND","GND","GND",
+ /*V0-V7*/ "SIO_S3","SIO_S5","TP_BMC_SIO_PWREQ_N","SIO_ONCONTROL","SIO_POWER_GOOD","LED_BMC_FW_CONFIG_DONE_N","FM_BMC_SUSACK_N","TP_IRQ_BMC_PCH_SMI_LPC_N_R",
+ /*W0-W7*/ "ESPI_IO0_LPC_LAD0_R","ESPI_IO1_LPC_LAD1_R","ESPI_IO2_LPC_LAD2_R","ESPI_IO3_LPC_LAD3_R","CLK_24M_66M_LPC0_ESPI_BMC","ESPI_CS0_N_LFRAME_N_BMC","IRQ_LPC_SERIRQ_ESPI_ALERT_N","RST_LPC_LRST_ESPI_RST_BMC_R_N",
+ /*X0-X7*/ "CPU_ERR2","SMI","POST_COMPLETE","TP_SPI_BMC_SAFS_R_CLK","TP_SPI_BMC_SAFS_R_MOSI","TP_SPI_BMC_SAFS_R_MISO","TP_SPI_BMC_SAFS_R_IO2","TP_SPI_BMC_SAFS_R_IO3",
+ /*Y0-Y7*/ "BMC_PWR_AMB_LED_R_N","IRQ_SML0_ALERT_BMC_R2_N","JTAG_CPLD_BMC_MUX_R_SEL","IRQ_SML1_PMBUS_BMC_ALERT_N","SPI_BMC_BOOT_R_IO2","SPI_BMC_BOOT_R_IO3","PU_SPI_BMC_BOOT_ABR","PU_SPI_BMC_BOOT_WP_N",
+ /*Z0-Z7*/ "CPU_ERR0","CPU_ERR1","PU_TP_PWRGD_P3V3_RISER2","PU_GPIOZ3","PU_GPIOZ4","PU_GPIOZ5","PU_GPIOZ6","PU_GPIOZ7";
+};
+
+&gpio1 {
+ status = "okay";
+ gpio-line-names = /* GPIO18 A-E */
+ /*A0-A7*/ "TP_GPIO18B5","TP_GPIO18B4","RST_EMMC_BMC_R_N","","","","","",
+ /*B0-B7*/ "","","PD_GPIOB2","","RGMII_BMC_RMM4_TX_R_CLK","RGMII_BMC_RMM4_TX_R_CTRL","RGMII_BMC_RMM4_R_TXD0","RGMII_BMC_RMM4_R_TXD1",
+ /*C0-C7*/ "RGMII_BMC_RMM4_R_TXD2","RGMII_BMC_RMM4_R_TXD3","RGMII_BMC_RMM4_RX_CLK","RGMII_BMC_RMM4_RX_CTRL","RGMII_BMC_RMM4_RXD0","RGMII_BMC_RMM4_RXD1","RGMII_BMC_RMM4_RXD2","RGMII_BMC_RMM4_RXD3",
+ /*D0-D7*/ "EMMC_BMC_R_CLK","EMMC_BMC_R_CMD","EMMC_BMC_R_DATA0","EMMC_BMC_R_DATA1","EMMC_BMC_R_DATA2","EMMC_BMC_R_DATA3","EMMC_BMC_CD_N","EMMC_BMC_WP_N",
+ /*E0-E3*/ "EMMC_BMC_R_DATA4","EMMC_BMC_R_DATA5","EMMC_BMC_R_DATA6","EMMC_BMC_R_DATA7";
+};
+
+&lpc_snoop {
+ snoop-ports = <0x80>;
+ status = "okay";
+};
+
--
2.30.2
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^ permalink raw reply related
* Re: [PATCH 1/2] dt-bindings: display: ti,am65x-dss: Add missing register & interrupt
From: Tomi Valkeinen @ 2022-04-20 7:05 UTC (permalink / raw)
To: Rob Herring
Cc: Jyri Sarha, Vignesh Raghavendra, Nishanth Menon, DRI Development,
Devicetree, Linux ARM Kernel, Linux Kernel, Nikhil Devshatwar,
Aradhya Bhatia
In-Reply-To: <Yl7FEuHEy66KUc5F@robh.at.kernel.org>
Hi,
On 19/04/2022 17:20, Rob Herring wrote:
> On Tue, Apr 19, 2022 at 12:33:01PM +0530, Aradhya Bhatia wrote:
>> The DSS IP on the ti-am65x soc supports an additional register space,
>> named "common1". Further. the IP services a maximum number of 2
>> interrupts.
>>
>> Add the missing register space "common1" and the additional interrupt.
>>
>> Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
>> ---
>> .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 10 +++++++---
>> 1 file changed, 7 insertions(+), 3 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
>> index 5c7d2cbc4aac..102059e9e0d5 100644
>> --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
>> +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
>> @@ -26,6 +26,7 @@ properties:
>> Addresses to each DSS memory region described in the SoC's TRM.
>> items:
>> - description: common DSS register area
>> + - description: common1 DSS register area
>
> You've just broken the ABI.
>
> New entries have to go on the end.
I'm curious, if the 'reg-names' is a required property, as it is here,
does this still break the ABI?
Tomi
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^ permalink raw reply
* [PATCH] arm64,trace: Add page fault traceponits
From: sunliming @ 2022-04-20 7:01 UTC (permalink / raw)
To: catalin.marinas, will; +Cc: linux-arm-kernel, linux-kernel, sunliming
The arm64 architecture lacks some tracepoints support, this patch
adds page fault tracepoints. The code and arch policy is mainly
inherited from x86.
Experimented on my centos8 virtual machine:
dracut:/# echo 1 > /sys/kernel/tracing/events/exceptions/enable
dracut:/# cat /sys/kernel/tracing/trace
The results:
sh-6098 [001] ..... 1186.024675: page_fault_user: addr=0xffffe153cc00 pc=0xffffa4117338 esr=0xffffe153cc00
cat-6126 [000] ..... 1186.024677: page_fault_kernel: addr=0xffffa4323740 pc=schedule_tail esr=0xffffa4323740
sh-6098 [001] ..... 1186.026085: page_fault_user: addr=0xaaaad23fae34 pc=0xaaaad231c0fc esr=0xaaaad23fae34
cat-6126 [000] ..... 1186.026106: page_fault_user: addr=0xffffa414565c pc=0xffffa414565c esr=0xffffa414565c
cat-6126 [000] ..... 1186.026222: page_fault_user: addr=0xffffa4214e10 pc=0xffffa4145670 esr=0xffffa4214e10
cat-6126 [000] ..... 1186.026243: page_fault_user: addr=0xffffa420fd88 pc=0xffffa41456ac esr=0xffffa420fd88
cat-6126 [000] ..... 1186.026282: page_fault_user: addr=0xffffa4117338 pc=0xffffa4117338 esr=0xffffa4117338
cat-6126 [000] ..... 1186.026308: page_fault_user: addr=0xffffe153cc00 pc=0xffffa4117338 esr=0xffffe153cc00
cat-6126 [000] ..... 1186.026365: page_fault_user: addr=0xaaaad231bd84 pc=0xaaaad231bd84 esr=0xaaaad231bd84
sh-6098 [001] ..... 1186.026372: page_fault_user: addr=0xaaab04330098 pc=0xffffa411be68 esr=0xaaab04330098
cat-6126 [000] ..... 1186.026394: page_fault_user: addr=0xaaaad22ef420 pc=0xaaaad22ef420 esr=0xaaaad22ef420
cat-6126 [000] ..... 1186.026414: page_fault_user: addr=0xaaaad23ee9b0 pc=0xaaaad22ef424 esr=0xaaaad23ee9b0
cat-6126 [000] ..... 1186.026426: page_fault_user: addr=0xffffa40c3110 pc=0xffffa40c3110 esr=0xffffa40c3110
cat-6126 [000] ..... 1186.026450: page_fault_user: addr=0xaaaad22f23f8 pc=0xaaaad22f23f8 esr=0xaaaad22f23f8
cat-6126 [000] ..... 1186.026467: page_fault_user: addr=0xaaaad23f0030 pc=0xaaaad22f240c esr=0xaaaad23f0030
cat-6126 [000] ..... 1186.026481: page_fault_user: addr=0xaaaad23fae3c pc=0xaaaad231be40 esr=0xaaaad23fae3c
cat-6126 [000] ..... 1186.026530: page_fault_user: addr=0xffffa40d63d8 pc=0xffffa40d63d8 esr=0xffffa40d63d8
cat-6126 [000] ..... 1186.026554: page_fault_user: addr=0xffffa431f650 pc=0xffffa40d63f8 esr=0xffffa431f650
sh-6098 [001] ..... 1186.026556: page_fault_user: addr=0xaaab04358d28 pc=0xffffa411be70 esr=0xaaab04358d28
cat-6126 [000] ..... 1186.026571: page_fault_user: addr=0xaaaad24015d0 pc=0xffffa40d640c esr=0xaaaad24015d0
cat-6126 [000] ..... 1186.026600: page_fault_user: addr=0xaaaad2332be8 pc=0xaaaad2332be8 esr=0xaaaad2332be8
cat-6126 [000] ..... 1186.026703: page_fault_user: addr=0xffffa416c438 pc=0xffffa416c438 esr=0xffffa416c438
sh-6098 [001] ..... 1186.026749: page_fault_user: addr=0xaaab04369d70 pc=0xffffa41193d8 esr=0xaaab04369d70
cat-6126 [000] ..... 1186.027610: page_fault_user: addr=0xaaaad2307754 pc=0xaaaad2307754 esr=0xaaaad2307754
cat-6126 [000] ..... 1186.027711: page_fault_user: addr=0xaaaad24014c4 pc=0xaaaad23310e4 esr=0xaaaad24014c4
cat-6126 [000] ..... 1186.027892: page_fault_user: addr=0xaaab04359a80 pc=0xaaaad23052f0 esr=0xaaab04359a80
cat-6126 [000] ..... 1186.027916: page_fault_user: addr=0xaaaad236cf80 pc=0xaaaad236cf80 esr=0xaaaad236cf80
Signed-off-by: sunliming <sunliming@kylinos.cn>
---
arch/arm64/include/asm/trace/common.h | 12 +++++
arch/arm64/include/asm/trace/exceptions.h | 54 +++++++++++++++++++++++
arch/arm64/kernel/Makefile | 1 +
arch/arm64/kernel/tracepoint.c | 24 ++++++++++
arch/arm64/mm/Makefile | 3 ++
arch/arm64/mm/fault.c | 19 ++++++++
6 files changed, 113 insertions(+)
create mode 100644 arch/arm64/include/asm/trace/common.h
create mode 100644 arch/arm64/include/asm/trace/exceptions.h
create mode 100644 arch/arm64/kernel/tracepoint.c
diff --git a/arch/arm64/include/asm/trace/common.h b/arch/arm64/include/asm/trace/common.h
new file mode 100644
index 000000000000..f0f9bcdb74d9
--- /dev/null
+++ b/arch/arm64/include/asm/trace/common.h
@@ -0,0 +1,12 @@
+#ifndef _ASM_TRACE_COMMON_H
+#define _ASM_TRACE_COMMON_H
+
+#ifdef CONFIG_TRACING
+DECLARE_STATIC_KEY_FALSE(trace_pagefault_key);
+#define trace_pagefault_enabled() \
+ static_branch_unlikely(&trace_pagefault_key)
+#else
+static inline bool trace_pagefault_enabled(void) { return false; }
+#endif
+
+#endif
diff --git a/arch/arm64/include/asm/trace/exceptions.h b/arch/arm64/include/asm/trace/exceptions.h
new file mode 100644
index 000000000000..b0309aeca50b
--- /dev/null
+++ b/arch/arm64/include/asm/trace/exceptions.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#undef TRACE_SYSTEM
+#define TRACE_SYSTEM exceptions
+
+#if !defined(_TRACE_PAGE_FAULT_H) || defined(TRACE_HEADER_MULTI_READ)
+#define _TRACE_PAGE_FAULT_H
+
+#include <linux/tracepoint.h>
+#include <asm/trace/common.h>
+
+extern int trace_pagefault_reg(void);
+extern void trace_pagefault_unreg(void);
+
+DECLARE_EVENT_CLASS(arm64_exceptions,
+
+ TP_PROTO(unsigned long addr, struct pt_regs *regs,
+ unsigned int esr),
+
+ TP_ARGS(addr, regs, esr),
+
+ TP_STRUCT__entry(
+ __field(unsigned long, addr)
+ __field(unsigned long, pc)
+ __field(unsigned int, esr)
+ ),
+
+ TP_fast_assign(
+ __entry->addr = addr;
+ __entry->pc = regs->pc;
+ __entry->esr = esr;
+ ),
+
+ TP_printk("addr=%ps pc=%ps esr=0x%lx",
+ (void *)__entry->addr, (void *)__entry->pc,
+ __entry->addr));
+
+#define DEFINE_PAGE_FAULT_EVENT(name) \
+DEFINE_EVENT_FN(arm64_exceptions, name, \
+ TP_PROTO(unsigned long addr, struct pt_regs *regs, \
+ unsigned int esr), \
+ TP_ARGS(addr, regs, esr), \
+ trace_pagefault_reg, trace_pagefault_unreg);
+
+DEFINE_PAGE_FAULT_EVENT(page_fault_user);
+DEFINE_PAGE_FAULT_EVENT(page_fault_kernel);
+
+#undef TRACE_INCLUDE_PATH
+#undef TRACE_INCLUDE_FILE
+#define TRACE_INCLUDE_PATH .
+#define TRACE_INCLUDE_FILE exceptions
+#endif /* _TRACE_PAGE_FAULT_H */
+
+/* This part must be outside protection */
+#include <trace/define_trace.h>
diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile
index 986837d7ec82..538476d91894 100644
--- a/arch/arm64/kernel/Makefile
+++ b/arch/arm64/kernel/Makefile
@@ -74,6 +74,7 @@ obj-$(CONFIG_ARM64_PTR_AUTH) += pointer_auth.o
obj-$(CONFIG_ARM64_MTE) += mte.o
obj-y += vdso-wrap.o
obj-$(CONFIG_COMPAT_VDSO) += vdso32-wrap.o
+obj-$(CONFIG_TRACING) += tracepoint.o
obj-y += probes/
head-y := head.o
diff --git a/arch/arm64/kernel/tracepoint.c b/arch/arm64/kernel/tracepoint.c
new file mode 100644
index 000000000000..ea36aa37a885
--- /dev/null
+++ b/arch/arm64/kernel/tracepoint.c
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Code for supporting page fault tracepoints.
+ *
+ *
+ */
+#include <linux/jump_label.h>
+#include <linux/atomic.h>
+
+#include <asm/trace/exceptions.h>
+
+DEFINE_STATIC_KEY_FALSE(trace_pagefault_key);
+
+int trace_pagefault_reg(void)
+{
+ static_branch_inc(&trace_pagefault_key);
+ return 0;
+}
+
+void trace_pagefault_unreg(void)
+{
+ static_branch_dec(&trace_pagefault_key);
+}
+
diff --git a/arch/arm64/mm/Makefile b/arch/arm64/mm/Makefile
index ff1e800ba7a1..62fef44062fa 100644
--- a/arch/arm64/mm/Makefile
+++ b/arch/arm64/mm/Makefile
@@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
+
obj-y := dma-mapping.o extable.o fault.o init.o \
cache.o copypage.o flush.o \
ioremap.o mmap.o pgd.o mmu.o \
@@ -12,5 +13,7 @@ obj-$(CONFIG_DEBUG_VIRTUAL) += physaddr.o
obj-$(CONFIG_ARM64_MTE) += mteswap.o
KASAN_SANITIZE_physaddr.o += n
+CFLAGS_fault.o := -I $(srctree)/$(src)/../include/asm/trace
+
obj-$(CONFIG_KASAN) += kasan_init.o
KASAN_SANITIZE_kasan_init.o := n
diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c
index 77341b160aca..5898d18ee20c 100644
--- a/arch/arm64/mm/fault.c
+++ b/arch/arm64/mm/fault.c
@@ -42,6 +42,9 @@
#include <asm/tlbflush.h>
#include <asm/traps.h>
+#define CREATE_TRACE_POINTS
+#include <asm/trace/exceptions.h>
+
struct fault_info {
int (*fn)(unsigned long far, unsigned int esr,
struct pt_regs *regs);
@@ -515,6 +518,20 @@ static bool is_write_abort(unsigned int esr)
return (esr & ESR_ELx_WNR) && !(esr & ESR_ELx_CM);
}
+static __always_inline void
+trace_page_fault_entries(struct pt_regs *regs, unsigned int esr,
+ unsigned long addr)
+{
+ if (!trace_pagefault_enabled())
+ return;
+
+ if (user_mode(regs))
+ trace_page_fault_user(addr, regs, esr);
+ else
+ trace_page_fault_kernel(addr, regs, esr);
+}
+
+
static int __kprobes do_page_fault(unsigned long far, unsigned int esr,
struct pt_regs *regs)
{
@@ -525,6 +542,8 @@ static int __kprobes do_page_fault(unsigned long far, unsigned int esr,
unsigned int mm_flags = FAULT_FLAG_DEFAULT;
unsigned long addr = untagged_addr(far);
+ trace_page_fault_entries(regs, esr, addr);
+
if (kprobe_page_fault(regs, esr))
return 0;
--
2.25.1
No virus found
Checked by Hillstone Network AntiVirus
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^ permalink raw reply related
* Re: [PATCH 1/2 v3] dt-bindings: dspi: added for semtech sx1301
From: Krzysztof Kozlowski @ 2022-04-20 6:58 UTC (permalink / raw)
To: Changming Huang, broonie, robh+dt, krzysztof.kozlowski+dt,
linux-spi, devicetree, linux-kernel, shawnguo, leoyang.li,
linux-arm-kernel
In-Reply-To: <20220420035045.33940-1-jerry.huang@nxp.com>
On 20/04/2022 05:50, Changming Huang wrote:
> Add DT Binding doc for semtech sx1301
>
> Signed-off-by: Changming Huang <jerry.huang@nxp.com>
> ---
> changes in v3:
> - add the dt-bindings
>
> .../bindings/spi/semtech,sx1301.yaml | 45 +++++++++++++++++++
> 1 file changed, 45 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/spi/semtech,sx1301.yaml
>
> diff --git a/Documentation/devicetree/bindings/spi/semtech,sx1301.yaml b/Documentation/devicetree/bindings/spi/semtech,sx1301.yaml
> new file mode 100644
> index 000000000000..f65fb5809218
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/semtech,sx1301.yaml
> @@ -0,0 +1,45 @@
> +# SPDX-License-Identifier: GPL-2.0
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/spi/semtech,sx1301.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Semtech sx1301 devicetree bindings
Remove "devicetree bindings" and add instead short description (type) of
the device (SPI controller?).
> +
> +allOf:
> + - $ref: "spi-controller.yaml"
allOf after maintainers.
> +
> +maintainers:
> + - Changming Huang <jerry.huang@nxp.com>
> +
> +properties:
> + compatible:
> + const: semtech,sx1301
> +
> + reg:
> + maxItems: 1
> +
> + spi-max-frequency: true
> +
> + fsl,spi-cs-sck-delay: true
> +
> + fsl,spi-sck-cs-delay: true
> +
> +required:
> + - compatible
> + - reg
> + - spi-max-frequency
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + mikrobus@0 {
Isn't MikroBUS more than SPI, but you implement here only it's part? If
so, name it just "spi".
Best regards,
Krzysztof
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* Re: [PATCH 3/3] dt-bindings: arm: mediatek: infracfg: Convert to DT schema
From: Krzysztof Kozlowski @ 2022-04-20 6:54 UTC (permalink / raw)
To: Yassine Oudjana, Rob Herring, Krzysztof Kozlowski,
Matthias Brugger
Cc: Sam Shih, Stephen Boyd, Ryder Lee, Yassine Oudjana, devicetree,
linux-mediatek, linux-arm-kernel, linux-kernel
In-Reply-To: <20220419180938.19397-4-y.oudjana@protonmail.com>
On 19/04/2022 20:09, Yassine Oudjana wrote:
> From: Yassine Oudjana <y.oudjana@protonmail.com>
>
> Convert infracfg bindings to DT schema format. Not all drivers
> currently implement resets, so #reset-cells is made a required
> property only for those that do. Using power-controller in the
> example node name makes #power-domain-cells required causing
> a dt_binding_check error. To solve this, the node is renamed to
> syscon@10001000.
>
> Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
> ---
> .../arm/mediatek/mediatek,infracfg.txt | 42 ----------
> .../arm/mediatek/mediatek,infracfg.yaml | 79 +++++++++++++++++++
> 2 files changed, 79 insertions(+), 42 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
> create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
> deleted file mode 100644
> index f66bd720571d..000000000000
> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt
> +++ /dev/null
> @@ -1,42 +0,0 @@
> -Mediatek infracfg controller
> -============================
> -
> -The Mediatek infracfg controller provides various clocks and reset
> -outputs to the system.
> -
> -Required Properties:
> -
> -- compatible: Should be one of:
> - - "mediatek,mt2701-infracfg", "syscon"
> - - "mediatek,mt2712-infracfg", "syscon"
> - - "mediatek,mt6765-infracfg", "syscon"
> - - "mediatek,mt6779-infracfg_ao", "syscon"
> - - "mediatek,mt6797-infracfg", "syscon"
> - - "mediatek,mt7622-infracfg", "syscon"
> - - "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon"
> - - "mediatek,mt7629-infracfg", "syscon"
> - - "mediatek,mt7986-infracfg", "syscon"
> - - "mediatek,mt8135-infracfg", "syscon"
> - - "mediatek,mt8167-infracfg", "syscon"
> - - "mediatek,mt8173-infracfg", "syscon"
> - - "mediatek,mt8183-infracfg", "syscon"
> - - "mediatek,mt8516-infracfg", "syscon"
> -- #clock-cells: Must be 1
> -- #reset-cells: Must be 1
> -
> -The infracfg controller uses the common clk binding from
> -Documentation/devicetree/bindings/clock/clock-bindings.txt
> -The available clocks are defined in dt-bindings/clock/mt*-clk.h.
> -Also it uses the common reset controller binding from
> -Documentation/devicetree/bindings/reset/reset.txt.
> -The available reset outputs are defined in
> -dt-bindings/reset/mt*-resets.h
> -
> -Example:
> -
> -infracfg: power-controller@10001000 {
> - compatible = "mediatek,mt8173-infracfg", "syscon";
> - reg = <0 0x10001000 0 0x1000>;
> - #clock-cells = <1>;
> - #reset-cells = <1>;
> -};
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
> new file mode 100644
> index 000000000000..4f43fe9f103e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml
> @@ -0,0 +1,79 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,infracfg.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: MediaTek Infrastructure System Configuration Controller
> +
> +maintainers:
> + - Matthias Brugger <matthias.bgg@gmail.com>
> +
> +description:
> + The Mediatek infracfg controller provides various clocks and reset outputs
> + to the system.
Mention here the headers with clock and reset constants. The same for
patches 1 and 2.
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:
> + - enum:
> + - mediatek,mt2701-infracfg
> + - mediatek,mt2712-infracfg
> + - mediatek,mt6765-infracfg
> + - mediatek,mt6779-infracfg_ao
> + - mediatek,mt6797-infracfg
> + - mediatek,mt7622-infracfg
> + - mediatek,mt7629-infracfg
> + - mediatek,mt7986-infracfg
> + - mediatek,mt8135-infracfg
> + - mediatek,mt8167-infracfg
> + - mediatek,mt8173-infracfg
> + - mediatek,mt8183-infracfg
> + - mediatek,mt8516-infracfg
> + - const: syscon
> + - items:
> + - const: mediatek,mt7623-infracfg
> + - const: mediatek,mt2701-infracfg
> + - const: syscon
> +
> + reg:
> + maxItems: 1
> +
> + '#clock-cells':
> + const: 1
> +
> + '#reset-cells':
> + const: 1
> +
> +required:
> + - compatible
> + - reg
> + - '#clock-cells'
> +
> +if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - mediatek,mt2701-infracfg
> + - mediatek,mt2712-infracfg
> + - mediatek,mt7622-infracfg
> + - mediatek,mt7986-infracfg
> + - mediatek,mt8135-infracfg
> + - mediatek,mt8173-infracfg
> + - mediatek,mt8183-infracfg
> +then:
> + required:
> + - '#reset-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + infracfg: syscon@10001000 {
reset-controller or clock-controller instead, because syscon is for
blocks having only the syscon function.
Best regards,
Krzysztof
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^ permalink raw reply
* Re: [PATCH 2/3] dt-bindings: arm: mediatek: apmixedsys: Convert to DT schema
From: Krzysztof Kozlowski @ 2022-04-20 6:50 UTC (permalink / raw)
To: Yassine Oudjana, Rob Herring, Krzysztof Kozlowski,
Matthias Brugger
Cc: Sam Shih, Stephen Boyd, Ryder Lee, Yassine Oudjana, devicetree,
linux-mediatek, linux-arm-kernel, linux-kernel
In-Reply-To: <20220419180938.19397-3-y.oudjana@protonmail.com>
On 19/04/2022 20:09, Yassine Oudjana wrote:
Thank you for your patch. There is something to discuss/improve.
> +
> +title: MediaTek AP Mixedsys Controller
> +
> +maintainers:
> + - Matthias Brugger <matthias.bgg@gmail.com>
> +
> +description:
> + The Mediatek apmixedsys controller provides PLLs to the system.
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:
> + - enum:
Same comments as patch 1 - no need for items here, just enum. Please
also put the new binding in clock subsystem.
Best regards,
Krzysztof
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^ permalink raw reply
* Re: [PATCH 1/3] dt-bindings: arm: mediatek: topckgen: Convert to DT schema
From: Krzysztof Kozlowski @ 2022-04-20 6:48 UTC (permalink / raw)
To: Yassine Oudjana, Rob Herring, Krzysztof Kozlowski,
Matthias Brugger
Cc: Sam Shih, Stephen Boyd, Ryder Lee, Yassine Oudjana, devicetree,
linux-mediatek, linux-arm-kernel, linux-kernel
In-Reply-To: <efc6d3ee-b060-b070-1471-af940428964a@linaro.org>
On 20/04/2022 08:47, Krzysztof Kozlowski wrote:
> On 19/04/2022 20:09, Yassine Oudjana wrote:
>> From: Yassine Oudjana <y.oudjana@protonmail.com>
>>
>> Convert topckgen bindings to DT schema format. MT2701, MT7623 and
>> MT7629 device trees currently have the syscon compatible without
>> it being mentioned in the old DT bindings file which introduces
>> dtbs_check errors when converting to DT schema as-is, so
>> mediatek,mt2701-topckgen and mediatek,mt7629-topckgen are placed
>> in the last items list with the syscon compatible, and syscon is
>> added to the mediatek,mt7623-topckgen list.
>>
>
> Thank you for your patch. There is something to discuss/improve.
>
>> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.yaml
>> new file mode 100644
>> index 000000000000..9ce9cf673cbc
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.yaml
>> @@ -0,0 +1,60 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,topckgen.yaml#"
>> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
>> +
>> +title: MediaTek Top Clock Generator Controller
>> +
>> +maintainers:
>> + - Matthias Brugger <matthias.bgg@gmail.com>
>> +
>> +description:
>> + The Mediatek topckgen controller provides various clocks to the system.
>> +
>> +properties:
>> + compatible:
>> + oneOf:
>> + - items:
>
> These are not a list, so skip items. Just enum. Rest looks good.
Actually one more through - this looks like clock-controller, so please
move the binding to ../bindings/clock/ directory.
Best regards,
Krzysztof
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^ permalink raw reply
* Re: [PATCH 1/3] dt-bindings: arm: mediatek: topckgen: Convert to DT schema
From: Krzysztof Kozlowski @ 2022-04-20 6:47 UTC (permalink / raw)
To: Yassine Oudjana, Rob Herring, Krzysztof Kozlowski,
Matthias Brugger
Cc: Sam Shih, Stephen Boyd, Ryder Lee, Yassine Oudjana, devicetree,
linux-mediatek, linux-arm-kernel, linux-kernel
In-Reply-To: <20220419180938.19397-2-y.oudjana@protonmail.com>
On 19/04/2022 20:09, Yassine Oudjana wrote:
> From: Yassine Oudjana <y.oudjana@protonmail.com>
>
> Convert topckgen bindings to DT schema format. MT2701, MT7623 and
> MT7629 device trees currently have the syscon compatible without
> it being mentioned in the old DT bindings file which introduces
> dtbs_check errors when converting to DT schema as-is, so
> mediatek,mt2701-topckgen and mediatek,mt7629-topckgen are placed
> in the last items list with the syscon compatible, and syscon is
> added to the mediatek,mt7623-topckgen list.
>
Thank you for your patch. There is something to discuss/improve.
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.yaml
> new file mode 100644
> index 000000000000..9ce9cf673cbc
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,topckgen.yaml
> @@ -0,0 +1,60 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,topckgen.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: MediaTek Top Clock Generator Controller
> +
> +maintainers:
> + - Matthias Brugger <matthias.bgg@gmail.com>
> +
> +description:
> + The Mediatek topckgen controller provides various clocks to the system.
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:
These are not a list, so skip items. Just enum. Rest looks good.
> + - enum:
> + - mediatek,mt6797-topckgen
> + - mediatek,mt7622-topckgen
> + - mediatek,mt8135-topckgen
> + - mediatek,mt8173-topckgen
> + - mediatek,mt8516-topckgen
Best regards,
Krzysztof
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^ permalink raw reply
* Re: [PATCH v9 4/6] dt-bindings: mfd: sensehat: Add Raspberry Pi Sense HAT schema
From: Krzysztof Kozlowski @ 2022-04-20 6:44 UTC (permalink / raw)
To: Charles Mirabile, linux-kernel
Cc: Serge Schneider, Stefan Wahren, Nicolas Saenz Julienne,
Mattias Brugger, linux-rpi-kernel, linux-arm-kernel, fedora-rpi,
Miguel Ojeda, Rob Herring, Krzysztof Kozlowski, Dmitry Torokhov,
Lee Jones, devicetree, linux-input, Mwesigwa Guma, Joel Savitz
In-Reply-To: <20220419205158.28088-5-cmirabil@redhat.com>
On 19/04/2022 22:51, Charles Mirabile wrote:
> This patch adds the device tree bindings for the Sense HAT
> and each of its children devices in yaml form.
>
> Co-developed-by: Mwesigwa Guma <mguma@redhat.com>
> Signed-off-by: Mwesigwa Guma <mguma@redhat.com>
> Co-developed-by: Joel Savitz <jsavitz@redhat.com>
> Signed-off-by: Joel Savitz <jsavitz@redhat.com>
> Signed-off-by: Charles Mirabile <cmirabil@redhat.com>
> ---
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
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^ permalink raw reply
* Re: [PATCH -next v4 1/4] mm: page_table_check: move pxx_user_accessible_page into x86
From: Tong Tiangen @ 2022-04-20 6:44 UTC (permalink / raw)
To: Anshuman Khandual, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
Dave Hansen, x86, H. Peter Anvin, Pasha Tatashin, Andrew Morton,
Catalin Marinas, Will Deacon, Paul Walmsley, Palmer Dabbelt,
Albert Ou
Cc: linux-kernel, linux-mm, linux-arm-kernel, linux-riscv,
Kefeng Wang, Guohanjun
In-Reply-To: <1671baf7-046e-7c52-183f-fd654125fd67@arm.com>
在 2022/4/19 17:29, Anshuman Khandual 写道:
>
>
> On 4/18/22 09:14, Tong Tiangen wrote:
>> --- a/mm/page_table_check.c
>> +++ b/mm/page_table_check.c
>> @@ -10,6 +10,14 @@
>> #undef pr_fmt
>> #define pr_fmt(fmt) "page_table_check: " fmt
>>
>> +#ifndef PMD_PAGE_SIZE
>> +#define PMD_PAGE_SIZE PMD_SIZE
>> +#endif
>> +
>> +#ifndef PUD_PAGE_SIZE
>> +#define PUD_PAGE_SIZE PUD_SIZE
>> +#endif
>
> Why cannot PMD_SIZE/PUD_SIZE be used on every platform instead ? What is the
> need for using PUD_PAGE_SIZE/PMD_PAGE_SIZE ? Are they different on x86 ?
> .
Hi, Pasha：
I checked the definitions of PMD_SIZE/PUD_SIZE and
PUD_PAGE_SIZE/PMD_PAGE_SIZE in x86 architecture and their use outside
the architecture(eg: in mm/, all used PMD_SIZE/PUD_SIZE), Would it be
better to use a unified PMD_SIZE/PUD_SIZE here?
Thanks,
Tong.
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^ permalink raw reply
* RE: [PATCH 2/2] EDAC: synopsys: re-enable the interrupts in intr_handler for V3.X Synopsys EDAC DDR
From: Sherry Sun @ 2022-04-20 6:23 UTC (permalink / raw)
To: Michal Simek, bp@alien8.de, mchehab@kernel.org,
tony.luck@intel.com, james.morse@arm.com, rric@kernel.org
Cc: linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, dl-linux-imx
In-Reply-To: <ab18f598-d4f5-049c-66f3-3ce2d5c01670@xilinx.com>
> > Since zynqmp_get_error_info() is called during CE/UE interrupt, at the
> > end of zynqmp_get_error_info(), it wirtes 0 to ECC_CLR_OFST, which cause
> > the CE/UE interrupts of V3.X Synopsys EDAC DDR been disabled, then the
> > interrupt handler will be called only once, so need to re-enable the
> > interrupts at the end of intr_handler for V3.X Synopsys EDAC DDR.
> >
> > Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> > ---
> > drivers/edac/synopsys_edac.c | 4 ++++
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c
> > index 1b630f0be119..3a1db34a8546 100644
> > --- a/drivers/edac/synopsys_edac.c
> > +++ b/drivers/edac/synopsys_edac.c
> > @@ -521,6 +521,8 @@ static void handle_error(struct mem_ctl_info *mci,
> struct synps_ecc_status *p)
> > memset(p, 0, sizeof(*p));
> > }
> >
> > +static void enable_intr(struct synps_edac_priv *priv);
> > +
> > /**
> > * intr_handler - Interrupt Handler for ECC interrupts.
> > * @irq: IRQ number.
> > @@ -562,6 +564,8 @@ static irqreturn_t intr_handler(int irq, void *dev_id)
> > /* v3.0 of the controller does not have this register */
> > if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR))
> > writel(regval, priv->baseaddr + DDR_QOS_IRQ_STAT_OFST);
> > + else
> > + enable_intr(priv);
>
> nit: newline here would be good.
Hi Michal, thanks for your comments, I will add the newline here in V2.
Best regards
Sherry
>
> > return IRQ_HANDLED;
> > }
> >
>
> Acked-by: Michal Simek <michal.simek@xilinx.com>
>
> Thanks,
> Michal
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^ permalink raw reply
* Re: [PATCH] mtd: spi-nor: Introduce templates for SPI NOR operations
From: Pratyush Yadav @ 2022-04-20 6:32 UTC (permalink / raw)
To: Tudor Ambarus
Cc: vigneshr, richard, michal.simek, linux-kernel, michael, linux-mtd,
miquel.raynal, linux-arm-kernel
In-Reply-To: <20220304093011.198173-1-tudor.ambarus@microchip.com>
On 04/03/22 11:30AM, Tudor Ambarus wrote:
> Clean the op declaration and hide the details of each op. With this it
> results a cleanner, easier to read code. No functional change expected.
>
> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
I have not looked at the changes very closely but the idea sounds fine
to me.
Acked-by: Pratyush Yadav <p.yadav@ti.com>
--
Regards,
Pratyush Yadav
Texas Instruments Inc.
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* [soc:pxa-multiplatform-5.18 37/48] arch/arm/mach-pxa/pxa2xx.c:58:5: warning: no previous prototype for 'pxa2xx_smemc_get_sdram_rows'
From: kernel test robot @ 2022-04-20 6:06 UTC (permalink / raw)
To: Arnd Bergmann; +Cc: kbuild-all, linux-arm-kernel, arm
tree: https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git pxa-multiplatform-5.18
head: faeb13a8cc88ff47971ffd2b2af3d14bc0b351be
commit: 71cd82cc6d1b6e92a352668bfe24d78d34e6dd03 [37/48] ARM: pxa: move smemc register access from clk to platform
config: arm-corgi_defconfig (https://download.01.org/0day-ci/archive/20220420/202204201338.poJP66ow-lkp@intel.com/config)
compiler: arm-linux-gnueabi-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git/commit/?id=71cd82cc6d1b6e92a352668bfe24d78d34e6dd03
git remote add soc https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git
git fetch --no-tags soc pxa-multiplatform-5.18
git checkout 71cd82cc6d1b6e92a352668bfe24d78d34e6dd03
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross W=1 O=build_dir ARCH=arm SHELL=/bin/bash
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
arch/arm/mach-pxa/pxa2xx.c:21:6: warning: no previous prototype for 'pxa2xx_clear_reset_status' [-Wmissing-prototypes]
21 | void pxa2xx_clear_reset_status(unsigned int mask)
| ^~~~~~~~~~~~~~~~~~~~~~~~~
>> arch/arm/mach-pxa/pxa2xx.c:58:5: warning: no previous prototype for 'pxa2xx_smemc_get_sdram_rows' [-Wmissing-prototypes]
58 | int pxa2xx_smemc_get_sdram_rows(void)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~
vim +/pxa2xx_smemc_get_sdram_rows +58 arch/arm/mach-pxa/pxa2xx.c
57
> 58 int pxa2xx_smemc_get_sdram_rows(void)
--
0-DAY CI Kernel Test Service
https://01.org/lkp
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* Re: [PATCH 2/2] EDAC: synopsys: re-enable the interrupts in intr_handler for V3.X Synopsys EDAC DDR
From: Michal Simek @ 2022-04-20 5:57 UTC (permalink / raw)
To: Sherry Sun, bp, mchehab, michal.simek, tony.luck, james.morse,
rric
Cc: linux-edac, linux-kernel, linux-arm-kernel, linux-imx
In-Reply-To: <20220318111742.15730-3-sherry.sun@nxp.com>
On 3/18/22 12:17, Sherry Sun wrote:
> Since zynqmp_get_error_info() is called during CE/UE interrupt, at the
> end of zynqmp_get_error_info(), it wirtes 0 to ECC_CLR_OFST, which cause
> the CE/UE interrupts of V3.X Synopsys EDAC DDR been disabled, then the
> interrupt handler will be called only once, so need to re-enable the
> interrupts at the end of intr_handler for V3.X Synopsys EDAC DDR.
>
> Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> ---
> drivers/edac/synopsys_edac.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c
> index 1b630f0be119..3a1db34a8546 100644
> --- a/drivers/edac/synopsys_edac.c
> +++ b/drivers/edac/synopsys_edac.c
> @@ -521,6 +521,8 @@ static void handle_error(struct mem_ctl_info *mci, struct synps_ecc_status *p)
> memset(p, 0, sizeof(*p));
> }
>
> +static void enable_intr(struct synps_edac_priv *priv);
> +
> /**
> * intr_handler - Interrupt Handler for ECC interrupts.
> * @irq: IRQ number.
> @@ -562,6 +564,8 @@ static irqreturn_t intr_handler(int irq, void *dev_id)
> /* v3.0 of the controller does not have this register */
> if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR))
> writel(regval, priv->baseaddr + DDR_QOS_IRQ_STAT_OFST);
> + else
> + enable_intr(priv);
nit: newline here would be good.
> return IRQ_HANDLED;
> }
>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Thanks,
Michal
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* Re: [PATCH 1/2] EDAC: synopsys: Add disable_intr support for V3.X Synopsys EDAC DDR
From: Michal Simek @ 2022-04-20 5:56 UTC (permalink / raw)
To: Sherry Sun, bp, mchehab, michal.simek, tony.luck, james.morse,
rric
Cc: linux-edac, linux-kernel, linux-arm-kernel, linux-imx
In-Reply-To: <20220318111742.15730-2-sherry.sun@nxp.com>
On 3/18/22 12:17, Sherry Sun wrote:
> V3.X Synopsys EDAC DDR doesn't have the QOS Interrupt register, need
> to change to use the ECC Clear Register to disable the interrupts.
>
> Signed-off-by: Sherry Sun <sherry.sun@nxp.com>
> ---
> drivers/edac/synopsys_edac.c | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c
> index f05ff02c0656..1b630f0be119 100644
> --- a/drivers/edac/synopsys_edac.c
> +++ b/drivers/edac/synopsys_edac.c
> @@ -859,8 +859,11 @@ static void enable_intr(struct synps_edac_priv *priv)
> static void disable_intr(struct synps_edac_priv *priv)
> {
> /* Disable UE/CE Interrupts */
> - writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
> - priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
> + if (priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)
> + writel(0x0, priv->baseaddr + ECC_CLR_OFST);
> + else
> + writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK,
> + priv->baseaddr + DDR_QOS_IRQ_DB_OFST);
> }
>
> static int setup_irq(struct mem_ctl_info *mci,
Acked-by: Michal Simek <michal.simek@xilinx.com>
Thanks,
Michal
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^ permalink raw reply
* Re: [PATCH v4 1/2] mtd: rawnand: meson: discard the common MMC sub clock framework
From: Liang Yang @ 2022-04-20 5:44 UTC (permalink / raw)
To: Miquel Raynal
Cc: linux-mtd, Rob Herring, Richard Weinberger, Vignesh Raghavendra,
Jerome Brunet, Neil Armstrong, Martin Blumenstingl, Kevin Hilman,
Jianxin Pan, Victor Wan, XianWei Zhao, Kelvin Zhang, BiChao Zheng,
YongHui Yu, linux-arm-kernel, linux-amlogic, linux-kernel,
devicetree
In-Reply-To: <20220419172528.2dd75e7b@xps13>
Hi Miquel,
On 2022/4/19 23:25, Miquel Raynal wrote:
> [ EXTERNAL EMAIL ]
>
> Hello,
>
> liang.yang@amlogic.com wrote on Tue, 19 Apr 2022 17:17:48 +0800:
>
>> Hello Miquel,
>>
>> On 2022/4/19 16:26, Miquel Raynal wrote:
>>> [ EXTERNAL EMAIL ]
>>>
>>> Hello,
>>>
>>> liang.yang@amlogic.com wrote on Mon, 18 Apr 2022 11:40:10 +0800:
>>>
>>>> Hi Miquel,
>>>>
>>>> i have some confusion when i prepare the patches. for DT compatibility, it falls back to the old DT when failed to get resource by the new DT, but there is some points:
>>>> a. old DT depends on MMC sub clock driver, but it never be merged, so it can't work.
>>>
>>> I don't get what you mean here, sorry. I believe there is a new way to
>>> describe this clock but grabbing the one from the MMC still works, does
>>> not it?
>>>
>>
>> No, it doesn't. after the NFC driver using the MMC sub clock framework was merged into the mainline of kernel, we didn't continue to submit the series of patches about MMC sub clock after v9. when i found that, we made a discussion to decide whether to recover the series of patches about MMC sub clock framework, finally, see the description from cover letter, we plan to abandon it and adopt the new clock scheme in this series of patches.
>
> I am not sure to follow. Is the current code completely broken? I
> believe it is not, so I don't understand your issue.
i think only the code about the clock is completely broken.
>
> Can you please summarize the situation?
Yes. the current NFC clock implementation depends on the following
series of patches
[https://lore.kernel.org/all/20220121074508.42168-5-liang.yang@amlogic.com],
which we call "Meson MMC Sub Clock Controller Driver".
when i was preparing the NFC patchset at that time, we discussed how the
clock should be implemented base on the special clock framework for NFC
and EMMC port. then we decided to implement a driver "Meson MMC Sub
Clock Controller Driver". so another people begin to prepare "Meson MMC
Sub Clock Controller Driver", but submitted it by different patchset.
finally, now the meson NFC patchset is accepted and merged, but "Meson
MMC Sub Clock Controller Driver" patchset is not. also we decide to
abandon the patset "Meson MMC Sub Clock Controller Driver" and implement
the new clock design in this series.
>
>>
>> Thanks.
>>
>>>> b. if it falls back to the old DT, beside the regmap lookup below, it seems that we have to preserve the code of the old clock setting in nfc_clk_init().
>>>
>>> Yes, probably.
>>>
>>>> do we still need to avoid break DT compatibility?
>>>
>>> We should try our best to avoid breaking the DT, yes.
>>>
>>>>
>>>> Thanks.
>>>>
>>>> On 2022/4/11 10:40, Liang Yang wrote:
>>>>>>> nfc->dev = dev;
>>>>>>> - res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>>>>>> - nfc->reg_base = devm_ioremap_resource(dev, res);
>>>>>>> + nfc->reg_base = devm_platform_ioremap_resource_byname(pdev, "nfc");
>>>>>>
>>>>>> This change seems unrelated.
>>>>>
>>>>> To be consistent with the following > devm_platform_ioremap_resource_byname(pdev, "emmc"). do you mean that we > don't need it?>
>>>>>>> if (IS_ERR(nfc->reg_base))
>>>>>>> return PTR_ERR(nfc->reg_base);
>>>>>>> - nfc->reg_clk =
>>>>>>> - syscon_regmap_lookup_by_phandle(dev->of_node,
>>>>>>> - "amlogic,mmc-syscon");
>>>>>>> - if (IS_ERR(nfc->reg_clk)) {
>>>>>>> - dev_err(dev, "Failed to lookup clock base\n");
>>>>>>> - return PTR_ERR(nfc->reg_clk);
>>>>>>> - }
>>>>>>> + nfc->sd_emmc_clock = devm_platform_ioremap_resource_byname(pdev, >>> "emmc");
>>>>>>> + if (IS_ERR(nfc->sd_emmc_clock))
>>>>>>> + return PTR_ERR(nfc->sd_emmc_clock);
>>>>>>
>>>>>> While I agree this is much better than the previous solution, we cannot
>>>>>> break DT compatibility, so you need to try getting the emmc clock, but
>>>>>> if it fails you should fallback to the regmap lookup.
>>>>>
>>>>> ok, i will fix it next version. thanks.
>>>>> >>>> >>>>> irq = platform_get_irq(pdev, 0);
>>>
>>>
>>> Thanks,
>>> Miquèl
>>>
>>> .
>
>
> Thanks,
> Miquèl
>
> .
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* Re: [PATCH v13 0/2] arm64: Enable BTI for the executable as well as the interpreter
From: Kees Cook @ 2022-04-20 5:33 UTC (permalink / raw)
To: will, broonie, catalin.marinas
Cc: Kees Cook, linux-arm-kernel, jeremy.linton, hjl.tools, libc-alpha,
szabolcs.nagy, yu-cheng.yu, ebiederm, linux-arch
In-Reply-To: <20220419105156.347168-1-broonie@kernel.org>
On Tue, 19 Apr 2022 11:51:54 +0100, Mark Brown wrote:
> Deployments of BTI on arm64 have run into issues interacting with
> systemd's MemoryDenyWriteExecute feature. Currently for dynamically
> linked executables the kernel will only handle architecture specific
> properties like BTI for the interpreter, the expectation is that the
> interpreter will then handle any properties on the main executable.
> For BTI this means remapping the executable segments PROT_EXEC |
> PROT_BTI.
>
> [...]
Applied to for-next/execve, thanks!
[1/2] elf: Allow architectures to parse properties on the main executable
https://git.kernel.org/kees/c/b2f2553c8e89
[2/2] arm64: Enable BTI for main executable as well as the interpreter
https://git.kernel.org/kees/c/b65c760600e2
--
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* Re: [Patch v1] iommu: arm-smmu: disable large page mappings for Nvidia arm-smmu
From: Ashish Mhetre @ 2022-04-20 5:32 UTC (permalink / raw)
To: Robin Murphy, thierry.reding, vdumpa, will, joro, jonathanh,
linux-tegra, linux-arm-kernel, iommu, linux-kernel
Cc: nicolinc, Snikam, Pritesh Raithatha
In-Reply-To: <52df6c79-3ee7-35e2-b72a-44ee9cb48c34@arm.com>
On 4/20/2022 1:57 AM, Robin Murphy wrote:
> External email: Use caution opening links or attachments
>
>
> On 2022-04-17 10:04, Ashish Mhetre wrote:
>> Tegra194 and Tegra234 SoCs have the erratum that causes walk cache
>> entries to not be invalidated correctly. The problem is that the walk
>> cache index generated for IOVA is not same across translation and
>> invalidation requests. This is leading to page faults when PMD entry is
>> released during unmap and populated with new PTE table during subsequent
>> map request. Disabling large page mappings avoids the release of PMD
>> entry and avoid translations seeing stale PMD entry in walk cache.
>> Fix this by limiting the page mappings to PAGE_SIZE for Tegra194 and
>> Tegra234 devices. This is recommended fix from Tegra hardware design
>> team.
>
> Is this related to any of the several known MMU-500 invalidation errata,
> or is it definitely specific to something NVIDIA have done with their
> integration?
>
It's not a known MMU-500 errata. It is specific to NVIDIA.
>> Co-developed-by: Pritesh Raithatha <praithatha@nvidia.com>
>> Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
>> Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>
>> ---
>> drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c | 23 ++++++++++++++++++++
>> drivers/iommu/arm/arm-smmu/arm-smmu.c | 3 +++
>> drivers/iommu/arm/arm-smmu/arm-smmu.h | 1 +
>> 3 files changed, 27 insertions(+)
>>
>> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
>> b/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
>> index 01e9b50b10a1..b7a3d06da2f4 100644
>> --- a/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
>> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-nvidia.c
>> @@ -258,6 +258,27 @@ static void nvidia_smmu_probe_finalize(struct
>> arm_smmu_device *smmu, struct devi
>> dev_name(dev), err);
>> }
>>
>> +static void nvidia_smmu_cfg_pgsize_bitmap(struct arm_smmu_device *smmu)
>> +{
>> + const struct device_node *np = smmu->dev->of_node;
>> +
>> + /*
>> + * Tegra194 and Tegra234 SoCs have the erratum that causes walk
>> cache
>> + * entries to not be invalidated correctly. The problem is that
>> the walk
>> + * cache index generated for IOVA is not same across translation
>> and
>> + * invalidation requests. This is leading to page faults when
>> PMD entry
>> + * is released during unmap and populated with new PTE table during
>> + * subsequent map request. Disabling large page mappings avoids the
>> + * release of PMD entry and avoid translations seeing stale PMD
>> entry in
>> + * walk cache.
>> + * Fix this by limiting the page mappings to PAGE_SIZE on
>> Tegra194 and
>> + * Tegra234.
>> + */
>> + if (of_device_is_compatible(np, "nvidia,tegra234-smmu") ||
>> + of_device_is_compatible(np, "nvidia,tegra194-smmu"))
>> + smmu->pgsize_bitmap = PAGE_SIZE;
>> +}
>> +
>> static const struct arm_smmu_impl nvidia_smmu_impl = {
>> .read_reg = nvidia_smmu_read_reg,
>> .write_reg = nvidia_smmu_write_reg,
>> @@ -268,10 +289,12 @@ static const struct arm_smmu_impl
>> nvidia_smmu_impl = {
>> .global_fault = nvidia_smmu_global_fault,
>> .context_fault = nvidia_smmu_context_fault,
>> .probe_finalize = nvidia_smmu_probe_finalize,
>> + .cfg_pgsize_bitmap = nvidia_smmu_cfg_pgsize_bitmap,
>> };
>>
>> static const struct arm_smmu_impl nvidia_smmu_single_impl = {
>> .probe_finalize = nvidia_smmu_probe_finalize,
>> + .cfg_pgsize_bitmap = nvidia_smmu_cfg_pgsize_bitmap,
>> };
>>
>> struct arm_smmu_device *nvidia_smmu_impl_init(struct arm_smmu_device
>> *smmu)
>> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c
>> b/drivers/iommu/arm/arm-smmu/arm-smmu.c
>> index 568cce590ccc..3692a19a588a 100644
>> --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c
>> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c
>> @@ -1872,6 +1872,9 @@ static int arm_smmu_device_cfg_probe(struct
>> arm_smmu_device *smmu)
>> if (smmu->features & ARM_SMMU_FEAT_FMT_AARCH64_64K)
>> smmu->pgsize_bitmap |= SZ_64K | SZ_512M;
>>
>> + if (smmu->impl && smmu->impl->cfg_pgsize_bitmap)
>> + smmu->impl->cfg_pgsize_bitmap(smmu);
>
> I'm not the biggest fan of adding a super-specific hook for this, when
> it seems like it could just as easily be handled in the init_context
> hook, which is where it is precisely for the purpose of mangling the
> pgtable_cfg to influence io-pgtable's behaviour.
>
Yes, we can use init_context() to override pgsize_bitmap. I'll update
that in next version.
> Thanks,
> Robin.
>
>> +
>> if (arm_smmu_ops.pgsize_bitmap == -1UL)
>> arm_smmu_ops.pgsize_bitmap = smmu->pgsize_bitmap;
>> else
>> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h
>> b/drivers/iommu/arm/arm-smmu/arm-smmu.h
>> index 2b9b42fb6f30..5d9b03024969 100644
>> --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h
>> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h
>> @@ -442,6 +442,7 @@ struct arm_smmu_impl {
>> void (*write_s2cr)(struct arm_smmu_device *smmu, int idx);
>> void (*write_sctlr)(struct arm_smmu_device *smmu, int idx, u32
>> reg);
>> void (*probe_finalize)(struct arm_smmu_device *smmu, struct
>> device *dev);
>> + void (*cfg_pgsize_bitmap)(struct arm_smmu_device *smmu);
>> };
>>
>> #define INVALID_SMENDX -1
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* [PATCH] coresight: etm4x: return 0 instead of using local ret variable
From: Shile Zhang @ 2022-04-20 5:28 UTC (permalink / raw)
To: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin
Cc: coresight, linux-arm-kernel, linux-kernel, Shile Zhang
The etm4_remove function (now it's rename to etm4_remove_dev) always
return 0, and it has been changed to void in commit 4fd269e74f2f
("amba: Make the remove callback return void"). But its weird that the
changes is gone in mainline. which is remained in 5.10.y branch.
Just backport the changes of etm4_remove_dev and return 0 directly in it's
caller function etm4_remove_platform_dev.
Signed-off-by: Shile Zhang <shile.zhang@linux.alibaba.com>
---
drivers/hwtracing/coresight/coresight-etm4x-core.c | 11 +++++------
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index 7f416a12000e..141f8209a152 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -2104,7 +2104,7 @@ static void clear_etmdrvdata(void *info)
etmdrvdata[cpu] = NULL;
}
-static int __exit etm4_remove_dev(struct etmv4_drvdata *drvdata)
+static void __exit etm4_remove_dev(struct etmv4_drvdata *drvdata)
{
etm_perf_symlink(drvdata->csdev, false);
/*
@@ -2125,8 +2125,6 @@ static int __exit etm4_remove_dev(struct etmv4_drvdata *drvdata)
cscfg_unregister_csdev(drvdata->csdev);
coresight_unregister(drvdata->csdev);
-
- return 0;
}
static void __exit etm4_remove_amba(struct amba_device *adev)
@@ -2139,13 +2137,14 @@ static void __exit etm4_remove_amba(struct amba_device *adev)
static int __exit etm4_remove_platform_dev(struct platform_device *pdev)
{
- int ret = 0;
struct etmv4_drvdata *drvdata = dev_get_drvdata(&pdev->dev);
if (drvdata)
- ret = etm4_remove_dev(drvdata);
+ etm4_remove_dev(drvdata);
+
pm_runtime_disable(&pdev->dev);
- return ret;
+
+ return 0;
}
static const struct amba_id etm4_ids[] = {
--
2.33.0.rc2
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* Re: [PATCH net 1/1] net: stmmac: add fsleep() in HW Rx timestamp checking loop
From: Tan Tee Min @ 2022-04-20 5:15 UTC (permalink / raw)
To: Richard Cochran
Cc: Jakub Kicinski, Tan Tee Min, Giuseppe Cavallaro, Alexandre Torgue,
Jose Abreu, David S . Miller, Paolo Abeni, Maxime Coquelin,
Rayagond Kokatanur, netdev, linux-stm32, linux-arm-kernel,
linux-kernel, stable, Voon Wei Feng, Wong Vee Khee,
Song Yoong Siang, Alexandre Torgue
In-Reply-To: <20220419132853.GA19386@hoboy.vegasvil.org>
On Tue, Apr 19, 2022 at 06:28:53AM -0700, Richard Cochran wrote:
> On Tue, Apr 19, 2022 at 08:52:20AM +0800, Tan Tee Min wrote:
>
> > I agree that the fsleep(1) (=1us) is a big hammer.
> > Thus in order to improve this, I’ve figured out a smaller delay
> > time that is enough for the context descriptor to be ready which
> > is ndelay(500) (=500ns).
>
> Why isn't the context descriptor ready?
>
> I mean, the frame already belongs to the CPU, right?
No. The context descriptor (frame) is possibly still owned by the
DMA controller in this situation.
This is why a looping in the original code to wait for the descriptor
to be owned by the application CPU. However, when NAPI is busy polling,
the context descriptor might be still owned by the DMA controller even
after the looping.
Thus, we are adding an additional nanosecond delay inside the loop,
so that the DMA controller can get a short moment to breathe and
complete the context descriptor.
Thanks,
Tee Min
>
> Thanks,
> Richard
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* Re: [PATCH -next v4 3/4] arm64: mm: add support for page table check
From: Anshuman Khandual @ 2022-04-20 5:05 UTC (permalink / raw)
To: Pasha Tatashin
Cc: Tong Tiangen, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
Dave Hansen, maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT),
H. Peter Anvin, Andrew Morton, Catalin Marinas, Will Deacon,
Paul Walmsley, Palmer Dabbelt, Albert Ou, LKML, linux-mm,
Linux ARM, linux-riscv, Kefeng Wang, Guohanjun
In-Reply-To: <CA+CK2bCPrQ=F0jNRxcVZ9f18Rm-kAATO3xFE79TZDoWQ99GC4Q@mail.gmail.com>
On 4/19/22 18:49, Pasha Tatashin wrote:
> On Tue, Apr 19, 2022 at 6:22 AM Anshuman Khandual
> <anshuman.khandual@arm.com> wrote:
>>
>>
>> On 4/18/22 09:14, Tong Tiangen wrote:
>>> +#ifdef CONFIG_PAGE_TABLE_CHECK
>>> +static inline bool pte_user_accessible_page(pte_t pte)
>>> +{
>>> + return pte_present(pte) && (pte_user(pte) || pte_user_exec(pte));
>>> +}
>>> +
>>> +static inline bool pmd_user_accessible_page(pmd_t pmd)
>>> +{
>>> + return pmd_present(pmd) && (pmd_user(pmd) || pmd_user_exec(pmd));
>>> +}
>>> +
>>> +static inline bool pud_user_accessible_page(pud_t pud)
>>> +{
>>> + return pud_present(pud) && pud_user(pud);
>>> +}
>>> +#endif
>> Wondering why check for these page table entry states when init_mm
>> has already being excluded ? Should not user page tables be checked
>> for in entirety for all updates ? what is the rationale for filtering
>> out only pxx_user_access_page entries ?
>
> The point is to prevent false sharing and memory corruption issues.
> The idea of PTC to be simple and relatively independent from the MM
> state machine that catches invalid page sharing. I.e. if an R/W anon
Right, this mechanism here is truly interdependent validation, which is
orthogonal to other MM states. Although I was curious, if mm_struct is
not 'init_mm', what percentage of its total page table mapped entries
will be user accessible ? These new helpers only filter out entries that
could potentially create false sharing leading upto memory corruption ?
I am wondering if there is any other way such filtering could have been
applied without adding all these new page table helpers just for page
table check purpose.
> page is accessible by user land, that page can never be mapped into
> another process (internally shared anons are treated as named
> mappings).
Right.
>
> Therefore, we try not to rely on MM states, and ensure that when a
> page-table entry is accessible by user it meets the required
> assumptions: no false sharing, etc.
Right, filtering reduces the page table entries that needs interception
during update (set/clear), but was just curious is there another way of
doing it, without adding page table check specific helpers on platforms
subscribing PAGE_TABLE_CHECK ?
>
> For example, one bug that was caught with PTC was where a driver on an
> unload would put memory on a freelist but memory is still mapped in
> user page table.
Should not page's refcount (that it is being used else where) prevented
releases into free list ? But page table check here might just detect
such scenarios even before page gets released.
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* [soc:pxa-multiplatform-5.18 37/48] arch/arm/mach-pxa/smemc.c:76:14: warning: no previous prototype for 'pxa3xx_smemc_get_memclkdiv'
From: kernel test robot @ 2022-04-20 4:35 UTC (permalink / raw)
To: Arnd Bergmann; +Cc: kbuild-all, linux-arm-kernel, arm
tree: https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git pxa-multiplatform-5.18
head: faeb13a8cc88ff47971ffd2b2af3d14bc0b351be
commit: 71cd82cc6d1b6e92a352668bfe24d78d34e6dd03 [37/48] ARM: pxa: move smemc register access from clk to platform
config: arm-pxa_defconfig (https://download.01.org/0day-ci/archive/20220420/202204201249.l1HnSEwz-lkp@intel.com/config)
compiler: arm-linux-gnueabi-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git/commit/?id=71cd82cc6d1b6e92a352668bfe24d78d34e6dd03
git remote add soc https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git
git fetch --no-tags soc pxa-multiplatform-5.18
git checkout 71cd82cc6d1b6e92a352668bfe24d78d34e6dd03
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross W=1 O=build_dir ARCH=arm SHELL=/bin/bash
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
>> arch/arm/mach-pxa/smemc.c:76:14: warning: no previous prototype for 'pxa3xx_smemc_get_memclkdiv' [-Wmissing-prototypes]
76 | unsigned int pxa3xx_smemc_get_memclkdiv(void)
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
vim +/pxa3xx_smemc_get_memclkdiv +76 arch/arm/mach-pxa/smemc.c
74
75 static const unsigned int df_clkdiv[4] = { 1, 2, 4, 1 };
> 76 unsigned int pxa3xx_smemc_get_memclkdiv(void)
--
0-DAY CI Kernel Test Service
https://01.org/lkp
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* Re: [PATCH v2 6/6] nvme-apple: Add initial Apple SoC NVMe driver
From: hch @ 2022-04-20 4:34 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Sven Peter, hch@lst.de, Keith Busch, axboe@fb.com,
sagi@grimberg.me, Hector Martin, Alyssa Rosenzweig, Rob Herring,
Krzysztof Kozlowski, Marc Zyngier, DTML, Linux ARM,
Linux Kernel Mailing List, linux-nvme, linux-spdx
In-Reply-To: <CAK8P3a2CWZb3vdHQvseJZQwPbUFDRo5Z9aGb7iVgodT1YeB5Yw@mail.gmail.com>
On Tue, Apr 19, 2022 at 11:52:15AM +0200, Arnd Bergmann wrote:
> > I just checked again and 64-bit accesses seem to work fine.
> > I'll remove the lo_hi_* calls and this include.
>
> If you remove the #include, it is no longer possible to compile-test
> this on all 32-bit architectures, though that is probably fine as long
> as the Kconfig file has the right dependencies, like
>
> depends on ARCH_APPLE || (COMPILE_TEST && 64BIT)
>
> I'd prefer to keep the #include here, but I don't mind the dependency
> if Christoph prefers it that way.
So thre's really two steps here:
1) stop uing lo_hi_readq diretly which forces 32-bit access even on
64-bit platforms
2) stop using the io-64-nonatomic headers entirely
I definitively want 1) done if the hardware does not require it. Trying
to cater to 32-bit build tests on hardware that has no chance of ever
being used there by including the header seems a bit silly, but if
it makes folks happy I can live with it.
>
> Arnd
---end quoted text---
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