* Re: [RFC v1 1/2] scmi: Introduce pinctrl SCMI protocol driver
From: Cristian Marussi @ 2023-04-20 17:05 UTC (permalink / raw)
To: Oleksii Moisieiev
Cc: sudeep.holla@arm.com, Linus Walleij, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org,
michal.simek, vincent.guittot, souvik.chakravarty
In-Reply-To: <ZDcqx9JVMvqr2WYu@e120937-lin>
On Wed, Apr 12, 2023 at 11:04:05PM +0100, Cristian Marussi wrote:
> On Fri, Apr 07, 2023 at 10:18:27AM +0000, Oleksii Moisieiev wrote:
> > Implementation of the SCMI client driver, which implements
> > PINCTRL_PROTOCOL. This protocol has ID 19 and is described
> > in the latest DEN0056 document.
>
> Hi,
>
Hi Oleksii,
one more thing that I missed in my previous review down below.
> > This protocol is part of the feature that was designed to
> > separate the pinctrl subsystem from the SCP firmware.
> > The idea is to separate communication of the pin control
> > subsystem with the hardware to SCP firmware
> > (or a similar system, such as ATF), which provides an interface
> > to give the OS ability to control the hardware through SCMI protocol.
> > This is a generic driver that implements SCMI protocol,
> > independent of the platform type.
> >
> > DEN0056 document:
> > https://developer.arm.com/documentation/den0056/latest
> >
>
[snip]
> > +static int scmi_pinctrl_request_config(const struct scmi_handle *handle,
> > + u32 selector,
> > + enum scmi_pinctrl_selector_type type,
> > + u32 *config)
> > +{
> > + struct scmi_xfer *t;
> > + struct scmi_conf_tx *tx;
> > + __le32 *packed_config;
> > + u32 attributes = 0;
> > + int ret;
> > +
> > + if (!handle || !config || type == FUNCTION_TYPE)
> > + return -EINVAL;
> > +
> > + ret = scmi_pinctrl_validate_id(handle, selector, type);
> > + if (ret)
> > + return ret;
> > +
> > + ret = scmi_xfer_get_init(handle, PINCTRL_CONFIG_GET,
> > + SCMI_PROTOCOL_PINCTRL,
> > + sizeof(*tx), sizeof(*packed_config), &t);
> > + if (ret)
> > + return ret;
> > +
> > + tx = t->tx.buf;
> > + packed_config = t->rx.buf;
> > + tx->identifier = cpu_to_le32(selector);
> > + attributes = SET_TYPE_BITS(attributes, type);
> > + attributes = SET_CONFIG(attributes, *config);
> > +
Looking at scmi_conf_tx and these pinctrl get/set functions, you do not
seem to consider the ConfigType field in the SCMI related messages, so
basically using always the Default 0 Type, and as a consequence you dont
either expose any way to choose a Different type in the related SCMI
protocol ops; I imagine this is because the pinctrl driver currently using
this protocol, at the end, does not need any of the other available types
(as in Table 23 of the spec).
This is fine for pinctrl driver as it is now, BUT the SCMI pinctrl
protocol implementation in the core SCMI stack and its related
protocol_operations as exposed in scmi_protocol.h should be generic
enough to serve any possible user of the SCMI pinctrl protocol (and there
is already a request to extend/amend the spec somehow to send multiple pin
setup of different types in one go as you may have seen), so I'd say it's
better if you add also a ConfigType param to the get/set_config scmi_pinctrl_ops
and expose the whole ConfigType enums (Table23) in scmi_protocol.h (like we do for
sensor classes on scmi_protocol.h) to address this; the pinctrl driver
can then anyway call such new protocol_ops with a Default type, but at
least the SCMI protocol_ops interface will remain generic and could be
reused iin other scenarios.
This is equally true for all the other protocol messages (should I have
miss something else for now...I'll review again you next V2 anyway).
Thanks,
Cristian
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^ permalink raw reply
* Re: [RFC v1 1/2] scmi: Introduce pinctrl SCMI protocol driver
From: Oleksii Moisieiev @ 2023-04-20 17:23 UTC (permalink / raw)
To: Cristian Marussi
Cc: sudeep.holla@arm.com, Linus Walleij, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org,
michal.simek@amd.com, vincent.guittot@linaro.org,
souvik.chakravarty@arm.com
In-Reply-To: <ZEFw0TYs3TEHuM1D@pluto>
Hi Cristian,
On 20.04.23 20:05, Cristian Marussi wrote:
> On Wed, Apr 12, 2023 at 11:04:05PM +0100, Cristian Marussi wrote:
>> On Fri, Apr 07, 2023 at 10:18:27AM +0000, Oleksii Moisieiev wrote:
>>> Implementation of the SCMI client driver, which implements
>>> PINCTRL_PROTOCOL. This protocol has ID 19 and is described
>>> in the latest DEN0056 document.
>> Hi,
>>
> Hi Oleksii,
>
> one more thing that I missed in my previous review down below.
>
>>> This protocol is part of the feature that was designed to
>>> separate the pinctrl subsystem from the SCP firmware.
>>> The idea is to separate communication of the pin control
>>> subsystem with the hardware to SCP firmware
>>> (or a similar system, such as ATF), which provides an interface
>>> to give the OS ability to control the hardware through SCMI protocol.
>>> This is a generic driver that implements SCMI protocol,
>>> independent of the platform type.
>>>
>>> DEN0056 document:
>>> https://urldefense.com/v3/__https://developer.arm.com/documentation/den0056/latest__;!!GF_29dbcQIUBPA!0kMLQ5c3tKsMfWCqTKHp6eolY3sTZlyKmAD7B7pbiSESABUUoBzmhgrYdDgWGC_g0vgLE4zwrS4ppeTOD8KizP9fIeJkpg$ [developer[.]arm[.]com]
>>>
> [snip]
>
>>> +static int scmi_pinctrl_request_config(const struct scmi_handle *handle,
>>> + u32 selector,
>>> + enum scmi_pinctrl_selector_type type,
>>> + u32 *config)
>>> +{
>>> + struct scmi_xfer *t;
>>> + struct scmi_conf_tx *tx;
>>> + __le32 *packed_config;
>>> + u32 attributes = 0;
>>> + int ret;
>>> +
>>> + if (!handle || !config || type == FUNCTION_TYPE)
>>> + return -EINVAL;
>>> +
>>> + ret = scmi_pinctrl_validate_id(handle, selector, type);
>>> + if (ret)
>>> + return ret;
>>> +
>>> + ret = scmi_xfer_get_init(handle, PINCTRL_CONFIG_GET,
>>> + SCMI_PROTOCOL_PINCTRL,
>>> + sizeof(*tx), sizeof(*packed_config), &t);
>>> + if (ret)
>>> + return ret;
>>> +
>>> + tx = t->tx.buf;
>>> + packed_config = t->rx.buf;
>>> + tx->identifier = cpu_to_le32(selector);
>>> + attributes = SET_TYPE_BITS(attributes, type);
>>> + attributes = SET_CONFIG(attributes, *config);
>>> +
> Looking at scmi_conf_tx and these pinctrl get/set functions, you do not
> seem to consider the ConfigType field in the SCMI related messages, so
> basically using always the Default 0 Type, and as a consequence you dont
> either expose any way to choose a Different type in the related SCMI
> protocol ops; I imagine this is because the pinctrl driver currently using
> this protocol, at the end, does not need any of the other available types
> (as in Table 23 of the spec).
>
I'm not sure I've understood your point. Pinctrl subsystem pass config
in so-called Packed format. So this means that config is both input and
output parameter. Packed format means that u32 config has both config id
and config value packed inside.
So I receive packed config with both id and value on config_set call and
then just send it over SCMI, expecting error from server if config is
invalid. On config_get call I receive config parameter with only id
packed inside, them pass it to the server and receive packed_config with
both id and value, which is ready to be returned to the subsystem.
> This is fine for pinctrl driver as it is now, BUT the SCMI pinctrl
> protocol implementation in the core SCMI stack and its related
> protocol_operations as exposed in scmi_protocol.h should be generic
> enough to serve any possible user of the SCMI pinctrl protocol (and there
> is already a request to extend/amend the spec somehow to send multiple pin
> setup of different types in one go as you may have seen), so I'd say it's
> better if you add also a ConfigType param to the get/set_config scmi_pinctrl_ops
> and expose the whole ConfigType enums (Table23) in scmi_protocol.h (like we do for
> sensor classes on scmi_protocol.h) to address this; the pinctrl driver
> can then anyway call such new protocol_ops with a Default type, but at
> least the SCMI protocol_ops interface will remain generic and could be
> reused iin other scenarios.
>
> This is equally true for all the other protocol messages (should I have
> miss something else for now...I'll review again you next V2 anyway).
>
> Thanks,
> Cristian
>
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^ permalink raw reply
* Re: [PATCH v3 00/13] mm, dma, arm64: Reduce ARCH_KMALLOC_MINALIGN to 8
From: Catalin Marinas @ 2023-04-20 17:43 UTC (permalink / raw)
To: Petr Tesarik
Cc: Isaac Manjarres, Linus Torvalds, Arnd Bergmann, Christoph Hellwig,
Greg Kroah-Hartman, Will Deacon, Marc Zyngier, Andrew Morton,
Herbert Xu, Ard Biesheuvel, Saravana Kannan, Alasdair Kergon,
Daniel Vetter, Joerg Roedel, Mark Brown, Mike Snitzer,
Rafael J. Wysocki, Robin Murphy, linux-mm, iommu,
linux-arm-kernel
In-Reply-To: <66a67d9e-70ce-9e2c-3b23-2d49447c4f24@huawei.com>
On Thu, Apr 20, 2023 at 11:52:00AM +0200, Petr Tesarik wrote:
> On 4/19/2023 6:06 PM, Catalin Marinas wrote:
> > On Thu, Mar 16, 2023 at 11:38:47AM -0700, Isaac Manjarres wrote:
> >[...]>> Given this, I don't think there's anything blocking this series from
> >> being merged. The requirement for SWIOTLB to get to the minimum
> >> kmalloc alignment down to 8 bytes shouldn't prevent this series from
> >> being merged, as the amount of memory that is allocated for SWIOTLB
> >> can be configured through the commandline to minimize the impact of
> >> having SWIOTLB memory. Additionally, even if no SWIOTLB is present,
> >> this series still offers memory savings on a lot of ARM64 platforms
> >> by using the cache line size as the minimum alignment for kmalloc.
> >
> > Actually, there's some progress on the swiotlb front to allow dynamic
> > allocation. I haven't reviewed the series yet (I wasn't aware of it
> > until v2) but at a quick look, it limits the dynamic allocation to
> > bouncing buffers of at least a page size. Maybe this can be later
> > improved for buffers below ARCH_DMA_MINALIGN.
>
> Indeed. My patch allocates dynamic bounce buffers with
> dma_direct_alloc_pages() to keep things simple for now, but there is no
> real reason against allocating less than a page with another suitable
> allocator.
I guess it could fall back to a suitably aligned kmalloc() for smaller
sizes.
> However, I'd be interested what the use case is, so I can assess the
> performance impact, which depends on workload, and FYI it may not even
> be negative. ;-)
On arm64 we have an ARCH_DMA_MINALIGN of 128 bytes as that's the largest
cache line size that you can find on a non-coherent platform. The
implication is that ARCH_KMALLOC_MINALIGN is also 128, so smaller
slab-{8,16,32,64,96,192} caches cannot be created, leading to some
memory wastage.
This series decouples the two static alignments so that we can have an
ARCH_KMALLOC_MINALIGN of 8 while keeping ARCH_DMA_MINALIGN as 128. The
problem is that there are some drivers that do a small kmalloc() (below
a cache line size; typically USB drivers) and expect DMA to such buffer
to work. If the cache line is shared with some unrelated data, either
the cache maintenance in the DMA API corrupts such data or the cache
dirtying overrides inbound DMA data.
So, the solution is to bounce such small buffers if they end up in
functions like dma_map_single(). All we need is for the bounce buffer to
be aligned to the cache line size and honour the coherent mask (normally
ok with one of the GFP_DMA/DMA32 flags if required).
The swiotlb buffer would solve this but there are some (mobile)
platforms where the vendor disables the bounce buffer to save memory.
Having a way to dynamically allocate it in those rare cases above would
be helpful.
--
Catalin
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^ permalink raw reply
* arm64/for-kernelci build: 2 builds: 0 failed, 2 passed (v6.3-rc7-84-g14f8db1c0f9a7)
From: kernelci.org bot @ 2023-04-20 18:19 UTC (permalink / raw)
To: will, catalin.marinas, linux-arm-kernel, kernel-build-reports,
kernelci-results
arm64/for-kernelci build: 2 builds: 0 failed, 2 passed (v6.3-rc7-84-g14f8db1c0f9a7)
Full Build Summary: https://kernelci.org/build/arm64/branch/for-kernelci/kernel/v6.3-rc7-84-g14f8db1c0f9a7/
Tree: arm64
Branch: for-kernelci
Git Describe: v6.3-rc7-84-g14f8db1c0f9a7
Git Commit: 14f8db1c0f9a79c4256c48e45f50e5db74d55109
Git URL: https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git
Built: 1 unique architecture
================================================================================
Detailed per-defconfig build reports:
--------------------------------------------------------------------------------
allmodconfig (arm64, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches
--------------------------------------------------------------------------------
defconfig (arm64, gcc-10) — PASS, 0 errors, 0 warnings, 0 section mismatches
---
For more info write to <info@kernelci.org>
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^ permalink raw reply
* Re: [RFC v1 1/2] scmi: Introduce pinctrl SCMI protocol driver
From: Cristian Marussi @ 2023-04-20 18:47 UTC (permalink / raw)
To: Oleksii Moisieiev
Cc: sudeep.holla@arm.com, Linus Walleij, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org,
michal.simek@amd.com, vincent.guittot@linaro.org,
souvik.chakravarty@arm.com
In-Reply-To: <e2c3eae9-4c99-43fe-abcf-4f1840c58c64@epam.com>
On Thu, Apr 20, 2023 at 05:23:05PM +0000, Oleksii Moisieiev wrote:
> Hi Cristian,
>
Hi,
> On 20.04.23 20:05, Cristian Marussi wrote:
> > On Wed, Apr 12, 2023 at 11:04:05PM +0100, Cristian Marussi wrote:
> >> On Fri, Apr 07, 2023 at 10:18:27AM +0000, Oleksii Moisieiev wrote:
> >>> Implementation of the SCMI client driver, which implements
> >>> PINCTRL_PROTOCOL. This protocol has ID 19 and is described
> >>> in the latest DEN0056 document.
> >> Hi,
> >>
> > Hi Oleksii,
> >
> > one more thing that I missed in my previous review down below.
> >
> >>> This protocol is part of the feature that was designed to
> >>> separate the pinctrl subsystem from the SCP firmware.
> >>> The idea is to separate communication of the pin control
> >>> subsystem with the hardware to SCP firmware
> >>> (or a similar system, such as ATF), which provides an interface
> >>> to give the OS ability to control the hardware through SCMI protocol.
> >>> This is a generic driver that implements SCMI protocol,
> >>> independent of the platform type.
> >>>
> >>> DEN0056 document:
> >>> https://urldefense.com/v3/__https://developer.arm.com/documentation/den0056/latest__;!!GF_29dbcQIUBPA!0kMLQ5c3tKsMfWCqTKHp6eolY3sTZlyKmAD7B7pbiSESABUUoBzmhgrYdDgWGC_g0vgLE4zwrS4ppeTOD8KizP9fIeJkpg$ [developer[.]arm[.]com]
> >>>
> > [snip]
> >
> >>> +static int scmi_pinctrl_request_config(const struct scmi_handle *handle,
> >>> + u32 selector,
> >>> + enum scmi_pinctrl_selector_type type,
> >>> + u32 *config)
> >>> +{
> >>> + struct scmi_xfer *t;
> >>> + struct scmi_conf_tx *tx;
> >>> + __le32 *packed_config;
> >>> + u32 attributes = 0;
> >>> + int ret;
> >>> +
> >>> + if (!handle || !config || type == FUNCTION_TYPE)
> >>> + return -EINVAL;
> >>> +
> >>> + ret = scmi_pinctrl_validate_id(handle, selector, type);
> >>> + if (ret)
> >>> + return ret;
> >>> +
> >>> + ret = scmi_xfer_get_init(handle, PINCTRL_CONFIG_GET,
> >>> + SCMI_PROTOCOL_PINCTRL,
> >>> + sizeof(*tx), sizeof(*packed_config), &t);
> >>> + if (ret)
> >>> + return ret;
> >>> +
> >>> + tx = t->tx.buf;
> >>> + packed_config = t->rx.buf;
> >>> + tx->identifier = cpu_to_le32(selector);
> >>> + attributes = SET_TYPE_BITS(attributes, type);
> >>> + attributes = SET_CONFIG(attributes, *config);
> >>> +
> > Looking at scmi_conf_tx and these pinctrl get/set functions, you do not
> > seem to consider the ConfigType field in the SCMI related messages, so
> > basically using always the Default 0 Type, and as a consequence you dont
> > either expose any way to choose a Different type in the related SCMI
> > protocol ops; I imagine this is because the pinctrl driver currently using
> > this protocol, at the end, does not need any of the other available types
> > (as in Table 23 of the spec).
> >
> I'm not sure I've understood your point. Pinctrl subsystem pass config
> in so-called Packed format. So this means that config is both input and
> output parameter. Packed format means that u32 config has both config id
> and config value packed inside.
>
Sorry I was meant to make the above comment on the PINCTRL_SET path but
I messed up and commented on the GET path....my bad.
Anyway even considering the packed format and looking at the PINCTRL_SET
function scmi_pinctrl_apply_config I dont understand how this works.
> So I receive packed config with both id and value on config_set call and
> then just send it over SCMI, expecting error from server if config is
This is where I dont understand: you receive a packed 32bit config from
pinctrl subsystem via ops->set_config together with the pin_id and in turn
this calls down into this apply_config where you build the packet:
> + ret = scmi_pinctrl_validate_id(handle, selector, type);
> + if (ret)
> + return ret;
> +
> + ret = scmi_xfer_get_init(handle, PINCTRL_CONFIG_SET,
> + SCMI_PROTOCOL_PINCTRL,
> + sizeof(*tx), 0, &t);
> + if (ret)
> + return ret;
> +
> + tx = t->tx.buf;
> + tx->identifier = cpu_to_le32(selector);
you set the pin number
> + attributes = SET_TYPE_BITS(attributes, type);
then set the Selector type as PIN_TYPE in the attributes bits 9:8
> + attributes = SET_CONFIG(attributes, config);
And here you set the PackedFormat received from pinctrl into the
bits 7:0 of attributes...(...BUT you then assign back to attributes
which is 32 bit so I think this is another bug because this way you
clear any bit just set above with SET_TYPE_BITS...but this is not the
point now...lets ignore this... ad you should anyway use bitfield.h in V2)
...so this attributes now, as you explained me, include both the selector
type (PIN vs GROUP) in bits 9:8 (bugs apart) and then, as a packed format
the ConfigType and the Value to set, both packed into the bits 7:0
> + tx->attributes = cpu_to_le32(attributes);
> +
You convert to proper endianity and
> + ret = scmi_do_xfer(handle, t);
> +
send straight to the SCMI server as a payload for PINCTRL_SET....so you
send basically the pin identifier in this case (u32) AND the u32 with
the attributes which includes the Selector PIN vs GROUP and the
ConfigType ..this last as a packed thing including also the value...
(so this could contain....looking at Table23 as an example:
Bias-pull-up (4) + a value in Ohms)
....BUT from the spec v3.2-BETA regarding PINCTRL_SET (4.11.2.7), you are
supposed to send one more u32 field "config_value" as the payload of
PINCTRL_SET (page 172) wth such field beaing the effectively carried
value to set....field which is instead now NOT considered at all and
so just sent as zero all of the time ... am I missing something ?
...so my understanding is that, being the expected format by the spec as
in 4.11.2.7, you should instead pick the PackedFormat your received as a 32bit
config, UNPACK it and split it into the attributes and config_value field....
from the v3.2 BETA spec I have I cannot see where the 32 bit attributes
payload is supposed to carry straight away the packedformat value...
...as it is implemented now, it is out of spec (at least the latest
v3.2-BETA public that I can see)... and if it works for you, it just means
your backend server is equally out-of-spec....which is probably a way of being
compliant BUT not the way we need to here :P
I cannot see any other way I can interpret this to make it
work...apologies if I am missing something, in such a case please explain...
Thanks,
Cristian
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* Re: [PATCH] perf cs-etm: Add support for coresight trace for any range of CPUs
From: Arnaldo Carvalho de Melo @ 2023-04-20 18:33 UTC (permalink / raw)
To: James Clark
Cc: Suzuki K Poulose, Ganapatrao Kulkarni, mathieu.poirier, darren,
scott, scclevenger, linux-kernel, coresight, linux-arm-kernel,
mike.leach
In-Reply-To: <53132776-c998-a24f-a811-d8fb2e5e6535@arm.com>
Em Thu, Apr 20, 2023 at 04:44:21PM +0100, James Clark escreveu:
> On 20/04/2023 14:03, Suzuki K Poulose wrote:
> > On 20/04/2023 13:37, Ganapatrao Kulkarni wrote:
> >> On 20-04-2023 06:00 pm, James Clark wrote:
> >>> On 20/04/2023 12:47, Ganapatrao Kulkarni wrote:
> >>>> My patch is rebased on 6.3-RC7 codebase with Mike's 3 perf patches
> >>>> related to dynamic id [1] support(queued for 6.4).
> >>>> "perf report -D" works for me.
> >>> I was referring to sparse CPU lists, which I think you mentioned above
> >>> doesn't work even with this patch.
> >>>> [1] https://www.spinics.net/lists/linux-perf-users/msg27452.html
> >>> It should be based on the next branch here:
> >>> git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git
> >> OK.
> > It need not be. Since this patch is purely perf tools patch and has
> > nothing to do with the kernel drivers, it should be beased on whatever
> > the tip of the perf tool tree is. Otherwise we risk rebasing to that
> > eventually.
> Good point, sorry for the confusion!
> I wonder if we could have some kind of new staging branch that has both
> up to date perf and coresight changes at the same time? Either that
> would make things like this easier, or more complicated. I'm not sure.
> I suppose I can DIY it quite easily but then everyone would have to as well.
My two cents: It this was available together with a CI that would run
'perf test' + 'make -C tools/perf build-test' and any other set of
tests, that would be great.
But not having it also has an advantage: no lockstep development,
tooling should gracefully work with whatever is available.
I say this because it is a really common theme, even Debian had a
packaging scheme that shoehorned (forcefully fused?) perf's and the
kernel's version :-\
- Arnaldo
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* arm64/for-kernelci baseline: 26 runs, 5 regressions (v6.3-rc7-84-g14f8db1c0f9a7)
From: kernelci.org bot @ 2023-04-20 19:02 UTC (permalink / raw)
To: will, catalin.marinas, linux-arm-kernel, kernel-build-reports,
kernelci-results
arm64/for-kernelci baseline: 26 runs, 5 regressions (v6.3-rc7-84-g14f8db1c0f9a7)
Regressions Summary
-------------------
platform | arch | lab | compiler | defconfig | regressions
-------------------+-------+---------------+----------+-----------+------------
fsl-ls1088a-rdb | arm64 | lab-nxp | gcc-10 | defconfig | 1
fsl-lx2160a-rdb | arm64 | lab-nxp | gcc-10 | defconfig | 1
juno-uboot | arm64 | lab-broonie | gcc-10 | defconfig | 1
kontron-pitx-imx8m | arm64 | lab-kontron | gcc-10 | defconfig | 1
rk3399-rock-pi-4b | arm64 | lab-collabora | gcc-10 | defconfig | 1
Details: https://kernelci.org/test/job/arm64/branch/for-kernelci/kernel/v6.3-rc7-84-g14f8db1c0f9a7/plan/baseline/
Test: baseline
Tree: arm64
Branch: for-kernelci
Describe: v6.3-rc7-84-g14f8db1c0f9a7
URL: https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git
SHA: 14f8db1c0f9a79c4256c48e45f50e5db74d55109
Test Regressions
----------------
platform | arch | lab | compiler | defconfig | regressions
-------------------+-------+---------------+----------+-----------+------------
fsl-ls1088a-rdb | arm64 | lab-nxp | gcc-10 | defconfig | 1
Details: https://kernelci.org/test/plan/id/64417cd3fdc08755e82e8672
Results: 5 PASS, 1 FAIL, 1 SKIP
Full config: defconfig
Compiler: gcc-10 (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110)
Plain log: https://storage.kernelci.org//arm64/for-kernelci/v6.3-rc7-84-g14f8db1c0f9a7/arm64/defconfig/gcc-10/lab-nxp/baseline-fsl-ls1088a-rdb.txt
HTML log: https://storage.kernelci.org//arm64/for-kernelci/v6.3-rc7-84-g14f8db1c0f9a7/arm64/defconfig/gcc-10/lab-nxp/baseline-fsl-ls1088a-rdb.html
Rootfs: http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230414.0/arm64/rootfs.cpio.gz
* baseline.bootrr.deferred-probe-empty: https://kernelci.org/test/case/id/64417cd3fdc08755e82e8677
failing since 105 days (last pass: v6.1-rc6-92-g6d464646530f, first fail: v6.1-rc2)
2023-04-20T17:56:09.736838 [ 17.558396] <LAVA_SIGNAL_ENDRUN 0_dmesg 1204902_1.5.2.4.1>
2023-04-20T17:56:09.844479 / # #
2023-04-20T17:56:09.946348 export SHELL=/bin/sh
2023-04-20T17:56:09.946963 #
2023-04-20T17:56:10.048420 / # export SHELL=/bin/sh. /lava-1204902/environment
2023-04-20T17:56:10.048978
2023-04-20T17:56:10.150526 / # . /lava-1204902/environment/lava-1204902/bin/lava-test-runner /lava-1204902/1
2023-04-20T17:56:10.151342
2023-04-20T17:56:10.153614 / # /lava-1204902/bin/lava-test-runner /lava-1204902/1
2023-04-20T17:56:10.173544 + export 'TESTRUN_ID=1_bootrr'
... (11 line(s) more)
platform | arch | lab | compiler | defconfig | regressions
-------------------+-------+---------------+----------+-----------+------------
fsl-lx2160a-rdb | arm64 | lab-nxp | gcc-10 | defconfig | 1
Details: https://kernelci.org/test/plan/id/64417ccffdc08755e82e8667
Results: 5 PASS, 1 FAIL, 1 SKIP
Full config: defconfig
Compiler: gcc-10 (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110)
Plain log: https://storage.kernelci.org//arm64/for-kernelci/v6.3-rc7-84-g14f8db1c0f9a7/arm64/defconfig/gcc-10/lab-nxp/baseline-fsl-lx2160a-rdb.txt
HTML log: https://storage.kernelci.org//arm64/for-kernelci/v6.3-rc7-84-g14f8db1c0f9a7/arm64/defconfig/gcc-10/lab-nxp/baseline-fsl-lx2160a-rdb.html
Rootfs: http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230414.0/arm64/rootfs.cpio.gz
* baseline.bootrr.deferred-probe-empty: https://kernelci.org/test/case/id/64417ccffdc08755e82e866c
failing since 48 days (last pass: v6.1-rc5-63-g9500fc6e9e60, first fail: v6.2-143-g596b6b709632)
2023-04-20T17:55:42.707207 [ 13.226108] <LAVA_SIGNAL_ENDRUN 0_dmesg 1204900_1.5.2.4.1>
2023-04-20T17:55:42.813584 / # #
2023-04-20T17:55:42.915791 export SHELL=/bin/sh
2023-04-20T17:55:42.916307 #
2023-04-20T17:55:43.017700 / # export SHELL=/bin/sh. /lava-1204900/environment
2023-04-20T17:55:43.018225
2023-04-20T17:55:43.119974 / # . /lava-1204900/environment/lava-1204900/bin/lava-test-runner /lava-1204900/1
2023-04-20T17:55:43.120949
2023-04-20T17:55:43.122680 / # /lava-1204900/bin/lava-test-runner /lava-1204900/1
2023-04-20T17:55:43.146736 + export 'TESTRUN_ID=1_bootrr'
... (11 line(s) more)
platform | arch | lab | compiler | defconfig | regressions
-------------------+-------+---------------+----------+-----------+------------
juno-uboot | arm64 | lab-broonie | gcc-10 | defconfig | 1
Details: https://kernelci.org/test/plan/id/64417e479afdd8a3962e85f8
Results: 60 PASS, 1 FAIL, 1 SKIP
Full config: defconfig
Compiler: gcc-10 (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110)
Plain log: https://storage.kernelci.org//arm64/for-kernelci/v6.3-rc7-84-g14f8db1c0f9a7/arm64/defconfig/gcc-10/lab-broonie/baseline-juno-uboot.txt
HTML log: https://storage.kernelci.org//arm64/for-kernelci/v6.3-rc7-84-g14f8db1c0f9a7/arm64/defconfig/gcc-10/lab-broonie/baseline-juno-uboot.html
Rootfs: http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230414.0/arm64/rootfs.cpio.gz
* baseline.bootrr.deferred-probe-empty: https://kernelci.org/test/case/id/64417e479afdd8a3962e8633
failing since 105 days (last pass: v6.1-rc7-151-ge3cb714fb489, first fail: v6.1-rc2)
2023-04-20T18:02:36.519270 <8>[ 25.968349] <LAVA_SIGNAL_ENDRUN 0_dmesg 363051_1.5.2.4.1>
2023-04-20T18:02:36.628360 / # #
2023-04-20T18:02:36.731320 export SHELL=/bin/sh
2023-04-20T18:02:36.732085 #
2023-04-20T18:02:36.834037 / # export SHELL=/bin/sh. /lava-363051/environment
2023-04-20T18:02:36.834825
2023-04-20T18:02:36.936793 / # . /lava-363051/environment/lava-363051/bin/lava-test-runner /lava-363051/1
2023-04-20T18:02:36.938169
2023-04-20T18:02:36.950670 / # /lava-363051/bin/lava-test-runner /lava-363051/1
2023-04-20T18:02:36.982635 + export 'TESTRUN_ID=1_bootrr'
... (41 line(s) more)
platform | arch | lab | compiler | defconfig | regressions
-------------------+-------+---------------+----------+-----------+------------
kontron-pitx-imx8m | arm64 | lab-kontron | gcc-10 | defconfig | 1
Details: https://kernelci.org/test/plan/id/64417d6d36444b0a182e8618
Results: 0 PASS, 1 FAIL, 0 SKIP
Full config: defconfig
Compiler: gcc-10 (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110)
Plain log: https://storage.kernelci.org//arm64/for-kernelci/v6.3-rc7-84-g14f8db1c0f9a7/arm64/defconfig/gcc-10/lab-kontron/baseline-kontron-pitx-imx8m.txt
HTML log: https://storage.kernelci.org//arm64/for-kernelci/v6.3-rc7-84-g14f8db1c0f9a7/arm64/defconfig/gcc-10/lab-kontron/baseline-kontron-pitx-imx8m.html
Rootfs: http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230414.0/arm64/rootfs.cpio.gz
* baseline.login: https://kernelci.org/test/case/id/64417d6d36444b0a182e8619
new failure (last pass: v6.3-rc7-73-g327bf9bb94cf)
platform | arch | lab | compiler | defconfig | regressions
-------------------+-------+---------------+----------+-----------+------------
rk3399-rock-pi-4b | arm64 | lab-collabora | gcc-10 | defconfig | 1
Details: https://kernelci.org/test/plan/id/64417c8932e7759bf62e8620
Results: 5 PASS, 1 FAIL, 1 SKIP
Full config: defconfig
Compiler: gcc-10 (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110)
Plain log: https://storage.kernelci.org//arm64/for-kernelci/v6.3-rc7-84-g14f8db1c0f9a7/arm64/defconfig/gcc-10/lab-collabora/baseline-rk3399-rock-pi-4b.txt
HTML log: https://storage.kernelci.org//arm64/for-kernelci/v6.3-rc7-84-g14f8db1c0f9a7/arm64/defconfig/gcc-10/lab-collabora/baseline-rk3399-rock-pi-4b.html
Rootfs: http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230414.0/arm64/rootfs.cpio.gz
* baseline.bootrr.deferred-probe-empty: https://kernelci.org/test/case/id/64417c8932e7759bf62e8625
failing since 105 days (last pass: v6.1-rc7-151-ge3cb714fb489, first fail: v6.1-rc2)
2023-04-20T17:55:05.318475 / # #
2023-04-20T17:55:05.419464 export SHELL=/bin/sh
2023-04-20T17:55:05.419578 #
2023-04-20T17:55:05.520527 / # export SHELL=/bin/sh. /lava-10066493/environment
2023-04-20T17:55:05.520641
2023-04-20T17:55:05.621588 / # . /lava-10066493/environment/lava-10066493/bin/lava-test-runner /lava-10066493/1
2023-04-20T17:55:05.621846
2023-04-20T17:55:05.631644 / # /lava-10066493/bin/lava-test-runner /lava-10066493/1
2023-04-20T17:55:05.692621 + export 'TESTRUN_ID=1_bootrr'
2023-04-20T17:55:05.692701 + cd /lava-10066493/1/tests/1_bootrr
... (12 line(s) more)
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH 3/3] ARM: dts: axp209: Add iio-hwmon node for internal temperature
From: Jonathan McDowell @ 2023-04-20 19:06 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Rob Herring, Krzysztof Kozlowski, Chen-Yu Tsai, Jernej Skrabec,
Samuel Holland, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel
In-Reply-To: <25a8dcf9-fd1b-0eb3-eced-7a1e158ca7fc@linaro.org>
On Sun, Apr 16, 2023 at 09:27:46AM +0200, Krzysztof Kozlowski wrote:
> On 15/04/2023 19:47, Jonathan McDowell wrote:
> > This adds a DT node to hook up the internal temperature ADC to the
>
> Do not use "This commit/patch", but imperative mood. See:
> https://elixir.bootlin.com/linux/v5.17.1/source/Documentation/process/submitting-patches.rst#L95
>
> > iio-hwmon driver. The various voltage + current ADCs are consumed and
> > exposed by their respective drivers, but this is not and is always
> > available. Naming chosen to match the axp20x_ prefix the power sensors
> > use.
>
> Weird choice.
You think? I didn't choose the axp20x_ prefix for the others, but it
made sense to me that all the sensors from the same device would be
identifiable as such. From your comment below it sounds like you'd
prefer I use the more generic pmic-temp as the node name? Will do for
v2.
> > Signed-off-by: Jonathan McDowell <noodles@earth.li>
> > ---
> > arch/arm/boot/dts/axp209.dtsi | 7 +++++++
> > 1 file changed, 7 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/axp209.dtsi b/arch/arm/boot/dts/axp209.dtsi
> > index ca240cd6f6c3..f00b5a7ec106 100644
> > --- a/arch/arm/boot/dts/axp209.dtsi
> > +++ b/arch/arm/boot/dts/axp209.dtsi
> > @@ -48,6 +48,13 @@
> > * http://dl.linux-sunxi.org/AXP/AXP209%20Datasheet%20v1.0_cn.pdf
> > */
> >
> > +/ {
> > + axp20x_temp {
>
> No underscores in node names.
>
> Node names should be generic.
> https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
>
> > + compatible = "iio-hwmon";
> > + io-channels = <&axp_adc 4>; /* Internal temperature */
> > + };
> > +};
> > +
> > &axp209 {
> > compatible = "x-powers,axp209";
> > interrupt-controller;
J.
--
"My house has this new innovation called "windows". Even my bedroom
has them. " -- Paul Tomblin
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [patch 00/37] cpu/hotplug, x86: Reworked parallel CPU bringup
From: Thomas Gleixner @ 2023-04-20 19:10 UTC (permalink / raw)
To: Paul Menzel
Cc: Sean Christopherson, Andrew Cooper, linux-kernel, x86,
David Woodhouse, Brian Gerst, Arjan van de Veen, Paolo Bonzini,
Paul McKenney, Tom Lendacky, Oleksandr Natalenko,
Guilherme G. Piccoli, Piotr Gorski, David Woodhouse, Usama Arif,
Jürgen Groß, Boris Ostrovsky, xen-devel, Russell King,
Arnd Bergmann, linux-arm-kernel, Catalin Marinas, Will Deacon,
Guo Ren, linux-csky, Thomas Bogendoerfer, linux-mips,
James E. J. Bottomley, Helge Deller, linux-parisc, Paul Walmsley,
Palmer Dabbelt, linux-riscv, Mark Rutland, Sabin Rapan
In-Reply-To: <56e59a4d-a47f-4bfe-7db5-5f921062ad69@molgen.mpg.de>
On Thu, Apr 20 2023 at 18:47, Paul Menzel wrote:
> Am 20.04.23 um 17:57 schrieb Thomas Gleixner:
> I quickly applied it on top of your branch, but I am getting:
As I said it was untested. I was traveling and did not have access to a
machine to even build it completely. Fixed up and tested version below.
Thanks,
tglx
---
--- a/arch/x86/include/asm/apicdef.h
+++ b/arch/x86/include/asm/apicdef.h
@@ -138,7 +138,8 @@
#define APIC_EILVT_MASKED (1 << 16)
#define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
-#define APIC_BASE_MSR 0x800
+#define APIC_BASE_MSR 0x800
+#define APIC_X2APIC_ID_MSR 0x802
#define XAPIC_ENABLE (1UL << 11)
#define X2APIC_ENABLE (1UL << 10)
@@ -162,6 +163,7 @@
#define APIC_CPUID(apicid) ((apicid) & XAPIC_DEST_CPUS_MASK)
#define NUM_APIC_CLUSTERS ((BAD_APICID + 1) >> XAPIC_DEST_CPUS_SHIFT)
+#ifndef __ASSEMBLY__
/*
* the local APIC register structure, memory mapped. Not terribly well
* tested, but we might eventually use this one in the future - the
@@ -435,4 +437,5 @@ enum apic_delivery_modes {
APIC_DELIVERY_MODE_EXTINT = 7,
};
+#endif /* !__ASSEMBLY__ */
#endif /* _ASM_X86_APICDEF_H */
--- a/arch/x86/include/asm/smp.h
+++ b/arch/x86/include/asm/smp.h
@@ -195,14 +195,13 @@ extern void nmi_selftest(void);
#endif
extern unsigned int smpboot_control;
+extern unsigned long apic_mmio_base;
#endif /* !__ASSEMBLY__ */
/* Control bits for startup_64 */
-#define STARTUP_APICID_CPUID_1F 0x80000000
-#define STARTUP_APICID_CPUID_0B 0x40000000
-#define STARTUP_APICID_CPUID_01 0x20000000
-#define STARTUP_APICID_SEV_ES 0x10000000
+#define STARTUP_READ_APICID 0x80000000
+#define STARTUP_APICID_SEV_ES 0x40000000
/* Top 8 bits are reserved for control */
#define STARTUP_PARALLEL_MASK 0xFF000000
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -101,6 +101,8 @@ static int apic_extnmi __ro_after_init =
*/
static bool virt_ext_dest_id __ro_after_init;
+unsigned long apic_mmio_base __ro_after_init;
+
/*
* Map cpu index to physical APIC ID
*/
@@ -2164,6 +2166,7 @@ void __init register_lapic_address(unsig
if (!x2apic_mode) {
set_fixmap_nocache(FIX_APIC_BASE, address);
+ apic_mmio_base = APIC_BASE;
apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
APIC_BASE, address);
}
--- a/arch/x86/kernel/head_64.S
+++ b/arch/x86/kernel/head_64.S
@@ -24,8 +24,10 @@
#include "../entry/calling.h"
#include <asm/export.h>
#include <asm/nospec-branch.h>
+#include <asm/apicdef.h>
#include <asm/fixmap.h>
#include <asm/smp.h>
+
#include <asm/sev-common.h>
/*
@@ -237,37 +239,25 @@ SYM_INNER_LABEL(secondary_startup_64_no_
#ifdef CONFIG_SMP
/*
- * For parallel boot, the APIC ID is retrieved from CPUID, and then
- * used to look up the CPU number. For booting a single CPU, the
- * CPU number is encoded in smpboot_control.
+ * For parallel boot, the APIC ID is either retrieved the APIC or
+ * from CPUID, and then used to look up the CPU number.
+ * For booting a single CPU, the CPU number is encoded in
+ * smpboot_control.
*
- * Bit 31 STARTUP_APICID_CPUID_1F flag (use CPUID 0x1f)
- * Bit 30 STARTUP_APICID_CPUID_0B flag (use CPUID 0x0b)
- * Bit 29 STARTUP_APICID_CPUID_01 flag (use CPUID 0x01)
- * Bit 28 STARTUP_APICID_SEV_ES flag (CPUID 0x0b via GHCB MSR)
+ * Bit 31 STARTUP_APICID_READ (Read APICID from APIC)
+ * Bit 30 STARTUP_APICID_SEV_ES flag (CPUID 0x0b via GHCB MSR)
* Bit 0-23 CPU# if STARTUP_APICID_CPUID_xx flags are not set
*/
movl smpboot_control(%rip), %ecx
+ testl $STARTUP_READ_APICID, %ecx
+ jnz .Lread_apicid
#ifdef CONFIG_AMD_MEM_ENCRYPT
testl $STARTUP_APICID_SEV_ES, %ecx
jnz .Luse_sev_cpuid_0b
#endif
- testl $STARTUP_APICID_CPUID_1F, %ecx
- jnz .Luse_cpuid_1f
- testl $STARTUP_APICID_CPUID_0B, %ecx
- jnz .Luse_cpuid_0b
- testl $STARTUP_APICID_CPUID_01, %ecx
- jnz .Luse_cpuid_01
andl $(~STARTUP_PARALLEL_MASK), %ecx
jmp .Lsetup_cpu
-.Luse_cpuid_01:
- mov $0x01, %eax
- cpuid
- mov %ebx, %edx
- shr $24, %edx
- jmp .Lsetup_AP
-
#ifdef CONFIG_AMD_MEM_ENCRYPT
.Luse_sev_cpuid_0b:
/* Set the GHCB MSR to request CPUID 0x0B_EDX */
@@ -292,24 +282,30 @@ SYM_INNER_LABEL(secondary_startup_64_no_
jmp .Lsetup_AP
#endif
-.Luse_cpuid_0b:
- mov $0x0B, %eax
- xorl %ecx, %ecx
- cpuid
+.Lread_apicid:
+ mov $MSR_IA32_APICBASE, %ecx
+ rdmsr
+ testl $X2APIC_ENABLE, %eax
+ jnz .Lread_apicid_msr
+
+ /* Read the APIC ID from the fix-mapped MMIO space. */
+ movq apic_mmio_base(%rip), %rcx
+ addq $APIC_ID, %rcx
+ movl (%rcx), %eax
+ shr $24, %eax
jmp .Lsetup_AP
-.Luse_cpuid_1f:
- mov $0x1f, %eax
- xorl %ecx, %ecx
- cpuid
+.Lread_apicid_msr:
+ mov $APIC_X2APIC_ID_MSR, %ecx
+ rdmsr
.Lsetup_AP:
- /* EDX contains the APIC ID of the current CPU */
+ /* EAX contains the APIC ID of the current CPU */
xorq %rcx, %rcx
leaq cpuid_to_apicid(%rip), %rbx
.Lfind_cpunr:
- cmpl (%rbx,%rcx,4), %edx
+ cmpl (%rbx,%rcx,4), %eax
jz .Lsetup_cpu
inc %ecx
#ifdef CONFIG_FORCE_NR_CPUS
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -1253,41 +1253,22 @@ bool __init arch_cpuhp_init_parallel_bri
return false;
}
- /* Encrypted guests require special CPUID handling. */
+ /* Encrypted guests require special handling. */
if (cc_platform_has(CC_ATTR_GUEST_STATE_ENCRYPT)) {
switch (cc_get_vendor()) {
case CC_VENDOR_AMD:
ctrl = STARTUP_APICID_SEV_ES;
if (topology_extended_leaf == 0x0b)
- goto setup;
+ break;
fallthrough;
default:
pr_info("Parallel CPU startup disabled due to guest state encryption\n");
return false;
}
+ } else {
+ ctrl = STARTUP_READ_APICID;
}
- switch (topology_extended_leaf) {
- case 0x0b:
- ctrl = STARTUP_APICID_CPUID_0B;
- break;
- case 0x1f:
- ctrl = STARTUP_APICID_CPUID_1F;
- break;
- case 0x00:
- /* For !x2APIC mode 8 bits from leaf 0x01 are sufficient. */
- if (!x2apic_mode) {
- ctrl = STARTUP_APICID_CPUID_01;
- break;
- }
- fallthrough;
- default:
- pr_info("Parallel CPU startup disabled. Unsupported topology leaf %u\n",
- topology_extended_leaf);
- return false;
- }
-
-setup:
pr_debug("Parallel CPU startup enabled: 0x%08x\n", ctrl);
smpboot_control = ctrl;
return true;
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^ permalink raw reply
* Re: [PATCH 1/3] ARM: dts: sun5i: chip: Enable bluetooth
From: Jonathan McDowell @ 2023-04-20 19:12 UTC (permalink / raw)
To: Andre Przywara, Saravana Kannan, Greg Kroah-Hartman
Cc: Rob Herring, Krzysztof Kozlowski, Chen-Yu Tsai, Jernej Skrabec,
Samuel Holland, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel
In-Reply-To: <20230416012421.255bfd19@slackpad.lan>
On Sun, Apr 16, 2023 at 01:24:21AM +0100, Andre Przywara wrote:
> On Sat, 15 Apr 2023 18:46:03 +0100
> Jonathan McDowell <noodles@earth.li> wrote:
>
> > The C.H.I.P has an rtl8723bs device with the bluetooth interface hooked
> > up on UART3. Support for this didn't exist in mainline when the DTS was
> > initially added, but it does now, so enable it.
> >
> > Signed-off-by: Jonathan McDowell <noodles@earth.li>
> > ---
> > arch/arm/boot/dts/sun5i-r8-chip.dts | 4 ++++
> > 1 file changed, 4 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/sun5i-r8-chip.dts b/arch/arm/boot/dts/sun5i-r8-chip.dts
> > index fd37bd1f3920..4d72a181d8aa 100644
> > --- a/arch/arm/boot/dts/sun5i-r8-chip.dts
> > +++ b/arch/arm/boot/dts/sun5i-r8-chip.dts
> > @@ -255,6 +255,10 @@ &uart3 {
> > pinctrl-0 = <&uart3_pg_pins>,
> > <&uart3_cts_rts_pg_pins>;
> > status = "okay";
> > +
> > + bluetooth {
> > + compatible = "realtek,rtl8723bs-bt";
> > + }
>
> As the kernel test robot already pointed out, there is a semicolon
> missing here.
> Otherwise looks good (dt-validate passes), but don't know if there are
> any wakeup GPIOs connected (can't seem to find a schematic?).
So there are wakeups, but if I add:
device-wake-gpios = <&axp_gpio 3 GPIO_ACTIVE_LOW>;
host-wake-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
then some odd sort of dependency issue happens where the serial port
load is deferred waiting for the GPIO to appear, and then the device
doesn't work. Error in dmesg is:
serial serial0-0: deferred probe pending
on 6.3-rc and on 6.1 I get:
dw-apb-uart 1c28c00.serial: Failed to create device link (0x180) with axp20x-gpio
I'm not clear why it's trying to link the serial port to the GPIO; it
seems that it should be the bluetooth device that depends on both the
UART and the GPIO, and that the GPIO is actually optional so shouldn't
hold up loading, but I can't see how that should be represented.
Adding Greg + Saravana in the hope they can tell me what I've done wrong
here. The LED driver using a different GPIO line on the axp209 works
fine, so the device is definitely loaded and working ok.
> > };
> >
> > &usb_otg {
>
J.
--
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| : :' : Happy to accept PGP signed
| `. `' or encrypted mail - RSA
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* Re: [PATCH 2/3] ARM: dts: sun5i: Add port E pinmux settings for mmc2
From: Jonathan McDowell @ 2023-04-20 19:13 UTC (permalink / raw)
To: Andre Przywara
Cc: Rob Herring, Krzysztof Kozlowski, Chen-Yu Tsai, Jernej Skrabec,
Samuel Holland, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel
In-Reply-To: <20230416014756.2270af13@slackpad.lan>
On Sun, Apr 16, 2023 at 01:47:56AM +0100, Andre Przywara wrote:
> On Sat, 15 Apr 2023 18:46:24 +0100
> Jonathan McDowell <noodles@earth.li> wrote:
>
> Hi,
>
> > These alternate pins for mmc2 are brought out to the 40 pin U14 header
> > on the C.H.I.P and can be used to add an external MMC device with a 4
> > bit interface. See
> >
> > https://byteporter.com/ntc-chip-micro-sd-slot/
> >
> > for further details on how.
> >
> > Signed-off-by: Jonathan McDowell <noodles@earth.li>
> > ---
> > arch/arm/boot/dts/sun5i.dtsi | 8 ++++++++
> > 1 file changed, 8 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
> > index 250d6b87ab4d..e4922506ce22 100644
> > --- a/arch/arm/boot/dts/sun5i.dtsi
> > +++ b/arch/arm/boot/dts/sun5i.dtsi
> > @@ -517,6 +517,14 @@ mmc2_4bit_pc_pins: mmc2-4bit-pc-pins {
> > bias-pull-up;
> > };
> >
>
> As this seems to be a highly non-standard and rare modification, that
> doesn't even get used in the mainline DT, please add a:
> /omit-if-no-ref/
> line, so we don't get this into every sun5i board.
Neat, will add in v2.
> Otherwise looks good, though I don't know if that should belong into
> the same DT overlay that is probably used to also enable the MMC2 node.
I pondered that, but we already have the mmc2-4bit-pc-pins definition
here so it seemed helpful to add the pe-pins too.
> > + mmc2_4bit_pe_pins: mmc2-4bit-pe-pins {
> > + pins = "PE4", "PE5", "PE6", "PE7",
> > + "PE8", "PE9";
> > + function = "mmc2";
> > + drive-strength = <30>;
> > + bias-pull-up;
> > + };
> > +
> > mmc2_8bit_pins: mmc2-8bit-pins {
> > pins = "PC6", "PC7", "PC8", "PC9",
> > "PC10", "PC11", "PC12", "PC13",
>
J.
--
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* Re: [PATCH 2/6] drm: bridge: samsung-dsim: Fix PMS Calculator on imx8m[mnp]
From: Adam Ford @ 2023-04-20 19:15 UTC (permalink / raw)
To: Alexander Stein
Cc: Marek Vasut, dri-devel, Krzysztof Kozlowski, aford,
Frieder Schrempf, Laurent Pinchart, Andrzej Hajda, m.szyprowski,
Robert Foss, Jernej Skrabec, Jagan Teki, NXP Linux Team,
devicetree, Jonas Karlman, Sascha Hauer, Rob Herring,
linux-arm-kernel, Neil Armstrong, linux-kernel,
Pengutronix Kernel Team, Shawn Guo
In-Reply-To: <CAHCN7xK0Dban7ueB_ASrTOjqWK0++ujOoQ_RZpz=FR2Fktzy0g@mail.gmail.com>
On Tue, Apr 18, 2023 at 6:53 AM Adam Ford <aford173@gmail.com> wrote:
>
> On Mon, Apr 17, 2023 at 2:00 AM Alexander Stein
> <alexander.stein@ew.tq-group.com> wrote:
> >
> > Hi,
> >
> > Am Montag, 17. April 2023, 00:31:24 CEST schrieb Adam Ford:
> > > On Sun, Apr 16, 2023 at 5:07 PM Marek Vasut <marex@denx.de> wrote:
> > > > On 4/15/23 12:40, Adam Ford wrote:
> > > > > According to Table 13-45 of the i.MX8M Mini Reference Manual, the min
> > > > > and max values for M and the frequency range for the VCO_out
> > > > > calculator were incorrect. This also appears to be the case for the
> > > > > imx8mn and imx8mp.
> > > > >
> > > > > To fix this, make new variables to hold the min and max values of m
> > > > > and the minimum value of VCO_out, and update the PMS calculator to
> > > > > use these new variables instead of using hard-coded values to keep
> > > > > the backwards compatibility with other parts using this driver.
> > > >
> > > > [...]
> > > >
> > > > > static const struct samsung_dsim_driver_data imx8mm_dsi_driver_data =
> > > > > {
> > > > >
> > > > > @@ -470,6 +485,9 @@ static const struct samsung_dsim_driver_data
> > > > > imx8mm_dsi_driver_data = {> >
> > > > > */
> > > > >
> > > > > .pll_p_offset = 14,
> > > > > .reg_values = imx8mm_dsim_reg_values,
> > > > >
> > > > > + .m_min = 64,
> > > > > + .m_max = 1023,
> > > > > + .vco_min = 1050,
> > > >
> > > > You might want to call this 'min_freq' since there is a 'max_freq' which
> > > > seems to indicate what VCO max frequency is.
> > > >
> > > > Note that the same datasheet contains the following information:
> > > > "
> > > > MIPI_DPHY_M_PLLPMS field descriptions
> > > >
> > > > 12–4 PMS_M
> > > > Specifies the PLL PMS value for the M divider
> > > > NOTE: The programmable divider range should be within 25 to 125 to
> > > > ensure PLL stability.
> > >
> > > I was confused by this because this statement is not consistent with
> > > the link they reference jumps me to the table where it reads M is
> > > between 64 and 1023.
> > >
> > > > NOTE: The M and P divider values should be considered together to ensure
> > > > VCO ouput frequency
> > > > (VCO_out) range is between 350 MHz to 750 MHz.
> > > > Please refer to the topic DPHY PLL for more information.
> > >
> > > I was confused by this too, because the NXP documentation reads the
> > > 350 - 750MHz that you state, but "Table 13-45: DPHY PLL Parameters"
> > > which immediately follows that sentence on page 4158 shows VCO_out is
> > > between 1050-2100 MHz.
I reached out to my NXP rep asking if the VCO_out is 350-750 or if it
should be 1050-2100, and received the following statement:
" Yes it is definitely wrong, the one that is part of the NOTE in
MIPI_DPHY_M_PLLPMS register table against PMS_P, PMS_M and PMS_S is
not correct. I will report this to Doc team, the one customer should
be take into account is the Table 13-40 DPHY PLL Parameters and the
Note above."
Table 13-40 (for the Nano) reads the VCO_out is 1050-2100, despite
other text stating 350-750MHz, so I believe this patch is appropriate.
I'll add the above statement to the commit message as confirmation
when I submit a V2 of this series.
adam
> > >
> > > I compared the PMS values for a variety of frequencies to those that
> > > were set in the downstream NXP code, and the PMS values matched.
> > > Maybe someone from NXP can explain the discrepancy.
> >
> > Also note that, according to Table 13-28 in RM (Rev 2 07/2022) for i.MX8M
> > Nano, VCO_out and Fout has a maximum of 1500MHz only. Although the note above
> > mentions a range of 1050-2100MHz...
>
> I looked up the limits in NXP's downstream kernel [1] , and I believe
> these values match the table in the reference manual instead of the
> conflicting sentence. I am guessing this is why the PMS values I get
> match those of the NXP downstream kernel.
>
> adam
>
> [1] - https://github.com/nxp-imx/linux-imx/blob/lf-6.1.y/drivers/gpu/drm/imx/sec_mipi_pll_1432x.h#L38
>
> >
> > Best regards,
> > Alexander
> > --
> > TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
> > Amtsgericht München, HRB 105018
> > Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
> > http://www.tq-group.com/
> >
> >
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^ permalink raw reply
* [PATCH] firmware: arm_scmi: Fix incorrect alloc_workqueue() invocation
From: Tejun Heo @ 2023-04-20 19:33 UTC (permalink / raw)
To: Sudeep Holla
Cc: Cristian Marussi, linux-arm-kernel, linux-kernel, kernel-team
scmi_xfer_raw_worker_init() is specifying a flag, WQ_SYSFS, as @max_active.
Fix it by or'ing WQ_SYSFS into @flags so that it actually enables sysfs
interface and using 0 for @max_active for the default setting.
Signed-off-by: Tejun Heo <tj@kernel.org>
---
drivers/firmware/arm_scmi/raw_mode.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/firmware/arm_scmi/raw_mode.c
+++ b/drivers/firmware/arm_scmi/raw_mode.c
@@ -1066,7 +1066,7 @@ static int scmi_xfer_raw_worker_init(str
raw->wait_wq = alloc_workqueue("scmi-raw-wait-wq-%d",
WQ_UNBOUND | WQ_FREEZABLE |
- WQ_HIGHPRI, WQ_SYSFS, raw->id);
+ WQ_HIGHPRI | WQ_SYSFS, 0, raw->id);
if (!raw->wait_wq)
return -ENOMEM;
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* [PATCH] perf/arm-cci: Slightly optimize cci_pmu_sync_counters()
From: Christophe JAILLET @ 2023-04-20 20:27 UTC (permalink / raw)
To: Will Deacon, Mark Rutland
Cc: linux-kernel, kernel-janitors, Christophe JAILLET,
linux-arm-kernel
When the 'mask' bitmap is cleared, it is better to use its full maximum
size instead of only the needed size.
This lets the compiler optimize it because the size is now known at compile
time. HW_CNTRS_MAX is small (i.e. currently 9), so a call to memset() is
saved.
Also, as 'mask' is local to the function, the non-atomic __set_bit() can
also safely be used here.
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
---
drivers/perf/arm-cci.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/perf/arm-cci.c b/drivers/perf/arm-cci.c
index 03b1309875ae..998259f1d973 100644
--- a/drivers/perf/arm-cci.c
+++ b/drivers/perf/arm-cci.c
@@ -645,7 +645,7 @@ static void cci_pmu_sync_counters(struct cci_pmu *cci_pmu)
struct cci_pmu_hw_events *cci_hw = &cci_pmu->hw_events;
DECLARE_BITMAP(mask, HW_CNTRS_MAX);
- bitmap_zero(mask, cci_pmu->num_cntrs);
+ bitmap_zero(mask, HW_CNTRS_MAX);
for_each_set_bit(i, cci_pmu->hw_events.used_mask, cci_pmu->num_cntrs) {
struct perf_event *event = cci_hw->events[i];
@@ -656,7 +656,7 @@ static void cci_pmu_sync_counters(struct cci_pmu *cci_pmu)
if (event->hw.state & PERF_HES_STOPPED)
continue;
if (event->hw.state & PERF_HES_ARCH) {
- set_bit(i, mask);
+ __set_bit(i, mask);
event->hw.state &= ~PERF_HES_ARCH;
}
}
--
2.34.1
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^ permalink raw reply related
* Re: [PATCH] dt-bindings: arm/soc: mediatek: Drop unneeded quotes
From: Rob Herring @ 2023-04-20 20:44 UTC (permalink / raw)
To: Rob Herring
Cc: devicetree, AngeloGioacchino Del Regno, Krzysztof Kozlowski,
linux-arm-kernel, Matthias Brugger, linux-mediatek, linux-kernel
In-Reply-To: <20230322173501.3970991-1-robh@kernel.org>
On Wed, 22 Mar 2023 12:34:59 -0500, Rob Herring wrote:
> Cleanup bindings dropping unneeded quotes. Once all these are fixed,
> checking for this can be enabled in yamllint.
>
> Signed-off-by: Rob Herring <robh@kernel.org>
> ---
> .../devicetree/bindings/arm/mediatek/mediatek,infracfg.yaml | 4 ++--
> .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml | 4 ++--
> .../bindings/arm/mediatek/mediatek,mt7622-pcie-mirror.yaml | 4 ++--
> .../devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml | 4 ++--
> .../bindings/arm/mediatek/mediatek,mt7986-wed-pcie.yaml | 4 ++--
> .../bindings/arm/mediatek/mediatek,mt8186-clock.yaml | 4 ++--
> .../bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml | 4 ++--
> .../bindings/arm/mediatek/mediatek,mt8192-clock.yaml | 4 ++--
> .../bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml | 4 ++--
> .../bindings/arm/mediatek/mediatek,mt8195-clock.yaml | 4 ++--
> .../bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml | 4 ++--
> .../devicetree/bindings/arm/mediatek/mediatek,pericfg.yaml | 4 ++--
> Documentation/devicetree/bindings/soc/mediatek/devapc.yaml | 4 ++--
> 13 files changed, 26 insertions(+), 26 deletions(-)
>
Applied, thanks!
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* [PATCH RESEND v2 1/2] dt-bindings: input: atmel,maxtouch: add linux,keycodes
From: André Apitzsch @ 2023-04-20 21:03 UTC (permalink / raw)
To: Nick Dyer, Dmitry Torokhov, Rob Herring, Krzysztof Kozlowski,
Nicolas Ferre, Alexandre Belloni, Claudiu Beznea, Linus Walleij
Cc: linux-input, devicetree, linux-arm-kernel, linux-kernel,
André Apitzsch, Krzysztof Kozlowski
In-Reply-To: <20230407-atmel_keys-v2-0-e7b016886109@apitzsch.eu>
In some configurations the touch controller can support the touch keys.
Document the linux,keycodes property that enables those keys and
specifies the keycodes that should be used to report the key events.
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: André Apitzsch <git@apitzsch.eu>
---
Documentation/devicetree/bindings/input/atmel,maxtouch.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/input/atmel,maxtouch.yaml b/Documentation/devicetree/bindings/input/atmel,maxtouch.yaml
index 3ec579d63570..c40799355ed7 100644
--- a/Documentation/devicetree/bindings/input/atmel,maxtouch.yaml
+++ b/Documentation/devicetree/bindings/input/atmel,maxtouch.yaml
@@ -14,6 +14,9 @@ description: |
Atmel maXTouch touchscreen or touchpads such as the mXT244
and similar devices.
+allOf:
+ - $ref: input.yaml#
+
properties:
compatible:
const: atmel,maxtouch
@@ -60,6 +63,10 @@ properties:
or experiment to determine which bit corresponds to which input. Use
KEY_RESERVED for unused padding values.
+ linux,keycodes:
+ minItems: 1
+ maxItems: 8
+
atmel,wakeup-method:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
--
2.40.0
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* [PATCH RESEND v2 0/2] Input: atmel_mxt_ts - support capacitive keys
From: André Apitzsch @ 2023-04-20 21:03 UTC (permalink / raw)
To: Nick Dyer, Dmitry Torokhov, Rob Herring, Krzysztof Kozlowski,
Nicolas Ferre, Alexandre Belloni, Claudiu Beznea, Linus Walleij
Cc: linux-input, devicetree, linux-arm-kernel, linux-kernel,
André Apitzsch, Krzysztof Kozlowski
Add support for touch keys found in some Atmel touch controller
configurations.
Signed-off-by: André Apitzsch <git@apitzsch.eu>
---
Changes in v2:
* Added A-b, R-b tags
---
André Apitzsch (2):
dt-bindings: input: atmel,maxtouch: add linux,keycodes
Input: atmel_mxt_ts - support capacitive keys
.../devicetree/bindings/input/atmel,maxtouch.yaml | 7 ++
drivers/input/touchscreen/atmel_mxt_ts.c | 85 ++++++++++++++++++++++
2 files changed, 92 insertions(+)
---
base-commit: f2afccfefe7be1f7346564fe619277110d341f9b
change-id: 20230407-atmel_keys-7a49c6b677b2
Best regards,
--
André Apitzsch <git@apitzsch.eu>
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* [PATCH RESEND v2 2/2] Input: atmel_mxt_ts - support capacitive keys
From: André Apitzsch @ 2023-04-20 21:03 UTC (permalink / raw)
To: Nick Dyer, Dmitry Torokhov, Rob Herring, Krzysztof Kozlowski,
Nicolas Ferre, Alexandre Belloni, Claudiu Beznea, Linus Walleij
Cc: linux-input, devicetree, linux-arm-kernel, linux-kernel,
André Apitzsch
In-Reply-To: <20230407-atmel_keys-v2-0-e7b016886109@apitzsch.eu>
Add support for touch keys found in some Atmel touch controller
configurations.
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: André Apitzsch <git@apitzsch.eu>
---
drivers/input/touchscreen/atmel_mxt_ts.c | 85 ++++++++++++++++++++++++++++++++
1 file changed, 85 insertions(+)
diff --git a/drivers/input/touchscreen/atmel_mxt_ts.c b/drivers/input/touchscreen/atmel_mxt_ts.c
index 996bf434e1cb..eb368dd1abf0 100644
--- a/drivers/input/touchscreen/atmel_mxt_ts.c
+++ b/drivers/input/touchscreen/atmel_mxt_ts.c
@@ -55,6 +55,7 @@
#define MXT_TOUCH_KEYARRAY_T15 15
#define MXT_TOUCH_PROXIMITY_T23 23
#define MXT_TOUCH_PROXKEY_T52 52
+#define MXT_TOUCH_PTC_KEYS_T97 97
#define MXT_PROCI_GRIPFACE_T20 20
#define MXT_PROCG_NOISE_T22 22
#define MXT_PROCI_ONETOUCH_T24 24
@@ -326,9 +327,13 @@ struct mxt_data {
u16 T71_address;
u8 T9_reportid_min;
u8 T9_reportid_max;
+ u8 T15_reportid_min;
+ u8 T15_reportid_max;
u16 T18_address;
u8 T19_reportid;
u16 T44_address;
+ u8 T97_reportid_min;
+ u8 T97_reportid_max;
u8 T100_reportid_min;
u8 T100_reportid_max;
@@ -344,6 +349,9 @@ struct mxt_data {
u32 *t19_keymap;
unsigned int t19_num_keys;
+ u32 *t15_keymap;
+ unsigned int t15_num_keys;
+
enum mxt_suspend_mode suspend_mode;
u32 wakeup_method;
@@ -375,6 +383,7 @@ static bool mxt_object_readable(unsigned int type)
case MXT_TOUCH_KEYARRAY_T15:
case MXT_TOUCH_PROXIMITY_T23:
case MXT_TOUCH_PROXKEY_T52:
+ case MXT_TOUCH_PTC_KEYS_T97:
case MXT_TOUCH_MULTITOUCHSCREEN_T100:
case MXT_PROCI_GRIPFACE_T20:
case MXT_PROCG_NOISE_T22:
@@ -891,6 +900,25 @@ static void mxt_proc_t9_message(struct mxt_data *data, u8 *message)
data->update_input = true;
}
+static void mxt_proc_t15_messages(struct mxt_data *data, u8 *message)
+{
+ struct input_dev *input_dev = data->input_dev;
+ unsigned long keystates = get_unaligned_le32(&message[2]);
+ int key;
+
+ for (key = 0; key < data->t15_num_keys; key++) {
+ input_report_key(input_dev, data->t15_keymap[key],
+ !!(keystates & BIT(key)));
+ }
+
+ data->update_input = true;
+}
+
+static void mxt_proc_t97_messages(struct mxt_data *data, u8 *message)
+{
+ mxt_proc_t15_messages(data, message);
+}
+
static void mxt_proc_t100_message(struct mxt_data *data, u8 *message)
{
struct device *dev = &data->client->dev;
@@ -1017,6 +1045,12 @@ static int mxt_proc_message(struct mxt_data *data, u8 *message)
} else if (report_id >= data->T9_reportid_min &&
report_id <= data->T9_reportid_max) {
mxt_proc_t9_message(data, message);
+ } else if (report_id >= data->T15_reportid_min &&
+ report_id <= data->T15_reportid_max) {
+ mxt_proc_t15_messages(data, message);
+ } else if (report_id >= data->T97_reportid_min &&
+ report_id <= data->T97_reportid_max) {
+ mxt_proc_t97_messages(data, message);
} else if (report_id >= data->T100_reportid_min &&
report_id <= data->T100_reportid_max) {
mxt_proc_t100_message(data, message);
@@ -1689,9 +1723,13 @@ static void mxt_free_object_table(struct mxt_data *data)
data->T71_address = 0;
data->T9_reportid_min = 0;
data->T9_reportid_max = 0;
+ data->T15_reportid_min = 0;
+ data->T15_reportid_max = 0;
data->T18_address = 0;
data->T19_reportid = 0;
data->T44_address = 0;
+ data->T97_reportid_min = 0;
+ data->T97_reportid_max = 0;
data->T100_reportid_min = 0;
data->T100_reportid_max = 0;
data->max_reportid = 0;
@@ -1764,6 +1802,10 @@ static int mxt_parse_object_table(struct mxt_data *data,
object->num_report_ids - 1;
data->num_touchids = object->num_report_ids;
break;
+ case MXT_TOUCH_KEYARRAY_T15:
+ data->T15_reportid_min = min_id;
+ data->T15_reportid_max = max_id;
+ break;
case MXT_SPT_COMMSCONFIG_T18:
data->T18_address = object->start_address;
break;
@@ -1773,6 +1815,10 @@ static int mxt_parse_object_table(struct mxt_data *data,
case MXT_SPT_GPIOPWM_T19:
data->T19_reportid = min_id;
break;
+ case MXT_TOUCH_PTC_KEYS_T97:
+ data->T97_reportid_min = min_id;
+ data->T97_reportid_max = max_id;
+ break;
case MXT_TOUCH_MULTITOUCHSCREEN_T100:
data->multitouch = MXT_TOUCH_MULTITOUCHSCREEN_T100;
data->T100_reportid_min = min_id;
@@ -2050,6 +2096,7 @@ static int mxt_initialize_input_device(struct mxt_data *data)
int error;
unsigned int num_mt_slots;
unsigned int mt_flags = 0;
+ int i;
switch (data->multitouch) {
case MXT_TOUCH_MULTI_T9:
@@ -2095,6 +2142,10 @@ static int mxt_initialize_input_device(struct mxt_data *data)
input_dev->open = mxt_input_open;
input_dev->close = mxt_input_close;
+ input_dev->keycode = data->t15_keymap;
+ input_dev->keycodemax = data->t15_num_keys;
+ input_dev->keycodesize = sizeof(data->t15_keymap[0]);
+
input_set_capability(input_dev, EV_KEY, BTN_TOUCH);
/* For single touch */
@@ -2162,6 +2213,12 @@ static int mxt_initialize_input_device(struct mxt_data *data)
0, 255, 0, 0);
}
+ /* For T15 and T97 Key Array */
+ if (data->T15_reportid_min || data->T97_reportid_min) {
+ for (i = 0; i < data->t15_num_keys; i++)
+ input_set_capability(input_dev, EV_KEY, data->t15_keymap[i]);
+ }
+
input_set_drvdata(input_dev, data);
error = input_register_device(input_dev);
@@ -3080,8 +3137,10 @@ static void mxt_input_close(struct input_dev *dev)
static int mxt_parse_device_properties(struct mxt_data *data)
{
static const char keymap_property[] = "linux,gpio-keymap";
+ static const char buttons_property[] = "linux,keycodes";
struct device *dev = &data->client->dev;
u32 *keymap;
+ u32 *buttonmap;
int n_keys;
int error;
@@ -3111,6 +3170,32 @@ static int mxt_parse_device_properties(struct mxt_data *data)
data->t19_num_keys = n_keys;
}
+ if (device_property_present(dev, buttons_property)) {
+ n_keys = device_property_count_u32(dev, buttons_property);
+ if (n_keys <= 0) {
+ error = n_keys < 0 ? n_keys : -EINVAL;
+ dev_err(dev, "invalid/malformed '%s' property: %d\n",
+ buttons_property, error);
+ return error;
+ }
+
+ buttonmap = devm_kmalloc_array(dev, n_keys, sizeof(*buttonmap),
+ GFP_KERNEL);
+ if (!buttonmap)
+ return -ENOMEM;
+
+ error = device_property_read_u32_array(dev, buttons_property,
+ buttonmap, n_keys);
+ if (error) {
+ dev_err(dev, "failed to parse '%s' property: %d\n",
+ buttons_property, error);
+ return error;
+ }
+
+ data->t15_keymap = buttonmap;
+ data->t15_num_keys = n_keys;
+ }
+
return 0;
}
--
2.40.0
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* [PATCH net-next] net: mtk_eth_soc: mediatek: fix ppe flow accounting for v1 hardware
From: Daniel Golle @ 2023-04-20 21:06 UTC (permalink / raw)
To: netdev, linux-mediatek, linux-arm-kernel, linux-kernel,
Felix Fietkau, John Crispin, Sean Wang, Mark Lee,
Lorenzo Bianconi, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Matthias Brugger, AngeloGioacchino Del Regno
From: Felix Fietkau <nbd@nbd.name>
Older chips (like MT7622) use a different bit in ib2 to enable hardware
counter support. Add macros for both and select the appropriate bit.
Fixes: 3fbe4d8c0e53 ("net: ethernet: mtk_eth_soc: ppe: add support for flow accounting")
Signed-off-by: Felix Fietkau <nbd@nbd.name>
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
drivers/net/ethernet/mediatek/mtk_ppe.c | 10 ++++++++--
drivers/net/ethernet/mediatek/mtk_ppe.h | 3 ++-
2 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_ppe.c b/drivers/net/ethernet/mediatek/mtk_ppe.c
index dd9581334b054..9129821f3ab8f 100644
--- a/drivers/net/ethernet/mediatek/mtk_ppe.c
+++ b/drivers/net/ethernet/mediatek/mtk_ppe.c
@@ -601,6 +601,7 @@ __mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_foe_entry *entry,
struct mtk_eth *eth = ppe->eth;
u16 timestamp = mtk_eth_timestamp(eth);
struct mtk_foe_entry *hwe;
+ u32 val;
if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
entry->ib1 &= ~MTK_FOE_IB1_BIND_TIMESTAMP_V2;
@@ -617,8 +618,13 @@ __mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_foe_entry *entry,
wmb();
hwe->ib1 = entry->ib1;
- if (ppe->accounting)
- *mtk_foe_entry_ib2(eth, hwe) |= MTK_FOE_IB2_MIB_CNT;
+ if (ppe->accounting) {
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
+ val = MTK_FOE_IB2_MIB_CNT_V2;
+ else
+ val = MTK_FOE_IB2_MIB_CNT;
+ *mtk_foe_entry_ib2(eth, hwe) |= val;
+ }
dma_wmb();
diff --git a/drivers/net/ethernet/mediatek/mtk_ppe.h b/drivers/net/ethernet/mediatek/mtk_ppe.h
index e1aab2e8e2629..e51de31a52ec6 100644
--- a/drivers/net/ethernet/mediatek/mtk_ppe.h
+++ b/drivers/net/ethernet/mediatek/mtk_ppe.h
@@ -55,9 +55,10 @@ enum {
#define MTK_FOE_IB2_PSE_QOS BIT(4)
#define MTK_FOE_IB2_DEST_PORT GENMASK(7, 5)
#define MTK_FOE_IB2_MULTICAST BIT(8)
+#define MTK_FOE_IB2_MIB_CNT BIT(10)
#define MTK_FOE_IB2_WDMA_QID2 GENMASK(13, 12)
-#define MTK_FOE_IB2_MIB_CNT BIT(15)
+#define MTK_FOE_IB2_MIB_CNT_V2 BIT(15)
#define MTK_FOE_IB2_WDMA_DEVIDX BIT(16)
#define MTK_FOE_IB2_WDMA_WINFO BIT(17)
--
2.40.0
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^ permalink raw reply related
* [PATCH] arm64: Also reset KASAN tag if page is not PG_mte_tagged
From: Peter Collingbourne @ 2023-04-20 21:09 UTC (permalink / raw)
To: catalin.marinas, andreyknvl
Cc: Peter Collingbourne, Qun-wei Lin (林群崴),
Guangye Yang (杨光业), linux-mm,
Chinwen Chang (張錦文), kasan-dev, ryabinin.a.a,
linux-arm-kernel, vincenzo.frascino, will, eugenis, stable
Consider the following sequence of events:
1) A page in a PROT_READ|PROT_WRITE VMA is faulted.
2) Page migration allocates a page with the KASAN allocator,
causing it to receive a non-match-all tag, and uses it
to replace the page faulted in 1.
3) The program uses mprotect() to enable PROT_MTE on the page faulted in 1.
As a result of step 3, we are left with a non-match-all tag for a page
with tags accessible to userspace, which can lead to the same kind of
tag check faults that commit e74a68468062 ("arm64: Reset KASAN tag in
copy_highpage with HW tags only") intended to fix.
The general invariant that we have for pages in a VMA with VM_MTE_ALLOWED
is that they cannot have a non-match-all tag. As a result of step 2, the
invariant is broken. This means that the fix in the referenced commit
was incomplete and we also need to reset the tag for pages without
PG_mte_tagged.
Fixes: e5b8d9218951 ("arm64: mte: reset the page tag in page->flags")
Cc: <stable@vger.kernel.org> # 5.15
Link: https://linux-review.googlesource.com/id/I7409cdd41acbcb215c2a7417c1e50d37b875beff
Signed-off-by: Peter Collingbourne <pcc@google.com>
---
arch/arm64/mm/copypage.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/mm/copypage.c b/arch/arm64/mm/copypage.c
index 4aadcfb01754..a7bb20055ce0 100644
--- a/arch/arm64/mm/copypage.c
+++ b/arch/arm64/mm/copypage.c
@@ -21,9 +21,10 @@ void copy_highpage(struct page *to, struct page *from)
copy_page(kto, kfrom);
+ if (kasan_hw_tags_enabled())
+ page_kasan_tag_reset(to);
+
if (system_supports_mte() && page_mte_tagged(from)) {
- if (kasan_hw_tags_enabled())
- page_kasan_tag_reset(to);
/* It's a new page, shouldn't have been tagged yet */
WARN_ON_ONCE(!try_page_mte_tagging(to));
mte_copy_page_tags(kto, kfrom);
--
2.40.0.396.gfff15efe05-goog
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* ✅ PASS (SKIPPED 88 of 167): Test report for for-kernelci (6.3.0-rc7, arm-next, 14f8db1c)
From: cki-project @ 2023-04-20 21:20 UTC (permalink / raw)
To: catalin.marinas, linux-arm-kernel, will
Hi, we tested your kernel and here are the results:
Overall result: PASSED
Merge: OK
Compile: OK
Test: OK
Tested-by: CKI Project <cki-project@redhat.com>
Kernel information:
Commit message: Merge branch 'for-next/core' into for-kernelci
You can find all the details about the test run at
https://datawarehouse.cki-project.org/kcidb/checkouts/85509
One or more kernel tests failed:
We also see the following known issues which are not related to your changes:
Issue: kdump - kexec_boot: image_arm64_probe: Bad arm64 image header
URL: https://gitlab.com/redhat/centos-stream/tests/kernel/kernel-tests/-/issues/1580
Affected tests:
aarch64 - kdump - kexec_boot
aarch64 - kdump - kexec-file-load
Issue: Firmware test suite: mv: cannot stat 'dtcompilerparser.tab.c': No such file or directory
URL: https://gitlab.com/redhat/centos-stream/tests/kernel/kernel-tests/-/issues/1544
Affected tests:
aarch64 - Firmware test suite
Issue: Firmware test suite: cannot stat 'dtcompilerparser.tab.c': No such file or directory
URL: https://gitlab.com/redhat/centos-stream/tests/kernel/kernel-tests/-/issues/1611
Affected tests:
aarch64 - Firmware test suite
Issue: xfstests - _check_xfs_filesystem: filesystem on /dev/nvme0n1p4 is inconsistent (r)
URL: https://bugzilla.redhat.com/show_bug.cgi?id=1989409
Affected tests:
aarch64 - xfstests - btrfs
If you find a failure unrelated to your changes, please ask the test maintainer to review it.
This will prevent the failures from being incorrectly reported in the future.
Please reply to this email if you have any questions about the tests that we
ran or if you have any suggestions on how to make future tests more effective.
,-. ,-.
( C ) ( K ) Continuous
`-',-.`-' Kernel
( I ) Integration
`-'
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^ permalink raw reply
* Re: [PATCH] dt-bindings: rng: Drop unneeded quotes
From: Rob Herring @ 2023-04-20 21:30 UTC (permalink / raw)
To: Olivia Mackall, Herbert Xu, Krzysztof Kozlowski, Neil Armstrong,
Kevin Hilman, Jerome Brunet, Martin Blumenstingl, Ray Jui,
Scott Branden, Broadcom internal kernel review list,
Matthias Brugger, AngeloGioacchino Del Regno
Cc: linux-crypto, devicetree, linux-arm-kernel, linux-amlogic,
linux-kernel, linux-mediatek
In-Reply-To: <20230327170153.4105594-1-robh@kernel.org>
On Mon, Mar 27, 2023 at 12:01:53PM -0500, Rob Herring wrote:
> Cleanup bindings dropping unneeded quotes. Once all these are fixed,
> checking for this can be enabled in yamllint.
>
> Signed-off-by: Rob Herring <robh@kernel.org>
> ---
> Documentation/devicetree/bindings/rng/amlogic,meson-rng.yaml | 4 ++--
> Documentation/devicetree/bindings/rng/brcm,iproc-rng200.yaml | 4 ++--
> Documentation/devicetree/bindings/rng/mtk-rng.yaml | 4 ++--
> Documentation/devicetree/bindings/rng/ti,keystone-rng.yaml | 2 +-
> 4 files changed, 7 insertions(+), 7 deletions(-)
Applied, thanks!
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^ permalink raw reply
* [PATCH] remoteproc: imx_dsp_rproc: use modern pm_ops
From: Arnd Bergmann @ 2023-04-20 21:36 UTC (permalink / raw)
To: Bjorn Andersson, Mathieu Poirier, Shawn Guo, Sascha Hauer
Cc: Arnd Bergmann, Pengutronix Kernel Team, Fabio Estevam,
NXP Linux Team, Shengjiu Wang, Iuliana Prodan, Daniel Baluta,
Markus Elfring, linux-remoteproc, linux-arm-kernel, linux-kernel
From: Arnd Bergmann <arnd@arndb.de>
Without CONFIG_PM, the driver warns about unused functions:
drivers/remoteproc/imx_dsp_rproc.c:1210:12: error: 'imx_dsp_runtime_suspend' defined but not used [-Werror=unused-function]
1210 | static int imx_dsp_runtime_suspend(struct device *dev)
| ^~~~~~~~~~~~~~~~~~~~~~~
drivers/remoteproc/imx_dsp_rproc.c:1178:12: error: 'imx_dsp_runtime_resume' defined but not used [-Werror=unused-function]
1178 | static int imx_dsp_runtime_resume(struct device *dev)
| ^~~~~~~~~~~~~~~~~~~~~~
Change the old SET_SYSTEM_SLEEP_PM_OPS()/SET_RUNTIME_PM_OPS()
helpers to their modern replacements that avoid the warning,
and remove the now unnecessary __maybe_unused annotations
on the other PM helper functions.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
drivers/remoteproc/imx_dsp_rproc.c | 11 +++++------
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/remoteproc/imx_dsp_rproc.c b/drivers/remoteproc/imx_dsp_rproc.c
index cab06dbf37fb..2d75dea43f20 100644
--- a/drivers/remoteproc/imx_dsp_rproc.c
+++ b/drivers/remoteproc/imx_dsp_rproc.c
@@ -1243,7 +1243,7 @@ static void imx_dsp_load_firmware(const struct firmware *fw, void *context)
release_firmware(fw);
}
-static __maybe_unused int imx_dsp_suspend(struct device *dev)
+static int imx_dsp_suspend(struct device *dev)
{
struct rproc *rproc = dev_get_drvdata(dev);
struct imx_dsp_rproc *priv = rproc->priv;
@@ -1278,7 +1278,7 @@ static __maybe_unused int imx_dsp_suspend(struct device *dev)
return pm_runtime_force_suspend(dev);
}
-static __maybe_unused int imx_dsp_resume(struct device *dev)
+static int imx_dsp_resume(struct device *dev)
{
struct rproc *rproc = dev_get_drvdata(dev);
int ret = 0;
@@ -1312,9 +1312,8 @@ static __maybe_unused int imx_dsp_resume(struct device *dev)
}
static const struct dev_pm_ops imx_dsp_rproc_pm_ops = {
- SET_SYSTEM_SLEEP_PM_OPS(imx_dsp_suspend, imx_dsp_resume)
- SET_RUNTIME_PM_OPS(imx_dsp_runtime_suspend,
- imx_dsp_runtime_resume, NULL)
+ SYSTEM_SLEEP_PM_OPS(imx_dsp_suspend, imx_dsp_resume)
+ RUNTIME_PM_OPS(imx_dsp_runtime_suspend, imx_dsp_runtime_resume, NULL)
};
static const struct of_device_id imx_dsp_rproc_of_match[] = {
@@ -1332,7 +1331,7 @@ static struct platform_driver imx_dsp_rproc_driver = {
.driver = {
.name = "imx-dsp-rproc",
.of_match_table = imx_dsp_rproc_of_match,
- .pm = &imx_dsp_rproc_pm_ops,
+ .pm = pm_ptr(&imx_dsp_rproc_pm_ops),
},
};
module_platform_driver(imx_dsp_rproc_driver);
--
2.39.2
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^ permalink raw reply related
* [PATCH] arm64: mte: Do not set PG_mte_tagged if tags were not initialized
From: Peter Collingbourne @ 2023-04-20 21:43 UTC (permalink / raw)
To: catalin.marinas
Cc: Peter Collingbourne, linux-arm-kernel, vincenzo.frascino, will,
eugenis, stable
The mte_sync_page_tags() function sets PG_mte_tagged if it initializes
page tags. Then we return to mte_sync_tags(), which sets PG_mte_tagged
again. At best, this is redundant. However, it is possible for
mte_sync_page_tags() to return without having initialized tags for the
page, i.e. in the case where check_swap is true (non-compound page),
is_swap_pte(old_pte) is false and pte_is_tagged is false. So at worst,
we set PG_mte_tagged on a page with uninitialized tags. This can happen
if, for example, page migration causes a PTE for an untagged page to
be replaced. If the userspace program subsequently uses mprotect() to
enable PROT_MTE for that page, the uninitialized tags will be exposed
to userspace.
Fix it by removing the redundant call to set_page_mte_tagged().
Fixes: e059853d14ca ("arm64: mte: Fix/clarify the PG_mte_tagged semantics")
Signed-off-by: Peter Collingbourne <pcc@google.com>
Cc: <stable@vger.kernel.org> # 6.1
Link: https://linux-review.googlesource.com/id/Ib02d004d435b2ed87603b858ef7480f7b1463052
---
arch/arm64/kernel/mte.c | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/kernel/mte.c b/arch/arm64/kernel/mte.c
index f5bcb0dc6267..7e89968bd282 100644
--- a/arch/arm64/kernel/mte.c
+++ b/arch/arm64/kernel/mte.c
@@ -66,13 +66,10 @@ void mte_sync_tags(pte_t old_pte, pte_t pte)
return;
/* if PG_mte_tagged is set, tags have already been initialised */
- for (i = 0; i < nr_pages; i++, page++) {
- if (!page_mte_tagged(page)) {
+ for (i = 0; i < nr_pages; i++, page++)
+ if (!page_mte_tagged(page))
mte_sync_page_tags(page, old_pte, check_swap,
pte_is_tagged);
- set_page_mte_tagged(page);
- }
- }
/* ensure the tags are visible before the PTE is set */
smp_wmb();
--
2.40.0.634.g4ca3ef3211-goog
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* Re: [PATCH 1/6] drm: bridge: samsung-dsim: Support multi-lane calculations
From: Adam Ford @ 2023-04-20 21:51 UTC (permalink / raw)
To: Lucas Stach
Cc: dri-devel, Krzysztof Kozlowski, aford, Laurent Pinchart,
Andrzej Hajda, Fabio Estevam, m.szyprowski, marex, Robert Foss,
David Airlie, Jernej Skrabec, Jagan Teki, NXP Linux Team,
devicetree, Daniel Vetter, Jonas Karlman, Sascha Hauer, Inki Dae,
Rob Herring, linux-arm-kernel, Neil Armstrong, linux-kernel,
Pengutronix Kernel Team, Shawn Guo
In-Reply-To: <19d2c40180d0b9176e17aa6e91c1e7f36f77f626.camel@pengutronix.de>
On Thu, Apr 20, 2023 at 8:43 AM Lucas Stach <l.stach@pengutronix.de> wrote:
>
> Am Donnerstag, dem 20.04.2023 um 08:24 -0500 schrieb Adam Ford:
> > On Thu, Apr 20, 2023 at 8:06 AM Lucas Stach <l.stach@pengutronix.de> wrote:
> > >
> > > Hi Adam,
> > >
> > > Am Mittwoch, dem 19.04.2023 um 05:47 -0500 schrieb Adam Ford:
> > > > On Mon, Apr 17, 2023 at 6:55 AM Adam Ford <aford173@gmail.com> wrote:
> > > > >
> > > > > On Mon, Apr 17, 2023 at 3:43 AM Lucas Stach <l.stach@pengutronix.de> wrote:
> > > > > >
> > > > > > Hi Adam,
> > > > > >
> > > > > > Am Samstag, dem 15.04.2023 um 05:40 -0500 schrieb Adam Ford:
> > > > > > > If there is more than one lane, the HFP, HBP, and HSA is calculated in
> > > > > > > bytes/pixel, then they are divided amongst the different lanes with some
> > > > > > > additional overhead. This is necessary to achieve higher resolutions while
> > > > > > > keeping the pixel clocks lower as the number of lanes increase.
> > > > > > >
> > > > > >
> > > > > > In the testing I did to come up with my patch "drm: bridge: samsung-
> > > > > > dsim: fix blanking packet size calculation" the number of lanes didn't
> > > > > > make any difference. My testing might be flawed, as I could only
> > > > > > measure the blanking after translation from MIPI DSI to DPI, so I'm
> > > > > > interested to know what others did here. How did you validate the
> > > > > > blanking with your patch? Would you have a chance to test my patch and
> > > > > > see if it works or breaks in your setup?
> > > >
> > > > Lucas,
> > > >
> > > > I tried your patch instead of mine. Yours is dependent on the
> > > > hs_clock being always set to the burst clock which is configured by
> > > > the device tree. I unrolled a bit of my stuff and replaced it with
> > > > yours. It worked at 1080p, but when I tried a few other resolutions,
> > > > they did not work. I assume it's because the DSI clock is fixed and
> > > > not changing based on the pixel clock. In the version I did, I only
> > > > did that math when the lanes were > 1. In your patch, you divide by 8,
> > > > and in mine, I fetch the bits-per-pixel (which is 8) and I divide by
> > > > that just in case the bpp ever changes from 8. Overall, I think our
> > > > patches basically do the same thing.
> > >
> > > The calculations in your and my patch are quite different. I'm not
> > > taking into account the number of lanes or the MIPI format. I'm basing
I was taking the number of lanes into account in order to calculate
the clock rate, since 4-lanes can run slower.
> >
> > I was looking more at the division by 8 and the overhead correction of 6.
> > This number 6 also appears in the NXP downstream kernel [1]. I know
> > Marek V had some concerns about that.
> >
> Yea, I don't fully remember the details about the overhead. Need to
> page that back in. The division by 8 in my patch is just to get from
> the bit to a byte clock, nothing to do with the MIPI format bits per
> channel or something like that.
>
> > > the blanking size purely on the ratio between MIPI DSI byte clock and
> > > the DPI interface clock. It's quite counter-intuitive that the host
> > > would scale the blanking to the number of lanes automatically, but
> > > still require the MIPI packet offset removed, but that's what my
> > > measurements showed to produce the correct blanking after translation
> > > to DPI by the TC358767 bridge chip.
> >
> > How many lanes is your DSI interface using?
> >
> When I did the measurements to come up with the patch, I varied the
> number of lanes between 1 and 4. Different number of lanes didn't make
> a difference. In fact trying to compensate for the number of lanes when
> calculating the blanking size to program into the controller lead to
> wildly wrong blanking on the DPI side of the external bridge.
>
> > >
> > > If you dynamically scale the HS clock, then you would need to input the
> > > real used HS clock to the calculation in my patch, instead of the fixed
> > > burst mode rate.
> >
> > I think what you're saying makes sense.
> >
> > The code I originally modeled this from was from the NXP downstream
> > kernel where they define the calculation as being in words [2]. I am
> > not saying the NXP code is perfect, but the NXP code works. With this
> > series, my monitors are able to sync a bunch of different resolutions
> > from 1080p down to 640x480 and a bunch in between with various refresh
> > rates too. That was the goal of this series.
> >
> > Instead of just using your patch as-is, I will adapt yours to use the
> > scaled clock to see how it behaves and get back to you.
> >
>
> Thanks, that would be very much appreciated.
Lucas,
I took your patch and added a dsi state variable named "hs_clock" to
keep track of the output of samsung_dsim_set_pll which should be the
active high-speed clock.
I then replaced one line in your code to reference the hs_clock
instead of the burst clock:
@@ -960,7 +962,7 @@ static void samsung_dsim_set_display_mode(struct
samsung_dsim *dsi)
u32 reg;
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
- int byte_clk_khz = dsi->burst_clk_rate / 1000 / 8;
+ int byte_clk_khz = dsi->hs_clock / 1000 / 8;
int hfp = (m->hsync_start - m->hdisplay) *
byte_clk_khz / m->clock;
With that change, your patch works with the rest of my code, and I
think it's easier to read, and it doesn't involve recalculating the
clock speed each time since it's cached. If you're OK with that, I'll
incorporate your code into V2 of my series, and I'll apply my changes
as a subsequent patch. I hope to be able to send out V2 this weekend.
I would be curious to know frm Marek Szyprowski what the impact is on
the Samsung devices, if any.
adam
>
> I also don't assert that my calculation is perfect, as I also don't
> have any more information and needed to resort to observing the
> blanking after translation by the external bridge, so I hope we could
> get some better understanding of how things really work by checking
> what works for both our systems.
>
> > I have
> > finished reworking the dynamic DPHY settings, and I've fixed up making
> > the PLL device tree optional. If your patch works, I'll drop my
> > calculation and just build off what you have to use the scaled HS
> > clock when I submit the V2 and I'll make sure I CC you.
> >
> Thanks, I'm open to re-do my measurements with your new patches.
>
> Regards,
> Lucas
>
> > adam
> >
> > [1] - https://github.com/nxp-imx/linux-imx/blob/lf-6.1.y/drivers/gpu/drm/bridge/sec-dsim.c#L270
> > [2] - https://github.com/nxp-imx/linux-imx/blob/lf-6.1.y/drivers/gpu/drm/bridge/sec-dsim.c#L914
> >
> > >
> > > Regards,
> > > Lucas
>
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