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* Re: [RFC v1 1/2] scmi: Introduce pinctrl SCMI protocol driver
From: Cristian Marussi @ 2023-04-20 17:05 UTC (permalink / raw)
  To: Oleksii Moisieiev
  Cc: sudeep.holla@arm.com, Linus Walleij, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org,
	michal.simek, vincent.guittot, souvik.chakravarty
In-Reply-To: <ZDcqx9JVMvqr2WYu@e120937-lin>

On Wed, Apr 12, 2023 at 11:04:05PM +0100, Cristian Marussi wrote:
> On Fri, Apr 07, 2023 at 10:18:27AM +0000, Oleksii Moisieiev wrote:
> > Implementation of the SCMI client driver, which implements
> > PINCTRL_PROTOCOL. This protocol has ID 19 and is described
> > in the latest DEN0056 document.
> 
> Hi,
> 

Hi Oleksii,

one more thing that I missed in my previous review down below.

> > This protocol is part of the feature that was designed to
> > separate the pinctrl subsystem from the SCP firmware.
> > The idea is to separate communication of the pin control
> > subsystem with the hardware to SCP firmware
> > (or a similar system, such as ATF), which provides an interface
> > to give the OS ability to control the hardware through SCMI protocol.
> > This is a generic driver that implements SCMI protocol,
> > independent of the platform type.
> > 
> > DEN0056 document:
> > https://developer.arm.com/documentation/den0056/latest
> > 
> 

[snip]

> > +static int scmi_pinctrl_request_config(const struct scmi_handle *handle,
> > +				       u32 selector,
> > +				       enum scmi_pinctrl_selector_type type,
> > +				       u32 *config)
> > +{
> > +	struct scmi_xfer *t;
> > +	struct scmi_conf_tx *tx;
> > +	__le32 *packed_config;
> > +	u32 attributes = 0;
> > +	int ret;
> > +
> > +	if (!handle || !config || type == FUNCTION_TYPE)
> > +		return -EINVAL;
> > +
> > +	ret = scmi_pinctrl_validate_id(handle, selector, type);
> > +	if (ret)
> > +		return ret;
> > +
> > +	ret = scmi_xfer_get_init(handle, PINCTRL_CONFIG_GET,
> > +				 SCMI_PROTOCOL_PINCTRL,
> > +				 sizeof(*tx), sizeof(*packed_config), &t);
> > +	if (ret)
> > +		return ret;
> > +
> > +	tx = t->tx.buf;
> > +	packed_config = t->rx.buf;
> > +	tx->identifier = cpu_to_le32(selector);
> > +	attributes = SET_TYPE_BITS(attributes, type);
> > +	attributes = SET_CONFIG(attributes, *config);
> > +

Looking at scmi_conf_tx and these pinctrl get/set functions, you do not
seem to consider the ConfigType field in the SCMI related messages, so
basically using always the Default 0 Type, and as a consequence you dont
either expose any way to choose a Different type in the related SCMI
protocol ops; I imagine this is because the pinctrl driver currently using
this protocol, at the end, does not need any of the other available types
(as in Table 23 of the spec).

This is fine for pinctrl driver as it is now, BUT the SCMI pinctrl
protocol implementation in the core SCMI stack and its related
protocol_operations as exposed in scmi_protocol.h should be generic
enough to serve any possible user of the SCMI pinctrl protocol (and there
is already a request to extend/amend the spec somehow to send multiple pin
setup of different types in one go as you may have seen), so I'd say it's
better if you add also a ConfigType param to the get/set_config scmi_pinctrl_ops
and expose the whole ConfigType enums (Table23) in scmi_protocol.h (like we do for
sensor classes on scmi_protocol.h) to address this; the pinctrl driver
can then anyway call such new protocol_ops with a Default type, but at
least the SCMI protocol_ops interface will remain generic and could be
reused iin other scenarios.

This is equally true for all the other protocol messages (should I have
miss something else for now...I'll review again you next V2 anyway).

Thanks,
Cristian


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* Re: [PATCH] arm64: kexec: include reboot.h
From: Will Deacon @ 2023-04-20 17:04 UTC (permalink / raw)
  To: Catalin Marinas, Simon Horman
  Cc: kernel-team, Will Deacon, linux-kernel, Baoquan He,
	linux-arm-kernel, kexec, Leizhen (ThunderTown)
In-Reply-To: <20230418-arm64-kexec-include-reboot-v1-1-8453fd4fb3fb@kernel.org>

On Tue, 18 Apr 2023 13:54:00 +0200, Simon Horman wrote:
> Include reboot.h in machine_kexec.c for declaration of
> machine_crash_shutdown.
> 
> gcc-12 with W=1 reports:
> 
>  arch/arm64/kernel/machine_kexec.c:257:6: warning: no previous prototype for 'machine_crash_shutdown' [-Wmissing-prototypes]
>    257 | void machine_crash_shutdown(struct pt_regs *regs)
> 
> [...]

Applied to arm64 (for-next/misc), thanks!

[1/1] arm64: kexec: include reboot.h
      https://git.kernel.org/arm64/c/b7b4ce84c830

Cheers,
-- 
Will

https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev

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* Re: [PATCH] KVM: arm64: Ensure CPU PMU probes before pKVM host de-privilege
From: Will Deacon @ 2023-04-20 17:04 UTC (permalink / raw)
  To: linux-arm-kernel, Will Deacon
  Cc: catalin.marinas, kernel-team, kvmarm, Marc Zyngier, Fuad Tabba,
	Oliver Upton
In-Reply-To: <20230420123356.2708-1-will@kernel.org>

On Thu, 20 Apr 2023 13:33:56 +0100, Will Deacon wrote:
> Although pKVM supports CPU PMU emulation for non-protected guests since
> 722625c6f4c5 ("KVM: arm64: Reenable pmu in Protected Mode"), this relies
> on the PMU driver probing before the host has de-privileged so that the
> 'kvm_arm_pmu_available' static key can still be enabled by patching the
> hypervisor text.
> 
> As it happens, both of these events hang off device_initcall() but the
> PMU consistently won the race until 7755cec63ade ("arm64: perf: Move
> PMUv3 driver to drivers/perf"). Since then, the host will fail to boot
> when pKVM is enabled:
> 
> [...]

Applied to will (for-next/perf), thanks!

[1/1] KVM: arm64: Ensure CPU PMU probes before pKVM host de-privilege
      https://git.kernel.org/will/c/87727ba2bb05

Cheers,
-- 
Will

https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev

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* Re: [PATCH] arm64: delete dead code in this_cpu_set_vectors()
From: Will Deacon @ 2023-04-20 17:04 UTC (permalink / raw)
  To: Dan Carpenter, James Morse
  Cc: catalin.marinas, kernel-team, Will Deacon, Kristina Martsenko,
	Ard Biesheuvel, Liu Song, Mark Rutland, linux-kernel,
	kernel-janitors, D Scott Phillips, Mark Brown, linux-arm-kernel
In-Reply-To: <73859c9e-dea0-4764-bf01-7ae694fa2e37@kili.mountain>

On Wed, 19 Apr 2023 10:58:43 +0300, Dan Carpenter wrote:
> The "slot" variable is an enum, and in this context it is an unsigned
> int.  So the type means it can never be negative and also we never pass
> invalid data to this function.  If something did pass invalid data then
> this check would be insufficient protection.
> 
> 

Applied to arm64 (for-next/misc), thanks!

[1/1] arm64: delete dead code in this_cpu_set_vectors()
      https://git.kernel.org/arm64/c/460e70e2dc9a

Cheers,
-- 
Will

https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev

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* Re: [PATCH] arm64: errata: Add NXP iMX8QM workaround for A53 Cache coherency issue
From: Robin Murphy @ 2023-04-20 17:02 UTC (permalink / raw)
  To: Ivan T. Ivanov, Mark Rutland
  Cc: Catalin Marinas, Will Deacon, Mark Brown, Shawn Guo, Dong Aisheng,
	linux-arm-kernel, linux-imx
In-Reply-To: <rbzinid5ogfwd6mzgx3qey3xy4haok5jx3ghyvzzmteki2kxnn@224msirsgukg>

On 18/04/2023 5:54 pm, Ivan T. Ivanov wrote:
> On 04-17 16:35, Mark Rutland wrote:
> 
>>>>> @@ -835,7 +835,8 @@ static inline bool system_supports_bti(void)
>>>>>    static inline bool system_supports_tlb_range(void)
>>>>>    {
>>>>>    	return IS_ENABLED(CONFIG_ARM64_TLB_RANGE) &&
>>>>> -		cpus_have_const_cap(ARM64_HAS_TLB_RANGE);
>>>>> +		cpus_have_const_cap(ARM64_HAS_TLB_RANGE) &&
>>>>> +		!cpus_have_const_cap(ARM64_WORKAROUND_NXP_ERR050104);
>>>>>    }
>>>>
>>>> It'd be better to handle this in the detection of ARM64_HAS_TLB_RANGE, as we
>>>> have for CNP where has_useable_cnp() checks for ARM64_WORKAROUND_NVIDIA_CARMEL_CNP.
>>>
>>> It's not needed in either place, since neither Cortex-A53 or Cortex-A72
>>> support FEAT_TLBIRANGE, so this could never be true on affected platforms
>>> anyway.
>>
>> Ah, even better -- we can just drop it.
> 
> Ok.
> 
>>
>>> Tangentially, I understand this platform has an SMMU[1], so I'd say it would
>>> also be worth checking what SMMU_IDR0.BTM reports. With any luck it might be
>>> 0, but if it's 1 then strictly it would want to be overridden as part of a
>>> complete workaround as well. That wouldn't be a practical issue right now,
>>> not least since the current Linux driver doesn't even use BTM, but it's
>>> something which could need to be borne in mind in future.
>>
>> Absolutely.
> 
> I don't completely understand implication of this, but for SMMU inside
> iMX8QM report that "Broadcast TLB maintenance is supported"

Aha, in fact it seems we might be OK. I double-checked and it turns out 
that thanks to an MMU-500 erratum, we can't necessarily believe IDR0.BTM 
anyway. Thus anyone who adds DVM support to an SMMUv2 driver is going to 
need to implement some new firmware property or platform detection, at 
which point the chances of it getting silently enabled for i.MX8 (if 
indeed BTM isn't already a lie there) seem sufficiently remote that I'd 
feel fairly comfortable not doing anything explicit for now.

(The case of concern wouldn't be so much the expected use of DVM to 
share CPU pagetables with the SMMU, which in principle the regular CPU 
workaround should already cover, but more anyone trying to play clever 
tricks using DVM and CPU instructions to maintain private SMMU contexts 
rather than register-based commands.)

Thanks,
Robin.

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* Re: [patch 00/37] cpu/hotplug, x86: Reworked parallel CPU bringup
From: Paul Menzel @ 2023-04-20 16:47 UTC (permalink / raw)
  To: Thomas Gleixner
  Cc: Sean Christopherson, Andrew Cooper, linux-kernel, x86,
	David Woodhouse, Brian Gerst, Arjan van de Veen, Paolo Bonzini,
	Paul McKenney, Tom Lendacky, Oleksandr Natalenko,
	Guilherme G. Piccoli, Piotr Gorski, David Woodhouse, Usama Arif,
	Jürgen Groß, Boris Ostrovsky, xen-devel, Russell King,
	Arnd Bergmann, linux-arm-kernel, Catalin Marinas, Will Deacon,
	Guo Ren, linux-csky, Thomas Bogendoerfer, linux-mips,
	James E. J. Bottomley, Helge Deller, linux-parisc, Paul Walmsley,
	Palmer Dabbelt, linux-riscv, Mark Rutland, Sabin Rapan
In-Reply-To: <87v8hq35sk.ffs@tglx>

Dear Thomas,


Am 20.04.23 um 17:57 schrieb Thomas Gleixner:
> On Thu, Apr 20 2023 at 07:51, Sean Christopherson wrote:
>> On Thu, Apr 20, 2023, Thomas Gleixner wrote:
>>> On Thu, Apr 20 2023 at 10:23, Andrew Cooper wrote:
>>>> On 20/04/2023 9:32 am, Thomas Gleixner wrote:
>>>>> On Wed, Apr 19, 2023, Andrew Cooper wrote:
>>>>>> This was changed in x2APIC, which made the x2APIC_ID immutable.
>>>
>>>>> I'm pondering to simply deny parallel mode if x2APIC is not there.
>>>>
>>>> I'm not sure if that will help much.
>>>
>>> Spoilsport.
>>
>> LOL, well let me pile on then.  x2APIC IDs aren't immutable on AMD hardware.  The
>> ID is read-only when the CPU is in x2APIC mode, but any changes made to the ID
>> while the CPU is in xAPIC mode survive the transition to x2APIC.  From the APM:
>>
>>    A value previously written by software to the 8-bit APIC_ID register (MMIO offset
>>    30h) is converted by hardware into the appropriate format and reflected into the
>>    32-bit x2APIC_ID register (MSR 802h).
>>
>> FWIW, my observations from testing on bare metal are that the xAPIC ID is effectively
>> read-only (writes are dropped) on Intel CPUs as far back as Haswell, while the above
>> behavior described in the APM holds true on at least Rome and Milan.
>>
>> My guess is that Intel's uArch specific behavior of the xAPIC ID being read-only
>> was introduced when x2APIC came along, but I didn't test farther back than Haswell.
> 
> I'm not so worried about modern hardware. The horrorshow is the old muck
> as demonstrated and of course there is virt :)
> 
> Something like the completely untested below should just work whatever
> APIC ID the BIOS decided to dice.
> 
> That might just work on SEV too without that GHCB muck, but what do I
> know.
> 
> Thanks,
> 
>          tglx
> ---
> --- a/arch/x86/include/asm/apicdef.h
> +++ b/arch/x86/include/asm/apicdef.h
> @@ -138,7 +138,8 @@
>   #define		APIC_EILVT_MASKED	(1 << 16)
>   
>   #define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
> -#define APIC_BASE_MSR	0x800
> +#define APIC_BASE_MSR		0x800
> +#define APIC_X2APIC_ID_MSR	0x802
>   #define XAPIC_ENABLE	(1UL << 11)
>   #define X2APIC_ENABLE	(1UL << 10)
>   
> @@ -162,6 +163,7 @@
>   #define APIC_CPUID(apicid)	((apicid) & XAPIC_DEST_CPUS_MASK)
>   #define NUM_APIC_CLUSTERS	((BAD_APICID + 1) >> XAPIC_DEST_CPUS_SHIFT)
>   
> +#ifndef __ASSEMBLY__
>   /*
>    * the local APIC register structure, memory mapped. Not terribly well
>    * tested, but we might eventually use this one in the future - the
> @@ -435,4 +437,5 @@ enum apic_delivery_modes {
>   	APIC_DELIVERY_MODE_EXTINT	= 7,
>   };
>   
> +#endif /* !__ASSEMBLY__ */
>   #endif /* _ASM_X86_APICDEF_H */
> --- a/arch/x86/include/asm/smp.h
> +++ b/arch/x86/include/asm/smp.h
> @@ -195,14 +195,13 @@ extern void nmi_selftest(void);
>   #endif
>   
>   extern unsigned int smpboot_control;
> +extern unsigned long apic_mmio_base;
>   
>   #endif /* !__ASSEMBLY__ */
>   
>   /* Control bits for startup_64 */
> -#define STARTUP_APICID_CPUID_1F 0x80000000
> -#define STARTUP_APICID_CPUID_0B 0x40000000
> -#define STARTUP_APICID_CPUID_01 0x20000000
> -#define STARTUP_APICID_SEV_ES	0x10000000
> +#define STARTUP_READ_APICID	0x80000000
> +#define STARTUP_APICID_SEV_ES	0x40000000
>   
>   /* Top 8 bits are reserved for control */
>   #define STARTUP_PARALLEL_MASK	0xFF000000
> --- a/arch/x86/kernel/apic/apic.c
> +++ b/arch/x86/kernel/apic/apic.c
> @@ -101,6 +101,8 @@ static int apic_extnmi __ro_after_init =
>    */
>   static bool virt_ext_dest_id __ro_after_init;
>   
> +unsigned long apic_mmio_base __ro_after_init;
> +
>   /*
>    * Map cpu index to physical APIC ID
>    */
> @@ -2164,6 +2166,7 @@ void __init register_lapic_address(unsig
>   
>   	if (!x2apic_mode) {
>   		set_fixmap_nocache(FIX_APIC_BASE, address);
> +		apic_mmio_base = APIC_BASE;
>   		apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
>   			    APIC_BASE, address);
>   	}
> --- a/arch/x86/kernel/head_64.S
> +++ b/arch/x86/kernel/head_64.S
> @@ -24,8 +24,10 @@
>   #include "../entry/calling.h"
>   #include <asm/export.h>
>   #include <asm/nospec-branch.h>
> +#include <asm/apicdef.h>
>   #include <asm/fixmap.h>
>   #include <asm/smp.h>
> +
>   #include <asm/sev-common.h>
>   
>   /*
> @@ -237,37 +239,24 @@ SYM_INNER_LABEL(secondary_startup_64_no_
>   
>   #ifdef CONFIG_SMP
>   	/*
> -	 * For parallel boot, the APIC ID is retrieved from CPUID, and then
> -	 * used to look up the CPU number.  For booting a single CPU, the
> -	 * CPU number is encoded in smpboot_control.
> +	 * For parallel boot, the APIC ID is either retrieved the APIC or
> +	 * from CPUID, and then used to look up the CPU number.
> +	 * For booting a single CPU, the CPU number is encoded in
> +	 * smpboot_control.
>   	 *
> -	 * Bit 31	STARTUP_APICID_CPUID_1F flag (use CPUID 0x1f)
> -	 * Bit 30	STARTUP_APICID_CPUID_0B flag (use CPUID 0x0b)
> -	 * Bit 29	STARTUP_APICID_CPUID_01 flag (use CPUID 0x01)
> -	 * Bit 28	STARTUP_APICID_SEV_ES flag (CPUID 0x0b via GHCB MSR)
> +	 * Bit 31	STARTUP_APICID_READ (Read APICID from APIC)
> +	 * Bit 30	STARTUP_APICID_SEV_ES flag (CPUID 0x0b via GHCB MSR)
>   	 * Bit 0-23	CPU# if STARTUP_APICID_CPUID_xx flags are not set
>   	 */
>   	movl	smpboot_control(%rip), %ecx
> +	testl	$STARTUP_READ_APICID, %ecx
>   #ifdef CONFIG_AMD_MEM_ENCRYPT
>   	testl	$STARTUP_APICID_SEV_ES, %ecx
>   	jnz	.Luse_sev_cpuid_0b
>   #endif
> -	testl	$STARTUP_APICID_CPUID_1F, %ecx
> -	jnz	.Luse_cpuid_1f
> -	testl	$STARTUP_APICID_CPUID_0B, %ecx
> -	jnz	.Luse_cpuid_0b
> -	testl	$STARTUP_APICID_CPUID_01, %ecx
> -	jnz	.Luse_cpuid_01
>   	andl	$(~STARTUP_PARALLEL_MASK), %ecx
>   	jmp	.Lsetup_cpu
>   
> -.Luse_cpuid_01:
> -	mov	$0x01, %eax
> -	cpuid
> -	mov	%ebx, %edx
> -	shr	$24, %edx
> -	jmp	.Lsetup_AP
> -
>   #ifdef CONFIG_AMD_MEM_ENCRYPT
>   .Luse_sev_cpuid_0b:
>   	/* Set the GHCB MSR to request CPUID 0x0B_EDX */
> @@ -292,24 +281,30 @@ SYM_INNER_LABEL(secondary_startup_64_no_
>   	jmp	.Lsetup_AP
>   #endif
>   
> -.Luse_cpuid_0b:
> -	mov	$0x0B, %eax
> -	xorl	%ecx, %ecx
> -	cpuid
> -	jmp	.Lsetup_AP
> +.Lread_apicid:
> +	mov	$MSR_IA32_APICBASE, %ecx
> +	rdmsr
> +	testl	$X2APIC_ENABLE, %eax
> +	jnz	read_apicid_msr
> +
> +	/* Read the APIC ID from the fix-mapped MMIO space. */
> +	movq	apic_mmio_base(%rip), %rcx
> +	addq	$APIC_ID, %rcx
> +	movl	(%rcx), %eax
> +	shr	$24, %eax
> +	jnz	.Lread_apicid
>   
> -.Luse_cpuid_1f:
> -	mov	$0x1f, %eax
> -	xorl	%ecx, %ecx
> -	cpuid
> +.Lread_apicid_msr:
> +	mov	$APIC_X2APIC_ID_MSR, %ecx
> +	rdmsr
>   
>   .Lsetup_AP:
> -	/* EDX contains the APIC ID of the current CPU */
> +	/* EAX contains the APIC ID of the current CPU */
>   	xorq	%rcx, %rcx
>   	leaq	cpuid_to_apicid(%rip), %rbx
>   
>   .Lfind_cpunr:
> -	cmpl	(%rbx,%rcx,4), %edx
> +	cmpl	(%rbx,%rcx,4), %eax
>   	jz	.Lsetup_cpu
>   	inc	%ecx
>   #ifdef CONFIG_FORCE_NR_CPUS
> --- a/arch/x86/kernel/smpboot.c
> +++ b/arch/x86/kernel/smpboot.c
> @@ -1253,41 +1253,22 @@ bool __init arch_cpuhp_init_parallel_bri
>   		return false;
>   	}
>   
> -	/* Encrypted guests require special CPUID handling. */
> +	/* Encrypted guests require special handling. */
>   	if (cc_platform_has(CC_ATTR_GUEST_STATE_ENCRYPT)) {
>   		switch (cc_get_vendor()) {
>   		case CC_VENDOR_AMD:
>   			ctrl = STARTUP_APICID_SEV_ES;
>   			if (topology_extended_leaf == 0x0b)
> -				goto setup;
> +				break;
>   			fallthrough;
>   		default:
>   			pr_info("Parallel CPU startup disabled due to guest state encryption\n");
>   			return false;
>   		}
> +	} else {
> +		ctrl = STARTUP_READ_APICID;
>   	}
>   
> -	switch (topology_extended_leaf) {
> -	case 0x0b:
> -		ctrl = STARTUP_APICID_CPUID_0B;
> -		break;
> -	case 0x1f:
> -		ctrl = STARTUP_APICID_CPUID_1F;
> -		break;
> -	case 0x00:
> -		/* For !x2APIC mode 8 bits from leaf 0x01 are sufficient. */
> -		if (!x2apic_mode) {
> -			ctrl = STARTUP_APICID_CPUID_01;
> -			break;
> -		}
> -		fallthrough;
> -	default:
> -		pr_info("Parallel CPU startup disabled. Unsupported topology leaf %u\n",
> -			topology_extended_leaf);
> -		return false;
> -	}
> -
> -setup:
>   	pr_debug("Parallel CPU startup enabled: 0x%08x\n", ctrl);
>   	smpboot_control = ctrl;
>   	return true;

I quickly applied it on top of your branch, but I am getting:

```
$ wget https://lore.kernel.org/lkml/87v8hq35sk.ffs@tglx/raw
$ patch -p1 < raw
$ make
[…]
   LD      .tmp_vmlinux.kallsyms1
ld: arch/x86/kernel/head_64.o: in function `secondary_startup_64_no_verify':
(.head.text+0xbf): undefined reference to `read_apicid_msr'
make[1]: *** [scripts/Makefile.vmlinux:35: vmlinux] Error 1
make: *** [Makefile:1249: vmlinux] Error 2
```


Kind regards,

Paul

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* [PATCH v2 2/2] net: ethernet: mtk_eth_soc: use WO firmware for MT7981
From: Daniel Golle @ 2023-04-20 16:05 UTC (permalink / raw)
  To: devicetree, netdev, linux-mediatek, linux-arm-kernel,
	linux-kernel, Rob Herring, Krzysztof Kozlowski, Felix Fietkau,
	John Crispin, Sean Wang, Mark Lee, Lorenzo Bianconi,
	David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
	Matthias Brugger, AngeloGioacchino Del Regno
In-Reply-To: <cover.1681994362.git.daniel@makrotopia.org>

In order to support wireless offloading on MT7981 we need to load the
appropriate firmware. Recognize MT7981 and load mt7981_wo.bin.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
No changes since v1.

 drivers/net/ethernet/mediatek/mtk_wed_mcu.c | 7 ++++++-
 drivers/net/ethernet/mediatek/mtk_wed_wo.h  | 1 +
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
index 6bad0d262f286..071ed3dea860d 100644
--- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
+++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
@@ -326,7 +326,11 @@ mtk_wed_mcu_load_firmware(struct mtk_wed_wo *wo)
 		wo->hw->index + 1);
 
 	/* load firmware */
-	fw_name = wo->hw->index ? MT7986_FIRMWARE_WO1 : MT7986_FIRMWARE_WO0;
+	if (of_device_is_compatible(wo->hw->node, "mediatek,mt7981-wed"))
+		fw_name = MT7981_FIRMWARE_WO;
+	else
+		fw_name = wo->hw->index ? MT7986_FIRMWARE_WO1 : MT7986_FIRMWARE_WO0;
+
 	ret = request_firmware(&fw, fw_name, wo->hw->dev);
 	if (ret)
 		return ret;
@@ -386,5 +390,6 @@ int mtk_wed_mcu_init(struct mtk_wed_wo *wo)
 				  100, MTK_FW_DL_TIMEOUT);
 }
 
+MODULE_FIRMWARE(MT7981_FIRMWARE_WO);
 MODULE_FIRMWARE(MT7986_FIRMWARE_WO0);
 MODULE_FIRMWARE(MT7986_FIRMWARE_WO1);
diff --git a/drivers/net/ethernet/mediatek/mtk_wed_wo.h b/drivers/net/ethernet/mediatek/mtk_wed_wo.h
index dbcf42ce9173c..7a1a2a28f1acb 100644
--- a/drivers/net/ethernet/mediatek/mtk_wed_wo.h
+++ b/drivers/net/ethernet/mediatek/mtk_wed_wo.h
@@ -88,6 +88,7 @@ enum mtk_wed_dummy_cr_idx {
 	MTK_WED_DUMMY_CR_WO_STATUS,
 };
 
+#define MT7981_FIRMWARE_WO	"mediatek/mt7981_wo.bin"
 #define MT7986_FIRMWARE_WO0	"mediatek/mt7986_wo_0.bin"
 #define MT7986_FIRMWARE_WO1	"mediatek/mt7986_wo_1.bin"
 
-- 
2.40.0


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* [PATCH v2 1/2] dt-bindings: net: mediatek: add WED RX binding for MT7981 eth driver
From: Daniel Golle @ 2023-04-20 16:04 UTC (permalink / raw)
  To: devicetree, netdev, linux-mediatek, linux-arm-kernel,
	linux-kernel, Rob Herring, Krzysztof Kozlowski, Felix Fietkau,
	John Crispin, Sean Wang, Mark Lee, Lorenzo Bianconi,
	David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
	Matthias Brugger, AngeloGioacchino Del Regno
In-Reply-To: <cover.1681994362.git.daniel@makrotopia.org>

Add compatible string for mediatek,mt7981-wed as MT7981 also supports
RX WED just like MT7986, but needs a different firmware file.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
Changes since v1:
 * maintain alphabetic order

 .../devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml    | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml
index 5c223cb063d48..f7d578a171a4f 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mt7622-wed.yaml
@@ -20,6 +20,7 @@ properties:
     items:
       - enum:
           - mediatek,mt7622-wed
+          - mediatek,mt7981-wed
           - mediatek,mt7986-wed
       - const: syscon
 
-- 
2.40.0


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* [PATCH v2 0/2] net: ethernet: mtk_eth_soc: use WO firmware for MT7981
From: Daniel Golle @ 2023-04-20 16:04 UTC (permalink / raw)
  To: devicetree, netdev, linux-mediatek, linux-arm-kernel,
	linux-kernel, Rob Herring, Krzysztof Kozlowski, Felix Fietkau,
	John Crispin, Sean Wang, Mark Lee, Lorenzo Bianconi,
	David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
	Matthias Brugger, AngeloGioacchino Del Regno

In order to support wireless offloading on MT7981 we need to load the
appropriate firmware. Recognize MT7981 by introducing a new DT compatible
and load mt7981_wo.bin if it is set.

Changes since v1:
 * retain alphabetic order in dt-bindings

Daniel Golle (2):
  dt-bindings: net: mediatek: add WED RX binding for MT7981 eth driver
  net: ethernet: mtk_eth_soc: use WO firmware for MT7981

 .../bindings/arm/mediatek/mediatek,mt7622-wed.yaml         | 1 +
 drivers/net/ethernet/mediatek/mtk_wed_mcu.c                | 7 ++++++-
 drivers/net/ethernet/mediatek/mtk_wed_wo.h                 | 1 +
 3 files changed, 8 insertions(+), 1 deletion(-)

-- 
2.40.0


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* Re: [PATCH 1/3] dt-bindings: nvmem: brcm,nvram: add #nvmem-cell-cells for MACs
From: Rob Herring @ 2023-04-20 16:01 UTC (permalink / raw)
  To: Rafał Miłecki
  Cc: Krzysztof Kozlowski, Srinivas Kandagatla, Florian Fainelli,
	Hauke Mehrtens, devicetree, linux-arm-kernel,
	bcm-kernel-feedback-list, linux-kernel, Rafał Miłecki
In-Reply-To: <20230406110804.12024-1-zajec5@gmail.com>

On Thu, Apr 06, 2023 at 01:08:02PM +0200, Rafał Miłecki wrote:
> From: Rafał Miłecki <rafal@milecki.pl>
> 
> Broadcom's NVRAM contains MACs for Ethernet interfaces. Those MACs are
> usually base addresses that are also used for calculating other MACs.
> 
> For example if a router vendor decided to use gmac0 it most likely
> programmed NVRAM of each unit with a proper "et0macaddr" value. That is
> a base.
> 
> Ethernet interface is usually connected to switch port. Switch usually
> includes few LAN ports and a WAN port. MAC of WAN port gets calculated
> as relative address to the interface one. Offset varies depending on
> device model.
> 
> Wireless MACs may also need to be calculated using relevant offsets.
> 
> To support all those scenarios let MAC NVMEM cells be referenced with an
> index specifying MAC offset.
> 
> Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
> ---
>  .../devicetree/bindings/nvmem/brcm,nvram.yaml        | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/nvmem/brcm,nvram.yaml b/Documentation/devicetree/bindings/nvmem/brcm,nvram.yaml
> index 36def7128fca..a921e05cc544 100644
> --- a/Documentation/devicetree/bindings/nvmem/brcm,nvram.yaml
> +++ b/Documentation/devicetree/bindings/nvmem/brcm,nvram.yaml
> @@ -36,14 +36,26 @@ properties:
>    et0macaddr:
>      type: object
>      description: First Ethernet interface's MAC address
> +    properties:
> +      "#nvmem-cell-cells":
> +        description: The first argument is a MAC address offset.
> +        const: 1

Not a new issue, but these nodes are missing 'additionalProperties: 
false'. Can you add that. With that,

Reviewed-by: Rob Herring <robh@kernel.org>


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* Re: [patch 00/37] cpu/hotplug, x86: Reworked parallel CPU bringup
From: Thomas Gleixner @ 2023-04-20 15:57 UTC (permalink / raw)
  To: Sean Christopherson
  Cc: Andrew Cooper, Paul Menzel, linux-kernel, x86, David Woodhouse,
	Brian Gerst, Arjan van de Veen, Paolo Bonzini, Paul McKenney,
	Tom Lendacky, Oleksandr Natalenko, Guilherme G. Piccoli,
	Piotr Gorski, David Woodhouse, Usama Arif, Jürgen Groß,
	Boris Ostrovsky, xen-devel, Russell King, Arnd Bergmann,
	linux-arm-kernel, Catalin Marinas, Will Deacon, Guo Ren,
	linux-csky, Thomas Bogendoerfer, linux-mips,
	James E. J. Bottomley, Helge Deller, linux-parisc, Paul Walmsley,
	Palmer Dabbelt, linux-riscv, Mark Rutland, Sabin Rapan
In-Reply-To: <ZEFRhXua6Jxvit1R@google.com>

On Thu, Apr 20 2023 at 07:51, Sean Christopherson wrote:
> On Thu, Apr 20, 2023, Thomas Gleixner wrote:
>> On Thu, Apr 20 2023 at 10:23, Andrew Cooper wrote:
>> > On 20/04/2023 9:32 am, Thomas Gleixner wrote:
>> > > On Wed, Apr 19, 2023, Andrew Cooper wrote:
>> > > > This was changed in x2APIC, which made the x2APIC_ID immutable.
>>
>> >> I'm pondering to simply deny parallel mode if x2APIC is not there.
>> >
>> > I'm not sure if that will help much.
>> 
>> Spoilsport.
>
> LOL, well let me pile on then.  x2APIC IDs aren't immutable on AMD hardware.  The
> ID is read-only when the CPU is in x2APIC mode, but any changes made to the ID
> while the CPU is in xAPIC mode survive the transition to x2APIC.  From the APM:
>
>   A value previously written by software to the 8-bit APIC_ID register (MMIO offset
>   30h) is converted by hardware into the appropriate format and reflected into the
>   32-bit x2APIC_ID register (MSR 802h).
>
> FWIW, my observations from testing on bare metal are that the xAPIC ID is effectively
> read-only (writes are dropped) on Intel CPUs as far back as Haswell, while the above
> behavior described in the APM holds true on at least Rome and Milan.
>
> My guess is that Intel's uArch specific behavior of the xAPIC ID being read-only
> was introduced when x2APIC came along, but I didn't test farther back than Haswell.

I'm not so worried about modern hardware. The horrorshow is the old muck
as demonstrated and of course there is virt :)

Something like the completely untested below should just work whatever
APIC ID the BIOS decided to dice.

That might just work on SEV too without that GHCB muck, but what do I
know.

Thanks,

        tglx
---
--- a/arch/x86/include/asm/apicdef.h
+++ b/arch/x86/include/asm/apicdef.h
@@ -138,7 +138,8 @@
 #define		APIC_EILVT_MASKED	(1 << 16)
 
 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
-#define APIC_BASE_MSR	0x800
+#define APIC_BASE_MSR		0x800
+#define APIC_X2APIC_ID_MSR	0x802
 #define XAPIC_ENABLE	(1UL << 11)
 #define X2APIC_ENABLE	(1UL << 10)
 
@@ -162,6 +163,7 @@
 #define APIC_CPUID(apicid)	((apicid) & XAPIC_DEST_CPUS_MASK)
 #define NUM_APIC_CLUSTERS	((BAD_APICID + 1) >> XAPIC_DEST_CPUS_SHIFT)
 
+#ifndef __ASSEMBLY__
 /*
  * the local APIC register structure, memory mapped. Not terribly well
  * tested, but we might eventually use this one in the future - the
@@ -435,4 +437,5 @@ enum apic_delivery_modes {
 	APIC_DELIVERY_MODE_EXTINT	= 7,
 };
 
+#endif /* !__ASSEMBLY__ */
 #endif /* _ASM_X86_APICDEF_H */
--- a/arch/x86/include/asm/smp.h
+++ b/arch/x86/include/asm/smp.h
@@ -195,14 +195,13 @@ extern void nmi_selftest(void);
 #endif
 
 extern unsigned int smpboot_control;
+extern unsigned long apic_mmio_base;
 
 #endif /* !__ASSEMBLY__ */
 
 /* Control bits for startup_64 */
-#define STARTUP_APICID_CPUID_1F 0x80000000
-#define STARTUP_APICID_CPUID_0B 0x40000000
-#define STARTUP_APICID_CPUID_01 0x20000000
-#define STARTUP_APICID_SEV_ES	0x10000000
+#define STARTUP_READ_APICID	0x80000000
+#define STARTUP_APICID_SEV_ES	0x40000000
 
 /* Top 8 bits are reserved for control */
 #define STARTUP_PARALLEL_MASK	0xFF000000
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -101,6 +101,8 @@ static int apic_extnmi __ro_after_init =
  */
 static bool virt_ext_dest_id __ro_after_init;
 
+unsigned long apic_mmio_base __ro_after_init;
+
 /*
  * Map cpu index to physical APIC ID
  */
@@ -2164,6 +2166,7 @@ void __init register_lapic_address(unsig
 
 	if (!x2apic_mode) {
 		set_fixmap_nocache(FIX_APIC_BASE, address);
+		apic_mmio_base = APIC_BASE;
 		apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
 			    APIC_BASE, address);
 	}
--- a/arch/x86/kernel/head_64.S
+++ b/arch/x86/kernel/head_64.S
@@ -24,8 +24,10 @@
 #include "../entry/calling.h"
 #include <asm/export.h>
 #include <asm/nospec-branch.h>
+#include <asm/apicdef.h>
 #include <asm/fixmap.h>
 #include <asm/smp.h>
+
 #include <asm/sev-common.h>
 
 /*
@@ -237,37 +239,24 @@ SYM_INNER_LABEL(secondary_startup_64_no_
 
 #ifdef CONFIG_SMP
 	/*
-	 * For parallel boot, the APIC ID is retrieved from CPUID, and then
-	 * used to look up the CPU number.  For booting a single CPU, the
-	 * CPU number is encoded in smpboot_control.
+	 * For parallel boot, the APIC ID is either retrieved the APIC or
+	 * from CPUID, and then used to look up the CPU number.
+	 * For booting a single CPU, the CPU number is encoded in
+	 * smpboot_control.
 	 *
-	 * Bit 31	STARTUP_APICID_CPUID_1F flag (use CPUID 0x1f)
-	 * Bit 30	STARTUP_APICID_CPUID_0B flag (use CPUID 0x0b)
-	 * Bit 29	STARTUP_APICID_CPUID_01 flag (use CPUID 0x01)
-	 * Bit 28	STARTUP_APICID_SEV_ES flag (CPUID 0x0b via GHCB MSR)
+	 * Bit 31	STARTUP_APICID_READ (Read APICID from APIC)
+	 * Bit 30	STARTUP_APICID_SEV_ES flag (CPUID 0x0b via GHCB MSR)
 	 * Bit 0-23	CPU# if STARTUP_APICID_CPUID_xx flags are not set
 	 */
 	movl	smpboot_control(%rip), %ecx
+	testl	$STARTUP_READ_APICID, %ecx
 #ifdef CONFIG_AMD_MEM_ENCRYPT
 	testl	$STARTUP_APICID_SEV_ES, %ecx
 	jnz	.Luse_sev_cpuid_0b
 #endif
-	testl	$STARTUP_APICID_CPUID_1F, %ecx
-	jnz	.Luse_cpuid_1f
-	testl	$STARTUP_APICID_CPUID_0B, %ecx
-	jnz	.Luse_cpuid_0b
-	testl	$STARTUP_APICID_CPUID_01, %ecx
-	jnz	.Luse_cpuid_01
 	andl	$(~STARTUP_PARALLEL_MASK), %ecx
 	jmp	.Lsetup_cpu
 
-.Luse_cpuid_01:
-	mov	$0x01, %eax
-	cpuid
-	mov	%ebx, %edx
-	shr	$24, %edx
-	jmp	.Lsetup_AP
-
 #ifdef CONFIG_AMD_MEM_ENCRYPT
 .Luse_sev_cpuid_0b:
 	/* Set the GHCB MSR to request CPUID 0x0B_EDX */
@@ -292,24 +281,30 @@ SYM_INNER_LABEL(secondary_startup_64_no_
 	jmp	.Lsetup_AP
 #endif
 
-.Luse_cpuid_0b:
-	mov	$0x0B, %eax
-	xorl	%ecx, %ecx
-	cpuid
-	jmp	.Lsetup_AP
+.Lread_apicid:
+	mov	$MSR_IA32_APICBASE, %ecx
+	rdmsr
+	testl	$X2APIC_ENABLE, %eax
+	jnz	read_apicid_msr
+
+	/* Read the APIC ID from the fix-mapped MMIO space. */
+	movq	apic_mmio_base(%rip), %rcx
+	addq	$APIC_ID, %rcx
+	movl	(%rcx), %eax
+	shr	$24, %eax
+	jnz	.Lread_apicid
 
-.Luse_cpuid_1f:
-	mov	$0x1f, %eax
-	xorl	%ecx, %ecx
-	cpuid
+.Lread_apicid_msr:
+	mov	$APIC_X2APIC_ID_MSR, %ecx
+	rdmsr
 
 .Lsetup_AP:
-	/* EDX contains the APIC ID of the current CPU */
+	/* EAX contains the APIC ID of the current CPU */
 	xorq	%rcx, %rcx
 	leaq	cpuid_to_apicid(%rip), %rbx
 
 .Lfind_cpunr:
-	cmpl	(%rbx,%rcx,4), %edx
+	cmpl	(%rbx,%rcx,4), %eax
 	jz	.Lsetup_cpu
 	inc	%ecx
 #ifdef CONFIG_FORCE_NR_CPUS
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -1253,41 +1253,22 @@ bool __init arch_cpuhp_init_parallel_bri
 		return false;
 	}
 
-	/* Encrypted guests require special CPUID handling. */
+	/* Encrypted guests require special handling. */
 	if (cc_platform_has(CC_ATTR_GUEST_STATE_ENCRYPT)) {
 		switch (cc_get_vendor()) {
 		case CC_VENDOR_AMD:
 			ctrl = STARTUP_APICID_SEV_ES;
 			if (topology_extended_leaf == 0x0b)
-				goto setup;
+				break;
 			fallthrough;
 		default:
 			pr_info("Parallel CPU startup disabled due to guest state encryption\n");
 			return false;
 		}
+	} else {
+		ctrl = STARTUP_READ_APICID;
 	}
 
-	switch (topology_extended_leaf) {
-	case 0x0b:
-		ctrl = STARTUP_APICID_CPUID_0B;
-		break;
-	case 0x1f:
-		ctrl = STARTUP_APICID_CPUID_1F;
-		break;
-	case 0x00:
-		/* For !x2APIC mode 8 bits from leaf 0x01 are sufficient. */
-		if (!x2apic_mode) {
-			ctrl = STARTUP_APICID_CPUID_01;
-			break;
-		}
-		fallthrough;
-	default:
-		pr_info("Parallel CPU startup disabled. Unsupported topology leaf %u\n",
-			topology_extended_leaf);
-		return false;
-	}
-
-setup:
 	pr_debug("Parallel CPU startup enabled: 0x%08x\n", ctrl);
 	smpboot_control = ctrl;
 	return true;

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* Re: [PATCH v2 1/2] dt-bindings: pwm: mediatek: Add mediatek,mt7981 compatible
From: Krzysztof Kozlowski @ 2023-04-20 15:52 UTC (permalink / raw)
  To: Daniel Golle, devicetree, linux-pwm, linux-mediatek,
	linux-arm-kernel, linux-kernel, Rob Herring, Krzysztof Kozlowski,
	Thierry Reding, Uwe Kleine-König, Matthias Brugger,
	AngeloGioacchino Del Regno, John Crispin
In-Reply-To: <2662c29ec80458852bb8c9041656bca46e2662dd.1681992038.git.daniel@makrotopia.org>

On 20/04/2023 14:35, Daniel Golle wrote:
> Add compatible string for the PWM unit found of the MediaTek MT7981 SoC.
> This is in preparation to adding support in the pwm-mediatek.c driver.
> 
> Signed-off-by: Daniel Golle <daniel@makrotopia.org>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> No changes since v1.


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof


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* Re: [PATCH 1/2] dt-bindings: pwm: mediatek: Add mediatek,mt7981 compatible
From: Krzysztof Kozlowski @ 2023-04-20 15:50 UTC (permalink / raw)
  To: Daniel Golle, devicetree, linux-pwm, linux-mediatek,
	linux-arm-kernel, linux-kernel, Rob Herring, Krzysztof Kozlowski,
	Thierry Reding, Uwe Kleine-König, Matthias Brugger,
	AngeloGioacchino Del Regno, John Crispin
In-Reply-To: <4877689269af862ea9ddd199d8aa96b2d7fcf6fe.1681932165.git.daniel@makrotopia.org>

On 19/04/2023 21:24, Daniel Golle wrote:
> Add compatible string for the PWM unit found of the MediaTek MT7981 SoC.
> This is in preparation to adding support in the pwm-mediatek.c driver.
> 
> Signed-off-by: Daniel Golle <daniel@makrotopia.org>
> ---
>  Documentation/devicetree/bindings/pwm/mediatek,mt2712-pwm.yaml | 1 +
>  1 file changed, 1 insertion(+)


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof


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* Re: [PATCH 2/4] dt-bindings: net: can: Make interrupt attributes optional for MCAN
From: Krzysztof Kozlowski @ 2023-04-20 15:47 UTC (permalink / raw)
  To: Judith Mendez, Chandrasekar Ramakrishnan, Wolfgang Grandegger,
	Marc Kleine-Budde
  Cc: David S . Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
	Schuyler Patton, Nishanth Menon, Vignesh Raghavendra, Tero Kristo,
	Rob Herring, Krzysztof Kozlowski, Oliver Hartkopp,
	linux-arm-kernel, devicetree, linux-kernel, linux-can, netdev
In-Reply-To: <20230419223323.20384-3-jm@ti.com>

On 20/04/2023 00:33, Judith Mendez wrote:
> For MCAN, remove interrupt and interrupt names from the required
> section.
> 
> On AM62x SoC, MCANs on MCU domain do not have hardware interrupt
> routed to A53 Linux, instead they will use software interrupt
> by hrtimer. Make interrupt attributes optional in MCAN node
> by removing from required section.
> 
> Signed-off-by: Judith Mendez <jm@ti.com>
> ---


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof


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* Re: [PATCH 2/4] dt-bindings: net: can: Make interrupt attributes optional for MCAN
From: Krzysztof Kozlowski @ 2023-04-20 15:47 UTC (permalink / raw)
  To: Marc Kleine-Budde, Judith Mendez
  Cc: Chandrasekar Ramakrishnan, Wolfgang Grandegger, David S . Miller,
	Eric Dumazet, Jakub Kicinski, Paolo Abeni, Schuyler Patton,
	Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Rob Herring,
	Krzysztof Kozlowski, Oliver Hartkopp, linux-arm-kernel,
	devicetree, linux-kernel, linux-can, netdev
In-Reply-To: <20230420-zoom-demystify-c31d6bf25295-mkl@pengutronix.de>

On 20/04/2023 12:01, Marc Kleine-Budde wrote:
> On 19.04.2023 17:33:21, Judith Mendez wrote:
>> For MCAN, remove interrupt and interrupt names from the required
>> section.
>>
>> On AM62x SoC, MCANs on MCU domain do not have hardware interrupt
>> routed to A53 Linux, instead they will use software interrupt
>> by hrtimer. Make interrupt attributes optional in MCAN node
>> by removing from required section.
>>
>> Signed-off-by: Judith Mendez <jm@ti.com>
> 
> This series basically adds polling support to the driver, which is
> needed due to HW limitations.
> 
> The proposed logic in the driver is to use polling if
> platform_get_irq_byname() fails (due to whatever reason) use polling
> with a hard-coded interval.
> 
> In the kernel I've found the following properties that describe the
> polling interval:
> 
> bindings/input/input.yaml:
> 
> |   poll-interval:
> |     description: Poll interval time in milliseconds.
> |     $ref: /schemas/types.yaml#/definitions/uint32
> 
> 
> bindings/thermal/thermal-zones.yaml:
> 
> |       polling-delay:
> |         $ref: /schemas/types.yaml#/definitions/uint32
> |         description:
> |           The maximum number of milliseconds to wait between polls when
> |           checking this thermal zone. Setting this to 0 disables the polling
> |           timers setup by the thermal framework and assumes that the thermal
> |           sensors in this zone support interrupts.
> 
> bindings/regulator/dlg,da9121.yaml
> 
> |   dlg,irq-polling-delay-passive-ms:
> |     minimum: 1000
> |     maximum: 10000
> |     description: |
> |       Specify the polling period, measured in milliseconds, between interrupt status
> |       update checks. Range 1000-10000 ms.
> 
> From my point of view the poll-interval from the input subsystem looks
> good. Any objections to use it to specify the polling interval for
> IRQ-less devices, too?

Better to skip it, if delay can be figured out by driver based on
something else (e.g. clocks).

Best regards,
Krzysztof


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* Re: [PATCH] perf cs-etm: Add support for coresight trace for any range of CPUs
From: James Clark @ 2023-04-20 15:44 UTC (permalink / raw)
  To: Suzuki K Poulose, Ganapatrao Kulkarni
  Cc: mathieu.poirier, acme, darren, scott, scclevenger, linux-kernel,
	coresight, linux-arm-kernel, mike.leach
In-Reply-To: <902dea0e-456b-d763-fdb5-a520ea3d7536@arm.com>



On 20/04/2023 14:03, Suzuki K Poulose wrote:
> On 20/04/2023 13:37, Ganapatrao Kulkarni wrote:
>>
>>
>> On 20-04-2023 06:00 pm, James Clark wrote:
>>>
>>>
>>> On 20/04/2023 12:47, Ganapatrao Kulkarni wrote:
>>>>
> 
> ...
> 
>>>> My patch is rebased on 6.3-RC7 codebase with Mike's 3 perf patches
>>>> related to dynamic id [1] support(queued for 6.4).
>>>>
>>>> "perf report -D" works for me.
>>>
>>> I was referring to sparse CPU lists, which I think you mentioned above
>>> doesn't work even with this patch.
>>>
>>>>
>>>> [1] https://www.spinics.net/lists/linux-perf-users/msg27452.html
>>>>
>>>
>>> It should be based on the next branch here:
>>> git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git
>>
>> OK.
> 
> It need not be. Since this patch is purely perf tools patch and has
> nothing to do with the kernel drivers, it should be beased on whatever
> the tip of the perf tool tree is. Otherwise we risk rebasing to that
> eventually.
> 
> Cheers
> Suzuki
> 

Good point, sorry for the confusion!

I wonder if we could have some kind of new staging branch that has both
up to date perf and coresight changes at the same time? Either that
would make things like this easier, or more complicated. I'm not sure.

I suppose I can DIY it quite easily but then everyone would have to as well.

James

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* Re: [PATCH v3 1/2] dt-bindings: arm: sunxi: add ICnova A20 ADB4006 binding
From: Krzysztof Kozlowski @ 2023-04-20 15:42 UTC (permalink / raw)
  To: Ludwig Kormann, samuel, jernej.skrabec, wens, robh+dt,
	krzysztof.kozlowski+dt, andre.przywara
  Cc: linux-arm-kernel, devicetree, linux-sunxi, linux-kernel
In-Reply-To: <20230420102409.1394618-2-ludwig.kormann@in-circuit.de>

On 20/04/2023 12:24, Ludwig Kormann wrote:
> Document board compatible names for In-Circuit ICnova A20 ADB4006
> development board.
> 
> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
> Signed-off-by: Ludwig Kormann <ludwig.kormann@in-circuit.de>
> ---


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof


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* Re: [PATCH v2 1/4] spi: s3c64xx: changed to PIO mode if there is no DMA
From: Krzysztof Kozlowski @ 2023-04-20 15:40 UTC (permalink / raw)
  To: Jaewon Kim, Mark Brown, Andi Shyti, Alim Akhtar
  Cc: linux-spi, linux-samsung-soc, linux-arm-kernel, linux-kernel,
	Chanho Park
In-Reply-To: <20230419060639.38853-2-jaewon02.kim@samsung.com>

On 19/04/2023 08:06, Jaewon Kim wrote:
> Polling mode supported with qurik if there was no DMA in the SOC.
> However, there are cased where we cannot or do not want to use DMA.
> To support this case, if DMA is not set, it is switched to polling mode.
> 

(...)

>  #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
> -#define is_polling(x)	(x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL)
> +#define is_polling(x)	(x->cntrlr_info->polling)
>  
>  #define RXBUSY    (1<<2)
>  #define TXBUSY    (1<<3)
> @@ -1067,6 +1066,11 @@ static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
>  		sci->num_cs = temp;
>  	}
>  
> +	if (!of_find_property(dev->of_node, "dmas", NULL)) {

of_property_present()


Best regards,
Krzysztof


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* Re: [PATCH v2 2/4] spi: s3c64xx: add cpu_relax in polling loop
From: Krzysztof Kozlowski @ 2023-04-20 15:39 UTC (permalink / raw)
  To: Jaewon Kim, Mark Brown, Andi Shyti, Alim Akhtar
  Cc: linux-spi, linux-samsung-soc, linux-arm-kernel, linux-kernel,
	Chanho Park
In-Reply-To: <abbf5608-dbe7-af39-e555-d76ffe65dea4@samsung.com>

On 19/04/2023 13:13, Jaewon Kim wrote:
> 
> On 23. 4. 19. 17:14, Krzysztof Kozlowski wrote:
>> On 19/04/2023 08:06, Jaewon Kim wrote:
>>> Adds cpu_relax() to prevent long busy-wait.
>> How cpu_relax prevents long waiting?
> 
> As I know, cpu_relax() can be converted to yield. This can prevent 
> excessive use of the CPU in busy-loop.

That's ok, you just wrote that it will prevent long waiting, so I assume
it will shorten the wait time.

> 
> I'll replace poor sentence like below in v3.
> 
> ("Adds cpu_relax() to allow CPU relaxation in busy-loop")
> 
>>> There is busy-wait loop to check data transfer completion in polling mode.
>>>
>>> Signed-off-by: Jaewon Kim<jaewon02.kim@samsung.com>
>>> ---
>>>   drivers/spi/spi-s3c64xx.c | 1 +
>>>   1 file changed, 1 insertion(+)
>>>
>>> diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
>>> index 273aa02322d9..886722fb40ea 100644
>>> --- a/drivers/spi/spi-s3c64xx.c
>>> +++ b/drivers/spi/spi-s3c64xx.c
>>> @@ -568,6 +568,7 @@ static int s3c64xx_wait_for_pio(struct s3c64xx_spi_driver_data *sdd,
>>>   
>>>   	val = msecs_to_loops(ms);
>>>   	do {
>>> +		cpu_relax();
>> Shouldn't this be just readl_poll_timeout()? Or the syntax would be too
>> complicated?
> 
> I think we can replace this while() loop to readl_poll_timeout().
> 
> However, we should use 0 value as 'delay_us' parameter. Because delay 
> can affect throughput.
> 
> 
> My purpose is add relax to this busy-loop.
> 
> we cannot give relax if we change to readl_poll_timeout().

readl_poll_timeout() will know to do the best. You do not need to add
cpu_relax there.


Best regards,
Krzysztof


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* Re: [PATCH v2 4/4] spi: s3c64xx: support interrupt based pio mode
From: Krzysztof Kozlowski @ 2023-04-20 15:37 UTC (permalink / raw)
  To: Jaewon Kim, Mark Brown, Andi Shyti, Alim Akhtar
  Cc: linux-spi, linux-samsung-soc, linux-arm-kernel, linux-kernel,
	Chanho Park
In-Reply-To: <af95919d-f422-feec-b58d-a9b8c54af6d8@samsung.com>

On 19/04/2023 11:45, Jaewon Kim wrote:
>>>   static int s3c64xx_wait_for_pio(struct s3c64xx_spi_driver_data *sdd,
>>> -				struct spi_transfer *xfer)
>>> +				struct spi_transfer *xfer, int use_irq)
>>>   {
>>>   	void __iomem *regs = sdd->regs;
>>>   	unsigned long val;
>>> +	unsigned long time;
>>>   	u32 status;
>>>   	int loops;
>>>   	u32 cpy_len;
>>> @@ -563,17 +568,24 @@ static int s3c64xx_wait_for_pio(struct s3c64xx_spi_driver_data *sdd,
>>>   	int ms;
>>>   	u32 tx_time;
>>>   
>>> -	/* sleep during signal transfer time */
>>> -	status = readl(regs + S3C64XX_SPI_STATUS);
>>> -	if (RX_FIFO_LVL(status, sdd) < xfer->len) {
>>> -		tx_time = (xfer->len * 8 * 1000 * 1000) / sdd->cur_speed;
>>> -		usleep_range(tx_time / 2, tx_time);
>>> -	}
>> You just added this code. Adding and immediately removing it, suggests
>> this should be one patch.
>>
> This code has been moved, not removed.

Move consists of remove and add. Add it in correct place since beginning.

Best regards,
Krzysztof


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* Re: [PATCH v2 11/19] arm64: add PTE_UXN/PTE_WRITE to SWAPPER_*_FLAGS
From: Joey Gouly @ 2023-04-20 15:29 UTC (permalink / raw)
  To: Catalin Marinas
  Cc: linux-arm-kernel, nd, broonie, james.morse, mark.rutland, maz,
	oliver.upton, suzuki.poulose, will, yuzenghui
In-Reply-To: <ZDgvQ8LQtW0fA4rS@arm.com>

Hi,

On Thu, Apr 13, 2023 at 05:35:15PM +0100, Catalin Marinas wrote:
> On Thu, Apr 13, 2023 at 12:05:05PM +0100, Joey Gouly wrote:
> > With PIE enabled, the swapper PTEs would have a Permission Indirection Index
> > (PIIndex) of 0. A PIIndex of 0 is not currently used by any other PTEs.
> > 
> > To avoid using index 0 specifically for the swapper PTEs, mark them as
> > PTE_UXN and PTE_WRITE, so that they map to a PAGE_KERNEL_EXEC equivalent.
> > 
> > Signed-off-by: Joey Gouly <joey.gouly@arm.com>
> > Cc: Catalin Marinas <catalin.marinas@arm.com>
> > Cc: Will Deacon <will@kernel.org>
> > Cc: Mark Rutland <mark.rutland@arm.com>
> > ---
> >  arch/arm64/include/asm/kernel-pgtable.h | 4 ++--
> >  arch/arm64/kernel/head.S                | 8 ++++----
> >  arch/arm64/mm/proc.S                    | 2 +-
> >  3 files changed, 7 insertions(+), 7 deletions(-)
> > 
> > diff --git a/arch/arm64/include/asm/kernel-pgtable.h b/arch/arm64/include/asm/kernel-pgtable.h
> > index fcd14197756f..daf1909116f6 100644
> > --- a/arch/arm64/include/asm/kernel-pgtable.h
> > +++ b/arch/arm64/include/asm/kernel-pgtable.h
> > @@ -104,8 +104,8 @@
> >  /*
> >   * Initial memory map attributes.
> >   */
> > -#define SWAPPER_PTE_FLAGS	(PTE_TYPE_PAGE | PTE_AF | PTE_SHARED)
> > -#define SWAPPER_PMD_FLAGS	(PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S)
> > +#define SWAPPER_PTE_FLAGS	(PTE_TYPE_PAGE | PTE_AF | PTE_SHARED | PTE_UXN | PTE_WRITE)
> > +#define SWAPPER_PMD_FLAGS	(PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S | PTE_UXN | PTE_WRITE)
> 
> I mentioned on the previous version, I think it's better not to add the
> PTE_WRITE here but in the users of these macros where writeable is
> required (e.g. SWAPPER_RX_MMUFLAGS doesn't need PTE_WRITE as it has
> PTE_RDONLY).

I didn't ignore the previous comment, I just misunderstood it and thought I
should leave it as is. I've made the change now!

Thanks,
Joey

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* [PATCH v2 3/3] firmware: arm_ffa: Fix FFA device names for logical partitions
From: Sudeep Holla @ 2023-04-20 15:06 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: Sudeep Holla, Marc Bonnici, Jens Wiklander, Lucian Paul-Trifu
In-Reply-To: <20230419-ffa_fixes_6-4-v2-0-d9108e43a176@arm.com>

Each physical partition can provide multiple services each with UUID.
Each such service can be presented as logical partition with a unique
combination of VM ID and UUID. The number of distinct UUID in a system
will be less than or equal to the number of logical partitions.

However, currently it fails to register more than one logical partition
or service within a physical partition as the device name contains only
VM ID while both VM ID and UUID are maintained in the partition information.
The kernel complains with the below message:

  | sysfs: cannot create duplicate filename '/devices/arm-ffa-8001'
  | CPU: 1 PID: 1 Comm: swapper/0 Not tainted 6.3.0-rc7 #8
  | Hardware name: FVP Base RevC (DT)
  | Call trace:
  |  dump_backtrace+0xf8/0x118
  |  show_stack+0x18/0x24
  |  dump_stack_lvl+0x50/0x68
  |  dump_stack+0x18/0x24
  |  sysfs_create_dir_ns+0xe0/0x13c
  |  kobject_add_internal+0x220/0x3d4
  |  kobject_add+0x94/0x100
  |  device_add+0x144/0x5d8
  |  device_register+0x20/0x30
  |  ffa_device_register+0x88/0xd8
  |  ffa_setup_partitions+0x108/0x1b8
  |  ffa_init+0x2ec/0x3a4
  |  do_one_initcall+0xcc/0x240
  |  do_initcall_level+0x8c/0xac
  |  do_initcalls+0x54/0x94
  |  do_basic_setup+0x1c/0x28
  |  kernel_init_freeable+0x100/0x16c
  |  kernel_init+0x20/0x1a0
  |  ret_from_fork+0x10/0x20
  | kobject_add_internal failed for arm-ffa-8001 with -EEXIST, don't try to
  | register things with the same name in the same directory.
  | arm_ffa arm-ffa: unable to register device arm-ffa-8001 err=-17
  | ARM FF-A: ffa_setup_partitions: failed to register partition ID 0x8001

By virtue of being random enough to avoid collisions when generated in a
distributed system, there is no way to compress UUID keys to the number
of bits required to identify each. We can eliminate '-' in the name but
it is not worth eliminating 4 bytes and add unnecessary logic for doing
that. Also v1.0 doesn't provide the UUID of the partitions which makes
it hard to use the same for the device name.

So to keep it simple, let us alloc an ID using ida_alloc() and append the
same to "arm-ffa" to make up a unique device name. Also stash the id value
in ffa_dev to help freeing the ID later when the device is destroyed.

Fixes: e781858488b9 ("firmware: arm_ffa: Add initial FFA bus support for device enumeration")
Reported-by: Lucian Paul-Trifu <lucian.paul-trifu@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
---
 drivers/firmware/arm_ffa/bus.c | 16 +++++++++++++---
 include/linux/arm_ffa.h        |  1 +
 2 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/drivers/firmware/arm_ffa/bus.c b/drivers/firmware/arm_ffa/bus.c
index 36bd5423c2f0..2b8bfcd010f5 100644
--- a/drivers/firmware/arm_ffa/bus.c
+++ b/drivers/firmware/arm_ffa/bus.c
@@ -15,6 +15,8 @@
 
 #include "common.h"
 
+static DEFINE_IDA(ffa_bus_id);
+
 static int ffa_device_match(struct device *dev, struct device_driver *drv)
 {
 	const struct ffa_device_id *id_table;
@@ -131,6 +133,7 @@ static void ffa_release_device(struct device *dev)
 {
 	struct ffa_device *ffa_dev = to_ffa_dev(dev);
 
+	ida_free(&ffa_bus_id, ffa_dev->id);
 	kfree(ffa_dev);
 }
 
@@ -171,18 +174,24 @@ bool ffa_device_is_valid(struct ffa_device *ffa_dev)
 struct ffa_device *ffa_device_register(const uuid_t *uuid, int vm_id,
 				       const struct ffa_ops *ops)
 {
-	int ret;
+	int id, ret;
 	struct device *dev;
 	struct ffa_device *ffa_dev;
 
+	id = ida_alloc_min(&ffa_bus_id, 1, GFP_KERNEL);
+	if (id < 0)
+		return NULL;
+
 	ffa_dev = kzalloc(sizeof(*ffa_dev), GFP_KERNEL);
-	if (!ffa_dev)
+	if (!ffa_dev) {
+		ida_free(&ffa_bus_id, id);
 		return NULL;
+	}
 
 	dev = &ffa_dev->dev;
 	dev->bus = &ffa_bus_type;
 	dev->release = ffa_release_device;
-	dev_set_name(&ffa_dev->dev, "arm-ffa-%04x", vm_id);
+	dev_set_name(&ffa_dev->dev, "arm-ffa-%d", id);
 
 	ffa_dev->vm_id = vm_id;
 	ffa_dev->ops = ops;
@@ -218,4 +227,5 @@ void arm_ffa_bus_exit(void)
 {
 	ffa_devices_unregister();
 	bus_unregister(&ffa_bus_type);
+	ida_destroy(&ffa_bus_id);
 }
diff --git a/include/linux/arm_ffa.h b/include/linux/arm_ffa.h
index c87aeecaa9b2..583fe3b49a49 100644
--- a/include/linux/arm_ffa.h
+++ b/include/linux/arm_ffa.h
@@ -96,6 +96,7 @@
 
 /* FFA Bus/Device/Driver related */
 struct ffa_device {
+	u32 id;
 	int vm_id;
 	bool mode_32bit;
 	uuid_t uuid;

-- 
2.40.0


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* [PATCH v2 0/3] firmware: arm_ffa: Some fixes for v6.4
From: Sudeep Holla @ 2023-04-20 15:06 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: Sudeep Holla, Marc Bonnici, Jens Wiklander, Lucian Paul-Trifu

This series has assorted set of 3 fixes to the issues reported recently.

Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
---
Changes in v2:
- Remove the usage of index to the partition information table as FFA device
  id as that is possible only if the core driver adds the device but ideally
  since it is exported ffa_device_register() can be called from anywhere
  and the ID must be generated within it to avoid collision.
- Used IDA for device ID allocation
- Link to v1: https://lore.kernel.org/r/20230419-ffa_fixes_6-4-v1-0-1881ee6699f1@arm.com

---
Sudeep Holla (3):
      firmware: arm_ffa: Check if ffa_driver remove is present before executing
      firmware: arm_ffa: Fix usage of partition info get count flag
      firmware: arm_ffa: Fix FFA device names for logical partitions

 drivers/firmware/arm_ffa/bus.c    | 19 +++++++++++++++----
 drivers/firmware/arm_ffa/driver.c |  3 ++-
 include/linux/arm_ffa.h           |  1 +
 3 files changed, 18 insertions(+), 5 deletions(-)
---
base-commit: cb0856346a60fe3eb837ba5e73588a41f81ac05f
change-id: 20230419-ffa_fixes_6-4-cf2aadf75d05

Best regards,
-- 
Regards,
Sudeep


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* [PATCH v2 1/3] firmware: arm_ffa: Check if ffa_driver remove is present before executing
From: Sudeep Holla @ 2023-04-20 15:06 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: Sudeep Holla, Marc Bonnici, Jens Wiklander, Lucian Paul-Trifu
In-Reply-To: <20230419-ffa_fixes_6-4-v2-0-d9108e43a176@arm.com>

Currently ffa_drv->remove() is called unconditionally from
ffa_device_remove(). Since the driver registration doesn't check for it
and allows it to be registered without .remove callback, we need to check
for the presence of it before executing it from ffa_device_remove() to
above a NULL pointer dereference like the one below:

  | Unable to handle kernel NULL pointer dereference at virtual address 0000000000000000
  | Mem abort info:
  |   ESR = 0x0000000086000004
  |   EC = 0x21: IABT (current EL), IL = 32 bits
  |   SET = 0, FnV = 0
  |   EA = 0, S1PTW = 0
  |   FSC = 0x04: level 0 translation fault
  | user pgtable: 4k pages, 48-bit VAs, pgdp=0000000881cc8000
  | [0000000000000000] pgd=0000000000000000, p4d=0000000000000000
  | Internal error: Oops: 0000000086000004 [#1] PREEMPT SMP
  | CPU: 3 PID: 130 Comm: rmmod Not tainted 6.3.0-rc7 #6
  | Hardware name: FVP Base RevC (DT)
  | pstate: 63402809 (nZCv daif +PAN -UAO +TCO +DIT -SSBS BTYPE=-c)
  | pc : 0x0
  | lr : ffa_device_remove+0x20/0x2c
  | Call trace:
  |  0x0
  |  device_release_driver_internal+0x16c/0x260
  |  driver_detach+0x90/0xd0
  |  bus_remove_driver+0xdc/0x11c
  |  driver_unregister+0x30/0x54
  |  ffa_driver_unregister+0x14/0x20
  |  cleanup_module+0x18/0xeec
  |  __arm64_sys_delete_module+0x234/0x378
  |  invoke_syscall+0x40/0x108
  |  el0_svc_common+0xb4/0xf0
  |  do_el0_svc+0x30/0xa4
  |  el0_svc+0x2c/0x7c
  |  el0t_64_sync_handler+0x84/0xf0
  |  el0t_64_sync+0x190/0x194

Fixes: 244f5d597e1e ("firmware: arm_ffa: Add missing remove callback to ffa_bus_type")
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
---
 drivers/firmware/arm_ffa/bus.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/firmware/arm_ffa/bus.c b/drivers/firmware/arm_ffa/bus.c
index f29d77ecf72d..36bd5423c2f0 100644
--- a/drivers/firmware/arm_ffa/bus.c
+++ b/drivers/firmware/arm_ffa/bus.c
@@ -53,7 +53,8 @@ static void ffa_device_remove(struct device *dev)
 {
 	struct ffa_driver *ffa_drv = to_ffa_driver(dev->driver);
 
-	ffa_drv->remove(to_ffa_dev(dev));
+	if (ffa_drv->remove)
+		ffa_drv->remove(to_ffa_dev(dev));
 }
 
 static int ffa_device_uevent(const struct device *dev, struct kobj_uevent_env *env)

-- 
2.40.0


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* [PATCH v2 2/3] firmware: arm_ffa: Fix usage of partition info get count flag
From: Sudeep Holla @ 2023-04-20 15:06 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: Sudeep Holla, Marc Bonnici, Jens Wiklander, Lucian Paul-Trifu
In-Reply-To: <20230419-ffa_fixes_6-4-v2-0-d9108e43a176@arm.com>

Commit bb1be7498500 ("firmware: arm_ffa: Add v1.1 get_partition_info support")
adds support to discovery the UUIDs of the partitions or just fetch the
partition count using the PARTITION_INFO_GET_RETURN_COUNT_ONLY flag.

However the commit doesn't handle the fact that the older version doesn't
understand the flag and must be MBZ which results in firmware returning
invalid parameter error. That results in the failure of the driver probe
which is in correct.

Limit the usage of the PARTITION_INFO_GET_RETURN_COUNT_ONLY flag for the
versions above v1.0(i.e v1.1 and onwards) which fixes the issue.

Fixes: bb1be7498500 ("firmware: arm_ffa: Add v1.1 get_partition_info support")
Reported-by: Jens Wiklander <jens.wiklander@linaro.org>
Reported-by: Marc Bonnici <marc.bonnici@arm.com>
Tested-by: Jens Wiklander <jens.wiklander@linaro.org>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
---
 drivers/firmware/arm_ffa/driver.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/firmware/arm_ffa/driver.c b/drivers/firmware/arm_ffa/driver.c
index fa85c64d3ded..4aced2e5b772 100644
--- a/drivers/firmware/arm_ffa/driver.c
+++ b/drivers/firmware/arm_ffa/driver.c
@@ -193,7 +193,8 @@ __ffa_partition_info_get(u32 uuid0, u32 uuid1, u32 uuid2, u32 uuid3,
 	int idx, count, flags = 0, sz, buf_sz;
 	ffa_value_t partition_info;
 
-	if (!buffer || !num_partitions) /* Just get the count for now */
+	if (drv_info->version > FFA_VERSION_1_0 &&
+	    (!buffer || !num_partitions)) /* Just get the count for now */
 		flags = PARTITION_INFO_GET_RETURN_COUNT_ONLY;
 
 	mutex_lock(&drv_info->rx_lock);

-- 
2.40.0


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