* Re: [PATCH v3 1/5] dt-bindings: mfd: Add rk816 binding
From: Alex Bee @ 2024-03-23 21:17 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Lee Jones, Chris Zhong, Zhang Qing, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, linux-gpio, Rob Herring,
Conor Dooley, Heiko Stuebner, Linus Walleij, Liam Girdwood,
Mark Brown
In-Reply-To: <368eb339-4f0f-4471-9367-9263caa3fab7@linaro.org>
Am 23.03.24 um 15:32 schrieb Krzysztof Kozlowski:
> On 23/03/2024 14:27, Alex Bee wrote:
>> Add DT binding document for Rockchip's RK816 PMIC
>>
>> Signed-off-by: Alex Bee <knaerzche@gmail.com>
>
>> + regulators:
>> + type: object
>> + patternProperties:
>> + '^(boost|dcdc[1-4]|ldo[1-6]|otg-switch)$':
>> + type: object
>> + $ref: /schemas/regulator/regulator.yaml#
>> + unevaluatedProperties: false
> This is good.
>
>> + unevaluatedProperties: false
> I missed it last time, apologies. This (second) unevaluated should be
> "additionalProperties: false" instead.
Alright. Since there are no driver changes required for this change, I'll
give the other maintainers some time to review and fix it alongside in v4.
Alex
> With this fixed:
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
>
>
> Best regards,
> Krzysztof
>
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* Re: [WIP 1/3] rust: Introduce atomic module
From: Boqun Feng @ 2024-03-23 19:30 UTC (permalink / raw)
To: Miguel Ojeda
Cc: Andrew Lunn, rust-for-linux, linux-kernel, linux-arch, llvm,
Miguel Ojeda, Alex Gaynor, Wedson Almeida Filho, Gary Guo,
Björn Roy Baron, Benno Lossin, Andreas Hindborg, Alice Ryhl,
Alan Stern, Andrea Parri, Will Deacon, Peter Zijlstra,
Nicholas Piggin, David Howells, Jade Alglave, Luc Maranget,
Paul E. McKenney, Akira Yokosawa, Daniel Lustig, Joel Fernandes,
Nathan Chancellor, Nick Desaulniers, kent.overstreet,
Greg Kroah-Hartman, elver, Mark Rutland, Thomas Gleixner,
Ingo Molnar, Borislav Petkov, Dave Hansen, x86, H. Peter Anvin,
Catalin Marinas, torvalds, linux-arm-kernel, linux-fsdevel
In-Reply-To: <CANiq72=tB=uxaL9XGbnTBpXmj1pXEbxHQJDtAcA_yDiLjTVkRA@mail.gmail.com>
On Sat, Mar 23, 2024 at 08:13:56PM +0100, Miguel Ojeda wrote:
> On Sat, Mar 23, 2024 at 1:03 AM Boqun Feng <boqun.feng@gmail.com> wrote:
> >
> > I can continue to look an elegant way, now since we compile our own
> > `core` crate (where Rust atomic library locates), we can certain do a
> > sed trick to exclude the atomic code from Rust. It's pretty hacky, but
> > maybe others know how to teach linter to help.
>
> Yeah, but it requires copying the source and so on, like we did for
> `rusttest`. I would prefer to avoid another hack like that though (and
> the plan is to get rid of the existing hack anyway).
Agreed! The problem is better resolved via modularization of `core`.
Regards,
Boqun
>
> Cheers,
> Miguel
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* Re: [WIP 1/3] rust: Introduce atomic module
From: Miguel Ojeda @ 2024-03-23 19:13 UTC (permalink / raw)
To: Boqun Feng
Cc: Andrew Lunn, rust-for-linux, linux-kernel, linux-arch, llvm,
Miguel Ojeda, Alex Gaynor, Wedson Almeida Filho, Gary Guo,
Björn Roy Baron, Benno Lossin, Andreas Hindborg, Alice Ryhl,
Alan Stern, Andrea Parri, Will Deacon, Peter Zijlstra,
Nicholas Piggin, David Howells, Jade Alglave, Luc Maranget,
Paul E. McKenney, Akira Yokosawa, Daniel Lustig, Joel Fernandes,
Nathan Chancellor, Nick Desaulniers, kent.overstreet,
Greg Kroah-Hartman, elver, Mark Rutland, Thomas Gleixner,
Ingo Molnar, Borislav Petkov, Dave Hansen, x86, H. Peter Anvin,
Catalin Marinas, torvalds, linux-arm-kernel, linux-fsdevel
In-Reply-To: <Zf4cP6lx7LHmt3dz@boqun-archlinux>
On Sat, Mar 23, 2024 at 1:03 AM Boqun Feng <boqun.feng@gmail.com> wrote:
>
> I can continue to look an elegant way, now since we compile our own
> `core` crate (where Rust atomic library locates), we can certain do a
> sed trick to exclude the atomic code from Rust. It's pretty hacky, but
> maybe others know how to teach linter to help.
Yeah, but it requires copying the source and so on, like we did for
`rusttest`. I would prefer to avoid another hack like that though (and
the plan is to get rid of the existing hack anyway).
Cheers,
Miguel
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* Re: [WIP 1/3] rust: Introduce atomic module
From: Miguel Ojeda @ 2024-03-23 19:09 UTC (permalink / raw)
To: Andrew Lunn
Cc: Alice Ryhl, Boqun Feng, rust-for-linux, linux-kernel, linux-arch,
llvm, Miguel Ojeda, Alex Gaynor, Wedson Almeida Filho, Gary Guo,
Björn Roy Baron, Benno Lossin, Andreas Hindborg, Alan Stern,
Andrea Parri, Will Deacon, Peter Zijlstra, Nicholas Piggin,
David Howells, Jade Alglave, Luc Maranget, Paul E. McKenney,
Akira Yokosawa, Daniel Lustig, Joel Fernandes, Nathan Chancellor,
Nick Desaulniers, kent.overstreet, Greg Kroah-Hartman, elver,
Mark Rutland, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
Dave Hansen, x86, H. Peter Anvin, Catalin Marinas, torvalds,
linux-arm-kernel, linux-fsdevel
In-Reply-To: <497668ec-c2d5-4cb4-9c2d-8e6f7129a42e@lunn.ch>
On Sat, Mar 23, 2024 at 3:10 PM Andrew Lunn <andrew@lunn.ch> wrote:
>
> Just looking down the road a bit, are there other features in the
> standard library which are not applicable to Linux kernel space?
> Ideally we want a solution not just for atomics but a generic solution
> which can disable a collection of features? Maybe one by one?
We requested a few of these in the past for both `core` [1] and
`alloc` [2], and we got some which we use (see the `cfg(no_*)`s). It
is what we called "modularization of `core`" too.
[1] https://github.com/Rust-for-Linux/linux/issues/514
[2] https://github.com/Rust-for-Linux/linux/issues/408
Cheers,
Miguel
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* Re: [PATCH v3 8/9] dt-bindings: xlnx: Add VTC and TPG bindings
From: Conor Dooley @ 2024-03-23 19:08 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Anatoliy Klymenko, Laurent Pinchart, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, David Airlie, Daniel Vetter,
Michal Simek, Andrzej Hajda, Neil Armstrong, Robert Foss,
Jonas Karlman, Jernej Skrabec, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Mauro Carvalho Chehab, Tomi Valkeinen, dri-devel,
linux-arm-kernel, linux-kernel, devicetree, linux-media
In-Reply-To: <4439d51f-072a-4b0f-a6e4-b95192eac83b@linaro.org>
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On Sat, Mar 23, 2024 at 11:22:22AM +0100, Krzysztof Kozlowski wrote:
> On 22/03/2024 19:05, Conor Dooley wrote:
> > On Fri, Mar 22, 2024 at 06:59:18AM +0100, Krzysztof Kozlowski wrote:
> >> On 21/03/2024 21:43, Anatoliy Klymenko wrote:
> >>> diff --git a/include/dt-bindings/media/media-bus-format.h b/include/dt-bindings/media/media-bus-format.h
> >>> new file mode 100644
> >>> index 000000000000..60fc6e11dabc
> >>> --- /dev/null
> >>> +++ b/include/dt-bindings/media/media-bus-format.h
> >>> @@ -0,0 +1,177 @@
> >>> +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
> >>> +/*
> >>> + * Media Bus API header
> >>> + *
> >>> + * Copyright (C) 2009, Guennadi Liakhovetski <g.liakhovetski@gmx.de>
> >>> + *
> >>> + * This program is free software; you can redistribute it and/or modify
> >>> + * it under the terms of the GNU General Public License version 2 as
> >>> + * published by the Free Software Foundation.
> >>
> >> That's not true. Your SPDX tells something entirely different.
> >>
> >> Anyway, you did not explain why you need to copy anything anywhere.
> >
> > I assume by "copy anything anywhere" you mean "why did you copy a linux
> > uapi header into the bindings?
>
> Yes, I trimmed context too much.
>
> The reasoning of copying some UAPI and claiming it is a binding was:
> "Copy media-bus-formats.h into dt-bindings/media to suplement TPG DT node."
> so as seen *there is no reason*.
>
> Commit msg should explain why we are doing things.
Oh for sure. I was just wondering if you were complaining about the UAPI
header or if that comment was about the copyright notice. If it had been
the latter I was gonna point out the former :)
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* Re: [PATCH v2 5/5] KVM: arm64: Exclude FP ownership from kvm_vcpu_arch
From: Marc Zyngier @ 2024-03-23 19:06 UTC (permalink / raw)
To: Mark Brown
Cc: kvmarm, linux-arm-kernel, kvm, James Morse, Suzuki K Poulose,
Oliver Upton, Zenghui Yu, James Clark, Anshuman Khandual,
Dongli Zhang
In-Reply-To: <fe5edef8-e61d-42b3-b4da-6f6bebd60013@sirena.org.uk>
On Fri, 22 Mar 2024 17:52:45 +0000,
Mark Brown <broonie@kernel.org> wrote:
>
> On Fri, Mar 22, 2024 at 05:09:45PM +0000, Marc Zyngier wrote:
> > In retrospect, it is fairly obvious that the FP state ownership
> > is only meaningful for a given CPU, and that locating this
> > information in the vcpu was just a mistake.
> >
> > Move the ownership tracking into the host data structure, and
> > rename it from fp_state to fp_owner, which is a better description
> > (name suggested by Mark Brown).
>
> There's still the thing with the interaction with SME support - to
> summarise what I think you're asking for the userspace ABI there:
Well, the SME support is still pretty prospective, and this patch has
no impact on an existing ABI.
>
> - Create a requirement for userspace to set SVCR prior to setting any
> vector impacted register to ensure the correct format and that data
> isn't zeroed when SVCR is set.
> - Use the value of SVCR.SM and the guest maximum SVE and SME VLs to
> select the currently visible vector length for the Z, P and FFR
> registers, and if FFR can be accessed if not available in streaming
> mode.
> - Changes to SVCR.SM zero register data in the same way writes to the
> physical register do.
> - This also implies discarding or failing all writes to ZA and ZT0
> unless SVCR.ZA is set for consistency.
All of that seems reasonable, as long as it is comes as a consequence
of enabling SME. It should be run by the QEMU people though, as they
are the ones that will make use of it. Please Cc them when you post
the patches or even better, reach out to them beforehand.
> - Add support for the V registers in the sysreg interface when SVE is
> enabled.
We already support the V registers with KVM_REG_ARM_CORE_REG(). Why
would you add any new interface for this? The kernel should be
perfectly capable of dealing with the placement of the data in the
internal structures, and there is no need to tie the userspace ABI to
how we deal with that placement (kvm_regs is already purely
userspace).
> then the implementation can do what it likes to achieve that, the most
> obvious thing being to store in native format for the current hardware
> mode based on SVCR.{SM,ZA}. Does that sound about right?
Apart from the statement about the V registers, this seems OK. But
again, I want to see this agreed with the QEMU folks.
M.
--
Without deviation from the norm, progress is not possible.
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* Re: [PATCH 04/25] clk: meson: a1: add the audio clock controller driver
From: Jan Dakinevich @ 2024-03-23 18:02 UTC (permalink / raw)
To: Jerome Brunet
Cc: Neil Armstrong, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, Kevin Hilman,
Martin Blumenstingl, Liam Girdwood, Mark Brown, Linus Walleij,
Jaroslav Kysela, Takashi Iwai, linux-amlogic, linux-clk,
devicetree, linux-kernel, linux-arm-kernel, alsa-devel,
linux-sound, linux-gpio, kernel
In-Reply-To: <1jo7bafv90.fsf@starbuckisacylon.baylibre.com>
Jerome, I have reworked my driver reusing axg-audio code as most as I
could and now I have one more question. Lets see on this definition from
axg-audio:
#define AUD_MST_MUX(_name, _reg, _flag) \
AUD_MUX(_name##_sel, _reg, 0x7, 24, _flag, \
mst_mux_parent_data, 0)
#define AUD_MST_MCLK_MUX(_name, _reg) \
AUD_MST_MUX(_name, _reg, CLK_MUX_ROUND_CLOSEST)
CLK_SET_RATE_PARENT is not set here. But why? It means, that topmost pll
clock will not be reconfigured at runtime to satisfy the rate that was
requested from axg-tdm.
On 3/19/24 11:30, Jerome Brunet wrote:
>
> On Tue 19 Mar 2024 at 04:47, Jan Dakinevich <jan.dakinevich@salutedevices.com> wrote:
>
>> Let's start from the end:
>>
>>> No - Looks to me you just have two clock controllers you are trying
>> force into one.
>>
>>> Again, this shows 2 devices. The one related to your 'map0' should
>> request AUD2_CLKID_AUDIOTOP as input and enable it right away.
>>
>> Most of fishy workarounds that you commented is caused the fact the mmio
>> of this clock controller is divided into two parts. Compare it with
>> axg-audio driver, things that was part of contigous memory region (like
>> pdm) here are moved to second region. Is this enough to make a guess
>> that these are two devices?
>
> I see obsolutely no reason to think it is a single device nor to add all the quirks
> you have the way you did. So yes, in that case, 2 zones, 2 devices.
>
>>
>> Concerning AUD2_CLKID_AUDIOTOP clock, as it turned out, it must be
>> enabled before enabling of clocks from second region too. That is
>> AUD2_CLKID_AUDIOTOP clock feeds both parts of this clock controller.
>>
>
> Yes. I understood the first time around and already commented on that.
>
>>
>> On 3/15/24 12:20, Jerome Brunet wrote:
>>>
>>> On Fri 15 Mar 2024 at 02:21, Jan Dakinevich <jan.dakinevich@salutedevices.com> wrote:
>>>
>>>> This controller provides clocks and reset functionality for audio
>>>> peripherals on Amlogic A1 SoC family.
>>>>
>>>> The driver is almost identical to 'axg-audio', however it would be better
>>>> to keep it separate due to following reasons:
>>>>
>>>> - significant amount of bits has another definition. I will bring there
>>>> a mess of new defines with A1_ suffixes.
>>>>
>>>> - registers of this controller are located in two separate regions. It
>>>> will give a lot of complications for 'axg-audio' to support this.
>>>>
>>>> Signed-off-by: Jan Dakinevich <jan.dakinevich@salutedevices.com>
>>>> ---
>>>> drivers/clk/meson/Kconfig | 13 +
>>>> drivers/clk/meson/Makefile | 1 +
>>>> drivers/clk/meson/a1-audio.c | 556 +++++++++++++++++++++++++++++++++++
>>>> drivers/clk/meson/a1-audio.h | 58 ++++
>>>> 4 files changed, 628 insertions(+)
>>>> create mode 100644 drivers/clk/meson/a1-audio.c
>>>> create mode 100644 drivers/clk/meson/a1-audio.h
>>>>
>>>> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
>>>> index d6a2fa5f7e88..80c4a18c83d2 100644
>>>> --- a/drivers/clk/meson/Kconfig
>>>> +++ b/drivers/clk/meson/Kconfig
>>>> @@ -133,6 +133,19 @@ config COMMON_CLK_A1_PERIPHERALS
>>>> device, A1 SoC Family. Say Y if you want A1 Peripherals clock
>>>> controller to work.
>>>>
>>>> +config COMMON_CLK_A1_AUDIO
>>>> + tristate "Amlogic A1 SoC Audio clock controller support"
>>>> + depends on ARM64
>>>> + select COMMON_CLK_MESON_REGMAP
>>>> + select COMMON_CLK_MESON_CLKC_UTILS
>>>> + select COMMON_CLK_MESON_PHASE
>>>> + select COMMON_CLK_MESON_SCLK_DIV
>>>> + select COMMON_CLK_MESON_AUDIO_RSTC
>>>> + help
>>>> + Support for the Audio clock controller on Amlogic A113L based
>>>> + device, A1 SoC Family. Say Y if you want A1 Audio clock controller
>>>> + to work.
>>>> +
>>>> config COMMON_CLK_G12A
>>>> tristate "G12 and SM1 SoC clock controllers support"
>>>> depends on ARM64
>>>> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
>>>> index 88d94921a4dc..4968fc7ad555 100644
>>>> --- a/drivers/clk/meson/Makefile
>>>> +++ b/drivers/clk/meson/Makefile
>>>> @@ -20,6 +20,7 @@ obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o
>>>> obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
>>>> obj-$(CONFIG_COMMON_CLK_A1_PLL) += a1-pll.o
>>>> obj-$(CONFIG_COMMON_CLK_A1_PERIPHERALS) += a1-peripherals.o
>>>> +obj-$(CONFIG_COMMON_CLK_A1_AUDIO) += a1-audio.o
>>>> obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
>>>> obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o
>>>> obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o
>>>> diff --git a/drivers/clk/meson/a1-audio.c b/drivers/clk/meson/a1-audio.c
>>>> new file mode 100644
>>>> index 000000000000..6039116c93ba
>>>> --- /dev/null
>>>> +++ b/drivers/clk/meson/a1-audio.c
>>>> @@ -0,0 +1,556 @@
>>>> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
>>>> +/*
>>>> + * Copyright (c) 2024, SaluteDevices. All Rights Reserved.
>>>> + *
>>>> + * Author: Jan Dakinevich <jan.dakinevich@salutedevices.com>
>>>> + */
>>>> +
>>>> +#include <linux/clk.h>
>>>> +#include <linux/clk-provider.h>
>>>> +#include <linux/init.h>
>>>> +#include <linux/of_device.h>
>>>> +#include <linux/module.h>
>>>> +#include <linux/platform_device.h>
>>>> +#include <linux/regmap.h>
>>>> +#include <linux/reset.h>
>>>> +#include <linux/reset-controller.h>
>>>> +#include <linux/slab.h>
>>>> +
>>>> +#include "meson-clkc-utils.h"
>>>> +#include "meson-audio-rstc.h"
>>>> +#include "clk-regmap.h"
>>>> +#include "clk-phase.h"
>>>> +#include "sclk-div.h"
>>>> +#include "a1-audio.h"
>>>> +
>>>> +#define AUDIO_PDATA(_name) \
>>>> + ((const struct clk_parent_data[]) { { .hw = &(_name).hw } })
>>>
>>> Not a fan - yet another level of macro.
>>>
>>>> +
>>>> +#define AUDIO_MUX(_name, _reg, _mask, _shift, _pdata) \
>>>> +static struct clk_regmap _name = { \
>>>> + .map = AUDIO_REG_MAP(_reg), \
>>>> + .data = &(struct clk_regmap_mux_data){ \
>>>> + .offset = AUDIO_REG_OFFSET(_reg), \
>>>> + .mask = (_mask), \
>>>> + .shift = (_shift), \
>>>> + }, \
>>>> + .hw.init = &(struct clk_init_data) { \
>>>> + .name = #_name, \
>>>> + .ops = &clk_regmap_mux_ops, \
>>>> + .parent_data = (_pdata), \
>>>> + .num_parents = ARRAY_SIZE(_pdata), \
>>>> + .flags = CLK_SET_RATE_PARENT, \
>>>> + }, \
>>>> +}
>>>> +
>>>> +#define AUDIO_DIV(_name, _reg, _shift, _width, _pdata) \
>>>> +static struct clk_regmap _name = { \
>>>> + .map = AUDIO_REG_MAP(_reg), \
>>>> + .data = &(struct clk_regmap_div_data){ \
>>>> + .offset = AUDIO_REG_OFFSET(_reg), \
>>>> + .shift = (_shift), \
>>>> + .width = (_width), \
>>>> + }, \
>>>> + .hw.init = &(struct clk_init_data) { \
>>>> + .name = #_name, \
>>>> + .ops = &clk_regmap_divider_ops, \
>>>> + .parent_data = (_pdata), \
>>>> + .num_parents = 1, \
>>>> + .flags = CLK_SET_RATE_PARENT, \
>>>> + }, \
>>>> +}
>>>> +
>>>> +#define AUDIO_GATE(_name, _reg, _bit, _pdata) \
>>>> +static struct clk_regmap _name = { \
>>>> + .map = AUDIO_REG_MAP(_reg), \
>>>> + .data = &(struct clk_regmap_gate_data){ \
>>>> + .offset = AUDIO_REG_OFFSET(_reg), \
>>>> + .bit_idx = (_bit), \
>>>> + }, \
>>>> + .hw.init = &(struct clk_init_data) { \
>>>> + .name = #_name, \
>>>> + .ops = &clk_regmap_gate_ops, \
>>>> + .parent_data = (_pdata), \
>>>> + .num_parents = 1, \
>>>> + .flags = CLK_SET_RATE_PARENT, \
>>>> + }, \
>>>> +}
>>>> +
>>>> +#define AUDIO_SCLK_DIV(_name, _reg, _div_shift, _div_width, \
>>>> + _hi_shift, _hi_width, _pdata, _set_rate_parent) \
>>>> +static struct clk_regmap _name = { \
>>>> + .map = AUDIO_REG_MAP(_reg), \
>>>> + .data = &(struct meson_sclk_div_data) { \
>>>> + .div = { \
>>>> + .reg_off = AUDIO_REG_OFFSET(_reg), \
>>>> + .shift = (_div_shift), \
>>>> + .width = (_div_width), \
>>>> + }, \
>>>> + .hi = { \
>>>> + .reg_off = AUDIO_REG_OFFSET(_reg), \
>>>> + .shift = (_hi_shift), \
>>>> + .width = (_hi_width), \
>>>> + }, \
>>>> + }, \
>>>> + .hw.init = &(struct clk_init_data) { \
>>>> + .name = #_name, \
>>>> + .ops = &meson_sclk_div_ops, \
>>>> + .parent_data = (_pdata), \
>>>> + .num_parents = 1, \
>>>> + .flags = (_set_rate_parent) ? CLK_SET_RATE_PARENT : 0, \
>>>
>>> Does not help readeability. Just pass the flag as axg-audio does.
>>>
>>>> + }, \
>>>> +}
>>>> +
>>>> +#define AUDIO_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2, \
>>>> + _pdata) \
>>>> +static struct clk_regmap _name = { \
>>>> + .map = AUDIO_REG_MAP(_reg), \
>>>> + .data = &(struct meson_clk_triphase_data) { \
>>>> + .ph0 = { \
>>>> + .reg_off = AUDIO_REG_OFFSET(_reg), \
>>>> + .shift = (_shift0), \
>>>> + .width = (_width), \
>>>> + }, \
>>>> + .ph1 = { \
>>>> + .reg_off = AUDIO_REG_OFFSET(_reg), \
>>>> + .shift = (_shift1), \
>>>> + .width = (_width), \
>>>> + }, \
>>>> + .ph2 = { \
>>>> + .reg_off = AUDIO_REG_OFFSET(_reg), \
>>>> + .shift = (_shift2), \
>>>> + .width = (_width), \
>>>> + }, \
>>>> + }, \
>>>> + .hw.init = &(struct clk_init_data) { \
>>>> + .name = #_name, \
>>>> + .ops = &meson_clk_triphase_ops, \
>>>> + .parent_data = (_pdata), \
>>>> + .num_parents = 1, \
>>>> + .flags = CLK_SET_RATE_PARENT | CLK_DUTY_CYCLE_PARENT, \
>>>> + }, \
>>>> +}
>>>> +
>>>> +#define AUDIO_SCLK_WS(_name, _reg, _width, _shift_ph, _shift_ws, \
>>>> + _pdata) \
>>>> +static struct clk_regmap _name = { \
>>>> + .map = AUDIO_REG_MAP(_reg), \
>>>> + .data = &(struct meson_sclk_ws_inv_data) { \
>>>> + .ph = { \
>>>> + .reg_off = AUDIO_REG_OFFSET(_reg), \
>>>> + .shift = (_shift_ph), \
>>>> + .width = (_width), \
>>>> + }, \
>>>> + .ws = { \
>>>> + .reg_off = AUDIO_REG_OFFSET(_reg), \
>>>> + .shift = (_shift_ws), \
>>>> + .width = (_width), \
>>>> + }, \
>>>> + }, \
>>>> + .hw.init = &(struct clk_init_data) { \
>>>> + .name = #_name, \
>>>> + .ops = &meson_sclk_ws_inv_ops, \
>>>> + .parent_data = (_pdata), \
>>>> + .num_parents = 1, \
>>>> + .flags = CLK_SET_RATE_PARENT | CLK_DUTY_CYCLE_PARENT, \
>>>> + }, \
>>>> +}
>>>
>>> All the above does essentially the same things as the macro of
>>> axg-audio, to some minor differences. Yet it is another set to maintain.
>>>
>>
>> Except one thing... Here I keep memory identifier to which this clock
>> belongs:
>>
>> .map = AUDIO_REG_MAP(_reg),
>>
>> It is workaround, but ->map the only common field in clk_regmap that
>> could be used for this purpose.
>>
>>
>>> I'd much prefer if you put the axg-audio macro in a header a re-used
>>> those. There would a single set to maintain. You may then specialize the
>>> included in the driver C file, to avoid redundant parameters
>>>
>>> Rework axg-audio to use clk_parent_data if you must, but not in the same
>>> series please.
>>>
>>>> +
>>>> +static const struct clk_parent_data a1_pclk_pdata[] = {
>>>> + { .fw_name = "pclk", },
>>>> +};
>>>> +
>>>> +AUDIO_GATE(audio_ddr_arb, AUDIO_CLK_GATE_EN0, 0, a1_pclk_pdata);
>>>> +AUDIO_GATE(audio_tdmin_a, AUDIO_CLK_GATE_EN0, 1, a1_pclk_pdata);
>>>> +AUDIO_GATE(audio_tdmin_b, AUDIO_CLK_GATE_EN0, 2, a1_pclk_pdata);
>>>> +AUDIO_GATE(audio_tdmin_lb, AUDIO_CLK_GATE_EN0, 3, a1_pclk_pdata);
>>>> +AUDIO_GATE(audio_loopback, AUDIO_CLK_GATE_EN0, 4, a1_pclk_pdata);
>>>> +AUDIO_GATE(audio_tdmout_a, AUDIO_CLK_GATE_EN0, 5, a1_pclk_pdata);
>>>> +AUDIO_GATE(audio_tdmout_b, AUDIO_CLK_GATE_EN0, 6, a1_pclk_pdata);
>>>> +AUDIO_GATE(audio_frddr_a, AUDIO_CLK_GATE_EN0, 7, a1_pclk_pdata);
>>>> +AUDIO_GATE(audio_frddr_b, AUDIO_CLK_GATE_EN0, 8, a1_pclk_pdata);
>>>> +AUDIO_GATE(audio_toddr_a, AUDIO_CLK_GATE_EN0, 9, a1_pclk_pdata);
>>>> +AUDIO_GATE(audio_toddr_b, AUDIO_CLK_GATE_EN0, 10, a1_pclk_pdata);
>>>> +AUDIO_GATE(audio_spdifin, AUDIO_CLK_GATE_EN0, 11, a1_pclk_pdata);
>>>> +AUDIO_GATE(audio_resample, AUDIO_CLK_GATE_EN0, 12, a1_pclk_pdata);
>>>> +AUDIO_GATE(audio_eqdrc, AUDIO_CLK_GATE_EN0, 13, a1_pclk_pdata);
>>>> +AUDIO_GATE(audio_audiolocker, AUDIO_CLK_GATE_EN0, 14, a1_pclk_pdata);
>>> This is what I mean by redundant parameter ^
>>>
>>
>> Yep. I could define something like AUDIO_PCLK_GATE().
>>
>>>> +
>>>> +AUDIO_GATE(audio2_ddr_arb, AUDIO2_CLK_GATE_EN0, 0, a1_pclk_pdata);
>>>> +AUDIO_GATE(audio2_pdm, AUDIO2_CLK_GATE_EN0, 1, a1_pclk_pdata);
>>>> +AUDIO_GATE(audio2_tdmin_vad, AUDIO2_CLK_GATE_EN0, 2, a1_pclk_pdata);
>>>> +AUDIO_GATE(audio2_toddr_vad, AUDIO2_CLK_GATE_EN0, 3, a1_pclk_pdata);
>>>> +AUDIO_GATE(audio2_vad, AUDIO2_CLK_GATE_EN0, 4, a1_pclk_pdata);
>>>> +AUDIO_GATE(audio2_audiotop, AUDIO2_CLK_GATE_EN0, 7, a1_pclk_pdata);
>>>> +
>>>> +static const struct clk_parent_data a1_mst_pdata[] = {
>>>> + { .fw_name = "dds_in" },
>>>> + { .fw_name = "fclk_div2" },
>>>> + { .fw_name = "fclk_div3" },
>>>> + { .fw_name = "hifi_pll" },
>>>> + { .fw_name = "xtal" },
>>>> +};
>>>> +
>>>> +#define AUDIO_MST_MCLK(_name, _reg) \
>>>> + AUDIO_MUX(_name##_mux, (_reg), 0x7, 24, a1_mst_pdata); \
>>>> + AUDIO_DIV(_name##_div, (_reg), 0, 16, \
>>>> + AUDIO_PDATA(_name##_mux)); \
>>>> + AUDIO_GATE(_name, (_reg), 31, AUDIO_PDATA(_name##_div))
>>>> +
>>>> +AUDIO_MST_MCLK(audio_mst_a_mclk, AUDIO_MCLK_A_CTRL);
>>>> +AUDIO_MST_MCLK(audio_mst_b_mclk, AUDIO_MCLK_B_CTRL);
>>>> +AUDIO_MST_MCLK(audio_mst_c_mclk, AUDIO_MCLK_C_CTRL);
>>>> +AUDIO_MST_MCLK(audio_mst_d_mclk, AUDIO_MCLK_D_CTRL);
>>>> +AUDIO_MST_MCLK(audio_spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
>>>> +AUDIO_MST_MCLK(audio_eqdrc_clk, AUDIO_CLK_EQDRC_CTRL);
>>>> +
>>>> +AUDIO_MUX(audio_resample_clk_mux, AUDIO_CLK_RESAMPLE_CTRL, 0xf, 24,
>>>> + a1_mst_pdata);
>>>> +AUDIO_DIV(audio_resample_clk_div, AUDIO_CLK_RESAMPLE_CTRL, 0, 8,
>>>> + AUDIO_PDATA(audio_resample_clk_mux));
>>>> +AUDIO_GATE(audio_resample_clk, AUDIO_CLK_RESAMPLE_CTRL, 31,
>>>> + AUDIO_PDATA(audio_resample_clk_div));
>>>> +
>>>> +AUDIO_MUX(audio_locker_in_clk_mux, AUDIO_CLK_LOCKER_CTRL, 0xf, 8,
>>>> + a1_mst_pdata);
>>>> +AUDIO_DIV(audio_locker_in_clk_div, AUDIO_CLK_LOCKER_CTRL, 0, 8,
>>>> + AUDIO_PDATA(audio_locker_in_clk_mux));
>>>> +AUDIO_GATE(audio_locker_in_clk, AUDIO_CLK_LOCKER_CTRL, 15,
>>>> + AUDIO_PDATA(audio_locker_in_clk_div));
>>>> +
>>>> +AUDIO_MUX(audio_locker_out_clk_mux, AUDIO_CLK_LOCKER_CTRL, 0xf, 24,
>>>> + a1_mst_pdata);
>>>> +AUDIO_DIV(audio_locker_out_clk_div, AUDIO_CLK_LOCKER_CTRL, 16, 8,
>>>> + AUDIO_PDATA(audio_locker_out_clk_mux));
>>>> +AUDIO_GATE(audio_locker_out_clk, AUDIO_CLK_LOCKER_CTRL, 31,
>>>> + AUDIO_PDATA(audio_locker_out_clk_div));
>>>> +
>>>> +AUDIO_MST_MCLK(audio2_vad_mclk, AUDIO2_MCLK_VAD_CTRL);
>>>> +AUDIO_MST_MCLK(audio2_vad_clk, AUDIO2_CLK_VAD_CTRL);
>>>> +AUDIO_MST_MCLK(audio2_pdm_dclk, AUDIO2_CLK_PDMIN_CTRL0);
>>>> +AUDIO_MST_MCLK(audio2_pdm_sysclk, AUDIO2_CLK_PDMIN_CTRL1);
>>>> +
>>>> +#define AUDIO_MST_SCLK(_name, _reg0, _reg1, _pdata) \
>>>> + AUDIO_GATE(_name##_pre_en, (_reg0), 31, (_pdata)); \
>>>> + AUDIO_SCLK_DIV(_name##_div, (_reg0), 20, 10, 0, 0, \
>>>> + AUDIO_PDATA(_name##_pre_en), true); \
>>>> + AUDIO_GATE(_name##_post_en, (_reg0), 30, \
>>>> + AUDIO_PDATA(_name##_div)); \
>>>> + AUDIO_TRIPHASE(_name, (_reg1), 1, 0, 2, 4, \
>>>> + AUDIO_PDATA(_name##_post_en))
>>>> +
>>>
>>> Again, I'm not a fan of this many levels of macro. I can live with it
>>> but certainly don't want the burden of reviewing and maintaining for
>>> clock driver. AXG / G12 and A1 are obviously closely related, so make it common.
>>>
>>>> +#define AUDIO_MST_LRCLK(_name, _reg0, _reg1, _pdata) \
>>>> + AUDIO_SCLK_DIV(_name##_div, (_reg0), 0, 10, 10, 10, \
>>>> + (_pdata), false); \
>>>> + AUDIO_TRIPHASE(_name, (_reg1), 1, 1, 3, 5, \
>>>> + AUDIO_PDATA(_name##_div))
>>>> +
>>>> +AUDIO_MST_SCLK(audio_mst_a_sclk, AUDIO_MST_A_SCLK_CTRL0, AUDIO_MST_A_SCLK_CTRL1,
>>>> + AUDIO_PDATA(audio_mst_a_mclk));
>>>> +AUDIO_MST_SCLK(audio_mst_b_sclk, AUDIO_MST_B_SCLK_CTRL0, AUDIO_MST_B_SCLK_CTRL1,
>>>> + AUDIO_PDATA(audio_mst_b_mclk));
>>>> +AUDIO_MST_SCLK(audio_mst_c_sclk, AUDIO_MST_C_SCLK_CTRL0, AUDIO_MST_C_SCLK_CTRL1,
>>>> + AUDIO_PDATA(audio_mst_c_mclk));
>>>> +AUDIO_MST_SCLK(audio_mst_d_sclk, AUDIO_MST_D_SCLK_CTRL0, AUDIO_MST_D_SCLK_CTRL1,
>>>> + AUDIO_PDATA(audio_mst_d_mclk));
>>>> +
>>>> +AUDIO_MST_LRCLK(audio_mst_a_lrclk, AUDIO_MST_A_SCLK_CTRL0, AUDIO_MST_A_SCLK_CTRL1,
>>>> + AUDIO_PDATA(audio_mst_a_sclk_post_en));
>>>> +AUDIO_MST_LRCLK(audio_mst_b_lrclk, AUDIO_MST_B_SCLK_CTRL0, AUDIO_MST_B_SCLK_CTRL1,
>>>> + AUDIO_PDATA(audio_mst_b_sclk_post_en));
>>>> +AUDIO_MST_LRCLK(audio_mst_c_lrclk, AUDIO_MST_C_SCLK_CTRL0, AUDIO_MST_C_SCLK_CTRL1,
>>>> + AUDIO_PDATA(audio_mst_c_sclk_post_en));
>>>> +AUDIO_MST_LRCLK(audio_mst_d_lrclk, AUDIO_MST_D_SCLK_CTRL0, AUDIO_MST_D_SCLK_CTRL1,
>>>> + AUDIO_PDATA(audio_mst_d_sclk_post_en));
>>>> +
>>>> +static const struct clk_parent_data a1_mst_sclk_pdata[] = {
>>>> + { .hw = &audio_mst_a_sclk.hw },
>>>> + { .hw = &audio_mst_b_sclk.hw },
>>>> + { .hw = &audio_mst_c_sclk.hw },
>>>> + { .hw = &audio_mst_d_sclk.hw },
>>>> + { .fw_name = "slv_sclk0" },
>>>> + { .fw_name = "slv_sclk1" },
>>>> + { .fw_name = "slv_sclk2" },
>>>> + { .fw_name = "slv_sclk3" },
>>>> + { .fw_name = "slv_sclk4" },
>>>> + { .fw_name = "slv_sclk5" },
>>>> + { .fw_name = "slv_sclk6" },
>>>> + { .fw_name = "slv_sclk7" },
>>>> + { .fw_name = "slv_sclk8" },
>>>> + { .fw_name = "slv_sclk9" },
>>>> +};
>>>> +
>>>> +static const struct clk_parent_data a1_mst_lrclk_pdata[] = {
>>>> + { .hw = &audio_mst_a_lrclk.hw },
>>>> + { .hw = &audio_mst_b_lrclk.hw },
>>>> + { .hw = &audio_mst_c_lrclk.hw },
>>>> + { .hw = &audio_mst_d_lrclk.hw },
>>>> + { .fw_name = "slv_lrclk0" },
>>>> + { .fw_name = "slv_lrclk1" },
>>>> + { .fw_name = "slv_lrclk2" },
>>>> + { .fw_name = "slv_lrclk3" },
>>>> + { .fw_name = "slv_lrclk4" },
>>>> + { .fw_name = "slv_lrclk5" },
>>>> + { .fw_name = "slv_lrclk6" },
>>>> + { .fw_name = "slv_lrclk7" },
>>>> + { .fw_name = "slv_lrclk8" },
>>>> + { .fw_name = "slv_lrclk9" },
>>>> +};
>>>> +
>>>> +#define AUDIO_TDM_SCLK(_name, _reg) \
>>>> + AUDIO_MUX(_name##_mux, (_reg), 0xf, 24, a1_mst_sclk_pdata); \
>>>> + AUDIO_GATE(_name##_pre_en, (_reg), 31, \
>>>> + AUDIO_PDATA(_name##_mux)); \
>>>> + AUDIO_GATE(_name##_post_en, (_reg), 30, \
>>>> + AUDIO_PDATA(_name##_pre_en)); \
>>>> + AUDIO_SCLK_WS(_name, (_reg), 1, 29, 28, \
>>>> + AUDIO_PDATA(_name##_post_en))
>>>> +
>>>> +#define AUDIO_TDM_LRCLK(_name, _reg) \
>>>> + AUDIO_MUX(_name, (_reg), 0xf, 20, a1_mst_lrclk_pdata)
>>>> +
>>>> +AUDIO_TDM_SCLK(audio_tdmin_a_sclk, AUDIO_CLK_TDMIN_A_CTRL);
>>>> +AUDIO_TDM_SCLK(audio_tdmin_b_sclk, AUDIO_CLK_TDMIN_B_CTRL);
>>>> +AUDIO_TDM_SCLK(audio_tdmin_lb_sclk, AUDIO_CLK_TDMIN_LB_CTRL);
>>>> +AUDIO_TDM_SCLK(audio_tdmout_a_sclk, AUDIO_CLK_TDMOUT_A_CTRL);
>>>> +AUDIO_TDM_SCLK(audio_tdmout_b_sclk, AUDIO_CLK_TDMOUT_B_CTRL);
>>>> +
>>>> +AUDIO_TDM_LRCLK(audio_tdmin_a_lrclk, AUDIO_CLK_TDMIN_A_CTRL);
>>>> +AUDIO_TDM_LRCLK(audio_tdmin_b_lrclk, AUDIO_CLK_TDMIN_B_CTRL);
>>>> +AUDIO_TDM_LRCLK(audio_tdmin_lb_lrclk, AUDIO_CLK_TDMIN_LB_CTRL);
>>>> +AUDIO_TDM_LRCLK(audio_tdmout_a_lrclk, AUDIO_CLK_TDMOUT_A_CTRL);
>>>> +AUDIO_TDM_LRCLK(audio_tdmout_b_lrclk, AUDIO_CLK_TDMOUT_B_CTRL);
>>>> +
>>>> +static struct clk_hw *a1_audio_hw_clks[] = {
>>>> + [AUD_CLKID_DDR_ARB] = &audio_ddr_arb.hw,
>>>> + [AUD_CLKID_TDMIN_A] = &audio_tdmin_a.hw,
>>>> + [AUD_CLKID_TDMIN_B] = &audio_tdmin_b.hw,
>>>> + [AUD_CLKID_TDMIN_LB] = &audio_tdmin_lb.hw,
>>>> + [AUD_CLKID_LOOPBACK] = &audio_loopback.hw,
>>>> + [AUD_CLKID_TDMOUT_A] = &audio_tdmout_a.hw,
>>>> + [AUD_CLKID_TDMOUT_B] = &audio_tdmout_b.hw,
>>>> + [AUD_CLKID_FRDDR_A] = &audio_frddr_a.hw,
>>>> + [AUD_CLKID_FRDDR_B] = &audio_frddr_b.hw,
>>>> + [AUD_CLKID_TODDR_A] = &audio_toddr_a.hw,
>>>> + [AUD_CLKID_TODDR_B] = &audio_toddr_b.hw,
>>>> + [AUD_CLKID_SPDIFIN] = &audio_spdifin.hw,
>>>> + [AUD_CLKID_RESAMPLE] = &audio_resample.hw,
>>>> + [AUD_CLKID_EQDRC] = &audio_eqdrc.hw,
>>>> + [AUD_CLKID_LOCKER] = &audio_audiolocker.hw,
>>>> + [AUD_CLKID_MST_A_MCLK_SEL] = &audio_mst_a_mclk_mux.hw,
>>>> + [AUD_CLKID_MST_A_MCLK_DIV] = &audio_mst_a_mclk_div.hw,
>>>> + [AUD_CLKID_MST_A_MCLK] = &audio_mst_a_mclk.hw,
>>>> + [AUD_CLKID_MST_B_MCLK_SEL] = &audio_mst_b_mclk_mux.hw,
>>>> + [AUD_CLKID_MST_B_MCLK_DIV] = &audio_mst_b_mclk_div.hw,
>>>> + [AUD_CLKID_MST_B_MCLK] = &audio_mst_b_mclk.hw,
>>>> + [AUD_CLKID_MST_C_MCLK_SEL] = &audio_mst_c_mclk_mux.hw,
>>>> + [AUD_CLKID_MST_C_MCLK_DIV] = &audio_mst_c_mclk_div.hw,
>>>> + [AUD_CLKID_MST_C_MCLK] = &audio_mst_c_mclk.hw,
>>>> + [AUD_CLKID_MST_D_MCLK_SEL] = &audio_mst_d_mclk_mux.hw,
>>>> + [AUD_CLKID_MST_D_MCLK_DIV] = &audio_mst_d_mclk_div.hw,
>>>> + [AUD_CLKID_MST_D_MCLK] = &audio_mst_d_mclk.hw,
>>>> + [AUD_CLKID_RESAMPLE_CLK_SEL] = &audio_resample_clk_mux.hw,
>>>> + [AUD_CLKID_RESAMPLE_CLK_DIV] = &audio_resample_clk_div.hw,
>>>> + [AUD_CLKID_RESAMPLE_CLK] = &audio_resample_clk.hw,
>>>> + [AUD_CLKID_LOCKER_IN_CLK_SEL] = &audio_locker_in_clk_mux.hw,
>>>> + [AUD_CLKID_LOCKER_IN_CLK_DIV] = &audio_locker_in_clk_div.hw,
>>>> + [AUD_CLKID_LOCKER_IN_CLK] = &audio_locker_in_clk.hw,
>>>> + [AUD_CLKID_LOCKER_OUT_CLK_SEL] = &audio_locker_out_clk_mux.hw,
>>>> + [AUD_CLKID_LOCKER_OUT_CLK_DIV] = &audio_locker_out_clk_div.hw,
>>>> + [AUD_CLKID_LOCKER_OUT_CLK] = &audio_locker_out_clk.hw,
>>>> + [AUD_CLKID_SPDIFIN_CLK_SEL] = &audio_spdifin_clk_mux.hw,
>>>> + [AUD_CLKID_SPDIFIN_CLK_DIV] = &audio_spdifin_clk_div.hw,
>>>> + [AUD_CLKID_SPDIFIN_CLK] = &audio_spdifin_clk.hw,
>>>> + [AUD_CLKID_EQDRC_CLK_SEL] = &audio_eqdrc_clk_mux.hw,
>>>> + [AUD_CLKID_EQDRC_CLK_DIV] = &audio_eqdrc_clk_div.hw,
>>>> + [AUD_CLKID_EQDRC_CLK] = &audio_eqdrc_clk.hw,
>>>> + [AUD_CLKID_MST_A_SCLK_PRE_EN] = &audio_mst_a_sclk_pre_en.hw,
>>>> + [AUD_CLKID_MST_A_SCLK_DIV] = &audio_mst_a_sclk_div.hw,
>>>> + [AUD_CLKID_MST_A_SCLK_POST_EN] = &audio_mst_a_sclk_post_en.hw,
>>>> + [AUD_CLKID_MST_A_SCLK] = &audio_mst_a_sclk.hw,
>>>> + [AUD_CLKID_MST_B_SCLK_PRE_EN] = &audio_mst_b_sclk_pre_en.hw,
>>>> + [AUD_CLKID_MST_B_SCLK_DIV] = &audio_mst_b_sclk_div.hw,
>>>> + [AUD_CLKID_MST_B_SCLK_POST_EN] = &audio_mst_b_sclk_post_en.hw,
>>>> + [AUD_CLKID_MST_B_SCLK] = &audio_mst_b_sclk.hw,
>>>> + [AUD_CLKID_MST_C_SCLK_PRE_EN] = &audio_mst_c_sclk_pre_en.hw,
>>>> + [AUD_CLKID_MST_C_SCLK_DIV] = &audio_mst_c_sclk_div.hw,
>>>> + [AUD_CLKID_MST_C_SCLK_POST_EN] = &audio_mst_c_sclk_post_en.hw,
>>>> + [AUD_CLKID_MST_C_SCLK] = &audio_mst_c_sclk.hw,
>>>> + [AUD_CLKID_MST_D_SCLK_PRE_EN] = &audio_mst_d_sclk_pre_en.hw,
>>>> + [AUD_CLKID_MST_D_SCLK_DIV] = &audio_mst_d_sclk_div.hw,
>>>> + [AUD_CLKID_MST_D_SCLK_POST_EN] = &audio_mst_d_sclk_post_en.hw,
>>>> + [AUD_CLKID_MST_D_SCLK] = &audio_mst_d_sclk.hw,
>>>> + [AUD_CLKID_MST_A_LRCLK_DIV] = &audio_mst_a_lrclk_div.hw,
>>>> + [AUD_CLKID_MST_A_LRCLK] = &audio_mst_a_lrclk.hw,
>>>> + [AUD_CLKID_MST_B_LRCLK_DIV] = &audio_mst_b_lrclk_div.hw,
>>>> + [AUD_CLKID_MST_B_LRCLK] = &audio_mst_b_lrclk.hw,
>>>> + [AUD_CLKID_MST_C_LRCLK_DIV] = &audio_mst_c_lrclk_div.hw,
>>>> + [AUD_CLKID_MST_C_LRCLK] = &audio_mst_c_lrclk.hw,
>>>> + [AUD_CLKID_MST_D_LRCLK_DIV] = &audio_mst_d_lrclk_div.hw,
>>>> + [AUD_CLKID_MST_D_LRCLK] = &audio_mst_d_lrclk.hw,
>>>> + [AUD_CLKID_TDMIN_A_SCLK_SEL] = &audio_tdmin_a_sclk_mux.hw,
>>>> + [AUD_CLKID_TDMIN_A_SCLK_PRE_EN] = &audio_tdmin_a_sclk_pre_en.hw,
>>>> + [AUD_CLKID_TDMIN_A_SCLK_POST_EN] = &audio_tdmin_a_sclk_post_en.hw,
>>>> + [AUD_CLKID_TDMIN_A_SCLK] = &audio_tdmin_a_sclk.hw,
>>>> + [AUD_CLKID_TDMIN_A_LRCLK] = &audio_tdmin_a_lrclk.hw,
>>>> + [AUD_CLKID_TDMIN_B_SCLK_SEL] = &audio_tdmin_b_sclk_mux.hw,
>>>> + [AUD_CLKID_TDMIN_B_SCLK_PRE_EN] = &audio_tdmin_b_sclk_pre_en.hw,
>>>> + [AUD_CLKID_TDMIN_B_SCLK_POST_EN] = &audio_tdmin_b_sclk_post_en.hw,
>>>> + [AUD_CLKID_TDMIN_B_SCLK] = &audio_tdmin_b_sclk.hw,
>>>> + [AUD_CLKID_TDMIN_B_LRCLK] = &audio_tdmin_b_lrclk.hw,
>>>> + [AUD_CLKID_TDMIN_LB_SCLK_SEL] = &audio_tdmin_lb_sclk_mux.hw,
>>>> + [AUD_CLKID_TDMIN_LB_SCLK_PRE_EN] = &audio_tdmin_lb_sclk_pre_en.hw,
>>>> + [AUD_CLKID_TDMIN_LB_SCLK_POST_EN] = &audio_tdmin_lb_sclk_post_en.hw,
>>>> + [AUD_CLKID_TDMIN_LB_SCLK] = &audio_tdmin_lb_sclk.hw,
>>>> + [AUD_CLKID_TDMIN_LB_LRCLK] = &audio_tdmin_lb_lrclk.hw,
>>>> + [AUD_CLKID_TDMOUT_A_SCLK_SEL] = &audio_tdmout_a_sclk_mux.hw,
>>>> + [AUD_CLKID_TDMOUT_A_SCLK_PRE_EN] = &audio_tdmout_a_sclk_pre_en.hw,
>>>> + [AUD_CLKID_TDMOUT_A_SCLK_POST_EN] = &audio_tdmout_a_sclk_post_en.hw,
>>>> + [AUD_CLKID_TDMOUT_A_SCLK] = &audio_tdmout_a_sclk.hw,
>>>> + [AUD_CLKID_TDMOUT_A_LRCLK] = &audio_tdmout_a_lrclk.hw,
>>>> + [AUD_CLKID_TDMOUT_B_SCLK_SEL] = &audio_tdmout_b_sclk_mux.hw,
>>>> + [AUD_CLKID_TDMOUT_B_SCLK_PRE_EN] = &audio_tdmout_b_sclk_pre_en.hw,
>>>> + [AUD_CLKID_TDMOUT_B_SCLK_POST_EN] = &audio_tdmout_b_sclk_post_en.hw,
>>>> + [AUD_CLKID_TDMOUT_B_SCLK] = &audio_tdmout_b_sclk.hw,
>>>> + [AUD_CLKID_TDMOUT_B_LRCLK] = &audio_tdmout_b_lrclk.hw,
>>>> +
>>>> + [AUD2_CLKID_DDR_ARB] = &audio2_ddr_arb.hw,
>>>> + [AUD2_CLKID_PDM] = &audio2_pdm.hw,
>>>> + [AUD2_CLKID_TDMIN_VAD] = &audio2_tdmin_vad.hw,
>>>> + [AUD2_CLKID_TODDR_VAD] = &audio2_toddr_vad.hw,
>>>> + [AUD2_CLKID_VAD] = &audio2_vad.hw,
>>>> + [AUD2_CLKID_AUDIOTOP] = &audio2_audiotop.hw,
>>>> + [AUD2_CLKID_VAD_MCLK_SEL] = &audio2_vad_mclk_mux.hw,
>>>> + [AUD2_CLKID_VAD_MCLK_DIV] = &audio2_vad_mclk_div.hw,
>>>> + [AUD2_CLKID_VAD_MCLK] = &audio2_vad_mclk.hw,
>>>> + [AUD2_CLKID_VAD_CLK_SEL] = &audio2_vad_clk_mux.hw,
>>>> + [AUD2_CLKID_VAD_CLK_DIV] = &audio2_vad_clk_div.hw,
>>>> + [AUD2_CLKID_VAD_CLK] = &audio2_vad_clk.hw,
>>>> + [AUD2_CLKID_PDM_DCLK_SEL] = &audio2_pdm_dclk_mux.hw,
>>>> + [AUD2_CLKID_PDM_DCLK_DIV] = &audio2_pdm_dclk_div.hw,
>>>> + [AUD2_CLKID_PDM_DCLK] = &audio2_pdm_dclk.hw,
>>>> + [AUD2_CLKID_PDM_SYSCLK_SEL] = &audio2_pdm_sysclk_mux.hw,
>>>> + [AUD2_CLKID_PDM_SYSCLK_DIV] = &audio2_pdm_sysclk_div.hw,
>>>> + [AUD2_CLKID_PDM_SYSCLK] = &audio2_pdm_sysclk.hw,
>>>> +};
>>>> +
>>>> +static struct meson_clk_hw_data a1_audio_clks = {
>>>> + .hws = a1_audio_hw_clks,
>>>> + .num = ARRAY_SIZE(a1_audio_hw_clks),
>>>> +};
>>>> +
>>>> +static struct regmap *a1_audio_map(struct platform_device *pdev,
>>>> + unsigned int index)
>>>> +{
>>>> + char name[32];
>>>> + const struct regmap_config cfg = {
>>>> + .reg_bits = 32,
>>>> + .val_bits = 32,
>>>> + .reg_stride = 4,
>>>> + .name = name,
>>>
>>> Not necessary
>>>
>>
>> This implementation uses two regmaps, and this field allow to avoid
>> errors like this:
>>
>> [ 0.145530] debugfs: Directory 'fe050000.audio-clock-controller' with
>> parent 'regmap' already present!
>>
>>>> + };
>>>> + void __iomem *base;
>>>> +
>>>> + base = devm_platform_ioremap_resource(pdev, index);
>>>> + if (IS_ERR(base))
>>>> + return base;
>>>> +
>>>> + scnprintf(name, sizeof(name), "%d", index);
>>>> + return devm_regmap_init_mmio(&pdev->dev, base, &cfg);
>>>> +}
>>>
>>> That is overengineered. Please keep it simple. Declare the regmap_config
>>> as static const global, and do it like axg-audio please.
>>>
>>
>> This only reason why it is not "static const" because I need to set
>> unique name for each regmap.
>>
>>>> +
>>>> +static int a1_register_clk(struct platform_device *pdev,
>>>> + struct regmap *map0, struct regmap *map1,
>>>> + struct clk_hw *hw)
>>>> +{
>>>> + struct clk_regmap *clk = container_of(hw, struct clk_regmap, hw);
>>>> +
>>>> + if (!hw)
>>>> + return 0;
>>>> +
>>>> + switch ((unsigned long)clk->map) {
>>>> + case AUDIO_RANGE_0:
>>>> + clk->map = map0;
>>>> + break;
>>>> + case AUDIO_RANGE_1:
>>>> + clk->map = map1;
>>>> + break;
>>>
>>> ... fishy
>>>
>>>> + default:
>>>> + WARN_ON(1);
>>>> + return -EINVAL;
>>>> + }
>>>> +
>>>> + return devm_clk_hw_register(&pdev->dev, hw);
>>>> +}
>>>> +
>>>> +static int a1_audio_clkc_probe(struct platform_device *pdev)
>>>> +{
>>>> + struct regmap *map0, *map1;
>>>> + struct clk *clk;
>>>> + unsigned int i;
>>>> + int ret;
>>>> +
>>>> + clk = devm_clk_get_enabled(&pdev->dev, "pclk");
>>>> + if (WARN_ON(IS_ERR(clk)))
>>>> + return PTR_ERR(clk);
>>>> +
>>>> + map0 = a1_audio_map(pdev, 0);
>>>> + if (IS_ERR(map0))
>>>> + return PTR_ERR(map0);
>>>> +
>>>> + map1 = a1_audio_map(pdev, 1);
>>>> + if (IS_ERR(map1))
>>>> + return PTR_ERR(map1);
>>>
>>> No - Looks to me you just have two clock controllers you are trying
>>> force into one.
>>>
>>
>> See the begining.
>>
>>>> +
>>>> + /*
>>>> + * Register and enable AUD2_CLKID_AUDIOTOP clock first. Unless
>>>> + * it is enabled any read/write to 'map0' hangs the CPU.
>>>> + */
>>>> +
>>>> + ret = a1_register_clk(pdev, map0, map1,
>>>> + a1_audio_clks.hws[AUD2_CLKID_AUDIOTOP]);
>>>> + if (ret)
>>>> + return ret;
>>>> +
>>>> + ret = clk_prepare_enable(a1_audio_clks.hws[AUD2_CLKID_AUDIOTOP]->clk);
>>>> + if (ret)
>>>> + return ret;
>>>
>>> Again, this shows 2 devices. The one related to your 'map0' should
>>> request AUD2_CLKID_AUDIOTOP as input and enable it right away.
>>>
>>
>> See the begining.
>>
>>>> +
>>>> + for (i = 0; i < a1_audio_clks.num; i++) {
>>>> + if (i == AUD2_CLKID_AUDIOTOP)
>>>> + continue;
>>>> +
>>>> + ret = a1_register_clk(pdev, map0, map1, a1_audio_clks.hws[i]);
>>>> + if (ret)
>>>> + return ret;
>>>> + }
>>>> +
>>>> + ret = devm_of_clk_add_hw_provider(&pdev->dev, meson_clk_hw_get,
>>>> + &a1_audio_clks);
>>>> + if (ret)
>>>> + return ret;
>>>> +
>>>> + BUILD_BUG_ON((unsigned long)AUDIO_REG_MAP(AUDIO_SW_RESET0) !=
>>>> + AUDIO_RANGE_0);
>>>
>>> Why is that necessary ?
>>>
>>
>> A little paranoia. Here AUDIO_SW_RESET0 is handled as map0's register,
>> and I want to assert it.
>>
>>>> + return meson_audio_rstc_register(&pdev->dev, map0,
>>>> + AUDIO_REG_OFFSET(AUDIO_SW_RESET0), 32);
>>>> +}
>>>> +
>>>> +static const struct of_device_id a1_audio_clkc_match_table[] = {
>>>> + { .compatible = "amlogic,a1-audio-clkc", },
>>>> + {}
>>>> +};
>>>> +MODULE_DEVICE_TABLE(of, a1_audio_clkc_match_table);
>>>> +
>>>> +static struct platform_driver a1_audio_clkc_driver = {
>>>> + .probe = a1_audio_clkc_probe,
>>>> + .driver = {
>>>> + .name = "a1-audio-clkc",
>>>> + .of_match_table = a1_audio_clkc_match_table,
>>>> + },
>>>> +};
>>>> +module_platform_driver(a1_audio_clkc_driver);
>>>> +
>>>> +MODULE_DESCRIPTION("Amlogic A1 Audio Clock driver");
>>>> +MODULE_AUTHOR("Jan Dakinevich <jan.dakinevich@salutedevices.com>");
>>>> +MODULE_LICENSE("GPL");
>>>> diff --git a/drivers/clk/meson/a1-audio.h b/drivers/clk/meson/a1-audio.h
>>>> new file mode 100644
>>>> index 000000000000..f994e87276cd
>>>> --- /dev/null
>>>> +++ b/drivers/clk/meson/a1-audio.h
>>>> @@ -0,0 +1,58 @@
>>>> +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
>>>> +/*
>>>> + * Copyright (c) 2024, SaluteDevices. All Rights Reserved.
>>>> + *
>>>> + * Author: Jan Dakinevich <jan.dakinevich@salutedevices.com>
>>>> + */
>>>> +
>>>> +#ifndef __A1_AUDIO_H
>>>> +#define __A1_AUDIO_H
>>>> +
>>>> +#define AUDIO_RANGE_0 0xa
>>>> +#define AUDIO_RANGE_1 0xb
>>>> +#define AUDIO_RANGE_SHIFT 16
>>>> +
>>>> +#define AUDIO_REG(_range, _offset) \
>>>> + (((_range) << AUDIO_RANGE_SHIFT) + (_offset))
>>>> +
>>>> +#define AUDIO_REG_OFFSET(_reg) \
>>>> + ((_reg) & ((1 << AUDIO_RANGE_SHIFT) - 1))
>>>> +
>>>> +#define AUDIO_REG_MAP(_reg) \
>>>> + ((void *)((_reg) >> AUDIO_RANGE_SHIFT))
>>>
>>> That is seriouly overengineered.
>>> The following are offset. Just write what they are.
>>>
>>
>> This is all in order to keep range's identifier together with offset and
>> then use it to store the identifier in clk_regmaps.
>>
>>> There is not reason to put that into a header. It is only going to be
>>> used by a single driver.
>>>>> +
>>>> +#define AUDIO_CLK_GATE_EN0 AUDIO_REG(AUDIO_RANGE_0, 0x000)
>>>> +#define AUDIO_MCLK_A_CTRL AUDIO_REG(AUDIO_RANGE_0, 0x008)
>>>> +#define AUDIO_MCLK_B_CTRL AUDIO_REG(AUDIO_RANGE_0, 0x00c)
>>>> +#define AUDIO_MCLK_C_CTRL AUDIO_REG(AUDIO_RANGE_0, 0x010)
>>>> +#define AUDIO_MCLK_D_CTRL AUDIO_REG(AUDIO_RANGE_0, 0x014)
>>>> +#define AUDIO_MCLK_E_CTRL AUDIO_REG(AUDIO_RANGE_0, 0x018)
>>>> +#define AUDIO_MCLK_F_CTRL AUDIO_REG(AUDIO_RANGE_0, 0x01c)
>>>> +#define AUDIO_SW_RESET0 AUDIO_REG(AUDIO_RANGE_0, 0x028)
>>>> +#define AUDIO_MST_A_SCLK_CTRL0 AUDIO_REG(AUDIO_RANGE_0, 0x040)
>>>> +#define AUDIO_MST_A_SCLK_CTRL1 AUDIO_REG(AUDIO_RANGE_0, 0x044)
>>>> +#define AUDIO_MST_B_SCLK_CTRL0 AUDIO_REG(AUDIO_RANGE_0, 0x048)
>>>> +#define AUDIO_MST_B_SCLK_CTRL1 AUDIO_REG(AUDIO_RANGE_0, 0x04c)
>>>> +#define AUDIO_MST_C_SCLK_CTRL0 AUDIO_REG(AUDIO_RANGE_0, 0x050)
>>>> +#define AUDIO_MST_C_SCLK_CTRL1 AUDIO_REG(AUDIO_RANGE_0, 0x054)
>>>> +#define AUDIO_MST_D_SCLK_CTRL0 AUDIO_REG(AUDIO_RANGE_0, 0x058)
>>>> +#define AUDIO_MST_D_SCLK_CTRL1 AUDIO_REG(AUDIO_RANGE_0, 0x05c)
>>>> +#define AUDIO_CLK_TDMIN_A_CTRL AUDIO_REG(AUDIO_RANGE_0, 0x080)
>>>> +#define AUDIO_CLK_TDMIN_B_CTRL AUDIO_REG(AUDIO_RANGE_0, 0x084)
>>>> +#define AUDIO_CLK_TDMIN_LB_CTRL AUDIO_REG(AUDIO_RANGE_0, 0x08c)
>>>> +#define AUDIO_CLK_TDMOUT_A_CTRL AUDIO_REG(AUDIO_RANGE_0, 0x090)
>>>> +#define AUDIO_CLK_TDMOUT_B_CTRL AUDIO_REG(AUDIO_RANGE_0, 0x094)
>>>> +#define AUDIO_CLK_SPDIFIN_CTRL AUDIO_REG(AUDIO_RANGE_0, 0x09c)
>>>> +#define AUDIO_CLK_RESAMPLE_CTRL AUDIO_REG(AUDIO_RANGE_0, 0x0a4)
>>>> +#define AUDIO_CLK_LOCKER_CTRL AUDIO_REG(AUDIO_RANGE_0, 0x0a8)
>>>> +#define AUDIO_CLK_EQDRC_CTRL AUDIO_REG(AUDIO_RANGE_0, 0x0c0)
>>>> +
>>>> +#define AUDIO2_CLK_GATE_EN0 AUDIO_REG(AUDIO_RANGE_1, 0x00c)
>>>> +#define AUDIO2_MCLK_VAD_CTRL AUDIO_REG(AUDIO_RANGE_1, 0x040)
>>>> +#define AUDIO2_CLK_VAD_CTRL AUDIO_REG(AUDIO_RANGE_1, 0x044)
>>>> +#define AUDIO2_CLK_PDMIN_CTRL0 AUDIO_REG(AUDIO_RANGE_1, 0x058)
>>>> +#define AUDIO2_CLK_PDMIN_CTRL1 AUDIO_REG(AUDIO_RANGE_1, 0x05c)
>>>> +
>>>> +#include <dt-bindings/clock/amlogic,a1-audio-clkc.h>
>>>> +
>>>> +#endif /* __A1_AUDIO_H */
>>>
>>>
>
>
--
Best regards
Jan Dakinevich
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: Fixing the devicetree of Rock 5 Model B (and possibly others)
From: Pratham Patel @ 2024-03-23 17:23 UTC (permalink / raw)
To: Linux regressions mailing list
Cc: sebastian.reichel@collabora.com, saravanak@google.com,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
stable@vger.kernel.org
In-Reply-To: <092a7c4c-0a75-4b27-acec-385fdcfb9f7a@leemhuis.info>
[-- Attachment #1.1.1: Type: text/plain, Size: 620 bytes --]
On Saturday, March 23rd, 2024 at 22:47, Linux regression tracking (Thorsten Leemhuis) <regressions@leemhuis.info> wrote:
>
>
> On 23.03.24 18:02, Pratham Patel wrote:
>
> > Since the introduction of the `of: property: fw_devlink: Fix stupid bug in remote-endpoint parsing` patch,
>
>
> There is an earlier bug report asking for a revert of that patch:
>
> https://lore.kernel.org/all/ZfvN5jDrftG-YRG4@titan/
>
> > an issue
>
>
> Is your problem maybe similar to the one above?
I don't get that exact message in the boot log but yes.
> Ciao, Thorsten
-- Pratham Patel
[-- Attachment #1.1.2: publickey - prathampatel@thefossguy.com - 0xF2DDE54D.asc --]
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_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: Fixing the devicetree of Rock 5 Model B (and possibly others)
From: Linux regression tracking (Thorsten Leemhuis) @ 2024-03-23 17:17 UTC (permalink / raw)
To: Pratham Patel, sebastian.reichel@collabora.com,
saravanak@google.com
Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
regressions@lists.linux.dev, stable@vger.kernel.org
In-Reply-To: <tQ0L3-34g4t-mzfQIP6KDe5OYelGnEo6Udzq6Kb_nEcljppSQUXOktpE__nL-CdLOu9gW-4tIIbjtSbqrdCrjEkdhZLPiiHTqRcCB6WORuM=@thefossguy.com>
On 23.03.24 18:02, Pratham Patel wrote:
> Since the introduction of the `of: property: fw_devlink: Fix stupid bug in remote-endpoint parsing` patch,
There is an earlier bug report asking for a revert of that patch:
https://lore.kernel.org/all/ZfvN5jDrftG-YRG4@titan/
> an issue
Is your problem maybe similar to the one above?
Ciao, Thorsten
> with the device-tree of the Rock 5 Model B has been detected. All the stable kernels (6.7.y and 6.8.y) work on the Orange Pi 5, which has the Rockchip RK3588S SoC (same as the RK3588, but less I/O basically). So, being an owner of only two SBCs which use the RK3588* SoC, it appears that the Rock 5 Model B's DT is incorrect.
>
> I looked at the patch and tried several things, neither resulted in anything that would point me to the core issue. Then I tried this:
>
> ```
> $ grep -C 3 remote-endpoint arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
>
> port {
> es8316_p0_0: endpoint {
> remote-endpoint = <&i2s0_8ch_p0_0>;
> };
> };
> };
> --
> i2s0_8ch_p0_0: endpoint {
> dai-format = "i2s";
> mclk-fs = <256>;
> remote-endpoint = <&es8316_p0_0>;
> };
> };
> };
> ```
>
> So, from a cursory look, the issue seems to be related to either the DT node for the audio codec or related to the es8316's binding itself. Though I doubt that the later is the issue because if that were the issue, _someone_ with a Pine64 Pinebook Pro would've raised alarms. So far, this seems to be related to the `rk3588-rock-5b.dts` and possibly with the `rk3588s-rock-5a.dts` too.
>
> I would **love** to help but I'm afraid I device-trees are not something that I am at-all familiar with. That said, I am open to methods of debugging this issue to provide a fix myself.
>
> I would have replied to the patch's link but unfortunately, I haven't yet setup neomutt and my email provider's web UI doesn't have a [straightforward] way to reply using the 'In-Reply-To' header, hence a new thread. Apologies for the inconvenience caused.
>
> -- Pratham Patel
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: Fixing the devicetree of Rock 5 Model B (and possibly others)
From: Dragan Simic @ 2024-03-23 17:09 UTC (permalink / raw)
To: Pratham Patel
Cc: sebastian.reichel, saravanak, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, regressions, stable
In-Reply-To: <tQ0L3-34g4t-mzfQIP6KDe5OYelGnEo6Udzq6Kb_nEcljppSQUXOktpE__nL-CdLOu9gW-4tIIbjtSbqrdCrjEkdhZLPiiHTqRcCB6WORuM=@thefossguy.com>
Hello Pratham,
On 2024-03-23 18:02, Pratham Patel wrote:
> Since the introduction of the `of: property: fw_devlink: Fix stupid
> bug in remote-endpoint parsing` patch, an issue with the device-tree
> of the Rock 5 Model B has been detected. All the stable kernels (6.7.y
> and 6.8.y) work on the Orange Pi 5, which has the Rockchip RK3588S SoC
> (same as the RK3588, but less I/O basically). So, being an owner of
> only two SBCs which use the RK3588* SoC, it appears that the Rock 5
> Model B's DT is incorrect.
>
> I looked at the patch and tried several things, neither resulted in
> anything that would point me to the core issue. Then I tried this:
Could you, please, clarify a bit what's the actual issue you're
experiencing on your Rock 5B?
> ```
> $ grep -C 3 remote-endpoint
> arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
>
> port {
> es8316_p0_0: endpoint {
> remote-endpoint = <&i2s0_8ch_p0_0>;
> };
> };
> };
> --
> i2s0_8ch_p0_0: endpoint {
> dai-format = "i2s";
> mclk-fs = <256>;
> remote-endpoint = <&es8316_p0_0>;
> };
> };
> };
> ```
>
> So, from a cursory look, the issue seems to be related to either the
> DT node for the audio codec or related to the es8316's binding itself.
> Though I doubt that the later is the issue because if that were the
> issue, _someone_ with a Pine64 Pinebook Pro would've raised alarms. So
> far, this seems to be related to the `rk3588-rock-5b.dts` and possibly
> with the `rk3588s-rock-5a.dts` too.
>
> I would **love** to help but I'm afraid I device-trees are not
> something that I am at-all familiar with. That said, I am open to
> methods of debugging this issue to provide a fix myself.
>
> I would have replied to the patch's link but unfortunately, I haven't
> yet setup neomutt and my email provider's web UI doesn't have a
> [straightforward] way to reply using the 'In-Reply-To' header, hence a
> new thread. Apologies for the inconvenience caused.
>
> -- Pratham Patel
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: Fixing the devicetree of Rock 5 Model B (and possibly others)
From: Pratham Patel @ 2024-03-23 17:08 UTC (permalink / raw)
To: sebastian.reichel@collabora.com, saravanak@google.com
Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
regressions@lists.linux.dev, stable@vger.kernel.org
In-Reply-To: <tQ0L3-34g4t-mzfQIP6KDe5OYelGnEo6Udzq6Kb_nEcljppSQUXOktpE__nL-CdLOu9gW-4tIIbjtSbqrdCrjEkdhZLPiiHTqRcCB6WORuM=@thefossguy.com>
[-- Attachment #1.1.1: Type: text/plain, Size: 2170 bytes --]
Ugh, just now noticing that I forgot to send the boot log captured over UART and forgot to disable sending the pubkey as an attachment.
The word wrap is broken because of course the web UI isn't mindful of that.
Sorry!
-- Pratham Patel
On Saturday, March 23rd, 2024 at 22:32, Pratham Patel <prathampatel@thefossguy.com> wrote:
>
>
> Since the introduction of the `of: property: fw_devlink: Fix stupid bug in remote-endpoint parsing` patch, an issue with the device-tree of the Rock 5 Model B has been detected. All the stable kernels (6.7.y and 6.8.y) work on the Orange Pi 5, which has the Rockchip RK3588S SoC (same as the RK3588, but less I/O basically). So, being an owner of only two SBCs which use the RK3588* SoC, it appears that the Rock 5 Model B's DT is incorrect.
>
> I looked at the patch and tried several things, neither resulted in anything that would point me to the core issue. Then I tried this:
>
> ```
> $ grep -C 3 remote-endpoint arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
>
> port {
> es8316_p0_0: endpoint {
> remote-endpoint = <&i2s0_8ch_p0_0>;
>
> };
> };
> };
> --
> i2s0_8ch_p0_0: endpoint {
> dai-format = "i2s";
> mclk-fs = <256>;
>
> remote-endpoint = <&es8316_p0_0>;
>
> };
> };
> };
> ```
>
> So, from a cursory look, the issue seems to be related to either the DT node for the audio codec or related to the es8316's binding itself. Though I doubt that the later is the issue because if that were the issue, someone with a Pine64 Pinebook Pro would've raised alarms. So far, this seems to be related to the `rk3588-rock-5b.dts` and possibly with the `rk3588s-rock-5a.dts` too.
>
> I would love to help but I'm afraid I device-trees are not something that I am at-all familiar with. That said, I am open to methods of debugging this issue to provide a fix myself.
>
> I would have replied to the patch's link but unfortunately, I haven't yet setup neomutt and my email provider's web UI doesn't have a [straightforward] way to reply using the 'In-Reply-To' header, hence a new thread. Apologies for the inconvenience caused.
>
> -- Pratham Patel
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1.1.2: rock5b-boot.log --]
[-- Type: text/x-log; filename="rock5b-boot.log"; name="rock5b-boot.log", Size: 30299 bytes --]
\x1e\x1en/{24/02/04-10:09:20,fwver: v1.16
LPDDR4X, 2112MHz
channel[0] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=16 Size=4096MB
channel[1] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=16 Size=4096MB
channel[2] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=16 Size=4096MB
channel[3] BW=16 Col=10 Bk=8 CS0 Row=17 CS1 Row=17 CS=2 Die BW=16 Size=4096MB
Manufacturer ID:0xff
CH0 RX Vref:28.9%, TX Vref:21.8%,21.8%
CH1 RX Vref:28.9%, TX Vref:22.8%,23.8%
CH2 RX Vref:27.1%, TX Vref:22.8%,21.8%
CH3 RX Vref:26.7%, TX Vref:22.8%,21.8%
change to F1: 528MHz
change to F2: 1068MHz
change to F3: 1560MHz
change to F0: 2112MHz
out
U-Boot SPL 2024.01 (Jan 08 2024 - 15:37:48 +0000)
Trying to boot from SPI
## Checking hash(es) for config config-1 ... OK
## Checking hash(es) for Image atf-1 ... sha256+ OK
## Checking hash(es) for Image u-boot ... sha256+ OK
## Checking hash(es) for Image fdt-1 ... sha256+ OK
## Checking hash(es) for Image atf-2 ... sha256+ OK
NOTICE: BL31: v2.10.0 (release):
NOTICE: BL31: Built : 00:00:00, Jan 1 1980
U-Boot 2024.01 (Jan 08 2024 - 15:37:48 +0000)
Model: Radxa ROCK 5 Model B
DRAM: 16 GiB (effective 15.7 GiB)
Core: 761 devices, 30 uclasses, devicetree: separate
MMC: mmc@fe2c0000: 1, mmc@fe2d0000: 2, mmc@fe2e0000: 0
Loading Environment from nowhere... OK
In: serial@feb50000
Out: serial@feb50000
Err: serial@feb50000
Model: Radxa ROCK 5 Model B
Net: No ethernet found.
Hit any key to stop autoboot: 2 \b\b\b 1 \b\b\b 0
Card did not respond to voltage select! : -110
pcie_dw_rockchip pcie@fe170000: PCIe-4 Link Fail
** Booting bootflow 'nvme#0.blk#1.bootdev.part_1' with efi
^[7^[[r^[[999;999H^[[6n^[8Card did not respond to voltage select! : -110
Card did not respond to voltage select! : -110
Booting /efi\boot\bootaa64.efi
^[[?25l ^[[2J^[[1;1H^[[0;37;40m^[[2J^[[1;1H^[[12;23H^[[0;30;47m NixOS (Generation 84 NixOS Tapir 23.11.5541.56528ee42526 (Linux 6.7.7), built on 2024-03-23) ^[[13;23H^[[0;37;40m NixOS (Generation 83 NixOS Tapir 23.11.5541.56528ee42526 (Linux 6.8.1), built on 2024-03-23) ^[[14;23H^[[0;37;40m NixOS (Generation 82 NixOS Tapir 23.11.5511.f091af045dff (Linux 6.8.1), built on 2024-03-22) ^[[15;23H^[[0;37;40m NixOS (Generation 81 NixOS Tapir 23.11.5511.f091af045dff (Linux 6.8.1), built on 2024-03-22) ^[[16;23H^[[0;37;40m NixOS (Generation 80 NixOS Tapir 23.11.5511.f091af045dff (Linux 6.8.1), built on 2024-03-22) ^[[17;23H^[[0;37;40m NixOS (Generation 79 NixOS Tapir 23.11.5511.f091af045dff (Linux 6.8.1), built on 2024-03-22) ^[[18;23H^[[0;37;40m NixOS (Generation 78 NixOS Tapir 23.11.5511.f091af045dff (Linux 6.8.1), built on 2024-03-21) ^[[19;23H^[[0;37;40m NixOS (Generation 77 NixOS Tapir 23.11.5474.fa9f817df522 (Linux 6.7.8), built on 2024-03-21) ^[[20;23H^[[0;37;40m NixOS (Generation 76 NixOS Tapir 23.11.5441.614b4613980a (Linux 6.7.8), built on 2024-03-20) ^[[21;23H^[[0;37;40m NixOS (Generation 75 NixOS Tapir 23.11.5441.614b4613980a (Linux 6.7.8), built on 2024-03-20) ^[[22;23H^[[0;37;40m NixOS (Generation 74 NixOS Tapir 23.11.5441.614b4613980a (Linux 6.7.8), built on 2024-03-19) ^[[23;23H^[[0;37;40m NixOS (Generation 73 NixOS Tapir 23.11.5441.614b4613980a (Linux 6.7.8), built on 2024-03-19) ^[[24;23H^[[0;37;40m NixOS (Generation 72 NixOS Tapir 23.11.5441.614b4613980a (Linux 6.7.8), built on 2024-03-19) ^[[25;23H^[[0;37;40m NixOS (Generation 71 NixOS Tapir 23.11.5441.614b4613980a (Linux 6.7.8), built on 2024-03-19) ^[[26;23H^[[0;37;40m NixOS (Generation 70 NixOS Tapir 23.11.5441.614b4613980a (Linux 6.7.8), built on 2024-03-19) ^[[27;23H^[[0;37;40m NixOS (Generation 69 NixOS Tapir 23.11.5441.614b4613980a (Linux 6.7.8), built on 2024-03-18) ^[[28;23H^[[0;37;40m NixOS (Generation 68 NixOS Tapir 23.11.5441.614b4613980a (Linux 6.7.8), built on 2024-03-18) ^[[29;23H^[[0;37;40m NixOS (Generation 67 NixOS Tapir 23.11.5441.614b4613980a (Linux 6.8.1), built on 2024-03-18) ^[[30;23H^[[0;37;40m NixOS (Generation 66 NixOS Tapir 23.11.5441.614b4613980a (Linux 6.8.1), built on 2024-03-18) ^[[31;23H^[[0;37;40m NixOS (Generation 65 NixOS Tapir 23.11.5441.614b4613980a (Linux 6.7.8), built on 2024-03-18) ^[[33;1H^[[0;37;40m Boot in 5 s. ^[[32;20H^[[0;37;40m────────────────────────────────────────────────────────────────────────────────────────────────────────^[[12;23H^[[0;37;40m NixOS (Generation 84 NixOS Tapir 23.11.5541.56528ee42526 (Linux 6.7.7), built on 2024-03-23) ^[[13;23H^[[0;30;47m NixOS (Generation 83 NixOS Tapir 23.11.5541.56528ee42526 (Linux 6.8.1), built on 2024-03-23) ^[[32;1H^[[0;37;40m ^[[33;1H^[[0;37;40m ^[[13;23H^[[0;37;40m NixOS (Generation 83 NixOS Tapir 23.11.5541.56528ee42526 (Linux 6.8.1), built on 2024-03-23) ^[[14;23H^[[0;30;47m NixOS (Generation 82 NixOS Tapir 23.11.5511.f091af045dff (Linux 6.8.1), built on 2024-03-22) ^[[32;1H^[[0;37;40m ^[[33;1H^[[0;37;40m ^[[0;37;40m^[[2J^[[1;1HEFI stub: Booting Linux Kernel...
EFI stub: EFI_RNG_PROTOCOL unavailable
EFI stub: Loaded initrd from LINUX_EFI_INITRD_MEDIA_GUID device path
EFI stub: Using DTB from configuration table
EFI stub: Exiting boot services...
[ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
[ 0.000000] Linux version 6.8.1 (nixbld@localhost) (gcc (GCC) 12.3.0, GNU ld (GNU Binutils) 2.40) #1-NixOS SMP Fri Mar 22 07:27:36 UTC 2024
[ 0.000000] KASLR disabled due to lack of seed
[ 0.000000] Machine model: Radxa ROCK 5 Model B
[ 0.000000] printk: debug: ignoring loglevel setting.
[ 0.000000] efi: EFI v2.10 by Das U-Boot
[ 0.000000] efi: RTPROP=0xecba2040 SMBIOS=0xecbd6000 INITRD=0xec0bc040 MEMRESERVE=0xec0bb040
[ 0.000000] OF: reserved mem: 0x00000003fc000000..0x00000003fc4fffff (5120 KiB) nomap non-reusable gap1@3,fc000000
[ 0.000000] OF: reserved mem: 0x00000003fff00000..0x00000003ffffffff (1024 KiB) nomap non-reusable gap2@3,fff00000
[ 0.000000] NUMA: No NUMA configuration found
[ 0.000000] NUMA: Faking a node at [mem 0x0000000000200000-0x00000003ffffffff]
[ 0.000000] NUMA: NODE_DATA [mem 0x3fdea58c0-0x3fdea8fff]
[ 0.000000] Zone ranges:
[ 0.000000] DMA [mem 0x0000000000200000-0x00000000ffffffff]
[ 0.000000] DMA32 empty
[ 0.000000] Normal [mem 0x0000000100000000-0x00000003ffffffff]
[ 0.000000] Device empty
[ 0.000000] Movable zone start for each node
[ 0.000000] Early memory node ranges
[ 0.000000] node 0: [mem 0x0000000000200000-0x00000000ecba1fff]
[ 0.000000] node 0: [mem 0x00000000ecba2000-0x00000000ecba2fff]
[ 0.000000] node 0: [mem 0x00000000ecba3000-0x00000000ecba3fff]
[ 0.000000] node 0: [mem 0x00000000ecba4000-0x00000000ecbc5fff]
[ 0.000000] node 0: [mem 0x00000000ecbc6000-0x00000000ecbd5fff]
[ 0.000000] node 0: [mem 0x00000000ecbd6000-0x00000000ecbd6fff]
[ 0.000000] node 0: [mem 0x00000000ecbd7000-0x00000000efefffff]
[ 0.000000] node 0: [mem 0x00000000eff00000-0x00000000eff0ffff]
[ 0.000000] node 0: [mem 0x00000000eff10000-0x00000000efffffff]
[ 0.000000] node 0: [mem 0x0000000100000000-0x00000003fbffffff]
[ 0.000000] node 0: [mem 0x00000003fc000000-0x00000003fc4fffff]
[ 0.000000] node 0: [mem 0x00000003fc500000-0x00000003ffefffff]
[ 0.000000] node 0: [mem 0x00000003fff00000-0x00000003ffffffff]
[ 0.000000] Initmem setup node 0 [mem 0x0000000000200000-0x00000003ffffffff]
[ 0.000000] On node 0, zone DMA: 512 pages in unavailable ranges
[ 0.000000] cma: Reserved 32 MiB at 0x00000000ede00000 on node -1
[ 0.000000] psci: probing for conduit method from DT.
[ 0.000000] psci: PSCIv1.1 detected in firmware.
[ 0.000000] psci: Using standard PSCI v0.2 function IDs
[ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
[ 0.000000] psci: SMC Calling Convention v1.4
[ 0.000000] percpu: Embedded 53 pages/cpu s91112 r8192 d117784 u217088
[ 0.000000] pcpu-alloc: s91112 r8192 d117784 u217088 alloc=53*4096
[ 0.000000] pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 [0] 4 [0] 5 [0] 6 [0] 7
[ 0.000000] Detected VIPT I-cache on CPU0
[ 0.000000] CPU features: detected: GIC system register CPU interface
[ 0.000000] CPU features: detected: Virtualization Host Extensions
[ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
[ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
[ 0.000000] alternatives: applying boot alternatives
[ 0.000000] Kernel command line: initrd=\efi\nixos\pb837bxwkd30cqyh6m9cirkgf81ylmd8-initrd-linux-6.8.1-g488fc7ad2bc8-initrd.efi init=/nix/store/v00aha5h3cm5fi4d5ghm1mz5g4pjyxlv-nixos-system-mahadev-23.11.5511.f091af045dff/init audit=0 ignore_loglevel boot.shell_on_fail fsck.mode=auto fsck.repair=preen plymouth.enable=0 rd.plymouth=0 no_console_suspend loglevel=4 kvm-intel.vmentry_l1d_flush=always
[ 0.000000] audit: disabled (until reboot)
[ 0.000000] Dentry cache hash table entries: 2097152 (order: 12, 16777216 bytes, linear)
[ 0.000000] Inode-cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
[ 0.000000] Fallback order for Node 0: 0
[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 4063752
[ 0.000000] Policy zone: Normal
[ 0.000000] mem auto-init: stack:all(zero), heap alloc:off, heap free:off
[ 0.000000] software IO TLB: area num 8.
[ 0.000000] software IO TLB: mapped [mem 0x00000000e74e0000-0x00000000eb4e0000] (64MB)
[ 0.000000] Memory: 16013768K/16513024K available (22272K kernel code, 6394K rwdata, 21480K rodata, 14656K init, 1018K bss, 466488K reserved, 32768K cma-reserved)
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
[ 0.000000] ftrace: allocating 71385 entries in 279 pages
[ 0.000000] ftrace: allocated 279 pages with 5 groups
[ 0.000000] trace event string verifier disabled
[ 0.000000] rcu: Hierarchical RCU implementation.
[ 0.000000] rcu: RCU event tracing is enabled.
[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=384 to nr_cpu_ids=8.
[ 0.000000] Rude variant of Tasks RCU enabled.
[ 0.000000] Tracing variant of Tasks RCU enabled.
[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
[ 0.000000] GICv3: 480 SPIs implemented
[ 0.000000] GICv3: 0 Extended SPIs implemented
[ 0.000000] GICv3: MBI range [424:479]
[ 0.000000] GICv3: Using MBI frame 0x00000000fe610000
[ 0.000000] Root IRQ handler: gic_handle_irq
[ 0.000000] GICv3: GICv3 features: 16 PPIs
[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x00000000fe680000
[ 0.000000] ITS [mem 0xfe640000-0xfe65ffff]
[ 0.000000] GIC: enabling workaround for ITS: Rockchip erratum RK3588001
[ 0.000000] ITS@0x00000000fe640000: allocated 8192 Devices @1002d0000 (indirect, esz 8, psz 64K, shr 0)
[ 0.000000] ITS@0x00000000fe640000: allocated 32768 Interrupt Collections @1002e0000 (flat, esz 2, psz 64K, shr 0)
[ 0.000000] ITS: using cache flushing for cmd queue
[ 0.000000] ITS [mem 0xfe660000-0xfe67ffff]
[ 0.000000] GIC: enabling workaround for ITS: Rockchip erratum RK3588001
[ 0.000000] ITS@0x00000000fe660000: allocated 8192 Devices @100300000 (indirect, esz 8, psz 64K, shr 0)
[ 0.000000] ITS@0x00000000fe660000: allocated 32768 Interrupt Collections @100310000 (flat, esz 2, psz 64K, shr 0)
[ 0.000000] ITS: using cache flushing for cmd queue
[ 0.000000] GICv3: using LPI property table @0x0000000100320000
[ 0.000000] GIC: using cache flushing for LPI property table
[ 0.000000] GICv3: CPU0: using allocated LPI pending table @0x0000000100330000
[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
[ 0.000000] arch_timer: cp15 timer(s) running at 24.00MHz (phys).
[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x588fe9dc0, max_idle_ns: 440795202592 ns
[ 0.000000] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps every 4398046511097ns
[ 0.006274] Console: colour dummy device 80x25
[ 0.006287] printk: legacy console [tty0] enabled
[ 0.009265] Calibrating delay loop (skipped), value calculated using timer frequency.. 48.00 BogoMIPS (lpj=96000)
[ 0.009298] pid_max: default: 32768 minimum: 301
[ 0.013557] LSM: initializing lsm=capability,landlock,yama,bpf,integrity
[ 0.018396] landlock: Up and running.
[ 0.018413] Yama: becoming mindful.
[ 0.018454] LSM support for eBPF active
[ 0.019967] Mount-cache hash table entries: 32768 (order: 6, 262144 bytes, linear)
[ 0.020033] Mountpoint-cache hash table entries: 32768 (order: 6, 262144 bytes, linear)
[ 0.026493] RCU Tasks Rude: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1.
[ 0.026636] RCU Tasks Trace: Setting shift to 3 and lim to 1 rcu_task_cb_adjust=1.
[ 0.026994] rcu: Hierarchical SRCU implementation.
[ 0.027014] rcu: Max phase no-delay instances is 1000.
[ 0.028786] Platform MSI: msi-controller@fe640000 domain created
[ 0.028825] Platform MSI: msi-controller@fe660000 domain created
[ 0.029155] PCI/MSI: /interrupt-controller@fe600000/msi-controller@fe640000 domain created
[ 0.029202] PCI/MSI: /interrupt-controller@fe600000/msi-controller@fe660000 domain created
[ 0.029534] fsl-mc MSI: msi-controller@fe640000 domain created
[ 0.029570] fsl-mc MSI: msi-controller@fe660000 domain created
[ 0.039009] Remapping and enabling EFI services.
[ 0.039671] smp: Bringing up secondary CPUs ...
[ 0.040591] Detected VIPT I-cache on CPU1
[ 0.040665] GICv3: CPU1: found redistributor 100 region 0:0x00000000fe6a0000
[ 0.040680] GICv3: CPU1: using allocated LPI pending table @0x0000000100340000
[ 0.040731] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
[ 0.041704] Detected VIPT I-cache on CPU2
[ 0.041772] GICv3: CPU2: found redistributor 200 region 0:0x00000000fe6c0000
[ 0.041787] GICv3: CPU2: using allocated LPI pending table @0x0000000100350000
[ 0.041832] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
[ 0.042789] Detected VIPT I-cache on CPU3
[ 0.042858] GICv3: CPU3: found redistributor 300 region 0:0x00000000fe6e0000
[ 0.042872] GICv3: CPU3: using allocated LPI pending table @0x0000000100360000
[ 0.042915] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
[ 0.043846] CPU features: detected: Spectre-v4
[ 0.043851] CPU features: detected: Spectre-BHB
[ 0.043857] Detected PIPT I-cache on CPU4
[ 0.043899] GICv3: CPU4: found redistributor 400 region 0:0x00000000fe700000
[ 0.043908] GICv3: CPU4: using allocated LPI pending table @0x0000000100370000
[ 0.043937] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
[ 0.044815] Detected PIPT I-cache on CPU5
[ 0.044866] GICv3: CPU5: found redistributor 500 region 0:0x00000000fe720000
[ 0.044876] GICv3: CPU5: using allocated LPI pending table @0x0000000100380000
[ 0.044906] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
[ 0.045889] Detected PIPT I-cache on CPU6
[ 0.045937] GICv3: CPU6: found redistributor 600 region 0:0x00000000fe740000
[ 0.045947] GICv3: CPU6: using allocated LPI pending table @0x0000000100390000
[ 0.045976] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
[ 0.046821] Detected PIPT I-cache on CPU7
[ 0.046871] GICv3: CPU7: found redistributor 700 region 0:0x00000000fe760000
[ 0.046880] GICv3: CPU7: using allocated LPI pending table @0x00000001003a0000
[ 0.046909] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
[ 0.047032] smp: Brought up 1 node, 8 CPUs
[ 0.047326] SMP: Total of 8 processors activated.
[ 0.047339] CPU: All CPU(s) started at EL2
[ 0.047352] CPU features: detected: 32-bit EL0 Support
[ 0.047365] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
[ 0.047383] CPU features: detected: Common not Private translations
[ 0.047396] CPU features: detected: CRC32 instructions
[ 0.047413] CPU features: detected: RCpc load-acquire (LDAPR)
[ 0.047427] CPU features: detected: LSE atomic instructions
[ 0.047441] CPU features: detected: Privileged Access Never
[ 0.047454] CPU features: detected: RAS Extension Support
[ 0.047470] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
[ 0.047673] alternatives: applying system-wide alternatives
[ 0.053944] CPU features: detected: Hardware dirty bit management on CPU4-7
[ 0.059766] devtmpfs: initialized
[ 0.074402] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[ 0.074422] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
[ 0.076136] pinctrl core: initialized pinctrl subsystem
[ 0.078742] SMBIOS 3.0 present.
[ 0.078758] DMI: Unknown Unknown Product/Unknown Product, BIOS 2024.01 01/01/2024
[ 0.080100] NET: Registered PF_NETLINK/PF_ROUTE protocol family
[ 0.081023] DMA: preallocated 2048 KiB GFP_KERNEL pool for atomic allocations
[ 0.081356] DMA: preallocated 2048 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
[ 0.081563] DMA: preallocated 2048 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
[ 0.082309] thermal_sys: Registered thermal governor 'step_wise'
[ 0.082313] thermal_sys: Registered thermal governor 'power_allocator'
[ 0.082351] cpuidle: using governor ladder
[ 0.082370] cpuidle: using governor menu
[ 0.082721] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
[ 0.082872] ASID allocator initialised with 65536 entries
[ 0.085129] Serial: AMBA PL011 UART driver
[ 0.110076] gpio gpiochip0: Static allocation of GPIO base is deprecated, use dynamic allocation.
[ 0.110401] rockchip-gpio fd8a0000.gpio: probed /pinctrl/gpio@fd8a0000
[ 0.110601] gpio gpiochip1: Static allocation of GPIO base is deprecated, use dynamic allocation.
[ 0.110720] rockchip-gpio fec20000.gpio: probed /pinctrl/gpio@fec20000
[ 0.110885] gpio gpiochip2: Static allocation of GPIO base is deprecated, use dynamic allocation.
[ 0.111004] rockchip-gpio fec30000.gpio: probed /pinctrl/gpio@fec30000
[ 0.111217] gpio gpiochip3: Static allocation of GPIO base is deprecated, use dynamic allocation.
[ 0.111323] rockchip-gpio fec40000.gpio: probed /pinctrl/gpio@fec40000
[ 0.111491] gpio gpiochip4: Static allocation of GPIO base is deprecated, use dynamic allocation.
[ 0.111597] rockchip-gpio fec50000.gpio: probed /pinctrl/gpio@fec50000
[ 0.116146] platform fc000000.usb: Fixed dependency cycle(s) with /i2c@feac0000/usb-typec@22/connector
[ 0.117630] platform fed80000.phy: Fixed dependency cycle(s) with /i2c@feac0000/usb-typec@22/connector
[ 0.119097] Modules: 16256 pages in range for non-PLT usage
[ 0.119102] Modules: 507776 pages in range for PLT usage
[ 0.120107] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
[ 0.120123] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
[ 0.120131] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
[ 0.120137] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
[ 0.120144] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
[ 0.120150] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
[ 0.120156] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
[ 0.120161] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
[ 0.123530] fbcon: Taking over console
[ 0.123573] ACPI: Interpreter disabled.
[ 0.126163] iommu: Default domain type: Translated
[ 0.126175] iommu: DMA domain TLB invalidation policy: strict mode
[ 0.130680] SCSI subsystem initialized
[ 0.130835] libata version 3.00 loaded.
[ 0.130979] usbcore: registered new interface driver usbfs
[ 0.131004] usbcore: registered new interface driver hub
[ 0.131025] usbcore: registered new device driver usb
[ 0.132020] pps_core: LinuxPPS API ver. 1 registered
[ 0.132027] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[ 0.132047] PTP clock support registered
[ 0.132168] EDAC MC: Ver: 3.0.0
[ 0.132930] scmi_core: SCMI protocol bus registered
[ 0.133027] efivars: Registered efivars operations
[ 0.134140] FPGA manager framework
[ 0.134285] Advanced Linux Sound Architecture Driver Initialized.
[ 0.135019] vgaarb: loaded
[ 0.135858] clocksource: Switched to clocksource arch_sys_counter
[ 0.137405] VFS: Disk quotas dquot_6.6.0
[ 0.137567] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[ 0.137757] netfs: FS-Cache loaded
[ 0.137975] pnp: PnP ACPI: disabled
[ 0.144988] NET: Registered PF_INET protocol family
[ 0.145305] IP idents hash table entries: 262144 (order: 9, 2097152 bytes, linear)
[ 0.203655] tcp_listen_portaddr_hash hash table entries: 8192 (order: 5, 131072 bytes, linear)
[ 0.203797] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
[ 0.203840] TCP established hash table entries: 131072 (order: 8, 1048576 bytes, linear)
[ 0.204835] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
[ 0.206727] TCP: Hash tables configured (established 131072 bind 65536)
[ 0.207115] MPTCP token hash table entries: 16384 (order: 6, 393216 bytes, linear)
[ 0.207315] UDP hash table entries: 8192 (order: 6, 262144 bytes, linear)
[ 0.207682] UDP-Lite hash table entries: 8192 (order: 6, 262144 bytes, linear)
[ 0.208211] NET: Registered PF_UNIX/PF_LOCAL protocol family
[ 0.208778] RPC: Registered named UNIX socket transport module.
[ 0.208790] RPC: Registered udp transport module.
[ 0.208795] RPC: Registered tcp transport module.
[ 0.208801] RPC: Registered tcp-with-tls transport module.
[ 0.208806] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 0.208816] NET: Registered PF_XDP protocol family
[ 0.208830] PCI: CLS 0 bytes, default 64
[ 0.209128] Trying to unpack rootfs image as initramfs...
[ 0.216400] kvm [1]: IPA Size Limit: 40 bits
[ 0.216429] kvm [1]: GICv3: no GICV resource entry
[ 0.216436] kvm [1]: disabling GICv2 emulation
[ 0.216456] kvm [1]: GIC system register CPU interface enabled
[ 0.216479] kvm [1]: vgic interrupt IRQ18
[ 0.216512] kvm [1]: VHE mode initialized successfully
[ 0.217603] Initialise system trusted keyrings
[ 0.217785] workingset: timestamp_bits=42 max_order=22 bucket_order=0
[ 0.217821] zbud: loaded
[ 0.222723] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[ 0.224044] NFS: Registering the id_resolver key type
[ 0.224083] Key type id_resolver registered
[ 0.224088] Key type id_legacy registered
[ 0.224171] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
[ 0.224178] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
[ 0.224284] 9p: Installing v9fs 9p2000 file system support
[ 0.263496] Key type asymmetric registered
[ 0.263507] Asymmetric key parser 'x509' registered
[ 0.263557] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
[ 0.263784] io scheduler mq-deadline registered
[ 0.263792] io scheduler kyber registered
[ 0.286712] EINJ: ACPI disabled.
[ 0.301701] dma-pl330 fea10000.dma-controller: Loaded driver for PL330 DMAC-241330
[ 0.301720] dma-pl330 fea10000.dma-controller: DBUFF-128x8bytes Num_Chans-8 Num_Peri-32 Num_Events-16
[ 0.302585] dma-pl330 fea30000.dma-controller: Loaded driver for PL330 DMAC-241330
[ 0.302598] dma-pl330 fea30000.dma-controller: DBUFF-128x8bytes Num_Chans-8 Num_Peri-32 Num_Events-16
[ 0.303432] dma-pl330 fed10000.dma-controller: Loaded driver for PL330 DMAC-241330
[ 0.303442] dma-pl330 fed10000.dma-controller: DBUFF-128x8bytes Num_Chans-8 Num_Peri-32 Num_Events-16
[ 0.314949] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
[ 0.316893] feb50000.serial: ttyS2 at MMIO 0xfeb50000 (irq = 41, base_baud = 1500000) is a 16550A
[ 0.317022] printk: legacy console [ttyS2] enabled
[ 0.435225] Freeing initrd memory: 9992K
[ 0.436255] feb90000.serial: ttyS0 at MMIO 0xfeb90000 (irq = 42, base_baud = 1500000) is a 16550A
[ 0.468133] msm_serial: driver initialized
[ 0.468868] SuperH (H)SCI(F) driver initialized
[ 0.469477] STM32 USART driver initialized
[ 0.479642] loop: module loaded
[ 0.480709] megasas: 07.727.03.00-rc1
[ 0.484940] spi spi2.0: Fixed dependency cycle(s) with /spi@feb20000/pmic@0/regulators/dcdc-reg7
[ 0.485747] spi spi2.0: Fixed dependency cycle(s) with /spi@feb20000/pmic@0/dvs3-null-pins
[ 0.486475] spi spi2.0: Fixed dependency cycle(s) with /spi@feb20000/pmic@0/dvs2-null-pins
[ 0.487203] spi spi2.0: Fixed dependency cycle(s) with /spi@feb20000/pmic@0/dvs1-null-pins
[ 0.490237] tun: Universal TUN/TAP device driver, 1.6
[ 0.491652] thunder_xcv, ver 1.0
[ 0.491965] thunder_bgx, ver 1.0
[ 0.492259] nicpf, ver 1.0
[ 0.493567] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
[ 0.494202] hns3: Copyright (c) 2017 Huawei Corporation.
[ 0.494682] hclge is initializing
[ 0.495002] e1000: Intel(R) PRO/1000 Network Driver
[ 0.495430] e1000: Copyright (c) 1999-2006 Intel Corporation.
[ 0.495981] e1000e: Intel(R) PRO/1000 Network Driver
[ 0.496420] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
[ 0.496969] igb: Intel(R) Gigabit Ethernet Network Driver
[ 0.497445] igb: Copyright (c) 2007-2014 Intel Corporation.
[ 0.497972] igbvf: Intel(R) Gigabit Virtual Function Network Driver
[ 0.498522] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
[ 0.499328] sky2: driver version 1.30
[ 0.512741] usbcore: registered new interface driver usb-storage
[ 0.515759] i2c_dev: i2c /dev entries driver
[ 0.519486] platform fe470000.i2s: Fixed dependency cycle(s) with /i2c@fec90000/audio-codec@11
[ 0.519645] fan53555-regulator 0-0042: FAN53555 Option[10] Rev[1] Detected!
[ 0.520116] fan53555-regulator 0-0043: FAN53555 Option[10] Rev[1] Detected!
[ 0.520284] i2c 3-0011: Fixed dependency cycle(s) with /i2s@fe470000
[ 21.583850] rcu: INFO: rcu_sched self-detected stall on CPU
[ 21.584347] rcu: 4-....: (5248 ticks this GP) idle=68ac/1/0x4000000000000000 softirq=22/29 fqs=2625
[ 21.585154] rcu: (t=5250 jiffies g=-1151 q=98 ncpus=8)
[ 21.585618] CPU: 4 PID: 1 Comm: swapper/0 Not tainted 6.8.1 #1-NixOS
[ 21.586179] Hardware name: Unknown Unknown Product/Unknown Product, BIOS 2024.01 01/01/2024
[ 21.586910] pstate: 20400009 (nzCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[ 21.587523] pc : smp_call_function_many_cond+0x174/0x5f8
[ 21.587999] lr : smp_call_function_many_cond+0x134/0x5f8
[ 21.588470] sp : ffff8000840bb810
[ 21.588763] x29: ffff8000840bb810 x28: 0000000000000000 x27: 0000000000000005
[ 21.589396] x26: ffff0003fde0e7e0 x25: ffff80008393ece0 x24: 0000000000000008
[ 21.590027] x23: 0000000000000001 x22: 0000000000000001 x21: ffff0003fddcfd08
[ 21.590657] x20: ffff8000839431d8 x19: ffff0003fddcfd00 x18: 0000000000000014
[ 21.591288] x17: 00000000bf994921 x16: 000000009a336ddc x15: 00000000013520bf
[ 21.591918] x14: 0000000000000000 x13: 0000000000000008 x12: 0101010101010101
[ 21.592549] x11: 7f7f7f7f7f7f7f7f x10: ffff8400843d0417 x9 : ffff800080809060
[ 21.593179] x8 : ffff0003fddcfd40 x7 : 0000000000000000 x6 : 0000000000000004
[ 21.593808] x5 : ffff80008393e000 x4 : 0000000000000005 x3 : ffff0003fde0e7e8
[ 21.594438] x2 : 0000000000000000 x1 : 0000000000000011 x0 : 0000000000000005
[ 21.595068] Call trace:
[ 21.595288] smp_call_function_many_cond+0x174/0x5f8
[ 21.595728] on_each_cpu_cond_mask+0x2c/0x40
[ 21.596109] cpuidle_register_driver+0x294/0x318
[ 21.596524] cpuidle_register+0x24/0x100
[ 21.596875] psci_cpuidle_probe+0x2e4/0x490
[ 21.597247] platform_probe+0x70/0xd0
[ 21.597575] really_probe+0x18c/0x3d8
[ 21.597905] __driver_probe_device+0x84/0x180
[ 21.598294] driver_probe_device+0x44/0x120
[ 21.598669] __device_attach_driver+0xc4/0x168
[ 21.599063] bus_for_each_drv+0x8c/0xf0
[ 21.599408] __device_attach+0xa4/0x1c0
[ 21.599748] device_initial_probe+0x1c/0x30
[ 21.600118] bus_probe_device+0xb4/0xc0
[ 21.600462] device_add+0x68c/0x888
[ 21.600775] platform_device_add+0x19c/0x270
[ 21.601154] platform_device_register_full+0xdc/0x178
[ 21.601602] psci_idle_init+0xa0/0xc8
[ 21.601934] do_one_initcall+0x60/0x290
[ 21.602275] kernel_init_freeable+0x20c/0x3e0
[ 21.602664] kernel_init+0x2c/0x1f8
[ 21.602979] ret_from_fork+0x10/0x20
[ 21.603299] Sending NMI from CPU 4 to CPUs 5:
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^ permalink raw reply
* Fixing the devicetree of Rock 5 Model B (and possibly others)
From: Pratham Patel @ 2024-03-23 17:02 UTC (permalink / raw)
To: sebastian.reichel@collabora.com, saravanak@google.com
Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
regressions@lists.linux.dev, stable@vger.kernel.org
[-- Attachment #1.1.1: Type: text/plain, Size: 1961 bytes --]
Since the introduction of the `of: property: fw_devlink: Fix stupid bug in remote-endpoint parsing` patch, an issue with the device-tree of the Rock 5 Model B has been detected. All the stable kernels (6.7.y and 6.8.y) work on the Orange Pi 5, which has the Rockchip RK3588S SoC (same as the RK3588, but less I/O basically). So, being an owner of only two SBCs which use the RK3588* SoC, it appears that the Rock 5 Model B's DT is incorrect.
I looked at the patch and tried several things, neither resulted in anything that would point me to the core issue. Then I tried this:
```
$ grep -C 3 remote-endpoint arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
port {
es8316_p0_0: endpoint {
remote-endpoint = <&i2s0_8ch_p0_0>;
};
};
};
--
i2s0_8ch_p0_0: endpoint {
dai-format = "i2s";
mclk-fs = <256>;
remote-endpoint = <&es8316_p0_0>;
};
};
};
```
So, from a cursory look, the issue seems to be related to either the DT node for the audio codec or related to the es8316's binding itself. Though I doubt that the later is the issue because if that were the issue, _someone_ with a Pine64 Pinebook Pro would've raised alarms. So far, this seems to be related to the `rk3588-rock-5b.dts` and possibly with the `rk3588s-rock-5a.dts` too.
I would **love** to help but I'm afraid I device-trees are not something that I am at-all familiar with. That said, I am open to methods of debugging this issue to provide a fix myself.
I would have replied to the patch's link but unfortunately, I haven't yet setup neomutt and my email provider's web UI doesn't have a [straightforward] way to reply using the 'In-Reply-To' header, hence a new thread. Apologies for the inconvenience caused.
-- Pratham Patel
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^ permalink raw reply
* Re: [WIP 0/3] Memory model and atomic API in Rust
From: Boqun Feng @ 2024-03-23 14:55 UTC (permalink / raw)
To: Andrew Lunn
Cc: Kent Overstreet, rust-for-linux, linux-kernel, linux-arch, llvm,
Miguel Ojeda, Alex Gaynor, Wedson Almeida Filho, Gary Guo,
Björn Roy Baron, Benno Lossin, Andreas Hindborg, Alice Ryhl,
Alan Stern, Andrea Parri, Will Deacon, Peter Zijlstra,
Nicholas Piggin, David Howells, Jade Alglave, Luc Maranget,
Paul E. McKenney, Akira Yokosawa, Daniel Lustig, Joel Fernandes,
Nathan Chancellor, Nick Desaulniers, kent.overstreet,
Greg Kroah-Hartman, elver, Mark Rutland, Thomas Gleixner,
Ingo Molnar, Borislav Petkov, Dave Hansen, x86, H. Peter Anvin,
Catalin Marinas, torvalds, linux-arm-kernel, linux-fsdevel
In-Reply-To: <Zf7qGONJY33KdLCH@Boquns-Mac-mini.home>
On Sat, Mar 23, 2024 at 07:41:28AM -0700, Boqun Feng wrote:
> On Sat, Mar 23, 2024 at 03:29:11PM +0100, Andrew Lunn wrote:
> > > There are also issues like where one Rust thread does a store(..,
> > > RELEASE), and a C thread does a rcu_deference(), in practice, it
> > > probably works but no one works out (and no one would work out) a model
> > > to describe such an interaction.
> >
> > Isn't that what Paul E. McKenney litmus tests are all about?
> >
>
> Litmus tests (or herd, or any other memory model tools) works for either
> LKMM or C++ memory model. But there is no model I'm aware of works for
> the communication between two memory models. So for example:
>
> Rust thread:
>
> let mut foo: Box<Foo> = ...;
> foo.a = 1;
> let global_ptr: &AtomicPtr = ...;
> global_ptr.store(foo.leak() as _, RELEASE);
>
>
> C thread:
>
> rcu_read_lock();
>
> foo = rcu_dereference(global_ptr);
> if (foo) {
> r1 = foo->a;
> }
>
> rcu_read_unlock();
>
> no tool or model yet to guarantee "r1" is 1, but yeah, in practice for
> the case we care, it's probably guaranteed. But no tool or model means
> challenging for code reasoning.
>
There are also cases where two similar APIs from C++ memory model and
LKMM have different semantics, for example, a SeqCst atomic in C++
memory model doesn't imply a full barrier, while a fully ordered LKMM
atomic does:
Rust:
a.store(1, RELAXED);
x.fetch_add(1, SeqCst);
b.store(2, RELAXED);
// ^ writes to a and b are not ordered.
C:
WRITE_ONCE(*a, 1);
atomic_fetch_add(x, 1);
WRITE_ONCE(*b, 2);
// ^ writes to a and b are ordered.
So if you used to have two parts synchronizing each other with LKMM
atomics, converting one side to Rust *and* using Rust atomics requires
much caution.
Regards,
Boqun
> Regards,
> Boqun
>
> > tools/memory-model/litmus-test
> >
> > Andrew
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^ permalink raw reply
* Re: [WIP 0/3] Memory model and atomic API in Rust
From: Boqun Feng @ 2024-03-23 14:41 UTC (permalink / raw)
To: Andrew Lunn
Cc: Kent Overstreet, rust-for-linux, linux-kernel, linux-arch, llvm,
Miguel Ojeda, Alex Gaynor, Wedson Almeida Filho, Gary Guo,
Björn Roy Baron, Benno Lossin, Andreas Hindborg, Alice Ryhl,
Alan Stern, Andrea Parri, Will Deacon, Peter Zijlstra,
Nicholas Piggin, David Howells, Jade Alglave, Luc Maranget,
Paul E. McKenney, Akira Yokosawa, Daniel Lustig, Joel Fernandes,
Nathan Chancellor, Nick Desaulniers, kent.overstreet,
Greg Kroah-Hartman, elver, Mark Rutland, Thomas Gleixner,
Ingo Molnar, Borislav Petkov, Dave Hansen, x86, H. Peter Anvin,
Catalin Marinas, torvalds, linux-arm-kernel, linux-fsdevel
In-Reply-To: <03f629b6-1e4e-4689-9b69-db0b75577822@lunn.ch>
On Sat, Mar 23, 2024 at 03:29:11PM +0100, Andrew Lunn wrote:
> > There are also issues like where one Rust thread does a store(..,
> > RELEASE), and a C thread does a rcu_deference(), in practice, it
> > probably works but no one works out (and no one would work out) a model
> > to describe such an interaction.
>
> Isn't that what Paul E. McKenney litmus tests are all about?
>
Litmus tests (or herd, or any other memory model tools) works for either
LKMM or C++ memory model. But there is no model I'm aware of works for
the communication between two memory models. So for example:
Rust thread:
let mut foo: Box<Foo> = ...;
foo.a = 1;
let global_ptr: &AtomicPtr = ...;
global_ptr.store(foo.leak() as _, RELEASE);
C thread:
rcu_read_lock();
foo = rcu_dereference(global_ptr);
if (foo) {
r1 = foo->a;
}
rcu_read_unlock();
no tool or model yet to guarantee "r1" is 1, but yeah, in practice for
the case we care, it's probably guaranteed. But no tool or model means
challenging for code reasoning.
Regards,
Boqun
> tools/memory-model/litmus-test
>
> Andrew
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^ permalink raw reply
* Re: [PATCH v3 1/5] dt-bindings: mfd: Add rk816 binding
From: Krzysztof Kozlowski @ 2024-03-23 14:32 UTC (permalink / raw)
To: Alex Bee, Lee Jones, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Heiko Stuebner, Linus Walleij, Liam Girdwood,
Mark Brown
Cc: Chris Zhong, Zhang Qing, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, linux-gpio
In-Reply-To: <20240323132757.141861-4-knaerzche@gmail.com>
On 23/03/2024 14:27, Alex Bee wrote:
> Add DT binding document for Rockchip's RK816 PMIC
>
> Signed-off-by: Alex Bee <knaerzche@gmail.com>
> + regulators:
> + type: object
> + patternProperties:
> + '^(boost|dcdc[1-4]|ldo[1-6]|otg-switch)$':
> + type: object
> + $ref: /schemas/regulator/regulator.yaml#
> + unevaluatedProperties: false
This is good.
> + unevaluatedProperties: false
I missed it last time, apologies. This (second) unevaluated should be
"additionalProperties: false" instead.
With this fixed:
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
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^ permalink raw reply
* Re: [WIP 0/3] Memory model and atomic API in Rust
From: Andrew Lunn @ 2024-03-23 14:29 UTC (permalink / raw)
To: Boqun Feng
Cc: Kent Overstreet, rust-for-linux, linux-kernel, linux-arch, llvm,
Miguel Ojeda, Alex Gaynor, Wedson Almeida Filho, Gary Guo,
Björn Roy Baron, Benno Lossin, Andreas Hindborg, Alice Ryhl,
Alan Stern, Andrea Parri, Will Deacon, Peter Zijlstra,
Nicholas Piggin, David Howells, Jade Alglave, Luc Maranget,
Paul E. McKenney, Akira Yokosawa, Daniel Lustig, Joel Fernandes,
Nathan Chancellor, Nick Desaulniers, kent.overstreet,
Greg Kroah-Hartman, elver, Mark Rutland, Thomas Gleixner,
Ingo Molnar, Borislav Petkov, Dave Hansen, x86, H. Peter Anvin,
Catalin Marinas, torvalds, linux-arm-kernel, linux-fsdevel
In-Reply-To: <Zf4fDJNBeRN5HOYo@boqun-archlinux>
> There are also issues like where one Rust thread does a store(..,
> RELEASE), and a C thread does a rcu_deference(), in practice, it
> probably works but no one works out (and no one would work out) a model
> to describe such an interaction.
Isn't that what Paul E. McKenney litmus tests are all about?
tools/memory-model/litmus-test
Andrew
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^ permalink raw reply
* Re: [WIP 1/3] rust: Introduce atomic module
From: Andrew Lunn @ 2024-03-23 14:10 UTC (permalink / raw)
To: Alice Ryhl
Cc: Boqun Feng, rust-for-linux, linux-kernel, linux-arch, llvm,
Miguel Ojeda, Alex Gaynor, Wedson Almeida Filho, Gary Guo,
Björn Roy Baron, Benno Lossin, Andreas Hindborg, Alan Stern,
Andrea Parri, Will Deacon, Peter Zijlstra, Nicholas Piggin,
David Howells, Jade Alglave, Luc Maranget, Paul E. McKenney,
Akira Yokosawa, Daniel Lustig, Joel Fernandes, Nathan Chancellor,
Nick Desaulniers, kent.overstreet, Greg Kroah-Hartman, elver,
Mark Rutland, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
Dave Hansen, x86, H. Peter Anvin, Catalin Marinas, torvalds,
linux-arm-kernel, linux-fsdevel
In-Reply-To: <CAH5fLggdVDccDwBa3z+3YfjKFLegh7ZvcSzfhnEbAGSk=THKrw@mail.gmail.com>
On Sat, Mar 23, 2024 at 10:58:16AM +0100, Alice Ryhl wrote:
> On Sat, Mar 23, 2024 at 12:52 AM Andrew Lunn <andrew@lunn.ch> wrote:
> >
> > > +//! These primitives should have the same semantics as their C counterparts, for precise definitions
> > > +//! of the semantics, please refer to tools/memory-model. Note that Linux Kernel Memory
> > > +//! (Consistency) Model is the only model for Rust development in kernel right now, please avoid to
> > > +//! use Rust's own atomics.
> >
> > Is it possible to somehow poison rusts own atomics? I would not be
> > too surprised if somebody with good Rust knowledge but new to the
> > kernel tries using Rusts atomics. Either getting the compiler to fail
> > the build, or it throws an Opps on first invocation would be good.
>
> We could try to get a flag added to the Rust standard library that
> removes the core::sync::atomic module entirely, then pass that flag.
Just looking down the road a bit, are there other features in the
standard library which are not applicable to Linux kernel space?
Ideally we want a solution not just for atomics but a generic solution
which can disable a collection of features? Maybe one by one?
And i assume somebody will try to use Rust in uboot/barebox. It
probably has similar requirements to the Linux kernel? But what about
Zephyr? Or VxWorks? Darwin?
Andrew
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^ permalink raw reply
* [PATCH] iommu/arm-smmu-v3: Fix access for STE.SHCFG
From: Mostafa Saleh @ 2024-03-23 13:46 UTC (permalink / raw)
To: will, robin.murphy, linux-arm-kernel, iommu
Cc: linux-kernel, joro, jgg, nicolinc, mshavit, Mostafa Saleh
STE attributes(NSCFG, PRIVCFG, INSTCFG) use value 0 for "Use Icomming",
for some reason SHCFG doesn't follow that, and it is defined as "0b01".
Currently the driver sets SHCFG to Use Incoming for stage-2 and bypass
domains.
However according to the User Manual (ARM IHI 0070 F.b):
When SMMU_IDR1.ATTR_TYPES_OVR == 0, this field is RES0 and the
incoming Shareability attribute is used.
This patch adds a condition for writing SHCFG to Use incoming to be
compliant with the architecture, and defines ATTR_TYPE_OVR as a new
feature discovered from IDR1.
This also required to propagate the SMMU through some functions args.
There is no need to add similar condition for the newly introduced function
arm_smmu_get_ste_used() as the values of the STE are the same before and
after any transition, so this will not trigger any change. (we already
do the same for the VMID).
Although this is a misconfiguration from the driver, this has been there
for a long time, so probably no HW running Linux is affected by it.
Reported-by: Will Deacon <will@kernel.org>
Closes: https://lore.kernel.org/all/20240215134952.GA690@willie-the-truck/
Signed-off-by: Mostafa Saleh <smostafa@google.com>
---
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 35 ++++++++++++++-------
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 2 ++
2 files changed, 25 insertions(+), 12 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
index 5ed036225e69..67149fe68199 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
@@ -1453,14 +1453,17 @@ static void arm_smmu_make_abort_ste(struct arm_smmu_ste *target)
FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_ABORT));
}
-static void arm_smmu_make_bypass_ste(struct arm_smmu_ste *target)
+static void arm_smmu_make_bypass_ste(struct arm_smmu_device *smmu,
+ struct arm_smmu_ste *target)
{
memset(target, 0, sizeof(*target));
target->data[0] = cpu_to_le64(
STRTAB_STE_0_V |
FIELD_PREP(STRTAB_STE_0_CFG, STRTAB_STE_0_CFG_BYPASS));
- target->data[1] = cpu_to_le64(
- FIELD_PREP(STRTAB_STE_1_SHCFG, STRTAB_STE_1_SHCFG_INCOMING));
+
+ if (smmu->features & ARM_SMMU_FEAT_ATTR_TYPES_OVR)
+ target->data[1] = cpu_to_le64(FIELD_PREP(STRTAB_STE_1_SHCFG,
+ STRTAB_STE_1_SHCFG_INCOMING));
}
static void arm_smmu_make_cdtable_ste(struct arm_smmu_ste *target,
@@ -1523,6 +1526,7 @@ static void arm_smmu_make_s2_domain_ste(struct arm_smmu_ste *target,
typeof(&pgtbl_cfg->arm_lpae_s2_cfg.vtcr) vtcr =
&pgtbl_cfg->arm_lpae_s2_cfg.vtcr;
u64 vtcr_val;
+ struct arm_smmu_device *smmu = master->smmu;
memset(target, 0, sizeof(*target));
target->data[0] = cpu_to_le64(
@@ -1531,9 +1535,11 @@ static void arm_smmu_make_s2_domain_ste(struct arm_smmu_ste *target,
target->data[1] = cpu_to_le64(
FIELD_PREP(STRTAB_STE_1_EATS,
- master->ats_enabled ? STRTAB_STE_1_EATS_TRANS : 0) |
- FIELD_PREP(STRTAB_STE_1_SHCFG,
- STRTAB_STE_1_SHCFG_INCOMING));
+ master->ats_enabled ? STRTAB_STE_1_EATS_TRANS : 0));
+
+ if (smmu->features & ARM_SMMU_FEAT_ATTR_TYPES_OVR)
+ target->data[1] |= cpu_to_le64(FIELD_PREP(STRTAB_STE_1_SHCFG,
+ STRTAB_STE_1_SHCFG_INCOMING));
vtcr_val = FIELD_PREP(STRTAB_STE_2_VTCR_S2T0SZ, vtcr->tsz) |
FIELD_PREP(STRTAB_STE_2_VTCR_S2SL0, vtcr->sl) |
@@ -1560,7 +1566,8 @@ static void arm_smmu_make_s2_domain_ste(struct arm_smmu_ste *target,
* This can safely directly manipulate the STE memory without a sync sequence
* because the STE table has not been installed in the SMMU yet.
*/
-static void arm_smmu_init_initial_stes(struct arm_smmu_ste *strtab,
+static void arm_smmu_init_initial_stes(struct arm_smmu_device *smmu,
+ struct arm_smmu_ste *strtab,
unsigned int nent)
{
unsigned int i;
@@ -1569,7 +1576,7 @@ static void arm_smmu_init_initial_stes(struct arm_smmu_ste *strtab,
if (disable_bypass)
arm_smmu_make_abort_ste(strtab);
else
- arm_smmu_make_bypass_ste(strtab);
+ arm_smmu_make_bypass_ste(smmu, strtab);
strtab++;
}
}
@@ -1597,7 +1604,7 @@ static int arm_smmu_init_l2_strtab(struct arm_smmu_device *smmu, u32 sid)
return -ENOMEM;
}
- arm_smmu_init_initial_stes(desc->l2ptr, 1 << STRTAB_SPLIT);
+ arm_smmu_init_initial_stes(smmu, desc->l2ptr, 1 << STRTAB_SPLIT);
arm_smmu_write_strtab_l1_desc(strtab, desc);
return 0;
}
@@ -2637,8 +2644,9 @@ static int arm_smmu_attach_dev_identity(struct iommu_domain *domain,
struct device *dev)
{
struct arm_smmu_ste ste;
+ struct arm_smmu_master *master = dev_iommu_priv_get(dev);
- arm_smmu_make_bypass_ste(&ste);
+ arm_smmu_make_bypass_ste(master->smmu, &ste);
return arm_smmu_attach_dev_ste(dev, &ste);
}
@@ -3264,7 +3272,7 @@ static int arm_smmu_init_strtab_linear(struct arm_smmu_device *smmu)
reg |= FIELD_PREP(STRTAB_BASE_CFG_LOG2SIZE, smmu->sid_bits);
cfg->strtab_base_cfg = reg;
- arm_smmu_init_initial_stes(strtab, cfg->num_l1_ents);
+ arm_smmu_init_initial_stes(smmu, strtab, cfg->num_l1_ents);
return 0;
}
@@ -3777,6 +3785,9 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu)
return -ENXIO;
}
+ if (reg & IDR1_ATTR_TYPES_OVR)
+ smmu->features |= ARM_SMMU_FEAT_ATTR_TYPES_OVR;
+
/* Queue sizes, capped to ensure natural alignment */
smmu->cmdq.q.llq.max_n_shift = min_t(u32, CMDQ_MAX_SZ_SHIFT,
FIELD_GET(IDR1_CMDQS, reg));
@@ -3992,7 +4003,7 @@ static void arm_smmu_rmr_install_bypass_ste(struct arm_smmu_device *smmu)
* STE table is not programmed to HW, see
* arm_smmu_initial_bypass_stes()
*/
- arm_smmu_make_bypass_ste(
+ arm_smmu_make_bypass_ste(smmu,
arm_smmu_get_step_for_sid(smmu, rmr->sids[i]));
}
}
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
index 23baf117e7e4..2a19bb63e5c6 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
@@ -44,6 +44,7 @@
#define IDR1_TABLES_PRESET (1 << 30)
#define IDR1_QUEUES_PRESET (1 << 29)
#define IDR1_REL (1 << 28)
+#define IDR1_ATTR_TYPES_OVR (1 << 27)
#define IDR1_CMDQS GENMASK(25, 21)
#define IDR1_EVTQS GENMASK(20, 16)
#define IDR1_PRIQS GENMASK(15, 11)
@@ -647,6 +648,7 @@ struct arm_smmu_device {
#define ARM_SMMU_FEAT_SVA (1 << 17)
#define ARM_SMMU_FEAT_E2H (1 << 18)
#define ARM_SMMU_FEAT_NESTING (1 << 19)
+#define ARM_SMMU_FEAT_ATTR_TYPES_OVR (1 << 20)
u32 features;
#define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0)
--
2.44.0.396.g6e790dbe36-goog
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^ permalink raw reply related
* Re: [PATCH v5 00/27] Update SMMUv3 to the modern iommu API (part 2/3)
From: Mostafa Saleh @ 2024-03-23 13:38 UTC (permalink / raw)
To: Jason Gunthorpe
Cc: iommu, Joerg Roedel, linux-arm-kernel, Robin Murphy, Will Deacon,
Eric Auger, Jean-Philippe Brucker, Moritz Fischer, Michael Shavit,
Nicolin Chen, patches, Shameerali Kolothum Thodi
In-Reply-To: <0-v5-9a37e0c884ce+31e3-smmuv3_newapi_p2_jgg@nvidia.com>
Hi Jason,
On Mon, Mar 04, 2024 at 07:43:48PM -0400, Jason Gunthorpe wrote:
> Continuing the work of part 1 this focuses on the CD, PASID and SVA
> components:
>
> - attach_dev failure does not change the HW configuration.
>
> - Full PASID API support including:
> - S1/SVA domains attached to PASIDs
I am still going through the series, but I see at the end the main SMMUv3
driver has set_dev_pasid operation, are there any in-tree drivers that
use that? (and how can I test it).
> - IDENTITY/BLOCKED/S1 attached to RID
> - Change of the RID domain while PASIDs are attached
>
> - Streamlined SVA support using the core infrastructure
>
> - Hitless, whenever possible, change between two domains
Can you please clarify what cases are expected to be hitless?
From what I see if ASID and TTB0 changes that would break the CD.
>
> Making the CD programming work like the new STE programming allows
> untangling some of the confusing SVA flows. From there the focus is on
> building out the core infrastructure for dealing with PASID and CD
> entries, then keeping track of unique SSID's for ATS invalidation.
>
> The ATS ordering is generalized so that the PASID flow can use it and put
> into a form where it is fully hitless, whenever possible. Care is taken to
> ensure that ATC flushes are present after any change in translation.
>
> Finally we simply kill the entire outdated SVA mmu_notifier implementation
> in one shot and switch it over to the newly created generic PASID & CD
> code. This avoids the messy and confusing approach of trying to
> incrementally untangle this in place. The new code is small and simple
> enough this is much better than trying to figure out smaller steps.
>
> Once SVA is resting on the right CD code it is straightforward to make the
> PASID interface functionally complete.
>
> It achieves the same goals as the several series from Michael and the S1DSS
> series from Nicolin that were trying to improve portions of the API.
>
> This is on github:
> https://github.com/jgunthorpe/linux/commits/smmuv3_newapi
>
> v5:
> - Rebase on v6.8-rc7 & Will's tree
> - Accomdate the SVA rc patch removing the master list iteration
> - Move the kfree(to_smmu_domain(domain)) hunk to the right patch
> - Move S1DSS get_used hunk to "Allow IDENTITY/BLOCKED to be set while
> PASID is used"
> v4: https://lore.kernel.org/r/0-v4-e7091cdd9e8d+43b1-smmuv3_newapi_p2_jgg@nvidia.com
> - Rebase on v6.8-rc1, adjust to use mm_get_enqcmd_pasid() and eventually
> remove all references from ARM. Move the new ARM_SMMU_FEAT_STALL_FORCE
> stuff to arm_smmu_make_sva_cd()
> - Adjust to use the new shared STE/CD writer logic. Disable some of the
> sanity checks for the interior of the series
> - Return ERR_PTR from domain_alloc functions
> - Move the ATS disablement flow into arm_smmu_attach_prepare()/commit()
> which lets all the STE update flows use the same sequence. This is
> needed for nesting in part 3
> - Put ssid in attach_state
> - Replace to_smmu_domain_safe() with to_smmu_domain_devices()
> v3: https://lore.kernel.org/r/0-v3-9083a9368a5c+23fb-smmuv3_newapi_p2_jgg@nvidia.com
> - Rebase on the latest part 1
> - update comments and commit messages
> - Fix error exit in arm_smmu_set_pasid()
> - Fix inverted logic for btm_invalidation
> - Add missing ATC invalidation on mm release
> - Add a big comment explaining that BTM is not enabled and what is
> missing to enable it.
> v2: https://lore.kernel.org/r/0-v2-16665a652079+5947-smmuv3_newapi_p2_jgg@nvidia.com
> - Rebased on iommmufd + Joerg's tree
> - Use sid_smmu_domain consistently to refer to the domain attached to the
> device (eg the PCIe RID)
> - Rework how arm_smmu_attach_*() and callers flow to be more careful
> about ordering around ATC invalidation. The ATC must be invalidated
> after it is impossible to establish stale entires.
> - ATS disable is now entirely part of arm_smmu_attach_dev_ste(), which is
> the only STE type that ever disables ATS.
> - Remove the 'existing_master_domain' optimization, the code is
> functionally fine without it.
> - Whitespace, spelling, and checkpatch related items
> - Fixed wrong value stored in the xa for the BTM flows
> - Use pasid more consistently instead of id
> v1: https://lore.kernel.org/r/0-v1-afbb86647bbd+5-smmuv3_newapi_p2_jgg@nvidia.com
>
> Jason Gunthorpe (27):
> iommu/arm-smmu-v3: Do not allow a SVA domain to be set on the wrong
> PASID
> iommu/arm-smmu-v3: Do not ATC invalidate the entire domain
> iommu/arm-smmu-v3: Add a type for the CD entry
> iommu/arm-smmu-v3: Add an ops indirection to the STE code
> iommu/arm-smmu-v3: Make CD programming use arm_smmu_write_entry()
> iommu/arm-smmu-v3: Consolidate clearing a CD table entry
> iommu/arm-smmu-v3: Move the CD generation for S1 domains into a
> function
> iommu/arm-smmu-v3: Move allocation of the cdtable into
> arm_smmu_get_cd_ptr()
> iommu/arm-smmu-v3: Allocate the CD table entry in advance
> iommu/arm-smmu-v3: Move the CD generation for SVA into a function
> iommu/arm-smmu-v3: Build the whole CD in arm_smmu_make_s1_cd()
> iommu/arm-smmu-v3: Start building a generic PASID layer
> iommu/arm-smmu-v3: Make smmu_domain->devices into an allocated list
> iommu/arm-smmu-v3: Make changing domains be hitless for ATS
> iommu/arm-smmu-v3: Add ssid to struct arm_smmu_master_domain
> iommu/arm-smmu-v3: Keep track of valid CD entries in the cd_table
> iommu/arm-smmu-v3: Thread SSID through the arm_smmu_attach_*()
> interface
> iommu/arm-smmu-v3: Make SVA allocate a normal arm_smmu_domain
> iommu/arm-smmu-v3: Keep track of arm_smmu_master_domain for SVA
> iommu: Add ops->domain_alloc_sva()
> iommu/arm-smmu-v3: Put the SVA mmu notifier in the smmu_domain
> iommu/arm-smmu-v3: Consolidate freeing the ASID/VMID
> iommu/arm-smmu-v3: Move the arm_smmu_asid_xa to per-smmu like vmid
> iommu/arm-smmu-v3: Bring back SVA BTM support
> iommu/arm-smmu-v3: Allow IDENTITY/BLOCKED to be set while PASID is
> used
> iommu/arm-smmu-v3: Allow a PASID to be set when RID is
> IDENTITY/BLOCKED
> iommu/arm-smmu-v3: Allow setting a S1 domain to a PASID
>
> .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 639 +++++-----
> drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 1036 +++++++++++------
> drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 79 +-
> drivers/iommu/iommu-sva.c | 4 +-
> drivers/iommu/iommu.c | 12 +-
> include/linux/iommu.h | 3 +
> 6 files changed, 1024 insertions(+), 749 deletions(-)
>
>
> base-commit: 98b23ebb0c84657a135957d727eedebd1280cbbf
> --
> 2.43.2
>
Thansks,
Mostafa
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^ permalink raw reply
* [PATCH v3 5/5] regulator: rk808: Add RK816 support
From: Alex Bee @ 2024-03-23 13:28 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Heiko Stuebner, Linus Walleij, Liam Girdwood, Mark Brown
Cc: Chris Zhong, Zhang Qing, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, linux-gpio, Alex Bee
In-Reply-To: <20240323132757.141861-2-knaerzche@gmail.com>
Add support for rk816 to the existing rk808 regulator driver.
The infrastructure of the driver can be re-used as is. A peculiarity for
this version is, that BUCK1/BUCK2 have a (common) bit which needs to
toggled after a voltage change to confirm the change. Regulator regmap
takes care of that by defining a apply_bit and apply_reg for those
regulators.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
changes since v1:
- align regulator's .name and .of_match with updated binding
changes since v2:
- align regulator's .name and .of_match with updated binding
(dropped "-regulator" prefix)
drivers/regulator/rk808-regulator.c | 202 +++++++++++++++++++++++++++-
1 file changed, 201 insertions(+), 1 deletion(-)
diff --git a/drivers/regulator/rk808-regulator.c b/drivers/regulator/rk808-regulator.c
index a6a563e402d0..14b60abd6afc 100644
--- a/drivers/regulator/rk808-regulator.c
+++ b/drivers/regulator/rk808-regulator.c
@@ -158,6 +158,11 @@
RK8XX_DESC_COM(_id, _match, _supply, _min, _max, _step, _vreg, \
_vmask, _ereg, _emask, 0, 0, _etime, &rk808_reg_ops)
+#define RK816_DESC(_id, _match, _supply, _min, _max, _step, _vreg, \
+ _vmask, _ereg, _emask, _disval, _etime) \
+ RK8XX_DESC_COM(_id, _match, _supply, _min, _max, _step, _vreg, \
+ _vmask, _ereg, _emask, _emask, _disval, _etime, &rk816_reg_ops)
+
#define RK817_DESC(_id, _match, _supply, _min, _max, _step, _vreg, \
_vmask, _ereg, _emask, _disval, _etime) \
RK8XX_DESC_COM(_id, _match, _supply, _min, _max, _step, _vreg, \
@@ -258,7 +263,7 @@ static const unsigned int rk808_buck1_2_ramp_table[] = {
2000, 4000, 6000, 10000
};
-/* RK817 RK809 */
+/* RK817/RK809/RK816 (buck 1/2 only) */
static const unsigned int rk817_buck1_4_ramp_table[] = {
3000, 6300, 12500, 25000
};
@@ -640,6 +645,38 @@ static int rk808_set_suspend_disable(struct regulator_dev *rdev)
rdev->desc->enable_mask);
}
+static const struct rk8xx_register_bit rk816_suspend_bits[] = {
+ RK8XX_REG_BIT(RK818_SLEEP_SET_OFF_REG1, 0),
+ RK8XX_REG_BIT(RK818_SLEEP_SET_OFF_REG1, 1),
+ RK8XX_REG_BIT(RK818_SLEEP_SET_OFF_REG1, 2),
+ RK8XX_REG_BIT(RK818_SLEEP_SET_OFF_REG1, 3),
+ RK8XX_REG_BIT(RK818_SLEEP_SET_OFF_REG2, 0),
+ RK8XX_REG_BIT(RK818_SLEEP_SET_OFF_REG2, 1),
+ RK8XX_REG_BIT(RK818_SLEEP_SET_OFF_REG2, 2),
+ RK8XX_REG_BIT(RK818_SLEEP_SET_OFF_REG2, 3),
+ RK8XX_REG_BIT(RK818_SLEEP_SET_OFF_REG2, 4),
+ RK8XX_REG_BIT(RK818_SLEEP_SET_OFF_REG2, 5),
+ RK8XX_REG_BIT(RK818_SLEEP_SET_OFF_REG1, 5),
+ RK8XX_REG_BIT(RK818_SLEEP_SET_OFF_REG1, 6),
+};
+
+static int rk816_set_suspend_enable(struct regulator_dev *rdev)
+{
+ int rid = rdev_get_id(rdev);
+
+ return regmap_update_bits(rdev->regmap, rk816_suspend_bits[rid].reg,
+ rk816_suspend_bits[rid].bit,
+ rk816_suspend_bits[rid].bit);
+}
+
+static int rk816_set_suspend_disable(struct regulator_dev *rdev)
+{
+ int rid = rdev_get_id(rdev);
+
+ return regmap_update_bits(rdev->regmap, rk816_suspend_bits[rid].reg,
+ rk816_suspend_bits[rid].bit, 0);
+}
+
static int rk817_set_suspend_enable_ctrl(struct regulator_dev *rdev,
unsigned int en)
{
@@ -913,6 +950,54 @@ static const struct regulator_ops rk809_buck5_ops_range = {
.set_suspend_disable = rk817_set_suspend_disable,
};
+static const struct regulator_ops rk816_buck1_2_ops_ranges = {
+ .list_voltage = regulator_list_voltage_linear_range,
+ .map_voltage = regulator_map_voltage_linear_range,
+ .get_voltage_sel = regulator_get_voltage_sel_regmap,
+ .set_voltage_sel = regulator_set_voltage_sel_regmap,
+ .set_voltage_time_sel = regulator_set_voltage_time_sel,
+ .enable = regulator_enable_regmap,
+ .disable = regulator_disable_regmap,
+ .is_enabled = regulator_is_enabled_regmap,
+ .set_mode = rk8xx_set_mode,
+ .get_mode = rk8xx_get_mode,
+ .set_suspend_mode = rk8xx_set_suspend_mode,
+ .set_ramp_delay = regulator_set_ramp_delay_regmap,
+ .set_suspend_voltage = rk808_set_suspend_voltage_range,
+ .set_suspend_enable = rk816_set_suspend_enable,
+ .set_suspend_disable = rk816_set_suspend_disable,
+};
+
+static const struct regulator_ops rk816_buck4_ops_ranges = {
+ .list_voltage = regulator_list_voltage_linear_range,
+ .map_voltage = regulator_map_voltage_linear_range,
+ .get_voltage_sel = regulator_get_voltage_sel_regmap,
+ .set_voltage_sel = regulator_set_voltage_sel_regmap,
+ .set_voltage_time_sel = regulator_set_voltage_time_sel,
+ .enable = regulator_enable_regmap,
+ .disable = regulator_disable_regmap,
+ .is_enabled = regulator_is_enabled_regmap,
+ .set_mode = rk8xx_set_mode,
+ .get_mode = rk8xx_get_mode,
+ .set_suspend_mode = rk8xx_set_suspend_mode,
+ .set_suspend_voltage = rk808_set_suspend_voltage_range,
+ .set_suspend_enable = rk816_set_suspend_enable,
+ .set_suspend_disable = rk816_set_suspend_disable,
+};
+
+static const struct regulator_ops rk816_reg_ops = {
+ .list_voltage = regulator_list_voltage_linear,
+ .map_voltage = regulator_map_voltage_linear,
+ .get_voltage_sel = regulator_get_voltage_sel_regmap,
+ .set_voltage_sel = regulator_set_voltage_sel_regmap,
+ .enable = regulator_enable_regmap,
+ .disable = regulator_disable_regmap,
+ .is_enabled = rk8xx_is_enabled_wmsk_regmap,
+ .set_suspend_voltage = rk808_set_suspend_voltage,
+ .set_suspend_enable = rk816_set_suspend_enable,
+ .set_suspend_disable = rk816_set_suspend_disable,
+};
+
static const struct regulator_ops rk817_reg_ops = {
.list_voltage = regulator_list_voltage_linear,
.map_voltage = regulator_map_voltage_linear,
@@ -1392,6 +1477,117 @@ static const struct regulator_desc rk809_reg[] = {
DISABLE_VAL(3)),
};
+static const struct linear_range rk816_buck_4_voltage_ranges[] = {
+ REGULATOR_LINEAR_RANGE(800000, 0, 26, 100000),
+ REGULATOR_LINEAR_RANGE(3500000, 27, 31, 0),
+};
+
+static const struct regulator_desc rk816_reg[] = {
+ {
+ .name = "dcdc1",
+ .supply_name = "vcc1",
+ .of_match = of_match_ptr("dcdc1"),
+ .regulators_node = of_match_ptr("regulators"),
+ .id = RK816_ID_DCDC1,
+ .ops = &rk816_buck1_2_ops_ranges,
+ .type = REGULATOR_VOLTAGE,
+ .n_voltages = 64,
+ .linear_ranges = rk805_buck_1_2_voltage_ranges,
+ .n_linear_ranges = ARRAY_SIZE(rk805_buck_1_2_voltage_ranges),
+ .vsel_reg = RK818_BUCK1_ON_VSEL_REG,
+ .vsel_mask = RK818_BUCK_VSEL_MASK,
+ .apply_reg = RK816_DCDC_EN_REG2,
+ .apply_bit = RK816_BUCK_DVS_CONFIRM,
+ .enable_reg = RK816_DCDC_EN_REG1,
+ .enable_mask = BIT(4) | BIT(0),
+ .enable_val = BIT(4) | BIT(0),
+ .disable_val = BIT(4),
+ .ramp_reg = RK818_BUCK1_CONFIG_REG,
+ .ramp_mask = RK808_RAMP_RATE_MASK,
+ .ramp_delay_table = rk817_buck1_4_ramp_table,
+ .n_ramp_values = ARRAY_SIZE(rk817_buck1_4_ramp_table),
+ .of_map_mode = rk8xx_regulator_of_map_mode,
+ .owner = THIS_MODULE,
+ }, {
+ .name = "dcdc2",
+ .supply_name = "vcc2",
+ .of_match = of_match_ptr("dcdc2"),
+ .regulators_node = of_match_ptr("regulators"),
+ .id = RK816_ID_DCDC2,
+ .ops = &rk816_buck1_2_ops_ranges,
+ .type = REGULATOR_VOLTAGE,
+ .n_voltages = 64,
+ .linear_ranges = rk805_buck_1_2_voltage_ranges,
+ .n_linear_ranges = ARRAY_SIZE(rk805_buck_1_2_voltage_ranges),
+ .vsel_reg = RK818_BUCK2_ON_VSEL_REG,
+ .vsel_mask = RK818_BUCK_VSEL_MASK,
+ .apply_reg = RK816_DCDC_EN_REG2,
+ .apply_bit = RK816_BUCK_DVS_CONFIRM,
+ .enable_reg = RK816_DCDC_EN_REG1,
+ .enable_mask = BIT(5) | BIT(1),
+ .enable_val = BIT(5) | BIT(1),
+ .disable_val = BIT(5),
+ .ramp_reg = RK818_BUCK2_CONFIG_REG,
+ .ramp_mask = RK808_RAMP_RATE_MASK,
+ .ramp_delay_table = rk817_buck1_4_ramp_table,
+ .n_ramp_values = ARRAY_SIZE(rk817_buck1_4_ramp_table),
+ .of_map_mode = rk8xx_regulator_of_map_mode,
+ .owner = THIS_MODULE,
+ }, {
+ .name = "dcdc3",
+ .supply_name = "vcc3",
+ .of_match = of_match_ptr("dcdc3"),
+ .regulators_node = of_match_ptr("regulators"),
+ .id = RK816_ID_DCDC3,
+ .ops = &rk808_switch_ops,
+ .type = REGULATOR_VOLTAGE,
+ .n_voltages = 1,
+ .enable_reg = RK816_DCDC_EN_REG1,
+ .enable_mask = BIT(6) | BIT(2),
+ .enable_val = BIT(6) | BIT(2),
+ .disable_val = BIT(6),
+ .of_map_mode = rk8xx_regulator_of_map_mode,
+ .owner = THIS_MODULE,
+ }, {
+ .name = "dcdc4",
+ .supply_name = "vcc4",
+ .of_match = of_match_ptr("dcdc4"),
+ .regulators_node = of_match_ptr("regulators"),
+ .id = RK816_ID_DCDC4,
+ .ops = &rk816_buck4_ops_ranges,
+ .type = REGULATOR_VOLTAGE,
+ .n_voltages = 32,
+ .linear_ranges = rk816_buck_4_voltage_ranges,
+ .n_linear_ranges = ARRAY_SIZE(rk816_buck_4_voltage_ranges),
+ .vsel_reg = RK818_BUCK4_ON_VSEL_REG,
+ .vsel_mask = RK818_BUCK4_VSEL_MASK,
+ .enable_reg = RK816_DCDC_EN_REG1,
+ .enable_mask = BIT(7) | BIT(3),
+ .enable_val = BIT(7) | BIT(3),
+ .disable_val = BIT(7),
+ .of_map_mode = rk8xx_regulator_of_map_mode,
+ .owner = THIS_MODULE,
+ },
+ RK816_DESC(RK816_ID_LDO1, "ldo1", "vcc5", 800, 3400, 100,
+ RK818_LDO1_ON_VSEL_REG, RK818_LDO_VSEL_MASK,
+ RK816_LDO_EN_REG1, ENABLE_MASK(0), DISABLE_VAL(0), 400),
+ RK816_DESC(RK816_ID_LDO2, "ldo2", "vcc5", 800, 3400, 100,
+ RK818_LDO2_ON_VSEL_REG, RK818_LDO_VSEL_MASK,
+ RK816_LDO_EN_REG1, ENABLE_MASK(1), DISABLE_VAL(1), 400),
+ RK816_DESC(RK816_ID_LDO3, "ldo3", "vcc5", 800, 3400, 100,
+ RK818_LDO3_ON_VSEL_REG, RK818_LDO_VSEL_MASK,
+ RK816_LDO_EN_REG1, ENABLE_MASK(2), DISABLE_VAL(2), 400),
+ RK816_DESC(RK816_ID_LDO4, "ldo4", "vcc6", 800, 3400, 100,
+ RK818_LDO4_ON_VSEL_REG, RK818_LDO_VSEL_MASK,
+ RK816_LDO_EN_REG1, ENABLE_MASK(3), DISABLE_VAL(3), 400),
+ RK816_DESC(RK816_ID_LDO5, "ldo5", "vcc6", 800, 3400, 100,
+ RK818_LDO5_ON_VSEL_REG, RK818_LDO_VSEL_MASK,
+ RK816_LDO_EN_REG2, ENABLE_MASK(0), DISABLE_VAL(0), 400),
+ RK816_DESC(RK816_ID_LDO6, "ldo6", "vcc6", 800, 3400, 100,
+ RK818_LDO6_ON_VSEL_REG, RK818_LDO_VSEL_MASK,
+ RK816_LDO_EN_REG2, ENABLE_MASK(1), DISABLE_VAL(1), 400),
+};
+
static const struct regulator_desc rk817_reg[] = {
{
.name = "DCDC_REG1",
@@ -1714,6 +1910,10 @@ static int rk808_regulator_probe(struct platform_device *pdev)
regulators = rk809_reg;
nregulators = RK809_NUM_REGULATORS;
break;
+ case RK816_ID:
+ regulators = rk816_reg;
+ nregulators = ARRAY_SIZE(rk816_reg);
+ break;
case RK817_ID:
regulators = rk817_reg;
nregulators = RK817_NUM_REGULATORS;
--
2.43.2
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* [PATCH v3 4/5] regulator: rk808: Support apply_bit for rk808_set_suspend_voltage_range
From: Alex Bee @ 2024-03-23 13:28 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Heiko Stuebner, Linus Walleij, Liam Girdwood, Mark Brown
Cc: Chris Zhong, Zhang Qing, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, linux-gpio, Alex Bee
In-Reply-To: <20240323132757.141861-2-knaerzche@gmail.com>
rk808_set_suspend_voltage_range currently does not account the existence of
apply_bit/apply_reg.
This adds support for those in same way it is done in
regulator_set_voltage_sel_regmap and is required for the upcoming RK816
support
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
changes since v1:
- none
drivers/regulator/rk808-regulator.c | 16 +++++++++++++---
1 file changed, 13 insertions(+), 3 deletions(-)
diff --git a/drivers/regulator/rk808-regulator.c b/drivers/regulator/rk808-regulator.c
index d89ae7f16d7a..a6a563e402d0 100644
--- a/drivers/regulator/rk808-regulator.c
+++ b/drivers/regulator/rk808-regulator.c
@@ -534,15 +534,25 @@ static int rk808_set_suspend_voltage_range(struct regulator_dev *rdev, int uv)
{
unsigned int reg;
int sel = regulator_map_voltage_linear_range(rdev, uv, uv);
+ int ret;
if (sel < 0)
return -EINVAL;
reg = rdev->desc->vsel_reg + RK808_SLP_REG_OFFSET;
- return regmap_update_bits(rdev->regmap, reg,
- rdev->desc->vsel_mask,
- sel);
+ ret = regmap_update_bits(rdev->regmap, reg,
+ rdev->desc->vsel_mask,
+ sel);
+ if (ret)
+ return ret;
+
+ if (rdev->desc->apply_bit)
+ ret = regmap_update_bits(rdev->regmap, rdev->desc->apply_reg,
+ rdev->desc->apply_bit,
+ rdev->desc->apply_bit);
+
+ return ret;
}
static int rk805_set_suspend_enable(struct regulator_dev *rdev)
--
2.43.2
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^ permalink raw reply related
* [PATCH v3 3/5] pinctrl: rk805: Add rk816 pinctrl support
From: Alex Bee @ 2024-03-23 13:27 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Heiko Stuebner, Linus Walleij, Liam Girdwood, Mark Brown
Cc: Chris Zhong, Zhang Qing, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, linux-gpio, Alex Bee
In-Reply-To: <20240323132757.141861-2-knaerzche@gmail.com>
This adds support for RK816 to the exising rk805 pinctrl driver
It has a single pin which can be configured as input from a thermistor (for
instance in an attached battery) or as a gpio.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
changes since v1:
- rename pin-function names according to the updated binding
- added missing fun_reg for rk816_gpio_cfgs
changes since v2:
- aligned pin-function names with binding (dropped "pin_fun"-prefix)
drivers/pinctrl/pinctrl-rk805.c | 69 +++++++++++++++++++++++++++++++++
1 file changed, 69 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-rk805.c b/drivers/pinctrl/pinctrl-rk805.c
index 56d916f2cee6..c42f1bf93404 100644
--- a/drivers/pinctrl/pinctrl-rk805.c
+++ b/drivers/pinctrl/pinctrl-rk805.c
@@ -93,6 +93,11 @@ enum rk806_pinmux_option {
RK806_PINMUX_FUN5,
};
+enum rk816_pinmux_option {
+ RK816_PINMUX_THERMISTOR,
+ RK816_PINMUX_GPIO,
+};
+
enum {
RK805_GPIO0,
RK805_GPIO1,
@@ -104,6 +109,10 @@ enum {
RK806_GPIO_DVS3
};
+enum {
+ RK816_GPIO0,
+};
+
static const char *const rk805_gpio_groups[] = {
"gpio0",
"gpio1",
@@ -115,6 +124,10 @@ static const char *const rk806_gpio_groups[] = {
"gpio_pwrctrl3",
};
+static const char *const rk816_gpio_groups[] = {
+ "gpio0",
+};
+
/* RK805: 2 output only GPIOs */
static const struct pinctrl_pin_desc rk805_pins_desc[] = {
PINCTRL_PIN(RK805_GPIO0, "gpio0"),
@@ -128,6 +141,11 @@ static const struct pinctrl_pin_desc rk806_pins_desc[] = {
PINCTRL_PIN(RK806_GPIO_DVS3, "gpio_pwrctrl3"),
};
+/* RK816 */
+static const struct pinctrl_pin_desc rk816_pins_desc[] = {
+ PINCTRL_PIN(RK816_GPIO0, "gpio0"),
+};
+
static const struct rk805_pin_function rk805_pin_functions[] = {
{
.name = "gpio",
@@ -176,6 +194,21 @@ static const struct rk805_pin_function rk806_pin_functions[] = {
},
};
+static const struct rk805_pin_function rk816_pin_functions[] = {
+ {
+ .name = "gpio",
+ .groups = rk816_gpio_groups,
+ .ngroups = ARRAY_SIZE(rk816_gpio_groups),
+ .mux_option = RK816_PINMUX_GPIO,
+ },
+ {
+ .name = "thermistor",
+ .groups = rk816_gpio_groups,
+ .ngroups = ARRAY_SIZE(rk816_gpio_groups),
+ .mux_option = RK816_PINMUX_THERMISTOR,
+ },
+};
+
static const struct rk805_pin_group rk805_pin_groups[] = {
{
.name = "gpio0",
@@ -207,6 +240,14 @@ static const struct rk805_pin_group rk806_pin_groups[] = {
}
};
+static const struct rk805_pin_group rk816_pin_groups[] = {
+ {
+ .name = "gpio0",
+ .pins = { RK816_GPIO0 },
+ .npins = 1,
+ },
+};
+
#define RK805_GPIO0_VAL_MSK BIT(0)
#define RK805_GPIO1_VAL_MSK BIT(1)
@@ -255,6 +296,20 @@ static struct rk805_pin_config rk806_gpio_cfgs[] = {
}
};
+#define RK816_FUN_MASK BIT(2)
+#define RK816_VAL_MASK BIT(3)
+#define RK816_DIR_MASK BIT(4)
+
+static struct rk805_pin_config rk816_gpio_cfgs[] = {
+ {
+ .fun_reg = RK818_IO_POL_REG,
+ .fun_msk = RK816_FUN_MASK,
+ .reg = RK818_IO_POL_REG,
+ .val_msk = RK816_VAL_MASK,
+ .dir_msk = RK816_DIR_MASK,
+ },
+};
+
/* generic gpio chip */
static int rk805_gpio_get(struct gpio_chip *chip, unsigned int offset)
{
@@ -439,6 +494,8 @@ static int rk805_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev,
return _rk805_pinctrl_set_mux(pctldev, offset, RK805_PINMUX_GPIO);
case RK806_ID:
return _rk805_pinctrl_set_mux(pctldev, offset, RK806_PINMUX_FUN5);
+ case RK816_ID:
+ return _rk805_pinctrl_set_mux(pctldev, offset, RK816_PINMUX_GPIO);
}
return -ENOTSUPP;
@@ -588,6 +645,18 @@ static int rk805_pinctrl_probe(struct platform_device *pdev)
pci->pin_cfg = rk806_gpio_cfgs;
pci->gpio_chip.ngpio = ARRAY_SIZE(rk806_gpio_cfgs);
break;
+ case RK816_ID:
+ pci->pins = rk816_pins_desc;
+ pci->num_pins = ARRAY_SIZE(rk816_pins_desc);
+ pci->functions = rk816_pin_functions;
+ pci->num_functions = ARRAY_SIZE(rk816_pin_functions);
+ pci->groups = rk816_pin_groups;
+ pci->num_pin_groups = ARRAY_SIZE(rk816_pin_groups);
+ pci->pinctrl_desc.pins = rk816_pins_desc;
+ pci->pinctrl_desc.npins = ARRAY_SIZE(rk816_pins_desc);
+ pci->pin_cfg = rk816_gpio_cfgs;
+ pci->gpio_chip.ngpio = ARRAY_SIZE(rk816_gpio_cfgs);
+ break;
default:
dev_err(&pdev->dev, "unsupported RK805 ID %lu\n",
pci->rk808->variant);
--
2.43.2
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^ permalink raw reply related
* [PATCH v3 2/5] mfd: rk8xx: Add RK816 support
From: Alex Bee @ 2024-03-23 13:27 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Heiko Stuebner, Linus Walleij, Liam Girdwood, Mark Brown
Cc: Chris Zhong, Zhang Qing, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, linux-gpio, Alex Bee
In-Reply-To: <20240323132757.141861-2-knaerzche@gmail.com>
This integrates RK816 support in the this existing rk8xx mfd driver.
This version has unaligned interrupt registers, which requires to define a
separate get_irq_reg callback for the regmap. Apart from that the
integration is straightforward and the existing structures can be used as
is. The initialization sequence has been taken from vendor kernel.
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
chnages since v1:
- un-constify rk816_get_irq_reg's return type
drivers/mfd/Kconfig | 4 +-
drivers/mfd/rk8xx-core.c | 103 ++++++++++++++++++++++++++++
drivers/mfd/rk8xx-i2c.c | 45 +++++++++++-
include/linux/mfd/rk808.h | 141 ++++++++++++++++++++++++++++++++++++++
4 files changed, 290 insertions(+), 3 deletions(-)
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 4b023ee229cf..2e7286cc98e4 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -1225,7 +1225,7 @@ config MFD_RK8XX
select MFD_CORE
config MFD_RK8XX_I2C
- tristate "Rockchip RK805/RK808/RK809/RK817/RK818 Power Management Chip"
+ tristate "Rockchip RK805/RK808/RK809/RK816/RK817/RK818 Power Management Chip"
depends on I2C && OF
select MFD_CORE
select REGMAP_I2C
@@ -1233,7 +1233,7 @@ config MFD_RK8XX_I2C
select MFD_RK8XX
help
If you say yes here you get support for the RK805, RK808, RK809,
- RK817 and RK818 Power Management chips.
+ RK816, RK817 and RK818 Power Management chips.
This driver provides common support for accessing the device
through I2C interface. The device supports multiple sub-devices
including interrupts, RTC, LDO & DCDC regulators, and onkey.
diff --git a/drivers/mfd/rk8xx-core.c b/drivers/mfd/rk8xx-core.c
index e2261b68b844..c68a380332e7 100644
--- a/drivers/mfd/rk8xx-core.c
+++ b/drivers/mfd/rk8xx-core.c
@@ -28,6 +28,10 @@ static const struct resource rtc_resources[] = {
DEFINE_RES_IRQ(RK808_IRQ_RTC_ALARM),
};
+static const struct resource rk816_rtc_resources[] = {
+ DEFINE_RES_IRQ(RK816_IRQ_RTC_ALARM),
+};
+
static const struct resource rk817_rtc_resources[] = {
DEFINE_RES_IRQ(RK817_IRQ_RTC_ALARM),
};
@@ -87,6 +91,21 @@ static const struct mfd_cell rk808s[] = {
},
};
+static const struct mfd_cell rk816s[] = {
+ { .name = "rk805-pinctrl", },
+ { .name = "rk808-clkout", },
+ { .name = "rk808-regulator", },
+ { .name = "rk805-pwrkey",
+ .num_resources = ARRAY_SIZE(rk805_key_resources),
+ .resources = rk805_key_resources,
+ },
+ {
+ .name = "rk808-rtc",
+ .num_resources = ARRAY_SIZE(rk816_rtc_resources),
+ .resources = rk816_rtc_resources,
+ },
+};
+
static const struct mfd_cell rk817s[] = {
{ .name = "rk808-clkout", },
{ .name = "rk808-regulator", },
@@ -148,6 +167,17 @@ static const struct rk808_reg_data rk808_pre_init_reg[] = {
VB_LO_SEL_3500MV },
};
+static const struct rk808_reg_data rk816_pre_init_reg[] = {
+ { RK818_BUCK1_CONFIG_REG, RK817_RAMP_RATE_MASK,
+ RK817_RAMP_RATE_12_5MV_PER_US },
+ { RK818_BUCK2_CONFIG_REG, RK817_RAMP_RATE_MASK,
+ RK817_RAMP_RATE_12_5MV_PER_US },
+ { RK818_BUCK4_CONFIG_REG, BUCK_ILMIN_MASK, BUCK_ILMIN_250MA },
+ { RK808_THERMAL_REG, TEMP_HOTDIE_MSK, TEMP105C},
+ { RK808_VB_MON_REG, VBAT_LOW_VOL_MASK | VBAT_LOW_ACT_MASK,
+ RK808_VBAT_LOW_3V0 | EN_VABT_LOW_SHUT_DOWN },
+};
+
static const struct rk808_reg_data rk817_pre_init_reg[] = {
{RK817_RTC_CTRL_REG, RTC_STOP, RTC_STOP},
/* Codec specific registers */
@@ -350,6 +380,59 @@ static const struct regmap_irq rk808_irqs[] = {
},
};
+static const unsigned int rk816_irq_status_offsets[] = {
+ (RK816_INT_STS_REG1 - RK816_INT_STS_REG1),
+ (RK816_INT_STS_REG2 - RK816_INT_STS_REG1),
+ (RK816_INT_STS_REG3 - RK816_INT_STS_REG1),
+};
+
+static const unsigned int rk816_irq_mask_offsets[] = {
+ (RK816_INT_STS_MSK_REG1 - RK816_INT_STS_MSK_REG1),
+ (RK816_INT_STS_MSK_REG2 - RK816_INT_STS_MSK_REG1),
+ (RK816_INT_STS_MSK_REG3 - RK816_INT_STS_MSK_REG1),
+};
+
+static unsigned int rk816_get_irq_reg(struct regmap_irq_chip_data *data,
+ unsigned int base, int index)
+{
+ unsigned int irq_reg = base;
+
+ switch (base) {
+ case RK816_INT_STS_REG1:
+ irq_reg += rk816_irq_status_offsets[index];
+ break;
+ case RK816_INT_STS_MSK_REG1:
+ irq_reg += rk816_irq_mask_offsets[index];
+ break;
+ }
+
+ return irq_reg;
+};
+
+static const struct regmap_irq rk816_irqs[] = {
+ /* INT_STS_REG1 IRQs */
+ REGMAP_IRQ_REG(RK816_IRQ_PWRON_FALL, 0, RK816_INT_STS_PWRON_FALL),
+ REGMAP_IRQ_REG(RK816_IRQ_PWRON_RISE, 0, RK816_INT_STS_PWRON_RISE),
+
+ /* INT_STS_REG2 IRQs */
+ REGMAP_IRQ_REG(RK816_IRQ_VB_LOW, 1, RK816_INT_STS_VB_LOW),
+ REGMAP_IRQ_REG(RK816_IRQ_PWRON, 1, RK816_INT_STS_PWRON),
+ REGMAP_IRQ_REG(RK816_IRQ_PWRON_LP, 1, RK816_INT_STS_PWRON_LP),
+ REGMAP_IRQ_REG(RK816_IRQ_HOTDIE, 1, RK816_INT_STS_HOTDIE),
+ REGMAP_IRQ_REG(RK816_IRQ_RTC_ALARM, 1, RK816_INT_STS_RTC_ALARM),
+ REGMAP_IRQ_REG(RK816_IRQ_RTC_PERIOD, 1, RK816_INT_STS_RTC_PERIOD),
+ REGMAP_IRQ_REG(RK816_IRQ_USB_OV, 1, RK816_INT_STS_USB_OV),
+
+ /* INT_STS3 IRQs */
+ REGMAP_IRQ_REG(RK816_IRQ_PLUG_IN, 2, RK816_INT_STS_PLUG_IN),
+ REGMAP_IRQ_REG(RK816_IRQ_PLUG_OUT, 2, RK816_INT_STS_PLUG_OUT),
+ REGMAP_IRQ_REG(RK816_IRQ_CHG_OK, 2, RK816_INT_STS_CHG_OK),
+ REGMAP_IRQ_REG(RK816_IRQ_CHG_TE, 2, RK816_INT_STS_CHG_TE),
+ REGMAP_IRQ_REG(RK816_IRQ_CHG_TS, 2, RK816_INT_STS_CHG_TS),
+ REGMAP_IRQ_REG(RK816_IRQ_CHG_CVTLIM, 2, RK816_INT_STS_CHG_CVTLIM),
+ REGMAP_IRQ_REG(RK816_IRQ_DISCHG_ILIM, 2, RK816_INT_STS_DISCHG_ILIM),
+};
+
static const struct regmap_irq rk818_irqs[] = {
/* INT_STS */
[RK818_IRQ_VOUT_LO] = {
@@ -482,6 +565,18 @@ static const struct regmap_irq_chip rk808_irq_chip = {
.init_ack_masked = true,
};
+static const struct regmap_irq_chip rk816_irq_chip = {
+ .name = "rk816",
+ .irqs = rk816_irqs,
+ .num_irqs = ARRAY_SIZE(rk816_irqs),
+ .num_regs = 3,
+ .get_irq_reg = rk816_get_irq_reg,
+ .status_base = RK816_INT_STS_REG1,
+ .mask_base = RK816_INT_STS_MSK_REG1,
+ .ack_base = RK816_INT_STS_REG1,
+ .init_ack_masked = true,
+};
+
static struct regmap_irq_chip rk817_irq_chip = {
.name = "rk817",
.irqs = rk817_irqs,
@@ -530,6 +625,7 @@ static int rk808_power_off(struct sys_off_data *data)
reg = RK817_SYS_CFG(3);
bit = DEV_OFF;
break;
+ case RK816_ID:
case RK818_ID:
reg = RK818_DEVCTRL_REG;
bit = DEV_OFF;
@@ -637,6 +733,13 @@ int rk8xx_probe(struct device *dev, int variant, unsigned int irq, struct regmap
cells = rk808s;
nr_cells = ARRAY_SIZE(rk808s);
break;
+ case RK816_ID:
+ rk808->regmap_irq_chip = &rk816_irq_chip;
+ pre_init_reg = rk816_pre_init_reg;
+ nr_pre_init_regs = ARRAY_SIZE(rk816_pre_init_reg);
+ cells = rk816s;
+ nr_cells = ARRAY_SIZE(rk816s);
+ break;
case RK818_ID:
rk808->regmap_irq_chip = &rk818_irq_chip;
pre_init_reg = rk818_pre_init_reg;
diff --git a/drivers/mfd/rk8xx-i2c.c b/drivers/mfd/rk8xx-i2c.c
index 75b5cf09d5a0..69a6b297d723 100644
--- a/drivers/mfd/rk8xx-i2c.c
+++ b/drivers/mfd/rk8xx-i2c.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Rockchip RK808/RK818 Core (I2C) driver
+ * Rockchip RK805/RK808/RK816/RK817/RK818 Core (I2C) driver
*
* Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
* Copyright (C) 2016 PHYTEC Messtechnik GmbH
@@ -49,6 +49,35 @@ static bool rk808_is_volatile_reg(struct device *dev, unsigned int reg)
return false;
}
+static bool rk816_is_volatile_reg(struct device *dev, unsigned int reg)
+{
+ /*
+ * Technically the ROUND_30s bit makes RTC_CTRL_REG volatile, but
+ * we don't use that feature. It's better to cache.
+ */
+
+ switch (reg) {
+ case RK808_SECONDS_REG ... RK808_WEEKS_REG:
+ case RK808_RTC_STATUS_REG:
+ case RK808_VB_MON_REG:
+ case RK808_THERMAL_REG:
+ case RK816_DCDC_EN_REG1:
+ case RK816_DCDC_EN_REG2:
+ case RK816_INT_STS_REG1:
+ case RK816_INT_STS_REG2:
+ case RK816_INT_STS_REG3:
+ case RK808_DEVCTRL_REG:
+ case RK816_SUP_STS_REG:
+ case RK816_GGSTS_REG:
+ case RK816_ZERO_CUR_ADC_REGH:
+ case RK816_ZERO_CUR_ADC_REGL:
+ case RK816_GASCNT_REG(0) ... RK816_BAT_VOL_REGL:
+ return true;
+ }
+
+ return false;
+}
+
static bool rk817_is_volatile_reg(struct device *dev, unsigned int reg)
{
/*
@@ -100,6 +129,14 @@ static const struct regmap_config rk808_regmap_config = {
.volatile_reg = rk808_is_volatile_reg,
};
+static const struct regmap_config rk816_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 8,
+ .max_register = RK816_DATA_REG(18),
+ .cache_type = REGCACHE_MAPLE,
+ .volatile_reg = rk816_is_volatile_reg,
+};
+
static const struct regmap_config rk817_regmap_config = {
.reg_bits = 8,
.val_bits = 8,
@@ -123,6 +160,11 @@ static const struct rk8xx_i2c_platform_data rk809_data = {
.variant = RK809_ID,
};
+static const struct rk8xx_i2c_platform_data rk816_data = {
+ .regmap_cfg = &rk816_regmap_config,
+ .variant = RK816_ID,
+};
+
static const struct rk8xx_i2c_platform_data rk817_data = {
.regmap_cfg = &rk817_regmap_config,
.variant = RK817_ID,
@@ -161,6 +203,7 @@ static const struct of_device_id rk8xx_i2c_of_match[] = {
{ .compatible = "rockchip,rk805", .data = &rk805_data },
{ .compatible = "rockchip,rk808", .data = &rk808_data },
{ .compatible = "rockchip,rk809", .data = &rk809_data },
+ { .compatible = "rockchip,rk816", .data = &rk816_data },
{ .compatible = "rockchip,rk817", .data = &rk817_data },
{ .compatible = "rockchip,rk818", .data = &rk818_data },
{ },
diff --git a/include/linux/mfd/rk808.h b/include/linux/mfd/rk808.h
index 78e167a92483..b90d1c278790 100644
--- a/include/linux/mfd/rk808.h
+++ b/include/linux/mfd/rk808.h
@@ -113,6 +113,145 @@ enum rk808_reg {
#define RK808_INT_STS_MSK_REG2 0x4f
#define RK808_IO_POL_REG 0x50
+/* RK816 */
+enum rk816_reg {
+ RK816_ID_DCDC1,
+ RK816_ID_DCDC2,
+ RK816_ID_DCDC3,
+ RK816_ID_DCDC4,
+ RK816_ID_LDO1,
+ RK816_ID_LDO2,
+ RK816_ID_LDO3,
+ RK816_ID_LDO4,
+ RK816_ID_LDO5,
+ RK816_ID_LDO6,
+ RK816_ID_BOOST,
+ RK816_ID_OTG_SW,
+};
+
+enum rk816_irqs {
+ /* INT_STS_REG1 */
+ RK816_IRQ_PWRON_FALL,
+ RK816_IRQ_PWRON_RISE,
+
+ /* INT_STS_REG2 */
+ RK816_IRQ_VB_LOW,
+ RK816_IRQ_PWRON,
+ RK816_IRQ_PWRON_LP,
+ RK816_IRQ_HOTDIE,
+ RK816_IRQ_RTC_ALARM,
+ RK816_IRQ_RTC_PERIOD,
+ RK816_IRQ_USB_OV,
+
+ /* INT_STS_REG3 */
+ RK816_IRQ_PLUG_IN,
+ RK816_IRQ_PLUG_OUT,
+ RK816_IRQ_CHG_OK,
+ RK816_IRQ_CHG_TE,
+ RK816_IRQ_CHG_TS,
+ RK816_IRQ_CHG_CVTLIM,
+ RK816_IRQ_DISCHG_ILIM,
+};
+
+/* power channel registers */
+#define RK816_DCDC_EN_REG1 0x23
+
+#define RK816_DCDC_EN_REG2 0x24
+#define RK816_BOOST_EN BIT(1)
+#define RK816_OTG_EN BIT(2)
+#define RK816_BOOST_EN_MSK BIT(5)
+#define RK816_OTG_EN_MSK BIT(6)
+#define RK816_BUCK_DVS_CONFIRM BIT(7)
+
+#define RK816_LDO_EN_REG1 0x27
+
+#define RK816_LDO_EN_REG2 0x28
+
+/* interrupt registers and irq definitions */
+#define RK816_INT_STS_REG1 0x49
+#define RK816_INT_STS_MSK_REG1 0x4a
+#define RK816_INT_STS_PWRON_FALL BIT(5)
+#define RK816_INT_STS_PWRON_RISE BIT(6)
+
+#define RK816_INT_STS_REG2 0x4c
+#define RK816_INT_STS_MSK_REG2 0x4d
+#define RK816_INT_STS_VB_LOW BIT(1)
+#define RK816_INT_STS_PWRON BIT(2)
+#define RK816_INT_STS_PWRON_LP BIT(3)
+#define RK816_INT_STS_HOTDIE BIT(4)
+#define RK816_INT_STS_RTC_ALARM BIT(5)
+#define RK816_INT_STS_RTC_PERIOD BIT(6)
+#define RK816_INT_STS_USB_OV BIT(7)
+
+#define RK816_INT_STS_REG3 0x4e
+#define RK816_INT_STS_MSK_REG3 0x4f
+#define RK816_INT_STS_PLUG_IN BIT(0)
+#define RK816_INT_STS_PLUG_OUT BIT(1)
+#define RK816_INT_STS_CHG_OK BIT(2)
+#define RK816_INT_STS_CHG_TE BIT(3)
+#define RK816_INT_STS_CHG_TS BIT(4)
+#define RK816_INT_STS_CHG_CVTLIM BIT(6)
+#define RK816_INT_STS_DISCHG_ILIM BIT(7)
+
+/* charger, boost and OTG registers */
+#define RK816_OTG_BUCK_LDO_CONFIG_REG 0x2a
+#define RK816_CHRG_CONFIG_REG 0x2b
+#define RK816_BOOST_ON_VESL_REG 0x54
+#define RK816_BOOST_SLP_VSEL_REG 0x55
+#define RK816_CHRG_BOOST_CONFIG_REG 0x9a
+#define RK816_SUP_STS_REG 0xa0
+#define RK816_USB_CTRL_REG 0xa1
+#define RK816_CHRG_CTRL(x) (0xa3 + (x))
+#define RK816_BAT_CTRL_REG 0xa6
+#define RK816_BAT_HTS_TS_REG 0xa8
+#define RK816_BAT_LTS_TS_REG 0xa9
+
+/* adc and fuel gauge registers */
+#define RK816_TS_CTRL_REG 0xac
+#define RK816_ADC_CTRL_REG 0xad
+#define RK816_GGCON_REG 0xb0
+#define RK816_GGSTS_REG 0xb1
+#define RK816_ZERO_CUR_ADC_REGH 0xb2
+#define RK816_ZERO_CUR_ADC_REGL 0xb3
+#define RK816_GASCNT_CAL_REG(x) (0xb7 - (x))
+#define RK816_GASCNT_REG(x) (0xbb - (x))
+#define RK816_BAT_CUR_AVG_REGH 0xbc
+#define RK816_BAT_CUR_AVG_REGL 0xbd
+#define RK816_TS_ADC_REGH 0xbe
+#define RK816_TS_ADC_REGL 0xbf
+#define RK816_USB_ADC_REGH 0xc0
+#define RK816_USB_ADC_REGL 0xc1
+#define RK816_BAT_OCV_REGH 0xc2
+#define RK816_BAT_OCV_REGL 0xc3
+#define RK816_BAT_VOL_REGH 0xc4
+#define RK816_BAT_VOL_REGL 0xc5
+#define RK816_RELAX_ENTRY_THRES_REGH 0xc6
+#define RK816_RELAX_ENTRY_THRES_REGL 0xc7
+#define RK816_RELAX_EXIT_THRES_REGH 0xc8
+#define RK816_RELAX_EXIT_THRES_REGL 0xc9
+#define RK816_RELAX_VOL1_REGH 0xca
+#define RK816_RELAX_VOL1_REGL 0xcb
+#define RK816_RELAX_VOL2_REGH 0xcc
+#define RK816_RELAX_VOL2_REGL 0xcd
+#define RK816_RELAX_CUR1_REGH 0xce
+#define RK816_RELAX_CUR1_REGL 0xcf
+#define RK816_RELAX_CUR2_REGH 0xd0
+#define RK816_RELAX_CUR2_REGL 0xd1
+#define RK816_CAL_OFFSET_REGH 0xd2
+#define RK816_CAL_OFFSET_REGL 0xd3
+#define RK816_NON_ACT_TIMER_CNT_REG 0xd4
+#define RK816_VCALIB0_REGH 0xd5
+#define RK816_VCALIB0_REGL 0xd6
+#define RK816_VCALIB1_REGH 0xd7
+#define RK816_VCALIB1_REGL 0xd8
+#define RK816_FCC_GASCNT_REG(x) (0xdc - (x))
+#define RK816_IOFFSET_REGH 0xdd
+#define RK816_IOFFSET_REGL 0xde
+#define RK816_SLEEP_CON_SAMP_CUR_REG 0xdf
+
+/* general purpose data registers 0xe0 ~ 0xf2 */
+#define RK816_DATA_REG(x) (0xe0 + (x))
+
/* RK818 */
#define RK818_DCDC1 0
#define RK818_LDO1 4
@@ -791,6 +930,7 @@ enum rk806_dvs_mode {
#define VOUT_LO_INT BIT(0)
#define CLK32KOUT2_EN BIT(0)
+#define TEMP105C 0x08
#define TEMP115C 0x0c
#define TEMP_HOTDIE_MSK 0x0c
#define SLP_SD_MSK (0x3 << 2)
@@ -1191,6 +1331,7 @@ enum {
RK806_ID = 0x8060,
RK808_ID = 0x0000,
RK809_ID = 0x8090,
+ RK816_ID = 0x8160,
RK817_ID = 0x8170,
RK818_ID = 0x8180,
};
--
2.43.2
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^ permalink raw reply related
* [PATCH v3 1/5] dt-bindings: mfd: Add rk816 binding
From: Alex Bee @ 2024-03-23 13:27 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Heiko Stuebner, Linus Walleij, Liam Girdwood, Mark Brown
Cc: Chris Zhong, Zhang Qing, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, linux-gpio, Alex Bee
In-Reply-To: <20240323132757.141861-2-knaerzche@gmail.com>
Add DT binding document for Rockchip's RK816 PMIC
Signed-off-by: Alex Bee <knaerzche@gmail.com>
---
changes since v1:
- lowercase/hyphens for regulator node names
- rename "-reg" to "-regulator" to make node names generic
- dropped superfluous description for clock-output-names and
wakeup-source
- dropped "|" for text blocks that don't require to preserve formatting
- use full path for `$ref`s
- added pins description to the binding
- added charger function to description
changes since v2:
- dropped "-regulator"-suffix from regulator device names
- use "'"-quotes consistently in the binding
- dropped "pin_fun"-prefix from pin-function names
- added pin to example
.../bindings/mfd/rockchip,rk816.yaml | 274 ++++++++++++++++++
1 file changed, 274 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/rockchip,rk816.yaml
diff --git a/Documentation/devicetree/bindings/mfd/rockchip,rk816.yaml b/Documentation/devicetree/bindings/mfd/rockchip,rk816.yaml
new file mode 100644
index 000000000000..b960ded35e99
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/rockchip,rk816.yaml
@@ -0,0 +1,274 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/rockchip,rk816.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: RK816 Power Management Integrated Circuit
+
+maintainers:
+ - Chris Zhong <zyw@rock-chips.com>
+ - Zhang Qing <zhangqing@rock-chips.com>
+
+description:
+ Rockchip RK816 series PMIC. This device consists of an i2c controlled MFD
+ that includes regulators, a RTC, a GPIO controller, a power button, and a
+ battery charger manager with fuel gauge.
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rk816
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ '#clock-cells':
+ description:
+ See <dt-bindings/clock/rockchip,rk808.h> for clock IDs.
+ const: 1
+
+ clock-output-names:
+ maxItems: 2
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
+ system-power-controller:
+ type: boolean
+ description:
+ Telling whether or not this PMIC is controlling the system power.
+
+ wakeup-source:
+ type: boolean
+
+ vcc1-supply:
+ description:
+ The input supply for dcdc1.
+
+ vcc2-supply:
+ description:
+ The input supply for dcdc2.
+
+ vcc3-supply:
+ description:
+ The input supply for dcdc3.
+
+ vcc4-supply:
+ description:
+ The input supply for dcdc4.
+
+ vcc5-supply:
+ description:
+ The input supply for ldo1, ldo2, and ldo3.
+
+ vcc6-supply:
+ description:
+ The input supply for ldo4, ldo5, and ldo6.
+
+ vcc7-supply:
+ description:
+ The input supply for boost.
+
+ vcc8-supply:
+ description:
+ The input supply for otg-switch.
+
+ regulators:
+ type: object
+ patternProperties:
+ '^(boost|dcdc[1-4]|ldo[1-6]|otg-switch)$':
+ type: object
+ $ref: /schemas/regulator/regulator.yaml#
+ unevaluatedProperties: false
+ unevaluatedProperties: false
+
+patternProperties:
+ '-pins$':
+ type: object
+ additionalProperties: false
+ $ref: /schemas/pinctrl/pinmux-node.yaml
+
+ properties:
+ function:
+ enum: [gpio, thermistor]
+
+ pins:
+ $ref: /schemas/types.yaml#/definitions/string
+ const: gpio0
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/pinctrl/rockchip.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/gpio/gpio.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rk816: pmic@1a {
+ compatible = "rockchip,rk816";
+ reg = <0x1a>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA2 IRQ_TYPE_LEVEL_LOW>;
+ clock-output-names = "xin32k", "rk816-clkout2";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ gpio-controller;
+ system-power-controller;
+ wakeup-source;
+ #clock-cells = <1>;
+ #gpio-cells = <2>;
+
+ vcc1-supply = <&vcc_sys>;
+ vcc2-supply = <&vcc_sys>;
+ vcc3-supply = <&vcc_sys>;
+ vcc4-supply = <&vcc_sys>;
+ vcc5-supply = <&vcc33_io>;
+ vcc6-supply = <&vcc_sys>;
+
+ regulators {
+ vdd_cpu: dcdc1 {
+ regulator-name = "vdd_cpu";
+ regulator-min-microvolt = <750000>;
+ regulator-max-microvolt = <1450000>;
+ regulator-ramp-delay = <6001>;
+ regulator-initial-mode = <1>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_logic: dcdc2 {
+ regulator-name = "vdd_logic";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1250000>;
+ regulator-ramp-delay = <6001>;
+ regulator-initial-mode = <1>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vcc_ddr: dcdc3 {
+ regulator-name = "vcc_ddr";
+ regulator-initial-mode = <1>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc33_io: dcdc4 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc33_io";
+ regulator-initial-mode = <1>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vccio_pmu: ldo1 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vccio_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_tp: ldo2 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_tp";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_10: ldo3 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-name = "vdd_10";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+
+ vcc18_lcd: ldo4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc18_lcd";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vccio_sd: ldo5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vccio_sd";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vdd10_lcd: ldo6 {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-name = "vdd10_lcd";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1000000>;
+ };
+ };
+ };
+
+ rk816_gpio_pins: gpio-pins {
+ function = "gpio";
+ pins = "gpio0";
+ };
+ };
+ };
--
2.43.2
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^ permalink raw reply related
* [PATCH v3 0/5] Add RK816 PMIC support
From: Alex Bee @ 2024-03-23 13:27 UTC (permalink / raw)
To: Lee Jones, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Heiko Stuebner, Linus Walleij, Liam Girdwood, Mark Brown
Cc: Chris Zhong, Zhang Qing, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, linux-gpio, Alex Bee
This series aims to add support for Rockchip RK816 PMIC series. As per
datasheet it's targeted for RK3126/RK3128 (RK816-1), RK1108 (RK816-2) and
PX3-SE (RK816-3) but might be used for other SoCs as well. The MFD consists
of an integrated RTC, a GPIO controller, two 32k clock outputs, a power
key, 3 buck- and 6 ldo regulators, 3 regulator-switches, and charger with
integrated fuel gauge. Charger and fuel gauge are not part of this series.
Two of the switches (otg/boost) are part of the binding, but not of
the driver. They must only ever be enabled if no battery charging is
happening, but it will be enabled automatically if a battery is attached
and an external power source is connected. Thus that needs some
incorporation of a yet to be added charger driver.
Integration in the existing rk8xx-infrastructure was pretty straightforward
and only needed very little tweaking. In order to not further bloat the
driver(s) too much with additional `#define`s I tried to re-use existing
ones wherever possible.
The patches are loosely based on the vendor's implementation, verified
against the datasheet and tested/measured on a RK3126 board. As they are
touching several subsystems I'm sending them (very) early for the
6.10.-cycle.
changes since v1:
- integrated Krzysztof's feedback for the bindings and the resulting
driver changes
- fixed a sparse warning
link to v1:
https://lore.kernel.org/lkml/20240321143911.90210-2-knaerzche@gmail.com/
changes since v2:
- integrated Krzysztof's feedback to v2 of the bindings and the resulting
driver changes
link to v2:
https://lore.kernel.org/lkml/20240323085852.116756-1-knaerzche@gmail.com/
Please see individual patches for details about the changes.
Alex Bee (5):
dt-bindings: mfd: Add rk816 binding
mfd: rk8xx: Add RK816 support
pinctrl: rk805: Add rk816 pinctrl support
regulator: rk808: Support apply_bit for
rk808_set_suspend_voltage_range
regulator: rk808: Add RK816 support
.../bindings/mfd/rockchip,rk816.yaml | 274 ++++++++++++++++++
drivers/mfd/Kconfig | 4 +-
drivers/mfd/rk8xx-core.c | 103 +++++++
drivers/mfd/rk8xx-i2c.c | 45 ++-
drivers/pinctrl/pinctrl-rk805.c | 69 +++++
drivers/regulator/rk808-regulator.c | 218 +++++++++++++-
include/linux/mfd/rk808.h | 141 +++++++++
7 files changed, 847 insertions(+), 7 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mfd/rockchip,rk816.yaml
--
2.43.2
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