* [PATCH net-next v2 0/2] Add support for flower actions mirred and redirect
From: Daniel Machon @ 2024-04-05 7:44 UTC (permalink / raw)
To: Lars Povlsen, Steen Hegelund, UNGLinuxDriver, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni
Cc: Ratheesh Kannoth, linux-arm-kernel, netdev, linux-kernel,
Daniel Machon
================================================================================
Add support for tc flower actions mirred and redirect.
================================================================================
This series adds support for the two tc flower actions mirred and
redirect. Both actions are implemented by means of a port mask and a
mask mode. The mask mode controls how the mask is applied, and together
they are used by the switch to make a forwarding decision. Both actions
are configurable via the IS0 or IS2 VCAP's (ingress stage 0 and 2,
respectively).
Patch #1: adds support for tc flower mirred action.
Patch #2: adds support for tc flower redirect action.
Signed-off-by: Daniel Machon <daniel.machon@microchip.com>
---
Changes in v2:
- Squash patch #1 and #2 from previous version, to silence the false
positive NIPA warnings.
- Return directly from vcap_rule_add_action_u72() in *_mirred() and
*_redirect()
- Link to v1: https://lore.kernel.org/r/20240403-mirror-redirect-actions-v1-0-c8e7c8132c89@microchip.com
---
Daniel Machon (2):
net: sparx5: add support for tc flower mirred action.
net: sparx5: add support for tc flower redirect action
.../ethernet/microchip/sparx5/sparx5_tc_flower.c | 68 ++++++++++++++++++++++
drivers/net/ethernet/microchip/vcap/vcap_api.c | 12 ++++
.../net/ethernet/microchip/vcap/vcap_api_client.h | 2 +
3 files changed, 82 insertions(+)
---
base-commit: 5fc68320c1fb3c7d456ddcae0b4757326a043e6f
change-id: 20240402-mirror-redirect-actions-cc469cc58586
Best regards,
--
Daniel Machon <daniel.machon@microchip.com>
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* Re: [PATCH 01/17] dt-bindings: clock: google,gs101-clock: add HSI2 clock management unit
From: Krzysztof Kozlowski @ 2024-04-05 7:46 UTC (permalink / raw)
To: André Draszik, Peter Griffin, mturquette, sboyd, robh,
krzk+dt, conor+dt, vkoul, kishon, alim.akhtar, avri.altman,
bvanassche, s.nawrocki, cw00.choi, jejb, martin.petersen,
chanho61.park, ebiggers
Cc: linux-scsi, linux-phy, devicetree, linux-clk, linux-samsung-soc,
linux-kernel, linux-arm-kernel, tudor.ambarus, saravanak,
willmcvicker
In-Reply-To: <d1aaa3a350315b8eb60aaee416fad4382385ca3a.camel@linaro.org>
On 05/04/2024 09:15, André Draszik wrote:
> Hi Pete,
>
> On Thu, 2024-04-04 at 13:25 +0100, Peter Griffin wrote:
>> Add dt schema documentation and clock IDs for the High Speed Interface
>> 2 (HSI2) clock management unit. This CMU feeds high speed interfaces
>> such as PCIe and UFS.
>>
>> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
>> ---
>> .../bindings/clock/google,gs101-clock.yaml | 30 +++++++++++++++++--
>> 1 file changed, 28 insertions(+), 2 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml b/Documentation/devicetree/bindings/clock/google,gs101-
>> clock.yaml
>> index 1d2bcea41c85..a202fd5d1ead 100644
>> --- a/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
>> +++ b/Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
>> @@ -32,14 +32,15 @@ properties:
>> - google,gs101-cmu-misc
>> - google,gs101-cmu-peric0
>> - google,gs101-cmu-peric1
>> + - google,gs101-cmu-hsi2
>
> Can you keep this alphabetical and add hsi before misc please.
>>
>> clocks:
>> minItems: 1
>> - maxItems: 3
>> + maxItems: 5
>>
>> clock-names:
>> minItems: 1
>> - maxItems: 3
>> + maxItems: 5
>>
>> "#clock-cells":
>> const: 1
>> @@ -112,6 +113,31 @@ allOf:
>> - const: bus
>> - const: ip
>>
>> + - if:
>> + properties:
>> + compatible:
>> + contains:
>> + enum:
>> + - google,gs101-cmu-hsi2
>
> this block should also come before misc please.
>
> Once done, feel free to add
Yes, please, ack for both.
Best regards,
Krzysztof
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* Re: [PATCH 03/17] dt-bindings: ufs: exynos-ufs: Add gs101 compatible
From: Krzysztof Kozlowski @ 2024-04-05 7:49 UTC (permalink / raw)
To: Peter Griffin, mturquette, sboyd, robh, krzk+dt, conor+dt, vkoul,
kishon, alim.akhtar, avri.altman, bvanassche, s.nawrocki,
cw00.choi, jejb, martin.petersen, chanho61.park, ebiggers
Cc: linux-scsi, linux-phy, devicetree, linux-clk, linux-samsung-soc,
linux-kernel, linux-arm-kernel, tudor.ambarus, andre.draszik,
saravanak, willmcvicker
In-Reply-To: <20240404122559.898930-4-peter.griffin@linaro.org>
On 04/04/2024 14:25, Peter Griffin wrote:
> Add dedicated google,gs101-ufs compatible for Google Tensor gs101
> SoC.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> .../bindings/ufs/samsung,exynos-ufs.yaml | 51 +++++++++++++++----
> 1 file changed, 42 insertions(+), 9 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
> index b2b509b3944d..898da6c0e94f 100644
> --- a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
> +++ b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
> @@ -12,12 +12,10 @@ maintainers:
> description: |
> Each Samsung UFS host controller instance should have its own node.
>
> -allOf:
> - - $ref: ufs-common.yaml
> -
> properties:
> compatible:
> enum:
> + - google,gs101-ufs
> - samsung,exynos7-ufs
> - samsung,exynosautov9-ufs
> - samsung,exynosautov9-ufs-vh
> @@ -38,14 +36,12 @@ properties:
> - const: ufsp
>
> clocks:
> - items:
> - - description: ufs link core clock
> - - description: unipro main clock
> + minItems: 2
> + maxItems: 5
Keep here minItems and:
+ - description: ufs link core clock
+ - description: unipro main clock
+ - description: fmp clock
+ - description: ufs aclk clock
+ - description: ufs pclk clock
>
> clock-names:
> - items:
> - - const: core_clk
> - - const: sclk_unipro_main
> + minItems: 2
> + maxItems: 5
Similarly here
>
> phys:
> maxItems: 1
> @@ -72,6 +68,43 @@ required:
> - clocks
> - clock-names
>
> +allOf:
> + - $ref: ufs-common.yaml
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: google,gs101-ufs
> +
> + then:
> + properties:
> + clocks:
Enough is:
minItems: 5
> + items:
and drop the items since they are defined in top-level.
Your original code is correct, but with my approach we keep the list
synced between variants, at least part of the list. If another variant
appears, then maybe it will go back to your approach, but maybe we can
still have the same clocks and their order.
> + - description: ufs link core clock
> + - description: unipro main clock
> + - description: fmp clock
> + - description: ufs aclk clock
> + - description: ufs pclk clock
> +
> + clock-names:
minItems: 5
> + items:
> + - const: core_clk
> + - const: sclk_unipro_main
> + - const: fmp
> + - const: ufs_aclk
> + - const: ufs_pclk
> + else:
> + properties:
> + clocks:
maxItems: 2
> + items:
> + - description: ufs link core clock
> + - description: unipro main clock
> +
> + clock-names:
maxItems: 2
> + items:
> + - const: core_clk
> + - const: sclk_unipro_main
> +
> unevaluatedProperties: false
>
> examples:
Best regards,
Krzysztof
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^ permalink raw reply
* Re: [PATCH] arm64: dts: mediatek: mt2712: fix validation errors
From: AngeloGioacchino Del Regno @ 2024-04-05 7:50 UTC (permalink / raw)
To: Rafał Miłecki, Matthias Brugger, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
Rafał Miłecki
In-Reply-To: <20240301074741.8362-1-zajec5@gmail.com>
Il 01/03/24 08:47, Rafał Miłecki ha scritto:
> From: Rafał Miłecki <rafal@milecki.pl>
>
> 1. Fixup infracfg clock controller binding
> It also acts as reset controller so #reset-cells is required.
> 2. Use -pins suffix for pinctrl
>
> This fixes:
> arch/arm64/boot/dts/mediatek/mt2712-evb.dtb: syscon@10001000: '#reset-cells' is a required property
> from schema $id: http://devicetree.org/schemas/arm/mediatek/mediatek,infracfg.yaml#
> arch/arm64/boot/dts/mediatek/mt2712-evb.dtb: pinctrl@1000b000: 'eth_default', 'eth_sleep', 'usb0_iddig', 'usb1_iddig' do not match any of the regexes: 'pinctrl-[0-9]+', 'pins$'
> from schema $id: http://devicetree.org/schemas/pinctrl/mediatek,mt65xx-pinctrl.yaml#
>
> Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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* Re: [PATCH 04/17] dt-bindings: phy: samsung,ufs-phy: Add dedicated gs101-ufs-phy compatible
From: Krzysztof Kozlowski @ 2024-04-05 7:50 UTC (permalink / raw)
To: Peter Griffin, mturquette, sboyd, robh, krzk+dt, conor+dt, vkoul,
kishon, alim.akhtar, avri.altman, bvanassche, s.nawrocki,
cw00.choi, jejb, martin.petersen, chanho61.park, ebiggers
Cc: linux-scsi, linux-phy, devicetree, linux-clk, linux-samsung-soc,
linux-kernel, linux-arm-kernel, tudor.ambarus, andre.draszik,
saravanak, willmcvicker
In-Reply-To: <20240404122559.898930-5-peter.griffin@linaro.org>
On 04/04/2024 14:25, Peter Griffin wrote:
> Update dt schema to include the gs101 ufs phy compatible.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> Documentation/devicetree/bindings/phy/samsung,ufs-phy.yaml | 1 +
> 1 file changed, 1 insertion(+)
This should go via phy tree. DTS should not depend on other subsystems.
If, after resending as separate series, phy does not take patches for
longer time, feel free to ping me, but first let's try to go via phy/UFS.
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Best regards,
Krzysztof
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^ permalink raw reply
* Re: [PATCH 05/17] arm64: dts: exynos: gs101: enable cmu-hsi2 clock controller
From: Krzysztof Kozlowski @ 2024-04-05 7:51 UTC (permalink / raw)
To: Peter Griffin, mturquette, sboyd, robh, krzk+dt, conor+dt, vkoul,
kishon, alim.akhtar, avri.altman, bvanassche, s.nawrocki,
cw00.choi, jejb, martin.petersen, chanho61.park, ebiggers
Cc: linux-scsi, linux-phy, devicetree, linux-clk, linux-samsung-soc,
linux-kernel, linux-arm-kernel, tudor.ambarus, andre.draszik,
saravanak, willmcvicker
In-Reply-To: <20240404122559.898930-6-peter.griffin@linaro.org>
On 04/04/2024 14:25, Peter Griffin wrote:
> Enable the cmu_hsi2 clock management unit. It feeds some of
> the high speed interfaces such as PCIe and UFS.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> arch/arm64/boot/dts/exynos/google/gs101.dtsi | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
Was it really compiled?
Best regards,
Krzysztof
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^ permalink raw reply
* Re: [PATCH 07/17] arm64: dts: exynos: gs101: Add ufs, ufs-phy and ufs regulator dt nodes
From: Krzysztof Kozlowski @ 2024-04-05 7:53 UTC (permalink / raw)
To: Peter Griffin, mturquette, sboyd, robh, krzk+dt, conor+dt, vkoul,
kishon, alim.akhtar, avri.altman, bvanassche, s.nawrocki,
cw00.choi, jejb, martin.petersen, chanho61.park, ebiggers
Cc: linux-scsi, linux-phy, devicetree, linux-clk, linux-samsung-soc,
linux-kernel, linux-arm-kernel, tudor.ambarus, andre.draszik,
saravanak, willmcvicker
In-Reply-To: <20240404122559.898930-8-peter.griffin@linaro.org>
On 04/04/2024 14:25, Peter Griffin wrote:
> Enable the ufs controller, ufs phy and ufs regulator in device tree.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> .../boot/dts/exynos/google/gs101-oriole.dts | 17 +++++++++
> arch/arm64/boot/dts/exynos/google/gs101.dtsi | 35 +++++++++++++++++++
If you wish you can split DTSI and DTS into separate patches. Up to you.
> 2 files changed, 52 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts
> index 6be15e990b65..986eb5c9898a 100644
> --- a/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts
> +++ b/arch/arm64/boot/dts/exynos/google/gs101-oriole.dts
> @@ -53,6 +53,14 @@ button-power {
> wakeup-source;
> };
> };
> +
> + ufs_0_fixed_vcc_reg: regulator-0 {
> + compatible = "regulator-fixed";
> + regulator-name = "ufs-vcc";
> + gpio = <&gpp0 1 0>;
Use defines for GPIO flags, but more important: are you sure this is not
coming from a PMIC? What's the voltage? It looks like a stub for missing
PMIC, because UFS voltages are usually provided by PMIC.
> + regulator-boot-on;
> + enable-active-high;
> + };
> };
>
> &ext_24_5m {
> @@ -106,6 +114,15 @@ &serial_0 {
> status = "okay";
> };
>
> +&ufs_0 {
> + status = "okay";
> + vcc-supply = <&ufs_0_fixed_vcc_reg>;
> +};
> +
> +&ufs_0_phy {
> + status = "okay";
> +};
> +
> &usi_uart {
> samsung,clkreq-on; /* needed for UART mode */
> status = "okay";
> diff --git a/arch/arm64/boot/dts/exynos/google/gs101.dtsi b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> index 608369cec47b..9c94829bf14c 100644
> --- a/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> +++ b/arch/arm64/boot/dts/exynos/google/gs101.dtsi
> @@ -1277,6 +1277,41 @@ pinctrl_hsi2: pinctrl@14440000 {
> interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>;
> };
>
> + ufs_0_phy: phy@17e04000 {
> + compatible = "google,gs101-ufs-phy";
> + reg = <0x14704000 0x3000>;
> + reg-names = "phy-pma";
> + samsung,pmu-syscon = <&pmu_system_controller>;
> + #phy-cells = <0>;
> + clocks = <&ext_24_5m>;
> + clock-names = "ref_clk";
> + status = "disabled";
> + };
> +
> + ufs_0: ufs@14700000 {
> + compatible = "google,gs101-ufs";
> +
Drop blank line.
> + reg = <0x14700000 0x200>,
> + <0x14701100 0x200>,
> + <0x14780000 0xa000>,
> + <0x14600000 0x100>;
Best regards,
Krzysztof
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^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: usb: mtk-xhci: add compatible for MT7988
From: AngeloGioacchino Del Regno @ 2024-04-05 7:55 UTC (permalink / raw)
To: Rafał Miłecki, Matthias Brugger, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: Chunfeng Yun, Greg Kroah-Hartman, Daniel Golle, linux-usb,
linux-arm-kernel, linux-mediatek, devicetree, linux-kernel,
Rafał Miłecki
In-Reply-To: <20240213130044.1976-1-zajec5@gmail.com>
Il 13/02/24 14:00, Rafał Miłecki ha scritto:
> From: Rafał Miłecki <rafal@milecki.pl>
>
> MT7988 SoC contains two on-SoC XHCI controllers. Add proper binding.
>
> Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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^ permalink raw reply
* Re: [PATCH 08/17] clk: samsung: gs101: add support for cmu_hsi2
From: Krzysztof Kozlowski @ 2024-04-05 7:55 UTC (permalink / raw)
To: Peter Griffin, mturquette, sboyd, robh, krzk+dt, conor+dt, vkoul,
kishon, alim.akhtar, avri.altman, bvanassche, s.nawrocki,
cw00.choi, jejb, martin.petersen, chanho61.park, ebiggers
Cc: linux-scsi, linux-phy, devicetree, linux-clk, linux-samsung-soc,
linux-kernel, linux-arm-kernel, tudor.ambarus, andre.draszik,
saravanak, willmcvicker
In-Reply-To: <20240404122559.898930-9-peter.griffin@linaro.org>
On 04/04/2024 14:25, Peter Griffin wrote:
> CMU_HSI2 is the clock management unit used for the hsi2 block.
> HSI stands for High Speed Interface and as such it generates
> clocks for PCIe, UFS and MMC card.
>
> This patch adds support for the muxes, dividers, and gates in
> cmu_hsi2.
>
> CLK_GOUT_HSI2_HSI2_CMU_HSI2_PCLK is marked as CLK_IS_CRITICAL
> as disabling it leads to an immediate system hang.
>
> CLK_GOUT_HSI2_SYSREG_HSI2_PCLK is also marked CLK_IS_CRITICAL.
> A hang is not observed with fine grained clock control, but
> UFS IP does not function with syscon controlling this clock
> just around hsi2_sysreg register accesses.
>
> CLK_GOUT_HSI2_GPIO_HSI2_PCLK is marked CLK_IGNORE_UNUSED until
> the exynos pinctrl clock patches land then it can be removed.
>
> Some clocks in this unit have very long names. To help with this
> the clock name mangling strategy was updated to include removing
> the following sub-strings.
> - G4X2_DWC_PCIE_CTL_
> - G4X1_DWC_PCIE_CTL_
> - PCIE_SUB_CTRL_
> - INST_0_
> - LN05LPE_
> - TM_WRAPPER_
> - SF_
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
>
> ---
> Updated regex for clock name mangling
> sed \
> -e 's|^PLL_LOCKTIME_PLL_\([^_]\+\)|fout_\L\1_pll|' \
> \
> -e 's|^PLL_CON0_MUX_CLKCMU_\([^_]\+\)_\(.*\)|mout_\L\1_\2|' \
> -e 's|^PLL_CON0_PLL_\(.*\)|mout_pll_\L\1|' \
> -e 's|^CLK_CON_MUX_MUX_CLK_\(.*\)|mout_\L\1|' \
> -e '/^PLL_CON[1-4]_[^_]\+_/d' \
> -e '/^[^_]\+_CMU_[^_]\+_CONTROLLER_OPTION/d' \
> -e '/^CLKOUT_CON_BLK_[^_]\+_CMU_[^_]\+_CLKOUT0/d' \
> \
> -e 's|_IPCLKPORT||' \
> -e 's|_RSTNSYNC||' \
> -e 's|_G4X2_DWC_PCIE_CTL||' \
> -e 's|_G4X1_DWC_PCIE_CTL||' \
> -e 's|_PCIE_SUB_CTRL||' \
> -e 's|_INST_0||g' \
> -e 's|_LN05LPE||' \
> -e 's|_TM_WRAPPER||' \
> -e 's|_SF||' \
> \
> -e 's|^CLK_CON_DIV_DIV_CLK_\([^_]\+\)_\(.*\)|dout_\L\1_\2|' \
> \
> -e 's|^CLK_CON_BUF_CLKBUF_\([^_]\+\)_\(.*\)|gout_\L\1_\2|' \
> -e 's|^CLK_CON_GAT_CLK_BLK_\([^_]\+\)_UID_\(.*\)|gout_\L\1_\2|' \
> -e 's|^gout_[^_]\+_[^_]\+_cmu_\([^_]\+\)_pclk$|gout_\1_\1_pclk|' \
> -e 's|^CLK_CON_GAT_GOUT_BLK_\([^_]\+\)_UID_\(.*\)|gout_\L\1_\2|' \
> -e 's|^CLK_CON_GAT_CLK_\([^_]\+\)_\(.*\)|gout_\L\1_clk_\L\1_\2|' \
> \
> -e '/^\(DMYQCH\|PCH\|QCH\|QUEUE\)_/d'
> ---
> drivers/clk/samsung/clk-gs101.c | 558 +++++++++++++++++++++++
> include/dt-bindings/clock/google,gs101.h | 63 +++
Bindings are separate patches.
> 2 files changed, 621 insertions(+)
>
> diff --git a/drivers/clk/samsung/clk-gs101.c b/drivers/clk/samsung/clk-gs101.c
> index d065e343a85d..b9f84c7d5c22 100644
> --- a/drivers/clk/samsung/clk-gs101.c
> +++ b/drivers/clk/samsung/clk-gs101.c
> @@ -22,6 +22,7 @@
> #define CLKS_NR_MISC (CLK_GOUT_MISC_XIU_D_MISC_ACLK + 1)
> #define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK + 1)
> #define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK + 1)
> +#define CLKS_NR_HSI2 (CLK_GOUT_HSI2_XIU_P_HSI2_ACLK + 1)
>
> /* ---- CMU_TOP ------------------------------------------------------------- */
>
> @@ -3409,6 +3410,560 @@ static const struct samsung_cmu_info peric1_cmu_info __initconst = {
> .clk_name = "bus",
> };
>
> +/* ---- CMU_HSI2 ---------------------------------------------------------- */
> +
> +/* Register Offset definitions for CMU_HSI2 (0x14400000) */
> +#define PLL_CON0_MUX_CLKCMU_HSI2_BUS_USER 0x0600
> +#define PLL_CON1_MUX_CLKCMU_HSI2_BUS_USER 0x0604
> +#define PLL_CON0_MUX_CLKCMU_HSI2_MMC_CARD_USER 0x0610
> +#define PLL_CON1_MUX_CLKCMU_HSI2_MMC_CARD_USER 0x0614
> +#define PLL_CON0_MUX_CLKCMU_HSI2_PCIE_USER 0x0620
> +#define PLL_CON1_MUX_CLKCMU_HSI2_PCIE_USER 0x0624
> +#define PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER 0x0630
> +#define PLL_CON1_MUX_CLKCMU_HSI2_UFS_EMBD_USER 0x0634
> +#define HSI2_CMU_HSI2_CONTROLLER_OPTION 0x0800
> +#define CLKOUT_CON_BLK_HSI2_CMU_HSI2_CLKOUT0 0x0810
> +#define CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN 0x2000
> +#define CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN 0x2004
> +#define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_ACLK 0x2008
> +#define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_PCLK 0x200c
> +#define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_ACLK 0x2010
> +#define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_PCLK 0x2014
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_D_TZPC_HSI2_IPCLKPORT_PCLK 0x201c
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLK 0x2020
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK 0x2024
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK 0x2028
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHM_AXI_P_HSI2_IPCLKPORT_I_CLK 0x202c
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHS_ACEL_D_HSI2_IPCLKPORT_I_CLK 0x2030
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK 0x2034
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_SDCLKIN 0x2038
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG 0x203c
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG 0x2040
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG 0x2044
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK 0x2048
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG 0x204c
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG 0x2050
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG 0x2054
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK 0x2058
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK 0x205c
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK 0x2060
> +#define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK 0x2064
Is it doable to use shorter register names while still keeping them
close to datasheet/manual? This one is a bit too much... actually most
of them are quite too much. :)
...
> +
> /* ---- platform_driver ----------------------------------------------------- */
>
> static int __init gs101_cmu_probe(struct platform_device *pdev)
> @@ -3432,6 +3987,9 @@ static const struct of_device_id gs101_cmu_of_match[] = {
> }, {
> .compatible = "google,gs101-cmu-peric1",
> .data = &peric1_cmu_info,
> + }, {
> + .compatible = "google,gs101-cmu-hsi2",
> + .data = &hsi2_cmu_info,
Keep these also alphabetically ordered by compatible.
Best regards,
Krzysztof
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^ permalink raw reply
* Re: [PATCH 2/2] arm64: dts: mediatek: mt7988: add XHCI controllers
From: AngeloGioacchino Del Regno @ 2024-04-05 7:56 UTC (permalink / raw)
To: Rafał Miłecki, Matthias Brugger, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: Chunfeng Yun, Greg Kroah-Hartman, Daniel Golle, linux-usb,
linux-arm-kernel, linux-mediatek, devicetree, linux-kernel,
Rafał Miłecki
In-Reply-To: <20240213130044.1976-2-zajec5@gmail.com>
Il 13/02/24 14:00, Rafał Miłecki ha scritto:
> From: Rafał Miłecki <rafal@milecki.pl>
>
> Add bindings of two on-SoC XHCI controllers.
>
> Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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* Re: [PATCH 10/17] phy: samsung-ufs: ufs: Add SoC callbacks for calibration and clk data recovery
From: Krzysztof Kozlowski @ 2024-04-05 7:56 UTC (permalink / raw)
To: Peter Griffin, mturquette, sboyd, robh, krzk+dt, conor+dt, vkoul,
kishon, alim.akhtar, avri.altman, bvanassche, s.nawrocki,
cw00.choi, jejb, martin.petersen, chanho61.park, ebiggers
Cc: linux-scsi, linux-phy, devicetree, linux-clk, linux-samsung-soc,
linux-kernel, linux-arm-kernel, tudor.ambarus, andre.draszik,
saravanak, willmcvicker
In-Reply-To: <20240404122559.898930-11-peter.griffin@linaro.org>
On 04/04/2024 14:25, Peter Griffin wrote:
> Some SoCs like gs101 don't fit in well with the existing pll lock and
> clock data recovery (CDR) callback used by existing exynos platforms.
>
> Allow SoCs to specifify and implement their own calibration and CDR
> functions that can be called by the generic samsung phy code.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
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* Re: [PATCH 11/17] phy: samsung-ufs: ufs: Add support for gs101 UFS phy tuning
From: Krzysztof Kozlowski @ 2024-04-05 7:57 UTC (permalink / raw)
To: Peter Griffin, mturquette, sboyd, robh, krzk+dt, conor+dt, vkoul,
kishon, alim.akhtar, avri.altman, bvanassche, s.nawrocki,
cw00.choi, jejb, martin.petersen, chanho61.park, ebiggers
Cc: linux-scsi, linux-phy, devicetree, linux-clk, linux-samsung-soc,
linux-kernel, linux-arm-kernel, tudor.ambarus, andre.draszik,
saravanak, willmcvicker
In-Reply-To: <20240404122559.898930-12-peter.griffin@linaro.org>
On 04/04/2024 14:25, Peter Griffin wrote:
> Add the m-phy tuning values for gs101 UFS phy and SoC callbacks
> gs101_phy_wait_for_calibration() and gs101_phy_wait_for_cdr_lock().
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
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^ permalink raw reply
* Re: [PATCH 3/7] crypto: Remove the now superfluous sentinel element from ctl_table array
From: Herbert Xu @ 2024-04-05 7:56 UTC (permalink / raw)
To: j.granados
Cc: Andrew Morton, Muchun Song, Miaohe Lin, Naoya Horiguchi,
John Johansen, Paul Moore, James Morris, Serge E. Hallyn,
David Howells, Jarkko Sakkinen, Kees Cook, David S. Miller,
Jens Axboe, Pavel Begunkov, Atish Patra, Anup Patel, Will Deacon,
Mark Rutland, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Luis Chamberlain, linux-mm, linux-kernel, linux-fsdevel, apparmor,
linux-security-module, keyrings, linux-crypto, io-uring,
linux-riscv, linux-arm-kernel
In-Reply-To: <20240328-jag-sysctl_remset_misc-v1-3-47c1463b3af2@samsung.com>
On Thu, Mar 28, 2024 at 04:57:50PM +0100, Joel Granados via B4 Relay wrote:
> From: Joel Granados <j.granados@samsung.com>
>
> This commit comes at the tail end of a greater effort to remove the
> empty elements at the end of the ctl_table arrays (sentinels) which will
> reduce the overall build time size of the kernel and run time memory
> bloat by ~64 bytes per sentinel (further information Link :
> https://lore.kernel.org/all/ZO5Yx5JFogGi%2FcBo@bombadil.infradead.org/)
>
> Remove sentinel from crypto_sysctl_table
>
> Signed-off-by: Joel Granados <j.granados@samsung.com>
> ---
> crypto/fips.c | 1 -
> 1 file changed, 1 deletion(-)
Patch applied. Thanks.
--
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
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* Re: [PATCH 12/17] scsi: ufs: host: ufs-exynos: Add EXYNOS_UFS_OPT_UFSPR_SECURE option
From: Krzysztof Kozlowski @ 2024-04-05 7:57 UTC (permalink / raw)
To: Peter Griffin, mturquette, sboyd, robh, krzk+dt, conor+dt, vkoul,
kishon, alim.akhtar, avri.altman, bvanassche, s.nawrocki,
cw00.choi, jejb, martin.petersen, chanho61.park, ebiggers
Cc: linux-scsi, linux-phy, devicetree, linux-clk, linux-samsung-soc,
linux-kernel, linux-arm-kernel, tudor.ambarus, andre.draszik,
saravanak, willmcvicker
In-Reply-To: <20240404122559.898930-13-peter.griffin@linaro.org>
On 04/04/2024 14:25, Peter Griffin wrote:
> This option is intended to be set on platforms whose ufspr
> registers are only accessible via smc call (such as gs101).
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
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^ permalink raw reply
* Re: [PATCH 13/17] scsi: ufs: host: ufs-exynos: add EXYNOS_UFS_OPT_TIMER_TICK_SELECT option
From: Krzysztof Kozlowski @ 2024-04-05 7:58 UTC (permalink / raw)
To: Peter Griffin, mturquette, sboyd, robh, krzk+dt, conor+dt, vkoul,
kishon, alim.akhtar, avri.altman, bvanassche, s.nawrocki,
cw00.choi, jejb, martin.petersen, chanho61.park, ebiggers
Cc: linux-scsi, linux-phy, devicetree, linux-clk, linux-samsung-soc,
linux-kernel, linux-arm-kernel, tudor.ambarus, andre.draszik,
saravanak, willmcvicker
In-Reply-To: <20240404122559.898930-14-peter.griffin@linaro.org>
On 04/04/2024 14:25, Peter Griffin wrote:
> This option is intended to be set for SoCs that have HCI_V2P1_CTRL
> register and can select their tick source via IA_TICK_SEL bit.
>
> Source clock selection for timer tick
> 0x0 = Bus clock (aclk)
> 0x1 = Function clock (mclk)
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
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^ permalink raw reply
* Re: [PATCH 14/17] scsi: ufs: host: ufs-exynos: allow max frequencies up to 267Mhz
From: Krzysztof Kozlowski @ 2024-04-05 7:58 UTC (permalink / raw)
To: Peter Griffin, mturquette, sboyd, robh, krzk+dt, conor+dt, vkoul,
kishon, alim.akhtar, avri.altman, bvanassche, s.nawrocki,
cw00.choi, jejb, martin.petersen, chanho61.park, ebiggers
Cc: linux-scsi, linux-phy, devicetree, linux-clk, linux-samsung-soc,
linux-kernel, linux-arm-kernel, tudor.ambarus, andre.draszik,
saravanak, willmcvicker
In-Reply-To: <20240404122559.898930-15-peter.griffin@linaro.org>
On 04/04/2024 14:25, Peter Griffin wrote:
> Platforms such as Tensor gs101 the pclk frequency is 267Mhz.
> Increase PCLK_AVAIL_MAX so we don't fail the frequency check.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Best regards,
Krzysztof
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^ permalink raw reply
* Re: [PATCH 15/17] scsi: ufs: host: ufs-exynos: add some pa_dbg_ register offsets into drvdata
From: Krzysztof Kozlowski @ 2024-04-05 7:59 UTC (permalink / raw)
To: Peter Griffin, mturquette, sboyd, robh, krzk+dt, conor+dt, vkoul,
kishon, alim.akhtar, avri.altman, bvanassche, s.nawrocki,
cw00.choi, jejb, martin.petersen, chanho61.park, ebiggers
Cc: linux-scsi, linux-phy, devicetree, linux-clk, linux-samsung-soc,
linux-kernel, linux-arm-kernel, tudor.ambarus, andre.draszik,
saravanak, willmcvicker
In-Reply-To: <20240404122559.898930-16-peter.griffin@linaro.org>
On 04/04/2024 14:25, Peter Griffin wrote:
> This allows these registers to be at different offsets or not
> exist at all on some SoCs variants.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> drivers/ufs/host/ufs-exynos.c | 38 ++++++++++++++++++++++++-----------
> drivers/ufs/host/ufs-exynos.h | 6 +++++-
> 2 files changed, 31 insertions(+), 13 deletions(-)
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Best regards,
Krzysztof
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^ permalink raw reply
* Re: [PATCH 16/17] scsi: ufs: host: ufs-exynos: Add support for Tensor gs101 SoC
From: Krzysztof Kozlowski @ 2024-04-05 7:59 UTC (permalink / raw)
To: Peter Griffin, mturquette, sboyd, robh, krzk+dt, conor+dt, vkoul,
kishon, alim.akhtar, avri.altman, bvanassche, s.nawrocki,
cw00.choi, jejb, martin.petersen, chanho61.park, ebiggers
Cc: linux-scsi, linux-phy, devicetree, linux-clk, linux-samsung-soc,
linux-kernel, linux-arm-kernel, tudor.ambarus, andre.draszik,
saravanak, willmcvicker
In-Reply-To: <20240404122559.898930-17-peter.griffin@linaro.org>
On 04/04/2024 14:25, Peter Griffin wrote:
> Add a dedicated compatible and drv_data with associated
> hooks for gs101 SoC found on Pixel 6.
>
> Note we make use of the previously added EXYNOS_UFS_OPT_UFSPR_SECURE
> option, to skip initialisation of UFSPR registers as these are only
> accessible via SMC call.
>
> EXYNOS_UFS_OPT_TIMER_TICK_SELECT option is also set to select tick
> source. This has been done so as not to effect any existing platforms.
>
> DBG_OPTION_SUITE on gs101 has different address offsets to other SoCs
> so these register offsets now come from uic_attr struct.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Best regards,
Krzysztof
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^ permalink raw reply
* [RFC 0/8] arm64/hw_breakpoint: Enable FEAT_Debugv8p9
From: Anshuman Khandual @ 2024-04-05 8:00 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Anshuman Khandual, Jonathan Corbet, Marc Zyngier, Oliver Upton,
James Morse, Suzuki K Poulose, Catalin Marinas, Will Deacon,
Mark Brown, Mark Rutland, kvmarm, linux-kernel
This series enables FEAT_Debugv8p9 thus extending breakpoint and watchpoint
support upto 64. This has been lightly tested and still work is in progress
but would like to get some early feedback on the approach.
Possible impact of context switches while tracing kernel addresses needs to
be evaluated regarding MDSELR_EL1 access. This series is based on v6.9-rc2.
Cc: Jonathan Corbet <corbet@lwn.net>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Oliver Upton <oliver.upton@linux.dev>
Cc: James Morse <james.morse@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: kvmarm@lists.linux.dev
Cc: linux-kernel@vger.kernel.org
Anshuman Khandual (8):
arm64/sysreg: Add register fields for MDSELR_EL1
arm64/sysreg: Add register fields for HDFGRTR2_EL2
arm64/sysreg: Add register fields for HDFGWTR2_EL2
arm64/sysreg: Update ID_AA64MMFR0_EL1 register
KVM: arm64: Explicitly handle MDSELR_EL1 traps as UNDEFINED
arm64/cpufeature: Add field details for ID_AA64DFR1_EL1 register
arm64/boot: Enable EL2 requirements for FEAT_Debugv8p9
arm64/hw_breakpoint: Enable FEAT_Debugv8p9
Documentation/arch/arm64/booting.rst | 19 +++++++
arch/arm64/include/asm/debug-monitors.h | 2 +-
arch/arm64/include/asm/el2_setup.h | 27 ++++++++++
arch/arm64/include/asm/hw_breakpoint.h | 46 +++++++++++++----
arch/arm64/include/asm/kvm_arm.h | 1 +
arch/arm64/kernel/cpufeature.c | 21 ++++++--
arch/arm64/kernel/debug-monitors.c | 16 ++++--
arch/arm64/kernel/hw_breakpoint.c | 33 ++++++++++++
arch/arm64/kvm/sys_regs.c | 1 +
arch/arm64/tools/sysreg | 68 +++++++++++++++++++++++++
10 files changed, 214 insertions(+), 20 deletions(-)
--
2.25.1
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^ permalink raw reply
* Re: [PATCH 17/17] MAINTAINERS: Add phy-gs101-ufs file to Tensor GS101.
From: Krzysztof Kozlowski @ 2024-04-05 8:00 UTC (permalink / raw)
To: Peter Griffin, mturquette, sboyd, robh, krzk+dt, conor+dt, vkoul,
kishon, alim.akhtar, avri.altman, bvanassche, s.nawrocki,
cw00.choi, jejb, martin.petersen, chanho61.park, ebiggers
Cc: linux-scsi, linux-phy, devicetree, linux-clk, linux-samsung-soc,
linux-kernel, linux-arm-kernel, tudor.ambarus, andre.draszik,
saravanak, willmcvicker
In-Reply-To: <20240404122559.898930-18-peter.griffin@linaro.org>
On 04/04/2024 14:25, Peter Griffin wrote:
> Add the newly created ufs phy for GS101 to MAINTAINERS.
>
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> ---
> MAINTAINERS | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 491d48f7c2fa..48ac9bd64f22 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -9256,6 +9256,7 @@ S: Maintained
> F: Documentation/devicetree/bindings/clock/google,gs101-clock.yaml
> F: arch/arm64/boot/dts/exynos/google/
> F: drivers/clk/samsung/clk-gs101.c
> +F: drivers/phy/samsung/phy-gs101-ufs.c
This could go also via phy-tree:
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Best regards,
Krzysztof
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* [RFC 2/8] arm64/sysreg: Add register fields for HDFGRTR2_EL2
From: Anshuman Khandual @ 2024-04-05 8:00 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Anshuman Khandual, Jonathan Corbet, Marc Zyngier, Oliver Upton,
James Morse, Suzuki K Poulose, Catalin Marinas, Will Deacon,
Mark Brown, Mark Rutland, kvmarm, linux-kernel
In-Reply-To: <20240405080008.1225223-1-anshuman.khandual@arm.com>
This adds register fields for HDFGRTR2_EL2 as per the definitions based
on DDI0601 2023-12.
Cc: Will Deacon <will@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
arch/arm64/tools/sysreg | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 4c58fd7a70e6..9bcd8a0d55c4 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -2444,6 +2444,34 @@ Field 1 ICIALLU
Field 0 ICIALLUIS
EndSysreg
+Sysreg HDFGRTR2_EL2 3 4 3 1 0
+Res0 63:24
+Field 23 nMDSTEPOP_EL1
+Field 22 nTRBMPAM_EL1
+Res0 21
+Field 20 nTRCITECR_EL1
+Field 19 nPMSDSFR_EL1
+Field 18 nSPMDEVAFF_EL1
+Field 17 nSPMID
+Field 16 nSPMSCR_EL1
+Field 15 nSPMACCESSR_EL1
+Field 14 nSPMCR_EL0
+Field 13 nSPMOVS
+Field 12 nSPMINTEN
+Field 11 nSPMCNTEN
+Field 10 nSPMSELR_EL0
+Field 9 nSPMEVTYPERn_EL0
+Field 8 nSPMEVCNTRn_EL0
+Field 7 nPMSSCR_EL1
+Field 6 nPMSSDATA
+Field 5 nMDSELR_EL1
+Field 4 nPMUACR_EL1
+Field 3 nPMICFILTR_EL0
+Field 2 nPMICNTR_EL0
+Field 1 nPMIAR_EL1
+Field 0 nPMECR_EL1
+EndSysreg
+
Sysreg HDFGRTR_EL2 3 4 3 1 4
Field 63 PMBIDR_EL1
Field 62 nPMSNEVFR_EL1
--
2.25.1
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* [RFC 3/8] arm64/sysreg: Add register fields for HDFGWTR2_EL2
From: Anshuman Khandual @ 2024-04-05 8:00 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Anshuman Khandual, Jonathan Corbet, Marc Zyngier, Oliver Upton,
James Morse, Suzuki K Poulose, Catalin Marinas, Will Deacon,
Mark Brown, Mark Rutland, kvmarm, linux-kernel
In-Reply-To: <20240405080008.1225223-1-anshuman.khandual@arm.com>
This adds register fields for HDFGWTR2_EL2 as per the definitions based
on DDI0601 2023-12.
Cc: Will Deacon <will@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
arch/arm64/tools/sysreg | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 9bcd8a0d55c4..c38414352dd8 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -2472,6 +2472,33 @@ Field 1 nPMIAR_EL1
Field 0 nPMECR_EL1
EndSysreg
+Sysreg HDFGWTR2_EL2 3 4 3 1 1
+Res0 63:24
+Field 23 nMDSTEPOP_EL1
+Field 22 nTRBMPAM_EL1
+Field 21 nPMZR_EL0
+Field 20 nTRCITECR_EL1
+Field 19 nPMSDSFR_EL1
+Res0 18:17
+Field 16 nSPMSCR_EL1
+Field 15 nSPMACCESSR_EL1
+Field 14 nSPMCR_EL0
+Field 13 nSPMOVS
+Field 12 nSPMINTEN
+Field 11 nSPMCNTEN
+Field 10 nSPMSELR_EL0
+Field 9 nSPMEVTYPERn_EL0
+Field 8 nSPMEVCNTRn_EL0
+Field 7 nPMSSCR_EL1
+Res0 6
+Field 5 nMDSELR_EL1
+Field 4 nPMUACR_EL1
+Field 3 nPMICFILTR_EL0
+Field 2 nPMICNTR_EL0
+Field 1 nPMIAR_EL1
+Field 0 nPMECR_EL1
+EndSysreg
+
Sysreg HDFGRTR_EL2 3 4 3 1 4
Field 63 PMBIDR_EL1
Field 62 nPMSNEVFR_EL1
--
2.25.1
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* [RFC 4/8] arm64/sysreg: Update ID_AA64MMFR0_EL1 register
From: Anshuman Khandual @ 2024-04-05 8:00 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Anshuman Khandual, Jonathan Corbet, Marc Zyngier, Oliver Upton,
James Morse, Suzuki K Poulose, Catalin Marinas, Will Deacon,
Mark Brown, Mark Rutland, kvmarm, linux-kernel
In-Reply-To: <20240405080008.1225223-1-anshuman.khandual@arm.com>
This updates ID_AA64MMFR0_EL1.FGT and ID_AA64MMFR0_EL1.PARANGE register
fields as per the definitions based on DDI0601 2023-12.
Cc: Will Deacon <will@kernel.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
arch/arm64/tools/sysreg | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index c38414352dd8..7ba4fa99c160 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -1567,6 +1567,7 @@ EndEnum
UnsignedEnum 59:56 FGT
0b0000 NI
0b0001 IMP
+ 0b0010 FGT2
EndEnum
Res0 55:48
UnsignedEnum 47:44 EXS
@@ -1628,6 +1629,7 @@ Enum 3:0 PARANGE
0b0100 44
0b0101 48
0b0110 52
+ 0b0111 56
EndEnum
EndSysreg
--
2.25.1
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* [RFC 5/8] KVM: arm64: Explicitly handle MDSELR_EL1 traps as UNDEFINED
From: Anshuman Khandual @ 2024-04-05 8:00 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Anshuman Khandual, Jonathan Corbet, Marc Zyngier, Oliver Upton,
James Morse, Suzuki K Poulose, Catalin Marinas, Will Deacon,
Mark Brown, Mark Rutland, kvmarm, linux-kernel
In-Reply-To: <20240405080008.1225223-1-anshuman.khandual@arm.com>
Currently read_sanitised_id_aa64dfr0_el1() caps the ID_AA64DFR0.DebugVer to
ID_AA64DFR0_DebugVer_V8P8, resulting in FEAT_Debugv8p9 not being exposed to
the guest. MDSELR_EL1 register access in the guest, is currently trapped by
the existing configuration of the fine-grained traps.
As the register is not described in sys_reg_descs[] table emulate_sys_reg()
will warn that this is unknown access before injecting an UNDEFINED
exception into the guest. Any well-behaved guests shouldn't try to use this
register, but any badly-behaved guests could, thus resulting in unnecessary
warnings. To avoid such warnings, access to MDSELR_EL1 should be explicitly
handled as UNDEFINED via updating sys_reg_desc[] as required.
Cc: Marc Zyngier <maz@kernel.org>
Cc: Oliver Upton <oliver.upton@linux.dev>
Cc: James Morse <james.morse@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: kvmarm@lists.linux.dev
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
arch/arm64/kvm/sys_regs.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index c9f4f387155f..2956bdcd358e 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -2203,6 +2203,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
{ SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 },
DBG_BCR_BVR_WCR_WVR_EL1(2),
DBG_BCR_BVR_WCR_WVR_EL1(3),
+ { SYS_DESC(SYS_MDSELR_EL1), undef_access },
DBG_BCR_BVR_WCR_WVR_EL1(4),
DBG_BCR_BVR_WCR_WVR_EL1(5),
DBG_BCR_BVR_WCR_WVR_EL1(6),
--
2.25.1
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* [RFC 6/8] arm64/cpufeature: Add field details for ID_AA64DFR1_EL1 register
From: Anshuman Khandual @ 2024-04-05 8:00 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Anshuman Khandual, Jonathan Corbet, Marc Zyngier, Oliver Upton,
James Morse, Suzuki K Poulose, Catalin Marinas, Will Deacon,
Mark Brown, Mark Rutland, kvmarm, linux-kernel
In-Reply-To: <20240405080008.1225223-1-anshuman.khandual@arm.com>
This adds required field details for ID_AA64DFR1_EL1, and also drops dummy
ftr_raz[] array which is now redundant. These register fields will be used
to enable increased breakpoint and watchpoint registers via FEAT_Debugv8p9
later.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
cc: Mark Brown <broonie@kernel.org
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
arch/arm64/kernel/cpufeature.c | 21 ++++++++++++++++-----
1 file changed, 16 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 56583677c1f2..128f2836fc1e 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -527,6 +527,21 @@ static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
ARM64_FTR_END,
};
+static const struct arm64_ftr_bits ftr_id_aa64dfr1[] = {
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_ABL_CMPs_SHIFT, 8, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_DPFZS_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_EBEP_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_ITE_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_ABLE_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_PMICNTR_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_SPMU_SHIFT, 4, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_CTX_CMPs_SHIFT, 8, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_WRPs_SHIFT, 8, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_BRPs_SHIFT, 8, 0),
+ ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR1_EL1_SYSPMUID_SHIFT, 8, 0),
+ ARM64_FTR_END,
+};
+
static const struct arm64_ftr_bits ftr_mvfr0[] = {
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPRound_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPShVec_SHIFT, 4, 0),
@@ -705,10 +720,6 @@ static const struct arm64_ftr_bits ftr_single32[] = {
ARM64_FTR_END,
};
-static const struct arm64_ftr_bits ftr_raz[] = {
- ARM64_FTR_END,
-};
-
#define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \
.sys_id = id, \
.reg = &(struct arm64_ftr_reg){ \
@@ -781,7 +792,7 @@ static const struct __ftr_reg_entry {
/* Op1 = 0, CRn = 0, CRm = 5 */
ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
- ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
+ ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_id_aa64dfr1),
/* Op1 = 0, CRn = 0, CRm = 6 */
ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
--
2.25.1
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