* Re: [PATCH 1/6] dt-bindings: net: snps,dwmac: remove tx-sched-sp property
From: Krzysztof Kozlowski @ 2024-04-05 15:49 UTC (permalink / raw)
To: Flavio Suligoi, Alexandre Torgue, Jose Abreu, David S . Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Maxime Coquelin,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Bjorn Andersson, Konrad Dybcio, Giuseppe Cavallaro
Cc: netdev, linux-stm32, linux-arm-kernel, devicetree, imx,
linux-arm-msm, linux-kernel
In-Reply-To: <20240405152800.638461-2-f.suligoi@asem.it>
On 05/04/2024 17:27, Flavio Suligoi wrote:
> The property "tx-sched-sp" no longer exists, as it was removed from the
> file:
>
> drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
>
> by the commit:
Keep syntax as asked by submitting patches, so "by the commit sha ("foo
bar").
>
> commit aed6864035b1 ("net: stmmac: platform: Delete a redundant condition
> branch")
>
> Signed-off-by: Flavio Suligoi <f.suligoi@asem.it>
> ---
> .../devicetree/bindings/net/snps,dwmac.yaml | 14 --------------
> 1 file changed, 14 deletions(-)
This means by default we have tx-sched-sp... I guess it is fine,
assuming there are no other users (projects) of this binding property.
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Best regards,
Krzysztof
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* Re: [PATCH bpf-next] arm64, bpf: add internal-only MOV instruction to resolve per-CPU addrs
From: Alexei Starovoitov @ 2024-04-05 15:48 UTC (permalink / raw)
To: Puranjay Mohan
Cc: Catalin Marinas, Will Deacon, Alexei Starovoitov, Daniel Borkmann,
Andrii Nakryiko, Martin KaFai Lau, Eduard Zingerman, Song Liu,
Yonghong Song, John Fastabend, KP Singh, Stanislav Fomichev,
Hao Luo, Jiri Olsa, Zi Shen Lim, Xu Kuohai, Florent Revest,
linux-arm-kernel, LKML, bpf
In-Reply-To: <20240405091707.66675-1-puranjay12@gmail.com>
On Fri, Apr 5, 2024 at 2:17 AM Puranjay Mohan <puranjay12@gmail.com> wrote:
>
> Support an instruction for resolving absolute addresses of per-CPU
> data from their per-CPU offsets. This instruction is internal-only and
> users are not allowed to use them directly. They will only be used for
> internal inlining optimizations for now between BPF verifier and BPF
> JITs.
>
> Since commit 7158627686f0 ("arm64: percpu: implement optimised pcpu
> access using tpidr_el1"), the per-cpu offset for the CPU is stored in
> the tpidr_el1/2 register of that CPU.
>
> To support this BPF instruction in the ARM64 JIT, the following ARM64
> instructions are emitted:
>
> mov dst, src // Move src to dst, if src != dst
> mrs tmp, tpidr_el1/2 // Move per-cpu offset of the current cpu in tmp.
> add dst, dst, tmp // Add the per cpu offset to the dst.
>
> If CONFIG_SMP is not defined, then nothing is emitted if src == dst, and
> mov dst, src is emitted if dst != src.
>
> To measure the performance improvement provided by this change, the
> benchmark in [1] was used:
>
> Before:
> glob-arr-inc : 23.597 ± 0.012M/s
> arr-inc : 23.173 ± 0.019M/s
> hash-inc : 12.186 ± 0.028M/s
>
> After:
> glob-arr-inc : 23.819 ± 0.034M/s
> arr-inc : 23.285 ± 0.017M/s
> hash-inc : 12.419 ± 0.011M/s
>
> [1] https://github.com/anakryiko/linux/commit/8dec900975ef
You don't see as big of a gain, because bpf_get_smp_processor_id()
is not inlined yet on arm64.
But even without it I expected bigger gains.
Could you do 'perf report' before/after ?
Just want to see what's on top.
>
> Signed-off-by: Puranjay Mohan <puranjay12@gmail.com>
> ---
> arch/arm64/include/asm/insn.h | 7 +++++++
> arch/arm64/lib/insn.c | 11 +++++++++++
> arch/arm64/net/bpf_jit.h | 6 ++++++
> arch/arm64/net/bpf_jit_comp.c | 16 ++++++++++++++++
> 4 files changed, 40 insertions(+)
>
> diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h
> index db1aeacd4cd9..d16d68550c22 100644
> --- a/arch/arm64/include/asm/insn.h
> +++ b/arch/arm64/include/asm/insn.h
> @@ -135,6 +135,11 @@ enum aarch64_insn_special_register {
> AARCH64_INSN_SPCLREG_SP_EL2 = 0xF210
> };
>
> +enum aarch64_insn_system_register {
> + AARCH64_INSN_SYSREG_TPIDR_EL1 = 0xC684,
> + AARCH64_INSN_SYSREG_TPIDR_EL2 = 0xE682,
> +};
> +
> enum aarch64_insn_variant {
> AARCH64_INSN_VARIANT_32BIT,
> AARCH64_INSN_VARIANT_64BIT
> @@ -686,6 +691,8 @@ u32 aarch64_insn_gen_cas(enum aarch64_insn_register result,
> }
> #endif
> u32 aarch64_insn_gen_dmb(enum aarch64_insn_mb_type type);
> +u32 aarch64_insn_gen_mrs(enum aarch64_insn_register result,
> + enum aarch64_insn_system_register sysreg);
>
> s32 aarch64_get_branch_offset(u32 insn);
> u32 aarch64_set_branch_offset(u32 insn, s32 offset);
> diff --git a/arch/arm64/lib/insn.c b/arch/arm64/lib/insn.c
> index a635ab83fee3..b008a9b46a7f 100644
> --- a/arch/arm64/lib/insn.c
> +++ b/arch/arm64/lib/insn.c
> @@ -1515,3 +1515,14 @@ u32 aarch64_insn_gen_dmb(enum aarch64_insn_mb_type type)
>
> return insn;
> }
> +
> +u32 aarch64_insn_gen_mrs(enum aarch64_insn_register result,
> + enum aarch64_insn_system_register sysreg)
> +{
> + u32 insn = aarch64_insn_get_mrs_value();
> +
> + insn &= ~GENMASK(19, 0);
> + insn |= sysreg << 5;
> + return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RT,
> + insn, result);
> +}
> diff --git a/arch/arm64/net/bpf_jit.h b/arch/arm64/net/bpf_jit.h
> index 23b1b34db088..b627ef7188c7 100644
> --- a/arch/arm64/net/bpf_jit.h
> +++ b/arch/arm64/net/bpf_jit.h
> @@ -297,4 +297,10 @@
> #define A64_ADR(Rd, offset) \
> aarch64_insn_gen_adr(0, offset, Rd, AARCH64_INSN_ADR_TYPE_ADR)
>
> +/* MRS */
> +#define A64_MRS_TPIDR_EL1(Rt) \
> + aarch64_insn_gen_mrs(Rt, AARCH64_INSN_SYSREG_TPIDR_EL1)
> +#define A64_MRS_TPIDR_EL2(Rt) \
> + aarch64_insn_gen_mrs(Rt, AARCH64_INSN_SYSREG_TPIDR_EL2)
> +
> #endif /* _BPF_JIT_H */
> diff --git a/arch/arm64/net/bpf_jit_comp.c b/arch/arm64/net/bpf_jit_comp.c
> index 76b91f36c729..e9ad9f257a18 100644
> --- a/arch/arm64/net/bpf_jit_comp.c
> +++ b/arch/arm64/net/bpf_jit_comp.c
> @@ -877,6 +877,17 @@ static int build_insn(const struct bpf_insn *insn, struct jit_ctx *ctx,
> emit(A64_ORR(1, tmp, dst, tmp), ctx);
> emit(A64_MOV(1, dst, tmp), ctx);
> break;
> + } else if (insn_is_mov_percpu_addr(insn)) {
> + if (dst != src)
> + emit(A64_MOV(1, dst, src), ctx);
> +#ifdef CONFIG_SMP
> + if (cpus_have_cap(ARM64_HAS_VIRT_HOST_EXTN))
> + emit(A64_MRS_TPIDR_EL2(tmp), ctx);
> + else
> + emit(A64_MRS_TPIDR_EL1(tmp), ctx);
> + emit(A64_ADD(1, dst, dst, tmp), ctx);
> +#endif
> + break;
> }
> switch (insn->off) {
> case 0:
> @@ -2527,6 +2538,11 @@ bool bpf_jit_supports_arena(void)
> return true;
> }
>
> +bool bpf_jit_supports_percpu_insn(void)
> +{
> + return true;
> +}
> +
> void bpf_jit_free(struct bpf_prog *prog)
> {
> if (prog->jited) {
> --
> 2.40.1
>
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* Re: [PATCH RFT 10/10] arm64: dts: microchip: sparx5_pcb135: drop duplicated NOR flash
From: Krzysztof Kozlowski @ 2024-04-05 15:46 UTC (permalink / raw)
To: Steen Hegelund, Conor Dooley, Nicolas Ferre, Claudiu Beznea,
Rob Herring, Krzysztof Kozlowski, Lars Povlsen, Daniel Machon,
UNGLinuxDriver, David S. Miller, Bjarni Jonasson,
linux-arm-kernel, devicetree, linux-kernel
In-Reply-To: <66872c085710223d5bf43cd601cfbc3e54425bbc.camel@microchip.com>
On 05/04/2024 14:11, Steen Hegelund wrote:
>>
>> -&spi0 {
>> - status = "okay";
>> - spi@0 {
>> - compatible = "spi-mux";
>> - mux-controls = <&mux>;
>> - #address-cells = <1>;
>> - #size-cells = <0>;
>> - reg = <0>; /* CS0 */
>> - flash@9 {
>> - compatible = "jedec,spi-nor";
>> - spi-max-frequency = <8000000>;
>> - reg = <0x9>; /* SPI */
>> - };
>> - };
>> -};
>> -
>
> I also tested this, and no surprise: same comment as for the pcb134 patch...
Thanks, I will send v2.
Best regards,
Krzysztof
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* Re: [PATCH RFT 09/10] arm64: dts: microchip: sparx5_pcb134: drop duplicated NOR flash
From: Krzysztof Kozlowski @ 2024-04-05 15:45 UTC (permalink / raw)
To: Steen Hegelund, Conor Dooley, Nicolas Ferre, Claudiu Beznea,
Rob Herring, Krzysztof Kozlowski, Lars Povlsen, Daniel Machon,
UNGLinuxDriver, David S. Miller, Bjarni Jonasson,
linux-arm-kernel, devicetree, linux-kernel
In-Reply-To: <67f29fa86207a68b148b826b71b1349d3552453d.camel@microchip.com>
On 05/04/2024 14:10, Steen Hegelund wrote:
> Hi Krzysztof,
>
> On Mon, 2024-04-01 at 17:37 +0200, Krzysztof Kozlowski wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>
>> Since beginning the DTS extended the SPI0 in two places adding two SPI
>> muxes, each with same SPI NOR flash. Both used exactly the same
>> chip-selects, so this was clearly buggy code. Without checking in
>> datasheet, assume device has only one SPI NOR flash, so code was
>> duplicated.
>>
>> Fixes dtc W=1 warnings:
>>
>> sparx5_pcb134_board.dtsi:277.10-281.4: Warning (unique_unit_address_if_enabled):
>> /axi@600000000/spi@600104000/flash@0: duplicate unit-address (also used in node
>> /axi@600000000/spi@600104000/spi@0)
>>
>> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
>>
>> ---
>>
>> Not tested on hardware
>> ---
>> .../boot/dts/microchip/sparx5_pcb134_board.dtsi | 16 ----------------
>> 1 file changed, 16 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
>> b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
>> index f165a409bc1d..dc7b59dfcb40 100644
>> --- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
>> +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi
>> @@ -281,22 +281,6 @@ flash@0 {
>> };
>> };
>>
>> -&spi0 {
>> - status = "okay";
>> - spi@0 {
>> - compatible = "spi-mux";
>> - mux-controls = <&mux>;
>> - #address-cells = <1>;
>> - #size-cells = <0>;
>> - reg = <0>; /* CS0 */
>> - flash@9 {
>> - compatible = "jedec,spi-nor";
>> - spi-max-frequency = <8000000>;
>> - reg = <0x9>; /* SPI */
>> - };
>> - };
>> -};
>> -
>
> When testing this on actual HW the SPI NOR is no longer accessible.
> The reason is that it sits behind a SPI-MUX and that needs to be present in the Device Tree.
>
> So if you do the "reverse" clean-up it works fine: Remove the simple spi0 node and keep the one that
> has the spi-mux reference.
Aaaa, so we need to do it that way. Thanks for testing! I'll send v2.
Best regards,
Krzysztof
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^ permalink raw reply
* Re: [PATCH v6 05/16] dt-bindings: net: wireless: describe the ath12k PCI module
From: Jeff Johnson @ 2024-04-05 15:44 UTC (permalink / raw)
To: Bartosz Golaszewski, Kalle Valo
Cc: Marcel Holtmann, Luiz Augusto von Dentz, David S . Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Konrad Dybcio,
Liam Girdwood, Mark Brown, Catalin Marinas, Will Deacon,
Bjorn Helgaas, Saravana Kannan, Geert Uytterhoeven, Arnd Bergmann,
Neil Armstrong, Marek Szyprowski, Alex Elder, Srini Kandagatla,
Greg Kroah-Hartman, Abel Vesa, Manivannan Sadhasivam,
Lukas Wunner, Dmitry Baryshkov, linux-bluetooth, netdev,
devicetree, linux-kernel, linux-wireless, linux-arm-msm,
linux-arm-kernel, linux-pci, linux-pm, Bartosz Golaszewski
In-Reply-To: <CAMRc=MdzhGxLNcNLWvRfqr0S9pey-iw964=AcYx_yDXgyDDjMA@mail.gmail.com>
On 4/5/2024 2:52 AM, Bartosz Golaszewski wrote:
> In addition to what Krzysztof already said about you seamingly
> confusing the maintenance of the driver vs maintenance of the
> device-tree bindings (IOW: structured hardware description) and in
> response to your question: I don't see any functional change to any
> dt-bindings neither from you nor from Jeff. Are you convinced you can
> maintain and properly review any changes?
Speaking just for myself, I know Bartosz is far more capable in this regard
than I am, so I'd expect him to be listed as a maintainer before me.
/jeff
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* [PATCH 0/6] Remove stmmac tx-sched-sp property from documentation and DT
From: Flavio Suligoi @ 2024-04-05 15:27 UTC (permalink / raw)
To: Alexandre Torgue, Jose Abreu, David S . Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Maxime Coquelin, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Bjorn Andersson,
Konrad Dybcio, Giuseppe Cavallaro
Cc: netdev, linux-stm32, linux-arm-kernel, devicetree, imx,
linux-arm-msm, linux-kernel, Flavio Suligoi
The property "tx-sched-sp" no longer exists, as it was removed from the
file:
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
by the commit:
commit aed6864035b1 ("net: stmmac: platform: Delete a redundant condition
branch")
This patch serie remove this property both from the "snps,dwmac.yaml"
documentation and from some device-tree boards files where was still used.
Flavio Suligoi (6):
dt-bindings: net: snps,dwmac: remove tx-sched-sp property
arm64: dts: imx8mp-beacon: remove tx-sched-sp property
arm64: dts: imx8mp-evk: remove tx-sched-sp property
arm64: dts: imx8mp-verdin: remove tx-sched-sp property
arm64: dts: qcom: sa8540p-ride: remove tx-sched-sp property
dts: qcom: sa8775p-ride: remove tx-sched-sp property
.../devicetree/bindings/net/snps,dwmac.yaml | 14 --------------
.../boot/dts/freescale/imx8mp-beacon-som.dtsi | 1 -
arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 1 -
arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi | 1 -
arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 2 --
arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 2 --
6 files changed, 21 deletions(-)
--
2.34.1
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* [PATCH 5/6] arm64: dts: qcom: sa8540p-ride: remove tx-sched-sp property
From: Flavio Suligoi @ 2024-04-05 15:27 UTC (permalink / raw)
To: Alexandre Torgue, Jose Abreu, David S . Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Maxime Coquelin, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Bjorn Andersson,
Konrad Dybcio, Giuseppe Cavallaro
Cc: netdev, linux-stm32, linux-arm-kernel, devicetree, imx,
linux-arm-msm, linux-kernel, Flavio Suligoi
In-Reply-To: <20240405152800.638461-1-f.suligoi@asem.it>
The property "tx-sched-sp" no longer exists, as it was removed from the
file:
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
by the commit:
commit aed6864035b1 ("net: stmmac: platform: Delete a redundant condition
branch")
Signed-off-by: Flavio Suligoi <f.suligoi@asem.it>
---
arch/arm64/boot/dts/qcom/sa8540p-ride.dts | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
index 177b9dad6ff7..11663cf81e45 100644
--- a/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
+++ b/arch/arm64/boot/dts/qcom/sa8540p-ride.dts
@@ -225,7 +225,6 @@ queue3 {
ethernet0_mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <1>;
- snps,tx-sched-sp;
queue0 {
snps,dcb-algorithm;
@@ -302,7 +301,6 @@ queue3 {
ethernet1_mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <1>;
- snps,tx-sched-sp;
queue0 {
snps,dcb-algorithm;
--
2.34.1
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* [PATCH 4/6] arm64: dts: imx8mp-verdin: remove tx-sched-sp property
From: Flavio Suligoi @ 2024-04-05 15:27 UTC (permalink / raw)
To: Alexandre Torgue, Jose Abreu, David S . Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Maxime Coquelin, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Bjorn Andersson,
Konrad Dybcio, Giuseppe Cavallaro
Cc: netdev, linux-stm32, linux-arm-kernel, devicetree, imx,
linux-arm-msm, linux-kernel, Flavio Suligoi
In-Reply-To: <20240405152800.638461-1-f.suligoi@asem.it>
The property "tx-sched-sp" no longer exists, as it was removed from the
file:
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
by the commit:
commit aed6864035b1 ("net: stmmac: platform: Delete a redundant condition
branch")
Signed-off-by: Flavio Suligoi <f.suligoi@asem.it>
---
arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
index f033d4310305..5b1b36a7ad38 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
@@ -260,7 +260,6 @@ queue4 {
mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <5>;
- snps,tx-sched-sp;
queue0 {
snps,dcb-algorithm;
--
2.34.1
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* [PATCH 1/6] dt-bindings: net: snps,dwmac: remove tx-sched-sp property
From: Flavio Suligoi @ 2024-04-05 15:27 UTC (permalink / raw)
To: Alexandre Torgue, Jose Abreu, David S . Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Maxime Coquelin, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Bjorn Andersson,
Konrad Dybcio, Giuseppe Cavallaro
Cc: netdev, linux-stm32, linux-arm-kernel, devicetree, imx,
linux-arm-msm, linux-kernel, Flavio Suligoi
In-Reply-To: <20240405152800.638461-1-f.suligoi@asem.it>
The property "tx-sched-sp" no longer exists, as it was removed from the
file:
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
by the commit:
commit aed6864035b1 ("net: stmmac: platform: Delete a redundant condition
branch")
Signed-off-by: Flavio Suligoi <f.suligoi@asem.it>
---
.../devicetree/bindings/net/snps,dwmac.yaml | 14 --------------
1 file changed, 14 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml
index 15073627c53a..21cc27e75f50 100644
--- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml
+++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml
@@ -328,9 +328,6 @@ properties:
snps,tx-sched-dwrr:
type: boolean
description: Deficit Weighted Round Robin
- snps,tx-sched-sp:
- type: boolean
- description: Strict priority
allOf:
- if:
required:
@@ -339,7 +336,6 @@ properties:
properties:
snps,tx-sched-wfq: false
snps,tx-sched-dwrr: false
- snps,tx-sched-sp: false
- if:
required:
- snps,tx-sched-wfq
@@ -347,7 +343,6 @@ properties:
properties:
snps,tx-sched-wrr: false
snps,tx-sched-dwrr: false
- snps,tx-sched-sp: false
- if:
required:
- snps,tx-sched-dwrr
@@ -355,15 +350,6 @@ properties:
properties:
snps,tx-sched-wrr: false
snps,tx-sched-wfq: false
- snps,tx-sched-sp: false
- - if:
- required:
- - snps,tx-sched-sp
- then:
- properties:
- snps,tx-sched-wrr: false
- snps,tx-sched-wfq: false
- snps,tx-sched-dwrr: false
patternProperties:
"^queue[0-9]$":
description: Each subnode represents a queue.
--
2.34.1
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^ permalink raw reply related
* [PATCH 3/6] arm64: dts: imx8mp-evk: remove tx-sched-sp property
From: Flavio Suligoi @ 2024-04-05 15:27 UTC (permalink / raw)
To: Alexandre Torgue, Jose Abreu, David S . Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Maxime Coquelin, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Bjorn Andersson,
Konrad Dybcio, Giuseppe Cavallaro
Cc: netdev, linux-stm32, linux-arm-kernel, devicetree, imx,
linux-arm-msm, linux-kernel, Flavio Suligoi
In-Reply-To: <20240405152800.638461-1-f.suligoi@asem.it>
The property "tx-sched-sp" no longer exists, as it was removed from the
file:
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
by the commit:
commit aed6864035b1 ("net: stmmac: platform: Delete a redundant condition
branch")
Signed-off-by: Flavio Suligoi <f.suligoi@asem.it>
---
arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
index 8be5b2a57f27..bb1003363e3e 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
@@ -251,7 +251,6 @@ ethphy0: ethernet-phy@1 {
mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <5>;
- snps,tx-sched-sp;
queue0 {
snps,dcb-algorithm;
--
2.34.1
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^ permalink raw reply related
* [PATCH 2/6] arm64: dts: imx8mp-beacon: remove tx-sched-sp property
From: Flavio Suligoi @ 2024-04-05 15:27 UTC (permalink / raw)
To: Alexandre Torgue, Jose Abreu, David S . Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Maxime Coquelin, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Bjorn Andersson,
Konrad Dybcio, Giuseppe Cavallaro
Cc: netdev, linux-stm32, linux-arm-kernel, devicetree, imx,
linux-arm-msm, linux-kernel, Flavio Suligoi
In-Reply-To: <20240405152800.638461-1-f.suligoi@asem.it>
The property "tx-sched-sp" no longer exists, as it was removed from the
file:
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
by the commit:
commit aed6864035b1 ("net: stmmac: platform: Delete a redundant condition
branch")
Signed-off-by: Flavio Suligoi <f.suligoi@asem.it>
---
arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi
index 8be251b69378..34339dc4a635 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-beacon-som.dtsi
@@ -106,7 +106,6 @@ queue4 {
mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <5>;
- snps,tx-sched-sp;
queue0 {
snps,dcb-algorithm;
--
2.34.1
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^ permalink raw reply related
* [PATCH 6/6] dts: qcom: sa8775p-ride: remove tx-sched-sp property
From: Flavio Suligoi @ 2024-04-05 15:28 UTC (permalink / raw)
To: Alexandre Torgue, Jose Abreu, David S . Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Maxime Coquelin, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Bjorn Andersson,
Konrad Dybcio, Giuseppe Cavallaro
Cc: netdev, linux-stm32, linux-arm-kernel, devicetree, imx,
linux-arm-msm, linux-kernel, Flavio Suligoi
In-Reply-To: <20240405152800.638461-1-f.suligoi@asem.it>
The property "tx-sched-sp" no longer exists, as it was removed from the
file:
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c
by the commit:
commit aed6864035b1 ("net: stmmac: platform: Delete a redundant condition
branch")
Signed-off-by: Flavio Suligoi <f.suligoi@asem.it>
---
arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 2 --
1 file changed, 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
index 26ad05bd3b3f..2e1770e07f45 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
+++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
@@ -334,7 +334,6 @@ queue3 {
mtl_tx_setup: tx-queues-config {
snps,tx-queues-to-use = <4>;
- snps,tx-sched-sp;
queue0 {
snps,dcb-algorithm;
@@ -404,7 +403,6 @@ queue3 {
mtl_tx_setup1: tx-queues-config {
snps,tx-queues-to-use = <4>;
- snps,tx-sched-sp;
queue0 {
snps,dcb-algorithm;
--
2.34.1
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^ permalink raw reply related
* Re: sa8775p-ride: What's a normal SMMU TLB sync time?
From: Andrew Halaney @ 2024-04-05 14:04 UTC (permalink / raw)
To: Bjorn Andersson
Cc: linux-arm-msm, robdclark, will, iommu, joro, linux-arm-kernel,
linux-kernel, quic_c_gdjako, quic_cgoldswo, quic_sukadev,
quic_pdaly, quic_sudaraja
In-Reply-To: <Zg9vEJV5JyGoM8KY@hu-bjorande-lv.qualcomm.com>
On Thu, Apr 04, 2024 at 08:25:04PM -0700, Bjorn Andersson wrote:
> On Tue, Apr 02, 2024 at 04:22:31PM -0500, Andrew Halaney wrote:
> > Hey,
> >
> > Sorry for the wide email, but I figured someone recently contributing
> > to / maintaining the Qualcomm SMMU driver may have some proper insights
> > into this.
> >
> > Recently I remembered that performance on some Qualcomm platforms
> > takes a major hit when you use iommu.strict=1/CONFIG_IOMMU_DEFAULT_DMA_STRICT.
> >
> > On the sa8775p-ride, I see most TLB sync calls to be about 150 us long,
> > with some spiking to 500 us, etc:
> >
> > [root@qti-snapdragon-ride4-sa8775p-09 ~]# trace-cmd start -p function_graph -g qcom_smmu_tlb_sync --max-graph-depth 1
> > plugin 'function_graph'
> > [root@qti-snapdragon-ride4-sa8775p-09 ~]# trace-cmd show
> > # tracer: function_graph
> > #
> > # CPU DURATION FUNCTION CALLS
> > # | | | | | | |
> > 0) ! 144.062 us | qcom_smmu_tlb_sync();
> >
> > On my sc8280xp-lenovo-thinkpad-x13s (only other Qualcomm platform I can compare
> > with) I see around 2-15 us with spikes up to 20-30 us. That's thanks to this
> > patch[0], which I guess improved the platform from 1-2 ms to the ~10 us number.
> >
> > It's not entirely clear to me how a DPU specific programming affects system
> > wide SMMU performance, but I'm curious if this is the only way to achieve this?
> > sa8775p doesn't have the DPU described even right now, so that's a bummer
> > as there's no way to make a similar immediate optimization, but I'm still struggling
> > to understand what that patch really did to improve things so maybe I'm missing
> > something.
> >
>
> The cause was that the TLB sync is synchronized with the display updates,
> but without appropriate safe_lut_tlb values the display side wouldn't
> play nice.
In my case we don't have display being driven at all. I'm not sure if
that changes the situation, or just complicates it. i.e. I'm unsure if
that means we're not hitting the display situation at all but something
else entirely (assuming this time is longer than ideal), or if the
safe_lut_tlb values still effect things despite Linux knowing nothing
about the display, which as far as I know is not configured by anyone
at the moment.
Any thoughts on that?
>
> Regards,
> Bjorn
>
> > I'm honestly not even sure what a "typical" range for TLB sync time would be,
> > but on sa8775p-ride its bad enough that some IRQs like UFS can cause RCU stalls
> > (pretty easy to reproduce with fio basic-verify.fio for example on the platform).
> > It also makes running with iommu.strict=1 impractical as performance for UFS,
> > ethernet, etc drops 75-80%.
> >
> > Does anyone have any bright ideas on how to improve this, or if I'm even in
> > the right for assuming that time is suspiciously long?
> >
> > Thanks,
> > Andrew
> >
> > [0] https://lore.kernel.org/linux-arm-msm/CAF6AEGs9PLiCZdJ-g42-bE6f9yMR6cMyKRdWOY5m799vF9o4SQ@mail.gmail.com/
> >
>
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^ permalink raw reply
* Re: [PATCH v17 11/35] virt: gunyah: Translate gh_rm_hyp_resource into gunyah_resource
From: Elliot Berman @ 2024-04-05 15:18 UTC (permalink / raw)
To: Pavan Kondeti
Cc: Alex Elder, Srinivas Kandagatla, Murali Nalajal, Trilok Soni,
Srivatsa Vaddagiri, Carl van Schaik, Philip Derrin,
Prakruthi Deepak Heragu, Jonathan Corbet, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Catalin Marinas, Will Deacon,
Konrad Dybcio, Bjorn Andersson, Dmitry Baryshkov, Fuad Tabba,
Sean Christopherson, Andrew Morton, linux-arm-msm, linux-doc,
linux-kernel, devicetree, linux-arm-kernel, linux-mm
In-Reply-To: <ff6a3fb2-5f1a-4baa-b42a-a7767e92885a@quicinc.com>
On Fri, Apr 05, 2024 at 08:40:40AM +0530, Pavan Kondeti wrote:
> On Thu, Feb 22, 2024 at 03:16:34PM -0800, Elliot Berman wrote:
> > When booting a Gunyah virtual machine, the host VM may gain capabilities
> > to interact with resources for the guest virtual machine. Examples of
> > such resources are vCPUs or message queues. To use those resources, we
> > need to translate the RM response into a gunyah_resource structure which
> > are useful to Linux drivers. Presently, Linux drivers need only to know
> > the type of resource, the capability ID, and an interrupt.
> >
> > On ARM64 systems, the interrupt reported by Gunyah is the GIC interrupt
> > ID number and always a SPI or extended SPI.
> >
> > Signed-off-by: Elliot Berman <quic_eberman@quicinc.com>
> > ---
> > arch/arm64/include/asm/gunyah.h | 36 ++++++++++++++++++++++
> > drivers/virt/gunyah/rsc_mgr.c | 67 +++++++++++++++++++++++++++++++++++++++++
> > drivers/virt/gunyah/rsc_mgr.h | 5 +++
> > include/linux/gunyah.h | 2 ++
> > 4 files changed, 110 insertions(+)
> >
> > diff --git a/arch/arm64/include/asm/gunyah.h b/arch/arm64/include/asm/gunyah.h
> > new file mode 100644
> > index 0000000000000..0cd3debe22b64
> > --- /dev/null
> > +++ b/arch/arm64/include/asm/gunyah.h
> > @@ -0,0 +1,36 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
> > + */
> > +#ifndef _ASM_GUNYAH_H
> > +#define _ASM_GUNYAH_H
> > +
> > +#include <linux/irq.h>
> > +#include <linux/irqdomain.h>
> > +
> > +static inline int arch_gunyah_fill_irq_fwspec_params(u32 virq,
> > + struct irq_fwspec *fwspec)
> > +{
> > + /* Assume that Gunyah gave us an SPI or ESPI; defensively check it */
> > + if (WARN(virq < 32, "Unexpected virq: %d\n", virq)) {
> > + return -EINVAL;
> > + } else if (virq <= 1019) {
> > + fwspec->param_count = 3;
> > + fwspec->param[0] = 0; /* GIC_SPI */
> > + fwspec->param[1] = virq - 32; /* virq 32 -> SPI 0 */
> > + fwspec->param[2] = IRQ_TYPE_EDGE_RISING;
> > + } else if (WARN(virq < 4096, "Unexpected virq: %d\n", virq)) {
> > + return -EINVAL;
> > + } else if (virq < 5120) {
> > + fwspec->param_count = 3;
> > + fwspec->param[0] = 2; /* GIC_ESPI */
> > + fwspec->param[1] = virq - 4096; /* virq 4096 -> ESPI 0 */
> > + fwspec->param[2] = IRQ_TYPE_EDGE_RISING;
> > + } else {
> > + WARN(1, "Unexpected virq: %d\n", virq);
> > + return -EINVAL;
> > + }
> > + return 0;
> > +}
> > +
>
> __get_intid_range() in gic-v3 driver looks more pleasing. Other than
> that the logic for the translation looks good to me.
Agreed, updated for v18.
static inline int arch_gunyah_fill_irq_fwspec_params(u32 virq,
struct irq_fwspec *fwspec)
{
/* Assume that Gunyah gave us an SPI or ESPI; defensively check it */
switch (virq) {
case 32 ... 1019:
fwspec->param_count = 3;
fwspec->param[0] = 0; /* GIC_SPI */
fwspec->param[1] = virq - 32; /* virq 32 -> SPI 0 */
fwspec->param[2] = IRQ_TYPE_EDGE_RISING;
break;
case 4096 ... 5119:
fwspec->param_count = 3;
fwspec->param[0] = 2; /* GIC_ESPI */
fwspec->param[1] = virq - 4096; /* virq 4096 -> ESPI 0 */
fwspec->param[2] = IRQ_TYPE_EDGE_RISING;
break;
default:
WARN(1, "Unexpected virq: %d\n", virq)
return -EINVAL;
}
return 0;
}
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^ permalink raw reply
* Re: [PATCH v2 02/18] PCI: endpoint: Introduce pci_epc_map_align()
From: Niklas Cassel @ 2024-04-05 15:18 UTC (permalink / raw)
To: Damien Le Moal
Cc: Kishon Vijay Abraham I, Manivannan Sadhasivam, Lorenzo Pieralisi,
Kishon Vijay Abraham I, Shawn Lin, Krzysztof Wilczyński,
Bjorn Helgaas, Heiko Stuebner, linux-pci, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, devicetree, linux-rockchip,
linux-arm-kernel, Rick Wertenbroek, Wilfred Mallawa
In-Reply-To: <9b3cfd8a-640d-4645-83a9-ddaa34cd09cd@kernel.org>
On Fri, Apr 05, 2024 at 09:43:42PM +0900, Damien Le Moal wrote:
> On 4/5/24 21:20, Niklas Cassel wrote:
> >
> > Now I understand that rockchip is the first one that does not have a fixed
> > alignment.
> > So for that platform, map_align() will be different from ep->page_size.
> > (For all DWC based drivers the outbound iATU alignment requirement is
> > the same as the page size.)
>
> Yes. So we can have a generic map_align() implementation that all these drivers
> can use as there .map_align method. No need to expose page size to the epc/epf
> core code.
I don't follow.
ep->page_size is used by pci_epc_multi_mem_init(), pci_epc_mem_alloc_addr()
and pci_epc_mem_free_addr(), so it is used by EPC core.
pci_epc_mem_alloc_addr() currently uses it to align up an allocation to the
page size, so that an allocation from the PCI window/memory space is a multiple
of page_size. How can we avoid exposing the page size to EPC core?
For a DWC-based driver, the mapping part requires that the start address of
the mapping should be aligned to the page size.
But e.g.
drivers/pci/controller/pcie-rockchip-ep.c, sets page size (smallest allocation):
to 1 MB:
windows[i].page_size = SZ_1M;
But the mapping part for rockchip-ep appears to have different requirements.
>
> > However, it would be nice if:
> > 1) We could have a default implementation of map_align() that by default uses
> > ep->page_size. Platforms that have non-fixed alignment requirements could
> > define their own map_align().
>
> See above. The default implementation can be a helper function defined in epc
> core that the drivers can use for their .map_align() method.
Sounds good.
> > 2) We fix dw_pcie_ep_raise_msi_irq() and dw_pcie_ep_raise_msix_irq() to use
> > the new pci_epc_map_align().
>
> Why ? That is completely internal to the controller driver.
Well, dw_pcie_ep_raise_msi_irq() and dw_pcie_ep_raise_msix_irq() currently does
some clearing of lower bits of the address before using .map_addr() to map the
an aligned outbound address. It will then write to the mapped address + some
offset.
Since it is already using .map_addr(), it seems like the perfect use case for
pci_epc_map_align(), as the function then would not need to do any clearing
of lower bits before mapping, nor writing to an offset within the mapping.
It would just use pci_epc_map_align() and then write to map->pci_addr.
> > 3) It is getting too complicated with all these...
> > epc_features->align, ep->page_size, map_align(), and .alignment in host driver.
> > I think that we need to document each of these in Documentation/PCI/endpoint/
>
> test host driver .alignment needs to be nuked. That one is nonsense.
> ep->page_size needs to stay internal to the driver. .map_align method is enough
> to handle any PCI address mapping constraint and will indicate memory size to
> allocate, offset into it etc. And for the BARs alignment, .align feature is not
> exactly great as it is not clear, but it is enough I think. So we could just
> rename it to be clear. And even maybe remove it from features. I do not see why
> an EPF needs to care about it given that epc core funstions are used to setup
> the bars.
+1 on renaming it to bar_alignment or inbound_alignment or similar.
I don't think that we can remove it from epc_features. It is used by
pci_epf_alloc_space() which uses epc_features->align to ensure that
when an EPF driver allocates the backing memory for a BAR, the backing
memory is aligned to bar_alignment. (An allocation of size X is guaranteed
to be aligned to X.)
> > 4) It would be nice if we could set page_size correctly for all the PCI device
> > and vendor IDs that have defined an .alignment in drivers/misc/pci_endpoint_test.c
> > in the correct EPC driver. That way, we should be able to completely remove all
> > .alignment specified in drivers/misc/pci_endpoint_test.c.
>
> The host side should be allowed to use any PCI address alignment it wants. So no
> alignment communicated at all. It is the EP side that needs to deal with alignment.
I think we are saying the same thing.
But in order to remove all .alignment uses in drivers/misc/pci_endpoint_test.c,
we will need to add modify the corresponding EPC driver to either:
- Define the ep->page_size, so that the generic map_align() implementation will
work.
(If you grep for page_size in drivers/pci/controller, you will see that
very few EPC drivers currently set ep->page_size, even though the PCI device
and vendor IDs for those same controllers have specified an alignment in
drivers/misc/pci_endpoint_test.c)
- Define a custom map_align() implementation.
> > 5) Unfortunately drivers/misc/pci_endpoint_test.c defines a default alignment
> > of 4K:
> > https://github.com/torvalds/linux/blob/v6.9-rc2/drivers/misc/pci_endpoint_test.c#L968
> > https://github.com/torvalds/linux/blob/v6.9-rc2/drivers/misc/pci_endpoint_test.c#L820
> >
> > It would be nice if we could get rid of this as well. Or perhaps add an option
> > to pci_test so that it does not use this 4k alignment, such that we can verify
> > that pci_epc_map_align() is actually working.
>
> Exactly. Get rid of any default alignment, add a test parameter to define one so
> that we can test different alignment+size combinations.
>
> > In my opinion 4) is the biggest win with this series, because it means that
> > we define the alignment in the EPC driver, instead of needing to define it in
> > each and every host side driver. But right now, this great improvement is not
> > really visible for someone looking quickly at the current series.
>
> Yes. Once in place, we can rework the test driver alignment stuff to make it
> optional instead of mandatory because of bad handling on the EP side :)
Perhaps it would be nice to have 5) implemented for this initial series,
so that it is possible to test that this new API is behaving as intended?
Kind regards,
Niklas
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^ permalink raw reply
* Re: [PATCH v15 2/8] phy: Add HDMI configuration options
From: Dmitry Baryshkov @ 2024-04-05 15:09 UTC (permalink / raw)
To: Vinod Koul
Cc: Maxime Ripard, Alexander Stein, Andrzej Hajda, Neil Armstrong,
Robert Foss, Laurent Pinchart, Jonas Karlman, Jernej Skrabec,
David Airlie, Daniel Vetter, Maarten Lankhorst, Thomas Zimmermann,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Kishon Vijay Abraham I, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, Sandor Yu, dri-devel,
devicetree, linux-kernel, linux-phy, imx, linux-arm-kernel, linux
In-Reply-To: <ZhAJridEyhUeFVr0@matsya>
On Fri, Apr 05, 2024 at 07:54:46PM +0530, Vinod Koul wrote:
> On 06-03-24, 15:48, Maxime Ripard wrote:
> > Hi Alexander,
> >
> > On Wed, Mar 06, 2024 at 11:16:19AM +0100, Alexander Stein wrote:
> > > From: Sandor Yu <Sandor.yu@nxp.com>
> > >
> > > Allow HDMI PHYs to be configured through the generic
> > > functions through a custom structure added to the generic union.
> > >
> > > The parameters added here are based on HDMI PHY
> > > implementation practices. The current set of parameters
> > > should cover the potential users.
> > >
> > > Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
> > > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > > Acked-by: Vinod Koul <vkoul@kernel.org>
> > > ---
> > > include/linux/phy/phy-hdmi.h | 24 ++++++++++++++++++++++++
> > > include/linux/phy/phy.h | 7 ++++++-
> > > 2 files changed, 30 insertions(+), 1 deletion(-)
> > > create mode 100644 include/linux/phy/phy-hdmi.h
> > >
> > > diff --git a/include/linux/phy/phy-hdmi.h b/include/linux/phy/phy-hdmi.h
> > > new file mode 100644
> > > index 0000000000000..b7de88e9090f0
> > > --- /dev/null
> > > +++ b/include/linux/phy/phy-hdmi.h
> > > @@ -0,0 +1,24 @@
> > > +/* SPDX-License-Identifier: GPL-2.0 */
> > > +/*
> > > + * Copyright 2022 NXP
> > > + */
> > > +
> > > +#ifndef __PHY_HDMI_H_
> > > +#define __PHY_HDMI_H_
> > > +
> > > +#include <linux/hdmi.h>
> > > +/**
> > > + * struct phy_configure_opts_hdmi - HDMI configuration set
> > > + * @pixel_clk_rate: Pixel clock of video modes in KHz.
> > > + * @bpc: Maximum bits per color channel.
> > > + * @color_space: Colorspace in enum hdmi_colorspace.
> > > + *
> > > + * This structure is used to represent the configuration state of a HDMI phy.
> > > + */
> > > +struct phy_configure_opts_hdmi {
> > > + unsigned int pixel_clk_rate;
> > > + unsigned int bpc;
> > > + enum hdmi_colorspace color_space;
> > > +};
> >
> > Does the PHY actually care about the pixel clock rate, color space and
> > formats, or does it only care about the character rate?
>
> Nope it should not
After taking a look at the Cadence PHY driver, I share the feeling that
hdptx_hdmi_feedback_factor() should be reworked into drm_display helper
and then the struct phy_configure_opts_hdmi can be limited to having a
single unsigned long char_freq or bit_rate field.
I'm not sure whether we need anything corresponding to the TMDS Bit
Clock Ratio control. As far as I understand, it can be deduced from the
Bit Rate.
--
With best wishes
Dmitry
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^ permalink raw reply
* Re: [PATCH 1/1] arm64: dts: imx8qxp-mek: add cm40_i2c, wm8960/wm8962 and sai[0,1,4,5]
From: Frank Li @ 2024-04-05 14:56 UTC (permalink / raw)
To: Francesco Dolcini
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
open list
In-Reply-To: <20240405063648.GA4562@francesco-nb>
On Fri, Apr 05, 2024 at 08:36:48AM +0200, Francesco Dolcini wrote:
> Hello Frank,
>
> On Thu, Apr 04, 2024 at 12:19:13PM -0400, Frank Li wrote:
> > imx8qxp-mek use two kind audio codec, wm8960 and wm8962. Using dummy gpio
> > i2c bus mux to connect both i2c devices. One will probe failure and other
> > will probe success when devices driver check whoami. So one dtb can cover
> > both board configuration.
> >
> > Signed-off-by: Frank Li <Frank.Li@nxp.com>
> > ---
> > arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 210 ++++++++++++++++++
> > 1 file changed, 210 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
> > index 8360bb851ac03..adff87c7cf305 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
> > +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
> > @@ -44,6 +51,105 @@ usb3_data_ss: endpoint {
>
> [...]
>
> > + /*
> > + * This dummy i2c mux. GPIO actually will not impact selection. At actual boards, only 1
> > + * device connectted. I2C client driver will check ID when probe. Only matched ID's driver
> > + * probe successfully.
> > + */
> > + i2cvmux: i2cmux {
> > + compatible = "i2c-mux-gpio";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + mux-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_HIGH>; /* use an unused gpio */
>
> There is for sure people that have more experience and competency that
> me and it would be interesting to hear their feedback, but this
> looks like a bad hack, and you are just playing with the driver
> behavior to ensure that you get what you need.
We want to use one dtb to handle differecne bench boards because some chips
are out of life-cycle. I don't think it is 'hack' although not
straightforward.
check woiam is quite common at i2c drivers. All used method is quite
common, I just change it from difference point.
>
> Francesco
>
>
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^ permalink raw reply
* Re: [PATCH v15 6/8] phy: freescale: Add DisplayPort/HDMI Combo-PHY driver for i.MX8MQ
From: Vinod Koul @ 2024-04-05 14:52 UTC (permalink / raw)
To: Alexander Stein
Cc: Andrzej Hajda, Neil Armstrong, Robert Foss, Laurent Pinchart,
Jonas Karlman, Jernej Skrabec, David Airlie, Daniel Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Kishon Vijay Abraham I,
Shawn Guo, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Sandor Yu, dri-devel, devicetree, linux-kernel, linux-phy, imx,
linux-arm-kernel, linux
In-Reply-To: <20240306101625.795732-7-alexander.stein@ew.tq-group.com>
On 06-03-24, 11:16, Alexander Stein wrote:
> From: Sandor Yu <Sandor.yu@nxp.com>
>
> Add Cadence HDP-TX DisplayPort and HDMI PHY driver for i.MX8MQ.
>
> Cadence HDP-TX PHY could be put in either DP mode or
> HDMI mode base on the configuration chosen.
> DisplayPort or HDMI PHY mode is configured in the driver.
>
> Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> ---
> drivers/phy/freescale/Kconfig | 10 +
> drivers/phy/freescale/Makefile | 1 +
> drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c | 1402 ++++++++++++++++++
> 3 files changed, 1413 insertions(+)
> create mode 100644 drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c
>
> diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig
> index 853958fb2c063..abacbe8ba8f46 100644
> --- a/drivers/phy/freescale/Kconfig
> +++ b/drivers/phy/freescale/Kconfig
> @@ -35,6 +35,16 @@ config PHY_FSL_IMX8M_PCIE
> Enable this to add support for the PCIE PHY as found on
> i.MX8M family of SOCs.
>
> +config PHY_FSL_IMX8MQ_HDPTX
> + tristate "Freescale i.MX8MQ DP/HDMI PHY support"
> + depends on OF && HAS_IOMEM
> + depends on COMMON_CLK
> + select GENERIC_PHY
> + select CDNS_MHDP_HELPER
> + help
> + Enable this to support the Cadence HDPTX DP/HDMI PHY driver
> + on i.MX8MQ SOC.
> +
> endif
>
> config PHY_FSL_LYNX_28G
> diff --git a/drivers/phy/freescale/Makefile b/drivers/phy/freescale/Makefile
> index cedb328bc4d28..17546a4da840a 100644
> --- a/drivers/phy/freescale/Makefile
> +++ b/drivers/phy/freescale/Makefile
> @@ -1,4 +1,5 @@
> # SPDX-License-Identifier: GPL-2.0-only
> +obj-$(CONFIG_PHY_FSL_IMX8MQ_HDPTX) += phy-fsl-imx8mq-hdptx.o
> obj-$(CONFIG_PHY_FSL_IMX8MQ_USB) += phy-fsl-imx8mq-usb.o
> obj-$(CONFIG_PHY_MIXEL_LVDS_PHY) += phy-fsl-imx8qm-lvds-phy.o
> obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY) += phy-fsl-imx8-mipi-dphy.o
> diff --git a/drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c b/drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c
> new file mode 100644
> index 0000000000000..3bf92718f826a
> --- /dev/null
> +++ b/drivers/phy/freescale/phy-fsl-imx8mq-hdptx.c
> @@ -0,0 +1,1402 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Cadence DP/HDMI PHY driver
> + *
> + * Copyright (C) 2022-2024 NXP Semiconductor, Inc.
> + */
> +#include <asm/unaligned.h>
> +#include <drm/bridge/cdns-mhdp-helper.h>
> +#include <linux/clk.h>
> +#include <linux/kernel.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +#include <linux/io.h>
> +
> +#define ADDR_PHY_AFE 0x80000
> +
> +/* PHY registers */
> +#define CMN_SSM_BIAS_TMR 0x0022
> +#define CMN_PLLSM0_PLLEN_TMR 0x0029
> +#define CMN_PLLSM0_PLLPRE_TMR 0x002a
> +#define CMN_PLLSM0_PLLVREF_TMR 0x002b
> +#define CMN_PLLSM0_PLLLOCK_TMR 0x002c
> +#define CMN_PLLSM0_USER_DEF_CTRL 0x002f
> +#define CMN_PSM_CLK_CTRL 0x0061
> +#define CMN_CDIAG_REFCLK_CTRL 0x0062
> +#define CMN_PLL0_VCOCAL_START 0x0081
> +#define CMN_PLL0_VCOCAL_INIT_TMR 0x0084
> +#define CMN_PLL0_VCOCAL_ITER_TMR 0x0085
> +#define CMN_PLL0_INTDIV 0x0094
> +#define CMN_PLL0_FRACDIV 0x0095
> +#define CMN_PLL0_HIGH_THR 0x0096
> +#define CMN_PLL0_DSM_DIAG 0x0097
> +#define CMN_PLL0_SS_CTRL2 0x0099
> +#define CMN_ICAL_INIT_TMR 0x00c4
> +#define CMN_ICAL_ITER_TMR 0x00c5
> +#define CMN_RXCAL_INIT_TMR 0x00d4
> +#define CMN_RXCAL_ITER_TMR 0x00d5
> +#define CMN_TXPUCAL_CTRL 0x00e0
> +#define CMN_TXPUCAL_INIT_TMR 0x00e4
> +#define CMN_TXPUCAL_ITER_TMR 0x00e5
> +#define CMN_TXPDCAL_CTRL 0x00f0
> +#define CMN_TXPDCAL_INIT_TMR 0x00f4
> +#define CMN_TXPDCAL_ITER_TMR 0x00f5
> +#define CMN_ICAL_ADJ_INIT_TMR 0x0102
> +#define CMN_ICAL_ADJ_ITER_TMR 0x0103
> +#define CMN_RX_ADJ_INIT_TMR 0x0106
> +#define CMN_RX_ADJ_ITER_TMR 0x0107
> +#define CMN_TXPU_ADJ_CTRL 0x0108
> +#define CMN_TXPU_ADJ_INIT_TMR 0x010a
> +#define CMN_TXPU_ADJ_ITER_TMR 0x010b
> +#define CMN_TXPD_ADJ_CTRL 0x010c
> +#define CMN_TXPD_ADJ_INIT_TMR 0x010e
> +#define CMN_TXPD_ADJ_ITER_TMR 0x010f
> +#define CMN_DIAG_PLL0_FBH_OVRD 0x01c0
> +#define CMN_DIAG_PLL0_FBL_OVRD 0x01c1
> +#define CMN_DIAG_PLL0_OVRD 0x01c2
> +#define CMN_DIAG_PLL0_TEST_MODE 0x01c4
> +#define CMN_DIAG_PLL0_V2I_TUNE 0x01c5
> +#define CMN_DIAG_PLL0_CP_TUNE 0x01c6
> +#define CMN_DIAG_PLL0_LF_PROG 0x01c7
> +#define CMN_DIAG_PLL0_PTATIS_TUNE1 0x01c8
> +#define CMN_DIAG_PLL0_PTATIS_TUNE2 0x01c9
> +#define CMN_DIAG_PLL0_INCLK_CTRL 0x01ca
> +#define CMN_DIAG_PLL0_PXL_DIVH 0x01cb
> +#define CMN_DIAG_PLL0_PXL_DIVL 0x01cc
> +#define CMN_DIAG_HSCLK_SEL 0x01e0
> +#define CMN_DIAG_PER_CAL_ADJ 0x01ec
> +#define CMN_DIAG_CAL_CTRL 0x01ed
> +#define CMN_DIAG_ACYA 0x01ff
> +#define XCVR_PSM_RCTRL 0x4001
> +#define XCVR_PSM_CAL_TMR 0x4002
> +#define XCVR_PSM_A0IN_TMR 0x4003
> +#define TX_TXCC_CAL_SCLR_MULT_0 0x4047
> +#define TX_TXCC_CPOST_MULT_00_0 0x404c
> +#define XCVR_DIAG_PLLDRC_CTRL 0x40e0
> +#define XCVR_DIAG_HSCLK_SEL 0x40e1
> +#define XCVR_DIAG_BIDI_CTRL 0x40e8
> +#define XCVR_DIAG_LANE_FCM_EN_MGN_TMR 0x40f2
> +#define TX_PSC_A0 0x4100
> +#define TX_PSC_A1 0x4101
> +#define TX_PSC_A2 0x4102
> +#define TX_PSC_A3 0x4103
> +#define TX_RCVDET_EN_TMR 0x4122
> +#define TX_RCVDET_ST_TMR 0x4123
> +#define TX_DIAG_TX_CTRL 0x41e0
> +#define TX_DIAG_TX_DRV 0x41e1
> +#define TX_DIAG_BGREF_PREDRV_DELAY 0x41e7
> +#define TX_DIAG_ACYA_0 0x41ff
> +#define TX_DIAG_ACYA_1 0x43ff
> +#define TX_DIAG_ACYA_2 0x45ff
> +#define TX_DIAG_ACYA_3 0x47ff
> +#define TX_ANA_CTRL_REG_1 0x5020
> +#define TX_ANA_CTRL_REG_2 0x5021
> +#define TX_DIG_CTRL_REG_1 0x5023
> +#define TX_DIG_CTRL_REG_2 0x5024
> +#define TXDA_CYA_AUXDA_CYA 0x5025
> +#define TX_ANA_CTRL_REG_3 0x5026
> +#define TX_ANA_CTRL_REG_4 0x5027
> +#define TX_ANA_CTRL_REG_5 0x5029
> +#define RX_PSC_A0 0x8000
> +#define RX_PSC_CAL 0x8006
> +#define PHY_HDP_MODE_CTRL 0xc008
> +#define PHY_HDP_CLK_CTL 0xc009
> +#define PHY_ISO_CMN_CTRL 0xc010
> +#define PHY_PMA_CMN_CTRL1 0xc800
> +#define PHY_PMA_ISO_CMN_CTRL 0xc810
> +#define PHY_PMA_ISO_PLL_CTRL1 0xc812
> +#define PHY_PMA_ISOLATION_CTRL 0xc81f
> +
> +/* PHY_HDP_CLK_CTL */
> +#define PLL_DATA_RATE_CLK_DIV_MASK GENMASK(15, 8)
> +#define PLL_DATA_RATE_CLK_DIV_HBR 0x24
> +#define PLL_DATA_RATE_CLK_DIV_HBR2 0x12
> +#define PLL_CLK_EN_ACK BIT(3)
> +#define PLL_CLK_EN BIT(2)
> +#define PLL_READY BIT(1)
> +#define PLL_EN BIT(0)
> +
> +/* PHY_PMA_CMN_CTRL1 */
> +#define CMA_REF_CLK_DIG_DIV_MASK GENMASK(13, 12)
> +#define CMA_REF_CLK_SEL_MASK GENMASK(6, 4)
> +#define CMA_REF_CLK_RCV_EN_MASK BIT(3)
> +#define CMA_REF_CLK_RCV_EN 1
> +#define CMN_READY BIT(0)
> +
> +/* PHY_PMA_ISO_PLL_CTRL1 */
> +#define CMN_PLL0_CLK_DATART_DIV_MASK GENMASK(7, 0)
> +
> +/* TX_DIAG_TX_DRV */
> +#define TX_DRIVER_PROG_BOOST_ENABLE BIT(10)
> +#define TX_DRIVER_PROG_BOOST_LEVEL_MASK GENMASK(9, 8)
> +#define TX_DRIVER_LDO_BG_DEPENDENT_REF_ENABLE BIT(7)
> +#define TX_DRIVER_LDO_BANDGAP_REF_ENABLE BIT(6)
> +
> +/* TX_TXCC_CAL_SCLR_MULT_0 */
> +#define SCALED_RESISTOR_CALIBRATION_CODE_ADD BIT(8)
> +#define RESISTOR_CAL_MULT_VAL_32_128 BIT(5)
> +
> +/* CMN_CDIAG_REFCLK_CTRL */
> +#define DIG_REF_CLK_DIV_SCALER_MASK GENMASK(14, 12)
> +#define REFCLK_TERMINATION_EN_OVERRIDE_EN BIT(7)
> +#define REFCLK_TERMINATION_EN_OVERRIDE BIT(6)
> +
> +/* CMN_DIAG_HSCLK_SEL */
> +#define HSCLK1_SEL_MASK GENMASK(5, 4)
> +#define HSCLK0_SEL_MASK GENMASK(1, 0)
> +#define HSCLK_PLL0_DIV2 1
> +
> +/* XCVR_DIAG_HSCLK_SEL */
> +#define HSCLK_SEL_MODE3_MASK GENMASK(13, 12)
> +#define HSCLK_SEL_MODE3_HSCLK1 1
> +
> +/* CMN_PLL0_VCOCAL_START */
> +#define VCO_CALIB_CODE_START_POINT_VAL_MASK GENMASK(8, 0)
> +
> +/* CMN_DIAG_PLL0_FBH_OVRD */
> +#define PLL_FEEDBACK_DIV_HI_OVERRIDE_EN BIT(15)
> +
> +/* CMN_DIAG_PLL0_FBL_OVRD */
> +#define PLL_FEEDBACK_DIV_LO_OVERRIDE_EN BIT(15)
> +
> +/* CMN_DIAG_PLL0_PXL_DIVH */
> +#define PLL_PCLK_DIV_EN BIT(15)
> +
> +/* XCVR_DIAG_PLLDRC_CTRL */
> +#define DPLL_CLK_SEL_MODE3 BIT(14)
> +#define DPLL_DATA_RATE_DIV_MODE3_MASK GENMASK(13, 12)
> +
> +/* TX_DIAG_TX_CTRL */
> +#define TX_IF_SUBRATE_MODE3_MASK GENMASK(7, 6)
> +
> +/* PHY_HDP_MODE_CTRL */
> +#define POWER_STATE_A3_ACK BIT(7)
> +#define POWER_STATE_A2_ACK BIT(6)
> +#define POWER_STATE_A1_ACK BIT(5)
> +#define POWER_STATE_A0_ACK BIT(4)
> +#define POWER_STATE_A3 BIT(3)
> +#define POWER_STATE_A2 BIT(2)
> +#define POWER_STATE_A1 BIT(1)
> +#define POWER_STATE_A0 BIT(0)
> +
> +/* PHY_PMA_ISO_CMN_CTRL */
> +#define CMN_MACRO_PWR_EN_ACK BIT(5)
> +
> +#define KEEP_ALIVE 0x18
> +
> +#define REF_CLK_27MHZ 27000000
> +
> +/* HDMI TX clock control settings */
> +struct hdptx_hdmi_ctrl {
> + u32 pixel_clk_freq_min;
> + u32 pixel_clk_freq_max;
> + u32 feedback_factor;
> + u32 data_range_kbps_min;
> + u32 data_range_kbps_max;
> + u32 cmnda_pll0_ip_div;
> + u32 cmn_ref_clk_dig_div;
> + u32 ref_clk_divider_scaler;
> + u32 pll_fb_div_total;
> + u32 cmnda_pll0_fb_div_low;
> + u32 cmnda_pll0_fb_div_high;
> + u32 pixel_div_total;
> + u32 cmnda_pll0_pxdiv_low;
> + u32 cmnda_pll0_pxdiv_high;
> + u32 vco_freq_min;
> + u32 vco_freq_max;
> + u32 vco_ring_select;
> + u32 cmnda_hs_clk_0_sel;
> + u32 cmnda_hs_clk_1_sel;
> + u32 hsclk_div_at_xcvr;
> + u32 hsclk_div_tx_sub_rate;
> + u32 cmnda_pll0_hs_sym_div_sel;
> + u32 cmnda_pll0_clk_freq_min;
> + u32 cmnda_pll0_clk_freq_max;
> +};
> +
> +struct cdns_hdptx_phy {
> + struct cdns_mhdp_base base;
> +
> + void __iomem *regs; /* DPTX registers base */
> + struct mutex mbox_mutex; /* mutex to protect mailbox */
> + struct device *dev;
> + struct phy *phy;
> + struct clk *ref_clk, *apb_clk;
> + u32 ref_clk_rate;
> + bool power_up;
> + union {
> + struct phy_configure_opts_hdmi hdmi;
> + struct phy_configure_opts_dp dp;
> + };
> +};
> +
> +/* HDMI TX clock control settings, pixel clock is output */
> +static const struct hdptx_hdmi_ctrl pixel_clk_output_ctrl_table[] = {
> +/*Minclk Maxclk Fdbak DR_min DR_max ip_d dig DS Totl */
> +{ 27000, 27000, 1000, 270000, 270000, 0x03, 0x1, 0x1, 240, 0x0bc, 0x030, 80, 0x026, 0x026, 2160000, 2160000, 0, 2, 2, 2, 4, 0x3, 27000, 27000},
> +{ 27000, 27000, 1250, 337500, 337500, 0x03, 0x1, 0x1, 300, 0x0ec, 0x03c, 100, 0x030, 0x030, 2700000, 2700000, 0, 2, 2, 2, 4, 0x3, 33750, 33750},
> +{ 27000, 27000, 1500, 405000, 405000, 0x03, 0x1, 0x1, 360, 0x11c, 0x048, 120, 0x03a, 0x03a, 3240000, 3240000, 0, 2, 2, 2, 4, 0x3, 40500, 40500},
> +{ 27000, 27000, 2000, 540000, 540000, 0x03, 0x1, 0x1, 240, 0x0bc, 0x030, 80, 0x026, 0x026, 2160000, 2160000, 0, 2, 2, 2, 4, 0x2, 54000, 54000},
> +{ 54000, 54000, 1000, 540000, 540000, 0x03, 0x1, 0x1, 480, 0x17c, 0x060, 80, 0x026, 0x026, 4320000, 4320000, 1, 2, 2, 2, 4, 0x3, 54000, 54000},
> +{ 54000, 54000, 1250, 675000, 675000, 0x04, 0x1, 0x1, 400, 0x13c, 0x050, 50, 0x017, 0x017, 2700000, 2700000, 0, 1, 1, 2, 4, 0x2, 67500, 67500},
> +{ 54000, 54000, 1500, 810000, 810000, 0x04, 0x1, 0x1, 480, 0x17c, 0x060, 60, 0x01c, 0x01c, 3240000, 3240000, 0, 2, 2, 2, 2, 0x2, 81000, 81000},
> +{ 54000, 54000, 2000, 1080000, 1080000, 0x03, 0x1, 0x1, 240, 0x0bc, 0x030, 40, 0x012, 0x012, 2160000, 2160000, 0, 2, 2, 2, 1, 0x1, 108000, 108000},
> +{ 74250, 74250, 1000, 742500, 742500, 0x03, 0x1, 0x1, 660, 0x20c, 0x084, 80, 0x026, 0x026, 5940000, 5940000, 1, 2, 2, 2, 4, 0x3, 74250, 74250},
> +{ 74250, 74250, 1250, 928125, 928125, 0x04, 0x1, 0x1, 550, 0x1b4, 0x06e, 50, 0x017, 0x017, 3712500, 3712500, 1, 1, 1, 2, 4, 0x2, 92812, 92812},
> +{ 74250, 74250, 1500, 1113750, 1113750, 0x04, 0x1, 0x1, 660, 0x20c, 0x084, 60, 0x01c, 0x01c, 4455000, 4455000, 1, 2, 2, 2, 2, 0x2, 111375, 111375},
> +{ 74250, 74250, 2000, 1485000, 1485000, 0x03, 0x1, 0x1, 330, 0x104, 0x042, 40, 0x012, 0x012, 2970000, 2970000, 0, 2, 2, 2, 1, 0x1, 148500, 148500},
> +{ 99000, 99000, 1000, 990000, 990000, 0x03, 0x1, 0x1, 440, 0x15c, 0x058, 40, 0x012, 0x012, 3960000, 3960000, 1, 2, 2, 2, 2, 0x2, 99000, 99000},
> +{ 99000, 99000, 1250, 1237500, 1237500, 0x03, 0x1, 0x1, 275, 0x0d8, 0x037, 25, 0x00b, 0x00a, 2475000, 2475000, 0, 1, 1, 2, 2, 0x1, 123750, 123750},
> +{ 99000, 99000, 1500, 1485000, 1485000, 0x03, 0x1, 0x1, 330, 0x104, 0x042, 30, 0x00d, 0x00d, 2970000, 2970000, 0, 2, 2, 2, 1, 0x1, 148500, 148500},
> +{ 99000, 99000, 2000, 1980000, 1980000, 0x03, 0x1, 0x1, 440, 0x15c, 0x058, 40, 0x012, 0x012, 3960000, 3960000, 1, 2, 2, 2, 1, 0x1, 198000, 198000},
> +{148500, 148500, 1000, 1485000, 1485000, 0x03, 0x1, 0x1, 660, 0x20c, 0x084, 40, 0x012, 0x012, 5940000, 5940000, 1, 2, 2, 2, 2, 0x2, 148500, 148500},
> +{148500, 148500, 1250, 1856250, 1856250, 0x04, 0x1, 0x1, 550, 0x1b4, 0x06e, 25, 0x00b, 0x00a, 3712500, 3712500, 1, 1, 1, 2, 2, 0x1, 185625, 185625},
> +{148500, 148500, 1500, 2227500, 2227500, 0x03, 0x1, 0x1, 495, 0x188, 0x063, 30, 0x00d, 0x00d, 4455000, 4455000, 1, 1, 1, 2, 2, 0x1, 222750, 222750},
> +{148500, 148500, 2000, 2970000, 2970000, 0x03, 0x1, 0x1, 660, 0x20c, 0x084, 40, 0x012, 0x012, 5940000, 5940000, 1, 2, 2, 2, 1, 0x1, 297000, 297000},
> +{198000, 198000, 1000, 1980000, 1980000, 0x03, 0x1, 0x1, 220, 0x0ac, 0x02c, 10, 0x003, 0x003, 1980000, 1980000, 0, 1, 1, 2, 1, 0x0, 198000, 198000},
> +{198000, 198000, 1250, 2475000, 2475000, 0x03, 0x1, 0x1, 550, 0x1b4, 0x06e, 25, 0x00b, 0x00a, 4950000, 4950000, 1, 1, 1, 2, 2, 0x1, 247500, 247500},
> +{198000, 198000, 1500, 2970000, 2970000, 0x03, 0x1, 0x1, 330, 0x104, 0x042, 15, 0x006, 0x005, 2970000, 2970000, 0, 1, 1, 2, 1, 0x0, 297000, 297000},
> +{198000, 198000, 2000, 3960000, 3960000, 0x03, 0x1, 0x1, 440, 0x15c, 0x058, 20, 0x008, 0x008, 3960000, 3960000, 1, 1, 1, 2, 1, 0x0, 396000, 396000},
> +{297000, 297000, 1000, 2970000, 2970000, 0x03, 0x1, 0x1, 330, 0x104, 0x042, 10, 0x003, 0x003, 2970000, 2970000, 0, 1, 1, 2, 1, 0x0, 297000, 297000},
> +{297000, 297000, 1500, 4455000, 4455000, 0x03, 0x1, 0x1, 495, 0x188, 0x063, 15, 0x006, 0x005, 4455000, 4455000, 1, 1, 1, 2, 1, 0x0, 445500, 445500},
> +{297000, 297000, 2000, 5940000, 5940000, 0x03, 0x1, 0x1, 660, 0x20c, 0x084, 20, 0x008, 0x008, 5940000, 5940000, 1, 1, 1, 2, 1, 0x0, 594000, 594000},
> +{594000, 594000, 1000, 5940000, 5940000, 0x03, 0x1, 0x1, 660, 0x20c, 0x084, 10, 0x003, 0x003, 5940000, 5940000, 1, 1, 1, 2, 1, 0x0, 594000, 594000},
> +{594000, 594000, 750, 4455000, 4455000, 0x03, 0x1, 0x1, 495, 0x188, 0x063, 10, 0x003, 0x003, 4455000, 4455000, 1, 1, 1, 2, 1, 0x0, 445500, 445500},
> +{594000, 594000, 625, 3712500, 3712500, 0x04, 0x1, 0x1, 550, 0x1b4, 0x06e, 10, 0x003, 0x003, 3712500, 3712500, 1, 1, 1, 2, 1, 0x0, 371250, 371250},
> +{594000, 594000, 500, 2970000, 2970000, 0x03, 0x1, 0x1, 660, 0x20c, 0x084, 10, 0x003, 0x003, 5940000, 5940000, 1, 1, 1, 2, 2, 0x1, 297000, 297000},
> +};
> +
> +/* HDMI TX PLL tuning settings */
> +struct hdptx_hdmi_pll_tuning {
> + u32 vco_freq_bin;
> + u32 vco_freq_min;
> + u32 vco_freq_max;
> + u32 volt_to_current_coarse;
> + u32 volt_to_current;
> + u32 ndac_ctrl;
> + u32 pmos_ctrl;
> + u32 ptat_ndac_ctrl;
> + u32 feedback_div_total;
> + u32 charge_pump_gain;
> + u32 coarse_code;
> + u32 v2i_code;
> + u32 vco_cal_code;
> +};
> +
> +/* HDMI TX PLL tuning settings, pixel clock is output */
> +static const struct hdptx_hdmi_pll_tuning pixel_clk_output_pll_table[] = {
> +/*bin VCO_freq min/max coar cod NDAC PMOS PTAT div-T P-Gain Coa V2I CAL */
> +{ 1, 1980000, 1980000, 0x4, 0x3, 0x0, 0x09, 0x09, 220, 0x42, 160, 5, 183 },
> +{ 2, 2160000, 2160000, 0x4, 0x3, 0x0, 0x09, 0x09, 240, 0x42, 166, 6, 208 },
> +{ 3, 2475000, 2475000, 0x5, 0x3, 0x1, 0x00, 0x07, 275, 0x42, 167, 6, 209 },
> +{ 4, 2700000, 2700000, 0x5, 0x3, 0x1, 0x00, 0x07, 300, 0x42, 188, 6, 230 },
> +{ 4, 2700000, 2700000, 0x5, 0x3, 0x1, 0x00, 0x07, 400, 0x4c, 188, 6, 230 },
> +{ 5, 2970000, 2970000, 0x6, 0x3, 0x1, 0x00, 0x07, 330, 0x42, 183, 6, 225 },
> +{ 6, 3240000, 3240000, 0x6, 0x3, 0x1, 0x00, 0x07, 360, 0x42, 203, 7, 256 },
> +{ 6, 3240000, 3240000, 0x6, 0x3, 0x1, 0x00, 0x07, 480, 0x4c, 203, 7, 256 },
> +{ 7, 3712500, 3712500, 0x4, 0x3, 0x0, 0x07, 0x0F, 550, 0x4c, 212, 7, 257 },
> +{ 8, 3960000, 3960000, 0x5, 0x3, 0x0, 0x07, 0x0F, 440, 0x42, 184, 6, 226 },
> +{ 9, 4320000, 4320000, 0x5, 0x3, 0x1, 0x07, 0x0F, 480, 0x42, 205, 7, 258 },
> +{ 10, 4455000, 4455000, 0x5, 0x3, 0x0, 0x07, 0x0F, 495, 0x42, 219, 7, 272 },
> +{ 10, 4455000, 4455000, 0x5, 0x3, 0x0, 0x07, 0x0F, 660, 0x4c, 219, 7, 272 },
> +{ 11, 4950000, 4950000, 0x6, 0x3, 0x1, 0x00, 0x07, 550, 0x42, 213, 7, 258 },
> +{ 12, 5940000, 5940000, 0x7, 0x3, 0x1, 0x00, 0x07, 660, 0x42, 244, 8, 292 },
> +};
> +
> +enum dp_link_rate {
> + RATE_1_6 = 162000,
> + RATE_2_1 = 216000,
> + RATE_2_4 = 243000,
> + RATE_2_7 = 270000,
> + RATE_3_2 = 324000,
> + RATE_4_3 = 432000,
> + RATE_5_4 = 540000,
> +};
> +
> +#define MAX_LINK_RATE RATE_5_4
> +
> +struct phy_pll_reg {
> + u16 val[7];
> + u32 addr;
> +};
> +
> +static const struct phy_pll_reg phy_pll_27m_cfg[] = {
> + /* 1.62 2.16 2.43 2.7 3.24 4.32 5.4 register address */
> + {{ 0x010e, 0x010e, 0x010e, 0x010e, 0x010e, 0x010e, 0x010e }, CMN_PLL0_VCOCAL_INIT_TMR },
> + {{ 0x001b, 0x001b, 0x001b, 0x001b, 0x001b, 0x001b, 0x001b }, CMN_PLL0_VCOCAL_ITER_TMR },
> + {{ 0x30b9, 0x3087, 0x3096, 0x30b4, 0x30b9, 0x3087, 0x30b4 }, CMN_PLL0_VCOCAL_START },
> + {{ 0x0077, 0x009f, 0x00b3, 0x00c7, 0x0077, 0x009f, 0x00c7 }, CMN_PLL0_INTDIV },
> + {{ 0xf9da, 0xf7cd, 0xf6c7, 0xf5c1, 0xf9da, 0xf7cd, 0xf5c1 }, CMN_PLL0_FRACDIV },
> + {{ 0x001e, 0x0028, 0x002d, 0x0032, 0x001e, 0x0028, 0x0032 }, CMN_PLL0_HIGH_THR },
> + {{ 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020 }, CMN_PLL0_DSM_DIAG },
> + {{ 0x0000, 0x1000, 0x1000, 0x1000, 0x0000, 0x1000, 0x1000 }, CMN_PLLSM0_USER_DEF_CTRL },
> + {{ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, CMN_DIAG_PLL0_OVRD },
> + {{ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, CMN_DIAG_PLL0_FBH_OVRD },
> + {{ 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 }, CMN_DIAG_PLL0_FBL_OVRD },
> + {{ 0x0006, 0x0007, 0x0007, 0x0007, 0x0006, 0x0007, 0x0007 }, CMN_DIAG_PLL0_V2I_TUNE },
> + {{ 0x0043, 0x0043, 0x0043, 0x0042, 0x0043, 0x0043, 0x0042 }, CMN_DIAG_PLL0_CP_TUNE },
> + {{ 0x0008, 0x0008, 0x0008, 0x0008, 0x0008, 0x0008, 0x0008 }, CMN_DIAG_PLL0_LF_PROG },
> + {{ 0x0100, 0x0001, 0x0001, 0x0001, 0x0100, 0x0001, 0x0001 }, CMN_DIAG_PLL0_PTATIS_TUNE1 },
> + {{ 0x0007, 0x0001, 0x0001, 0x0001, 0x0007, 0x0001, 0x0001 }, CMN_DIAG_PLL0_PTATIS_TUNE2 },
> + {{ 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020, 0x0020 }, CMN_DIAG_PLL0_TEST_MODE},
> + {{ 0x0016, 0x0016, 0x0016, 0x0016, 0x0016, 0x0016, 0x0016 }, CMN_PSM_CLK_CTRL }
> +};
> +
> +static int dp_link_rate_index(u32 rate)
> +{
> + switch (rate) {
> + case RATE_1_6:
> + return 0;
> + case RATE_2_1:
> + return 1;
> + case RATE_2_4:
> + return 2;
> + case RATE_2_7:
> + return 3;
> + case RATE_3_2:
> + return 4;
> + case RATE_4_3:
> + return 5;
> + case RATE_5_4:
> + return 6;
> + default:
> + return -1;
??
> + }
> +}
> +
> +static int cdns_phy_reg_write(struct cdns_hdptx_phy *cdns_phy, u32 addr, u32 val)
> +{
> + return cdns_mhdp_reg_write(&cdns_phy->base, ADDR_PHY_AFE + (addr << 2), val);
> +}
> +
> +static u32 cdns_phy_reg_read(struct cdns_hdptx_phy *cdns_phy, u32 addr)
> +{
> + u32 reg32;
> +
> + cdns_mhdp_reg_read(&cdns_phy->base, ADDR_PHY_AFE + (addr << 2), ®32);
> +
> + return reg32;
> +}
> +
> +static void hdptx_dp_aux_cfg(struct cdns_hdptx_phy *cdns_phy)
> +{
> + /* Power up Aux */
> + cdns_phy_reg_write(cdns_phy, TXDA_CYA_AUXDA_CYA, 1);
> +
> + cdns_phy_reg_write(cdns_phy, TX_DIG_CTRL_REG_1, 0x3);
> + ndelay(150);
> + cdns_phy_reg_write(cdns_phy, TX_DIG_CTRL_REG_2, 36);
> + ndelay(150);
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x0100);
> + ndelay(150);
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x0300);
> + ndelay(150);
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_3, 0x0000);
> + ndelay(150);
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, 0x2008);
> + ndelay(150);
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, 0x2018);
> + ndelay(150);
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, 0xa018);
> + ndelay(150);
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x030c);
> + ndelay(150);
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_5, 0x0000);
> + ndelay(150);
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_4, 0x1001);
> + ndelay(150);
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, 0xa098);
> + ndelay(150);
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, 0xa198);
> + ndelay(150);
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x030d);
> + ndelay(150);
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x030f);
> +}
> +
> +/* PMA common configuration for 27MHz */
> +static void hdptx_dp_phy_pma_cmn_cfg_27mhz(struct cdns_hdptx_phy *cdns_phy)
> +{
> + u32 num_lanes = cdns_phy->dp.lanes;
> + u16 val;
> + int k;
> +
> + /* Enable PMA input ref clk(CMN_REF_CLK_RCV_EN) */
> + val = cdns_phy_reg_read(cdns_phy, PHY_PMA_CMN_CTRL1);
> + val &= ~CMA_REF_CLK_RCV_EN_MASK;
> + val |= FIELD_PREP(CMA_REF_CLK_RCV_EN_MASK, CMA_REF_CLK_RCV_EN);
> + cdns_phy_reg_write(cdns_phy, PHY_PMA_CMN_CTRL1, val);
> +
> + /* Startup state machine registers */
> + cdns_phy_reg_write(cdns_phy, CMN_SSM_BIAS_TMR, 0x0087);
> + cdns_phy_reg_write(cdns_phy, CMN_PLLSM0_PLLEN_TMR, 0x001b);
> + cdns_phy_reg_write(cdns_phy, CMN_PLLSM0_PLLPRE_TMR, 0x0036);
> + cdns_phy_reg_write(cdns_phy, CMN_PLLSM0_PLLVREF_TMR, 0x001b);
> + cdns_phy_reg_write(cdns_phy, CMN_PLLSM0_PLLLOCK_TMR, 0x006c);
> +
> + /* Current calibration registers */
> + cdns_phy_reg_write(cdns_phy, CMN_ICAL_INIT_TMR, 0x0044);
> + cdns_phy_reg_write(cdns_phy, CMN_ICAL_ITER_TMR, 0x0006);
> + cdns_phy_reg_write(cdns_phy, CMN_ICAL_ADJ_INIT_TMR, 0x0022);
> + cdns_phy_reg_write(cdns_phy, CMN_ICAL_ADJ_ITER_TMR, 0x0006);
> +
> + /* Resistor calibration registers */
> + cdns_phy_reg_write(cdns_phy, CMN_TXPUCAL_INIT_TMR, 0x0022);
> + cdns_phy_reg_write(cdns_phy, CMN_TXPUCAL_ITER_TMR, 0x0006);
> + cdns_phy_reg_write(cdns_phy, CMN_TXPU_ADJ_INIT_TMR, 0x0022);
> + cdns_phy_reg_write(cdns_phy, CMN_TXPU_ADJ_ITER_TMR, 0x0006);
> + cdns_phy_reg_write(cdns_phy, CMN_TXPDCAL_INIT_TMR, 0x0022);
> + cdns_phy_reg_write(cdns_phy, CMN_TXPDCAL_ITER_TMR, 0x0006);
> + cdns_phy_reg_write(cdns_phy, CMN_TXPD_ADJ_INIT_TMR, 0x0022);
> + cdns_phy_reg_write(cdns_phy, CMN_TXPD_ADJ_ITER_TMR, 0x0006);
> + cdns_phy_reg_write(cdns_phy, CMN_RXCAL_INIT_TMR, 0x0022);
> + cdns_phy_reg_write(cdns_phy, CMN_RXCAL_ITER_TMR, 0x0006);
> + cdns_phy_reg_write(cdns_phy, CMN_RX_ADJ_INIT_TMR, 0x0022);
> + cdns_phy_reg_write(cdns_phy, CMN_RX_ADJ_ITER_TMR, 0x0006);
> +
> + for (k = 0; k < num_lanes; k = k + 1) {
> + /* Power state machine registers */
> + cdns_phy_reg_write(cdns_phy, XCVR_PSM_CAL_TMR | (k << 9), 0x016d);
> + cdns_phy_reg_write(cdns_phy, XCVR_PSM_A0IN_TMR | (k << 9), 0x016d);
> + /* Transceiver control and diagnostic registers */
> + cdns_phy_reg_write(cdns_phy, XCVR_DIAG_LANE_FCM_EN_MGN_TMR | (k << 9), 0x00a2);
> + cdns_phy_reg_write(cdns_phy, TX_DIAG_BGREF_PREDRV_DELAY | (k << 9), 0x0097);
> + /* Transmitter receiver detect registers */
> + cdns_phy_reg_write(cdns_phy, TX_RCVDET_EN_TMR | (k << 9), 0x0a8c);
> + cdns_phy_reg_write(cdns_phy, TX_RCVDET_ST_TMR | (k << 9), 0x0036);
> + }
> +
> + cdns_phy_reg_write(cdns_phy, TX_DIAG_ACYA_0, 1);
> + cdns_phy_reg_write(cdns_phy, TX_DIAG_ACYA_1, 1);
> + cdns_phy_reg_write(cdns_phy, TX_DIAG_ACYA_2, 1);
> + cdns_phy_reg_write(cdns_phy, TX_DIAG_ACYA_3, 1);
> +}
> +
> +static void hdptx_dp_phy_pma_cmn_pll0_27mhz(struct cdns_hdptx_phy *cdns_phy)
> +{
> + u32 num_lanes = cdns_phy->dp.lanes;
> + u32 link_rate = cdns_phy->dp.link_rate;
> + u16 val;
> + int index, i, k;
> +
> + /* DP PLL data rate 0/1 clock divider value */
> + val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
> + val &= ~PLL_DATA_RATE_CLK_DIV_MASK;
> + if (link_rate <= RATE_2_7)
> + val |= FIELD_PREP(PLL_DATA_RATE_CLK_DIV_MASK,
> + PLL_DATA_RATE_CLK_DIV_HBR);
> + else
> + val |= FIELD_PREP(PLL_DATA_RATE_CLK_DIV_MASK,
> + PLL_DATA_RATE_CLK_DIV_HBR2);
> + cdns_phy_reg_write(cdns_phy, PHY_HDP_CLK_CTL, val);
> +
> + /* High speed clock 0/1 div */
> + val = cdns_phy_reg_read(cdns_phy, CMN_DIAG_HSCLK_SEL);
> + val &= ~(HSCLK1_SEL_MASK | HSCLK0_SEL_MASK);
> + if (link_rate <= RATE_2_7) {
> + val |= FIELD_PREP(HSCLK1_SEL_MASK, HSCLK_PLL0_DIV2);
> + val |= FIELD_PREP(HSCLK0_SEL_MASK, HSCLK_PLL0_DIV2);
> + }
> + cdns_phy_reg_write(cdns_phy, CMN_DIAG_HSCLK_SEL, val);
> +
> + for (k = 0; k < num_lanes; k++) {
> + val = cdns_phy_reg_read(cdns_phy, (XCVR_DIAG_HSCLK_SEL | (k << 9)));
> + val &= ~HSCLK_SEL_MODE3_MASK;
> + if (link_rate <= RATE_2_7)
> + val |= FIELD_PREP(HSCLK_SEL_MODE3_MASK, HSCLK_SEL_MODE3_HSCLK1);
> + cdns_phy_reg_write(cdns_phy, (XCVR_DIAG_HSCLK_SEL | (k << 9)), val);
> + }
> +
> + /* DP PHY PLL 27MHz configuration */
> + index = dp_link_rate_index(link_rate);
> + for (i = 0; i < ARRAY_SIZE(phy_pll_27m_cfg); i++)
> + cdns_phy_reg_write(cdns_phy, phy_pll_27m_cfg[i].addr,
> + phy_pll_27m_cfg[i].val[index]);
> +
> + /* Transceiver control and diagnostic registers */
> + for (k = 0; k < num_lanes; k++) {
> + val = cdns_phy_reg_read(cdns_phy, (XCVR_DIAG_PLLDRC_CTRL | (k << 9)));
> + val &= ~(DPLL_DATA_RATE_DIV_MODE3_MASK | DPLL_CLK_SEL_MODE3);
> + if (link_rate <= RATE_2_7)
> + val |= FIELD_PREP(DPLL_DATA_RATE_DIV_MODE3_MASK, 2);
> + else
> + val |= FIELD_PREP(DPLL_DATA_RATE_DIV_MODE3_MASK, 1);
> + cdns_phy_reg_write(cdns_phy, (XCVR_DIAG_PLLDRC_CTRL | (k << 9)), val);
> + }
> +
> + for (k = 0; k < num_lanes; k = k + 1) {
> + /* Power state machine registers */
> + cdns_phy_reg_write(cdns_phy, (XCVR_PSM_RCTRL | (k << 9)), 0xbefc);
> + cdns_phy_reg_write(cdns_phy, (TX_PSC_A0 | (k << 9)), 0x6799);
> + cdns_phy_reg_write(cdns_phy, (TX_PSC_A1 | (k << 9)), 0x6798);
> + cdns_phy_reg_write(cdns_phy, (TX_PSC_A2 | (k << 9)), 0x0098);
> + cdns_phy_reg_write(cdns_phy, (TX_PSC_A3 | (k << 9)), 0x0098);
> + /* Receiver calibration power state definition register */
> + val = cdns_phy_reg_read(cdns_phy, RX_PSC_CAL | (k << 9));
> + val &= 0xffbb;
> + cdns_phy_reg_write(cdns_phy, (RX_PSC_CAL | (k << 9)), val);
> + val = cdns_phy_reg_read(cdns_phy, RX_PSC_A0 | (k << 9));
> + val &= 0xffbb;
> + cdns_phy_reg_write(cdns_phy, (RX_PSC_A0 | (k << 9)), val);
> + }
> +}
> +
> +static void hdptx_dp_phy_ref_clock_type(struct cdns_hdptx_phy *cdns_phy)
> +{
> + u32 val;
> +
> + val = cdns_phy_reg_read(cdns_phy, PHY_PMA_CMN_CTRL1);
> + val &= ~CMA_REF_CLK_SEL_MASK;
> + /*
> + * single ended reference clock (val |= 0x0030);
> + * differential clock (val |= 0x0000);
> + *
> + * for differential clock on the refclk_p and
> + * refclk_m off chip pins: CMN_DIAG_ACYA[8]=1'b1
> + * cdns_phy_reg_write(cdns_phy, CMN_DIAG_ACYA, 0x0100);
> + */
> + val |= FIELD_PREP(CMA_REF_CLK_SEL_MASK, 3);
> + cdns_phy_reg_write(cdns_phy, PHY_PMA_CMN_CTRL1, val);
> +}
> +
> +static int wait_for_ack(struct cdns_hdptx_phy *cdns_phy, u32 reg, u32 mask,
> + const char *err_msg)
> +{
> + u32 val, i;
> +
> + for (i = 0; i < 10; i++) {
> + val = cdns_phy_reg_read(cdns_phy, reg);
> + if (val & mask)
> + return 0;
> + msleep(20);
> + }
> +
> + dev_err(cdns_phy->dev, "%s\n", err_msg);
> + return -ETIMEDOUT;
> +}
> +
> +static int wait_for_ack_clear(struct cdns_hdptx_phy *cdns_phy, u32 reg, u32 mask,
> + const char *err_msg)
> +{
> + u32 val, i;
> +
> + for (i = 0; i < 10; i++) {
> + val = cdns_phy_reg_read(cdns_phy, reg);
> + if (!(val & mask))
> + return 0;
> + msleep(20);
> + }
> +
> + dev_err(cdns_phy->dev, "%s\n", err_msg);
> + return -ETIMEDOUT;
> +}
> +
> +static int hdptx_dp_phy_power_up(struct cdns_hdptx_phy *cdns_phy)
> +{
> + u32 val;
> + int ret = 0;
> +
> + /* Enable HDP PLL's for high speed clocks */
> + val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
> + val |= PLL_EN;
> + cdns_phy_reg_write(cdns_phy, PHY_HDP_CLK_CTL, val);
> + ret = wait_for_ack(cdns_phy, PHY_HDP_CLK_CTL, PLL_READY,
> + "Wait PLL Ack failed");
> + if (ret < 0)
> + return ret;
> +
> + /* Enable HDP PLL's data rate and full rate clocks out of PMA. */
> + val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
> + val |= PLL_CLK_EN;
> + cdns_phy_reg_write(cdns_phy, PHY_HDP_CLK_CTL, val);
> + ret = wait_for_ack(cdns_phy, PHY_HDP_CLK_CTL, PLL_CLK_EN_ACK,
> + "Wait PLL clock enable ACK failed");
> + if (ret < 0)
> + return ret;
> +
> + /* Configure PHY in A2 Mode */
> + cdns_phy_reg_write(cdns_phy, PHY_HDP_MODE_CTRL, POWER_STATE_A2);
> + ret = wait_for_ack(cdns_phy, PHY_HDP_MODE_CTRL, POWER_STATE_A2_ACK,
> + "Wait A2 Ack failed");
> + if (ret < 0)
> + return ret;
> +
> + /* Configure PHY in A0 mode (PHY must be in the A0 power
> + * state in order to transmit data)
> + */
> + cdns_phy_reg_write(cdns_phy, PHY_HDP_MODE_CTRL, POWER_STATE_A0);
> + ret = wait_for_ack(cdns_phy, PHY_HDP_MODE_CTRL, POWER_STATE_A0_ACK,
> + "Wait A0 Ack failed");
> + if (ret < 0)
> + return ret;
> +
> + cdns_phy->power_up = true;
> +
> + return ret;
> +}
> +
> +static int hdptx_dp_phy_power_down(struct cdns_hdptx_phy *cdns_phy)
> +{
> + u16 val;
> + int ret;
> +
> + if (!cdns_phy->power_up)
> + return 0;
> +
> + /* Place the PHY lanes in the A3 power state. */
> + cdns_phy_reg_write(cdns_phy, PHY_HDP_MODE_CTRL, POWER_STATE_A3);
> + ret = wait_for_ack(cdns_phy, PHY_HDP_MODE_CTRL, POWER_STATE_A3_ACK,
> + "Wait A3 Ack failed");
> + if (ret)
> + return ret;
> +
> + /* Disable HDP PLL's data rate and full rate clocks out of PMA. */
> + val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
> + val &= ~PLL_CLK_EN;
> + cdns_phy_reg_write(cdns_phy, PHY_HDP_CLK_CTL, val);
> + ret = wait_for_ack_clear(cdns_phy, PHY_HDP_CLK_CTL, PLL_CLK_EN_ACK,
> + "Wait PLL clock Ack clear failed");
> + if (ret)
> + return ret;
> +
> + /* Disable HDP PLL's for high speed clocks */
> + val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
> + val &= ~PLL_EN;
> + cdns_phy_reg_write(cdns_phy, PHY_HDP_CLK_CTL, val);
> + ret = wait_for_ack_clear(cdns_phy, PHY_HDP_CLK_CTL, PLL_READY,
> + "Wait PLL Ack clear failed");
> + if (ret)
> + return ret;
> +
> + cdns_phy->power_up = false;
> + return 0;
> +}
> +
> +static int cdns_hdptx_dp_configure(struct phy *phy,
> + union phy_configure_opts *opts)
> +{
> + struct cdns_hdptx_phy *cdns_phy = phy_get_drvdata(phy);
> + int ret;
> +
> + cdns_phy->dp.link_rate = opts->dp.link_rate;
> + cdns_phy->dp.lanes = opts->dp.lanes;
> +
> + if (cdns_phy->dp.link_rate > MAX_LINK_RATE) {
> + dev_err(cdns_phy->dev, "Link Rate(%d) Not supported\n", cdns_phy->dp.link_rate);
> + return false;
> + }
> +
> + /* Disable phy clock if PHY in power up state */
> + hdptx_dp_phy_power_down(cdns_phy);
> +
> + if (cdns_phy->ref_clk_rate == REF_CLK_27MHZ) {
> + hdptx_dp_phy_pma_cmn_cfg_27mhz(cdns_phy);
> + hdptx_dp_phy_pma_cmn_pll0_27mhz(cdns_phy);
> + } else {
> + dev_err(cdns_phy->dev, "Not support ref clock rate\n");
> + }
> +
> + /* PHY power up */
> + ret = hdptx_dp_phy_power_up(cdns_phy);
> +
> + return ret;
return hdptx_dp_phy_power_up() ?
> +}
> +
> +static bool hdptx_phy_check_alive(struct cdns_hdptx_phy *cdns_phy)
> +{
> + u32 alive, newalive;
> + u8 retries_left = 50;
> +
> + alive = readl(cdns_phy->regs + KEEP_ALIVE);
> +
> + while (retries_left--) {
> + udelay(2);
> +
> + newalive = readl(cdns_phy->regs + KEEP_ALIVE);
> + if (alive == newalive)
> + continue;
> + return true;
> + }
> + return false;
> +}
> +
> +static int hdptx_clk_enable(struct cdns_hdptx_phy *cdns_phy)
> +{
> + struct device *dev = cdns_phy->dev;
> + u32 ref_clk_rate;
> + int ret;
> +
> + cdns_phy->ref_clk = devm_clk_get(dev, "ref");
> + if (IS_ERR(cdns_phy->ref_clk)) {
> + dev_err(dev, "phy ref clock not found\n");
> + return PTR_ERR(cdns_phy->ref_clk);
> + }
> +
> + cdns_phy->apb_clk = devm_clk_get(dev, "apb");
> + if (IS_ERR(cdns_phy->apb_clk)) {
> + dev_err(dev, "phy apb clock not found\n");
> + return PTR_ERR(cdns_phy->apb_clk);
> + }
> +
> + ret = clk_prepare_enable(cdns_phy->ref_clk);
> + if (ret) {
> + dev_err(cdns_phy->dev, "Failed to prepare ref clock\n");
> + return ret;
> + }
> +
> + ref_clk_rate = clk_get_rate(cdns_phy->ref_clk);
> + if (!ref_clk_rate) {
> + dev_err(cdns_phy->dev, "Failed to get ref clock rate\n");
> + goto err_ref_clk;
> + }
> +
> + if (ref_clk_rate == REF_CLK_27MHZ) {
> + cdns_phy->ref_clk_rate = ref_clk_rate;
> + } else {
> + dev_err(cdns_phy->dev, "Not support Ref Clock Rate(%dHz)\n", ref_clk_rate);
> + goto err_ref_clk;
> + }
> +
> + ret = clk_prepare_enable(cdns_phy->apb_clk);
> + if (ret) {
> + dev_err(cdns_phy->dev, "Failed to prepare apb clock\n");
> + goto err_ref_clk;
> + }
> +
> + return 0;
> +
> +err_ref_clk:
> + clk_disable_unprepare(cdns_phy->ref_clk);
> + return -EINVAL;
> +}
> +
> +static void hdptx_clk_disable(struct cdns_hdptx_phy *cdns_phy)
> +{
> + clk_disable_unprepare(cdns_phy->apb_clk);
> + clk_disable_unprepare(cdns_phy->ref_clk);
> +}
> +
> +static void hdptx_hdmi_arc_config(struct cdns_hdptx_phy *cdns_phy)
> +{
> + u16 txpu_calib_code;
> + u16 txpd_calib_code;
> + u16 txpu_adj_calib_code;
> + u16 txpd_adj_calib_code;
> + u16 prev_calib_code;
> + u16 new_calib_code;
> + u16 rdata;
> +
> + /* Power ARC */
> + cdns_phy_reg_write(cdns_phy, TXDA_CYA_AUXDA_CYA, 0x0001);
> +
> + prev_calib_code = cdns_phy_reg_read(cdns_phy, TX_DIG_CTRL_REG_2);
> + txpu_calib_code = cdns_phy_reg_read(cdns_phy, CMN_TXPUCAL_CTRL);
> + txpd_calib_code = cdns_phy_reg_read(cdns_phy, CMN_TXPDCAL_CTRL);
> + txpu_adj_calib_code = cdns_phy_reg_read(cdns_phy, CMN_TXPU_ADJ_CTRL);
> + txpd_adj_calib_code = cdns_phy_reg_read(cdns_phy, CMN_TXPD_ADJ_CTRL);
> +
> + new_calib_code = ((txpu_calib_code + txpd_calib_code) / 2)
> + + txpu_adj_calib_code + txpd_adj_calib_code;
> +
> + if (new_calib_code != prev_calib_code) {
> + rdata = cdns_phy_reg_read(cdns_phy, TX_ANA_CTRL_REG_1);
> + rdata &= 0xdfff;
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, rdata);
> + cdns_phy_reg_write(cdns_phy, TX_DIG_CTRL_REG_2, new_calib_code);
> + mdelay(10);
> + rdata |= 0x2000;
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, rdata);
> + usleep_range(150, 250);
> + }
> +
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x0100);
> + usleep_range(100, 200);
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x0300);
> + usleep_range(100, 200);
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_3, 0x0000);
> + usleep_range(100, 200);
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, 0x2008);
> + usleep_range(100, 200);
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, 0x2018);
> + usleep_range(100, 200);
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, 0x2098);
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x030c);
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_5, 0x0010);
> + usleep_range(100, 200);
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_4, 0x4001);
> + mdelay(5);
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_1, 0x2198);
> + mdelay(5);
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x030d);
> + usleep_range(100, 200);
> + cdns_phy_reg_write(cdns_phy, TX_ANA_CTRL_REG_2, 0x030f);
> +}
> +
> +static void hdptx_hdmi_phy_set_vswing(struct cdns_hdptx_phy *cdns_phy)
> +{
> + u32 k;
> + const u32 num_lanes = 4;
> +
> + for (k = 0; k < num_lanes; k++) {
> + cdns_phy_reg_write(cdns_phy, (TX_DIAG_TX_DRV | (k << 9)),
> + TX_DRIVER_PROG_BOOST_ENABLE |
> + FIELD_PREP(TX_DRIVER_PROG_BOOST_LEVEL_MASK, 3) |
> + TX_DRIVER_LDO_BG_DEPENDENT_REF_ENABLE |
> + TX_DRIVER_LDO_BANDGAP_REF_ENABLE);
> + cdns_phy_reg_write(cdns_phy, (TX_TXCC_CPOST_MULT_00_0 | (k << 9)), 0x0);
> + cdns_phy_reg_write(cdns_phy, (TX_TXCC_CAL_SCLR_MULT_0 | (k << 9)),
> + SCALED_RESISTOR_CALIBRATION_CODE_ADD |
> + RESISTOR_CAL_MULT_VAL_32_128);
> + }
> +}
> +
> +static int hdptx_hdmi_feedback_factor(struct cdns_hdptx_phy *cdns_phy)
> +{
> + u32 feedback_factor;
> +
> + switch (cdns_phy->hdmi.color_space) {
> + case HDMI_COLORSPACE_YUV422:
> + feedback_factor = 1000;
> + break;
> +
> + case HDMI_COLORSPACE_YUV420:
> + switch (cdns_phy->hdmi.bpc) {
switch should use the same case, pls do read the coding style doc, it
helps!
> + case 8:
> + feedback_factor = 500;
> + break;
> + case 10:
> + feedback_factor = 625;
> + break;
> + case 12:
> + feedback_factor = 750;
> + break;
> + case 16:
> + feedback_factor = 1000;
> + break;
> + default:
> + dev_dbg(cdns_phy->dev, "Invalid ColorDepth\n");
> + return 0;
> + }
> + break;
> +
> + default:
> + /* Assume RGB/YUV444 */
> + switch (cdns_phy->hdmi.bpc) {
> + case 10:
> + feedback_factor = 1250;
> + break;
> + case 12:
> + feedback_factor = 1500;
> + break;
> + case 16:
> + feedback_factor = 2000;
> + break;
> + default:
> + feedback_factor = 1000;
> + }
> + }
> +
> + return feedback_factor;
> +}
> +
> +static int hdptx_hdmi_phy_config(struct cdns_hdptx_phy *cdns_phy,
> + const struct hdptx_hdmi_ctrl *p_ctrl_table,
> + const struct hdptx_hdmi_pll_tuning *p_pll_table,
> + bool pclk_in)
> +{
> + const u32 num_lanes = 4;
> + u32 val, k;
> + int ret;
> +
> + /* enable PHY isolation mode only for CMN */
> + cdns_phy_reg_write(cdns_phy, PHY_PMA_ISOLATION_CTRL, 0xd000);
> +
> + /* set cmn_pll0_clk_datart1_div/cmn_pll0_clk_datart0_div dividers */
> + val = cdns_phy_reg_read(cdns_phy, PHY_PMA_ISO_PLL_CTRL1);
> + val &= ~CMN_PLL0_CLK_DATART_DIV_MASK;
> + val |= FIELD_PREP(CMN_PLL0_CLK_DATART_DIV_MASK, 0x12);
> + cdns_phy_reg_write(cdns_phy, PHY_PMA_ISO_PLL_CTRL1, val);
> +
> + /* assert PHY reset from isolation register */
> + cdns_phy_reg_write(cdns_phy, PHY_ISO_CMN_CTRL, 0x0000);
> + /* assert PMA CMN reset */
> + cdns_phy_reg_write(cdns_phy, PHY_PMA_ISO_CMN_CTRL, 0x0000);
> +
> + /* register XCVR_DIAG_BIDI_CTRL */
> + for (k = 0; k < num_lanes; k++)
> + cdns_phy_reg_write(cdns_phy, XCVR_DIAG_BIDI_CTRL | (k << 9), 0x00ff);
> +
> + /* Describing Task phy_cfg_hdp */
> + val = cdns_phy_reg_read(cdns_phy, PHY_PMA_CMN_CTRL1);
> + val &= ~CMA_REF_CLK_RCV_EN_MASK;
> + val |= FIELD_PREP(CMA_REF_CLK_RCV_EN_MASK, CMA_REF_CLK_RCV_EN);
> + cdns_phy_reg_write(cdns_phy, PHY_PMA_CMN_CTRL1, val);
> +
> + /* PHY Registers */
> + val = cdns_phy_reg_read(cdns_phy, PHY_PMA_CMN_CTRL1);
> + val &= ~CMA_REF_CLK_DIG_DIV_MASK;
> + val |= FIELD_PREP(CMA_REF_CLK_DIG_DIV_MASK, p_ctrl_table->cmn_ref_clk_dig_div);
> + cdns_phy_reg_write(cdns_phy, PHY_PMA_CMN_CTRL1, val);
> +
> + val = cdns_phy_reg_read(cdns_phy, PHY_HDP_CLK_CTL);
> + val &= ~PLL_DATA_RATE_CLK_DIV_MASK;
> + val |= FIELD_PREP(PLL_DATA_RATE_CLK_DIV_MASK,
> + PLL_DATA_RATE_CLK_DIV_HBR2);
> + cdns_phy_reg_write(cdns_phy, PHY_HDP_CLK_CTL, val);
> +
> + /* Common control module control and diagnostic registers */
> + val = cdns_phy_reg_read(cdns_phy, CMN_CDIAG_REFCLK_CTRL);
> + val &= ~DIG_REF_CLK_DIV_SCALER_MASK;
> + val |= FIELD_PREP(DIG_REF_CLK_DIV_SCALER_MASK, p_ctrl_table->ref_clk_divider_scaler);
> + val |= REFCLK_TERMINATION_EN_OVERRIDE_EN | REFCLK_TERMINATION_EN_OVERRIDE;
> + cdns_phy_reg_write(cdns_phy, CMN_CDIAG_REFCLK_CTRL, val);
> +
> + /* High speed clock used */
> + val = cdns_phy_reg_read(cdns_phy, CMN_DIAG_HSCLK_SEL);
> + val &= ~(HSCLK1_SEL_MASK | HSCLK0_SEL_MASK);
> + val |= FIELD_PREP(HSCLK1_SEL_MASK, (p_ctrl_table->cmnda_hs_clk_1_sel >> 1));
> + val |= FIELD_PREP(HSCLK0_SEL_MASK, (p_ctrl_table->cmnda_hs_clk_0_sel >> 1));
> + cdns_phy_reg_write(cdns_phy, CMN_DIAG_HSCLK_SEL, val);
> +
> + for (k = 0; k < num_lanes; k++) {
> + val = cdns_phy_reg_read(cdns_phy, (XCVR_DIAG_HSCLK_SEL | (k << 9)));
> + val &= ~HSCLK_SEL_MODE3_MASK;
> + val |= FIELD_PREP(HSCLK_SEL_MODE3_MASK,
> + (p_ctrl_table->cmnda_hs_clk_0_sel >> 1));
> + cdns_phy_reg_write(cdns_phy, (XCVR_DIAG_HSCLK_SEL | (k << 9)), val);
> + }
> +
> + /* PLL 0 control state machine registers */
> + val = p_ctrl_table->vco_ring_select << 12;
> + cdns_phy_reg_write(cdns_phy, CMN_PLLSM0_USER_DEF_CTRL, val);
> +
> + if (pclk_in) {
> + val = 0x30a0;
> + } else {
> + val = cdns_phy_reg_read(cdns_phy, CMN_PLL0_VCOCAL_START);
> + val &= ~VCO_CALIB_CODE_START_POINT_VAL_MASK;
> + val |= FIELD_PREP(VCO_CALIB_CODE_START_POINT_VAL_MASK,
> + p_pll_table->vco_cal_code);
> + }
> + cdns_phy_reg_write(cdns_phy, CMN_PLL0_VCOCAL_START, val);
> +
> + cdns_phy_reg_write(cdns_phy, CMN_PLL0_VCOCAL_INIT_TMR, 0x0064);
> + cdns_phy_reg_write(cdns_phy, CMN_PLL0_VCOCAL_ITER_TMR, 0x000a);
> +
> + /* Common functions control and diagnostics registers */
> + val = p_ctrl_table->cmnda_pll0_hs_sym_div_sel << 8;
> + val |= p_ctrl_table->cmnda_pll0_ip_div;
> + cdns_phy_reg_write(cdns_phy, CMN_DIAG_PLL0_INCLK_CTRL, val);
> +
> + cdns_phy_reg_write(cdns_phy, CMN_DIAG_PLL0_OVRD, 0x0000);
> +
> + val = p_ctrl_table->cmnda_pll0_fb_div_high;
> + val |= PLL_FEEDBACK_DIV_HI_OVERRIDE_EN;
> + cdns_phy_reg_write(cdns_phy, CMN_DIAG_PLL0_FBH_OVRD, val);
> +
> + val = p_ctrl_table->cmnda_pll0_fb_div_low;
> + val |= PLL_FEEDBACK_DIV_LO_OVERRIDE_EN;
> + cdns_phy_reg_write(cdns_phy, CMN_DIAG_PLL0_FBL_OVRD, val);
> +
> + if (!pclk_in) {
> + val = p_ctrl_table->cmnda_pll0_pxdiv_low;
> + cdns_phy_reg_write(cdns_phy, CMN_DIAG_PLL0_PXL_DIVL, val);
> +
> + val = p_ctrl_table->cmnda_pll0_pxdiv_high;
> + val |= PLL_PCLK_DIV_EN;
> + cdns_phy_reg_write(cdns_phy, CMN_DIAG_PLL0_PXL_DIVH, val);
> + }
> +
> + val = p_pll_table->volt_to_current_coarse;
> + val |= (p_pll_table->volt_to_current) << 4;
> + cdns_phy_reg_write(cdns_phy, CMN_DIAG_PLL0_V2I_TUNE, val);
> +
> + val = p_pll_table->charge_pump_gain;
> + cdns_phy_reg_write(cdns_phy, CMN_DIAG_PLL0_CP_TUNE, val);
> +
> + cdns_phy_reg_write(cdns_phy, CMN_DIAG_PLL0_LF_PROG, 0x0008);
> +
> + val = p_pll_table->pmos_ctrl;
> + val |= (p_pll_table->ndac_ctrl) << 8;
> + cdns_phy_reg_write(cdns_phy, CMN_DIAG_PLL0_PTATIS_TUNE1, val);
> +
> + val = p_pll_table->ptat_ndac_ctrl;
> + cdns_phy_reg_write(cdns_phy, CMN_DIAG_PLL0_PTATIS_TUNE2, val);
> +
> + if (pclk_in)
> + cdns_phy_reg_write(cdns_phy, CMN_DIAG_PLL0_TEST_MODE, 0x0022);
> + else
> + cdns_phy_reg_write(cdns_phy, CMN_DIAG_PLL0_TEST_MODE, 0x0020);
> +
> + cdns_phy_reg_write(cdns_phy, CMN_PSM_CLK_CTRL, 0x0016);
> +
> + /* Transceiver control and diagnostic registers */
> + for (k = 0; k < num_lanes; k++) {
> + val = cdns_phy_reg_read(cdns_phy, (XCVR_DIAG_PLLDRC_CTRL | (k << 9)));
> + val &= ~DPLL_CLK_SEL_MODE3;
> + cdns_phy_reg_write(cdns_phy, (XCVR_DIAG_PLLDRC_CTRL | (k << 9)), val);
> + }
> +
> + for (k = 0; k < num_lanes; k++) {
> + val = cdns_phy_reg_read(cdns_phy, (TX_DIAG_TX_CTRL | (k << 9)));
> + val &= ~TX_IF_SUBRATE_MODE3_MASK;
> + val |= FIELD_PREP(TX_IF_SUBRATE_MODE3_MASK,
> + (p_ctrl_table->hsclk_div_tx_sub_rate >> 1));
> + cdns_phy_reg_write(cdns_phy, (TX_DIAG_TX_CTRL | (k << 9)), val);
> + }
> +
> + val = cdns_phy_reg_read(cdns_phy, PHY_PMA_CMN_CTRL1);
> + val &= ~CMA_REF_CLK_SEL_MASK;
> + /*
> + * single ended reference clock (val |= 0x0030);
> + * differential clock (val |= 0x0000);
> + * for differential clock on the refclk_p and
> + * refclk_m off chip pins: CMN_DIAG_ACYA[8]=1'b1
> + * cdns_phy_reg_write(cdns_phy, CMN_DIAG_ACYA, 0x0100);
> + */
> + val |= FIELD_PREP(CMA_REF_CLK_SEL_MASK, 3);
> + cdns_phy_reg_write(cdns_phy, PHY_PMA_CMN_CTRL1, val);
> +
> + /* Deassert PHY reset */
> + cdns_phy_reg_write(cdns_phy, PHY_ISO_CMN_CTRL, 0x0001);
> + cdns_phy_reg_write(cdns_phy, PHY_PMA_ISO_CMN_CTRL, 0x0003);
> +
> + /* Power state machine registers */
> + for (k = 0; k < num_lanes; k++)
> + cdns_phy_reg_write(cdns_phy, XCVR_PSM_RCTRL | (k << 9), 0xfefc);
> +
> + /* Assert cmn_macro_pwr_en */
> + cdns_phy_reg_write(cdns_phy, PHY_PMA_ISO_CMN_CTRL, 0x0013);
> +
> + /* wait for cmn_macro_pwr_en_ack */
> + ret = wait_for_ack(cdns_phy, PHY_PMA_ISO_CMN_CTRL, CMN_MACRO_PWR_EN_ACK,
> + "MA output macro power up failed");
> + if (ret < 0)
> + return ret;
> +
> + /* wait for cmn_ready */
> + ret = wait_for_ack(cdns_phy, PHY_PMA_CMN_CTRL1, CMN_READY,
> + "PMA output ready failed");
> + if (ret < 0)
> + return ret;
> +
> + for (k = 0; k < num_lanes; k++) {
> + cdns_phy_reg_write(cdns_phy, TX_PSC_A0 | (k << 9), 0x6791);
> + cdns_phy_reg_write(cdns_phy, TX_PSC_A1 | (k << 9), 0x6790);
> + cdns_phy_reg_write(cdns_phy, TX_PSC_A2 | (k << 9), 0x0090);
> + cdns_phy_reg_write(cdns_phy, TX_PSC_A3 | (k << 9), 0x0090);
> +
> + val = cdns_phy_reg_read(cdns_phy, RX_PSC_CAL | (k << 9));
> + val &= 0xffbb;
> + cdns_phy_reg_write(cdns_phy, RX_PSC_CAL | (k << 9), val);
> +
> + val = cdns_phy_reg_read(cdns_phy, RX_PSC_A0 | (k << 9));
> + val &= 0xffbb;
> + cdns_phy_reg_write(cdns_phy, RX_PSC_A0 | (k << 9), val);
> + }
> +
> + return 0;
> +}
> +
> +static int hdptx_hdmi_phy_cfg(struct cdns_hdptx_phy *cdns_phy, u32 rate)
> +{
> + const struct hdptx_hdmi_ctrl *p_ctrl_table;
> + const struct hdptx_hdmi_pll_tuning *p_pll_table;
> + const u32 refclk_freq_khz = cdns_phy->ref_clk_rate / 1000;
> + const bool pclk_in = false;
> + u32 pixel_freq = rate;
> + u32 vco_freq, char_freq;
> + u32 div_total, feedback_factor;
> + u32 i;
> +
> + feedback_factor = hdptx_hdmi_feedback_factor(cdns_phy);
> +
> + char_freq = pixel_freq * feedback_factor / 1000;
> +
> + dev_dbg(cdns_phy->dev,
> + "Pixel clock: (%d KHz), character clock: %d, bpc is (%0d-bit)\n",
> + pixel_freq, char_freq, cdns_phy->hdmi.bpc);
> +
> + /* Get right row from the ctrl_table table.
> + * Check if 'pixel_freq_khz' value matches the PIXEL_CLK_FREQ column.
> + * Consider only the rows with FEEDBACK_FACTOR column matching feedback_factor.
> + */
> + for (i = 0; i < ARRAY_SIZE(pixel_clk_output_ctrl_table); i++) {
> + if (feedback_factor == pixel_clk_output_ctrl_table[i].feedback_factor &&
> + pixel_freq == pixel_clk_output_ctrl_table[i].pixel_clk_freq_min) {
> + p_ctrl_table = &pixel_clk_output_ctrl_table[i];
> + break;
> + }
> + }
> + if (i == ARRAY_SIZE(pixel_clk_output_ctrl_table)) {
> + dev_warn(cdns_phy->dev,
> + "Pixel clk (%d KHz) not supported, bpc is (%0d-bit)\n",
> + pixel_freq, cdns_phy->hdmi.bpc);
> + return -EINVAL;
> + }
> +
> + div_total = p_ctrl_table->pll_fb_div_total;
> + vco_freq = refclk_freq_khz * div_total / p_ctrl_table->cmnda_pll0_ip_div;
> +
> + /* Get right row from the pixel_clk_output_pll_table table.
> + * Check if vco_freq_khz and feedback_div_total
> + * column matching with pixel_clk_output_pll_table.
> + */
> + for (i = 0; i < ARRAY_SIZE(pixel_clk_output_pll_table); i++) {
> + if (vco_freq == pixel_clk_output_pll_table[i].vco_freq_min &&
> + div_total == pixel_clk_output_pll_table[i].feedback_div_total) {
> + p_pll_table = &pixel_clk_output_pll_table[i];
> + break;
> + }
> + }
> + if (i == ARRAY_SIZE(pixel_clk_output_pll_table)) {
> + dev_warn(cdns_phy->dev, "VCO (%d KHz) not supported\n", vco_freq);
> + return -EINVAL;
> + }
> + dev_dbg(cdns_phy->dev, "VCO frequency is (%d KHz)\n", vco_freq);
> +
> + return hdptx_hdmi_phy_config(cdns_phy, p_ctrl_table, p_pll_table, pclk_in);
> +}
> +
> +static int hdptx_hdmi_phy_power_up(struct cdns_hdptx_phy *cdns_phy)
> +{
> + int ret = 0;
superfluous init
> +
> + /* set Power State to A2 */
> + cdns_phy_reg_write(cdns_phy, PHY_HDP_MODE_CTRL, POWER_STATE_A2);
> +
> + cdns_phy_reg_write(cdns_phy, TX_DIAG_ACYA_0, 1);
> + cdns_phy_reg_write(cdns_phy, TX_DIAG_ACYA_1, 1);
> + cdns_phy_reg_write(cdns_phy, TX_DIAG_ACYA_2, 1);
> + cdns_phy_reg_write(cdns_phy, TX_DIAG_ACYA_3, 1);
> +
> + ret = wait_for_ack(cdns_phy, PHY_HDP_MODE_CTRL, POWER_STATE_A2_ACK,
> + "Wait A2 Ack failed");
> + if (ret < 0)
> + return ret;
> +
> + /* Power up ARC */
> + hdptx_hdmi_arc_config(cdns_phy);
> +
> + /* Configure PHY in A0 mode (PHY must be in the A0 power
> + * state in order to transmit data)
> + */
> + cdns_phy_reg_write(cdns_phy, PHY_HDP_MODE_CTRL, POWER_STATE_A0);
> +
> + return wait_for_ack(cdns_phy, PHY_HDP_MODE_CTRL, POWER_STATE_A0_ACK,
> + "Wait A0 Ack failed");
> +}
> +
> +static int hdptx_hdmi_phy_power_down(struct cdns_hdptx_phy *cdns_phy)
> +{
> + u32 val;
> +
> + val = cdns_phy_reg_read(cdns_phy, PHY_HDP_MODE_CTRL);
> + val &= ~(POWER_STATE_A0 | POWER_STATE_A1 | POWER_STATE_A2 | POWER_STATE_A3);
> + /* PHY_DP_MODE_CTL set to A3 power state */
> + cdns_phy_reg_write(cdns_phy, PHY_HDP_MODE_CTRL, val | POWER_STATE_A3);
> +
> + return wait_for_ack(cdns_phy, PHY_HDP_MODE_CTRL, POWER_STATE_A3_ACK,
> + "Wait A3 Ack failed");
> +}
> +
> +static int cdns_hdptx_phy_on(struct phy *phy)
> +{
> + struct cdns_hdptx_phy *cdns_phy = phy_get_drvdata(phy);
> +
> + if (phy->attrs.mode == PHY_MODE_DP)
> + return hdptx_dp_phy_power_up(cdns_phy);
> + else
> + return hdptx_hdmi_phy_power_up(cdns_phy);
> +}
> +
> +static int cdns_hdptx_phy_off(struct phy *phy)
> +{
> + struct cdns_hdptx_phy *cdns_phy = phy_get_drvdata(phy);
> +
> + if (phy->attrs.mode == PHY_MODE_DP)
> + return hdptx_dp_phy_power_down(cdns_phy);
> + else
> + return hdptx_hdmi_phy_power_down(cdns_phy);
> + return 0;
> +}
> +
> +static int
> +cdns_hdptx_phy_valid(struct phy *phy, enum phy_mode mode,
> + int submode, union phy_configure_opts *opts)
> +{
> + u32 rate = opts->hdmi.pixel_clk_rate;
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(pixel_clk_output_ctrl_table); i++)
> + if (rate == pixel_clk_output_ctrl_table[i].pixel_clk_freq_min)
> + return 0;
> +
> + return -EINVAL;
> +}
> +
> +static int cdns_hdptx_phy_init(struct phy *phy)
> +{
> + return 0;
> +}
> +
> +static int cdns_hdptx_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
> +{
> + struct cdns_hdptx_phy *cdns_phy = phy_get_drvdata(phy);
> + int ret = 0;
> +
> + if (mode == PHY_MODE_DP) {
> + hdptx_dp_phy_ref_clock_type(cdns_phy);
> +
> + /* PHY power up */
> + ret = hdptx_dp_phy_power_up(cdns_phy);
> + if (ret < 0)
> + return ret;
> +
> + hdptx_dp_aux_cfg(cdns_phy);
> + } else if (mode != PHY_MODE_HDMI) {
> + dev_err(&phy->dev, "Invalid PHY mode: %u\n", mode);
> + return -EINVAL;
> + }
> +
> + return ret;
> +}
> +
> +static int cdns_hdptx_hdmi_configure(struct phy *phy,
> + union phy_configure_opts *opts)
> +{
> + struct cdns_hdptx_phy *cdns_phy = phy_get_drvdata(phy);
> + int ret;
> +
> + cdns_phy->hdmi.pixel_clk_rate = opts->hdmi.pixel_clk_rate;
> + cdns_phy->hdmi.color_space = opts->hdmi.color_space;
> + cdns_phy->hdmi.bpc = opts->hdmi.bpc;
> +
> + /* Check HDMI FW alive before HDMI PHY init */
> + ret = hdptx_phy_check_alive(cdns_phy);
> + if (!ret) {
> + dev_err(cdns_phy->dev, "NO HDMI FW running\n");
> + return -ENXIO;
> + }
> +
> + /* Configure PHY */
> + if (hdptx_hdmi_phy_cfg(cdns_phy, cdns_phy->hdmi.pixel_clk_rate) < 0) {
> + dev_err(cdns_phy->dev, "failed to set phy pclock\n");
> + return -EINVAL;
> + }
> +
> + ret = hdptx_hdmi_phy_power_up(cdns_phy);
> + if (ret < 0)
> + return ret;
> +
> + hdptx_hdmi_phy_set_vswing(cdns_phy);
> +
> + return 0;
> +}
> +
> +static int cdns_hdptx_configure(struct phy *phy,
> + union phy_configure_opts *opts)
> +{
> + if (phy->attrs.mode == PHY_MODE_DP)
> + return cdns_hdptx_dp_configure(phy, opts);
> + else
> + return cdns_hdptx_hdmi_configure(phy, opts);
> +}
> +
> +static const struct phy_ops cdns_hdptx_phy_ops = {
> + .init = cdns_hdptx_phy_init,
> + .set_mode = cdns_hdptx_phy_set_mode,
> + .configure = cdns_hdptx_configure,
> + .power_on = cdns_hdptx_phy_on,
> + .power_off = cdns_hdptx_phy_off,
> + .validate = cdns_hdptx_phy_valid,
> + .owner = THIS_MODULE,
> +};
> +
> +static int cdns_hdptx_phy_probe(struct platform_device *pdev)
> +{
> + struct cdns_hdptx_phy *cdns_phy;
> + struct device *dev = &pdev->dev;
> + struct device_node *node = dev->of_node;
> + struct phy_provider *phy_provider;
> + struct resource *res;
> + struct phy *phy;
> + int ret;
> +
> + cdns_phy = devm_kzalloc(dev, sizeof(*cdns_phy), GFP_KERNEL);
> + if (!cdns_phy)
> + return -ENOMEM;
> +
> + dev_set_drvdata(dev, cdns_phy);
> + cdns_phy->dev = dev;
> + mutex_init(&cdns_phy->mbox_mutex);
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + if (!res)
> + return -ENODEV;
> + cdns_phy->regs = devm_ioremap(dev, res->start, resource_size(res));
> + if (IS_ERR(cdns_phy->regs))
> + return PTR_ERR(cdns_phy->regs);
> +
> + phy = devm_phy_create(dev, node, &cdns_hdptx_phy_ops);
> + if (IS_ERR(phy))
> + return PTR_ERR(phy);
> +
> + cdns_phy->phy = phy;
> + phy_set_drvdata(phy, cdns_phy);
> +
> + /* init base struct for access mhdp mailbox */
> + cdns_phy->base.dev = cdns_phy->dev;
> + cdns_phy->base.regs = cdns_phy->regs;
> + cdns_phy->base.mbox_mutex = &cdns_phy->mbox_mutex;
> +
> + ret = hdptx_clk_enable(cdns_phy);
> + if (ret) {
> + dev_err(dev, "Init clk fail\n");
> + return -EINVAL;
> + }
> +
> + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> + if (IS_ERR(phy_provider)) {
> + ret = PTR_ERR(phy_provider);
> + goto clk_disable;
> + }
> +
> + dev_dbg(dev, "probe success!\n");
> +
> + return 0;
> +
> +clk_disable:
> + hdptx_clk_disable(cdns_phy);
> +
> + return -EINVAL;
> +}
> +
> +static int cdns_hdptx_phy_remove(struct platform_device *pdev)
> +{
> + struct cdns_hdptx_phy *cdns_phy = platform_get_drvdata(pdev);
> +
> + hdptx_clk_disable(cdns_phy);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id cdns_hdptx_phy_of_match[] = {
> + {.compatible = "fsl,imx8mq-hdptx-phy" },
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, cdns_hdptx_phy_of_match);
> +
> +static struct platform_driver cdns_hdptx_phy_driver = {
> + .probe = cdns_hdptx_phy_probe,
> + .remove = cdns_hdptx_phy_remove,
> + .driver = {
> + .name = "cdns-hdptx-phy",
> + .of_match_table = cdns_hdptx_phy_of_match,
> + }
> +};
> +module_platform_driver(cdns_hdptx_phy_driver);
> +
> +MODULE_AUTHOR("Sandor Yu <sandor.yu@nxp.com>");
> +MODULE_DESCRIPTION("Cadence HDP-TX DP/HDMI PHY driver");
> +MODULE_LICENSE("GPL");
> --
> 2.34.1
--
~Vinod
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^ permalink raw reply
* Re: [PATCH v2 04/18] PCI: endpoint: test: Use pci_epc_mem_map/unmap()
From: Niklas Cassel @ 2024-04-05 13:37 UTC (permalink / raw)
To: Damien Le Moal
Cc: Manivannan Sadhasivam, Lorenzo Pieralisi, Kishon Vijay Abraham I,
Shawn Lin, Krzysztof Wilczyński, Bjorn Helgaas,
Heiko Stuebner, linux-pci, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, devicetree, linux-rockchip, linux-arm-kernel,
Rick Wertenbroek, Wilfred Mallawa
In-Reply-To: <20240330041928.1555578-5-dlemoal@kernel.org>
On Sat, Mar 30, 2024 at 01:19:14PM +0900, Damien Le Moal wrote:
> Modify the endpoint test driver to use the functions pci_epc_mem_map()
> and pci_epc_mem_unmap() for the read, write and copy tests. For each
> test case, the transfer (dma or mmio) are executed in a loop to ensure
> that potentially partial mappings returned by pci_epc_mem_map() are
> correctly handled.
>
> Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
> ---
You probably want to rebase this series on top of:
[1] https://lore.kernel.org/linux-pci/20240314-pci-dbi-rework-v10-0-14a45c5a938e@linaro.org/
[2] https://lore.kernel.org/linux-pci/20240320113157.322695-1-cassel@kernel.org/
As these both modify pci-epf-test.c.
AFAICT both these series [1] (DBI rework v12, not v10) and [2] are fully
reviewed and seem to be ready to go.
They just seem to take a really long time to be picked up.
Kind regards,
Niklas
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^ permalink raw reply
* Re: [PATCH 2/2] arm64: dts: rockchip: add Protonic MECSBC device-tree
From: Andrew Lunn @ 2024-04-05 13:35 UTC (permalink / raw)
To: Sascha Hauer
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner,
devicetree, linux-arm-kernel, linux-rockchip, linux-kernel,
David Jander
In-Reply-To: <Zg_NwfxLhzdCjN87@pengutronix.de>
> Do you have a pointer why setting the delays in the phy is preferred
> over setting them in the network driver? In the end this requires us
> to have the correct phy driver whereas setting them in the network
> driver would just work for any phy driver?
One reason is that nearly every other board does it in the PHY. This
is something i've been trying to standardize on for years.
Another point is that when doing it in the MAC, most MAC drivers get
it wrong. RGMII needs 2ns delays on the clock lines. That delay can be
provided by the board, making the clock lines longer. Or the MAC or
the PHY can add the delays. phy-mode in DT tells you about what the
board requires. Your board does not have extra long clock lines, so
you need rgmii-id. If the MAC decides to implement the delay, it
should modify the value passed to the PHY to be rgmii, to indicate it
has added the delays, and the PHY should not. This is what many MAC
drivers get wrong, they don't do the masking. By standardizing on the
PHY doing the delay, we avoid this, keeping the MAC driver simple, and
probably bug free in this respect.
There is admittedly some historical confusion here. The design is not
the best. If would of been much better if the design would have both
phy-mode and mac-mode.
As for using genphy, yes it might work, but there is no real
guarantee. It is always best you drive the hardware using the driver
specific to it. Consider genphy as a fallback which might be good
enough that you can ssh into the board and install the correct
module. You should not really be using it in production.
Andrew
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^ permalink raw reply
* Re: [Intel-gfx] [PATCH v5 0/7] Introduce __xchg, non-atomic xchg
From: Jani Nikula @ 2024-04-05 14:47 UTC (permalink / raw)
To: Peter Zijlstra, Andrzej Hajda
Cc: Mark Rutland, linux-ia64, linux-sh, dri-devel, linux-kernel,
sparclinux, linux-riscv, linux-s390, linux-hexagon,
linux-snps-arc, intel-gfx, linux-xtensa, Arnd Bergmann,
Boqun Feng, linux-m68k, openrisc, loongarch, Rodrigo Vivi,
Andy Shevchenko, linux-arm-kernel, linux-parisc, linux-mips,
linux-alpha, Andrew Morton, linuxppc-dev
In-Reply-To: <Y/y0/VoPAVCXGKp3@hirez.programming.kicks-ass.net>
On Mon, 27 Feb 2023, Peter Zijlstra <peterz@infradead.org> wrote:
> On Thu, Feb 23, 2023 at 10:24:19PM +0100, Andrzej Hajda wrote:
>> On 22.02.2023 18:04, Peter Zijlstra wrote:
>> > On Wed, Jan 18, 2023 at 04:35:22PM +0100, Andrzej Hajda wrote:
>> >
>> > > Andrzej Hajda (7):
>> > > arch: rename all internal names __xchg to __arch_xchg
>> > > linux/include: add non-atomic version of xchg
>> > > arch/*/uprobes: simplify arch_uretprobe_hijack_return_addr
>> > > llist: simplify __llist_del_all
>> > > io_uring: use __xchg if possible
>> > > qed: use __xchg if possible
>> > > drm/i915/gt: use __xchg instead of internal helper
>> >
>> > Nothing crazy in here I suppose, I somewhat wonder why you went through
>> > the trouble, but meh.
>>
>> If you are asking why I have proposed this patchset, then the answer is
>> simple, 1st I've tried to find a way to move internal i915 helper to core
>> (see patch 7).
>> Then I was looking for possible other users of this helper. And apparently
>> there are many of them, patches 3-7 shows some.
>>
>>
>> >
>> > You want me to take this through te locking tree (for the next cycle,
>> > not this one) where I normally take atomic things or does someone else
>> > want this?
>>
>> If you could take it I will be happy.
>
> OK, I'll go queue it in tip/locking/core after -rc1. Thanks!
Is this where the series fell between the cracks, or was there some
follow-up that I missed?
I think this would still be useful. Andrzej, would you mind rebasing and
resending if there are no objections?
BR,
Jani.
--
Jani Nikula, Intel
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^ permalink raw reply
* Re: [PATCH 1/1] arm64: dts: imx8qxp-mek: add cm40_i2c, wm8960/wm8962 and sai[0,1,4,5]
From: Frank Li @ 2024-04-05 14:46 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
open list
In-Reply-To: <efc9c624-6a31-4299-a604-8aad1d0cd878@linaro.org>
On Fri, Apr 05, 2024 at 08:41:59AM +0200, Krzysztof Kozlowski wrote:
> On 04/04/2024 18:19, Frank Li wrote:
> > imx8qxp-mek use two kind audio codec, wm8960 and wm8962. Using dummy gpio
> > i2c bus mux to connect both i2c devices. One will probe failure and other
> > will probe success when devices driver check whoami. So one dtb can cover
> > both board configuration.
>
> I don't understand it. Either you add real device or not. If one board
> has two devices, then why do you need to check for failures?
>
> Anyway, don't add fake stuff to DTS.
NAK can't resolve the problem. It should be common problem for long time
cycle boards. Some chipes will be out life cycle. such as some sensor. So
chips on boards have been replace by some pin to pin compatible sensor. For
example:
old boards: use sensor A with address 0x1a
new bench: use sensor B with address 0x1b.
You can treat it as two kind boards, RevA or RevB. But most user want to
use one dtb to handle such small differences. For this case, it should be
simple. Just add a super set.
i2c
{
sensorA@1a
{
}
sensorB@1b
{
}
}
It also depend on whoami check by i2c devices. Only A or B will probe.
wm8960 and wm8962 are more complex example. wm8960 is out of life. But
wm8962 and wm8960 have the same i2c address. The current i2c frame can't
allow the same i2c address in one i2c bus.
You are feel to NAK my method, but I hope you also provide constructive
solution to help resolve the problem.
Frank
>
> NAK.
> >
> > Signed-off-by: Frank Li <Frank.Li@nxp.com>
> > ---
> > arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 210 ++++++++++++++++++
> > 1 file changed, 210 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
> > index 8360bb851ac03..adff87c7cf305 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
> > +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
> > @@ -30,6 +30,13 @@ reg_usdhc2_vmmc: usdhc2-vmmc {
> > enable-active-high;
> > };
> >
> > + reg_audio: regulator-wm8962 {
> > + compatible = "regulator-fixed";
> > + regulator-name = "3v3_aud";
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + };
> > +
> > gpio-sbu-mux {
> > compatible = "nxp,cbdtu02043", "gpio-sbu-mux";
> > pinctrl-names = "default";
> > @@ -44,6 +51,105 @@ usb3_data_ss: endpoint {
> > };
> > };
> > };
> > +
> > + sound-wm8960 {
> > + compatible = "fsl,imx-audio-wm8960";
> > + model = "wm8960-audio";
> > + audio-cpu = <&sai1>;
> > + audio-codec = <&wm8960>;
> > + hp-det-gpio = <&lsio_gpio1 0 GPIO_ACTIVE_HIGH>;
> > + audio-routing =
> > + "Headphone Jack", "HP_L",
> > + "Headphone Jack", "HP_R",
> > + "Ext Spk", "SPK_LP",
> > + "Ext Spk", "SPK_LN",
> > + "Ext Spk", "SPK_RP",
> > + "Ext Spk", "SPK_RN",
> > + "LINPUT1", "Mic Jack",
> > + "Mic Jack", "MICB";
> > + };
> > +
> > + sound-wm8962 {
> > + compatible = "fsl,imx-audio-wm8962";
> > + model = "wm8962-audio";
> > + audio-cpu = <&sai1>;
> > + audio-codec = <&wm8962>;
> > + hp-det-gpio = <&lsio_gpio1 0 GPIO_ACTIVE_HIGH>;
> > + audio-routing =
> > + "Headphone Jack", "HPOUTL",
> > + "Headphone Jack", "HPOUTR",
> > + "Ext Spk", "SPKOUTL",
> > + "Ext Spk", "SPKOUTR",
> > + "AMIC", "MICBIAS",
> > + "IN3R", "AMIC",
> > + "IN1R", "AMIC";
> > + };
> > +
> > + /*
> > + * This dummy i2c mux. GPIO actually will not impact selection. At actual boards, only 1
> > + * device connectted. I2C client driver will check ID when probe. Only matched ID's driver
> > + * probe successfully.
>
> NAK
>
>
> Best regards,
> Krzysztof
>
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* Re: [PATCH v2 3/3] arm64: dts: add description for solidrun cn9130 som and clearfog boards
From: Josua Mayer @ 2024-04-05 14:36 UTC (permalink / raw)
To: Krzysztof Kozlowski, Andrew Lunn, Gregory Clement,
Sebastian Hesselbarth, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Rob Herring
Cc: Yazan Shhady, linux-arm-kernel@lists.infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
In-Reply-To: <84bf0db5-856a-401b-8225-fd62f381beb6@linaro.org>
Hi Krzysztof,
Am 05.04.24 um 09:05 schrieb Krzysztof Kozlowski:
> On 04/04/2024 17:35, Josua Mayer wrote:
>> Add description for the SolidRun CN9130 SoM, and Clearfog Base / Pro
>> reference boards.
>>
>> The SoM has been designed as a pin-compatible replacement for the older
>> Armada 388 based SoM. Therefore it supports the same boards and a
>> similar feature set.
>>
>> Most notable upgrades:
>> - 4x Cortex-A72
>> - 10Gbps SFP
>> - Both eMMC and SD supported at the same time
>>
>> The developer first supporting this product at SolidRun decided to use
>> different filenames for the DTBs: Armada 388 uses the full
>> "clearfog" string while cn9130 uses the abbreviation "cf".
>> This name is already hard-coded in pre-installed vendor u-boot and can
>> not be changed easily.
>>
>> NOTICE IN CASE ANYBODY WANTS TO SELF-UPGRADE:
>> CN9130 SoM has a different footprint from Armada 388 SoM.
>> Components on the carrier board below the SoM may collide causing
>> damage, such as on Clearfog Base.
>>
>> Signed-off-by: Josua Mayer <josua@solid-run.com>
>> ---
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Thanks!
Meanwhile I found two instances of status-property in wrong place,
and also some small changes I prefer to make for v3
(discovered while working on cn9131 board).
Do you prefer in this case to drop your review tag,
or alternatively to keep it, but add separate patch in v3?
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^ permalink raw reply
* [PATCH] drm: fix DRM_DISPLAY_DP_HELPER dependencies, part 2
From: Arnd Bergmann @ 2024-04-05 14:35 UTC (permalink / raw)
To: Maxime Ripard
Cc: Arnd Bergmann, Andrzej Hajda, Neil Armstrong, Robert Foss,
Laurent Pinchart, Jonas Karlman, Jernej Skrabec,
Maarten Lankhorst, Thomas Zimmermann, David Airlie, Daniel Vetter,
Sandy Huang, Heiko Stübner, Andy Yan, Jani Nikula,
Lucas De Marchi, dri-devel, linux-kernel, linux-arm-kernel,
linux-rockchip
From: Arnd Bergmann <arnd@arndb.de>
After my fix yesterday, I ran into another problem of the same kind:
aarch64-linux-ld: drivers/gpu/drm/bridge/analogix/analogix_dp_core.o: in function `drm_dp_dpcd_readb':
analogix_dp_core.c:(.text+0x194): undefined reference to `drm_dp_dpcd_read'
aarch64-linux-ld: drivers/gpu/drm/bridge/analogix/analogix_dp_core.o: in function `drm_dp_dpcd_writeb':
analogix_dp_core.c:(.text+0x214): undefined reference to `drm_dp_dpcd_write'
aarch64-linux-ld: drivers/gpu/drm/bridge/analogix/analogix_dp_core.o: in function `analogix_dp_stop_crc':
analogix_dp_core.c:(.text+0x4b0): undefined reference to `drm_dp_stop_crc'
aarch64-linux-ld: drivers/gpu/drm/bridge/analogix/analogix_dp_core.o: in function `analogix_dp_start_crc':
analogix_dp_core.c:(.text+0xbe8): undefined reference to `drm_dp_start_crc'
Add the same dependency again to ROCKCHIP_ANALOGIX_DP after checking that
nothing else selects the analogix driver. Also add a dependency to
DRM_ANALOGIX_DP to make it easier to identifier future problems of
this type when they get introduced.
Fixes: 0323287de87d ("drm: Switch DRM_DISPLAY_DP_HELPER to depends on")
Fixes: d1ef8fc18be6 ("drm: fix DRM_DISPLAY_DP_HELPER dependencies")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
drivers/gpu/drm/bridge/analogix/Kconfig | 2 +-
drivers/gpu/drm/rockchip/Kconfig | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/Kconfig b/drivers/gpu/drm/bridge/analogix/Kconfig
index 12bfea53bf24..5b564fded6d6 100644
--- a/drivers/gpu/drm/bridge/analogix/Kconfig
+++ b/drivers/gpu/drm/bridge/analogix/Kconfig
@@ -28,7 +28,7 @@ config DRM_ANALOGIX_ANX78XX
config DRM_ANALOGIX_DP
tristate
- depends on DRM
+ depends on DRM_DISPLAY_HELPER
config DRM_ANALOGIX_ANX7625
tristate "Analogix Anx7625 MIPI to DP interface support"
diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
index 4b4ad75032fd..4c7072e6e34e 100644
--- a/drivers/gpu/drm/rockchip/Kconfig
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -36,7 +36,7 @@ config ROCKCHIP_VOP2
config ROCKCHIP_ANALOGIX_DP
bool "Rockchip specific extensions for Analogix DP driver"
depends on DRM_DISPLAY_DP_HELPER
- depends on DRM_DISPLAY_HELPER
+ depends on DRM_DISPLAY_HELPER=y || (DRM_DISPLAY_HELPER=m && DRM_ROCKCHIP=m)
depends on ROCKCHIP_VOP
help
This selects support for Rockchip SoC specific extensions
--
2.39.2
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* [PATCH v4 4/4] cpufreq: Use arch specific feedback for cpuinfo_cur_freq
From: Beata Michalska @ 2024-04-05 13:33 UTC (permalink / raw)
To: linux-kernel, linux-arm-kernel, ionela.voinescu, vanshikonda
Cc: sudeep.holla, will, catalin.marinas, vincent.guittot, sumitg,
yang, lihuisong
In-Reply-To: <20240405133319.859813-1-beata.michalska@arm.com>
Some architectures provide a way to determine an average frequency over
a certain period of time based on available performance monitors (AMU on
ARM or APERF/MPERf on x86). With those at hand, enroll arch_freq_get_on_cpu
into cpuinfo_cur_freq policy sysfs attribute handler, which is expected to
represent the current frequency of a given CPU, as obtained by the hardware.
This is the type of feedback that counters do provide.
Signed-off-by: Beata Michalska <beata.michalska@arm.com>
---
drivers/cpufreq/cpufreq.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c
index 66e10a19d76a..603533b2608f 100644
--- a/drivers/cpufreq/cpufreq.c
+++ b/drivers/cpufreq/cpufreq.c
@@ -795,8 +795,10 @@ store_one(scaling_max_freq, max);
static ssize_t show_cpuinfo_cur_freq(struct cpufreq_policy *policy,
char *buf)
{
- unsigned int cur_freq = __cpufreq_get(policy);
+ unsigned int cur_freq = arch_freq_get_on_cpu(policy->cpu);
+ if (!cur_freq)
+ cur_freq = __cpufreq_get(policy);
if (cur_freq)
return sprintf(buf, "%u\n", cur_freq);
--
2.25.1
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