* Re: [RFC PATCH v1 0/4] Reduce cost of ptep_get_lockless on arm64
From: Ryan Roberts @ 2024-04-09 16:35 UTC (permalink / raw)
To: David Hildenbrand, Mark Rutland, Catalin Marinas, Will Deacon,
Alexander Shishkin, Jiri Olsa, Ian Rogers, Adrian Hunter,
Andrew Morton, Muchun Song
Cc: linux-arm-kernel, linux-mm, linux-kernel
In-Reply-To: <f2aad459-e19c-45e2-a7ab-35383e8c3ba5@redhat.com>
On 08/04/2024 09:36, David Hildenbrand wrote:
> On 03.04.24 14:59, Ryan Roberts wrote:
>> On 27/03/2024 09:34, David Hildenbrand wrote:
>>> On 26.03.24 18:51, Ryan Roberts wrote:
>>>> On 26/03/2024 17:39, David Hildenbrand wrote:
>>>>> On 26.03.24 18:32, Ryan Roberts wrote:
>>>>>> On 26/03/2024 17:04, David Hildenbrand wrote:
>>>>>>>>>>>
>>>>>>>>>>> Likely, we just want to read "the real deal" on both sides of the
>>>>>>>>>>> pte_same()
>>>>>>>>>>> handling.
>>>>>>>>>>
>>>>>>>>>> Sorry I'm not sure I understand? You mean read the full pte including
>>>>>>>>>> access/dirty? That's the same as dropping the patch, right? Of course if
>>>>>>>>>> we do
>>>>>>>>>> that, we still have to keep pte_get_lockless() around for this case.
>>>>>>>>>> In an
>>>>>>>>>> ideal
>>>>>>>>>> world we would convert everything over to
>>>>>>>>>> ptep_get_lockless_norecency() and
>>>>>>>>>> delete ptep_get_lockless() to remove the ugliness from arm64.
>>>>>>>>>
>>>>>>>>> Yes, agreed. Patch #3 does not look too crazy and it wouldn't really
>>>>>>>>> affect
>>>>>>>>> any
>>>>>>>>> architecture.
>>>>>>>>>
>>>>>>>>> I do wonder if pte_same_norecency() should be defined per architecture
>>>>>>>>> and the
>>>>>>>>> default would be pte_same(). So we could avoid the mkold etc on all other
>>>>>>>>> architectures.
>>>>>>>>
>>>>>>>> Wouldn't that break it's semantics? The "norecency" of
>>>>>>>> ptep_get_lockless_norecency() means "recency information in the returned
>>>>>>>> pte
>>>>>>>> may
>>>>>>>> be incorrect". But the "norecency" of pte_same_norecency() means "ignore
>>>>>>>> the
>>>>>>>> access and dirty bits when you do the comparison".
>>>>>>>
>>>>>>> My idea was that ptep_get_lockless_norecency() would return the actual
>>>>>>> result on
>>>>>>> these architectures. So e.g., on x86, there would be no actual change in
>>>>>>> generated code.
>>>>>>
>>>>>> I think this is a bad plan... You'll end up with subtle differences between
>>>>>> architectures.
>>>>>>
>>>>>>>
>>>>>>> But yes, the documentation of these functions would have to be improved.
>>>>>>>
>>>>>>> Now I wonder if ptep_get_lockless_norecency() should actively clear
>>>>>>> dirty/accessed bits to more easily find any actual issues where the bits
>>>>>>> still
>>>>>>> matter ...
>>>>>>
>>>>>> I did a version that took that approach. Decided it was not as good as
>>>>>> this way
>>>>>> though. Now for the life of me, I can't remember my reasoning.
>>>>>
>>>>> Maybe because there are some code paths that check accessed/dirty without
>>>>> "correctness" implications? For example, if the PTE is already dirty, no
>>>>> need to
>>>>> set it dirty etc?
>>>>
>>>> I think I decided I was penalizing the architectures that don't care because
>>>> all
>>>> their ptep_get_norecency() and ptep_get_lockless_norecency() need to explicitly
>>>> clear access/dirty. And I would have needed ptep_get_norecency() from day 1 so
>>>> that I could feed its result into pte_same().
>>>
>>> True. With ptep_get_norecency() you're also penalizing other architectures.
>>> Therefore my original thought about making the behavior arch-specific, but the
>>> arch has to make sure to get the combination of
>>> ptep_get_lockless_norecency()+ptep_same_norecency() is right.
>>>
>>> So if an arch decide to ignore bits in ptep_get_lockless_norecency(), it must
>>> make sure to also ignore them in ptep_same_norecency(), and must be able to
>>> handle access/dirty bit changes differently.
>>>
>>> Maybe one could have one variant for "hw-managed access/dirty" vs. "sw managed
>>> accessed or dirty". Only the former would end up ignoring stuff here, the latter
>>> would not.
>>>
>>> But again, just some random thoughts how this affects other architectures and
>>> how we could avoid it. The issue I describe in patch #3 would be gone if
>>> ptep_same_norecency() would just do a ptep_same() check on other architectures
>>> -- and would make it easier to sell :)
>>>
>>
>> I've been thinking some more about this. I think your proposal is the following:
>>
>>
>> // ARM64
>> ptep_get_lockless_norecency()
>> {
>> - returned access/dirty may be incorrect
>> - returned access/dirty may be differently incorrect between 2 calls
>> }
>> pte_same_norecency()
>> {
>> - ignore access/dirty when doing comparison
>> }
>> ptep_set_access_flags(ptep, pte)
>> {
>> - must not assume access/dirty in pte are "more permissive" than
>> access/dirty in *ptep
>> - must only set access/dirty in *ptep, never clear
>> }
>>
>>
>> // Other arches: no change to generated code
>> ptep_get_lockless_norecency()
>> {
>> return ptep_get_lockless();
>> }
>> pte_same_norecency()
>> {
>> return pte_same();
>> }
>> ptep_set_access_flags(ptep, pte)
>> {
>> - may assume access/dirty in pte are "more permissive" than access/dirty
>> in *ptep
>> - if no HW access/dirty updates, "*ptep = pte" always results in "more
>> permissive" change
>> }
>>
>> An arch either specializes all 3 or none of them.
>>
>> This would allow us to get rid of ptep_get_lockless().
>>
>> And it addresses the bug you found with ptep_set_access_flags().
>>
>>
>> BUT, I still have a nagging feeling that there are likely to be other similar
>> problems caused by ignoring access/dirty during pte_same_norecency(). I can't
>> convince myself that its definitely all safe and robust.
>
> Right, we'd have to identify the other possible cases and document what an arch
> + common code must stick to to make it work.
>
> Some rules would be: if an arch implements ptep_get_lockless_norecency():
>
> (1) Passing the result from ptep_get_lockless_norecency() to pte_same()
> is wrong.
> (2) Checking pte_young()/pte_old/pte_dirty()/pte_clean() after
> ptep_get_lockless_norecency() is very likely wrong.
>
>
>>
>> So I'm leaning towards dropping patch 3 and therefore keeping
>> ptep_get_lockless() around.
>>
>> Let me know if you have any insight that might help me change my mind :)
>
> I'm wondering if it would help if we could find a better name (or concept) for
> "norecency" here, that expresses that only on some archs we'd have that fuzzy
> handling.
>
> Keeping ptep_get_lockless() around for now sounds like the best alternative.
Separately to this I've been playing with an idea to add support for uffd-wp and
soft-dirty SW PTE bits for arm64; it boils down to keeping the SW bits in
separate storage, linked from the ptdesc. And we have some constant HW PTE bits
that we can remove and replace with those SW bits so we can keep the pte_t the
same size and abstract it all with ptep_get() and set_ptes().
It was all looking straightforward until I got to ptep_get_lockless(). Now that
there are 2 separate locations for PTE bits, I can't read it all atomically.
So I've been looking at all this again, and getting myself even more confused.
I believe there are 2 classes of ptep_get_lockless() caller:
1) vmf->orig_pte = ptep_get_lockless(vmf->pte); in handle_pte_fault()
2) everyone else
--
(1) doesn't really care if orig_pte is consistent or not. It just wants to read
a value, do some speculative work based on that value, then lock the PTL, and
check the value hasn't changed. If it has changed, it backs out. So we don't
actually need any "lockless" guarrantees here; we could just use ptep_get().
In fact, prior to Hugh's commit 26e1a0c3277d ("mm: use pmdp_get_lockless()
without surplus barrier()"), we had this:
vmf->pte = pte_offset_map(vmf->pmd, vmf->address);
- vmf->orig_pte = *vmf->pte;
+ vmf->orig_pte = ptep_get_lockless(vmf->pte);
vmf->flags |= FAULT_FLAG_ORIG_PTE_VALID;
- /*
- * some architectures can have larger ptes than wordsize,
- * e.g.ppc44x-defconfig has CONFIG_PTE_64BIT=y and
- * CONFIG_32BIT=y, so READ_ONCE cannot guarantee atomic
- * accesses. The code below just needs a consistent view
- * for the ifs and we later double check anyway with the
- * ptl lock held. So here a barrier will do.
- */
- barrier();
if (pte_none(vmf->orig_pte)) {
--
(2) All the other users require that a subset of the pte fields are
self-consistent; specifically they don't care about access, dirty, uffd-wp or
soft-dirty. arm64 can guarrantee that all the other bits are self-consistent
just by calling ptep_get().
--
So, I'm making the bold claim that it was never neccessary to specialize
pte_get_lockless() on arm64, and I *think* we could just delete it so that
ptep_get_lockless() resolves to ptep_get() on arm64. That solves the original
aim without needing to introduce "norecency" variants.
Additionally I propose documenting ptep_get_lockless() to describe the set of
fields that are guarranteed to be self-consistent and the remaining fields which
are self-consistent only with best-effort.
Could it be this easy? My head is hurting...
Thanks,
Ryan
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^ permalink raw reply
* Re: [PATCH v6 4/4] drivers: watchdog: ast2500 and ast2600 support bootstatus
From: PeterYin @ 2024-04-09 16:28 UTC (permalink / raw)
To: patrick, Wim Van Sebroeck, Guenter Roeck, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Joel Stanley, Andrew Jeffery,
linux-watchdog, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
In-Reply-To: <20240328022231.3649741-5-peteryin.openbmc@gmail.com>
Peter Yin 於 3/28/24 10:22 寫道:
> Add WDIOF_EXTERN1 and WDIOF_CARDRESET bootstatus in ast2600
>
> Regarding the AST2600 specification, the WDTn Timeout Status Register
> (WDT10) has bit 1 reserved. Bit 1 of the status register indicates
> on ast2500 if the boot was from the second boot source.
> It does not indicate that the most recent reset was triggered by
> the watchdog. The code should just be changed to set WDIOF_CARDRESET
> if bit 0 of the status register is set.
>
> Include SCU register to veriy WDIOF_EXTERN1 in ast2600 SCU74 or
> ast2500 SCU3C when bit1 is set.
>
> Signed-off-by: Peter Yin <peteryin.openbmc@gmail.com>
> ---
> drivers/watchdog/aspeed_wdt.c | 35 +++++++++++++++++++++++++++++++----
> 1 file changed, 31 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/watchdog/aspeed_wdt.c b/drivers/watchdog/aspeed_wdt.c
> index b4773a6aaf8c..0e7ef860cbdc 100644
> --- a/drivers/watchdog/aspeed_wdt.c
> +++ b/drivers/watchdog/aspeed_wdt.c
> @@ -11,10 +11,12 @@
> #include <linux/io.h>
> #include <linux/kernel.h>
> #include <linux/kstrtox.h>
> +#include <linux/mfd/syscon.h>
> #include <linux/module.h>
> #include <linux/of.h>
> #include <linux/of_irq.h>
> #include <linux/platform_device.h>
> +#include <linux/regmap.h>
> #include <linux/watchdog.h>
>
> static bool nowayout = WATCHDOG_NOWAYOUT;
> @@ -77,11 +79,19 @@ MODULE_DEVICE_TABLE(of, aspeed_wdt_of_table);
> #define WDT_TIMEOUT_STATUS 0x10
> #define WDT_TIMEOUT_STATUS_IRQ BIT(2)
> #define WDT_TIMEOUT_STATUS_BOOT_SECONDARY BIT(1)
> +#define WDT_TIMEOUT_STATUS_EVENT BIT(0)
> #define WDT_CLEAR_TIMEOUT_STATUS 0x14
> #define WDT_CLEAR_TIMEOUT_AND_BOOT_CODE_SELECTION BIT(0)
> #define WDT_RESET_MASK1 0x1c
> #define WDT_RESET_MASK2 0x20
>
> +/*
> + * Ast2600 SCU74 bit1 is External reset flag
> + * Ast2500 SCU3C bit1 is External reset flag
> + */
> +#define AST2500_SYSTEM_RESET_EVENT 0x3C
> +#define AST2600_SYSTEM_RESET_EVENT 0x74
> +#define EXTERN_RESET_FLAG BIT(1)
> /*
> * WDT_RESET_WIDTH controls the characteristics of the external pulse (if
> * enabled), specifically:
> @@ -330,6 +340,11 @@ static int aspeed_wdt_probe(struct platform_device *pdev)
> if (IS_ERR(wdt->base))
> return PTR_ERR(wdt->base);
>
> + struct regmap *scu_base = syscon_regmap_lookup_by_phandle(dev->of_node,
> + "aspeed,scu");
> + if (IS_ERR(scu_base))
> + return PTR_ERR(scu_base);
> +
> wdt->wdd.info = &aspeed_wdt_info;
>
> if (wdt->cfg->irq_mask) {
> @@ -459,14 +474,26 @@ static int aspeed_wdt_probe(struct platform_device *pdev)
> }
>
> status = readl(wdt->base + WDT_TIMEOUT_STATUS);
> - if (status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY) {
> + if (status & WDT_TIMEOUT_STATUS_EVENT)
> wdt->wdd.bootstatus = WDIOF_CARDRESET;
>
> - if (of_device_is_compatible(np, "aspeed,ast2400-wdt") ||
> - of_device_is_compatible(np, "aspeed,ast2500-wdt"))
> - wdt->wdd.groups = bswitch_groups;
> + if (of_device_is_compatible(np, "aspeed,ast2600-wdt")) {
> + ret = regmap_read(scu_base,
> + AST2600_SYSTEM_RESET_EVENT,
> + &status);
> + } else {
> + ret = regmap_read(scu_base,
> + AST2500_SYSTEM_RESET_EVENT,
> + &status);
> + wdt->wdd.groups = bswitch_groups;
> }
>
> + /*
> + * Reset cause by Extern Reset
> + */
> + if (status & EXTERN_RESET_FLAG && !ret)
> + wdt->wdd.bootstatus |= WDIOF_EXTERN1;
> +
> dev_set_drvdata(dev, wdt);
>
> return devm_watchdog_register_device(dev, &wdt->wdd);
Hi Guenter,
Could you help me understand the definition of WDIOF_CARDRESET in
the kernel? If it resets the CPU, should all values be reset to default?
Should we check the POR (RstPwr Power on reset SRST# flag) flag in SCU
0x74 register bit 0 in ast2600?
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^ permalink raw reply
* Re: [PATCH v7 2/3] dt-bindings: pinctrl: Document nuvoton ma35d1 pin control
From: Rob Herring @ 2024-04-09 16:29 UTC (permalink / raw)
To: Jacky Huang
Cc: linus.walleij, krzysztof.kozlowski+dt, conor+dt, p.zabel,
j.neuschaefer, linux-arm-kernel, linux-gpio, devicetree,
linux-kernel, ychuang3, schung, Krzysztof Kozlowski
In-Reply-To: <20240409095637.2135-3-ychuang570808@gmail.com>
On Tue, Apr 09, 2024 at 09:56:36AM +0000, Jacky Huang wrote:
> From: Jacky Huang <ychuang3@nuvoton.com>
>
> Add documentation to describe nuvoton ma35d1 pin control and GPIO.
>
> Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
> .../pinctrl/nuvoton,ma35d1-pinctrl.yaml | 163 ++++++++++++++++++
> 1 file changed, 163 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/nuvoton,ma35d1-pinctrl.yaml
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/nuvoton,ma35d1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/nuvoton,ma35d1-pinctrl.yaml
> new file mode 100644
> index 000000000000..8b9ec263213f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/nuvoton,ma35d1-pinctrl.yaml
> @@ -0,0 +1,163 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pinctrl/nuvoton,ma35d1-pinctrl.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Nuvoton MA35D1 pin control and GPIO
> +
> +maintainers:
> + - Shan-Chun Hung <schung@nuvoton.com>
> + - Jacky Huang <ychuang3@nuvoton.com>
> +
> +allOf:
> + - $ref: pinctrl.yaml#
> +
> +properties:
> + compatible:
> + enum:
> + - nuvoton,ma35d1-pinctrl
> +
> + '#address-cells':
> + const: 1
> +
> + '#size-cells':
> + const: 1
> +
> + nuvoton,sys:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + phandle of the system-management node.
If these are the *only* registers to access the pinctrl functions, then
this binding should be a child node of the system-management node and
then you don't need this property.
And if the registers for pinctrl are a defined range, you should add a
'reg' property (even though Linux and regmap don't use it).
> +
> + ranges: true
This property makes no sense with the binding as-is. You don't have
any address to translate. Maybe with the above changes it will.
> +
> +patternProperties:
> + "^gpio@[0-9a-f]+$":
> + type: object
> + additionalProperties: false
> + properties:
> + gpio-controller: true
> +
> + '#gpio-cells':
> + const: 2
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + interrupt-controller: true
> +
> + '#interrupt-cells':
> + const: 2
> +
> + interrupts:
> + description:
> + The interrupt outputs to sysirq.
> + maxItems: 1
> +
> + required:
> + - gpio-controller
> + - '#gpio-cells'
> + - reg
> + - clocks
> + - interrupt-controller
> + - '#interrupt-cells'
> + - interrupts
> +
> + "^pin-[a-z0-9]+$":
> + type: object
> + description:
> + A pinctrl node should contain at least one subnodes representing the
> + pinctrl groups available on the machine. Each subnode will list the
> + pins it needs, and how they should be configured, with regard to muxer
> + configuration, pullups, drive strength, input enable/disable and input
> + schmitt.
> +
> + $ref: pincfg-node.yaml#
> +
> + properties:
> + power-source:
> + description: |
> + Valid arguments are described as below:
> + 0: power supply of 1.8V
> + 1: power supply of 3.3V
> + enum: [0, 1]
> +
> + drive-strength-microamp:
> + oneOf:
> + - enum: [ 2900, 4400, 5800, 7300, 8600, 10100, 11500, 13000 ]
> + description: 1.8V I/O driving strength
> + - enum: [ 17100, 25600, 34100, 42800, 48000, 56000, 77000, 82000 ]
> + description: 3.3V I/O driving strength
> +
> + unevaluatedProperties: false
In the indented cases, it's preferred to put this before 'properties'.
> +
> + "-grp$":
> + type: object
> + description:
> + Pinctrl node's client devices use subnodes for desired pin configuration.
> + Client device subnodes use below standard properties.
Missing $ref to common properties and 'unevaluatedProperties'.
> + properties:
> + nuvoton,pins:
> + description:
> + Each entry consists of 4 parameters and represents the mux and config
> + setting for one pin.
> + $ref: /schemas/types.yaml#/definitions/uint32-matrix
> + minItems: 1
> + items:
> + items:
> + - minimum: 0
> + maximum: 13
> + description:
> + Pin bank.
> + - minimum: 0
> + maximum: 15
> + description:
> + Pin bank index.
> + - minimum: 0
> + maximum: 15
> + description:
> + Mux 0 means GPIO and mux 1 to 15 means the specific device function.
> +
> +required:
> + - compatible
> + - nuvoton,sys
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/gpio/gpio.h>
> + #include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
> +
> + pinctrl@40040000 {
> + compatible = "nuvoton,ma35d1-pinctrl";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + nuvoton,sys = <&sys>;
> + ranges = <0 0x40040000 0xc00>;
> +
> + gpio@0 {
> + reg = <0x0 0x40>;
> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk GPA_GATE>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + uart-grp {
> + uart11-pins {
This is not what the schema says.
> + nuvoton,pins = <11 0 2>,
> + <11 1 2>,
> + <11 2 2>,
> + <11 3 2>;
> + bias-disable;
> + power-source = <1>;
> + };
> + };
Include a pin-* node in the example.
> + };
> --
> 2.34.1
>
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^ permalink raw reply
* Re: [PATCH v2] PCI: rockchip-host: Fix rockchip_pcie_host_init_port() PERST# handling
From: Bjorn Helgaas @ 2024-04-09 16:15 UTC (permalink / raw)
To: Damien Le Moal
Cc: Shawn Lin, Bjorn Helgaas, Heiko Stuebner, linux-pci,
Lorenzo Pieralisi, Krzysztof Wilczyński, linux-rockchip,
linux-arm-kernel
In-Reply-To: <20240330035043.1546087-1-dlemoal@kernel.org>
On Sat, Mar 30, 2024 at 12:50:43PM +0900, Damien Le Moal wrote:
> The PCIe specifications (PCI Express Electromechanical Specification rev
> 2.0, section 2.6.2) mandate that the PERST# signal must remain asserted
> for at least 100 usec (Tperst-clk) after the PCIe reference clock
> becomes stable (if a reference clock is supplied), for at least 100 msec
> after the power is stable (Tpvperl).
Reference current spec, e.g., "PCIe CEM r5.1, sec 2.9.2" and a note
about why you mention two parameters here but the code change only
uses one of them.
> In addition, the PCI Express Base SPecification Rev 2.0, section 6.6.1
> state that the host should wait for at least 100 msec from the end of a
> conventional reset (PERST# is de-asserted) before accessing the
> configuration space of the attached device.
Current spec, e.g., "PCIe r6.0, sec 6.6.1".
> Modify rockchip_pcie_host_init_port() by adding two 100ms sleep, one
> before and after bringing back PESRT signal to high using the ep_gpio
> GPIO. Comments are also added to clarify this behavior.
s/PESRT/PERST#/
This is two separate changes that really would be better as separate
patches.
> Signed-off-by: Damien Le Moal <dlemoal@kernel.org>
> ---
>
> Changes from v1:
> - Add more specification details to the commit message.
> - Add missing msleep(100) after PERST# is deasserted.
>
> drivers/pci/controller/pcie-rockchip-host.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/pci/controller/pcie-rockchip-host.c b/drivers/pci/controller/pcie-rockchip-host.c
> index 300b9dc85ecc..ff2fa27bd883 100644
> --- a/drivers/pci/controller/pcie-rockchip-host.c
> +++ b/drivers/pci/controller/pcie-rockchip-host.c
> @@ -294,6 +294,7 @@ static int rockchip_pcie_host_init_port(struct rockchip_pcie *rockchip)
> int err, i = MAX_LANE_NUM;
> u32 status;
>
> + /* Assert PERST */
> gpiod_set_value_cansleep(rockchip->ep_gpio, 0);
>
> err = rockchip_pcie_init_port(rockchip);
> @@ -322,8 +323,19 @@ static int rockchip_pcie_host_init_port(struct rockchip_pcie *rockchip)
> rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
> PCIE_CLIENT_CONFIG);
>
> + /*
> + * PCIe CME specifications mandate that PERST be asserted for at
> + * least 100ms after power is stable.
> + */
Remove comment completely (given use of PCIE_T_PVPERL_MS below).
> + msleep(100);
s/100/PCIE_T_PVPERL_MS/
> gpiod_set_value_cansleep(rockchip->ep_gpio, 1);
>
> + /*
> + * PCIe base specifications rev 2.0 mandate that the host wait for
> + * 100ms after completion of a conventional reset.
> + */
> + msleep(100);
Please add a #define for this since it's generic across all PCIe, not
just Rockchip.
I don't think the PCIe spec actually names this parameter. It's
similar to T_rhfa (Conventional PCI r3.0, sec 4.3.2), although I think
devices must be ready to accept config cycles after T_rhfa.
This delay is a little different because IIUC, a PCIe device doesn't
have to be "Configuration Ready"; after 100ms, it only has to be able
to respond with a "Request Retry Status" completion if it isn't
Configuration Ready yet.
So I think we should add something like
#define PCIE_T_RRS_READY_MS 100
to drivers/pci/pci.h for this case.
> /* 500ms timeout value should be enough for Gen1/2 training */
> err = readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_BASIC_STATUS1,
> status, PCIE_LINK_UP(status), 20,
> --
> 2.44.0
>
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^ permalink raw reply
* Re: [PATCH] KVM: arm64: Add support for FFA_PARTITION_INFO_GET
From: Vincent Donnefort @ 2024-04-09 16:15 UTC (permalink / raw)
To: Sebastian Ene
Cc: catalin.marinas, james.morse, jean-philippe, maz, oliver.upton,
qperret, qwandor, sudeep.holla, suzuki.poulose, tabba, will,
yuzenghui, kvmarm, linux-arm-kernel, linux-kernel, kernel-team
In-Reply-To: <20240409151908.541589-1-sebastianene@google.com>
Hi Seb,
On Tue, Apr 09, 2024 at 03:19:08PM +0000, Sebastian Ene wrote:
> Handle the FFA_PARTITION_INFO_GET host call inside the pKVM hypervisor
> and copy the response message back to the host buffers. Save the
> returned FF-A version as we will need it later to interpret the response
> from the TEE.
>
> Signed-off-by: Sebastian Ene <sebastianene@google.com>
> ---
> arch/arm64/kvm/hyp/nvhe/ffa.c | 49 +++++++++++++++++++++++++++++++++++
> 1 file changed, 49 insertions(+)
>
> diff --git a/arch/arm64/kvm/hyp/nvhe/ffa.c b/arch/arm64/kvm/hyp/nvhe/ffa.c
> index 320f2eaa14a9..72fc365bc7a8 100644
> --- a/arch/arm64/kvm/hyp/nvhe/ffa.c
> +++ b/arch/arm64/kvm/hyp/nvhe/ffa.c
> @@ -67,6 +67,7 @@ struct kvm_ffa_buffers {
> */
> static struct kvm_ffa_buffers hyp_buffers;
> static struct kvm_ffa_buffers host_buffers;
> +static u32 ffa_version;
>
> static void ffa_to_smccc_error(struct arm_smccc_res *res, u64 ffa_errno)
> {
> @@ -640,6 +641,49 @@ static bool do_ffa_features(struct arm_smccc_res *res,
> return true;
> }
>
> +static void do_ffa_part_get(struct arm_smccc_res *res,
> + struct kvm_cpu_context *ctxt)
> +{
> + DECLARE_REG(u32, uuid0, ctxt, 1);
> + DECLARE_REG(u32, uuid1, ctxt, 2);
> + DECLARE_REG(u32, uuid2, ctxt, 3);
> + DECLARE_REG(u32, uuid3, ctxt, 4);
> + DECLARE_REG(u32, flags, ctxt, 5);
> + u32 off, count, sz, buf_sz;
> +
> + hyp_spin_lock(&host_buffers.lock);
> + if (!host_buffers.rx) {
> + ffa_to_smccc_res(res, FFA_RET_INVALID_PARAMETERS);
> + goto out_unlock;
> + }
> +
> + arm_smccc_1_1_smc(FFA_PARTITION_INFO_GET, uuid0, uuid1,
> + uuid2, uuid3, flags, 0, 0,
> + res);
> +
> + if (res->a0 != FFA_SUCCESS)
> + goto out_unlock;
> +
> + count = res->a2;
> + if (!count)
> + goto out_unlock;
Looking at the table 13.34, it seems what's in "count" depends on the flag.
Shouldn't we check its value, and only memcpy into the host buffers if the flag
is 0?
> +
> + if (ffa_version > FFA_VERSION_1_0) {
> + buf_sz = sz = res->a3;
> + if (sz > sizeof(struct ffa_partition_info))
> + buf_sz = sizeof(struct ffa_partition_info);
What are you trying to protect against here? We have to trust EL3 anyway, (as
other functions do).
The WARN() could be kept though to make sure we won't overflow our buffer. But
it could be transformed into an error? FFA_RET_ABORTED?
> + } else {
> + /* FFA_VERSION_1_0 lacks the size in the response */
> + buf_sz = sz = 8;
> + }
> +
> + WARN_ON((count - 1) * sz + buf_sz > PAGE_SIZE);
> + for (off = 0; off < count * sz; off += sz)
> + memcpy(host_buffers.rx + off, hyp_buffers.rx + off, buf_sz);
> +out_unlock:
> + hyp_spin_unlock(&host_buffers.lock);
> +}
> +
> bool kvm_host_ffa_handler(struct kvm_cpu_context *host_ctxt, u32 func_id)
> {
> struct arm_smccc_res res;
> @@ -686,6 +730,9 @@ bool kvm_host_ffa_handler(struct kvm_cpu_context *host_ctxt, u32 func_id)
> case FFA_MEM_FRAG_TX:
> do_ffa_mem_frag_tx(&res, host_ctxt);
> goto out_handled;
> + case FFA_PARTITION_INFO_GET:
> + do_ffa_part_get(&res, host_ctxt);
> + break;
> }
>
> if (ffa_call_supported(func_id))
> @@ -726,6 +773,8 @@ int hyp_ffa_init(void *pages)
> if (FFA_MAJOR_VERSION(res.a0) != 1)
> return -EOPNOTSUPP;
>
> + ffa_version = res.a0;
> +
> arm_smccc_1_1_smc(FFA_ID_GET, 0, 0, 0, 0, 0, 0, 0, &res);
> if (res.a0 != FFA_SUCCESS)
> return -EOPNOTSUPP;
> --
> 2.44.0.478.gd926399ef9-goog
>
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^ permalink raw reply
* Re: [PATCH] arm64: arm_pmuv3: Correctly extract and check the PMUVer
From: Will Deacon @ 2024-04-09 16:09 UTC (permalink / raw)
To: Yicong Yang
Cc: mark.rutland, catalin.marinas, broonie, linux-arm-kernel,
linux-kernel, jonathan.cameron, prime.zeng, linuxarm, yangyicong
In-Reply-To: <20240408081158.15291-1-yangyicong@huawei.com>
On Mon, Apr 08, 2024 at 04:11:58PM +0800, Yicong Yang wrote:
> From: Yicong Yang <yangyicong@hisilicon.com>
>
> Currently we're using "sbfx" to extract the PMUVer from ID_AA64DFR0_EL1
> and skip the init/reset if no PMU present when the extracted PMUVer is
> negative or is zero. However for PMUv3p8 the PMUVer will be 0b1000 and
> PMUVer extracted by "sbfx" will always be negative and we'll skip the
> init/reset in __init_el2_debug/reset_pmuserenr_el0 unexpectedly.
>
> So this patch use "ubfx" instead of "sbfx" to extract the PMUVer. If
> the PMUVer is implementation defined (0b1111) then reset it to zero
> and skip the reset/init. Previously we'll also skip the init/reset
> if the PMUVer is higher than the version we known (currently PMUv3p9),
> with this patch we'll only skip if the PMU is not implemented or
> implementation defined. This keeps consistence with how we probe
> the PMU in the driver with pmuv3_implemented().
>
> Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
> ---
> arch/arm64/include/asm/assembler.h | 5 ++++-
> arch/arm64/include/asm/el2_setup.h | 5 ++++-
> 2 files changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h
> index ab8b396428da..3b7373d6c565 100644
> --- a/arch/arm64/include/asm/assembler.h
> +++ b/arch/arm64/include/asm/assembler.h
> @@ -480,7 +480,10 @@ alternative_endif
> */
> .macro reset_pmuserenr_el0, tmpreg
> mrs \tmpreg, id_aa64dfr0_el1
> - sbfx \tmpreg, \tmpreg, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4
> + ubfx \tmpreg, \tmpreg, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4
> + cmp \tmpreg, #ID_AA64DFR0_EL1_PMUVer_IMP_DEF
> + csel \tmpreg, xzr, \tmpreg, eq // If PMU's IMP_DEF, regard it
> + // as not implemented and skip
> cmp \tmpreg, #1 // Skip if no PMU present
> b.lt 9000f
> msr pmuserenr_el0, xzr // Disable PMU access from EL0
I think the cmp/csel/cmp/b.lt sequence might be a little tidier if you
reworked it to use ccmp. For example, something like (totally untested):
cmp \tmpreg, ID_AA64DFR0_EL1_PMUVer_NI
ccmp \tmpreg, ID_AA64DFR0_EL1_PMUVer_IMP_DEF, #4, ne
would then, I think, mean we could just b.eq 9000f. But please check
this because encoding nzcv as an immediate always catches me out.
> diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
> index b7afaa026842..2438e12b60c5 100644
> --- a/arch/arm64/include/asm/el2_setup.h
> +++ b/arch/arm64/include/asm/el2_setup.h
> @@ -59,7 +59,10 @@
>
> .macro __init_el2_debug
> mrs x1, id_aa64dfr0_el1
> - sbfx x0, x1, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4
> + ubfx x0, x1, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4
> + cmp x0, #ID_AA64DFR0_EL1_PMUVer_IMP_DEF
> + csel x0, xzr, x0, eq // If PMU's IMP_DEF, regard it
> + // as not implemented and skip
> cmp x0, #1
> b.lt .Lskip_pmu_\@ // Skip if no PMU present
> mrs x0, pmcr_el0 // Disable debug access traps
Similar sort of thing here.
Will
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^ permalink raw reply
* Re: [PATCH 1/1] arm64: dts: imx8qxp-mek: add cm40_i2c, wm8960/wm8962 and sai[0,1,4,5]
From: Frank Li @ 2024-04-09 16:02 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
open list
In-Reply-To: <76714850-0e02-4333-acce-02c7657666b0@linaro.org>
On Tue, Apr 09, 2024 at 08:33:22AM +0200, Krzysztof Kozlowski wrote:
> On 08/04/2024 17:36, Frank Li wrote:
> > On Fri, Apr 05, 2024 at 08:21:18PM +0200, Krzysztof Kozlowski wrote:
> >> On 05/04/2024 16:46, Frank Li wrote:
> >>> On Fri, Apr 05, 2024 at 08:41:59AM +0200, Krzysztof Kozlowski wrote:
> >>>> On 04/04/2024 18:19, Frank Li wrote:
> >>>>> imx8qxp-mek use two kind audio codec, wm8960 and wm8962. Using dummy gpio
> >>>>> i2c bus mux to connect both i2c devices. One will probe failure and other
> >>>>> will probe success when devices driver check whoami. So one dtb can cover
> >>>>> both board configuration.
> >>>>
> >>>> I don't understand it. Either you add real device or not. If one board
> >>>> has two devices, then why do you need to check for failures?
> >>>>
> >>>> Anyway, don't add fake stuff to DTS.
> >>>
> >>> NAK can't resolve the problem. It should be common problem for long time
> >>> cycle boards. Some chipes will be out life cycle. such as some sensor. So
> >>> chips on boards have been replace by some pin to pin compatible sensor. For
> >>> example:
> >>> old boards: use sensor A with address 0x1a
> >>> new bench: use sensor B with address 0x1b.
> >>>
> >>> You can treat it as two kind boards, RevA or RevB. But most user want to
> >>> use one dtb to handle such small differences. For this case, it should be
> >>> simple. Just add a super set.
> >>> i2c
> >>> {
> >>> sensorA@1a
> >>> {
> >>> }
> >>> sensorB@1b
> >>> {
> >>> }
> >>> }
> >>>
> >>> It also depend on whoami check by i2c devices. Only A or B will probe.
> >>>
> >>> wm8960 and wm8962 are more complex example. wm8960 is out of life. But
> >>> wm8962 and wm8960 have the same i2c address. The current i2c frame can't
> >>> allow the same i2c address in one i2c bus.
> >>>
> >>> You are feel to NAK my method, but I hope you also provide constructive
> >>> solution to help resolve the problem.
> >>
> >> Yes, we resolved it long time ago. Your bootloader can (usually easily)
> >> detect revision of the board and load appropriate DTS or DTS+DTSO.
> >
> > I knewn it. But the problem is one development boards A have many options,
> > so create many child dts for files, A1, A2, ... An which base on A
>
> So use DTSO, what's the problem? Other vendors, liek Rpi does not have
> problem with it and it works well. No confusion.
>
> >
> > If there are difference happen at A, create new B. then create all child
> > dtb, B1, B2, ... Bn. DTB number will increase exponent.
> >
> > If change is quite bit, we have to do that. But if change is quite small,
> > One dtb can cover it by driver auto detect, which will work like some
> > adaptor card have not plug into boards, or some sensor or NOR-flash have
> > not installed because reduce cost.
>
> You have two boards, not 20 here!
Actually, it is around ~20 derived boards. It is not upstream just because
we have not time to do that yet. After some clean up, I estimate about 7 -
- 10.
>
> >
> > Although boot loader can update dts or choose difference dts, It also cause
> > many confusition, such as layerscape, uboot update many kernel dtb's
> > information, which actually increase dependence between uboot and kernel.
> > Also it confuse people, for example, when try to debug kernel dtb, why
> > change have not token affect when change dts because not realized uboot
> > over write it.
> >
> > What's I dide is that trying to reduce unnecessary dts.
>
> There is no confusion. That's normal process, so if someone is confused
> by having variants of board, this someone will be even more confused by
> seeing non-existing hardware in his DTS.
How about existed dummy_clk and dummy regulator in dts?
>
> This problem was solved long time ago and you do not bring any
> reasonable new arguments. All vendors solved it (just look at ongoing
> discussions on board id) but only you have problem with their solution.
I never said solution was not work. Just not friend for user enough for
this case. It likes USB TypeC vs USB A port. Both works, just TypeC can't
care direction.
>
> NAK
>
> Best regards,
> Krzysztof
>
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^ permalink raw reply
* Re: [PATCH v3 18/18] arm64: dts: mediatek: add audio support for mt8365-evk
From: Krzysztof Kozlowski @ 2024-04-09 16:00 UTC (permalink / raw)
To: Alexandre Mergnat, Liam Girdwood, Mark Brown, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Lee Jones, Flora Fu, Jaroslav Kysela,
Takashi Iwai, Sumit Semwal, Christian König, Catalin Marinas,
Will Deacon, Rob Herring
Cc: linux-sound, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, linux-media, dri-devel, linaro-mm-sig
In-Reply-To: <20240226-audio-i350-v3-18-16bb2c974c55@baylibre.com>
On 09/04/2024 15:42, Alexandre Mergnat wrote:
> Add the sound node which is linked to the MT8365 SoC AFE and
> the MT6357 audio codec.
>
> Update the file header.
>
> Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 98 +++++++++++++++++++++++++++--
> 1 file changed, 94 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
> index 50cbaefa1a99..eb0c5f076dd4 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
> +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts
> @@ -1,9 +1,9 @@
> // SPDX-License-Identifier: GPL-2.0
> /*
> - * Copyright (c) 2021-2022 BayLibre, SAS.
> - * Authors:
> - * Fabien Parent <fparent@baylibre.com>
> - * Bernhard Rosenkränzer <bero@baylibre.com>
> + * Copyright (c) 2024 BayLibre, SAS.
What is happening with your copyrights? Why do you change existing ones?
> + * Authors: Fabien Parent <fparent@baylibre.com>
> + * Bernhard Rosenkränzer <bero@baylibre.com>
> + * Alexandre Mergnat <amergnat@baylibre.com>
> */
>
> /dts-v1/;
> @@ -86,6 +86,29 @@ optee_reserved: optee@43200000 {
> reg = <0 0x43200000 0 0x00c00000>;
> };
> };
> +
> + sound: sound {
> + compatible = "mediatek,mt8365-mt6357";
> + pinctrl-names = "default",
> + "dmic",
> + "miso_off",
> + "miso_on",
> + "mosi_off",
> + "mosi_on";
> + pinctrl-0 = <&aud_default_pins>;
> + pinctrl-1 = <&aud_dmic_pins>;
> + pinctrl-2 = <&aud_miso_off_pins>;
> + pinctrl-3 = <&aud_miso_on_pins>;
> + pinctrl-4 = <&aud_mosi_off_pins>;
> + pinctrl-5 = <&aud_mosi_on_pins>;
> + mediatek,platform = <&afe>;
> + status = "okay";
Where did you disable the node?
> + };
> +};
> +
> +&afe {
> + mediatek,dmic-mode = <1>;
> + status = "okay";
> };
>
> &cpu0 {
> @@ -174,6 +197,12 @@ &mmc1 {
> status = "okay";
> };
>
> +&mt6357_codec {
> + mediatek,micbias0-microvolt = <1900000>;
> + mediatek,micbias1-microvolt = <1700000>;
> + mediatek,vaud28-supply = <&mt6357_vaud28_reg>;
> +};
> +
> &mt6357_pmic {
> interrupts-extended = <&pio 145 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-controller;
> @@ -181,6 +210,67 @@ &mt6357_pmic {
> };
>
> &pio {
> + aud_default_pins: audiodefault-pins {
> + pins {
> + pinmux = <MT8365_PIN_72_CMDAT4__FUNC_I2S3_BCK>,
> + <MT8365_PIN_73_CMDAT5__FUNC_I2S3_LRCK>,
> + <MT8365_PIN_74_CMDAT6__FUNC_I2S3_MCK>,
> + <MT8365_PIN_75_CMDAT7__FUNC_I2S3_DO>;
You have broken indentation everywhere.
Best regards,
Krzysztof
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^ permalink raw reply
* Re: [PATCH v3 16/18] arm64: dts: mediatek: add mt6357 audio codec support
From: Krzysztof Kozlowski @ 2024-04-09 15:58 UTC (permalink / raw)
To: Alexandre Mergnat, Liam Girdwood, Mark Brown, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Lee Jones, Flora Fu, Jaroslav Kysela,
Takashi Iwai, Sumit Semwal, Christian König, Catalin Marinas,
Will Deacon, Rob Herring
Cc: linux-sound, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, linux-media, dri-devel, linaro-mm-sig
In-Reply-To: <20240226-audio-i350-v3-16-16bb2c974c55@baylibre.com>
On 09/04/2024 15:42, Alexandre Mergnat wrote:
> Add audio codec support of MT6357 PMIC.
> Update the file header.
Why?
>
> Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
> ---
> arch/arm64/boot/dts/mediatek/mt6357.dtsi | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt6357.dtsi b/arch/arm64/boot/dts/mediatek/mt6357.dtsi
> index 3330a03c2f74..ade410851524 100644
> --- a/arch/arm64/boot/dts/mediatek/mt6357.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt6357.dtsi
> @@ -1,7 +1,7 @@
> // SPDX-License-Identifier: (GPL-2.0 OR MIT)
> /*
> * Copyright (c) 2020 MediaTek Inc.
> - * Copyright (c) 2023 BayLibre Inc.
> + * Copyright (c) 2024 BayLibre Inc.
That's not a reasonable change. The file was published on 2023, wasn't
it? If this is not correct, please explain why/how and make it separate
patch.
> */
>
> #include <dt-bindings/input/input.h>
> @@ -10,6 +10,9 @@ &pwrap {
> mt6357_pmic: pmic {
> compatible = "mediatek,mt6357";
>
> + mt6357_codec: codec {
> + };
There is no single point of having empty nodes.
NAK.
Best regards,
Krzysztof
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^ permalink raw reply
* Re: [PATCH v3 04/18] dt-bindings: mfd: mediatek: Add codec property for MT6357 PMIC
From: Krzysztof Kozlowski @ 2024-04-09 15:56 UTC (permalink / raw)
To: Alexandre Mergnat, Liam Girdwood, Mark Brown, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Lee Jones, Flora Fu, Jaroslav Kysela,
Takashi Iwai, Sumit Semwal, Christian König, Catalin Marinas,
Will Deacon, Rob Herring
Cc: linux-sound, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, linux-media, dri-devel, linaro-mm-sig
In-Reply-To: <20240226-audio-i350-v3-4-16bb2c974c55@baylibre.com>
On 09/04/2024 15:42, Alexandre Mergnat wrote:
> Add the audio codec sub-device. This sub-device is used to set required
> and optional voltage properties between the codec and the board.
>
> Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
> ---
> Documentation/devicetree/bindings/mfd/mediatek,mt6357.yaml | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mfd/mediatek,mt6357.yaml b/Documentation/devicetree/bindings/mfd/mediatek,mt6357.yaml
> index 37423c2e0fdf..7c6a4a587b5f 100644
> --- a/Documentation/devicetree/bindings/mfd/mediatek,mt6357.yaml
> +++ b/Documentation/devicetree/bindings/mfd/mediatek,mt6357.yaml
> @@ -37,6 +37,11 @@ properties:
> "#interrupt-cells":
> const: 2
>
> + codec:
> + type: object
> + $ref: /schemas/sound/mt6357.yaml
> + unevaluatedProperties: false
Just put the properties here, without the codec node.
Also, your example is now incomplete.
Best regards,
Krzysztof
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^ permalink raw reply
* Re: [PATCH v2] rust: add flags for shadow call stack sanitizer
From: Miguel Ojeda @ 2024-04-09 15:55 UTC (permalink / raw)
To: Will Deacon
Cc: Alice Ryhl, Catalin Marinas, Jamie Cunliffe, Sami Tolvanen,
Masahiro Yamada, Nathan Chancellor, Nicolas Schier,
Ard Biesheuvel, Marc Zyngier, Mark Rutland, Mark Brown,
Nick Desaulniers, Kees Cook, Miguel Ojeda, Alex Gaynor,
Wedson Almeida Filho, Boqun Feng, Gary Guo, Björn Roy Baron,
Benno Lossin, Andreas Hindborg, Valentin Obst, linux-kbuild,
linux-kernel, linux-arm-kernel, rust-for-linux
In-Reply-To: <20240409103120.GA22557@willie-the-truck>
On Tue, Apr 9, 2024 at 12:31 PM Will Deacon <will@kernel.org> wrote:
>
> I think we have time to do this properly, like we did for the clang
> enablement a few years ago. In hindsight, avoiding hacks for the early
> toolchains back then was a really good idea because it meant we could
> rely on a solid baseline set of compiler features from the start.
Yeah, it sounds fair, thanks!
After the warning is fixed (i.e. `-Zfixed-x18` or similar is
implemented etc.), I would recommend adding support to the kernel for
the `-Z` (unstable) flags, similar to this patch, in order to test
them easily and getting `rustc` to stabilize them. Then the only
change required should be a name change to `-C` or similar.
Cheers,
Miguel
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^ permalink raw reply
* Re: [PATCH v3 03/18] ASoC: dt-bindings: mt6357: Add audio codec document
From: Krzysztof Kozlowski @ 2024-04-09 15:55 UTC (permalink / raw)
To: Alexandre Mergnat, Liam Girdwood, Mark Brown, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Lee Jones, Flora Fu, Jaroslav Kysela,
Takashi Iwai, Sumit Semwal, Christian König, Catalin Marinas,
Will Deacon, Rob Herring
Cc: linux-sound, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, linux-media, dri-devel, linaro-mm-sig
In-Reply-To: <20240226-audio-i350-v3-3-16bb2c974c55@baylibre.com>
On 09/04/2024 15:42, Alexandre Mergnat wrote:
> Add MT8365 audio codec bindings to set required
> and optional voltage properties between the codec and the board.
> The properties are:
> - phandle of the requiered power supply.
typo
> - Setup of microphone bias voltage.
> - Setup of the speaker pin pull-down.
>
> Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
> ---
> .../devicetree/bindings/sound/mt6357.yaml | 54 ++++++++++++++++++++++
Filename using compatible syntax, so missing vendor prefix.
> 1 file changed, 54 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/sound/mt6357.yaml b/Documentation/devicetree/bindings/sound/mt6357.yaml
> new file mode 100644
> index 000000000000..381cb71b959f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/sound/mt6357.yaml
> @@ -0,0 +1,54 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/sound/mt6357.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek MT6357 Codec
> +
> +maintainers:
> + - Alexandre Mergnat <amergnat@baylibre.com>
> +
> +description: |
Do not need '|' unless you need to preserve formatting.
> + This is the required and optional voltage properties for this subdevice.
> + The communication between MT6357 and SoC is through Mediatek PMIC wrapper.
> + For more detail, please visit Mediatek PMIC wrapper documentation.
> + Must be a child node of PMIC wrapper.
Why?
> +
> +properties:
> +
Drop blank line
> + mediatek,hp-pull-down:
> + description:
> + Earphone driver positive output stage short to
> + the audio reference ground.
> + type: boolean
> +
> + mediatek,micbias0-microvolt:
> + description: Selects MIC Bias 0 output voltage.
> + enum: [1700000, 1800000, 1900000, 2000000,
> + 2100000, 2500000, 2600000, 2700000]
> + default: 1700000
> +
> + mediatek,micbias1-microvolt:
> + description: Selects MIC Bias 1 output voltage.
> + enum: [1700000, 1800000, 1900000, 2000000,
> + 2100000, 2500000, 2600000, 2700000]
> + default: 1700000
> +
> + mediatek,vaud28-supply:
> + description: 2.8 volt supply phandle for the audio codec
Supplies go without vendor prefixes.
> +
> +required:
> + - mediatek,vaud28-supply
That's basically no-op schema. I do not understand what you are trying
to achieve here.
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + codec {
> + mediatek,micbias0-microvolt = <1900000>;
> + mediatek,micbias1-microvolt = <1700000>;
> + mediatek,vaud28-supply = <&mt6357_vaud28_reg>;
Sorry, this does not work. Change voltage to 1111111 and check the results.
Best regards,
Krzysztof
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^ permalink raw reply
* Re: [PATCH v3 02/18] ASoC: dt-bindings: mediatek,mt8365-mt6357: Add audio sound card document
From: Krzysztof Kozlowski @ 2024-04-09 15:51 UTC (permalink / raw)
To: Alexandre Mergnat, Liam Girdwood, Mark Brown, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Lee Jones, Flora Fu, Jaroslav Kysela,
Takashi Iwai, Sumit Semwal, Christian König, Catalin Marinas,
Will Deacon, Rob Herring
Cc: linux-sound, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, linux-media, dri-devel, linaro-mm-sig
In-Reply-To: <20240226-audio-i350-v3-2-16bb2c974c55@baylibre.com>
On 09/04/2024 15:42, Alexandre Mergnat wrote:
> Add soundcard bindings for the MT8365 SoC with the MT6357 audio codec.
>
> Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
> +patternProperties:
> + "^dai-link-[0-9]+$":
> + type: object
> + description:
> + Container for dai-link level properties and CODEC sub-nodes.
> +
> + properties:
> + codec:
> + type: object
> + description: Holds subnode which indicates codec dai.
> +
> + properties:
> + sound-dai:
> + maxItems: 1
> + description: phandle of the codec DAI
> +
> + additionalProperties: false
> +
> + link-name:
> + description:
> + This property corresponds to the name of the BE dai-link to which
> + we are going to update parameters in this node.
> + items:
> + const: 2ND_I2S_BE
What is the type of link-name? Why is it fixed? How can you have here
multiple dai links if all of them must have the same name?
Best regards,
Krzysztof
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^ permalink raw reply
* Re: [PATCH v3 01/18] ASoC: dt-bindings: mediatek,mt8365-afe: Add audio afe document
From: Krzysztof Kozlowski @ 2024-04-09 15:46 UTC (permalink / raw)
To: Alexandre Mergnat, Liam Girdwood, Mark Brown, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Lee Jones, Flora Fu, Jaroslav Kysela,
Takashi Iwai, Sumit Semwal, Christian König, Catalin Marinas,
Will Deacon, Rob Herring
Cc: linux-sound, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, linux-media, dri-devel, linaro-mm-sig
In-Reply-To: <20240226-audio-i350-v3-1-16bb2c974c55@baylibre.com>
On 09/04/2024 15:41, Alexandre Mergnat wrote:
> Add MT8365 audio front-end bindings
>
> Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
> ---
> +properties:
> + compatible:
> + const: mediatek,mt8365-afe-pcm
> +
> + reg:
> + maxItems: 1
> +
> + "#sound-dai-cells":
> + const: 0
> +
> + clocks:
> + items:
> + - description: 26M clock
> + - description: mux for audio clock
> + - description: audio i2s0 mck
> + - description: audio i2s1 mck
> + - description: audio i2s2 mck
> + - description: audio i2s3 mck
> + - description: engen 1 clock
> + - description: engen 2 clock
> + - description: audio 1 clock
> + - description: audio 2 clock
> + - description: mux for i2s0
> + - description: mux for i2s1
> + - description: mux for i2s2
> + - description: mux for i2s3
> +
> + clock-names:
> + items:
> + - const: top_clk26m_clk
> + - const: top_audio_sel
> + - const: audio_i2s0_m
> + - const: audio_i2s1_m
> + - const: audio_i2s2_m
> + - const: audio_i2s3_m
> + - const: engen1
> + - const: engen2
> + - const: aud1
> + - const: aud2
> + - const: i2s0_m_sel
> + - const: i2s1_m_sel
> + - const: i2s2_m_sel
> + - const: i2s3_m_sel
> +
> + interrupts:
> + maxItems: 1
> +
> + power-domains:
> + maxItems: 1
> +
> + mediatek,dmic-mode:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + description:
> + Indicates how many data pins are used to transmit two channels of PDM
> + signal. 1 means two wires, 0 means one wire. Default value is 0.
> + enum:
> + - 0 # one wire
> + - 1 # two wires
> +
> + mediatek,topckgen:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description: The phandle of the mediatek topckgen controller
Nothing improved, so again, so something which is not obvious. What is
it used for? Why AFE needs topckgen for example?
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - interrupts
> + - power-domains
> + - mediatek,topckgen
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/mediatek,mt8365-clk.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interrupt-controller/irq.h>
> + #include <dt-bindings/power/mediatek,mt8365-power.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + afe@11220000 {
Did you implement the comment or decided to keep afe?
BTW, whatever "consistency" you have in mind, it does not really matter
that much for that example. And for sure do not add incorrect code
intentionally just to fix it in next patch.
Best regards,
Krzysztof
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^ permalink raw reply
* Re: [PATCH v2 1/3] dt-bindings: display: mediatek: Add OF graph support for board path
From: Dmitry Baryshkov @ 2024-04-09 15:45 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: chunkuang.hu, robh, krzysztof.kozlowski+dt, conor+dt, p.zabel,
airlied, daniel, maarten.lankhorst, mripard, tzimmermann,
matthias.bgg, shawn.sung, yu-chang.lee, ck.hu, jitao.shi,
devicetree, linux-kernel, dri-devel, linux-mediatek,
linux-arm-kernel, wenst, kernel
In-Reply-To: <8600acf8-7b51-456b-8a81-4233cfd6f121@collabora.com>
On Tue, 9 Apr 2024 at 18:41, AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com> wrote:
>
> Il 09/04/24 17:20, Dmitry Baryshkov ha scritto:
> > On Tue, Apr 09, 2024 at 02:02:09PM +0200, AngeloGioacchino Del Regno wrote:
> >> The display IPs in MediaTek SoCs support being interconnected with
> >> different instances of DDP IPs (for example, merge0 or merge1) and/or
> >> with different DDP IPs (for example, rdma can be connected with either
> >> color, dpi, dsi, merge, etc), forming a full Display Data Path that
> >> ends with an actual display.
> >>
> >> The final display pipeline is effectively board specific, as it does
> >> depend on the display that is attached to it, and eventually on the
> >> sensors supported by the board (for example, Adaptive Ambient Light
> >> would need an Ambient Light Sensor, otherwise it's pointless!), other
> >> than the output type.
> >
> > With the color and gamma being in play, should the configuration be
> > board-driver or rather use-case driven with the driver being able to
> > reroute some of the blocks at runtime?
> >
>
> The driver can already set some blocks to "BYPASS MODE" at runtime, meaning
> that those will work as simple pass-through, performing *no* processing at
> all, so that's addressed from the very beginning.
>
> This doesn't mean that a specific pipeline must always support the "DISP_GAMMA"
> or the "DISP_CCOLOR" block(s) alone, or together, or in combination with another
> specific block.
I was thinking about slightly different case: do you have enough
colour blocks to drive all outputs or do you have to select them for
the particular output only?
(excuse me, I didn't check the platform details).
> For any other question, clarification, etc, I'm here :-)
>
> Cheers!
>
> >>
> >> Add support for OF graphs to most of the MediaTek DDP (display) bindings
> >> to add flexibility to build custom hardware paths, hence enabling board
> >> specific configuration of the display pipeline and allowing to finally
> >> migrate away from using hardcoded paths.
> >>
> >> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> >
>
--
With best wishes
Dmitry
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^ permalink raw reply
* Re: [PATCH v2 1/3] dt-bindings: display: mediatek: Add OF graph support for board path
From: AngeloGioacchino Del Regno @ 2024-04-09 15:41 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: chunkuang.hu, robh, krzysztof.kozlowski+dt, conor+dt, p.zabel,
airlied, daniel, maarten.lankhorst, mripard, tzimmermann,
matthias.bgg, shawn.sung, yu-chang.lee, ck.hu, jitao.shi,
devicetree, linux-kernel, dri-devel, linux-mediatek,
linux-arm-kernel, wenst, kernel
In-Reply-To: <oe75tx35rd27r2a24ofdxfaqwr53tylfp5fwz3nrwc2uz6nmrs@vwc2krbpy3fh>
Il 09/04/24 17:20, Dmitry Baryshkov ha scritto:
> On Tue, Apr 09, 2024 at 02:02:09PM +0200, AngeloGioacchino Del Regno wrote:
>> The display IPs in MediaTek SoCs support being interconnected with
>> different instances of DDP IPs (for example, merge0 or merge1) and/or
>> with different DDP IPs (for example, rdma can be connected with either
>> color, dpi, dsi, merge, etc), forming a full Display Data Path that
>> ends with an actual display.
>>
>> The final display pipeline is effectively board specific, as it does
>> depend on the display that is attached to it, and eventually on the
>> sensors supported by the board (for example, Adaptive Ambient Light
>> would need an Ambient Light Sensor, otherwise it's pointless!), other
>> than the output type.
>
> With the color and gamma being in play, should the configuration be
> board-driver or rather use-case driven with the driver being able to
> reroute some of the blocks at runtime?
>
The driver can already set some blocks to "BYPASS MODE" at runtime, meaning
that those will work as simple pass-through, performing *no* processing at
all, so that's addressed from the very beginning.
This doesn't mean that a specific pipeline must always support the "DISP_GAMMA"
or the "DISP_CCOLOR" block(s) alone, or together, or in combination with another
specific block.
For any other question, clarification, etc, I'm here :-)
Cheers!
>>
>> Add support for OF graphs to most of the MediaTek DDP (display) bindings
>> to add flexibility to build custom hardware paths, hence enabling board
>> specific configuration of the display pipeline and allowing to finally
>> migrate away from using hardcoded paths.
>>
>> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
>
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^ permalink raw reply
* Re: [PATCH bpf] arm32, bpf: Fix sign-extension mov instruction
From: Russell King (Oracle) @ 2024-04-09 15:40 UTC (permalink / raw)
To: Puranjay Mohan
Cc: Alexei Starovoitov, Daniel Borkmann, Andrii Nakryiko,
Martin KaFai Lau, Eduard Zingerman, Song Liu, Yonghong Song,
John Fastabend, KP Singh, Stanislav Fomichev, Hao Luo, Jiri Olsa,
bpf, linux-arm-kernel, linux-kernel, puranjay12
In-Reply-To: <20240409095038.26356-1-puranjay@kernel.org>
On Tue, Apr 09, 2024 at 09:50:38AM +0000, Puranjay Mohan wrote:
> The current implementation of the mov instruction with sign extension
> clobbers the source register because it sign extends the source and then
> moves it to the destination.
>
> Fix this by moving the src to a temporary register before doing the sign
> extension only if src is not an emulated register (on the scratch stack).
>
> Also fix the emit_a32_movsx_r64() to put the register back on scratch
> stack if that register is emulated on stack.
It would be good to include in the commit message an example or two of
the resulting assembly code so that it's clear what the expected
generation is. Instead, I'm going to have to work it out myself, but
I'm quite sure this is information you already have.
> Fixes: fc832653fa0d ("arm32, bpf: add support for sign-extension mov instruction")
> Reported-by: syzbot+186522670e6722692d86@syzkaller.appspotmail.com
> Closes: https://lore.kernel.org/all/000000000000e9a8d80615163f2a@google.com/
> Signed-off-by: Puranjay Mohan <puranjay@kernel.org>
> ---
> arch/arm/net/bpf_jit_32.c | 11 +++++++++--
> 1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/net/bpf_jit_32.c b/arch/arm/net/bpf_jit_32.c
> index 1d672457d02f..8fde6ab66cb4 100644
> --- a/arch/arm/net/bpf_jit_32.c
> +++ b/arch/arm/net/bpf_jit_32.c
> @@ -878,6 +878,13 @@ static inline void emit_a32_mov_r(const s8 dst, const s8 src, const u8 off,
>
> rt = arm_bpf_get_reg32(src, tmp[0], ctx);
> if (off && off != 32) {
> + /* If rt is not a stacked register, move it to tmp, so it doesn't get clobbered by
> + * the shift operations.
> + */
> + if (rt == src) {
> + emit(ARM_MOV_R(tmp[0], rt), ctx);
> + rt = tmp[0];
> + }
This change is adding inefficiency, don't we want to have the JIT
creating as efficient code as possible within the bounds of
reasonableness?
> emit(ARM_LSL_I(rt, rt, 32 - off), ctx);
> emit(ARM_ASR_I(rt, rt, 32 - off), ctx);
LSL and ASR can very easily take a different source register to the
destination register. All this needs to be is:
emit(ARM_LSL_I(tmp[0], rt, 32 - off), ctx);
emit(ARM_ASR_I(tmp[0], tmp[0], 32 - off), ctx);
rt = tmp[0];
This will generate:
lsl tmp[0], src, #32-off
asr tmp[0], tmp[0], #32-off
and then the store to the output register will occur.
What about the high-32 bits of the register pair - should that be
taking any value?
> }
I notice in passing that the comments are out of sync with the
code - please update the comments along with code changes.
> @@ -919,15 +926,15 @@ static inline void emit_a32_movsx_r64(const bool is64, const u8 off, const s8 ds
> const s8 *tmp = bpf2a32[TMP_REG_1];
> const s8 *rt;
>
> - rt = arm_bpf_get_reg64(dst, tmp, ctx);
> -
> emit_a32_mov_r(dst_lo, src_lo, off, ctx);
> if (!is64) {
> if (!ctx->prog->aux->verifier_zext)
> /* Zero out high 4 bytes */
> emit_a32_mov_i(dst_hi, 0, ctx);
> } else {
> + rt = arm_bpf_get_reg64(dst, tmp, ctx);
> emit(ARM_ASR_I(rt[0], rt[1], 31), ctx);
> + arm_bpf_put_reg64(dst, rt, ctx);
> }
> }
Why oh why oh why are we emitting code to read the source register
(which may be a load), then write it to the destination (which may
be a store) to only then immediately reload from the destination
to then do the sign extension? This is madness.
Please... apply some thought to the code generation from the JIT...
or I will remove you from being a maintainer of this code. I spent
time crafting some parts of the JIT to generate efficient code and
I'm seeing that a lot of that work is now being thrown away by
someone who seemingly doesn't care about generating "good" code.
Why not read the source 32-bit register (potentially into a temporary
register), store it to the destination low register, then do the
sign extension into the destination high register or zero the high
register. We _could_ be a bit more optimal here by checking whether
dst_hi is a stacked register and use that directly for the ASR
instruction, omitting the need to move it there afterwards - whether
that's worth it or not depends on the performance we expect from this
eBPF opcode.
rt = arm_bpf_get_reg32(src_lo, tmp[1], ctx);
/* rt may be either src[1] or tmp[1] */
/* write dst_lo */
arm_bpf_put_reg32(dst_lo, rt, ctx)
if (is64) {
emit(ARM_ASR_I(tmp[0], rt, 31), ctx);
arm_bpf_put_reg32(dst_hi, tmp[0], ctx);
} else if (!ctx->prog->aux->verifier_zext) {
emit_a32_mov_i(dst_hi, 0, ctx);
}
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
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^ permalink raw reply
* Re: [PATCH v6 00/16] power: sequencing: implement the subsystem and add first users
From: Bartosz Golaszewski @ 2024-04-09 15:35 UTC (permalink / raw)
To: Xilin Wu
Cc: Marcel Holtmann, Luiz Augusto von Dentz, David S . Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Kalle Valo, Bjorn Andersson,
Konrad Dybcio, Liam Girdwood, Mark Brown, Catalin Marinas,
Will Deacon, Bjorn Helgaas, Saravana Kannan, Geert Uytterhoeven,
Arnd Bergmann, Neil Armstrong, Marek Szyprowski, Alex Elder,
Srini Kandagatla, Greg Kroah-Hartman, Abel Vesa,
Manivannan Sadhasivam, Lukas Wunner, Dmitry Baryshkov,
linux-bluetooth, netdev, devicetree, linux-kernel, linux-wireless,
linux-arm-msm, linux-arm-kernel, linux-pci, linux-pm,
Bartosz Golaszewski
In-Reply-To: <6b63d5d2-5f30-4fbd-a872-91f32dc32c87@gmail.com>
On Sat, Apr 6, 2024 at 5:03 AM Xilin Wu <wuxilin123@gmail.com> wrote:
>
> I tested the patchset on SM8550 and it does give me working WiFi. However I
> seethe following warnings during boot.
>
> [ 5.973011] mhi mhi0: Requested to power ON
> [ 6.597591] mhi mhi0: Power on setup success
> [ 6.597631] sysfs: cannot create duplicate filename '/devices/platform/soc@0/1c00000.pcie/pci0000:00/0000:00:00.0/resource0'
> [ 6.597634] CPU: 7 PID: 154 Comm: kworker/u32:5 Tainted: G S 6.9.0-rc1-next-20240328-g955237c9980c #1
> [ 6.597635] Hardware name: AYN Odin 2 (DT)
> [ 6.597637] Workqueue: async async_run_entry_fn
> [ 6.597645] Call trace:
> [ 6.597646] dump_backtrace+0xa0/0x128
> [ 6.597649] show_stack+0x20/0x38
> [ 6.597650] dump_stack_lvl+0x74/0x90
> [ 6.597653] dump_stack+0x18/0x28
> [ 6.597654] sysfs_warn_dup+0x6c/0x90
> [ 6.597658] sysfs_add_bin_file_mode_ns+0xdc/0x100
> [ 6.597660] sysfs_create_bin_file+0x7c/0xb8
> [ 6.597662] pci_create_attr+0xb4/0x1a8
> [ 6.597665] pci_create_resource_files+0x64/0xd0
> [ 6.597667] pci_create_sysfs_dev_files+0x24/0x40
> [ 6.597669] pci_bus_add_device+0x54/0x138
> [ 6.597670] pci_bus_add_devices+0x40/0x98
> [ 6.597672] pci_host_probe+0x70/0xf0
> [ 6.597673] dw_pcie_host_init+0x248/0x658
> [ 6.597676] qcom_pcie_probe+0x234/0x330
> [ 6.597677] platform_probe+0x70/0xd8
> [ 6.597680] really_probe+0xc8/0x3a0
> [ 6.597681] __driver_probe_device+0x84/0x170
> [ 6.597682] driver_probe_device+0x44/0x120
> [ 6.597683] __device_attach_driver+0xc4/0x168
> [ 6.597684] bus_for_each_drv+0x8c/0xf0
> [ 6.597686] __device_attach_async_helper+0xb4/0x118
> [ 6.597687] async_run_entry_fn+0x40/0x178
> [ 6.597689] process_one_work+0x16c/0x410
> [ 6.597691] worker_thread+0x284/0x3a0
> [ 6.597693] kthread+0x118/0x128
> [ 6.597693] ret_from_fork+0x10/0x20
> [ 6.597698] ------------[ cut here ]------------
> [ 6.597698] proc_dir_entry '0000:00/00.0' already registered
> [ 6.597710] WARNING: CPU: 7 PID: 154 at fs/proc/generic.c:375 proc_register+0x138/0x1d0
> [ 6.597713] Modules linked in:
> [ 6.597714] CPU: 7 PID: 154 Comm: kworker/u32:5 Tainted: G S 6.9.0-rc1-next-20240328-g955237c9980c #1
> [ 6.597715] Hardware name: AYN Odin 2 (DT)
> [ 6.597716] Workqueue: async async_run_entry_fn
> [ 6.597718] pstate: 61400005 (nZCv daif +PAN -UAO -TCO +DIT -SSBS BTYPE=--)
> [ 6.597719] pc : proc_register+0x138/0x1d0
> [ 6.597721] lr : proc_register+0x138/0x1d0
> [ 6.597723] sp : ffff800081e3b9a0
> [ 6.597723] x29: ffff800081e3b9a0 x28: 0000000000000000 x27: ffffddb2a28eabe0
> [ 6.597725] x26: ffff3425c9ada5c0 x25: ffffddb2a2d4eef0 x24: ffff3425c9ada540
> [ 6.597726] x23: 0000000000000004 x22: ffff3425c7b1822c x21: 0000000000000004
> [ 6.597727] x20: ffff3425c7b18180 x19: ffff3425c9adaec8 x18: ffffffffffffffff
> [ 6.597729] x17: 3040636f732f6d72 x16: 6f6674616c702f73 x15: ffff800081e3b910
> [ 6.597730] x14: 0000000000000000 x13: 0a64657265747369 x12: 6765722079646165
> [ 6.597731] x11: fffffffffff00000 x10: ffffddb2a27c4fb0 x9 : ffffddb29f5d7528
> [ 6.597733] x8 : 00000000ffff7fff x7 : ffffddb2a27c4fb0 x6 : 80000000ffff8000
> [ 6.597734] x5 : 0000000000000358 x4 : 0000000000000000 x3 : 00000000ffffffff
> [ 6.597736] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff3425c5ce0000
> [ 6.597737] Call trace:
> [ 6.597737] proc_register+0x138/0x1d0
> [ 6.597739] proc_create_data+0x48/0x78
> [ 6.597741] pci_proc_attach_device+0x84/0x118
> [ 6.597743] pci_bus_add_device+0x5c/0x138
> [ 6.597744] pci_bus_add_devices+0x40/0x98
> [ 6.597745] pci_host_probe+0x70/0xf0
> [ 6.597746] dw_pcie_host_init+0x248/0x658
> [ 6.597748] qcom_pcie_probe+0x234/0x330
> [ 6.597749] platform_probe+0x70/0xd8
> [ 6.597750] really_probe+0xc8/0x3a0
> [ 6.597751] __driver_probe_device+0x84/0x170
> [ 6.597752] driver_probe_device+0x44/0x120
> [ 6.597753] __device_attach_driver+0xc4/0x168
> [ 6.597754] bus_for_each_drv+0x8c/0xf0
> [ 6.597756] __device_attach_async_helper+0xb4/0x118
> [ 6.597757] async_run_entry_fn+0x40/0x178
> [ 6.597759] process_one_work+0x16c/0x410
> [ 6.597760] worker_thread+0x284/0x3a0
> [ 6.597761] kthread+0x118/0x128
> [ 6.597762] ret_from_fork+0x10/0x20
> [ 6.597763] ---[ end trace 0000000000000000 ]---
>
> This probably only occurs when the relevant drivers on compiled as built-in.
> Similar behavior has been noticed before as well:
>
> https://lore.kernel.org/lkml/20240201155532.49707-1-brgl@bgdev.pl/T/#mdeeca9bc8e19458787d53738298abcfff443068a
>
> Thanks,
> Xilin
>
Thanks for the report. The reason for this was populating the platform
devices before the bridge device was fully added. In case of loadable
modules this meant the pwrctl probe would be deferred long enough for
that to complete so I didn't see it but with pwrctl built-in this
would trigger the problem. I fixed it locally and will resend with
that addressed.
Bart
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^ permalink raw reply
* [PATCH] cpufreq: Convert to exit callback returning void
From: Lizhe @ 2024-04-09 15:28 UTC (permalink / raw)
To: rafael, viresh.kumar, marcan, sven, alyssa, mmayer,
bcm-kernel-feedback-list
Cc: linux-pm, linux-kernel, asahi, linux-arm-kernel, Lizhe
For the exit() callback function returning an int type value,
this leads many driver authors mistakenly believing that error
handling can be performed by returning an error code. However,
the returned value is ignored, and to improve this situation.
it is proposed to modify the return type of the exit() callback
function to void.
Signed-off-by: Lizhe <sensor1010@163.com>
---
drivers/cpufreq/acpi-cpufreq.c | 4 +---
drivers/cpufreq/apple-soc-cpufreq.c | 4 +---
drivers/cpufreq/bmips-cpufreq.c | 4 +---
drivers/cpufreq/cppc_cpufreq.c | 3 +--
drivers/cpufreq/cpufreq-dt.c | 3 +--
drivers/cpufreq/cpufreq-nforce2.c | 6 ------
drivers/cpufreq/e_powersaver.c | 3 +--
include/linux/cpufreq.h | 2 +-
8 files changed, 7 insertions(+), 22 deletions(-)
diff --git a/drivers/cpufreq/acpi-cpufreq.c b/drivers/cpufreq/acpi-cpufreq.c
index 37f1cdf46d29..33f18140e9a4 100644
--- a/drivers/cpufreq/acpi-cpufreq.c
+++ b/drivers/cpufreq/acpi-cpufreq.c
@@ -906,7 +906,7 @@ static int acpi_cpufreq_cpu_init(struct cpufreq_policy *policy)
return result;
}
-static int acpi_cpufreq_cpu_exit(struct cpufreq_policy *policy)
+static void acpi_cpufreq_cpu_exit(struct cpufreq_policy *policy)
{
struct acpi_cpufreq_data *data = policy->driver_data;
@@ -919,8 +919,6 @@ static int acpi_cpufreq_cpu_exit(struct cpufreq_policy *policy)
free_cpumask_var(data->freqdomain_cpus);
kfree(policy->freq_table);
kfree(data);
-
- return 0;
}
static int acpi_cpufreq_resume(struct cpufreq_policy *policy)
diff --git a/drivers/cpufreq/apple-soc-cpufreq.c b/drivers/cpufreq/apple-soc-cpufreq.c
index 021f423705e1..af34c22fa273 100644
--- a/drivers/cpufreq/apple-soc-cpufreq.c
+++ b/drivers/cpufreq/apple-soc-cpufreq.c
@@ -305,7 +305,7 @@ static int apple_soc_cpufreq_init(struct cpufreq_policy *policy)
return ret;
}
-static int apple_soc_cpufreq_exit(struct cpufreq_policy *policy)
+static void apple_soc_cpufreq_exit(struct cpufreq_policy *policy)
{
struct apple_cpu_priv *priv = policy->driver_data;
@@ -313,8 +313,6 @@ static int apple_soc_cpufreq_exit(struct cpufreq_policy *policy)
dev_pm_opp_remove_all_dynamic(priv->cpu_dev);
iounmap(priv->reg_base);
kfree(priv);
-
- return 0;
}
static struct cpufreq_driver apple_soc_cpufreq_driver = {
diff --git a/drivers/cpufreq/bmips-cpufreq.c b/drivers/cpufreq/bmips-cpufreq.c
index 39221a9a187a..17a4c174553d 100644
--- a/drivers/cpufreq/bmips-cpufreq.c
+++ b/drivers/cpufreq/bmips-cpufreq.c
@@ -121,11 +121,9 @@ static int bmips_cpufreq_target_index(struct cpufreq_policy *policy,
return 0;
}
-static int bmips_cpufreq_exit(struct cpufreq_policy *policy)
+static void bmips_cpufreq_exit(struct cpufreq_policy *policy)
{
kfree(policy->freq_table);
-
- return 0;
}
static int bmips_cpufreq_init(struct cpufreq_policy *policy)
diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c
index 64420d9cfd1e..dccb9c1f087d 100644
--- a/drivers/cpufreq/cppc_cpufreq.c
+++ b/drivers/cpufreq/cppc_cpufreq.c
@@ -688,7 +688,7 @@ static int cppc_cpufreq_cpu_init(struct cpufreq_policy *policy)
return ret;
}
-static int cppc_cpufreq_cpu_exit(struct cpufreq_policy *policy)
+static void cppc_cpufreq_cpu_exit(struct cpufreq_policy *policy)
{
struct cppc_cpudata *cpu_data = policy->driver_data;
struct cppc_perf_caps *caps = &cpu_data->perf_caps;
@@ -705,7 +705,6 @@ static int cppc_cpufreq_cpu_exit(struct cpufreq_policy *policy)
caps->lowest_perf, cpu, ret);
cppc_cpufreq_put_cpu_data(policy);
- return 0;
}
static inline u64 get_delta(u64 t1, u64 t0)
diff --git a/drivers/cpufreq/cpufreq-dt.c b/drivers/cpufreq/cpufreq-dt.c
index 2d83bbc65dd0..eaf02579ea74 100644
--- a/drivers/cpufreq/cpufreq-dt.c
+++ b/drivers/cpufreq/cpufreq-dt.c
@@ -166,10 +166,9 @@ static int cpufreq_offline(struct cpufreq_policy *policy)
return 0;
}
-static int cpufreq_exit(struct cpufreq_policy *policy)
+static void cpufreq_exit(struct cpufreq_policy *policy)
{
clk_put(policy->clk);
- return 0;
}
static struct cpufreq_driver dt_cpufreq_driver = {
diff --git a/drivers/cpufreq/cpufreq-nforce2.c b/drivers/cpufreq/cpufreq-nforce2.c
index f7a7bcf6f52e..fedad1081973 100644
--- a/drivers/cpufreq/cpufreq-nforce2.c
+++ b/drivers/cpufreq/cpufreq-nforce2.c
@@ -359,11 +359,6 @@ static int nforce2_cpu_init(struct cpufreq_policy *policy)
return 0;
}
-static int nforce2_cpu_exit(struct cpufreq_policy *policy)
-{
- return 0;
-}
-
static struct cpufreq_driver nforce2_driver = {
.name = "nforce2",
.flags = CPUFREQ_NO_AUTO_DYNAMIC_SWITCHING,
@@ -371,7 +366,6 @@ static struct cpufreq_driver nforce2_driver = {
.target = nforce2_target,
.get = nforce2_get,
.init = nforce2_cpu_init,
- .exit = nforce2_cpu_exit,
};
#ifdef MODULE
diff --git a/drivers/cpufreq/e_powersaver.c b/drivers/cpufreq/e_powersaver.c
index ab93bce8ae77..6e958b09e1b5 100644
--- a/drivers/cpufreq/e_powersaver.c
+++ b/drivers/cpufreq/e_powersaver.c
@@ -360,14 +360,13 @@ static int eps_cpu_init(struct cpufreq_policy *policy)
return 0;
}
-static int eps_cpu_exit(struct cpufreq_policy *policy)
+static void eps_cpu_exit(struct cpufreq_policy *policy)
{
unsigned int cpu = policy->cpu;
/* Bye */
kfree(eps_cpu[cpu]);
eps_cpu[cpu] = NULL;
- return 0;
}
static struct cpufreq_driver eps_driver = {
diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h
index 9956afb9acc2..ffb8d85d73ee 100644
--- a/include/linux/cpufreq.h
+++ b/include/linux/cpufreq.h
@@ -386,7 +386,7 @@ struct cpufreq_driver {
int (*online)(struct cpufreq_policy *policy);
int (*offline)(struct cpufreq_policy *policy);
- int (*exit)(struct cpufreq_policy *policy);
+ void (*exit)(struct cpufreq_policy *policy);
int (*suspend)(struct cpufreq_policy *policy);
int (*resume)(struct cpufreq_policy *policy);
--
2.25.1
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^ permalink raw reply related
* Re: [PATCH net-next v1 00/12] First try to replace page_frag with page_frag_cache
From: Alexander Duyck @ 2024-04-09 15:29 UTC (permalink / raw)
To: Yunsheng Lin
Cc: davem, kuba, pabeni, netdev, linux-kernel, Matthias Brugger,
AngeloGioacchino Del Regno, Alexei Starovoitov, Daniel Borkmann,
Jesper Dangaard Brouer, John Fastabend, linux-arm-kernel,
linux-mediatek, bpf
In-Reply-To: <e3e3ad18-8ed0-4bd3-8126-2f60e8d3ae28@huawei.com>
On Tue, Apr 9, 2024 at 12:59 AM Yunsheng Lin <linyunsheng@huawei.com> wrote:
>
> On 2024/4/8 23:09, Alexander Duyck wrote:
> > On Mon, Apr 8, 2024 at 6:38 AM Yunsheng Lin <linyunsheng@huawei.com> wrote:
> >>
> >> On 2024/4/8 1:02, Alexander Duyck wrote:
> >>> On Sun, Apr 7, 2024 at 6:10 AM Yunsheng Lin <linyunsheng@huawei.com> wrote:
> >>>>
> >>>> After [1], Only there are two implementations for page frag:
> >>>>
> >>>> 1. mm/page_alloc.c: net stack seems to be using it in the
> >>>> rx part with 'struct page_frag_cache' and the main API
> >>>> being page_frag_alloc_align().
> >>>> 2. net/core/sock.c: net stack seems to be using it in the
> >>>> tx part with 'struct page_frag' and the main API being
> >>>> skb_page_frag_refill().
> >>>>
> >>>> This patchset tries to unfiy the page frag implementation
> >>>> by replacing page_frag with page_frag_cache for sk_page_frag()
> >>>> first. net_high_order_alloc_disable_key for the implementation
> >>>> in net/core/sock.c doesn't seems matter that much now have
> >>>> have pcp support for high-order pages in commit 44042b449872
> >>>> ("mm/page_alloc: allow high-order pages to be stored on the
> >>>> per-cpu lists").
> >>>>
> >>>> As the related change is mostly related to networking, so
> >>>> targeting the net-next. And will try to replace the rest
> >>>> of page_frag in the follow patchset.
> >>>>
> >>>> After this patchset, we are not only able to unify the page
> >>>> frag implementation a little, but seems able to have about
> >>>> 0.5+% performance boost testing by using the vhost_net_test
> >>>> introduced in [1] and page_frag_test.ko introduced in this
> >>>> patch.
> >>>
> >>> One question that jumps out at me for this is "why?". No offense but
> >>> this is a pretty massive set of changes with over 1400 additions and
> >>> 500+ deletions and I can't help but ask why, and this cover page
> >>> doesn't give me any good reason to think about accepting this set.
> >>
> >> There are 375 + 256 additions for testing module and the documentation
> >> update in the last two patches, and there is 198 additions and 176
> >> deletions for moving the page fragment allocator from page_alloc into
> >> its own file in patch 1.
> >> Without above number, there are above 600+ additions and 300+ deletions,
> >> deos that seems reasonable considering 140+ additions are needed to for
> >> the new API, 300+ additions and deletions for updating the users to use
> >> the new API as there are many users using the old API?
> >
> > Maybe it would make more sense to break this into 2 sets. The first
> > one adding your testing, and the second one consolidating the API.
> > With that we would have a clearly defined test infrastructure in place
> > for the second set which is making significant changes to the API. In
> > addition it would provide the opportunity for others to point out any
> > other test that they might want pulled in since this is likely to have
> > impact outside of just the tests you have proposed.
>
> Do you have someone might want pulled in some test in mind, if yes, then
> it might make sense to work together to minimise some possible duplicated
> work. If no, it does not make much sense to break this into 2 sets just to
> introduce a testing in the first set.
>
> If it helps you or someone to do the comparing test before and after patchset
> easier, I would reorder the patch adding the micro-benchmark ko to the first
> patch.
Well the socket code will be largely impacted by any changes to this.
Seems like it might make sense to think about coming up with a socket
based test for example that might make good use of the allocator
located there so we can test the consolidating of the page frag code
out of there.
> >
> >>> What is meant to be the benefit to the community for adding this? All
> >>> I am seeing is a ton of extra code to have to review as this
> >>> unification is adding an additional 1000+ lines without a good
> >>> explanation as to why they are needed.
> >>
> >> Some benefits I see for now:
> >> 1. Improve the maintainability of page frag's implementation:
> >> (1) future bugfix and performance can be done in one place.
> >> For example, we may able to save some space for the
> >> 'page_frag_cache' API user, and avoid 'get_page()' for
> >> the old 'page_frag' API user.
> >
> > The problem as I see it is it is consolidating all the consumers down
> > to the least common denominator in terms of performance. You have
> > already demonstrated that with patch 2 which enforces that all drivers
> > have to work from the bottom up instead of being able to work top down
> > in the page.
>
> I am agreed that consolidating 'the least common denominator' is what we
> do when we design a subsystem/libary and sometimes we may need to have a
> trade off between maintainability and perfromance.
>
> But your argument 'having to load two registers with the values and then
> compare them which saves us a few cycles' in [1] does not seems to justify
> that we need to have it's own implementation of page_frag, not to mention
> the 'work top down' way has its own disadvantages as mentioned in patch 2.
>
> Also, in patch 5 & 6, we need to load 'size' to a register anyway so that we
> can remove 'pagecnt_bias' and 'pfmemalloc' from 'struct page_frag_cache', it
> would be better you can work through the whole patchset to get a bigger picture.
>
> 1. https://lore.kernel.org/all/f4abe71b3439b39d17a6fb2d410180f367cadf5c.camel@gmail.com/
I haven't had a chance to review the entire patch set yet. I am hoping
to get to it tomorrow. That said, my main concern is that this becomes
a slippery slope. Where one thing leads to another and eventually this
becomes some overgrown setup that is no longer performant and has
people migrating back to the slab cache.
> >
> > This eventually leads you down the path where every time somebody has
> > a use case for it that may not be optimal for others it is going to be
> > a fight to see if the new use case can degrade the performance of the
> > other use cases.
>
> I think it is always better to have a disscusion[or 'fight'] about how to
> support a new use case:
> 1. refoctor the existing implementation to support the new use case, and
> introduce a new API for it if have to.
> 2. if the above does not work, and the use case is important enough that
> we might create/design a subsystem/libary for it.
>
> But from updating page_frag API, I do not see that we need the second
> option yet.
That is why we are having this discussion right now though. It seems
like you have your own use case that you want to use this for. So as a
result you are refactoring all the existing implementations and
crafting them to support your use case while trying to avoid
introducing regressions in the others. I would argue that based on
this set you are already trying to take the existing code and create a
"new" subsystem/library from it that is based on the original code
with only a few tweaks.
> >
> >> (2) Provide a proper API so that caller does not need to access
> >> internal data field. Exposing the internal data field may
> >> enable the caller to do some unexpcted implementation of
> >> its own like below, after this patchset the API user is not
> >> supposed to do access the data field of 'page_frag_cache'
> >> directly[Currently it is still acessable from API caller if
> >> the caller is not following the rule, I am not sure how to
> >> limit the access without any performance impact yet].
> >> https://elixir.bootlin.com/linux/v6.9-rc3/source/drivers/net/ethernet/chelsio/inline_crypto/chtls/chtls_io.c#L1141
> >
> > This just makes the issue I point out in 1 even worse. The problem is
> > this code has to be used at the very lowest of levels and is as
> > tightly optimized as it is since it is called at least once per packet
> > in the case of networking. Networking that is still getting faster
> > mind you and demanding even fewer cycles per packet to try and keep
> > up. I just see this change as taking us in the wrong direction.
>
> Yes, I am agreed with your point about 'demanding even fewer cycles per
> packet', but not so with 'tightly optimized'.
>
> 'tightly optimized' may mean everybody inventing their own wheels.
I hate to break this to you but that is the nature of things. If you
want to perform with decent performance you can only be so abstracted
away from the underlying implementation. The more generic you go the
less performance you will get.
> >
> >> 2. page_frag API may provide a central point for netwroking to allocate
> >> memory instead of calling page allocator directly in the future, so
> >> that we can decouple 'struct page' from networking.
> >
> > I hope not. The fact is the page allocator serves a very specific
> > purpose, and the page frag API was meant to serve a different one and
> > not be a replacement for it. One thing that has really irked me is the
> > fact that I have seen it abused as much as it has been where people
> > seem to think it is just a page allocator when it was really meant to
> > just provide a way to shard order 0 pages into sizes that are half a
> > page or less in size. I really meant for it to be a quick-n-dirty slab
> > allocator for sizes 2K or less where ideally we are working with
> > powers of 2.
> >
> > It concerns me that you are talking about taking this down a path that
> > will likely lead to further misuse of the code as a backdoor way to
> > allocate order 0 pages using this instead of just using the page
> > allocator.
>
> Let's not get to a conclusion here and wait to see how thing evolve
> in the future.
I still have an open mind, but this is a warning on where I will not
let this go. This is *NOT* an alternative to the page allocator. If we
need order 0 pages we should be allocating order 0 pages. Ideally this
is just for cases where we need memory in sizes 2K or less.
> >
> >>>
> >>> Also I wouldn't bother mentioning the 0.5+% performance gain as a
> >>> "bonus". Changes of that amount usually mean it is within the margin
> >>> of error. At best it likely means you haven't introduced a noticeable
> >>> regression.
> >>
> >> For micro-benchmark ko added in this patchset, performance gain seems quit
> >> stable from testing in system without any other load.
> >
> > Again, that doesn't mean anything. It could just be that the code
> > shifted somewhere due to all the code moved so a loop got more aligned
> > than it was before. To give you an idea I have seen performance gains
> > in the past from turning off Rx checksum for some workloads and that
> > was simply due to the fact that the CPUs were staying awake longer
> > instead of going into deep sleep states as such we could handle more
> > packets per second even though we were using more cycles. Without
> > significantly more context it is hard to say that the gain is anything
> > real at all and a 0.5% gain is well within that margin of error.
>
> As vhost_net_test added in [2] is heavily invovled with tun and virtio
> handling, the 0.5% gain does seems within that margin of error, there is
> why I added a micro-benchmark specificly for page_frag in this patchset.
>
> It is tested five times, three times with this patchset and two times without
> this patchset, the complete log is as below, even there is some noise, all
> the result with this patchset is better than the result without this patchset:
The problem is the vhost_net_test is you optimizing the page fragment
allocator for *YOUR* use case. I get that you want to show overall
improvement but that doesn't. You need to provide it with context for
the current users of the page fragment allocator in the form of
something other than one synthetic benchmark.
I could do the same thing by by tweaking the stack and making it drop
all network packets. The NICs would show a huge performance gain. It
doesn't mean it is usable by anybody. A benchmark is worthless without
the context about how it will impact other users.
Think about testing with real use cases for the areas that are already
making use of the page frags rather than your new synthetic benchmark
and the vhost case which you are optimizing for. Arguably this is why
so many implementations go their own way. It is difficult to optimize
for one use case without penalizing another and so the community needs
to be wiling to make that trade-off.
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* Re: [PATCH net-next v2 4/5] net: stmmac: add support for RZ/N1 GMAC
From: Geert Uytterhoeven @ 2024-04-09 15:27 UTC (permalink / raw)
To: Romain Gantois
Cc: David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Geert Uytterhoeven, Magnus Damm, Alexandre Torgue, Jose Abreu,
Maxime Coquelin, Russell King, Clément Léger,
Thomas Petazzoni, netdev, devicetree, linux-kernel,
linux-renesas-soc, linux-stm32, linux-arm-kernel
In-Reply-To: <20240409-rzn1-gmac1-v2-4-79ca45f2fc79@bootlin.com>
Hi Romain,
On Tue, Apr 9, 2024 at 11:21 AM Romain Gantois
<romain.gantois@bootlin.com> wrote:
> From: Clément Léger <clement.leger@bootlin.com>
>
> Add support for the Renesas RZ/N1 GMAC. This support can make use of a
> custom RZ/N1 PCS which is fetched by parsing the pcs-handle device tree
> property.
>
> Signed-off-by: "Clément Léger" <clement.leger@bootlin.com>
> Co-developed-by: Romain Gantois <romain.gantois@bootlin.com>
> Signed-off-by: Romain Gantois <romain.gantois@bootlin.com>
Thanks for your patch!
> --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig
> +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig
> @@ -142,6 +142,18 @@ config DWMAC_ROCKCHIP
> This selects the Rockchip RK3288 SoC glue layer support for
> the stmmac device driver.
>
> +config DWMAC_RZN1
> + tristate "Renesas RZ/N1 dwmac support"
> + default ARCH_RZN1
Why default to enabled?
> + depends on OF && (ARCH_RZN1 || COMPILE_TEST)
> + select PCS_RZN1_MIIC
> + help
> + Support for Ethernet controller on Renesas RZ/N1 SoC family.
> +
> + This selects the Renesas RZ/N1 SoC glue layer support for
> + the stmmac device driver. This support can make use of a custom MII
> + converter PCS device.
> +
> config DWMAC_SOCFPGA
> tristate "SOCFPGA dwmac support"
> default ARCH_INTEL_SOCFPGA
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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* Re: [PATCH v8 3/8] perf: imx_perf: let the driver manage the counter usage rather the user
From: Will Deacon @ 2024-04-09 15:26 UTC (permalink / raw)
To: Xu Yang
Cc: frank.li, mark.rutland, robh+dt, krzysztof.kozlowski+dt, conor+dt,
shawnguo, s.hauer, kernel, festevam, john.g.garry, jolsa,
namhyung, irogers, mike.leach, peterz, mingo, acme,
alexander.shishkin, adrian.hunter, linux-arm-kernel, devicetree,
linux-kernel, linux-perf-users, imx
In-Reply-To: <20240322063930.749126-3-xu.yang_2@nxp.com>
On Fri, Mar 22, 2024 at 02:39:25PM +0800, Xu Yang wrote:
> In current design, the user of perf app needs to input counter ID to count
> events. However, this is not user-friendly since the user needs to lookup
> the map table to find the counter. Instead of letting the user to input
> the counter, let this driver to manage the counters in this patch.
I think we still have to support the old interface so that we don't break
those existing users (even if the driver just ignores whatever counter ID
is provided in a backwards-compatible way).
> This will be implemented by:
> 1. allocate counter 0 for cycle event.
> 2. find unused counter from 1-10 for reference events.
> 3. allocate specific counter for counter-specific events.
>
> In this patch, counter attribute is removed too. To mark counter-specific
> events, counter ID will be encoded into perf_pmu_events_attr.id.
>
> Reviewed-by: Frank Li <Frank.Li@nxp.com>
> Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
>
> ---
> Changes in v6:
> - new patch
> Changes in v7:
> - no changes
> Changes in v8:
> - add Rb tag
> ---
> drivers/perf/fsl_imx9_ddr_perf.c | 168 ++++++++++++++++++-------------
> 1 file changed, 99 insertions(+), 69 deletions(-)
>
> diff --git a/drivers/perf/fsl_imx9_ddr_perf.c b/drivers/perf/fsl_imx9_ddr_perf.c
> index 0017f2c9ef91..b728719b494c 100644
> --- a/drivers/perf/fsl_imx9_ddr_perf.c
> +++ b/drivers/perf/fsl_imx9_ddr_perf.c
> @@ -245,14 +249,12 @@ static const struct attribute_group ddr_perf_events_attr_group = {
> .attrs = ddr_perf_events_attrs,
> };
>
> -PMU_FORMAT_ATTR(event, "config:0-7");
> -PMU_FORMAT_ATTR(counter, "config:8-15");
> +PMU_FORMAT_ATTR(event, "config:0-15");
Sadly, this is a user-visible change so I think it will break old tools,
won't it?
Will
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* Re: [PATCH 1/2] dt-bindings: usb: mtk-xhci: add compatible for MT7988
From: Rob Herring @ 2024-04-09 15:26 UTC (permalink / raw)
To: Rafał Miłecki
Cc: Matthias Brugger, AngeloGioacchino Del Regno, Krzysztof Kozlowski,
Conor Dooley, Chunfeng Yun, Greg Kroah-Hartman, Daniel Golle,
linux-usb, linux-arm-kernel, linux-mediatek, devicetree,
linux-kernel, Rafał Miłecki
In-Reply-To: <20240213130044.1976-1-zajec5@gmail.com>
On Tue, Feb 13, 2024 at 02:00:43PM +0100, Rafał Miłecki wrote:
> From: Rafał Miłecki <rafal@milecki.pl>
>
> MT7988 SoC contains two on-SoC XHCI controllers. Add proper binding.
>
> Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
> ---
> Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml | 1 +
> 1 file changed, 1 insertion(+)
Seems like this got missed. Applied now.
Rob
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* Re: [PATCH v3 00/13] drm/display: Convert helpers Kconfig symbols to depends on
From: Geert Uytterhoeven @ 2024-04-09 15:24 UTC (permalink / raw)
To: Jani Nikula
Cc: Maxime Ripard, Maarten Lankhorst, Thomas Zimmermann, David Airlie,
Daniel Vetter, dri-devel, Lucas De Marchi, kernel test robot,
linux-renesas-soc, linux-arm-kernel, linux-kbuild
In-Reply-To: <87edbe94ck.fsf@intel.com>
Hi Jani,
On Tue, Apr 9, 2024 at 1:13 PM Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Tue, 09 Apr 2024, Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Tue, Apr 9, 2024 at 12:04 PM Jani Nikula <jani.nikula@linux.intel.com> wrote:
> >> On Tue, 09 Apr 2024, Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> >> > The user should not need to know which helpers are needed for the driver
> >> > he is interested in. When a symbol selects another symbol, it should
> >> > just make sure the dependencies of the target symbol are met.
> >>
> >> It's really not "just make sure". This leads to perpetual illegal
> >> configurations, and duct tape fixes. Select should not be used for
> >> visible symbols or symbols with dependencies [1].
> >
> > In other words: none of these helpers should be visible...
>
> ...and should have no dependencies? :p
Unless they do have dependencies.
> >> What we'd need for usability is not more abuse of select, but rather 1)
> >> warnings for selecting symbols with dependencies, and 2) a way to enable
> >
> > Kconfig already warns if dependencies of selected symbols are not met.
>
> But it does lead to cases where a builtin tries to use a symbol from a
> module, failing at link time, not config time. Then I regularly see
> patches trying to fix this with IS_REACHABLE(), making it a silent
> runtime failure instead, when it should've been a config issue.
If a symbol for a builtin selects a symbol for a module, the latter
becomes builtin, too, so that does not cause such issues?
You can get such issues when a boolean symbol depends on a tristate
symbol...
> >> a kconfig option with all its dependencies, recursively. This is what we
> >> lack.
> >
> > You cannot force-enable all dependencies of the target symbol, as some
> > of these dependencies may be impossible to meet on the system you are
> > configuring a kernel for.
>
> Surely kconfig should be able to figure out if they're possible or not.
>
> > The current proper way is to add these dependencies to the source
> > symbol, which is what we have been doing everywhere else. Another
> > solution may be to teach Kconfig to ignore any symbols that select a
> > symbol with unmet dependencies.
>
> ...
>
> It seems like your main argument in favour of using select is that it's
> more convenient for people who configure the kernel. Because the user
> should be able to just enable a driver, and that would select everything
> that's needed. But where do we draw the line? Then what qualifies for
> "depends on"?
Hard (platform and subsystem) dependencies.
> Look at config DRM_I915 and where select abuse has lead us. Like, why
> don't we just select DRM, PCI and X86 as well instead of depend. :p
X86 and PCI are hard platform dependencies.
DRM is a subsystem dependency.
> A lot of things we have to select because it appears to generally be the
> case that if some places select and some places depends on a symbol,
> it'll lead to circular dependencies.
True. So all library code (incl. helpers) should be selected, and
not be used as a dependency.
The user shouldn't be aware that the driver uses library code (or not).
> Sure there may be a usability issue with using depends on. But the
> proper fix isn't hacking in kconfig files, it's to fix the usability in
> kconfig the tool UI. But nobody steps up, because at least I find the
> kconfig source to be inpenetrable. I've tried many times, and given up.
As long as Kconfig does not handle dependencies of selected symbols
automatically, adding explicit dependencies to the origin symbols is
the only workable solution.
> I mean, if you want to enable a driver D, it could, at a minimum, show
> you a tree of (possibly alternative) things you also need to enable. But
And this series is actually making that harder, by turning all these
selects of helpers into dependencies...
> if the dependencies aren't there, you won't even see the config for
> D. That's not something that should be "fixed" by abusing select in
> kconfig files.
I consider not seeing symbols when a hard dependency is not met as
a good thing. If everything was visible all the time, you would
have a very hard (well, harder than the current already-hard ;-)
time configuring your kernel.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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* Re: [PATCH v2 1/3] dt-bindings: display: mediatek: Add OF graph support for board path
From: Dmitry Baryshkov @ 2024-04-09 15:20 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: chunkuang.hu, robh, krzysztof.kozlowski+dt, conor+dt, p.zabel,
airlied, daniel, maarten.lankhorst, mripard, tzimmermann,
matthias.bgg, shawn.sung, yu-chang.lee, ck.hu, jitao.shi,
devicetree, linux-kernel, dri-devel, linux-mediatek,
linux-arm-kernel, wenst, kernel
In-Reply-To: <20240409120211.321153-2-angelogioacchino.delregno@collabora.com>
On Tue, Apr 09, 2024 at 02:02:09PM +0200, AngeloGioacchino Del Regno wrote:
> The display IPs in MediaTek SoCs support being interconnected with
> different instances of DDP IPs (for example, merge0 or merge1) and/or
> with different DDP IPs (for example, rdma can be connected with either
> color, dpi, dsi, merge, etc), forming a full Display Data Path that
> ends with an actual display.
>
> The final display pipeline is effectively board specific, as it does
> depend on the display that is attached to it, and eventually on the
> sensors supported by the board (for example, Adaptive Ambient Light
> would need an Ambient Light Sensor, otherwise it's pointless!), other
> than the output type.
With the color and gamma being in play, should the configuration be
board-driver or rather use-case driven with the driver being able to
reroute some of the blocks at runtime?
>
> Add support for OF graphs to most of the MediaTek DDP (display) bindings
> to add flexibility to build custom hardware paths, hence enabling board
> specific configuration of the display pipeline and allowing to finally
> migrate away from using hardcoded paths.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
--
With best wishes
Dmitry
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