* [PATCH v6 02/10] arm64: dts: lx2160a: change i2c0 (iic1) pinmux mask to one bit
From: Josua Mayer @ 2026-03-24 12:40 UTC (permalink / raw)
To: Frank Li, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Shawn Guo, Carlos Song
Cc: Mikhail Anikin, Yazan Shhady, Rabeeh Khoury, Frank Li,
linux-arm-kernel, devicetree, linux-kernel, Josua Mayer
In-Reply-To: <20260324-lx2160-sd-cd-v6-0-8bf207711848@solid-run.com>
LX2160A pinmux is done in groups by various length bitfields within
configuration registers.
The first i2c bus (called IIC1 in reference manual) is configured
through field IIC1_PMUX in register RCWSR14 bit 10 which is described in
the reference manual as a single bit, unlike the other i2c buses.
Change the bitmask for the pinmux nodes from 0x7 to 0x1 to ensure only
single bit is modified.
Further change the zero in the same line to hexadecimal format for
consistency.
This change is of cosmetic nature enforcing consistency with
documentation. There is no known issue when writing the extra two bits
marked in reference manual as reserved.
Fixes: 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c gpio to support bus recovery")
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index af74e77efabc5..d5bb55df03216 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -1794,11 +1794,11 @@ i2c7_scl_gpio: i2c7-scl-gpio-pins {
};
i2c0_scl: i2c0-scl-pins {
- pinctrl-single,bits = <0x8 0 (0x7 << 10)>;
+ pinctrl-single,bits = <0x8 0x0 (0x1 << 10)>;
};
i2c0_scl_gpio: i2c0-scl-gpio-pins {
- pinctrl-single,bits = <0x8 (0x1 << 10) (0x7 << 10)>;
+ pinctrl-single,bits = <0x8 (0x1 << 10) (0x1 << 10)>;
};
};
--
2.51.0
^ permalink raw reply related
* [PATCH v6 04/10] arm64: dts: lx2160a: rename pinmux nodes for readability
From: Josua Mayer @ 2026-03-24 12:40 UTC (permalink / raw)
To: Frank Li, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Shawn Guo, Carlos Song
Cc: Mikhail Anikin, Yazan Shhady, Rabeeh Khoury, Frank Li,
linux-arm-kernel, devicetree, linux-kernel, Josua Mayer
In-Reply-To: <20260324-lx2160-sd-cd-v6-0-8bf207711848@solid-run.com>
LX2160A pinmux is done in groups by various length bitfields within
configuration registers.
Each group of pins is named in the reference manual after a primary
function using soc-specific naming, e.g. IIC1 (for i2c0).
Hardware block numbering starts from zero in device-tree but one in the
reference manual.
Rename the already defined pinmux nodes originally added for changing
i2c pins between i2c and gpio functions reflecting the reference manual
name (IIC) in the node name, and the device-tree name (i2c, gpio) in the
label.
Specifically, drop the "_scl" suffix from the I2C labels because the
nodes actually configure both SDA and SCL pins together. Instead add
"_pins" suffix to avoid conflicts with I2C controller labels.
For GPIO functions, include the specific controller and pin numbers in
the label to clarify they are generic GPIOs and help spot mistakes.
No functional change intended.
Fixes: 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c gpio to support bus recovery")
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 64 +++++++++++++-------------
1 file changed, 32 insertions(+), 32 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index 41c9b4253f4a5..28500e8873909 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -750,8 +750,8 @@ i2c0: i2c@2000000 {
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
- pinctrl-0 = <&i2c0_scl>;
- pinctrl-1 = <&i2c0_scl_gpio>;
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-1 = <&gpio0_3_2_pins>;
scl-gpios = <&gpio0 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -766,8 +766,8 @@ i2c1: i2c@2010000 {
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
- pinctrl-0 = <&i2c1_scl>;
- pinctrl-1 = <&i2c1_scl_gpio>;
+ pinctrl-0 = <&i2c1_pins>;
+ pinctrl-1 = <&gpio0_31_30_pins>;
scl-gpios = <&gpio0 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -782,8 +782,8 @@ i2c2: i2c@2020000 {
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
- pinctrl-0 = <&i2c2_scl>;
- pinctrl-1 = <&i2c2_scl_gpio>;
+ pinctrl-0 = <&i2c2_pins>;
+ pinctrl-1 = <&gpio0_29_28_pins>;
scl-gpios = <&gpio0 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -798,8 +798,8 @@ i2c3: i2c@2030000 {
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
- pinctrl-0 = <&i2c3_scl>;
- pinctrl-1 = <&i2c3_scl_gpio>;
+ pinctrl-0 = <&i2c3_pins>;
+ pinctrl-1 = <&gpio0_27_26_pins>;
scl-gpios = <&gpio0 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -814,8 +814,8 @@ i2c4: i2c@2040000 {
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
- pinctrl-0 = <&i2c4_scl>;
- pinctrl-1 = <&i2c4_scl_gpio>;
+ pinctrl-0 = <&i2c4_pins>;
+ pinctrl-1 = <&gpio0_25_24_pins>;
scl-gpios = <&gpio0 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -830,8 +830,8 @@ i2c5: i2c@2050000 {
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
- pinctrl-0 = <&i2c5_scl>;
- pinctrl-1 = <&i2c5_scl_gpio>;
+ pinctrl-0 = <&i2c5_pins>;
+ pinctrl-1 = <&gpio0_23_22_pins>;
scl-gpios = <&gpio0 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -846,8 +846,8 @@ i2c6: i2c@2060000 {
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
- pinctrl-0 = <&i2c6_scl>;
- pinctrl-1 = <&i2c6_scl_gpio>;
+ pinctrl-0 = <&i2c6_i2c7_pins>;
+ pinctrl-1 = <&gpio1_18_15_pins>;
scl-gpios = <&gpio1 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -862,8 +862,8 @@ i2c7: i2c@2070000 {
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
QORIQ_CLK_PLL_DIV(16)>;
pinctrl-names = "default", "gpio";
- pinctrl-0 = <&i2c6_scl>;
- pinctrl-1 = <&i2c6_scl_gpio>;
+ pinctrl-0 = <&i2c6_i2c7_pins>;
+ pinctrl-1 = <&gpio1_18_15_pins>;
scl-gpios = <&gpio1 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "disabled";
};
@@ -1713,11 +1713,11 @@ pinmux_i2crv: pinmux@70010012c {
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x7>;
- i2c1_scl: i2c1-scl-pins {
+ i2c1_pins: iic2-i2c-pins {
pinctrl-single,bits = <0x0 0 0x7>;
};
- i2c1_scl_gpio: i2c1-scl-gpio-pins {
+ gpio0_31_30_pins: iic2-gpio-pins {
pinctrl-single,bits = <0x0 0x1 0x7>;
};
@@ -1725,35 +1725,35 @@ esdhc0_cd_wp_pins: iic2-sdhc-pins {
pinctrl-single,bits = <0x0 0x6 0x7>;
};
- i2c2_scl: i2c2-scl-pins {
+ i2c2_pins: iic3-i2c-pins {
pinctrl-single,bits = <0x0 0 (0x7 << 3)>;
};
- i2c2_scl_gpio: i2c2-scl-gpio-pins {
+ gpio0_29_28_pins: iic3-gpio-pins {
pinctrl-single,bits = <0x0 (0x1 << 3) (0x7 << 3)>;
};
- i2c3_scl: i2c3-scl-pins {
+ i2c3_pins: iic4-i2c-pins {
pinctrl-single,bits = <0x0 0 (0x7 << 6)>;
};
- i2c3_scl_gpio: i2c3-scl-gpio-pins {
+ gpio0_27_26_pins: iic4-gpio-pins {
pinctrl-single,bits = <0x0 (0x1 << 6) (0x7 << 6)>;
};
- i2c4_scl: i2c4-scl-pins {
+ i2c4_pins: iic5-i2c-pins {
pinctrl-single,bits = <0x0 0 (0x7 << 9)>;
};
- i2c4_scl_gpio: i2c4-scl-gpio-pins {
+ gpio0_25_24_pins: iic5-gpio-pins {
pinctrl-single,bits = <0x0 (0x1 << 9) (0x7 << 9)>;
};
- i2c5_scl: i2c5-scl-pins {
+ i2c5_pins: iic6-i2c-pins {
pinctrl-single,bits = <0x0 0 (0x7 << 12)>;
};
- i2c5_scl_gpio: i2c5-scl-gpio-pins {
+ gpio0_23_22_pins: iic6-gpio-pins {
pinctrl-single,bits = <0x0 (0x1 << 12) (0x7 << 12)>;
};
@@ -1777,19 +1777,19 @@ gpio0_14_12_pins: sdhc1-dir-gpio-pins {
pinctrl-single,bits = <0x0 (0x1 << 27) (0x7 << 27)>;
};
- i2c6_scl: i2c6-scl-pins {
- pinctrl-single,bits = <0x4 0x2 0x7>;
+ gpio1_18_15_pins: iic8-iic7-gpio-pins {
+ pinctrl-single,bits = <0x4 0x1 0x7>;
};
- i2c6_scl_gpio: i2c6-scl-gpio-pins {
- pinctrl-single,bits = <0x4 0x1 0x7>;
+ i2c6_i2c7_pins: iic8-iic7-i2c-pins {
+ pinctrl-single,bits = <0x4 0x2 0x7>;
};
- i2c0_scl: i2c0-scl-pins {
+ i2c0_pins: iic1-i2c-pins {
pinctrl-single,bits = <0x8 0x0 (0x1 << 10)>;
};
- i2c0_scl_gpio: i2c0-scl-gpio-pins {
+ gpio0_3_2_pins: iic1-gpio-pins {
pinctrl-single,bits = <0x8 (0x1 << 10) (0x1 << 10)>;
};
};
--
2.51.0
^ permalink raw reply related
* [PATCH v6 01/10] arm64: dts: lx2160a-cex7/lx2162a-sr-som: fix usd-cd & gpio pinmux
From: Josua Mayer @ 2026-03-24 12:40 UTC (permalink / raw)
To: Frank Li, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Shawn Guo, Carlos Song
Cc: Mikhail Anikin, Yazan Shhady, Rabeeh Khoury, Frank Li,
linux-arm-kernel, devicetree, linux-kernel, Josua Mayer, stable
In-Reply-To: <20260324-lx2160-sd-cd-v6-0-8bf207711848@solid-run.com>
Commit 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c gpio to
support bus recovery") introduced pinmux nodes for lx2160 i2c
interfaces, allowing runtime change between i2c and gpio functions
implementing bus recovery.
However, the dynamic configuration area (overwrite MUX) used by the
pinctrl-single driver initially reads as zero and does not reflect the
actual hardware state set by the Reset Configuration Word (RCW) at
power-on.
Because multiple groups of pins are configured from a single 32-bit
register, the first write from the pinctrl driver unintentionally clears
all other bits to zero.
For example, on the LX2162A Clearfog, RCWSR12 is initialized to
0x08000006. When any i2c pinmux is applied, it clears all other fields.
This inadvertently disables SD card-detect (IIC2_PMUX) and some GPIOs
(SDHC1_DIR_PMUX):
LX2162-CF RCWSR12: 0b0000100000000000 0000000000000110
IIC2_PMUX ||| ||| || | ||| |||XXX : I2C/GPIO/CD-WP
SDHC1_DIR_PMUX XXX ||| || | ||| ||| : SDHC/GPIO/SPI
Reverting the commit in question was considered but bus recovery is an
important feature.
Instead add pinmux nodes for those pins that were unintentionally
reconfigured on SolidRun LX2160A Clearfog-CX and LX2162A Clearfog
boards.
Fixes: 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c gpio to support bus recovery")
Cc: stable@vger.kernel.org
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
.../arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi | 7 +++++++
.../dts/freescale/fsl-lx2160a-clearfog-itx.dtsi | 2 ++
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 24 ++++++++++++++++++++++
.../boot/dts/freescale/fsl-lx2162a-clearfog.dts | 2 ++
.../boot/dts/freescale/fsl-lx2162a-sr-som.dtsi | 7 +++++++
5 files changed, 42 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
index eec2cd6c6d32a..7f6e39e27ce5c 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
@@ -162,6 +162,8 @@ rtc@51 {
};
&fspi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&fspi_data74_pins>, <&fspi_data30_pins>, <&fspi_dqs_sck_cs10_pins>;
status = "okay";
flash@0 {
@@ -177,6 +179,11 @@ flash@0 {
};
};
+&pinmux_i2crv {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio0_14_12_pins>;
+};
+
&usb0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
index af6258b2fe826..580ee9b3026e3 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
@@ -89,6 +89,8 @@ &emdio2 {
};
&esdhc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&esdhc0_cd_wp_pins>, <&esdhc0_cmd_data30_clk_vsel_pins>;
sd-uhs-sdr104;
sd-uhs-sdr50;
sd-uhs-sdr25;
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index 853b01452813a..af74e77efabc5 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -1721,6 +1721,10 @@ i2c1_scl_gpio: i2c1-scl-gpio-pins {
pinctrl-single,bits = <0x0 0x1 0x7>;
};
+ esdhc0_cd_wp_pins: iic2-sdhc-pins {
+ pinctrl-single,bits = <0x0 0x6 0x7>;
+ };
+
i2c2_scl: i2c2-scl-pins {
pinctrl-single,bits = <0x0 0 (0x7 << 3)>;
};
@@ -1753,6 +1757,26 @@ i2c5_scl_gpio: i2c5-scl-gpio-pins {
pinctrl-single,bits = <0x0 (0x1 << 12) (0x7 << 12)>;
};
+ fspi_data74_pins: xspi1-data74-pins {
+ pinctrl-single,bits = <0x0 0x0 (0x7 << 15)>;
+ };
+
+ fspi_data30_pins: xspi1-data30-pins {
+ pinctrl-single,bits = <0x0 0x0 (0x7 << 18)>;
+ };
+
+ fspi_dqs_sck_cs10_pins: xspi1-base-pins {
+ pinctrl-single,bits = <0x0 0x0 (0x7 << 21)>;
+ };
+
+ esdhc0_cmd_data30_clk_vsel_pins: sdhc1-base-sdhc-vsel-pins {
+ pinctrl-single,bits = <0x0 0x0 (0x7 << 24)>;
+ };
+
+ gpio0_14_12_pins: sdhc1-dir-gpio-pins {
+ pinctrl-single,bits = <0x0 (0x1 << 27) (0x7 << 27)>;
+ };
+
i2c6_scl: i2c6-scl-pins {
pinctrl-single,bits = <0x4 0x2 0x7>;
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
index eafef8718a0fe..8920326a06735 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
@@ -223,6 +223,8 @@ ethernet_phy8: ethernet-phy@15 {
};
&esdhc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&esdhc0_cd_wp_pins>, <&esdhc0_cmd_data30_clk_vsel_pins>;
sd-uhs-sdr104;
sd-uhs-sdr50;
sd-uhs-sdr25;
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi
index e914291e63a1a..e1344942eaaee 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi
@@ -30,6 +30,8 @@ &esdhc1 {
};
&fspi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&fspi_data74_pins>, <&fspi_data30_pins>, <&fspi_dqs_sck_cs10_pins>;
status = "okay";
flash@0 {
@@ -80,3 +82,8 @@ rtc@6f {
reg = <0x6f>;
};
};
+
+&pinmux_i2crv {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio0_14_12_pins>;
+};
--
2.51.0
^ permalink raw reply related
* [PATCH v6 00/10] arm64: dts: lx2160a: fix pinmux issues, update SolidRun boards
From: Josua Mayer @ 2026-03-24 12:40 UTC (permalink / raw)
To: Frank Li, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Shawn Guo, Carlos Song
Cc: Mikhail Anikin, Yazan Shhady, Rabeeh Khoury, Frank Li,
linux-arm-kernel, devicetree, linux-kernel, Josua Mayer, stable
Fix a bug with microsd card-detect & gpios pinmux on SolidRun
LX2160A Clearfog-CX & Honeycomb, and LX2162A Clearfog.
Then make small additions to SolidRun board descriptions.
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
Changes in v6:
- added pinmux label renaming reasons to commit description.
(Reported-by: Frank Li <Frank.li@nxp.com>)
- Link to v5: https://lore.kernel.org/r/20260314-lx2160-sd-cd-v5-0-83de721585e3@solid-run.com
Changes in v5:
- simplified lengthy commit descriptions on patches 1 and 7.
(Reported-by: Frank Li <Frank.li@nxp.com>)
- fixed i2c6 sda-gpios reference.
- Link to v4: https://lore.kernel.org/r/20260313-lx2160-sd-cd-v4-0-aabcf230fbff@solid-run.com
Changes in v4:
- separated each logical change into its own commit, improving
readability for reviewers.
- Link to v3: https://lore.kernel.org/r/20260304-lx2160-sd-cd-v3-0-dee4523600ef@solid-run.com
Changes in v3:
- added separate patch providing all pinmux nodes for RCWSR12 register
- abandoned revert strategy, implement minimal fix for solidrun boards
only.
- Link to v2: https://lore.kernel.org/r/20250714-lx2160-sd-cd-v2-1-603c6db94b60@solid-run.com
Changes in v2:
- changed to revert problematic commit, workaround is large effort
- Link to v1: https://lore.kernel.org/r/f32c5525-3162-4acd-880c-99fc46d3a63d@solid-run.com
---
Josua Mayer (10):
arm64: dts: lx2160a-cex7/lx2162a-sr-som: fix usd-cd & gpio pinmux
arm64: dts: lx2160a: change i2c0 (iic1) pinmux mask to one bit
arm64: dts: lx2160a: remove duplicate pinmux nodes
arm64: dts: lx2160a: rename pinmux nodes for readability
arm64: dts: lx2160a: add sda gpio references for i2c bus recovery
arm64: dts: lx2160a: change zeros to hexadecimal in pinmux nodes
arm64: dts: lx2160a: complete pinmux for rcwsr12 configuration word
arm64: dts: lx2160a-cex7: add rtc alias
arm64: dts: lx2162a-sr-som: add crypto & rtc aliases, model
arm64: dts: lx2162a-clearfog: set sfp connector leds function and source
.../arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi | 10 +-
.../dts/freescale/fsl-lx2160a-clearfog-itx.dtsi | 2 +
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 183 ++++++++++++++++-----
.../boot/dts/freescale/fsl-lx2162a-clearfog.dts | 10 ++
.../boot/dts/freescale/fsl-lx2162a-sr-som.dtsi | 19 ++-
5 files changed, 180 insertions(+), 44 deletions(-)
---
base-commit: 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f
change-id: 20260304-lx2160-sd-cd-39319803d8ad
Best regards,
--
Josua Mayer <josua@solid-run.com>
^ permalink raw reply
* Re: [PATCH v5 04/10] arm64: dts: lx2160a: rename pinmux nodes for readability
From: Josua Mayer @ 2026-03-24 12:40 UTC (permalink / raw)
To: Frank Li
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Carlos Song, Mikhail Anikin, Yazan Shhady, Rabeeh Khoury,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
In-Reply-To: <abqtOFohYjf0q6P1@lizhi-Precision-Tower-5810>
Am 18.03.26 um 14:48 schrieb Frank Li:
> On Tue, Mar 17, 2026 at 05:20:20PM +0000, Josua Mayer wrote:
>> Hi Frank,
>>
>> On 3/17/26 02:36, Frank Li wrote:
>>> On Sat, Mar 14, 2026 at 01:05:14PM +0100, Josua Mayer wrote:
>>>> LX2160A pinmux is done in groups by various length bitfields within
>>>> configuration registers.
>>>>
>>>> Each group of pins is named in the reference manual after a primary
>>>> function using soc-specific naming, e.g. IIC1 (for i2c0).
>>>>
>>>> Hardware block numbering starts from zero in device-tree but one in the
>>>> reference manual.
>>>>
>>>> Rename the already defined pinmux nodes originally added for changing
>>>> i2c pins between i2c and gpio functions reflecting the reference manual
>>>> name (IIC) in the node name, and the device-tree name (i2c, gpio) in the
>>>> label.
>>>>
>>>> This makes it more clear to future developers that these nodes do in
> Needn't 'this' just
>
> Make it more ...
Okay, I'll rephrase it. "Make it more clear" was an intended result from renaming,
not the action itself.
>
>>>> fact configure a group of pins, and helps with cross-referencing
>>>> documentation.
>>>>
>>>> No functional change intended.
>>>>
>>>> Fixes: 8a1365c7bbc1 ("arm64: dts: lx2160a: add pinmux and i2c gpio to support bus recovery")
>>>> Signed-off-by: Josua Mayer <josua@solid-run.com>
>>>> ---
>>>> arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 64 +++++++++++++-------------
>>>> 1 file changed, 32 insertions(+), 32 deletions(-)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
>>>> index 41c9b4253f4a5..28500e8873909 100644
>>>> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
>>>> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
>>>> @@ -750,8 +750,8 @@ i2c0: i2c@2000000 {
>>>> clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
>>>> QORIQ_CLK_PLL_DIV(16)>;
>>>> pinctrl-names = "default", "gpio";
>>>> - pinctrl-0 = <&i2c0_scl>;
>>>> - pinctrl-1 = <&i2c0_scl_gpio>;
>>>> + pinctrl-0 = <&i2c0_pins>;
>>>> + pinctrl-1 = <&gpio0_3_2_pins>;
>>> why need change label name here. It should scl, why need change to pins?
>> Readability.
>>
>> It should definitely not be called "scl" precisely because the node
>> previously labeled i2c0_scl actually configures both sda and scl together.
> This need mention in commit message about why rename.
Okay.
>
> Frank
>> And plain "&i2c0" is already taken, so I added _pins.
>>
>> For the gpios I also changed the label because we are in SoC dtsi,
>> and gpios are not specific to sda or scl function.
>>
>> Further including the gpio numbers in the label helps spotting mistakes.
>>
>> This patch-set is a story explaining chapter by chapter why initially
>> I just reverted the original commit.
>>
>> sincerely
>> Josua Mayer
^ permalink raw reply
* Re: [PATCH v3 1/6] can: flexcan: use dedicated IRQ handlers for multi-IRQ platforms
From: Ciprian Marian Costea @ 2026-03-24 12:30 UTC (permalink / raw)
To: Marc Kleine-Budde
Cc: Vincent Mailhol, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Frank Li, Sascha Hauer, Fabio Estevam, Pengutronix Kernel Team,
linux-can, devicetree, linux-kernel, imx, linux-arm-kernel,
NXP S32 Linux Team, Christophe Lizzi, Alberto Ruiz,
Enric Balletbo, Eric Chanudet
In-Reply-To: <20260324-psychedelic-idealistic-dormouse-95b03c-mkl@pengutronix.de>
On 3/24/2026 1:56 PM, Marc Kleine-Budde wrote:
> On 23.03.2026 14:58:22, Ciprian Costea wrote:
>> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>>
>> On platforms with multiple IRQ lines (S32G2, MCF5441X), all lines are
>> registered to the same flexcan_irq() handler. Since these are distinct IRQ
>> numbers, they can be dispatched concurrently on different CPUs. Both
>> instances then read the same iflag and ESR registers unconditionally,
>> leading to duplicate frame processing.
>>
>> Fix this by splitting the monolithic handler into focused parts:
>> - flexcan_do_mb(): processes mailbox events
>> - flexcan_do_state(): processes device state change events
>> - flexcan_do_berr(): processes bus error events
>>
>> Introduce dedicated IRQ handlers for multi-IRQ platforms:
>> - flexcan_irq_mb(): mailbox-only, used for mb-0, mb-1 IRQ lines
>> - flexcan_irq_boff(): state-change-only, used for boff/state IRQ line
>> - flexcan_irq_berr(): bus-error-only, used for berr IRQ line
>>
>> The combined flexcan_irq() handler is preserved for single-IRQ
>> platforms with no functional change.
>
> Thanks for implementing this.
>
> Can you take care of the S32G2 which has 2 mailbox IRQs, too? Please in
> a separate patch.
>
> My idea was to take the "irq" argument of the IRQ handler and the quirks
> and figure out if you are the first or second mailbox IRQ handler.
>
> Convert these
>
> | struct flexcan_priv {
> | [...]
> | u64 rx_mask;
> | u64 tx_mask;
> | [...]
> | }
>
> into a struct and put an array of 2 of these structs into "struct
> flexcan_priv". Use correct mask array depending on IRQ handler.
>
> regards,
> Marc
>
> --
> Pengutronix e.K. | Marc Kleine-Budde |
> Embedded Linux | https://www.pengutronix.de |
> Vertretung Nürnberg | Phone: +49-5121-206917-129 |
> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-9 |
Hello Marc,
Thanks for your review.
I'll add a separate patch implementing per-MB-IRQ mask handling (needed
by S32G2) in V4. And thanks for the implementation suggestion. I'll take
it into account.
Now, unrelated to the per-MB-IRQ refactor, one thing I noticed during
the IRQ handlers split: dev->stats counters (e.g. rx_fifo_errors) can
be incremented concurrently from different IRQ handlers on different CPUs.
That said, these are just diagnostic counters and lost increments
should be benign. Do you think this warrants any synchronization/locking
mechanism, or is the current behavior acceptable?
Regards,
Ciprian
^ permalink raw reply
* [PATCH v2 7/7] arm64: dts: ti: k3-j722s-main: use J722S compatibles for WIZ, gmii-sel and CPSW3G
From: Nora Schiffer @ 2026-03-24 12:29 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Nishanth Menon, Vignesh Raghavendra, Tero Kristo
Cc: Siddharth Vadapalli, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vinod Koul, Neil Armstrong, netdev, devicetree,
linux-kernel, linux-phy, linux-arm-kernel, linux, Nora Schiffer
In-Reply-To: <cover.1774354734.git.nora.schiffer@ew.tq-group.com>
Update WIZ, gmii-sel and CPSW3G to use the J722S-specific compatible
strings, enabling SGMII support. The fallback compatibles preserve
compatibility of the updated Device Trees with older kernels.
Signed-off-by: Nora Schiffer <nora.schiffer@ew.tq-group.com>
---
arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
index 9ee5d0c8ffd1e..70f430aa3a944 100644
--- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
@@ -18,7 +18,7 @@ serdes_refclk: clk-0 {
&cbass_main {
serdes_wiz0: phy@f000000 {
- compatible = "ti,am64-wiz-10g";
+ compatible = "ti,j722s-wiz-10g", "ti,am64-wiz-10g";
ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
#address-cells = <1>;
#size-cells = <1>;
@@ -56,7 +56,7 @@ serdes0: serdes@f000000 {
};
serdes_wiz1: phy@f010000 {
- compatible = "ti,am64-wiz-10g";
+ compatible = "ti,j722s-wiz-10g", "ti,am64-wiz-10g";
ranges = <0x0f010000 0x0 0x0f010000 0x00010000>;
#address-cells = <1>;
#size-cells = <1>;
@@ -451,6 +451,14 @@ pcie0_ctrl: pcie0-ctrl@4070 {
};
};
+&cpsw3g {
+ compatible = "ti,j722s-cpsw-nuss", "ti,am642-cpsw-nuss";
+};
+
+&phy_gmii_sel {
+ compatible = "ti,j722s-phy-gmii-sel", "ti,am654-phy-gmii-sel";
+};
+
&oc_sram {
reg = <0x00 0x70000000 0x00 0x40000>;
ranges = <0x00 0x00 0x70000000 0x40000>;
--
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
https://www.tq-group.com/
^ permalink raw reply related
* [PATCH v2 5/7] phy: ti: gmii-sel: add support for J722S SoC family
From: Nora Schiffer @ 2026-03-24 12:29 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Nishanth Menon, Vignesh Raghavendra, Tero Kristo
Cc: Siddharth Vadapalli, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vinod Koul, Neil Armstrong, netdev, devicetree,
linux-kernel, linux-phy, linux-arm-kernel, linux, Nora Schiffer
In-Reply-To: <cover.1774354734.git.nora.schiffer@ew.tq-group.com>
The J722S gmii-sel is mostly identical to the AM64's, but additionally
supports SGMII.
Signed-off-by: Nora Schiffer <nora.schiffer@ew.tq-group.com>
---
drivers/phy/ti/phy-gmii-sel.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/phy/ti/phy-gmii-sel.c b/drivers/phy/ti/phy-gmii-sel.c
index 6213c2b6005a5..4e242b1892334 100644
--- a/drivers/phy/ti/phy-gmii-sel.c
+++ b/drivers/phy/ti/phy-gmii-sel.c
@@ -251,6 +251,13 @@ struct phy_gmii_sel_soc_data phy_gmii_sel_soc_am654 = {
.regfields = phy_gmii_sel_fields_am654,
};
+static const
+struct phy_gmii_sel_soc_data phy_gmii_sel_soc_j722s = {
+ .use_of_data = true,
+ .regfields = phy_gmii_sel_fields_am654,
+ .extra_modes = BIT(PHY_INTERFACE_MODE_SGMII),
+};
+
static const
struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw5g_soc_j7200 = {
.use_of_data = true,
@@ -307,6 +314,10 @@ static const struct of_device_id phy_gmii_sel_id_table[] = {
.compatible = "ti,am654-phy-gmii-sel",
.data = &phy_gmii_sel_soc_am654,
},
+ {
+ .compatible = "ti,j722s-phy-gmii-sel",
+ .data = &phy_gmii_sel_soc_j722s,
+ },
{
.compatible = "ti,j7200-cpsw5g-phy-gmii-sel",
.data = &phy_gmii_sel_cpsw5g_soc_j7200,
--
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
https://www.tq-group.com/
^ permalink raw reply related
* [PATCH v2 6/7] net: ethernet: ti: am65-cpsw: add support for J722S SoC family
From: Nora Schiffer @ 2026-03-24 12:29 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Nishanth Menon, Vignesh Raghavendra, Tero Kristo
Cc: Siddharth Vadapalli, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vinod Koul, Neil Armstrong, netdev, devicetree,
linux-kernel, linux-phy, linux-arm-kernel, linux, Nora Schiffer
In-Reply-To: <cover.1774354734.git.nora.schiffer@ew.tq-group.com>
The J722S CPSW3G is mostly identical to the AM64's, but additionally
supports SGMII.
Signed-off-by: Nora Schiffer <nora.schiffer@ew.tq-group.com>
---
drivers/net/ethernet/ti/am65-cpsw-nuss.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c
index d9400599e80a4..7ac75fc8cdcf4 100644
--- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c
+++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c
@@ -3468,6 +3468,13 @@ static const struct am65_cpsw_pdata am64x_cpswxg_pdata = {
.fdqring_mode = K3_RINGACC_RING_MODE_RING,
};
+static const struct am65_cpsw_pdata j722s_cpswxg_pdata = {
+ .quirks = AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ,
+ .ale_dev_id = "am64-cpswxg",
+ .fdqring_mode = K3_RINGACC_RING_MODE_RING,
+ .extra_modes = BIT(PHY_INTERFACE_MODE_SGMII),
+};
+
static const struct am65_cpsw_pdata j7200_cpswxg_pdata = {
.quirks = 0,
.ale_dev_id = "am64-cpswxg",
@@ -3495,6 +3502,7 @@ static const struct of_device_id am65_cpsw_nuss_of_mtable[] = {
{ .compatible = "ti,am654-cpsw-nuss", .data = &am65x_sr1_0},
{ .compatible = "ti,j721e-cpsw-nuss", .data = &j721e_pdata},
{ .compatible = "ti,am642-cpsw-nuss", .data = &am64x_cpswxg_pdata},
+ { .compatible = "ti,j722s-cpsw-nuss", .data = &j722s_cpswxg_pdata},
{ .compatible = "ti,j7200-cpswxg-nuss", .data = &j7200_cpswxg_pdata},
{ .compatible = "ti,j721e-cpswxg-nuss", .data = &j721e_cpswxg_pdata},
{ .compatible = "ti,j784s4-cpswxg-nuss", .data = &j784s4_cpswxg_pdata},
--
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
https://www.tq-group.com/
^ permalink raw reply related
* [PATCH v2 1/7] dt-bindings: phy: ti: phy-j721e-wiz: Add ti,j722s-wiz-10g compatible
From: Nora Schiffer @ 2026-03-24 12:29 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Nishanth Menon, Vignesh Raghavendra, Tero Kristo
Cc: Siddharth Vadapalli, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vinod Koul, Neil Armstrong, netdev, devicetree,
linux-kernel, linux-phy, linux-arm-kernel, linux, Nora Schiffer
In-Reply-To: <cover.1774354734.git.nora.schiffer@ew.tq-group.com>
The J722S WIZ is mostly identical to the AM64's, but additionally supports
SGMII. The AM64 compatible ti,am64-wiz-10g is used as a fallback.
Signed-off-by: Nora Schiffer <nora.schiffer@ew.tq-group.com>
---
.../bindings/phy/ti,phy-j721e-wiz.yaml | 20 ++++++++++++-------
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
index 3f16ff14484d2..283e3eedc0f31 100644
--- a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
+++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
@@ -12,13 +12,19 @@ maintainers:
properties:
compatible:
- enum:
- - ti,j721e-wiz-16g
- - ti,j721e-wiz-10g
- - ti,j721s2-wiz-10g
- - ti,am64-wiz-10g
- - ti,j7200-wiz-10g
- - ti,j784s4-wiz-10g
+ oneOf:
+ - items:
+ - enum:
+ - ti,j721e-wiz-16g
+ - ti,j721e-wiz-10g
+ - ti,j721s2-wiz-10g
+ - ti,am64-wiz-10g
+ - ti,j7200-wiz-10g
+ - ti,j784s4-wiz-10g
+ - items:
+ - enum:
+ - ti,j722s-wiz-10g
+ - const: ti,am64-wiz-10g
power-domains:
maxItems: 1
--
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
https://www.tq-group.com/
^ permalink raw reply related
* [PATCH v2 4/7] phy: ti: phy-j721e-wiz: add support for J722S SoC family
From: Nora Schiffer @ 2026-03-24 12:29 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Nishanth Menon, Vignesh Raghavendra, Tero Kristo
Cc: Siddharth Vadapalli, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vinod Koul, Neil Armstrong, netdev, devicetree,
linux-kernel, linux-phy, linux-arm-kernel, linux, Nora Schiffer
In-Reply-To: <cover.1774354734.git.nora.schiffer@ew.tq-group.com>
The J722S WIZ is mostly identical to the AM64's, but additionally supports
SGMII.
Signed-off-by: Nora Schiffer <nora.schiffer@ew.tq-group.com>
---
drivers/phy/ti/phy-j721e-wiz.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index 6b584706b913a..7531a8a049123 100644
--- a/drivers/phy/ti/phy-j721e-wiz.c
+++ b/drivers/phy/ti/phy-j721e-wiz.c
@@ -331,6 +331,7 @@ enum wiz_type {
J721E_WIZ_16G,
J721E_WIZ_10G, /* Also for J7200 SR1.0 */
AM64_WIZ_10G,
+ J722S_WIZ_10G,
J7200_WIZ_10G, /* J7200 SR2.0 */
J784S4_WIZ_10G,
J721S2_WIZ_10G,
@@ -1020,6 +1021,7 @@ static void wiz_clock_cleanup(struct wiz *wiz, struct device_node *node)
switch (wiz->type) {
case AM64_WIZ_10G:
+ case J722S_WIZ_10G:
case J7200_WIZ_10G:
case J784S4_WIZ_10G:
case J721S2_WIZ_10G:
@@ -1089,6 +1091,7 @@ static void wiz_clock_init(struct wiz *wiz)
switch (wiz->type) {
case AM64_WIZ_10G:
+ case J722S_WIZ_10G:
case J7200_WIZ_10G:
switch (rate) {
case REF_CLK_100MHZ:
@@ -1158,6 +1161,7 @@ static int wiz_clock_probe(struct wiz *wiz, struct device_node *node)
switch (wiz->type) {
case AM64_WIZ_10G:
+ case J722S_WIZ_10G:
case J7200_WIZ_10G:
case J784S4_WIZ_10G:
case J721S2_WIZ_10G:
@@ -1246,6 +1250,14 @@ static int wiz_phy_fullrt_div(struct wiz *wiz, int lane)
if (wiz->lane_phy_type[lane] == PHY_TYPE_SGMII)
return regmap_field_write(wiz->p0_fullrt_div[lane], 0x2);
break;
+
+ case J722S_WIZ_10G:
+ if (wiz->lane_phy_type[lane] == PHY_TYPE_PCIE)
+ return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1);
+ if (wiz->lane_phy_type[lane] == PHY_TYPE_SGMII)
+ return regmap_field_write(wiz->p0_fullrt_div[lane], 0x2);
+ break;
+
default:
return 0;
}
@@ -1350,6 +1362,15 @@ static struct wiz_data am64_10g_data = {
.clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
};
+static struct wiz_data j722s_10g_data = {
+ .type = J722S_WIZ_10G,
+ .pll0_refclk_mux_sel = &pll0_refclk_mux_sel,
+ .pll1_refclk_mux_sel = &pll1_refclk_mux_sel,
+ .refclk_dig_sel = &refclk_dig_sel_10g,
+ .clk_mux_sel = clk_mux_sel_10g,
+ .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
+};
+
static struct wiz_data j7200_pg2_10g_data = {
.type = J7200_WIZ_10G,
.pll0_refclk_mux_sel = &sup_pll0_refclk_mux_sel,
@@ -1389,6 +1410,9 @@ static const struct of_device_id wiz_id_table[] = {
{
.compatible = "ti,am64-wiz-10g", .data = &am64_10g_data,
},
+ {
+ .compatible = "ti,j722s-wiz-10g", .data = &j722s_10g_data,
+ },
{
.compatible = "ti,j7200-wiz-10g", .data = &j7200_pg2_10g_data,
},
--
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
https://www.tq-group.com/
^ permalink raw reply related
* [PATCH v2 0/7] J722S SGMII support
From: Nora Schiffer @ 2026-03-24 12:29 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Nishanth Menon, Vignesh Raghavendra, Tero Kristo
Cc: Siddharth Vadapalli, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vinod Koul, Neil Armstrong, netdev, devicetree,
linux-kernel, linux-phy, linux-arm-kernel, linux, Nora Schiffer
The J722S CPSW and SERDES are very similar to the variants found on the
AM64, but they additionally support SGMII. Introduce new compatible
strings for the J722S to add this support to the drivers.
This is a prerequisite for the Single-Pair Ethernet interface of the
TQ-Systems MBa67xx baseboard for the TQMa67xx SoM, which will be
submitted separately.
v2:
- Keep support for the AM64 compatible strings as a fallback, adjust commit
messages (patches 1-3 and 7)
- No changes to patches 4-6
Nora Schiffer (7):
dt-bindings: phy: ti: phy-j721e-wiz: Add ti,j722s-wiz-10g compatible
dt-bindings: phy: ti: phy-gmii-sel: Add ti,j722s-phy-gmii-sel
compatible
dt-bindings: net: ti: k3-am654-cpsw-nuss: Add ti,j722s-cpsw-nuss
compatible
phy: ti: phy-j721e-wiz: add support for J722S SoC family
phy: ti: gmii-sel: add support for J722S SoC family
net: ethernet: ti: am65-cpsw: add support for J722S SoC family
arm64: dts: ti: k3-j722s-main: use J722S compatibles for WIZ, gmii-sel
and CPSW3G
.../bindings/net/ti,k3-am654-cpsw-nuss.yaml | 20 ++++++++++------
.../bindings/phy/ti,phy-gmii-sel.yaml | 24 ++++++++++++-------
.../bindings/phy/ti,phy-j721e-wiz.yaml | 20 ++++++++++------
arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 12 ++++++++--
drivers/net/ethernet/ti/am65-cpsw-nuss.c | 8 +++++++
drivers/phy/ti/phy-gmii-sel.c | 11 +++++++++
drivers/phy/ti/phy-j721e-wiz.c | 24 +++++++++++++++++++
7 files changed, 94 insertions(+), 25 deletions(-)
--
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
https://www.tq-group.com/
^ permalink raw reply
* [PATCH v2 3/7] dt-bindings: net: ti: k3-am654-cpsw-nuss: Add ti,j722s-cpsw-nuss compatible
From: Nora Schiffer @ 2026-03-24 12:29 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Nishanth Menon, Vignesh Raghavendra, Tero Kristo
Cc: Siddharth Vadapalli, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vinod Koul, Neil Armstrong, netdev, devicetree,
linux-kernel, linux-phy, linux-arm-kernel, linux, Nora Schiffer
In-Reply-To: <cover.1774354734.git.nora.schiffer@ew.tq-group.com>
The J722S CPSW3G is mostly identical to the AM64's, but additionally
supports SGMII. The AM64 compatible ti,am642-cpsw-nuss is used as a
fallback.
Signed-off-by: Nora Schiffer <nora.schiffer@ew.tq-group.com>
---
.../bindings/net/ti,k3-am654-cpsw-nuss.yaml | 20 ++++++++++++-------
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml b/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml
index a959c1d7e643a..70d25f5ff1cfe 100644
--- a/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml
+++ b/Documentation/devicetree/bindings/net/ti,k3-am654-cpsw-nuss.yaml
@@ -53,13 +53,19 @@ properties:
"#size-cells": true
compatible:
- enum:
- - ti,am642-cpsw-nuss
- - ti,am654-cpsw-nuss
- - ti,j7200-cpswxg-nuss
- - ti,j721e-cpsw-nuss
- - ti,j721e-cpswxg-nuss
- - ti,j784s4-cpswxg-nuss
+ oneOf:
+ - items:
+ - enum:
+ - ti,am642-cpsw-nuss
+ - ti,am654-cpsw-nuss
+ - ti,j7200-cpswxg-nuss
+ - ti,j721e-cpsw-nuss
+ - ti,j721e-cpswxg-nuss
+ - ti,j784s4-cpswxg-nuss
+ - items:
+ - enum:
+ - ti,j722s-cpsw-nuss
+ - const: ti,am642-cpsw-nuss
reg:
maxItems: 1
--
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
https://www.tq-group.com/
^ permalink raw reply related
* [PATCH v2 2/7] dt-bindings: phy: ti: phy-gmii-sel: Add ti,j722s-phy-gmii-sel compatible
From: Nora Schiffer @ 2026-03-24 12:29 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Nishanth Menon, Vignesh Raghavendra, Tero Kristo
Cc: Siddharth Vadapalli, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Vinod Koul, Neil Armstrong, netdev, devicetree,
linux-kernel, linux-phy, linux-arm-kernel, linux, Nora Schiffer
In-Reply-To: <cover.1774354734.git.nora.schiffer@ew.tq-group.com>
The J722S gmii-sel is mostly identical to the AM64's, but additionally
supports SGMII. The AM64 compatible ti,am654-phy-gmii-sel is used as a
fallback.
Signed-off-by: Nora Schiffer <nora.schiffer@ew.tq-group.com>
---
.../bindings/phy/ti,phy-gmii-sel.yaml | 24 ++++++++++++-------
1 file changed, 15 insertions(+), 9 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
index be41b4547ec6d..6e12a75100eb8 100644
--- a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
+++ b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml
@@ -47,15 +47,21 @@ description: |
properties:
compatible:
- enum:
- - ti,am3352-phy-gmii-sel
- - ti,dra7xx-phy-gmii-sel
- - ti,am43xx-phy-gmii-sel
- - ti,dm814-phy-gmii-sel
- - ti,am654-phy-gmii-sel
- - ti,j7200-cpsw5g-phy-gmii-sel
- - ti,j721e-cpsw9g-phy-gmii-sel
- - ti,j784s4-cpsw9g-phy-gmii-sel
+ oneOf:
+ - items:
+ - enum:
+ - ti,am3352-phy-gmii-sel
+ - ti,dra7xx-phy-gmii-sel
+ - ti,am43xx-phy-gmii-sel
+ - ti,dm814-phy-gmii-sel
+ - ti,am654-phy-gmii-sel
+ - ti,j7200-cpsw5g-phy-gmii-sel
+ - ti,j721e-cpsw9g-phy-gmii-sel
+ - ti,j784s4-cpsw9g-phy-gmii-sel
+ - items:
+ - enum:
+ - ti,j722s-phy-gmii-sel
+ - const: ti,am654-phy-gmii-sel
reg:
maxItems: 1
--
TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
Amtsgericht München, HRB 105018
Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
https://www.tq-group.com/
^ permalink raw reply related
* [PATCH] PCI: aspeed: Fix IRQ domain leak on platform_get_irq() failure
From: Jacky Chou @ 2026-03-24 12:22 UTC (permalink / raw)
To: Felix Gu, Lorenzo Pieralisi, Krzysztof Wilczyński,
Manivannan Sadhasivam, Rob Herring, Bjorn Helgaas, Joel Stanley,
Andrew Jeffery
Cc: linux-aspeed@lists.ozlabs.org, linux-pci@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
In-Reply-To: <20260324-aspeed-v1-1-354181624c00@gmail.com>
Hi Felix,
Thank you for your patch to help identify this issue.
> The aspeed_pcie_probe() function calls aspeed_pcie_init_irq_domain() which
> allocates pcie->intx_domain and initializes MSI. However, if
> platform_get_irq() fails afterwards, the cleanup action was not yet registered
> via devm_add_action_or_reset(), causing the IRQ domain resources to leak.
>
> Fix this by registering the devm cleanup action immediately after
> aspeed_pcie_init_irq_domain() succeeds, before calling platform_get_irq().
> This ensures proper cleanup on any subsequent failure.
>
> Fixes: 9aa0cb68fcc1 ("PCI: aspeed: Add ASPEED PCIe RC driver")
> Signed-off-by: Felix Gu <ustc.gu@gmail.com>
> ---
> drivers/pci/controller/pcie-aspeed.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/pci/controller/pcie-aspeed.c
> b/drivers/pci/controller/pcie-aspeed.c
> index 3e1a39d1e648..6acfae7d026e 100644
> --- a/drivers/pci/controller/pcie-aspeed.c
> +++ b/drivers/pci/controller/pcie-aspeed.c
> @@ -1052,14 +1052,14 @@ static int aspeed_pcie_probe(struct
> platform_device *pdev)
> if (ret)
> return ret;
>
> - irq = platform_get_irq(pdev, 0);
> - if (irq < 0)
> - return irq;
> -
> ret = devm_add_action_or_reset(dev, aspeed_pcie_irq_domain_free,
> pcie);
> if (ret)
> return ret;
>
> + irq = platform_get_irq(pdev, 0);
> + if (irq < 0)
> + return irq;
> +
> ret = devm_request_irq(dev, irq, aspeed_pcie_intr_handler,
> IRQF_SHARED,
> dev_name(dev), pcie);
> if (ret)
I have verified your patch on our platforms, AST2600 and AST2700, and it fixes this issue.
Tested-by: Jacky Chou <jacky_chou@aspeedtech.com>
Thanks,
Jacky
^ permalink raw reply
* Re: [PATCH 1/2] arm64/entry: Fix involuntary preemption exception masking
From: Thomas Gleixner @ 2026-03-24 12:19 UTC (permalink / raw)
To: Mark Rutland
Cc: vladimir.murzin, peterz, catalin.marinas, ruanjinjie,
linux-kernel, luto, will, linux-arm-kernel
In-Reply-To: <87fr5six4d.ffs@tglx>
On Sun, Mar 22 2026 at 00:25, Thomas Gleixner wrote:
> On Fri, Mar 20 2026 at 17:31, Mark Rutland wrote:
> Looking at those details made me also look at this magic
> arch_irqentry_exit_need_resched() inline function.
>
> /*
> * DAIF.DA are cleared at the start of IRQ/FIQ handling, and when GIC
> * priority masking is used the GIC irqchip driver will clear DAIF.IF
> * using gic_arch_enable_irqs() for normal IRQs. If anything is set in
> * DAIF we must have handled an NMI, so skip preemption.
> */
> if (system_uses_irq_prio_masking() && read_sysreg(daif))
> return false;
>
> Why is this using irqentry_enter/exit() in the first place?
Ah. The entry point does
if (regs_irqs_disabled(regs))
do_nmi();
else
do_irq();
So you end up in do_irq() and eventually in the preemption path and need
that check to prevent scheduling. So that should be fine and obviously
won't hit the code path I outlined.
Thanks,
tglx
^ permalink raw reply
* RE: [PATCH] arm64: dts: imx8mp-debix-model-a: Correct PAD settings for pmicirqgrp
From: Peng Fan @ 2026-03-24 12:18 UTC (permalink / raw)
To: Laurent Pinchart, Peng Fan (OSS)
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Marco Felsch, Daniel Scally, devicetree@vger.kernel.org,
imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, Kieran Bingham, Stefan Klug
In-Reply-To: <20260324093850.GA2351719@killaraus.ideasonboard.com>
Hi Laurent,
> Subject: Re: [PATCH] arm64: dts: imx8mp-debix-model-a: Correct PAD
> settings for pmicirqgrp
>
> Hi Peng,
>
> Thank you for the patch.
>
> On Tue, Mar 24, 2026 at 11:16:13AM +0800, Peng Fan (OSS) wrote:
> > From: Peng Fan <peng.fan@nxp.com>
> >
> > With commit 5d0efaf47ee90 ("regulator: pca9450: Correct interrupt
> > type"), there is interrupt storm for i.MX8MP DEBIX Model A. Per
> > schematic, there is no on board PULL-UP resistors for GPIO1_IO03, so
> > need to set PAD PUE and PU together to make pull up work properly.
> >
> > Fixes: c86d350aae68e ("arm64: dts: Add device tree for the Debix
> Model
> > A Board")
> > Reported-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > Closes:
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
>
> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Thanks for quick testing.
>
> Frank, would you be able to handle this as a v7.0 regression fix ?
>
> I think the same is needed for imx8mp-debix-som-a.dtsi, but I can't
> confirm it as I don't have the schematics for the SoM, neither do I have
> access to the board.
I also gave a look, seems there are several boards are not setting
PAD correctly.
imx8mp-icore-mx8mp.dtsi
imx8mp-edm-g.dtsi
imx8mp-dhcom-som.dtsi
imx8mp-debix-som-a-bmb-08.dts
imx8mp-debix-som-a.dtsi
imx8mp-data-modul-edm-sbc.dts
imx8mp-aristainetos3a-som-v1.dtsi
imx8mp-ab2.dts
imx8mp-navqp
imx8mp-skov
I not check schematic, but from the PAD settings, only set PU is
not enough, PUE should also be set, unless there is board
PU.
We may need to fix them all. Let me do further check to see
if there are schematics available on internet.
Regards
Peng.
>
> Dan, Kieran, Stefan, could one of you check if you get an interrupt
> storm from the PMIC on v7.0 ?
>
> > ---
> > arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts
> > b/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts
> > index
> >
> 9422beee30b29c5a551b08476c80fbff96af3439..df7489587e48ed0c6
> 78f11291f6f
> > 2b77082ade95 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts
> > +++ b/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts
> > @@ -440,7 +440,7 @@ MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA
> 0x400001c3
> >
> > pinctrl_pmic: pmicirqgrp {
> > fsl,pins = <
> > - MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03
> 0x41
> > + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03
> 0x000001c0
> > >;
> > };
> >
> >
> > ---
> > base-commit: 09c0f7f1bcdbc3c37a5a760cbec76bf18f278406
> > change-id: 20260324-imx8mp-dts-fix-512530fe4dcd
>
> --
> Regards,
>
> Laurent Pinchart
^ permalink raw reply
* Re: [PATCH v3 0/6] can: flexcan: Add NXP S32N79 SoC support
From: Ciprian Marian Costea @ 2026-03-24 12:18 UTC (permalink / raw)
To: Marc Kleine-Budde
Cc: Vincent Mailhol, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Frank Li, Sascha Hauer, Fabio Estevam, Pengutronix Kernel Team,
linux-can, devicetree, linux-kernel, imx, linux-arm-kernel,
NXP S32 Linux Team, Christophe Lizzi, Alberto Ruiz,
Enric Balletbo, Eric Chanudet
In-Reply-To: <20260324-nice-boa-of-elegance-10c519-mkl@pengutronix.de>
On 3/24/2026 1:58 PM, Marc Kleine-Budde wrote:
> On 23.03.2026 14:58:21, Ciprian Costea wrote:
>> From: Ciprian Marian Costea <ciprianmarian.costea@oss.nxp.com>
>>
>> This patch series adds FlexCAN support for the NXP S32N79 SoC.
>>
>> The S32N79 is an automotive-grade processor from NXP with multiple
>> FlexCAN instances. The FlexCAN IP integration on S32N79 differs from
>> other SoCs in the interrupt routing - it uses two separate interrupt
>> lines:
>> - one interrupt for mailboxes 0-127
>> - one interrupt for bus error detection and device state changes
>>
>> The CAN controllers are connected through an irqsteer interrupt
>> controller in the RCU (Resource Control Unit) domain.
>>
>> This series:
>> 1. Splits flexcan_irq() into dedicated handlers for multi-IRQ platforms
>> 2. Adds dt-bindings documentation for S32N79 FlexCAN
>> 3. Introduces FLEXCAN_QUIRK_IRQ_BERR to handle the two-interrupt
>> configuration
>> 4. Adds S32N79 device data and compatible string to the driver
>> 5. Adds FlexCAN device tree nodes for S32N79 SoC
>> 6. Enables FlexCAN devices on the S32N79-RDB board
>
> Can you please add support for multiple IRQs to
> flexcan_chip_interrupts_enable().
>
> regards,
> Marc
>
Hello Marc,
Yes. Thanks for pointing this out. I will update
flexcan_chip_interrupts_enable() in V4.
Regards,
Ciprian
^ permalink raw reply
* Re: [PATCH v2] net: stmmac: skip VLAN restore when VLAN hash ops are missing
From: Paolo Abeni @ 2026-03-24 12:14 UTC (permalink / raw)
To: Michal Piekos, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Maxime Coquelin, Alexandre Torgue, Ovidiu Panait,
Russell King (Oracle)
Cc: netdev, linux-stm32, linux-arm-kernel, linux-kernel
In-Reply-To: <20260321-vlan-restore-error-v2-1-45cf56a5223d@mmpsystems.pl>
On 3/21/26 6:38 AM, Michal Piekos wrote:
> stmmac_vlan_restore() unconditionally calls stmmac_vlan_update() when
> NETIF_F_VLAN_FEATURES is set. On platforms where priv->hw->vlan (or
> ->update_vlan_hash) is not provided, stmmac_update_vlan_hash() returns
> -EINVAL via stmmac_do_void_callback(), resulting in a spurious
> "Failed to restore VLANs" error even when no VLAN filtering is in use.
>
> Check presence of VLAN HW FILTER flags before stmmac_vlan_update().
>
> Tested on Orange Pi Zero 3.
>
> Fixes: bd7ad51253a7 ("net: stmmac: Fix VLAN HW state restore")
> Signed-off-by: Michal Piekos <michal.piekos@mmpsystems.pl>
> ---
> This patch fixes a noisy "Failed to restore VLANs" message on platforms
> where stmmac VLAN hash ops are not implemented.
> stmmac_vlan_restore() calls stmmac_vlan_update() without checking for
> VLAN hash ops presence which results in -EINVAL.
> ---
> Changes in v2:
> - Replace check for hash ops with check for HW FILTER flags
> - Link to v1: https://lore.kernel.org/r/20260314-vlan-restore-error-v1-1-4fc6c3e2115f@mmpsystems.pl
> ---
> drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> index 6827c99bde8c..cfc0ce9cec9c 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> @@ -6863,7 +6863,8 @@ static int stmmac_vlan_restore(struct stmmac_priv *priv)
> {
> int ret;
>
> - if (!(priv->dev->features & NETIF_F_VLAN_FEATURES))
> + if (!(priv->dev->features &
> + (NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_STAG_FILTER)))
> return 0;
>
> if (priv->hw->num_vlan)
Adding Russell.
It's not obvious to me that with this change the
restore_hw_vlan_rx_fltr() and vlan_update() callback are still invoked
in all the relevant driver/features permutation.
/P
^ permalink raw reply
* RE: [PATCH v2 0/9] accel: New driver for NXP's Neutron NPU
From: Ioana Ciocoi Radulescu @ 2026-03-24 12:12 UTC (permalink / raw)
To: Tomeu Vizoso
Cc: Oded Gabbay, Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann,
David Airlie, Simona Vetter, Sumit Semwal, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Shawn Guo, Frank Li,
Christian König, dri-devel@lists.freedesktop.org,
linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org,
devicetree@vger.kernel.org, imx@lists.linux.dev,
linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org,
linaro-mm-sig@lists.linaro.org, Jiwei Fu, Forrest Shi,
Alexandru Iulian Taran, Daniel Baluta
In-Reply-To: <CAAObsKDAzfib86rXqt9FjXV68yRkBzmijcyR+x=1MsPYd=MQWQ@mail.gmail.com>
On Saturday, March 21, 2026 at 7:19 PM, Tomeu Vizoso wrote:
>
> Hi Ioana,
>
> Looks like the userspace portion of the driver is closed source
> (libNeutronDriver.so)?
>
> https://github.com/nxp-imx/tflite-neutron-delegate/blob/lf-6.12.49_2.2
> .0/CMakeLists.txt
Hi Tomeu,
Yes, it's closed for now. We do plan to publish the source code
on github, but I believe that's still a few months away.
Thanks,
Ioana
>
> Regards,
>
> Tomeu
>
> On Fri, Mar 6, 2026 at 2:27 PM Ioana Ciocoi-Radulescu
> <ruxandra.radulescu@nxp.com> wrote:
> >
> > Introduce a new accel driver for the Neutron Neural Processing Unit
> > (NPU), along with associated dt-bindings and DTS node.
> >
> > The first patch extends the GEM DMA helper APIs to allow bidirectional
> > mapping of non-coherent DMA buffers. While not part of the Neutron
> > driver, it's a prerequisite allowing us to use the GEM DMA helper.
> >
> > Neutron is a Neural Processing Unit from NXP, providing machine
> > learning (ML) acceleration for edge AI applications. Neutron is
> > integrated on NXP SoCs such as the i.MX95.
> >
> > The NPU consists of the following:
> > - RISC-V core running a proprietary firmware
> > - One or more Neutron cores, representing the main computation
> > engine performing ML operations
> > - Dedicated fast memory (TCM)
> > - DMA engine that handles data transfers between DDR and TCM
> >
> > The firmware is closed source and distributed as a binary here [1].
> >
> > The Neutron software stack also contains a userspace library [1] and a
> > LiteRT custom delegate [2] that allow integration with standard LiteRT
> > tools.
> >
> > [1] https://github.com/nxp-upstream/neutron/tree/upstream
> > [2] https://github.com/nxp-imx/tflite-neutron-delegate
> >
> > Signed-off-by: Ioana Ciocoi-Radulescu <ruxandra.radulescu@nxp.com>
> > ---
> > Changes in v2:
> > - rebase on newer drm-misc-next
> > - dt bindings: clock fixes and renames
> > - update DTS to match new names
> > - remove unnecessary fields from neutron_job structure
> > - fix use of uninitialized variable
> >
> > - Link to v1:
> > https://lore.kernel.org/r/20260226-neutron-v1-0-46eccb3bb50a@nxp.com
> >
> > ---
> > Ioana Ciocoi-Radulescu (9):
> > drm/gem-dma: Add flag for bidirectional mapping of non-coherent GEM
> DMA buffers
> > accel/neutron: Add documentation for NXP Neutron accelerator driver
> > dt-bindings: npu: Add NXP Neutron
> > accel/neutron: Add driver for NXP Neutron NPU
> > accel/neutron: Add GEM buffer object support
> > accel/neutron: Add mailbox support
> > accel/neutron: Add job submission IOCTL
> > accel/neutron: Add logging support
> > arm64: dts: imx95: Add Neutron node
> >
> > Documentation/accel/index.rst | 1 +
> > Documentation/accel/neutron/index.rst | 12 +
> > Documentation/accel/neutron/neutron.rst | 131 ++++++++
> > .../devicetree/bindings/npu/nxp,imx95-neutron.yaml | 96 ++++++
> > MAINTAINERS | 10 +
> > arch/arm64/boot/dts/freescale/imx95.dtsi | 28 ++
> > drivers/accel/Kconfig | 1 +
> > drivers/accel/Makefile | 3 +-
> > drivers/accel/neutron/Kconfig | 16 +
> > drivers/accel/neutron/Makefile | 12 +
> > drivers/accel/neutron/neutron_debugfs.c | 34 ++
> > drivers/accel/neutron/neutron_debugfs.h | 15 +
> > drivers/accel/neutron/neutron_device.c | 239 +++++++++++++
> > drivers/accel/neutron/neutron_device.h | 155 +++++++++
> > drivers/accel/neutron/neutron_driver.c | 262 +++++++++++++++
> > drivers/accel/neutron/neutron_driver.h | 16 +
> > drivers/accel/neutron/neutron_gem.c | 116 +++++++
> > drivers/accel/neutron/neutron_gem.h | 14 +
> > drivers/accel/neutron/neutron_job.c | 372
> +++++++++++++++++++++
> > drivers/accel/neutron/neutron_job.h | 43 +++
> > drivers/accel/neutron/neutron_mailbox.c | 47 +++
> > drivers/accel/neutron/neutron_mailbox.h | 42 +++
> > drivers/gpu/drm/drm_gem_dma_helper.c | 6 +-
> > include/drm/drm_gem_dma_helper.h | 3 +
> > include/uapi/drm/neutron_accel.h | 130 +++++++
> > 25 files changed, 1801 insertions(+), 3 deletions(-)
> > ---
> > base-commit: 6716101ae42949e98ad4b9e71eeba08c055be410
> > change-id: 20260226-neutron-c435e39d167f
> >
> > Best regards,
> > --
> > Ioana Ciocoi-Radulescu <ruxandra.radulescu@nxp.com>
> >
^ permalink raw reply
* Re: [PATCH v4 1/3] dt-bindings: dma: arm-dma350: document generic and combined IRQ topologies
From: Robin Murphy @ 2026-03-24 12:04 UTC (permalink / raw)
To: Jun Guo, peter.chen, fugang.duan, robh, krzk+dt, conor+dt, vkoul,
ychuang3, schung, Frank.Li
Cc: dmaengine, devicetree, linux-kernel, cix-kernel-upstream,
linux-arm-kernel
In-Reply-To: <20260323114822.1925869-2-jun.guo@cixtech.com>
On 2026-03-23 11:48 am, Jun Guo wrote:
> Update the DMA-350 DT binding to match the current driver behavior.
>
> Allow both:
> - "arm,dma-350" as the generic compatible, and
> - "cix,sky1-dma-350", "arm,dma-350" for SoC-specific fallback usage.
>
> Also document interrupt topology variants supported by hardware
> integration:
> - one combined interrupt for all channels, or
> - one interrupt per channel (up to 8 channels).
To repeat myself for the 3rd time, this is at best unnecessary, and at
worst arguably wrong. Here's an example of a system which happens to use
the combined interrupt from another IP block which also offers both options:
https://web.git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/freescale/imx8qm.dtsi#n279
Same thing here; each channel is a distinct interrupt source, so it is
perfectly honest to describe that consistently in DT, regardless of
whether or not the interrupt signals are still distinct by the time they
reach the interrupt controller.
Furthermore, in this case the IRQ_COMB_NONSEC interrupt actually has
additional functionality beyond just being a mux of the individual
IRQ_CHANNEL interrupts. So although Linux probably won't ever care, if
it's going to be in the DT binding then it should really be distinct
from the channel interrupts anyway, since systems could well wire them
*all* up, and an OS could choose to use the IRQ_CHANNEL outputs directly
for individual channel completion/error status, while also using the
IRQ_COMB_NONSEC just for its overall INTR_ALLCH{STOPPED,PAUSED,IDLE} status.
If you only want to make your thing work in Linux, all that is needed is
a 1-line change in the driver to enable the INTR_ANYCHINTR bit (which as
I've also said before, we can do unconditionally because we're *not*
using the other INTR_ALLCH stuff), and to write your DT using the
existing binding. "One interrupt per channel" already carries no
expectation that they all have to be *different* interrupts.
Thanks,
Robin.
> Assisted-by: Cursor: GPT-5.3-Codex
> Signed-off-by: Jun Guo <jun.guo@cixtech.com>
> ---
> .../devicetree/bindings/dma/arm,dma-350.yaml | 34 +++++++++++++------
> 1 file changed, 24 insertions(+), 10 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/dma/arm,dma-350.yaml b/Documentation/devicetree/bindings/dma/arm,dma-350.yaml
> index 429f682f15d8..47091614d1b4 100644
> --- a/Documentation/devicetree/bindings/dma/arm,dma-350.yaml
> +++ b/Documentation/devicetree/bindings/dma/arm,dma-350.yaml
> @@ -14,7 +14,14 @@ allOf:
>
> properties:
> compatible:
> - const: arm,dma-350
> + description:
> + Use "arm,dma-350" for generic integration. A SoC-specific
> + compatible may be listed first, followed by "arm,dma-350".
> + oneOf:
> + - const: arm,dma-350
> + - items:
> + - const: cix,sky1-dma-350
> + - const: arm,dma-350
>
> reg:
> items:
> @@ -22,15 +29,22 @@ properties:
>
> interrupts:
> minItems: 1
> - items:
> - - description: Channel 0 interrupt
> - - description: Channel 1 interrupt
> - - description: Channel 2 interrupt
> - - description: Channel 3 interrupt
> - - description: Channel 4 interrupt
> - - description: Channel 5 interrupt
> - - description: Channel 6 interrupt
> - - description: Channel 7 interrupt
> + maxItems: 8
> + description:
> + Either one interrupt per channel (8 interrupts), or one
> + combined interrupt for all channels.
> + oneOf:
> + - items:
> + - description: Channel 0 interrupt
> + - description: Channel 1 interrupt
> + - description: Channel 2 interrupt
> + - description: Channel 3 interrupt
> + - description: Channel 4 interrupt
> + - description: Channel 5 interrupt
> + - description: Channel 6 interrupt
> + - description: Channel 7 interrupt
> + - items:
> + - description: Combined interrupt shared by all channels
>
> "#dma-cells":
> const: 1
^ permalink raw reply
* [PATCH v5 1/3] dt-bindings: dma: arm-dma350: document combined and per-channel IRQ topologies
From: Jun Guo @ 2026-03-24 12:01 UTC (permalink / raw)
To: peter.chen, fugang.duan, robh, krzk+dt, conor+dt, vkoul, ychuang3,
schung, robin.murphy, Frank.Li
Cc: dmaengine, devicetree, linux-kernel, cix-kernel-upstream,
linux-arm-kernel, Jun Guo
In-Reply-To: <20260324120113.3681830-1-jun.guo@cixtech.com>
Document the interrupt topologies supported by DMA-350 integration:
- one combined interrupt for all channels, or
- one interrupt per channel (up to 8 channels).
Assisted-by: Cursor:GPT-5.3-Codex
Signed-off-by: Jun Guo <jun.guo@cixtech.com>
---
.../devicetree/bindings/dma/arm,dma-350.yaml | 25 ++++++++++++-------
1 file changed, 16 insertions(+), 9 deletions(-)
diff --git a/Documentation/devicetree/bindings/dma/arm,dma-350.yaml b/Documentation/devicetree/bindings/dma/arm,dma-350.yaml
index 429f682f15d8..bec9dc32541b 100644
--- a/Documentation/devicetree/bindings/dma/arm,dma-350.yaml
+++ b/Documentation/devicetree/bindings/dma/arm,dma-350.yaml
@@ -22,15 +22,22 @@ properties:
interrupts:
minItems: 1
- items:
- - description: Channel 0 interrupt
- - description: Channel 1 interrupt
- - description: Channel 2 interrupt
- - description: Channel 3 interrupt
- - description: Channel 4 interrupt
- - description: Channel 5 interrupt
- - description: Channel 6 interrupt
- - description: Channel 7 interrupt
+ maxItems: 8
+ description:
+ Either one interrupt per channel (8 interrupts), or one
+ combined interrupt for all channels.
+ oneOf:
+ - items:
+ - description: Channel 0 interrupt
+ - description: Channel 1 interrupt
+ - description: Channel 2 interrupt
+ - description: Channel 3 interrupt
+ - description: Channel 4 interrupt
+ - description: Channel 5 interrupt
+ - description: Channel 6 interrupt
+ - description: Channel 7 interrupt
+ - items:
+ - description: Combined interrupt shared by all channels
"#dma-cells":
const: 1
--
2.34.1
^ permalink raw reply related
* [PATCH v5 3/3] arm64: dts: cix: add DT nodes for DMA
From: Jun Guo @ 2026-03-24 12:01 UTC (permalink / raw)
To: peter.chen, fugang.duan, robh, krzk+dt, conor+dt, vkoul, ychuang3,
schung, robin.murphy, Frank.Li
Cc: dmaengine, devicetree, linux-kernel, cix-kernel-upstream,
linux-arm-kernel, Jun Guo
In-Reply-To: <20260324120113.3681830-1-jun.guo@cixtech.com>
Add the device tree node for the dma controller of the CIX SKY1 SoC.
Signed-off-by: Jun Guo <jun.guo@cixtech.com>
---
arch/arm64/boot/dts/cix/sky1.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi
index 210739beac6d..124a29147c6c 100644
--- a/arch/arm64/boot/dts/cix/sky1.dtsi
+++ b/arch/arm64/boot/dts/cix/sky1.dtsi
@@ -480,6 +480,13 @@ iomuxc: pinctrl@4170000 {
reg = <0x0 0x04170000 0x0 0x1000>;
};
+ fch_dmac: dma-controller@4190000 {
+ compatible = "arm,dma-350";
+ reg = <0x0 0x4190000 0x0 0x10000>;
+ interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH 0>;
+ #dma-cells = <1>;
+ };
+
mbox_ap2se: mailbox@5060000 {
compatible = "cix,sky1-mbox";
reg = <0x0 0x05060000 0x0 0x10000>;
--
2.34.1
^ permalink raw reply related
* [PATCH v5 2/3] dma: arm-dma350: support combined IRQ mode with runtime IRQ topology detection
From: Jun Guo @ 2026-03-24 12:01 UTC (permalink / raw)
To: peter.chen, fugang.duan, robh, krzk+dt, conor+dt, vkoul, ychuang3,
schung, robin.murphy, Frank.Li
Cc: dmaengine, devicetree, linux-kernel, cix-kernel-upstream,
linux-arm-kernel, Jun Guo
In-Reply-To: <20260324120113.3681830-1-jun.guo@cixtech.com>
DMA-350 can be integrated with either per-channel IRQ lines or a single
combined IRQ line. Add support for both layouts in a unified way.
Detect IRQ topology at probe time via platform_irq_count(), then:
- request one global IRQ and enable DMANSECCTRL.INTREN_ANYCHINTR for
combined mode, or
- request per-channel IRQs for channel mode.
Refactor IRQ completion/error handling into a shared channel handler
used by both global and per-channel IRQ paths, and guard against IRQs
arriving without an active descriptor.
Assisted-by: Cursor:GPT-5.3-Codex
Signed-off-by: Jun Guo <jun.guo@cixtech.com>
---
drivers/dma/arm-dma350.c | 164 ++++++++++++++++++++++++++++++++-------
1 file changed, 138 insertions(+), 26 deletions(-)
diff --git a/drivers/dma/arm-dma350.c b/drivers/dma/arm-dma350.c
index 84220fa83029..9e42c34b74bb 100644
--- a/drivers/dma/arm-dma350.c
+++ b/drivers/dma/arm-dma350.c
@@ -14,6 +14,7 @@
#include "virt-dma.h"
#define DMAINFO 0x0f00
+#define DRIVER_NAME "arm-dma350"
#define DMA_BUILDCFG0 0xb0
#define DMA_CFG_DATA_WIDTH GENMASK(18, 16)
@@ -142,6 +143,9 @@
#define LINK_LINKADDR BIT(30)
#define LINK_LINKADDRHI BIT(31)
+/* DMA NONSECURE CONTROL REGISTER */
+#define DMANSECCTRL 0x20c
+#define INTREN_ANYCHINTR_EN BIT(0)
enum ch_ctrl_donetype {
CH_CTRL_DONETYPE_NONE = 0,
@@ -192,6 +196,7 @@ struct d350_chan {
struct d350 {
struct dma_device dma;
+ void __iomem *base;
int nchan;
int nreq;
struct d350_chan channels[] __counted_by(nchan);
@@ -461,18 +466,40 @@ static void d350_issue_pending(struct dma_chan *chan)
spin_unlock_irqrestore(&dch->vc.lock, flags);
}
-static irqreturn_t d350_irq(int irq, void *data)
+static void d350_handle_chan_irq(struct d350_chan *dch, struct device *dev,
+ int chan_id, u32 ch_status)
{
- struct d350_chan *dch = data;
- struct device *dev = dch->vc.chan.device->dev;
- struct virt_dma_desc *vd = &dch->desc->vd;
- u32 ch_status;
+ struct virt_dma_desc *vd;
+ bool intr_done = ch_status & CH_STAT_INTR_DONE;
+ bool intr_err = ch_status & CH_STAT_INTR_ERR;
- ch_status = readl(dch->base + CH_STATUS);
- if (!ch_status)
- return IRQ_NONE;
+ if (!intr_done && !intr_err) {
+ if (chan_id >= 0)
+ dev_warn(dev, "Channel %d unexpected IRQ: 0x%08x\n",
+ chan_id, ch_status);
+ else
+ dev_warn(dev, "Unexpected IRQ source? 0x%08x\n", ch_status);
+ writel_relaxed(ch_status, dch->base + CH_STATUS);
+ return;
+ }
+
+ writel_relaxed(ch_status, dch->base + CH_STATUS);
+
+ spin_lock(&dch->vc.lock);
+ if (!dch->desc) {
+ if (chan_id >= 0)
+ dev_warn(dev,
+ "Channel %d IRQ without active descriptor: 0x%08x\n",
+ chan_id, ch_status);
+ else
+ dev_warn(dev, "IRQ without active descriptor: 0x%08x\n",
+ ch_status);
+ spin_unlock(&dch->vc.lock);
+ return;
+ }
- if (ch_status & CH_STAT_INTR_ERR) {
+ vd = &dch->desc->vd;
+ if (intr_err) {
u32 errinfo = readl_relaxed(dch->base + CH_ERRINFO);
if (errinfo & (CH_ERRINFO_AXIRDPOISERR | CH_ERRINFO_AXIRDRESPERR))
@@ -483,14 +510,10 @@ static irqreturn_t d350_irq(int irq, void *data)
vd->tx_result.result = DMA_TRANS_ABORTED;
vd->tx_result.residue = d350_get_residue(dch);
- } else if (!(ch_status & CH_STAT_INTR_DONE)) {
- dev_warn(dev, "Unexpected IRQ source? 0x%08x\n", ch_status);
}
- writel_relaxed(ch_status, dch->base + CH_STATUS);
- spin_lock(&dch->vc.lock);
vchan_cookie_complete(vd);
- if (ch_status & CH_STAT_INTR_DONE) {
+ if (intr_done) {
dch->status = DMA_COMPLETE;
dch->residue = 0;
d350_start_next(dch);
@@ -499,6 +522,44 @@ static irqreturn_t d350_irq(int irq, void *data)
dch->residue = vd->tx_result.residue;
}
spin_unlock(&dch->vc.lock);
+}
+
+static irqreturn_t d350_global_irq(int irq, void *data)
+{
+ struct d350 *dmac = (struct d350 *)data;
+ irqreturn_t ret = IRQ_NONE;
+ int i;
+
+ (void)irq;
+
+ for (i = 0; i < dmac->nchan; i++) {
+ struct d350_chan *dch = &dmac->channels[i];
+ u32 ch_status;
+
+ ch_status = readl(dch->base + CH_STATUS);
+ if (!ch_status)
+ continue;
+
+ ret = IRQ_HANDLED;
+ d350_handle_chan_irq(dch, dmac->dma.dev, i, ch_status);
+ }
+
+ return ret;
+}
+
+static irqreturn_t d350_channel_irq(int irq, void *data)
+{
+ struct d350_chan *dch = data;
+ struct device *dev = dch->vc.chan.device->dev;
+ u32 ch_status;
+
+ (void)irq;
+
+ ch_status = readl(dch->base + CH_STATUS);
+ if (!ch_status)
+ return IRQ_NONE;
+
+ d350_handle_chan_irq(dch, dev, -1, ch_status);
return IRQ_HANDLED;
}
@@ -506,10 +567,18 @@ static irqreturn_t d350_irq(int irq, void *data)
static int d350_alloc_chan_resources(struct dma_chan *chan)
{
struct d350_chan *dch = to_d350_chan(chan);
- int ret = request_irq(dch->irq, d350_irq, IRQF_SHARED,
- dev_name(&dch->vc.chan.dev->device), dch);
- if (!ret)
- writel_relaxed(CH_INTREN_DONE | CH_INTREN_ERR, dch->base + CH_INTREN);
+ int ret = 0;
+
+ if (dch->irq >= 0) {
+ ret = request_irq(dch->irq, d350_channel_irq, IRQF_SHARED,
+ dev_name(&dch->vc.chan.dev->device), dch);
+ if (ret) {
+ dev_err(chan->device->dev, "Failed to request IRQ %d\n", dch->irq);
+ return ret;
+ }
+ }
+
+ writel_relaxed(CH_INTREN_DONE | CH_INTREN_ERR, dch->base + CH_INTREN);
return ret;
}
@@ -519,18 +588,21 @@ static void d350_free_chan_resources(struct dma_chan *chan)
struct d350_chan *dch = to_d350_chan(chan);
writel_relaxed(0, dch->base + CH_INTREN);
- free_irq(dch->irq, dch);
+ if (dch->irq >= 0) {
+ free_irq(dch->irq, dch);
+ dch->irq = -EINVAL;
+ }
vchan_free_chan_resources(&dch->vc);
}
static int d350_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
- struct d350 *dmac;
+ struct d350 *dmac = NULL;
void __iomem *base;
u32 reg;
- int ret, nchan, dw, aw, r, p;
- bool coherent, memset;
+ int ret, nchan, dw, aw, r, p, irq_count;
+ bool coherent, memset, combined_irq;
base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(base))
@@ -556,6 +628,7 @@ static int d350_probe(struct platform_device *pdev)
return -ENOMEM;
dmac->nchan = nchan;
+ dmac->base = base;
reg = readl_relaxed(base + DMAINFO + DMA_BUILDCFG1);
dmac->nreq = FIELD_GET(DMA_CFG_NUM_TRIGGER_IN, reg);
@@ -582,12 +655,46 @@ static int d350_probe(struct platform_device *pdev)
dmac->dma.device_issue_pending = d350_issue_pending;
INIT_LIST_HEAD(&dmac->dma.channels);
+ irq_count = platform_irq_count(pdev);
+ if (irq_count < 0)
+ return dev_err_probe(dev, irq_count,
+ "Failed to count interrupts\n");
+
+ if (irq_count == 1) {
+ combined_irq = true;
+ } else if (irq_count >= nchan) {
+ combined_irq = false;
+ } else {
+ return dev_err_probe(dev, -EINVAL,
+ "Invalid IRQ count %d for %d channels\n",
+ irq_count, nchan);
+ }
+
+ if (combined_irq) {
+ int host_irq = platform_get_irq(pdev, 0);
+
+ if (host_irq < 0)
+ return dev_err_probe(dev, host_irq,
+ "Failed to get IRQ\n");
+
+ ret = devm_request_irq(&pdev->dev, host_irq, d350_global_irq,
+ IRQF_SHARED, DRIVER_NAME, dmac);
+ if (ret)
+ return dev_err_probe(
+ dev, ret,
+ "Failed to request the combined IRQ %d\n",
+ host_irq);
+ /* Combined Non-Secure Channel Interrupt Enable */
+ writel_relaxed(INTREN_ANYCHINTR_EN, dmac->base + DMANSECCTRL);
+ }
+
/* Would be nice to have per-channel caps for this... */
memset = true;
for (int i = 0; i < nchan; i++) {
struct d350_chan *dch = &dmac->channels[i];
dch->base = base + DMACH(i);
+ dch->irq = -EINVAL;
writel_relaxed(CH_CMD_CLEAR, dch->base + CH_CMD);
reg = readl_relaxed(dch->base + CH_BUILDCFG1);
@@ -595,10 +702,15 @@ static int d350_probe(struct platform_device *pdev)
dev_warn(dev, "No command link support on channel %d\n", i);
continue;
}
- dch->irq = platform_get_irq(pdev, i);
- if (dch->irq < 0)
- return dev_err_probe(dev, dch->irq,
- "Failed to get IRQ for channel %d\n", i);
+
+ if (!combined_irq) {
+ dch->irq = platform_get_irq(pdev, i);
+ if (dch->irq < 0)
+ return dev_err_probe(
+ dev, dch->irq,
+ "Failed to get IRQ for channel %d\n",
+ i);
+ }
dch->has_wrap = FIELD_GET(CH_CFG_HAS_WRAP, reg);
dch->has_trig = FIELD_GET(CH_CFG_HAS_TRIGIN, reg) &
--
2.34.1
^ permalink raw reply related
* [PATCH v5 0/3] dmaengine: arm-dma350: support combined IRQ mode with runtime IRQ topology detection
From: Jun Guo @ 2026-03-24 12:01 UTC (permalink / raw)
To: peter.chen, fugang.duan, robh, krzk+dt, conor+dt, vkoul, ychuang3,
schung, robin.murphy, Frank.Li
Cc: dmaengine, devicetree, linux-kernel, cix-kernel-upstream,
linux-arm-kernel, Jun Guo
DMA-350 can be integrated with either one interrupt per channel or a
single combined interrupt for all channels. This series adds support
for the combined IRQ topology while keeping compatibility with the
per-channel topology.
Patch 1 updates the DT binding to describe both interrupt topologies
(1 combined IRQ or 8 per-channel IRQs).
Patch 2 updates the driver to detect IRQ topology at runtime via
platform_irq_count(), handle both modes in one code path, and enable
DMANSECCTRL.INTREN_ANYCHINTR only in combined IRQ mode.
Patch 3 adds the Sky1 DMA DT node using the combined IRQ topology.
Tested on CIX SKY1 with dmatest:
% echo 2000 > /sys/module/dmatest/parameters/timeout
% echo 1 > /sys/module/dmatest/parameters/iterations
% echo "" > /sys/module/dmatest/parameters/channel
% echo 1 > /sys/module/dmatest/parameters/run
Changes in v5:
- Fix the formatting issue in the AI tag.
- Remove the unnecessary "cix,sky1-dma-350".
Changes in v4:
- Reword binding text to align with kernel style.
- Revise the AI attribution to the standard format.
- Remove redundant links from the commit log.
Changes in v3:
- Rework binding compatible description to match generic-first model.
- Keep interrupts schema support for both 1-IRQ and 8-IRQ topologies.
- Drop SoC match-data dependency for IRQ mode selection.
- Detect IRQ topology via platform_irq_count() in probe path.
- Refactor IRQ handling into a shared channel handler.
- Enable DMANSECCTRL.INTREN_ANYCHINTR only in combined IRQ mode.
Changes in v2:
- Update to kernel standards, enhance patch description, and refactor
driver to use match data for hardware differentiation instead of
compatible strings.
Jun Guo (3):
dt-bindings: dma: arm-dma350: document combined and per-channel IRQ
topologies
dma: arm-dma350: support combined IRQ mode with runtime IRQ topology
detection
arm64: dts: cix: add DT nodes for DMA
.../devicetree/bindings/dma/arm,dma-350.yaml | 25 ++-
arch/arm64/boot/dts/cix/sky1.dtsi | 7 +
drivers/dma/arm-dma350.c | 164 +++++++++++++++---
3 files changed, 161 insertions(+), 35 deletions(-)
--
2.34.1
^ permalink raw reply
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