* [PATCH net-next 07/15] net: stmmac: qcom-ethqos: move two more RGMII_IO_MACRO_CONFIG2 out
From: Russell King (Oracle) @ 2026-03-24 13:12 UTC (permalink / raw)
To: Andrew Lunn
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, linux-arm-kernel, linux-arm-msm, linux-stm32,
Mohd Ayaan Anwar, netdev, Paolo Abeni
In-Reply-To: <acKNcX5PqtWYf8m3@shell.armlinux.org.uk>
RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL is always cleared, and
RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN is always updated with the phase
shift in each path through the switch, so these are independent of
the speed. Move them out.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
.../stmicro/stmmac/dwmac-qcom-ethqos.c | 18 +++++-------------
1 file changed, 5 insertions(+), 13 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
index 87af44dcef5a..84db57b3d7cb 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
@@ -420,13 +420,13 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos, int speed)
RGMII_IO_MACRO_CONFIG);
}
+ rgmii_clrmask(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
+ RGMII_IO_MACRO_CONFIG2);
+ rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN, phase_shift,
+ RGMII_IO_MACRO_CONFIG2);
+
switch (speed) {
case SPEED_1000:
- rgmii_clrmask(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
- RGMII_IO_MACRO_CONFIG2);
-
- rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
- phase_shift, RGMII_IO_MACRO_CONFIG2);
rgmii_clrmask(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
RGMII_IO_MACRO_CONFIG2);
rgmii_setmask(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
@@ -453,10 +453,6 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos, int speed)
break;
case SPEED_100:
- rgmii_clrmask(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
- RGMII_IO_MACRO_CONFIG2);
- rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
- phase_shift, RGMII_IO_MACRO_CONFIG2);
rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_2,
FIELD_PREP(RGMII_CONFIG_MAX_SPD_PRG_2, 1),
RGMII_IO_MACRO_CONFIG);
@@ -483,10 +479,6 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos, int speed)
break;
case SPEED_10:
- rgmii_clrmask(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
- RGMII_IO_MACRO_CONFIG2);
- rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
- phase_shift, RGMII_IO_MACRO_CONFIG2);
rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_9,
FIELD_PREP(RGMII_CONFIG_MAX_SPD_PRG_9, 19),
RGMII_IO_MACRO_CONFIG);
--
2.47.3
^ permalink raw reply related
* [PATCH net-next 06/15] net: stmmac: qcom-ethqos: move 1G vs 100M/10M RGMII settings
From: Russell King (Oracle) @ 2026-03-24 13:11 UTC (permalink / raw)
To: Andrew Lunn
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, linux-arm-kernel, linux-arm-msm, linux-stm32,
Mohd Ayaan Anwar, netdev, Paolo Abeni
In-Reply-To: <acKNcX5PqtWYf8m3@shell.armlinux.org.uk>
Move RGMII_CONFIG_BYPASS_TX_ID_EN, RGMII_CONFIG_POS_NEG_DATA_SEL and
RGMII_CONFIG_PROG_SWAP. There are two states for these: one group for
1G, and the logical inversion for 100M and 10M. Move this out of the
switch into an if-else clause.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
.../stmicro/stmmac/dwmac-qcom-ethqos.c | 26 +++++++++----------
1 file changed, 12 insertions(+), 14 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
index 3540471ff272..87af44dcef5a 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
@@ -404,14 +404,24 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos, int speed)
rgmii_setmask(ethqos, RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG);
- switch (speed) {
- case SPEED_1000:
+ if (speed == SPEED_1000) {
rgmii_clrmask(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
RGMII_IO_MACRO_CONFIG);
rgmii_setmask(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
RGMII_IO_MACRO_CONFIG);
rgmii_setmask(ethqos, RGMII_CONFIG_PROG_SWAP,
RGMII_IO_MACRO_CONFIG);
+ } else {
+ rgmii_setmask(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
+ RGMII_IO_MACRO_CONFIG);
+ rgmii_clrmask(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
+ RGMII_IO_MACRO_CONFIG);
+ rgmii_clrmask(ethqos, RGMII_CONFIG_PROG_SWAP,
+ RGMII_IO_MACRO_CONFIG);
+ }
+
+ switch (speed) {
+ case SPEED_1000:
rgmii_clrmask(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
RGMII_IO_MACRO_CONFIG2);
@@ -443,12 +453,6 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos, int speed)
break;
case SPEED_100:
- rgmii_setmask(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
- RGMII_IO_MACRO_CONFIG);
- rgmii_clrmask(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
- RGMII_IO_MACRO_CONFIG);
- rgmii_clrmask(ethqos, RGMII_CONFIG_PROG_SWAP,
- RGMII_IO_MACRO_CONFIG);
rgmii_clrmask(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
RGMII_IO_MACRO_CONFIG2);
rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
@@ -479,12 +483,6 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos, int speed)
break;
case SPEED_10:
- rgmii_setmask(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
- RGMII_IO_MACRO_CONFIG);
- rgmii_clrmask(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
- RGMII_IO_MACRO_CONFIG);
- rgmii_clrmask(ethqos, RGMII_CONFIG_PROG_SWAP,
- RGMII_IO_MACRO_CONFIG);
rgmii_clrmask(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
RGMII_IO_MACRO_CONFIG2);
rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
--
2.47.3
^ permalink raw reply related
* [PATCH net-next 05/15] net: stmmac: qcom-ethqos: move RGMII_CONFIG_DDR_MODE
From: Russell King (Oracle) @ 2026-03-24 13:11 UTC (permalink / raw)
To: Andrew Lunn
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, linux-arm-kernel, linux-arm-msm, linux-stm32,
Mohd Ayaan Anwar, netdev, Paolo Abeni
In-Reply-To: <acKNcX5PqtWYf8m3@shell.armlinux.org.uk>
RGMII_CONFIG_DDR_MODE is always set irrespective of the speed. Move
this out of the switch.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
index 7e389db40e8b..3540471ff272 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
@@ -402,10 +402,10 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos, int speed)
return -EINVAL;
}
+ rgmii_setmask(ethqos, RGMII_CONFIG_DDR_MODE, RGMII_IO_MACRO_CONFIG);
+
switch (speed) {
case SPEED_1000:
- rgmii_setmask(ethqos, RGMII_CONFIG_DDR_MODE,
- RGMII_IO_MACRO_CONFIG);
rgmii_clrmask(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
RGMII_IO_MACRO_CONFIG);
rgmii_setmask(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
@@ -443,8 +443,6 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos, int speed)
break;
case SPEED_100:
- rgmii_setmask(ethqos, RGMII_CONFIG_DDR_MODE,
- RGMII_IO_MACRO_CONFIG);
rgmii_setmask(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
RGMII_IO_MACRO_CONFIG);
rgmii_clrmask(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
@@ -481,8 +479,6 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos, int speed)
break;
case SPEED_10:
- rgmii_setmask(ethqos, RGMII_CONFIG_DDR_MODE,
- RGMII_IO_MACRO_CONFIG);
rgmii_setmask(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
RGMII_IO_MACRO_CONFIG);
rgmii_clrmask(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
--
2.47.3
^ permalink raw reply related
* [PATCH net-next 04/15] net: stmmac: qcom-ethqos: move detection of invalid RGMII speed
From: Russell King (Oracle) @ 2026-03-24 13:11 UTC (permalink / raw)
To: Andrew Lunn
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, linux-arm-kernel, linux-arm-msm, linux-stm32,
Mohd Ayaan Anwar, netdev, Paolo Abeni
In-Reply-To: <acKNcX5PqtWYf8m3@shell.armlinux.org.uk>
Move detection of invalid RGMII speeds (which will never be triggered)
before the switch() to allow register modifications that are common to
all speeds to be moved out of the switch.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
index 84f713ec8c28..7e389db40e8b 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
@@ -397,6 +397,11 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos, int speed)
/* Select RGMII, write 0 to interface select */
rgmii_clrmask(ethqos, RGMII_CONFIG_INTF_SEL, RGMII_IO_MACRO_CONFIG);
+ if (speed != SPEED_1000 && speed != SPEED_100 && speed != SPEED_10) {
+ dev_err(dev, "Invalid speed %d\n", speed);
+ return -EINVAL;
+ }
+
switch (speed) {
case SPEED_1000:
rgmii_setmask(ethqos, RGMII_CONFIG_DDR_MODE,
@@ -510,9 +515,6 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos, int speed)
rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
loopback, RGMII_IO_MACRO_CONFIG);
break;
- default:
- dev_err(dev, "Invalid speed %d\n", speed);
- return -EINVAL;
}
return 0;
--
2.47.3
^ permalink raw reply related
* [PATCH net-next 03/15] net: stmmac: qcom-ethqos: eliminate configure_func
From: Russell King (Oracle) @ 2026-03-24 13:11 UTC (permalink / raw)
To: Andrew Lunn
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, linux-arm-kernel, linux-arm-msm, linux-stm32,
Mohd Ayaan Anwar, netdev, Paolo Abeni
In-Reply-To: <acKNcX5PqtWYf8m3@shell.armlinux.org.uk>
Since ethqos_fix_mac_speed() is called via a function pointer, and only
indirects via the configure_func function pointer, eliminate this
unnecessary indirection.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
.../stmicro/stmmac/dwmac-qcom-ethqos.c | 33 ++++++++-----------
1 file changed, 14 insertions(+), 19 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
index b9cfcf32cebc..84f713ec8c28 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
@@ -100,9 +100,6 @@ struct ethqos_emac_driver_data {
struct qcom_ethqos {
struct platform_device *pdev;
void __iomem *rgmii_base;
- void (*configure_func)(struct qcom_ethqos *ethqos,
- phy_interface_t interface, int speed);
-
struct clk *link_clk;
struct phy *serdes_phy;
phy_interface_t phy_mode;
@@ -521,13 +518,17 @@ static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos, int speed)
return 0;
}
-static void ethqos_configure_rgmii(struct qcom_ethqos *ethqos,
- phy_interface_t interface, int speed)
+static void ethqos_fix_mac_speed_rgmii(void *bsp_priv,
+ phy_interface_t interface, int speed,
+ unsigned int mode)
{
- struct device *dev = ðqos->pdev->dev;
+ struct qcom_ethqos *ethqos = bsp_priv;
+ struct device *dev;
unsigned int i;
u32 val;
+ dev = ðqos->pdev->dev;
+
/* Reset to POR values and enable clk */
for (i = 0; i < ethqos->num_rgmii_por; i++)
rgmii_writel(ethqos, ethqos->rgmii_por[i].value,
@@ -601,9 +602,12 @@ static void ethqos_pcs_set_inband(struct qcom_ethqos *ethqos, bool enable)
/* On interface toggle MAC registers gets reset.
* Configure MAC block for SGMII on ethernet phy link up
*/
-static void ethqos_configure_sgmii(struct qcom_ethqos *ethqos,
- phy_interface_t interface, int speed)
+static void ethqos_fix_mac_speed_sgmii(void *bsp_priv,
+ phy_interface_t interface, int speed,
+ unsigned int mode)
{
+ struct qcom_ethqos *ethqos = bsp_priv;
+
switch (speed) {
case SPEED_2500:
case SPEED_1000:
@@ -623,14 +627,6 @@ static void ethqos_configure_sgmii(struct qcom_ethqos *ethqos,
ethqos_pcs_set_inband(ethqos, interface == PHY_INTERFACE_MODE_SGMII);
}
-static void ethqos_fix_mac_speed(void *priv, phy_interface_t interface,
- int speed, unsigned int mode)
-{
- struct qcom_ethqos *ethqos = priv;
-
- ethqos->configure_func(ethqos, interface, speed);
-}
-
static int qcom_ethqos_serdes_powerup(struct net_device *ndev, void *priv)
{
struct qcom_ethqos *ethqos = priv;
@@ -753,11 +749,11 @@ static int qcom_ethqos_probe(struct platform_device *pdev)
case PHY_INTERFACE_MODE_RGMII_ID:
case PHY_INTERFACE_MODE_RGMII_RXID:
case PHY_INTERFACE_MODE_RGMII_TXID:
- ethqos->configure_func = ethqos_configure_rgmii;
+ plat_dat->fix_mac_speed = ethqos_fix_mac_speed_rgmii;
break;
case PHY_INTERFACE_MODE_2500BASEX:
case PHY_INTERFACE_MODE_SGMII:
- ethqos->configure_func = ethqos_configure_sgmii;
+ plat_dat->fix_mac_speed = ethqos_fix_mac_speed_sgmii;
plat_dat->mac_finish = ethqos_mac_finish_serdes;
break;
default:
@@ -805,7 +801,6 @@ static int qcom_ethqos_probe(struct platform_device *pdev)
plat_dat->bsp_priv = ethqos;
plat_dat->set_clk_tx_rate = ethqos_set_clk_tx_rate;
- plat_dat->fix_mac_speed = ethqos_fix_mac_speed;
plat_dat->dump_debug_regs = rgmii_dump;
plat_dat->ptp_clk_freq_config = ethqos_ptp_clk_freq_config;
plat_dat->core_type = DWMAC_CORE_GMAC4;
--
2.47.3
^ permalink raw reply related
* [PATCH net-next 02/15] net: stmmac: qcom-ethqos: pass ethqos to ethqos_pcs_set_inband()
From: Russell King (Oracle) @ 2026-03-24 13:11 UTC (permalink / raw)
To: Andrew Lunn
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, linux-arm-kernel, linux-arm-msm, linux-stm32,
Mohd Ayaan Anwar, netdev, Paolo Abeni
In-Reply-To: <acKNcX5PqtWYf8m3@shell.armlinux.org.uk>
Rather than geting the stmmac_priv pointer in ethqos_configure_sgmii(),
move it into ethqos_pcs_set_inband() and pass the struct qcom_ethqos
pointer instead.
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
.../net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
index 502f2b184a87..b9cfcf32cebc 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
@@ -590,8 +590,11 @@ static void ethqos_configure_rgmii(struct qcom_ethqos *ethqos,
ethqos_rgmii_macro_init(ethqos, speed);
}
-static void ethqos_pcs_set_inband(struct stmmac_priv *priv, bool enable)
+static void ethqos_pcs_set_inband(struct qcom_ethqos *ethqos, bool enable)
{
+ struct net_device *dev = platform_get_drvdata(ethqos->pdev);
+ struct stmmac_priv *priv = netdev_priv(dev);
+
stmmac_pcs_ctrl_ane(priv, enable, 0);
}
@@ -601,9 +604,6 @@ static void ethqos_pcs_set_inband(struct stmmac_priv *priv, bool enable)
static void ethqos_configure_sgmii(struct qcom_ethqos *ethqos,
phy_interface_t interface, int speed)
{
- struct net_device *dev = platform_get_drvdata(ethqos->pdev);
- struct stmmac_priv *priv = netdev_priv(dev);
-
switch (speed) {
case SPEED_2500:
case SPEED_1000:
@@ -620,7 +620,7 @@ static void ethqos_configure_sgmii(struct qcom_ethqos *ethqos,
break;
}
- ethqos_pcs_set_inband(priv, interface == PHY_INTERFACE_MODE_SGMII);
+ ethqos_pcs_set_inband(ethqos, interface == PHY_INTERFACE_MODE_SGMII);
}
static void ethqos_fix_mac_speed(void *priv, phy_interface_t interface,
--
2.47.3
^ permalink raw reply related
* [PATCH net-next 01/15] net: stmmac: qcom-ethqos: remove ethqos_configure()
From: Russell King (Oracle) @ 2026-03-24 13:11 UTC (permalink / raw)
To: Andrew Lunn
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, linux-arm-kernel, linux-arm-msm, linux-stm32,
Mohd Ayaan Anwar, netdev, Paolo Abeni
In-Reply-To: <acKNcX5PqtWYf8m3@shell.armlinux.org.uk>
ethqos_configure() does nothing more than indirect via
ethqos->configure_func, and is only called from ethqos_fix_mac_speed()
just below. Move the indirect call into ethqos_fix_mac_speed().
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
---
drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 8 +-------
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
index 3ccf20fdf52a..502f2b184a87 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c
@@ -623,18 +623,12 @@ static void ethqos_configure_sgmii(struct qcom_ethqos *ethqos,
ethqos_pcs_set_inband(priv, interface == PHY_INTERFACE_MODE_SGMII);
}
-static void ethqos_configure(struct qcom_ethqos *ethqos,
- phy_interface_t interface, int speed)
-{
- return ethqos->configure_func(ethqos, interface, speed);
-}
-
static void ethqos_fix_mac_speed(void *priv, phy_interface_t interface,
int speed, unsigned int mode)
{
struct qcom_ethqos *ethqos = priv;
- ethqos_configure(ethqos, interface, speed);
+ ethqos->configure_func(ethqos, interface, speed);
}
static int qcom_ethqos_serdes_powerup(struct net_device *ndev, void *priv)
--
2.47.3
^ permalink raw reply related
* [PATCH net-next 00/15] net: stmmac: qcom-ethqos: more cleanups
From: Russell King (Oracle) @ 2026-03-24 13:11 UTC (permalink / raw)
To: Andrew Lunn
Cc: Alexandre Torgue, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, linux-arm-kernel, linux-arm-msm, linux-stm32,
Mohd Ayaan Anwar, netdev, Paolo Abeni
Further cleanups to qcom-ethqos, mainly concentrating on the RGMII
code, making it clearer what the differences are for each speed, thus
making the code more readable.
I'm still not really happy with this. The speed specific configuration
remains split between ethqos_fix_mac_speed_rgmii() and
ethqos_rgmii_macro_init(), where the latter is only ever called from
the former. So, I think further work is needed here - maybe it needs
restructuring into the various componenet parts of the RGMII block?
.../ethernet/stmicro/stmmac/dwmac-qcom-ethqos.c | 218 ++++++++-------------
1 file changed, 86 insertions(+), 132 deletions(-)
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
^ permalink raw reply
* Re: [PATCH v6 0/7] gpio: introduce a GPIO driver for SCMI
From: Linus Walleij @ 2026-03-24 13:10 UTC (permalink / raw)
To: Dan Carpenter
Cc: AKASHI Takahiro, arm-scmi, Bartosz Golaszewski, Conor Dooley,
Cristian Marussi, devicetree, Krzysztof Kozlowski,
linux-arm-kernel, linux-gpio, linux-kernel, Rob Herring,
Sudeep Holla, Andy Shevchenko, Bartosz Golaszewski,
Vincent Guittot, Khaled Ali Ahmed, Michal Simek
In-Reply-To: <cover.1774283146.git.dan.carpenter@linaro.org>
On Mon, Mar 23, 2026 at 8:01 PM Dan Carpenter <dan.carpenter@linaro.org> wrote:
> This basically abandons my earlier attempts and goes back to Takahiro
> Akashi's driver. Here is the link to Takahiro's patchset:
>
> https://lore.kernel.org/all/20231005025843.508689-1-takahiro.akashi@linaro.org/
>
> v6: Fix a build error when CONFIG_PINCONF is disabled
> Fix the dt-binding subject and my email address
> Use pinconf_to_config_packed() instead of PIN_CONF_PACKED()
v6 applied to this immutable branch:
https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git/log/?h=ib-scmi-pinctrl-gpio
Then merged into my devel branch for next.
Bartosz, you might want to pull it in!
Dan: thanks for your efforts to fix up the remaining hurdles and
bringing this to completion! Sometimes the last few % of work are
the hardest.
Also thanks to Takahiro for this idea: it worked out just like you
imagined.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH v2] net: stmmac: skip VLAN restore when VLAN hash ops are missing
From: Russell King (Oracle) @ 2026-03-24 13:04 UTC (permalink / raw)
To: Paolo Abeni, Ovidiu Panait
Cc: Michal Piekos, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Maxime Coquelin, Alexandre Torgue, netdev,
linux-stm32, linux-arm-kernel, linux-kernel
In-Reply-To: <5e5706bb-0f04-4bb1-94f4-45083a3c76fd@redhat.com>
On Tue, Mar 24, 2026 at 01:14:29PM +0100, Paolo Abeni wrote:
> On 3/21/26 6:38 AM, Michal Piekos wrote:
> > stmmac_vlan_restore() unconditionally calls stmmac_vlan_update() when
> > NETIF_F_VLAN_FEATURES is set. On platforms where priv->hw->vlan (or
> > ->update_vlan_hash) is not provided, stmmac_update_vlan_hash() returns
> > -EINVAL via stmmac_do_void_callback(), resulting in a spurious
> > "Failed to restore VLANs" error even when no VLAN filtering is in use.
> >
> > Check presence of VLAN HW FILTER flags before stmmac_vlan_update().
> >
> > Tested on Orange Pi Zero 3.
> >
> > Fixes: bd7ad51253a7 ("net: stmmac: Fix VLAN HW state restore")
> > Signed-off-by: Michal Piekos <michal.piekos@mmpsystems.pl>
> > ---
> > This patch fixes a noisy "Failed to restore VLANs" message on platforms
> > where stmmac VLAN hash ops are not implemented.
> > stmmac_vlan_restore() calls stmmac_vlan_update() without checking for
> > VLAN hash ops presence which results in -EINVAL.
> > ---
> > Changes in v2:
> > - Replace check for hash ops with check for HW FILTER flags
> > - Link to v1: https://lore.kernel.org/r/20260314-vlan-restore-error-v1-1-4fc6c3e2115f@mmpsystems.pl
> > ---
> > drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> > index 6827c99bde8c..cfc0ce9cec9c 100644
> > --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> > +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> > @@ -6863,7 +6863,8 @@ static int stmmac_vlan_restore(struct stmmac_priv *priv)
> > {
> > int ret;
> >
> > - if (!(priv->dev->features & NETIF_F_VLAN_FEATURES))
> > + if (!(priv->dev->features &
> > + (NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_STAG_FILTER)))
> > return 0;
> >
> > if (priv->hw->num_vlan)
> Adding Russell.
>
> It's not obvious to me that with this change the
> restore_hw_vlan_rx_fltr() and vlan_update() callback are still invoked
> in all the relevant driver/features permutation.
I think there's a few questions here.
When CONFIG_VLAN_8021Q is enabled, then we set the filter features
if the vlhash dma capability is set:
if (priv->dma_cap.vlhash) {
ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
ndev->features |= NETIF_F_HW_VLAN_STAG_FILTER;
}
Only dwmac4 and dwxgmac2 have the ability to set this feature (and
thus be synthesised with the feature enabled.) From what I understand,
when present, these features are permanently enabled (as they're not
set in hw_Features).
However, in stmmac_vlan_update() there is:
if (!priv->dma_cap.vlhash) {
if (count > 2) /* VID = 0 always passes filter */
return -EOPNOTSUPP;
pmatch = vid;
hash = 0;
}
So, it is clear that the intention is that stmmac_vlan_update() will
be called even when the NETIF_F_HW_VLAN_*TAG_FILTER features are not
present - consider a core that implements the VLAN ops, but has
priv->dma_cap.vlhash false.
It looks like vlan support was added in dwmac v4.0 and later cores
(from the hwif table.) As the vlan ops are NULL before that, the
horrid stmmac_do_void_callback() crud will return -EINVAL (yuck). The
method it calls is a void function, so the only possible return values
are zero if implemented, or -EINVAL if not.
stmmac_vlan_update() itself only ever returns zero if the netif
isn't running, or the above return value. So, an error returned from
stmmac_vlan_update() just means that the driver has no support for
programming the vlan configuration.
Looking at the implementations for the case where vlhash is false,
(where stmmac_update_vlan_hash() will be called with hash=0 and
perfect_match with a vid, vlan_update_hash() still write
to the VLAN_TAG register to configure vlan handling. I haven't
looked up exactly what it does.
The other possibility is dwxgmac2_update_vlan_hash(). This looks
similar.
So, I don't think that the correct solution is to only call this
function when one or more of NETIF_F_HW_VLAN_*TAG_FILTER feature flags
are set - clearly the code is written to handle the case where the
update_vlan_hash method is populated but vlhash is false and these
feature flags are clear.
Now I'm wondering whether the code in the STMMAC_VLAN_TAG_USED block
is correct:
/* Both mac100 and gmac support receive VLAN tag detection */
ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX;
if (dwmac_is_xmac(priv->plat->core_type)) {
ndev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
priv->hw->hw_vlan_en = true;
}
if (priv->dma_cap.vlhash) {
ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
ndev->features |= NETIF_F_HW_VLAN_STAG_FILTER;
}
if (priv->dma_cap.vlins)
ndev->features |= NETIF_F_HW_VLAN_CTAG_TX;
The test for dwmac_is_xmac() matches for dwmac4 and dwxgmac cores. If
this is true, then we will have the vlan ops populated, and it means
that NETIF_F_HW_VLAN_CTAG_RX can be configured by the user rather than
being always-enabled. Is this correct? I'm not sure - I haven't dug
into enough of the documentation for this yet. However, I suggest
that we need to always call stmmac_update_vlan_hash() for these cores.
So, I'm coming to the conclusion that we either need a test for
dwmac_is_xmac() and not the feature flags, or maybe we just get rid
of the "Failed to restore VLANs" error print and make
stmmac_vlan_restore() return void (nothing uses the return value.)
In summary, I'm not sure what the correct approach is - please reach
out to Ovidiu Panait <ovidiu.panait.rb@renesas.com> who recently added
this code, but I'm fairly sure that this solution is incorrect.
Really, Ovidiu Panait should be reviewing this patch as his recent
change introduced the problematical error print.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!
^ permalink raw reply
* Re: [PATCH v4 2/3] dma: arm-dma350: support combined IRQ mode with runtime IRQ topology detection
From: Robin Murphy @ 2026-03-24 12:59 UTC (permalink / raw)
To: Jun Guo, peter.chen, fugang.duan, robh, krzk+dt, conor+dt, vkoul,
ychuang3, schung, Frank.Li
Cc: dmaengine, devicetree, linux-kernel, cix-kernel-upstream,
linux-arm-kernel
In-Reply-To: <20260323114822.1925869-3-jun.guo@cixtech.com>
On 2026-03-23 11:48 am, Jun Guo wrote:
> DMA-350 can be integrated with either per-channel IRQ lines or a single
> combined IRQ line. Add support for both layouts in a unified way.
>
> Detect IRQ topology at probe time via platform_irq_count(), then:
> - request one global IRQ and enable DMANSECCTRL.INTREN_ANYCHINTR for
> combined mode, or
> - request per-channel IRQs for channel mode.
>
> Refactor IRQ completion/error handling into a shared channel handler
> used by both global and per-channel IRQ paths, and guard against IRQs
> arriving without an active descriptor.
>
> Assisted-by: Cursor: GPT-5.3-Codex
> Signed-off-by: Jun Guo <jun.guo@cixtech.com>
> ---
> drivers/dma/arm-dma350.c | 165 +++++++++++++++++++++++++++++++++------
> 1 file changed, 139 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/dma/arm-dma350.c b/drivers/dma/arm-dma350.c
> index 84220fa83029..2cf6f783b44f 100644
> --- a/drivers/dma/arm-dma350.c
> +++ b/drivers/dma/arm-dma350.c
> @@ -14,6 +14,7 @@
> #include "virt-dma.h"
>
> #define DMAINFO 0x0f00
> +#define DRIVER_NAME "arm-dma350"
Why is this here in the middle of register definitions? But frankly why
is it being added at all?
> #define DMA_BUILDCFG0 0xb0
> #define DMA_CFG_DATA_WIDTH GENMASK(18, 16)
> @@ -142,6 +143,9 @@
> #define LINK_LINKADDR BIT(30)
> #define LINK_LINKADDRHI BIT(31)
>
> +/* DMA NONSECURE CONTROL REGISTER */
> +#define DMANSECCTRL 0x20c
Please follow the existing code rather than making a confusing ugly
mess. DMANSECCTRL is a register frame at offset 0x0200; it contains
(among others) a register named NSEC_CTRL at offset 0x0c.
> +#define INTREN_ANYCHINTR_EN BIT(0)
>
> enum ch_ctrl_donetype {
> CH_CTRL_DONETYPE_NONE = 0,
> @@ -192,6 +196,7 @@ struct d350_chan {
>
> struct d350 {
> struct dma_device dma;
> + void __iomem *base;
Why?
> int nchan;
> int nreq;
> struct d350_chan channels[] __counted_by(nchan);
> @@ -461,18 +466,40 @@ static void d350_issue_pending(struct dma_chan *chan)
> spin_unlock_irqrestore(&dch->vc.lock, flags);
> }
>
> -static irqreturn_t d350_irq(int irq, void *data)
> +static void d350_handle_chan_irq(struct d350_chan *dch, struct device *dev,
> + int chan_id, u32 ch_status)
> {
> - struct d350_chan *dch = data;
> - struct device *dev = dch->vc.chan.device->dev;
> - struct virt_dma_desc *vd = &dch->desc->vd;
> - u32 ch_status;
> + struct virt_dma_desc *vd;
> + bool intr_done = ch_status & CH_STAT_INTR_DONE;
> + bool intr_err = ch_status & CH_STAT_INTR_ERR;
>
> - ch_status = readl(dch->base + CH_STATUS);
> - if (!ch_status)
> - return IRQ_NONE;
> + if (!intr_done && !intr_err) {
Why is the logic being changed here?
> + if (chan_id >= 0)
> + dev_warn(dev, "Channel %d unexpected IRQ: 0x%08x\n",
> + chan_id, ch_status);
Why? I see no reason why "dev" shouldn't still be the channel device.
> + else
> + dev_warn(dev, "Unexpected IRQ source? 0x%08x\n", ch_status);
> + writel_relaxed(ch_status, dch->base + CH_STATUS);
> + return;
> + }
> +
> + writel_relaxed(ch_status, dch->base + CH_STATUS);
> +
> + spin_lock(&dch->vc.lock);
> + if (!dch->desc) {
> + if (chan_id >= 0)
> + dev_warn(dev,
> + "Channel %d IRQ without active descriptor: 0x%08x\n",
> + chan_id, ch_status);
> + else
> + dev_warn(dev, "IRQ without active descriptor: 0x%08x\n",
> + ch_status);
> + spin_unlock(&dch->vc.lock);
> + return;
> + }
This seems entirely new and nothing to do with refactoring. Why do you
think it's necessary?
> - if (ch_status & CH_STAT_INTR_ERR) {
> + vd = &dch->desc->vd;
> + if (intr_err) {
> u32 errinfo = readl_relaxed(dch->base + CH_ERRINFO);
>
> if (errinfo & (CH_ERRINFO_AXIRDPOISERR | CH_ERRINFO_AXIRDRESPERR))
> @@ -483,14 +510,10 @@ static irqreturn_t d350_irq(int irq, void *data)
> vd->tx_result.result = DMA_TRANS_ABORTED;
>
> vd->tx_result.residue = d350_get_residue(dch);
> - } else if (!(ch_status & CH_STAT_INTR_DONE)) {
> - dev_warn(dev, "Unexpected IRQ source? 0x%08x\n", ch_status);
> }
> - writel_relaxed(ch_status, dch->base + CH_STATUS);
>
> - spin_lock(&dch->vc.lock);
I can't recall the details off-hand right now, but I have a strong
feeling the order of operations here was reasonably significant - what's
the justifcation for changing it?
> vchan_cookie_complete(vd);
> - if (ch_status & CH_STAT_INTR_DONE) {
> + if (intr_done) {
> dch->status = DMA_COMPLETE;
> dch->residue = 0;
> d350_start_next(dch);
> @@ -499,6 +522,44 @@ static irqreturn_t d350_irq(int irq, void *data)
> dch->residue = vd->tx_result.residue;
> }
> spin_unlock(&dch->vc.lock);
> +}
> +
> +static irqreturn_t d350_global_irq(int irq, void *data)
> +{
> + struct d350 *dmac = (struct d350 *)data;
This isn't C++
> + irqreturn_t ret = IRQ_NONE;
> + int i;
> +
> + (void)irq;
Why?
> + for (i = 0; i < dmac->nchan; i++) {
> + struct d350_chan *dch = &dmac->channels[i];
> + u32 ch_status;
> +
> + ch_status = readl(dch->base + CH_STATUS);
> + if (!ch_status)
Why is this factored out, only to be duplicated in both callers?
> + continue;
> +
> + ret = IRQ_HANDLED;
> + d350_handle_chan_irq(dch, dmac->dma.dev, i, ch_status);
> + }
> +
> + return ret;
> +}
> +
> +static irqreturn_t d350_channel_irq(int irq, void *data)
> +{
> + struct d350_chan *dch = data;
> + struct device *dev = dch->vc.chan.device->dev;
> + u32 ch_status;
> +
> + (void)irq;
> +
> + ch_status = readl(dch->base + CH_STATUS);
> + if (!ch_status)
> + return IRQ_NONE;
> +
> + d350_handle_chan_irq(dch, dev, -1, ch_status);
>
> return IRQ_HANDLED;
> }
> @@ -506,10 +567,18 @@ static irqreturn_t d350_irq(int irq, void *data)
> static int d350_alloc_chan_resources(struct dma_chan *chan)
> {
> struct d350_chan *dch = to_d350_chan(chan);
> - int ret = request_irq(dch->irq, d350_irq, IRQF_SHARED,
> - dev_name(&dch->vc.chan.dev->device), dch);
> - if (!ret)
> - writel_relaxed(CH_INTREN_DONE | CH_INTREN_ERR, dch->base + CH_INTREN);
> + int ret = 0;
> +
> + if (dch->irq >= 0) {
> + ret = request_irq(dch->irq, d350_channel_irq, IRQF_SHARED,
> + dev_name(&dch->vc.chan.dev->device), dch);
> + if (ret) {
> + dev_err(chan->device->dev, "Failed to request IRQ %d\n", dch->irq);
> + return ret;
> + }
> + }
> +
> + writel_relaxed(CH_INTREN_DONE | CH_INTREN_ERR, dch->base + CH_INTREN);
>
> return ret;
> }
> @@ -519,18 +588,21 @@ static void d350_free_chan_resources(struct dma_chan *chan)
> struct d350_chan *dch = to_d350_chan(chan);
>
> writel_relaxed(0, dch->base + CH_INTREN);
> - free_irq(dch->irq, dch);
> + if (dch->irq >= 0) {
> + free_irq(dch->irq, dch);
> + dch->irq = -EINVAL;
> + }
> vchan_free_chan_resources(&dch->vc);
> }
>
> static int d350_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> - struct d350 *dmac;
> + struct d350 *dmac = NULL;
Why?
> void __iomem *base;
> u32 reg;
> - int ret, nchan, dw, aw, r, p;
> - bool coherent, memset;
> + int ret, nchan, dw, aw, r, p, irq_count;
> + bool coherent, memset, combined_irq;
>
> base = devm_platform_ioremap_resource(pdev, 0);
> if (IS_ERR(base))
> @@ -556,6 +628,7 @@ static int d350_probe(struct platform_device *pdev)
> return -ENOMEM;
>
> dmac->nchan = nchan;
> + dmac->base = base;
>
> reg = readl_relaxed(base + DMAINFO + DMA_BUILDCFG1);
> dmac->nreq = FIELD_GET(DMA_CFG_NUM_TRIGGER_IN, reg);
> @@ -582,12 +655,46 @@ static int d350_probe(struct platform_device *pdev)
> dmac->dma.device_issue_pending = d350_issue_pending;
> INIT_LIST_HEAD(&dmac->dma.channels);
>
> + irq_count = platform_irq_count(pdev);
> + if (irq_count < 0)
> + return dev_err_probe(dev, irq_count,
> + "Failed to count interrupts\n");
> +
> + if (irq_count == 1) {
> + combined_irq = true;
What if there's only 1 channel and it is actually using its dedicated IRQ?
> + } else if (irq_count >= nchan) {
> + combined_irq = false;
> + } else {
> + return dev_err_probe(dev, -EINVAL,
> + "Invalid IRQ count %d for %d channels\n",
> + irq_count, nchan);
Thsi is a change in behaviour, since we wouldm't currently consider it
an error if the last 1 or more channels don't have an interrupt, but
aren't accessible anyway - if a system *always* reserved the last couple
of channels for the Secure world, arguably there would be no real
requiremnt to describe them in the Non-Secure DT at all.
> + }
> +
> + if (combined_irq) {
> + int host_irq = platform_get_irq(pdev, 0);
> +
> + if (host_irq < 0)
> + return dev_err_probe(dev, host_irq,
> + "Failed to get IRQ\n");
> +
> + ret = devm_request_irq(&pdev->dev, host_irq, d350_global_irq,
> + IRQF_SHARED, DRIVER_NAME, dmac);
> + if (ret)
> + return dev_err_probe(
> + dev, ret,
> + "Failed to request the combined IRQ %d\n",
> + host_irq);
> + /* Combined Non-Secure Channel Interrupt Enable */
> + writel_relaxed(INTREN_ANYCHINTR_EN, dmac->base + DMANSECCTRL);
> + }
> +
> /* Would be nice to have per-channel caps for this... */
> memset = true;
> for (int i = 0; i < nchan; i++) {
> struct d350_chan *dch = &dmac->channels[i];
>
> dch->base = base + DMACH(i);
> + dch->irq = -EINVAL;
> writel_relaxed(CH_CMD_CLEAR, dch->base + CH_CMD);
>
> reg = readl_relaxed(dch->base + CH_BUILDCFG1);
> @@ -595,10 +702,15 @@ static int d350_probe(struct platform_device *pdev)
> dev_warn(dev, "No command link support on channel %d\n", i);
> continue;
> }
> - dch->irq = platform_get_irq(pdev, i);
> - if (dch->irq < 0)
> - return dev_err_probe(dev, dch->irq,
> - "Failed to get IRQ for channel %d\n", i);
> +
> + if (!combined_irq) {
> + dch->irq = platform_get_irq(pdev, i);
But here's the thing - even if we *were* to do something special in the
DT binding, why not simply have:
if (combined_irq)
dch->irq = combined_irq_num;
else
dch->irq = platform_get_irq(pdev, i);
at this point, and then let everything else keep working the way it
already does?
Thanks,
Robin.
> + if (dch->irq < 0)
> + return dev_err_probe(
> + dev, dch->irq,
> + "Failed to get IRQ for channel %d\n",
> + i);
> + }
>
> dch->has_wrap = FIELD_GET(CH_CFG_HAS_WRAP, reg);
> dch->has_trig = FIELD_GET(CH_CFG_HAS_TRIGIN, reg) &
> @@ -640,6 +752,7 @@ static void d350_remove(struct platform_device *pdev)
> }
>
> static const struct of_device_id d350_of_match[] __maybe_unused = {
> + { .compatible = "cix,sky1-dma-350" },
> { .compatible = "arm,dma-350" },
> {}
> };
^ permalink raw reply
* [BOOTWRAPPER PATCH v2 2/2] Add support for GICv5
From: Vladimir Murzin @ 2026-03-24 12:59 UTC (permalink / raw)
To: linux-arm-kernel
Cc: vladimir.murzin, mark.rutland, maz, joey.gouly, Sascha.Bischoff
In-Reply-To: <20260324125906.67012-1-vladimir.murzin@arm.com>
Performs the minimal initialization required for GICv5 support. GICv5
support can be requested with --with-gic=v5.
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
---
Makefile.am | 7 ++
arch/aarch64/include/asm/cpu.h | 11 +++
common/gic-v5.c | 134 +++++++++++++++++++++++++++++++++
configure.ac | 7 +-
scripts/FDT.pm | 16 ++++
scripts/findbase-by-regname.pl | 44 +++++++++++
6 files changed, 216 insertions(+), 3 deletions(-)
create mode 100644 common/gic-v5.c
create mode 100755 scripts/findbase-by-regname.pl
diff --git a/Makefile.am b/Makefile.am
index 2710494..aacd639 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -82,6 +82,13 @@ PSCI_NODE :=
CPU_NODES :=
endif
+if GICV5
+GIC_IRS_BASE := $(shell perl -I $(SCRIPT_DIR) $(SCRIPT_DIR)/findbase-by-regname.pl $(KERNEL_DTB) "el3-config" 'arm,gic-v5-irs')
+GIC_IWB_BASE := $(shell perl -I $(SCRIPT_DIR) $(SCRIPT_DIR)/findbase.pl $(KERNEL_DTB) 0 'arm,gic-v5-iwb')
+DEFINES += -DGIC_IRS_BASE=$(GIC_IRS_BASE)
+DEFINES += -DGIC_IWB_BASE=$(GIC_IWB_BASE)
+endif
+
if GICV3
GIC_DIST_BASE := $(shell perl -I $(SCRIPT_DIR) $(SCRIPT_DIR)/findbase.pl $(KERNEL_DTB) 0 'arm,gic-v3')
GIC_RDIST_BASE := $(shell perl -I $(SCRIPT_DIR) $(SCRIPT_DIR)/findbase.pl $(KERNEL_DTB) 1 'arm,gic-v3')
diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h
index ac50474..af4191c 100644
--- a/arch/aarch64/include/asm/cpu.h
+++ b/arch/aarch64/include/asm/cpu.h
@@ -128,6 +128,7 @@
#define ID_AA64PFR1_EL1_THE BITS(51, 48)
#define ID_AA64PFR2_EL1 s3_0_c0_c4_2
+#define ID_AA64PFR2_EL1_GCIE BITS(15, 12)
#define ID_AA64PFR2_EL1_FPMR BITS(35, 32)
#define ID_AA64SMFR0_EL1 s3_0_c0_c4_5
@@ -169,6 +170,11 @@
#define ICC_CTLR_EL3 S3_6_C12_C12_4
#define ICC_PMR_EL1 S3_0_C4_C6_0
+#define ICC_PPI_DOMAINR0_EL3 S3_6_C12_C8_4
+#define ICC_PPI_DOMAINR1_EL3 S3_6_C12_C8_5
+#define ICC_PPI_DOMAINR2_EL3 S3_6_C12_C8_6
+#define ICC_PPI_DOMAINR3_EL3 S3_6_C12_C8_7
+
#define VSTCR_EL2 s3_4_c2_c6_2
#define VSCTLR_EL2 s3_4_c2_c0_0
@@ -245,6 +251,11 @@ static inline int has_gicv3_sysreg(void)
return !!mrs_field(ID_AA64PFR0_EL1, GIC);
}
+static inline int has_gicv5_sysreg(void)
+{
+ return !!mrs_field(ID_AA64PFR2_EL1, GCIE);
+}
+
#endif /* !__ASSEMBLY__ */
#endif
diff --git a/common/gic-v5.c b/common/gic-v5.c
new file mode 100644
index 0000000..cef2ece
--- /dev/null
+++ b/common/gic-v5.c
@@ -0,0 +1,134 @@
+/*
+ * gic-v5.c
+ *
+ * Copyright (C) 2025 ARM Limited. All rights reserved.
+ *
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE.txt file.
+ */
+
+#include <stdint.h>
+
+#include <cpu.h>
+#include <gic.h>
+#include <asm/io.h>
+
+#define IWB_IDR0 0x0
+#define IWB_IDR0_IW_RANGE_SHIFT 0x0
+#define IWB_IDR0_IW_RANGE_MASK 0x7ff
+
+#define IWB_CR0 0x80
+#define IWB_CR0_IWBEN (1 << 0)
+#define IWB_CR0_IDLE (1 << 1)
+
+#define IWB_WENABLE_STATUSR 0xc0
+#define IWB_WENABLE_STATUSR_IDLE (1 << 0)
+
+#define IWB_WDOMAIN_STATUSR 0xc4
+#define IWB_WDOMAIN_STATUSR_IDLE (1 << 0)
+
+#define IWB_WENABLER 0x2000
+#define IWB_WDOMAINR 0x8000
+
+#define IRS_IDR6 0x0018
+#define IRS_IDR6_SPI_IRS_RANGE_MASK 0x1ffffff
+
+#define IRS_IDR7 0x001c
+#define IRS_IDR7_SPI_BASE_MASK 0xffffff
+
+#define IRS_SPI_SELR 0x108
+#define IRS_SPI_DOMAINR 0x10c
+
+#define IRS_SPI_STATUSR 0x0118
+#define IRS_SPI_STATUSR_IDLE (1 << 0)
+
+
+static void gic_iwb_init(void) {
+ void *iwb_ptr = (void *)GIC_IWB_BASE;
+ unsigned int num;
+ unsigned int i;
+
+ /* Get number of implemented wires */
+ num = ((raw_readl(iwb_ptr + IWB_IDR0) >> IWB_IDR0_IW_RANGE_SHIFT) & IWB_IDR0_IW_RANGE_MASK) + 1;
+
+ /* Disable all wires */
+ for (i = 0; i < num; i++)
+ raw_writel(0, iwb_ptr + IWB_WENABLER + i * 4);
+
+
+ while (!(raw_readl(iwb_ptr + IWB_WENABLE_STATUSR) & IWB_WENABLE_STATUSR_IDLE));
+
+ /* Asign all wires to Non-Secure domain */
+ for (i = 0; i < num * 2; i++)
+ raw_writel(0x55555555, iwb_ptr + IWB_WDOMAINR + i * 4);
+
+ while (!(raw_readl(iwb_ptr + IWB_WDOMAIN_STATUSR) & IWB_WDOMAIN_STATUSR_IDLE));
+
+ /* Enable IWB */
+ raw_writel(IWB_CR0_IWBEN, iwb_ptr + IWB_CR0);
+
+ while (!(raw_readl(iwb_ptr + IWB_CR0) & IWB_CR0_IDLE));
+}
+
+static void gic_irs_init(void) {
+ void *irs_ptr = (void *)GIC_IRS_BASE;
+ unsigned int range;
+ unsigned int base;
+ unsigned int i;
+
+ /* Get the range of implemented SPI's ids */
+ base = raw_readl(irs_ptr + IRS_IDR7) & IRS_IDR7_SPI_BASE_MASK;
+ range = raw_readl(irs_ptr + IRS_IDR6) & IRS_IDR6_SPI_IRS_RANGE_MASK;
+
+ for (i = base; i < base + range; i++) {
+ /* Select SPI */
+ raw_writel(i, irs_ptr + IRS_SPI_SELR);
+ while (!(raw_readl(irs_ptr + IRS_SPI_STATUSR) & IRS_SPI_STATUSR_IDLE));
+
+ /* Asign SPI to Non-Secure domain */
+ raw_writel(1, irs_ptr + IRS_SPI_DOMAINR);
+ while (!(raw_readl(irs_ptr + IRS_SPI_STATUSR) & IRS_SPI_STATUSR_IDLE));
+ }
+}
+
+static void gic_ppi_init(void) {
+ uint64_t val = 0;
+
+ val |= 1UL << (2 * 31); // Trace Buffer Unit
+ val |= 1UL << (2 * 30); // EL1 Physical Timer
+ val |= 1UL << (2 * 28); // Non-secure EL2 Virtual Timer
+ val |= 1UL << (2 * 27); // EL1 Virtual Timer
+ val |= 1UL << (2 * 26); // Non-secure EL2 Physical Timer
+ val |= 1UL << (2 * 25); // GIC maintenance interrupt
+ val |= 1UL << (2 * 24); // Generic CTI interrupt trigger event
+ val |= 1UL << (2 * 23); // PMU overflow interrupt request
+ val |= 1UL << (2 * 22); // Debug communication channel
+ val |= 1UL << (2 * 21); // Profiling Buffer management interrupt request
+ val |= 1UL << (2 * 15); // Hardware accelerator for cleaning Dirty state interrupt
+ val |= 1UL << (2 * 3); // Reserved for software usage
+
+ /* Asign PPI to Non-Secure domain */
+ msr(ICC_PPI_DOMAINR0_EL3, val);
+ isb();
+}
+
+void gic_secure_init(void)
+{
+ /*
+ * If GICv5 is not available, skip initialisation. The OS will probably
+ * fail with a warning, but this should be easier to debug than a
+ * failure within the boot wrapper.
+ */
+ if (!has_gicv5_sysreg())
+ return;
+
+ if (this_cpu_logical_id() == 0) {
+ gic_iwb_init();
+ gic_irs_init();
+ }
+
+ gic_ppi_init();
+
+ return;
+}
+
diff --git a/configure.ac b/configure.ac
index 6f486c4..f4faff7 100644
--- a/configure.ac
+++ b/configure.ac
@@ -141,18 +141,19 @@ AC_SUBST([XEN_CMDLINE], [$X_CMDLINE])
AC_ARG_WITH([gic],
- AS_HELP_STRING([--with-gic={v2|v3}], [select GIC version]),
+ AS_HELP_STRING([--with-gic={v2|v3|v5}], [select GIC version]),
[GIC_VERSION=$withval],
[GIC_VERSION=v2])
AS_CASE([$GIC_VERSION],
- [v2|v3], [],
- [AC_MSG_ERROR([Invalid GIC version: $GIC_VERSION (use v2 or v3)])])
+ [v2|v3|v5], [],
+ [AC_MSG_ERROR([Invalid GIC version: $GIC_VERSION (use v2, v3, or v5)])])
AC_SUBST([GIC_VERSION], [$GIC_VERSION])
AM_CONDITIONAL([GICV2], [test "x$GIC_VERSION" = "xv2"])
AM_CONDITIONAL([GICV3], [test "x$GIC_VERSION" = "xv3"])
+AM_CONDITIONAL([GICV5], [test "x$GIC_VERSION" = "xv5"])
# Ensure that we have all the needed programs
diff --git a/scripts/FDT.pm b/scripts/FDT.pm
index 9adf70b..3f49ba6 100755
--- a/scripts/FDT.pm
+++ b/scripts/FDT.pm
@@ -322,6 +322,22 @@ sub get_num_reg_cells
return ($ac, $sc);
}
+sub get_regname_idx
+{
+ my $self = shift;
+ my $regname = shift;
+
+ my $prop = $self->get_property("reg-names");
+
+ return undef if (not defined($prop));
+
+ my @names = $prop->read_strings();
+
+ my ($idx) = grep { $names[$_] eq $regname } 0 .. $#names;
+
+ return $idx;
+}
+
sub translate_address
{
my $self = shift;
diff --git a/scripts/findbase-by-regname.pl b/scripts/findbase-by-regname.pl
new file mode 100755
index 0000000..49cd0ce
--- /dev/null
+++ b/scripts/findbase-by-regname.pl
@@ -0,0 +1,44 @@
+#!/usr/bin/perl -w
+# Find device register base addresses.
+#
+# Usage: ./$0 <DTB> <regname> <compatible ...>
+#
+# Copyright (C) 2026 ARM Limited. All rights reserved.
+#
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE.txt file.
+
+use warnings;
+use strict;
+
+use FDT;
+
+my $filename = shift;
+die("No filename provided") unless defined($filename);
+
+my $regname = shift;
+die("no reg regname provided") unless defined($regname);
+
+my @compats = shift;
+
+open (my $fh, "<:raw", $filename) or die("Unable to open file '$filename'");
+
+my $fdt = FDT->parse($fh) or die("Unable to parse DTB");
+
+my $root = $fdt->get_root();
+
+my @devs = ();
+for my $compat (@compats) {
+ push @devs, $root->find_compatible($compat);
+}
+
+# We only care about finding the first matching device
+my $dev = shift @devs;
+die("No matching devices found") if (not defined($dev));
+
+my $idx = $dev->get_regname_idx($regname);
+die("Cannot find reg name $regname") if (not defined($idx));
+my ($addr, $size) = $dev->get_translated_reg($idx);
+die("Cannot find reg entry $idx") if (not defined($addr) or not defined($size));
+
+printf("0x%016x\n", $addr);
--
2.34.1
^ permalink raw reply related
* [BOOTWRAPPER PATCH v2 1/2] Introduce --with-gic option
From: Vladimir Murzin @ 2026-03-24 12:59 UTC (permalink / raw)
To: linux-arm-kernel
Cc: vladimir.murzin, mark.rutland, maz, joey.gouly, Sascha.Bischoff
In-Reply-To: <20260324125906.67012-1-vladimir.murzin@arm.com>
We are about adding support for another GIC version, so introduce a
new --with-gic option to select the desired GIC version at configure
time. The default remains v2, preserving existing behavior. Howevere,
for GICv3, we replace the previous --enable-gicv3 option with
--with-gic=v3 which is backward-incompatible change (yet I hope we can
live with that).
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
---
Makefile.am | 8 +++++---
common/{gic.c => gic-v2.c} | 0
configure.ac | 23 ++++++++++++++++-------
3 files changed, 21 insertions(+), 10 deletions(-)
rename common/{gic.c => gic-v2.c} (100%)
diff --git a/Makefile.am b/Makefile.am
index 0178e5d..2710494 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -87,15 +87,17 @@ GIC_DIST_BASE := $(shell perl -I $(SCRIPT_DIR) $(SCRIPT_DIR)/findbase.pl $(KERNE
GIC_RDIST_BASE := $(shell perl -I $(SCRIPT_DIR) $(SCRIPT_DIR)/findbase.pl $(KERNEL_DTB) 1 'arm,gic-v3')
DEFINES += -DGIC_DIST_BASE=$(GIC_DIST_BASE)
DEFINES += -DGIC_RDIST_BASE=$(GIC_RDIST_BASE)
-COMMON_OBJ += gic-v3.o
-else
+endif
+
+if GICV2
GIC_DIST_BASE := $(shell perl -I $(SCRIPT_DIR) $(SCRIPT_DIR)/findbase.pl $(KERNEL_DTB) 0 'arm,cortex-a15-gic')
GIC_CPU_BASE := $(shell perl -I $(SCRIPT_DIR) $(SCRIPT_DIR)/findbase.pl $(KERNEL_DTB) 1 'arm,cortex-a15-gic')
DEFINES += -DGIC_CPU_BASE=$(GIC_CPU_BASE)
DEFINES += -DGIC_DIST_BASE=$(GIC_DIST_BASE)
-COMMON_OBJ += gic.o
endif
+COMMON_OBJ += gic-$(GIC_VERSION).o
+
if KERNEL_32
MBOX_OFFSET := 0x7ff8
TEXT_LIMIT := 0x3000
diff --git a/common/gic.c b/common/gic-v2.c
similarity index 100%
rename from common/gic.c
rename to common/gic-v2.c
diff --git a/configure.ac b/configure.ac
index 42858df..6f486c4 100644
--- a/configure.ac
+++ b/configure.ac
@@ -139,12 +139,21 @@ AC_ARG_WITH([xen-cmdline],
[X_CMDLINE=$withval])
AC_SUBST([XEN_CMDLINE], [$X_CMDLINE])
-# Allow a user to pass --enable-gicv3
-AC_ARG_ENABLE([gicv3],
- AS_HELP_STRING([--enable-gicv3], [enable GICv3 instead of GICv2]),
- [USE_GICV3=$enableval])
-AM_CONDITIONAL([GICV3], [test "x$USE_GICV3" = "xyes"])
-AS_IF([test "x$USE_GICV3" = "xyes"], [], [USE_GICV3=no])
+
+AC_ARG_WITH([gic],
+ AS_HELP_STRING([--with-gic={v2|v3}], [select GIC version]),
+ [GIC_VERSION=$withval],
+ [GIC_VERSION=v2])
+
+AS_CASE([$GIC_VERSION],
+ [v2|v3], [],
+ [AC_MSG_ERROR([Invalid GIC version: $GIC_VERSION (use v2 or v3)])])
+
+AC_SUBST([GIC_VERSION], [$GIC_VERSION])
+
+AM_CONDITIONAL([GICV2], [test "x$GIC_VERSION" = "xv2"])
+AM_CONDITIONAL([GICV3], [test "x$GIC_VERSION" = "xv3"])
+
# Ensure that we have all the needed programs
AC_PROG_CC
@@ -174,7 +183,7 @@ echo " Device tree compiler: ${DTC}"
echo " Linux kernel command line: ${CMDLINE}"
echo " Embedded initrd: ${FILESYSTEM:-NONE}"
echo " Use PSCI? ${USE_PSCI}"
-echo " Use GICv3? ${USE_GICV3}"
+echo " GIC version: ${GIC_VERSION}"
echo " Boot-wrapper execution state: AArch${BOOTWRAPPER_ES}"
echo " Kernel execution state: AArch${KERNEL_ES}"
echo " Xen image ${XEN_IMAGE:-NONE}"
--
2.34.1
^ permalink raw reply related
* [BOOTWRAPPER PATCH v2 0/2] Support GICv5
From: Vladimir Murzin @ 2026-03-24 12:59 UTC (permalink / raw)
To: linux-arm-kernel
Cc: vladimir.murzin, mark.rutland, maz, joey.gouly, Sascha.Bischoff
Small series adding GICv5 to the list of supported GIC
versions. Minimal implementation, just enough for Fast Models.
Thanks!
Changelog:
v1 -> v2
- Assign SW_PPI to NS domain (per Sascha)
Vladimir Murzin (2):
Introduce --with-gic option
Add support for GICv5
Makefile.am | 15 +++-
arch/aarch64/include/asm/cpu.h | 11 +++
common/{gic.c => gic-v2.c} | 0
common/gic-v5.c | 134 +++++++++++++++++++++++++++++++++
configure.ac | 24 ++++--
scripts/FDT.pm | 16 ++++
scripts/findbase-by-regname.pl | 44 +++++++++++
7 files changed, 234 insertions(+), 10 deletions(-)
rename common/{gic.c => gic-v2.c} (100%)
create mode 100644 common/gic-v5.c
create mode 100755 scripts/findbase-by-regname.pl
--
2.34.1
^ permalink raw reply
* Re: [PATCH 10/12] s390/ap: use generic driver_override infrastructure
From: Holger Dengler @ 2026-03-24 12:58 UTC (permalink / raw)
To: Danilo Krummrich, Russell King, Greg Kroah-Hartman,
Rafael J. Wysocki, Ioana Ciornei, Nipun Gupta, Nikhil Agarwal,
K. Y. Srinivasan, Haiyang Zhang, Wei Liu, Dexuan Cui, Long Li,
Bjorn Helgaas, Armin Wolf, Bjorn Andersson, Mathieu Poirier,
Vineeth Vijayan, Peter Oberparleiter, Heiko Carstens,
Vasily Gorbik, Alexander Gordeev, Christian Borntraeger,
Sven Schnelle, Harald Freudenberger, Mark Brown,
Michael S. Tsirkin, Jason Wang, Xuan Zhuo, Eugenio Pérez,
Alex Williamson, Juergen Gross, Stefano Stabellini,
Oleksandr Tyshchenko, Christophe Leroy (CS GROUP)
Cc: linux-kernel, driver-core, linuxppc-dev, linux-hyperv, linux-pci,
platform-driver-x86, linux-arm-msm, linux-remoteproc, linux-s390,
linux-spi, virtualization, kvm, xen-devel, linux-arm-kernel
In-Reply-To: <20260324005919.2408620-11-dakr@kernel.org>
On 24/03/2026 01:59, Danilo Krummrich wrote:
> When the AP masks are updated via apmask_store() or aqmask_store(),
> ap_bus_revise_bindings() is called after ap_attr_mutex has been
> released.
>
> This calls __ap_revise_reserved(), which accesses the driver_override
> field without holding any lock, racing against a concurrent
> driver_override_store() that may free the old string, resulting in a
> potential UAF.
>
> Fix this by using the driver-core driver_override infrastructure, which
> protects all accesses with an internal spinlock.
>
> Note that unlike most other buses, the AP bus does not check
> driver_override in its match() callback; the override is checked in
> ap_device_probe() and __ap_revise_reserved() instead.
>
> Also note that we do not enable the driver_override feature of struct
> bus_type, as AP - in contrast to most other buses - passes "" to
> sysfs_emit() when the driver_override pointer is NULL. Thus, printing
> "\n" instead of "(null)\n".
>
> Additionally, AP has a custom counter that is modified in the
> corresponding custom driver_override_store().
>
> Fixes: d38a87d7c064 ("s390/ap: Support driver_override for AP queue devices")
> Signed-off-by: Danilo Krummrich <dakr@kernel.org>
Tested-by: Holger Dengler <dengler@linux.ibm.com>
Reviewed-by: Holger Dengler <dengler@linux.ibm.com>
--
Mit freundlichen Grüßen / Kind regards
Holger Dengler
--
IBM Systems, Linux on IBM Z Development
dengler@linux.ibm.com
^ permalink raw reply
* [GIT PULL 4/4] ARM: samsung: mach code for v7.1
From: Krzysztof Kozlowski @ 2026-03-24 12:58 UTC (permalink / raw)
To: Arnd Bergmann, soc
Cc: Krzysztof Kozlowski, Alim Akhtar, Peter Griffin, linux-arm-kernel,
linux-samsung-soc, linux-kernel
In-Reply-To: <20260324125821.59728-5-krzk@kernel.org>
The following changes since commit 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f:
Linux 7.0-rc1 (2026-02-22 13:18:59 -0800)
are available in the Git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git tags/samsung-soc-7.1
for you to fetch changes up to 32d4b991f25eeffac7568ef51367f924394fbdc5:
ARM: samsung: exynos5250: Allow CPU1 to boot (2026-02-26 22:13:27 +0100)
----------------------------------------------------------------
Samsung mach/soc changes for v7.1
Fix booting of secondary CPU on Exynos5250 based Google Manta board -
difference in TZ firmware.
----------------------------------------------------------------
Alexandre Marquet (1):
ARM: samsung: exynos5250: Allow CPU1 to boot
arch/arm/mach-exynos/firmware.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
^ permalink raw reply
* [GIT PULL 2/4] arm64: dts: samsung: dts for v7.1
From: Krzysztof Kozlowski @ 2026-03-24 12:58 UTC (permalink / raw)
To: Arnd Bergmann, soc
Cc: Krzysztof Kozlowski, Alim Akhtar, Peter Griffin, linux-arm-kernel,
linux-samsung-soc, linux-kernel
In-Reply-To: <20260324125821.59728-5-krzk@kernel.org>
The following changes since commit 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f:
Linux 7.0-rc1 (2026-02-22 13:18:59 -0800)
are available in the Git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git tags/samsung-dt64-7.1
for you to fetch changes up to 90f771a9745476a5e2b95b5efe225a943c090bb9:
arm64: dts: exynos8895: Move I2C address/size-cells to DTSI (2026-03-10 17:04:20 +0100)
----------------------------------------------------------------
Samsung DTS ARM64 changes for v7.1
1. Add initial support for Axis ARTPEC-9 SoC and Alfred board using it.
Just like ARTPEC-8, this is a derivative of Samsung Exynos SoC made
for Axis, sharing most or all of core SoC blocks with Samsung
designs.
2. New boards: Exynos7870 based Samsung Galaxy J7 (2016) and Samsung
Galaxy J5 (2017).
3. Google GS101 Pixel phone: describe all PMIC regulators and Maxim
fuel-gauge.
4. ExynosAutov920: add G3D (GPU) clock controller (CMU).
----------------------------------------------------------------
Andras Sebok (1):
arm64: dts: exynos: add initial support for Samsung Galaxy J5
André Draszik (2):
arm64: dts: exynos: gs101-pixel: add all S2MPG1x regulators
arm64: dts: exynos: gs101-pixel-common: add Maxim MAX77759 fuel gauge
GyoungBo Min (1):
dt-bindings: clock: Add ARTPEC-9 clock controller
Kaustabh Chakraborty (2):
dt-bindings: arm: samsung: add compatible for samsung-j7xelte
dt-bindings: arm: samsung: add compatible for samsung-j5y17lte
Krzysztof Kozlowski (3):
arm64: dts: axis: artpec9: Fix missing soc unit address
arm64: dts: exynos7870: Move I2C address/size-cells to DTSI
arm64: dts: exynos8895: Move I2C address/size-cells to DTSI
Raghav Sharma (1):
arm64: dts: exynosautov920: add CMU_G3D clock DT nodes
Ravi Patel (2):
dt-bindings: arm: axis: Add ARTPEC-9 alfred board
arm64: dts: axis: Add ARTPEC-9 Alfred board support
Rayan Marzouk (1):
arm64: dts: exynos: add initial support for Samsung Galaxy J7 (2016)
SungMin Park (1):
arm64: dts: exynos: axis: Add initial ARTPEC-9 SoC support
Documentation/devicetree/bindings/arm/axis.yaml | 6 +
.../bindings/arm/samsung/samsung-boards.yaml | 2 +
.../bindings/clock/axis,artpec9-clock.yaml | 232 +++++++++
arch/arm64/boot/dts/exynos/Makefile | 2 +
arch/arm64/boot/dts/exynos/axis/Makefile | 3 +-
arch/arm64/boot/dts/exynos/axis/artpec9-alfred.dts | 36 ++
.../boot/dts/exynos/axis/artpec9-pinctrl.dtsi | 115 +++++
arch/arm64/boot/dts/exynos/axis/artpec9.dtsi | 277 +++++++++++
.../arm64/boot/dts/exynos/exynos7870-a2corelte.dts | 9 -
arch/arm64/boot/dts/exynos/exynos7870-j5y17lte.dts | 523 ++++++++++++++++++++
arch/arm64/boot/dts/exynos/exynos7870-j6lte.dts | 6 -
arch/arm64/boot/dts/exynos/exynos7870-j7xelte.dts | 494 +++++++++++++++++++
arch/arm64/boot/dts/exynos/exynos7870-on7xelte.dts | 9 -
arch/arm64/boot/dts/exynos/exynos7870.dtsi | 48 ++
arch/arm64/boot/dts/exynos/exynos8895-dreamlte.dts | 2 -
arch/arm64/boot/dts/exynos/exynos8895.dtsi | 128 +++++
arch/arm64/boot/dts/exynos/exynosautov920.dtsi | 13 +
arch/arm64/boot/dts/exynos/google/gs101-oriole.dts | 22 +
.../boot/dts/exynos/google/gs101-pixel-common.dtsi | 528 ++++++++++++++++++++-
arch/arm64/boot/dts/exynos/google/gs101-raven.dts | 18 +
include/dt-bindings/clock/axis,artpec9-clk.h | 195 ++++++++
21 files changed, 2640 insertions(+), 28 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/axis,artpec9-clock.yaml
create mode 100644 arch/arm64/boot/dts/exynos/axis/artpec9-alfred.dts
create mode 100644 arch/arm64/boot/dts/exynos/axis/artpec9-pinctrl.dtsi
create mode 100644 arch/arm64/boot/dts/exynos/axis/artpec9.dtsi
create mode 100644 arch/arm64/boot/dts/exynos/exynos7870-j5y17lte.dts
create mode 100644 arch/arm64/boot/dts/exynos/exynos7870-j7xelte.dts
create mode 100644 include/dt-bindings/clock/axis,artpec9-clk.h
^ permalink raw reply
* [GIT PULL 3/4] ARM: dts: samsung: dts for v7.1
From: Krzysztof Kozlowski @ 2026-03-24 12:58 UTC (permalink / raw)
To: Arnd Bergmann, soc
Cc: Krzysztof Kozlowski, Alim Akhtar, Peter Griffin, linux-arm-kernel,
linux-samsung-soc, linux-kernel
In-Reply-To: <20260324125821.59728-5-krzk@kernel.org>
The following changes since commit 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f:
Linux 7.0-rc1 (2026-02-22 13:18:59 -0800)
are available in the Git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git tags/samsung-dt-7.1
for you to fetch changes up to 44ee52a030a6dd2f6e0ecb3632ecf8b263114619:
ARM: dts: exyons4412: Drop duplicated I2C address/size-cells (2026-03-10 17:03:43 +0100)
----------------------------------------------------------------
Samsung DTS ARM changes for v7.1
1. New board: Exynos5250 based Google Manta (Nexus 10).
2. Few cleanups.
----------------------------------------------------------------
Alexandre Marquet (2):
dt-bindings: ARM: samsung: Add Google Manta (Nexus 10)
ARM: dts: exynos: Add Google Manta (Nexus 10)
Krzysztof Kozlowski (3):
ARM: dts: exynos3250: Drop duplicated I2C address/size-cells
ARM: dts: exynos4210-smdkv310: Drop duplicated I2C address/size-cells
ARM: dts: exyons4412: Drop duplicated I2C address/size-cells
.../bindings/arm/samsung/samsung-boards.yaml | 1 +
arch/arm/boot/dts/samsung/Makefile | 1 +
arch/arm/boot/dts/samsung/exynos3250-artik5.dtsi | 2 -
arch/arm/boot/dts/samsung/exynos3250-monk.dts | 4 -
arch/arm/boot/dts/samsung/exynos3250-rinato.dts | 4 -
arch/arm/boot/dts/samsung/exynos4210-smdkv310.dts | 2 -
.../boot/dts/samsung/exynos4412-itop-scp-core.dtsi | 2 -
arch/arm/boot/dts/samsung/exynos4412-origen.dts | 2 -
arch/arm/boot/dts/samsung/exynos5250-manta.dts | 564 +++++++++++++++++++++
9 files changed, 566 insertions(+), 16 deletions(-)
create mode 100644 arch/arm/boot/dts/samsung/exynos5250-manta.dts
^ permalink raw reply
* [GIT PULL 1/4] samsung: drivers for v7.1
From: Krzysztof Kozlowski @ 2026-03-24 12:58 UTC (permalink / raw)
To: Arnd Bergmann, soc
Cc: Krzysztof Kozlowski, Alim Akhtar, Peter Griffin, linux-arm-kernel,
linux-samsung-soc, linux-kernel
The following changes since commit 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f:
Linux 7.0-rc1 (2026-02-22 13:18:59 -0800)
are available in the Git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git tags/samsung-drivers-7.1
for you to fetch changes up to a2be37eedb52ea26938fa4cc9de1ff84963c57ad:
firmware: exynos-acpm: Drop fake 'const' on handle pointer (2026-02-28 15:47:03 +0100)
----------------------------------------------------------------
Samsung SoC drivers for v7.1
Few cleanups in ACPM firmware drivers, used on Google GS101 and newer
Samsung Exynos SoCs. Notable change is removing 'const' in
'struct acpm_handle' pointers, because even though the code does not
modify pointed data, it immediately drops the const via cast. Also code
is not logically readable when a reference getters/putters (e.g.
acpm_handle_put()) take a pointer to const, because the meaning of "get"
and "put" implies changing the memory, even if that changeable field is
outside of pointed data.
----------------------------------------------------------------
André Draszik (1):
dt-bindings: firmware: google,gs101-acpm-ipc: add S2MPG11 secondary PMIC
Krzysztof Kozlowski (4):
firmware: exynos-acpm: Use unsigned int for acpm_pmic_linux_errmap index
firmware: exynos-acpm: Count number of commands in acpm_xfer
firmware: exynos-acpm: Count acpm_xfer buffers with __counted_by_ptr
firmware: exynos-acpm: Drop fake 'const' on handle pointer
.../bindings/firmware/google,gs101-acpm-ipc.yaml | 50 +++++++++++++++++++++-
drivers/clk/samsung/clk-acpm.c | 4 +-
drivers/firmware/samsung/exynos-acpm-dvfs.c | 13 +++---
drivers/firmware/samsung/exynos-acpm-dvfs.h | 4 +-
drivers/firmware/samsung/exynos-acpm-pmic.c | 26 +++++------
drivers/firmware/samsung/exynos-acpm-pmic.h | 10 ++---
drivers/firmware/samsung/exynos-acpm.c | 30 +++++++------
drivers/firmware/samsung/exynos-acpm.h | 10 ++---
drivers/mfd/sec-acpm.c | 10 ++---
.../linux/firmware/samsung/exynos-acpm-protocol.h | 40 ++++++++---------
10 files changed, 120 insertions(+), 77 deletions(-)
^ permalink raw reply
* Re: [PATCH v3 5/5] KVM: arm64: Add SMC hook for SME dvmsync erratum
From: Catalin Marinas @ 2026-03-24 12:56 UTC (permalink / raw)
To: Vincent Donnefort
Cc: linux-arm-kernel, Will Deacon, Marc Zyngier, Oliver Upton,
Lorenzo Pieralisi, Sudeep Holla, James Morse, Mark Rutland,
Mark Brown, kvmarm
In-Reply-To: <acJkEEXKt_GunFLQ@google.com>
On Tue, Mar 24, 2026 at 10:14:40AM +0000, Vincent Donnefort wrote:
> On Mon, Mar 23, 2026 at 04:24:05PM +0000, Catalin Marinas wrote:
> > From: James Morse <james.morse@arm.com>
> >
> > C1-Pro cores with SME have an erratum where TLBI+DSB does not complete
> > all outstanding SME accesses. Instead a DSB needs to be executed on the
> > affecteed CPUs. The implication is pages cannot be unmapped from the
> > host stage2 then provided to the guest. Host SME accesses may occur
> > after this point.
> >
> > This erratum breaks pKVM's guarantees, and the workaround is hard to
> > implement as EL2 and EL1 share a security state meaning EL1 can mask
> > IPI sent by EL2, leading to interrupt blackouts.
> >
> > Instead, do this in EL3. This has the advantage of a separate security
> > state, meaning lower EL cannot mask the IPI. It is also simpler for EL3
> > to know about CPUs that are off or in PSCI's CPU_SUSPEND.
> >
> > Add the needed hook.
> >
> > Signed-off-by: James Morse <james.morse@arm.com>
> > Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
> > Cc: Marc Zyngier <maz@kernel.org>
> > Cc: Oliver Upton <oupton@kernel.org>
> > Cc: Will Deacon <will@kernel.org>
> > Cc: Mark Rutland <mark.rutland@arm.com>
> > Cc: Lorenzo Pieralisi <lpieralisi@kernel.org>
> > Cc: Sudeep Holla <sudeep.holla@kernel.org>
>
> In case this goes in before Will's p-guest series and with just a small comment
> below:
>
> Reviewed-by: Vincent Donnefort <vdonnefort@google.com>
Thanks.
I can leave this patch for later, maybe merge it after -rc1.
> > diff --git a/arch/arm64/kvm/hyp/nvhe/mem_protect.c b/arch/arm64/kvm/hyp/nvhe/mem_protect.c
> > index 38f66a56a766..ef8afbdd421b 100644
> > --- a/arch/arm64/kvm/hyp/nvhe/mem_protect.c
> > +++ b/arch/arm64/kvm/hyp/nvhe/mem_protect.c
> > @@ -5,6 +5,8 @@
> > */
> >
> > #include <linux/kvm_host.h>
> > +#include <linux/arm-smccc.h>
> > +
> > #include <asm/kvm_emulate.h>
> > #include <asm/kvm_hyp.h>
> > #include <asm/kvm_mmu.h>
> > @@ -28,6 +30,15 @@ static struct hyp_pool host_s2_pool;
> > static DEFINE_PER_CPU(struct pkvm_hyp_vm *, __current_vm);
> > #define current_vm (*this_cpu_ptr(&__current_vm))
> >
> > +static void pkvm_sme_dvmsync_fw_call(void)
> > +{
> > + if (alternative_has_cap_unlikely(ARM64_WORKAROUND_4193714)) {
> > + struct arm_smccc_res res;
> > +
> > + arm_smccc_1_1_smc(ARM_SMCCC_CPU_WORKAROUND_4193714, &res);
>
> With hyp tracing in kvmarm/next, this should be hyp_smccc_1_1_smc().
One more reason to leave it after -rc1.
--
Catalin
^ permalink raw reply
* Re: [PATCH v3 00/14] drm: Create drm_output_color_format enum
From: Maxime Ripard @ 2026-03-24 12:55 UTC (permalink / raw)
To: Nicolas Frattaroli, Jani Nikula, Maarten Lankhorst,
Thomas Zimmermann, David Airlie, Simona Vetter, Harry Wentland,
Leo Li, Rodrigo Siqueira, Alex Deucher, Christian König,
Andrzej Hajda, Neil Armstrong, Robert Foss, Laurent Pinchart,
Jonas Karlman, Jernej Skrabec, Andy Yan, Liviu Dudau,
Chun-Kuang Hu, Philipp Zabel, Matthias Brugger,
AngeloGioacchino Del Regno, Sandy Huang, Heiko Stübner,
Liu Ying, Chen-Yu Tsai, Samuel Holland, Dave Stevenson,
Maíra Canal, Raspberry Pi Kernel Maintenance, Maxime Ripard
Cc: dri-devel, linux-kernel, amd-gfx, linux-mediatek,
linux-arm-kernel, linux-rockchip, linux-sunxi, Jani Nikula
In-Reply-To: <20260305-drm-rework-color-formats-v3-0-f3935f6db579@kernel.org>
On Thu, 05 Mar 2026 10:04:52 +0100, Maxime Ripard wrote:
> This series creates an enum to represent the output color format as an
> enum instead of a bitmask, and consolidate the HDMI helpers to use the
> new enum.
>
> This should make Nicolas' work easier.
>
> It has been build tested, and passes kunit tests.
>
> [...]
Applied to misc/kernel.git (drm-misc-next).
Thanks!
Maxime
^ permalink raw reply
* Re: [PATCH] ASoC: dt-bindings: stm32: Fix incorrect compatible string in stm32h7-sai match
From: Olivier MOYSAN @ 2026-03-24 12:54 UTC (permalink / raw)
To: Jihed Chaibi, arnaud.pouliquen, mcoquelin.stm32, alexandre.torgue
Cc: lgirdwood, broonie, krzk+dt, robh, conor+dt, devicetree,
linux-sound, linux-stm32, linux-kernel, linux-arm-kernel
In-Reply-To: <20260321012011.125791-1-jihed.chaibi.dev@gmail.com>
Hi,
On 3/21/26 02:20, Jihed Chaibi wrote:
> The conditional block that defines clock constraints for the stm32h7-sai
> variant references "st,stm32mph7-sai", which does not match any compatible
> string in the enum. As a result, clock validation for the h7 variant is
> silently skipped. Correct the compatible string to "st,stm32h7-sai".
>
> Fixes: 8509bb1f11a1f ("ASoC: dt-bindings: add stm32mp25 support for sai")
> Signed-off-by: Jihed Chaibi <jihed.chaibi.dev@gmail.com>
> ---
> Documentation/devicetree/bindings/sound/st,stm32-sai.yaml | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml b/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml
> index 4a7129d0b157..551edf39e766 100644
> --- a/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml
> +++ b/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml
> @@ -164,7 +164,7 @@ allOf:
> properties:
> compatible:
> contains:
> - const: st,stm32mph7-sai
> + const: st,stm32h7-sai
> then:
> properties:
> clocks:
Reviewed-by: Olivier Moysan <olivier.moysan@foss.st.com>
Thanks
^ permalink raw reply
* [PATCH v4 6/6] drm/mediatek: Add TDSHP component support for MT8196
From: Jay Liu @ 2026-03-24 12:52 UTC (permalink / raw)
To: Chun-Kuang Hu, Philipp Zabel, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno
Cc: dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Jay Liu, CK Hu
In-Reply-To: <20260324125315.4715-1-jay.liu@mediatek.com>
Add TDSHP component support for MT8196.
TDSHP is a hardware module designed to enhance the sharpness and
clarity of displayed images by analyzing and improving edges and
fine details in frames.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Jay Liu <jay.liu@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 49 +++++++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_ddp_comp.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 +
3 files changed, 52 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
index 5cbc4b995d66..bd2b288938bf 100644
--- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
@@ -57,6 +57,14 @@
#define POSTMASK_RELAY_MODE BIT(0)
#define DISP_REG_POSTMASK_SIZE 0x0030
+#define DISP_REG_TDSHP_CTRL 0x0100
+#define DISP_TDSHP_CTRL_EN BIT(0)
+#define DISP_REG_TDSHP_CFG 0x0110
+#define DISP_TDSHP_RELAY_MODE BIT(0)
+#define DISP_REG_TDSHP_INPUT_SIZE 0x0120
+#define DISP_REG_TDSHP_OUTPUT_OFFSET 0x0124
+#define DISP_REG_TDSHP_OUTPUT_SIZE 0x0128
+
#define DISP_REG_UFO_START 0x0000
#define UFO_BYPASS BIT(2)
@@ -261,6 +269,37 @@ static void mtk_postmask_stop(struct device *dev)
writel_relaxed(0x0, priv->regs + DISP_REG_POSTMASK_EN);
}
+static void mtk_disp_tdshp_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+ mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs,
+ DISP_REG_TDSHP_INPUT_SIZE);
+ mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs,
+ DISP_REG_TDSHP_OUTPUT_SIZE);
+ mtk_ddp_write(cmdq_pkt, 0x0, &priv->cmdq_reg, priv->regs,
+ DISP_REG_TDSHP_OUTPUT_OFFSET);
+
+ mtk_ddp_write(cmdq_pkt, DISP_TDSHP_RELAY_MODE, &priv->cmdq_reg,
+ priv->regs, DISP_REG_TDSHP_CFG);
+}
+
+static void mtk_disp_tdshp_start(struct device *dev)
+{
+ struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+ writel(DISP_TDSHP_CTRL_EN, priv->regs + DISP_REG_TDSHP_CTRL);
+}
+
+static void mtk_disp_tdshp_stop(struct device *dev)
+{
+ struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+ writel(0, priv->regs + DISP_REG_TDSHP_CTRL);
+}
+
static void mtk_ufoe_start(struct device *dev)
{
struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
@@ -268,6 +307,14 @@ static void mtk_ufoe_start(struct device *dev)
writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
}
+static const struct mtk_ddp_comp_funcs ddp_tdshp = {
+ .clk_enable = mtk_ddp_clk_enable,
+ .clk_disable = mtk_ddp_clk_disable,
+ .config = mtk_disp_tdshp_config,
+ .start = mtk_disp_tdshp_start,
+ .stop = mtk_disp_tdshp_stop,
+};
+
static const struct mtk_ddp_comp_funcs ddp_aal = {
.clk_enable = mtk_aal_clk_enable,
.clk_disable = mtk_aal_clk_disable,
@@ -441,6 +488,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_POSTMASK] = "postmask",
[MTK_DISP_PWM] = "pwm",
[MTK_DISP_RDMA] = "rdma",
+ [MTK_DISP_TDSHP] = "tdshp",
[MTK_DISP_UFOE] = "ufoe",
[MTK_DISP_WDMA] = "wdma",
[MTK_DP_INTF] = "dp-intf",
@@ -496,6 +544,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_DRM_ID_MAX]
[DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma },
[DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma },
[DDP_COMPONENT_RDMA4] = { MTK_DISP_RDMA, 4, &ddp_rdma },
+ [DDP_COMPONENT_TDSHP0] = { MTK_DISP_TDSHP, 0, &ddp_tdshp },
[DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe },
[DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL },
[DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL },
diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
index 7244b55f6732..cf79b6f689d0 100644
--- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
@@ -38,6 +38,7 @@ enum mtk_ddp_comp_type {
MTK_DISP_POSTMASK,
MTK_DISP_PWM,
MTK_DISP_RDMA,
+ MTK_DISP_TDSHP,
MTK_DISP_UFOE,
MTK_DISP_WDMA,
MTK_DPI,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 6f6db2e1980e..3dd7d4bb7e41 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -789,6 +789,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_RDMA },
{ .compatible = "mediatek,mt8195-disp-rdma",
.data = (void *)MTK_DISP_RDMA },
+ { .compatible = "mediatek,mt8196-disp-tdshp",
+ .data = (void *)MTK_DISP_TDSHP },
{ .compatible = "mediatek,mt8173-disp-ufoe",
.data = (void *)MTK_DISP_UFOE },
{ .compatible = "mediatek,mt8173-disp-wdma",
--
2.46.0
^ permalink raw reply related
* [PATCH v4 5/6] drm/mediatek: Support multiple CCORR component
From: Jay Liu @ 2026-03-24 12:52 UTC (permalink / raw)
To: Chun-Kuang Hu, Philipp Zabel, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno
Cc: dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Jay Liu
In-Reply-To: <20260324125315.4715-1-jay.liu@mediatek.com>
Add CCORR component support for MT8196.
CCORR is a hardware module that optimizes the visual effects of
images by adjusting the color matrix, enabling features such as
night light.
The 8196 SoC has two CCORR hardware units, which must be chained
together in a fixed order in the display path to display the image
correctly. the `mtk_ccorr_ctm_set` API only utilizes one of these units.
To prevent the unused CCORR unit from inadvertently taking effect,
we need to block it in the mtk_crtc.c.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Jay Liu <jay.liu@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_crtc.c | 5 ++++-
drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 3 ++-
drivers/gpu/drm/mediatek/mtk_ddp_comp.h | 7 ++++---
drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 6 ++++--
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 2 +-
5 files changed, 15 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_crtc.c b/drivers/gpu/drm/mediatek/mtk_crtc.c
index fcb16f3f7b23..09b260a9a4ee 100644
--- a/drivers/gpu/drm/mediatek/mtk_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_crtc.c
@@ -872,11 +872,14 @@ static void mtk_crtc_atomic_flush(struct drm_crtc *crtc,
{
struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
int i;
+ bool ctm_set = false;
if (crtc->state->color_mgmt_changed)
for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
- mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state);
+ /* only set ctm once for the pipeline with two CCORR components */
+ if (!ctm_set)
+ ctm_set = mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state);
}
mtk_crtc_update_config(mtk_crtc, !!mtk_crtc->event);
}
diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
index 9672ea1f91a2..5cbc4b995d66 100644
--- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
@@ -458,7 +458,8 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_DRM_ID_MAX]
[DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal },
[DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal },
[DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL },
- [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr },
+ [DDP_COMPONENT_CCORR0] = { MTK_DISP_CCORR, 0, &ddp_ccorr },
+ [DDP_COMPONENT_CCORR1] = { MTK_DISP_CCORR, 1, &ddp_ccorr },
[DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color },
[DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color },
[DDP_COMPONENT_DITHER0] = { MTK_DISP_DITHER, 0, &ddp_dither },
diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
index 3f3d43f4330d..7244b55f6732 100644
--- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
@@ -77,7 +77,7 @@ struct mtk_ddp_comp_funcs {
struct drm_crtc_state *state);
void (*bgclr_in_on)(struct device *dev);
void (*bgclr_in_off)(struct device *dev);
- void (*ctm_set)(struct device *dev,
+ bool (*ctm_set)(struct device *dev,
struct drm_crtc_state *state);
struct device * (*dma_dev_get)(struct device *dev);
u32 (*get_blend_modes)(struct device *dev);
@@ -254,11 +254,12 @@ static inline void mtk_ddp_comp_bgclr_in_off(struct mtk_ddp_comp *comp)
comp->funcs->bgclr_in_off(comp->dev);
}
-static inline void mtk_ddp_ctm_set(struct mtk_ddp_comp *comp,
+static inline bool mtk_ddp_ctm_set(struct mtk_ddp_comp *comp,
struct drm_crtc_state *state)
{
if (comp->funcs && comp->funcs->ctm_set)
- comp->funcs->ctm_set(comp->dev, state);
+ return comp->funcs->ctm_set(comp->dev, state);
+ return false;
}
static inline struct device *mtk_ddp_comp_dma_dev_get(struct mtk_ddp_comp *comp)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
index 6d7bf4afa78d..ac59d81dbb26 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
@@ -80,7 +80,7 @@ void mtk_ccorr_stop(struct device *dev)
writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN);
}
-void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state)
+bool mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state)
{
struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev);
struct drm_property_blob *blob = state->ctm;
@@ -92,7 +92,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state)
u32 matrix_bits = ccorr->data->matrix_bits;
if (!blob)
- return;
+ return false;
ctm = (struct drm_color_ctm *)blob->data;
input = ctm->matrix;
@@ -110,6 +110,8 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state)
&ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_3);
mtk_ddp_write(cmdq_pkt, coeffs[8] << 16,
&ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_4);
+
+ return true;
}
static int mtk_disp_ccorr_bind(struct device *dev, struct device *master,
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 679d413bf10b..4203c28c38ce 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -22,7 +22,7 @@ void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state);
void mtk_aal_start(struct device *dev);
void mtk_aal_stop(struct device *dev);
-void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state);
+bool mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state);
int mtk_ccorr_clk_enable(struct device *dev);
void mtk_ccorr_clk_disable(struct device *dev);
void mtk_ccorr_config(struct device *dev, unsigned int w,
--
2.46.0
^ permalink raw reply related
* [PATCH v4 4/6] dt-bindings: display: mediatek: disp-tdshp: Add support for MT8196
From: Jay Liu @ 2026-03-24 12:52 UTC (permalink / raw)
To: Chun-Kuang Hu, Philipp Zabel, David Airlie, Simona Vetter,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno
Cc: dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Jay Liu
In-Reply-To: <20260324125315.4715-1-jay.liu@mediatek.com>
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="y", Size: 1678 bytes --]
Add disp-tdshp hardware description for MediaTek MT8196 SoC
Signed-off-by: Jay Liu <jay.liu@mediatek.com>
---
.../display/mediatek/mediatek,disp-tdshp.yaml | 46 +++++++++++++++++++
1 file changed, 46 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,disp-tdshp.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp-tdshp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp-tdshp.yaml
new file mode 100644
index 000000000000..048281a5b22f
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp-tdshp.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,disp-tdshp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek display 2D sharpness processor
+
+maintainers:
+ - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+ - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+ MediaTek display 2D sharpness processor, namely TDSHP, provides a
+ operation used to adjust sharpness in display system.
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt8196-disp-tdshp
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ disp-tdshp@321e0000 {
+ compatible = "mediatek,mt8196-disp-tdshp";
+ reg = <0 0x321e0000 0 0x1000>;
+ clocks = <&dispsys_config_clk 107>;
+ };
+ };
--
2.46.0
^ permalink raw reply related
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