* Re: [PATCH v2 2/5] clk: mediatek: Add mt8173-mfgtop driver
From: Brian Masney @ 2026-03-25 14:26 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: Stephen Boyd, Matthias Brugger, AngeloGioacchino Del Regno,
Frank Binns, Matt Coster, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Icenowy Zheng, Icenowy Zheng, David Airlie,
Simona Vetter, linux-clk, devicetree, linux-mediatek, dri-devel,
linux-arm-kernel, linux-kernel
In-Reply-To: <20260325071951.544031-3-wenst@chromium.org>
On Wed, Mar 25, 2026 at 03:19:46PM +0800, Chen-Yu Tsai wrote:
> The MFG (GPU) block on the MT8173 has a small glue layer, named MFG_TOP
> in the datasheet, that contains clock gates, some power sequence signal
> delays, and other unknown registers that get toggled when the GPU is
> powered on.
>
> The clock gates are exposed as clocks provided by a clock controller,
> while the power sequencing bits are exposed as one singular power domain.
>
> Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
> ---
> Changes since v1:
> - Reduce tab after GATE_MFG() by one tab
> - Move of_match_clk_mt8173_mfgtop to just before clk_mt8173_mfgtop_drv
> - Rename power domain to "mfg-top"
> - Add FORCE_ABORT and ACTIVE_PWRCTL_EN bits and explicitly clear
> ACTIVE_PWRCTL_EN bit
> ---
> drivers/clk/mediatek/Kconfig | 9 +
> drivers/clk/mediatek/Makefile | 1 +
> drivers/clk/mediatek/clk-mt8173-mfgtop.c | 243 +++++++++++++++++++++++
> 3 files changed, 253 insertions(+)
> create mode 100644 drivers/clk/mediatek/clk-mt8173-mfgtop.c
>
> diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
> index 2c09fd729bab..8dbd9f14be62 100644
> --- a/drivers/clk/mediatek/Kconfig
> +++ b/drivers/clk/mediatek/Kconfig
> @@ -537,6 +537,15 @@ config COMMON_CLK_MT8173_IMGSYS
> help
> This driver supports MediaTek MT8173 imgsys clocks.
>
> +config COMMON_CLK_MT8173_MFGTOP
> + tristate "Clock and power driver for MediaTek MT8173 mfgtop"
> + depends on COMMON_CLK_MT8173
> + default COMMON_CLK_MT8173
> + select PM_GENERIC_DOMAINS
> + select PM_GENERIC_DOMAINS_OF
> + help
> + This driver supports MediaTek MT8173 mfgtop clocks and power domain.
> +
> config COMMON_CLK_MT8173_MMSYS
> tristate "Clock driver for MediaTek MT8173 mmsys"
> depends on COMMON_CLK_MT8173
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index d8736a060dbd..892a54eeb281 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -82,6 +82,7 @@ obj-$(CONFIG_COMMON_CLK_MT8167_VDECSYS) += clk-mt8167-vdec.o
> obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173-apmixedsys.o clk-mt8173-infracfg.o \
> clk-mt8173-pericfg.o clk-mt8173-topckgen.o
> obj-$(CONFIG_COMMON_CLK_MT8173_IMGSYS) += clk-mt8173-img.o
> +obj-$(CONFIG_COMMON_CLK_MT8173_MFGTOP) += clk-mt8173-mfgtop.o
> obj-$(CONFIG_COMMON_CLK_MT8173_MMSYS) += clk-mt8173-mm.o
> obj-$(CONFIG_COMMON_CLK_MT8173_VDECSYS) += clk-mt8173-vdecsys.o
> obj-$(CONFIG_COMMON_CLK_MT8173_VENCSYS) += clk-mt8173-vencsys.o
> diff --git a/drivers/clk/mediatek/clk-mt8173-mfgtop.c b/drivers/clk/mediatek/clk-mt8173-mfgtop.c
> new file mode 100644
> index 000000000000..9e18f34166ae
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8173-mfgtop.c
> @@ -0,0 +1,243 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2024 Google LLC
> + * Author: Chen-Yu Tsai <wenst@chromium.org>
> + *
> + * Based on driver in downstream ChromeOS v5.15 kernel.
> + *
> + * Copyright (c) 2014 MediaTek Inc.
> + * Author: Chiawen Lee <chiawen.lee@mediatek.com>
> + */
> +
> +#include <dt-bindings/clock/mt8173-clk.h>
> +
> +#include <linux/bitfield.h>
> +#include <linux/clk.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_domain.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/regmap.h>
> +
> +#include "clk-gate.h"
> +#include "clk-mtk.h"
> +
> +static const struct mtk_gate_regs mfg_cg_regs = {
> + .sta_ofs = 0x0000,
> + .clr_ofs = 0x0008,
> + .set_ofs = 0x0004,
> +};
> +
> +#define GATE_MFG(_id, _name, _parent, _shift, _flags) \
> + GATE_MTK_FLAGS(_id, _name, _parent, &mfg_cg_regs, _shift, &mtk_clk_gate_ops_setclr, _flags)
> +
> +/* TODO: The block actually has dividers for the core and mem clocks. */
> +static const struct mtk_gate mfg_clks[] = {
> + GATE_MFG(CLK_MFG_AXI, "mfg_axi", "axi_mfg_in_sel", 0, CLK_SET_RATE_PARENT),
> + GATE_MFG(CLK_MFG_MEM, "mfg_mem", "mem_mfg_in_sel", 1, CLK_SET_RATE_PARENT),
> + GATE_MFG(CLK_MFG_G3D, "mfg_g3d", "mfg_sel", 2, CLK_SET_RATE_PARENT),
> + GATE_MFG(CLK_MFG_26M, "mfg_26m", "clk26m", 3, 0),
> +};
> +
> +static const struct mtk_clk_desc mfg_desc = {
> + .clks = mfg_clks,
> + .num_clks = ARRAY_SIZE(mfg_clks),
> +};
> +
> +struct mt8173_mfgtop_data {
> + struct clk_hw_onecell_data *clk_data;
> + struct regmap *regmap;
> + struct generic_pm_domain genpd;
> + struct of_phandle_args parent_pd, child_pd;
> + struct clk *clk_26m;
> +};
> +
> +/* Delay count in clock cycles */
> +#define MFG_ACTIVE_POWER_CON0 0x24
> + #define RST_B_DELAY_CNT GENMASK(7, 0) /* pwr_rst_b de-assert delay during power-up */
> + #define CLK_EN_DELAY_CNT GENMASK(15, 8) /* CLK_DIS deassert delay during power-up */
> + #define CLK_DIS_DELAY_CNT GENMASK(23, 16) /* CLK_DIS assert delay during power-down */
> + #define FORCE_ABORT BIT(30) /* write 1 to force abort a power event */
> + #define ACTIVE_PWRCTL_EN BIT(31) /* enable ACTIVE_POWER */
> +
> +#define MFG_ACTIVE_POWER_CON1 0x28
> + #define PWR_ON_S_DELAY_CNT GENMASK(7, 0) /* pwr_on_s assert delay during power-up */
> + #define ISO_DELAY_CNT GENMASK(15, 8) /* ISO assert delay during power-down */
> + #define ISOOFF_DELAY_CNT GENMASK(23, 16) /* ISO de-assert delay during power-up */
> + #define RST__DELAY_CNT GENMASK(31, 24) /* pwr_rsb_b assert delay during power-down */
Is the double underscore expected in the name?
> +
> +static int clk_mt8173_mfgtop_power_on(struct generic_pm_domain *domain)
> +{
> + struct mt8173_mfgtop_data *data = container_of(domain, struct mt8173_mfgtop_data, genpd);
> +
> + /* drives internal power management */
> + clk_prepare_enable(data->clk_26m);
> +
> + /* Power on/off delays for various signals */
> + regmap_write(data->regmap, MFG_ACTIVE_POWER_CON0,
Should the return value of clk_prepare_enable() and regmap_write() be
checked?
> + FIELD_PREP(RST_B_DELAY_CNT, 77) |
> + FIELD_PREP(CLK_EN_DELAY_CNT, 61) |
> + FIELD_PREP(CLK_DIS_DELAY_CNT, 60) |
> + FIELD_PREP(ACTIVE_PWRCTL_EN, 0));
> + regmap_write(data->regmap, MFG_ACTIVE_POWER_CON1,
> + FIELD_PREP(PWR_ON_S_DELAY_CNT, 11) |
> + FIELD_PREP(ISO_DELAY_CNT, 68) |
> + FIELD_PREP(ISOOFF_DELAY_CNT, 69) |
> + FIELD_PREP(RST__DELAY_CNT, 77));
> +
> + /* Magic numbers related to core switch sequence and delays */
> + regmap_write(data->regmap, 0xe0, 0x7a710184);
> + regmap_write(data->regmap, 0xe4, 0x835f6856);
> + regmap_write(data->regmap, 0xe8, 0x002b0234);
> + regmap_write(data->regmap, 0xec, 0x80000000);
> + regmap_write(data->regmap, 0xa0, 0x08000000);
> +
> + return 0;
> +}
> +
> +static int clk_mt8173_mfgtop_power_off(struct generic_pm_domain *domain)
> +{
> + struct mt8173_mfgtop_data *data = container_of(domain, struct mt8173_mfgtop_data, genpd);
> +
> + /* Magic numbers related to core switch sequence and delays */
> + regmap_write(data->regmap, 0xec, 0);
> +
> + /* drives internal power management */
> + clk_disable_unprepare(data->clk_26m);
> +
> + return 0;
> +}
> +
> +static int clk_mt8173_mfgtop_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *node = dev->of_node;
> + struct mt8173_mfgtop_data *data;
> + int ret;
> +
> + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
> + if (!data)
> + return -ENOMEM;
> +
> + platform_set_drvdata(pdev, data);
> +
> + data->clk_data = mtk_devm_alloc_clk_data(dev, ARRAY_SIZE(mfg_clks));
> + if (!data->clk_data)
> + return -ENOMEM;
> +
> + /* MTK clock gates also uses regmap */
> + data->regmap = device_node_to_regmap(node);
> + if (IS_ERR(data->regmap))
> + return dev_err_probe(dev, PTR_ERR(data->regmap), "Failed to get regmap\n");
> +
> + data->child_pd.np = node;
> + data->child_pd.args_count = 0;
> + ret = of_parse_phandle_with_args(node, "power-domains", "#power-domain-cells", 0,
> + &data->parent_pd);
> + if (ret)
> + return dev_err_probe(dev, ret, "Failed to parse power domain\n");
> +
> + devm_pm_runtime_enable(dev);
> + /*
> + * Do a pm_runtime_resume_and_get() to workaround a possible
> + * deadlock between clk_register() and the genpd framework.
> + */
> + ret = pm_runtime_resume_and_get(dev);
> + if (ret) {
> + dev_err_probe(dev, ret, "Failed to runtime resume device\n");
> + goto put_of_node;
> + }
> +
> + ret = mtk_clk_register_gates(dev, node, mfg_clks, ARRAY_SIZE(mfg_clks),
> + data->clk_data);
> + if (ret) {
> + dev_err_probe(dev, ret, "Failed to register clock gates\n");
> + goto put_pm_runtime;
> + }
> +
> + data->clk_26m = clk_hw_get_clk(data->clk_data->hws[CLK_MFG_26M], "26m");
> + if (IS_ERR(data->clk_26m)) {
> + dev_err_probe(dev, PTR_ERR(data->clk_26m), "Failed to get 26 MHz clock\n");
> + goto unregister_clks;
> + }
> +
> + ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, data->clk_data);
> + if (ret) {
> + dev_err_probe(dev, ret, "Failed to add clk OF provider\n");
> + goto put_26m_clk;
> + }
> +
> + data->genpd.name = "mfg-top";
> + data->genpd.power_on = clk_mt8173_mfgtop_power_on;
> + data->genpd.power_off = clk_mt8173_mfgtop_power_off;
> + ret = pm_genpd_init(&data->genpd, NULL, true);
> + if (ret) {
> + dev_err_probe(dev, ret, "Failed to add power domain\n");
> + goto del_clk_provider;
> + }
> +
> + ret = of_genpd_add_provider_simple(node, &data->genpd);
> + if (ret) {
> + dev_err_probe(dev, ret, "Failed to add power domain OF provider\n");
> + goto remove_pd;
> + }
> +
> + ret = of_genpd_add_subdomain(&data->parent_pd, &data->child_pd);
> + if (ret) {
> + dev_err_probe(dev, ret, "Failed to link PM domains\n");
> + goto del_pd_provider;
> + }
> +
> + pm_runtime_put(dev);
> + return 0;
> +
> +del_pd_provider:
> + of_genpd_del_provider(node);
> +remove_pd:
> + pm_genpd_remove(&data->genpd);
> +del_clk_provider:
> + of_clk_del_provider(node);
> +put_26m_clk:
> + clk_put(data->clk_26m);
> +unregister_clks:
> + mtk_clk_unregister_gates(mfg_clks, ARRAY_SIZE(mfg_clks), data->clk_data);
> +put_pm_runtime:
> + pm_runtime_put(dev);
> +put_of_node:
> + of_node_put(data->parent_pd.np);
> + return ret;
> +}
> +
> +static void clk_mt8173_mfgtop_remove(struct platform_device *pdev)
> +{
> + struct mt8173_mfgtop_data *data = platform_get_drvdata(pdev);
> + struct device_node *node = pdev->dev.of_node;
> +
> + of_genpd_remove_subdomain(&data->parent_pd, &data->child_pd);
> + of_genpd_del_provider(node);
> + pm_genpd_remove(&data->genpd);
> + of_clk_del_provider(node);
> + clk_put(data->clk_26m);
> + mtk_clk_unregister_gates(mfg_clks, ARRAY_SIZE(mfg_clks), data->clk_data);
> +}
> +
> +static const struct of_device_id of_match_clk_mt8173_mfgtop[] = {
> + { .compatible = "mediatek,mt8173-mfgtop", .data = &mfg_desc },
Is the match data and mfg_desc used?
Brian
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, of_match_clk_mt8173_mfgtop);
> +
> +static struct platform_driver clk_mt8173_mfgtop_drv = {
> + .probe = clk_mt8173_mfgtop_probe,
> + .remove = clk_mt8173_mfgtop_remove,
> + .driver = {
> + .name = "clk-mt8173-mfgtop",
> + .of_match_table = of_match_clk_mt8173_mfgtop,
> + },
> +};
> +module_platform_driver(clk_mt8173_mfgtop_drv);
> +
> +MODULE_DESCRIPTION("MediaTek MT8173 mfgtop clock driver");
> +MODULE_LICENSE("GPL");
> --
> 2.53.0.1018.g2bb0e51243-goog
>
^ permalink raw reply
* [PATCH v8 00/23] CoreSight: Refactor power management for CoreSight path
From: Leo Yan @ 2026-03-25 14:26 UTC (permalink / raw)
To: Suzuki K Poulose, Mike Leach, James Clark, Yeoreum Yun,
Mark Rutland, Will Deacon, Yabin Cui, Keita Morisaki,
Yuanfang Zhang, Greg Kroah-Hartman, Alexander Shishkin
Cc: coresight, linux-arm-kernel, Leo Yan, Mike Leach
This series focuses on CoreSight path power management. The changes can
be divided into four parts for review:
Patches 01 - 08: Refactor the CPU idle flow with moving common code into
the CoreSight core layer.
Patches 09 - 18: Refactor path enabling and disabling with range, add
path control during CPU idle.
Patches 19 - 20: Support the sink (TRBE) control during CPU idle.
Patches 21 - 23: Move the CPU hotplug flow into the coresight core layer
and simplify the code.
This series is rebased on the coresight-next branch and has been verified
on Juno-r2 (ETM + ETR) and FVP RevC (ETE + TRBE).
---
Changes in v8:
- Moved the "cpu" field in coresight_device for better pack with new
patch 01 (Suzuki).
- Added check if not set CPU for per_cpu_source/per_cpu_sink (Suzuki).
- Renamed spinlock name in syscfg (Suzuki).
- Refactored paired enable and disable path with new patches
10 and 12 (Suzuki).
- Link to v7: https://lore.kernel.org/r/20260320-arm_coresight_path_power_management_improvement-v7-0-327ddd36b58b@arm.com
Changes in v7:
- Added a flag in coresight_desc to indicate CPU bound device (Suzuki).
- Used coresight_mutex to protect per-CPU source pointer (Suzuki).
- Added a spinlock for exclusive access per-CPU source pointer (Suzuki).
- Dropped .pm_is_needed() callback (Suzuki).
- Supported range in path enabling / disabling (Suzuki).
- Gathered test and review tags (Levi / James).
- Link to v6: https://lore.kernel.org/r/20260305-arm_coresight_path_power_management_improvement-v6-0-eff765d211a9@arm.com
Changes in v6:
- Rebase on the latest coresight-next branch.
- Always save and restore TRBE context during idle (Will).
- Use get_cpu() / put_cpu() when set the per CPU source pointer.
- Link to v5: https://lore.kernel.org/r/20251119-arm_coresight_path_power_management_improvement-v5-0-f615a301ad0b@arm.com
Signed-off-by: Leo Yan <leo.yan@arm.com>
---
Leo Yan (22):
coresight: Extract device init into coresight_init_dev()
coresight: Populate CPU ID into coresight_device
coresight: Remove .cpu_id() callback from source ops
coresight: sysfs: Validate CPU online status for per-CPU sources
coresight: Move per-CPU source pointer to core layer
coresight: Register CPU PM notifier in core layer
coresight: etm4x: Hook CPU PM callbacks
coresight: etm4x: Remove redundant condition checks in save and restore
coresight: syscfg: Use spinlock to protect active variables
coresight: Move source helper disabling to coresight_disable_path()
coresight: Control path with range
coresight: Use helpers to fetch first and last nodes
coresight: Introduce coresight_enable_source() helper
coresight: Save active path for system tracers
coresight: etm4x: Set active path on target CPU
coresight: etm3x: Set active path on target CPU
coresight: sysfs: Use source's path pointer for path control
coresight: Control path during CPU idle
coresight: Add PM callbacks for sink device
coresight: sysfs: Increment refcount only for system tracers
coresight: Take hotplug lock in enable_source_store() for Sysfs mode
coresight: Move CPU hotplug callbacks to core layer
Yabin Cui (1):
coresight: trbe: Save and restore state across CPU low power state
drivers/hwtracing/coresight/coresight-catu.c | 2 +-
drivers/hwtracing/coresight/coresight-core.c | 428 ++++++++++++++++++---
drivers/hwtracing/coresight/coresight-cti-core.c | 9 +-
drivers/hwtracing/coresight/coresight-etm-perf.c | 25 +-
drivers/hwtracing/coresight/coresight-etm3x-core.c | 73 +---
drivers/hwtracing/coresight/coresight-etm4x-core.c | 154 ++------
drivers/hwtracing/coresight/coresight-priv.h | 4 +
drivers/hwtracing/coresight/coresight-syscfg.c | 21 +-
drivers/hwtracing/coresight/coresight-syscfg.h | 2 +
drivers/hwtracing/coresight/coresight-sysfs.c | 126 ++----
drivers/hwtracing/coresight/coresight-trbe.c | 61 ++-
include/linux/coresight.h | 15 +-
12 files changed, 570 insertions(+), 350 deletions(-)
---
base-commit: a90863095f84f6d17c49716e4e2212d28a6b25b5
change-id: 20251104-arm_coresight_path_power_management_improvement-dab4966f8280
Best regards,
--
Leo Yan <leo.yan@arm.com>
^ permalink raw reply
* [PATCH v8 01/23] coresight: Extract device init into coresight_init_dev()
From: Leo Yan @ 2026-03-25 14:26 UTC (permalink / raw)
To: Suzuki K Poulose, Mike Leach, James Clark, Yeoreum Yun,
Mark Rutland, Will Deacon, Yabin Cui, Keita Morisaki,
Yuanfang Zhang, Greg Kroah-Hartman, Alexander Shishkin
Cc: coresight, linux-arm-kernel, Leo Yan
In-Reply-To: <20260325-arm_coresight_path_power_management_improvement-v8-0-7b1902e18041@arm.com>
Use a new function coresight_init_dev() for device structure allocation
and initialization. This makes it easier to extend with additional
initialization operations in the future.
Signed-off-by: Leo Yan <leo.yan@arm.com>
---
drivers/hwtracing/coresight/coresight-core.c | 27 +++++++++++++++++++--------
1 file changed, 19 insertions(+), 8 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c
index 46f247f73cf64a97b9353b84ba5b76b991676f5f..5452de9367d450de399a2107016c3fddb894fc82 100644
--- a/drivers/hwtracing/coresight/coresight-core.c
+++ b/drivers/hwtracing/coresight/coresight-core.c
@@ -1322,20 +1322,16 @@ void coresight_release_platform_data(struct device *dev,
devm_kfree(dev, pdata);
}
-struct coresight_device *coresight_register(struct coresight_desc *desc)
+static struct coresight_device *
+coresight_init_device(struct coresight_desc *desc)
{
- int ret;
struct coresight_device *csdev;
- bool registered = false;
csdev = kzalloc_obj(*csdev);
- if (!csdev) {
- ret = -ENOMEM;
- goto err_out;
- }
+ if (!csdev)
+ return ERR_PTR(-ENOMEM);
csdev->pdata = desc->pdata;
-
csdev->type = desc->type;
csdev->subtype = desc->subtype;
csdev->ops = desc->ops;
@@ -1348,6 +1344,21 @@ struct coresight_device *coresight_register(struct coresight_desc *desc)
csdev->dev.release = coresight_device_release;
csdev->dev.bus = &coresight_bustype;
+ return csdev;
+}
+
+struct coresight_device *coresight_register(struct coresight_desc *desc)
+{
+ int ret;
+ struct coresight_device *csdev;
+ bool registered = false;
+
+ csdev = coresight_init_device(desc);
+ if (IS_ERR(csdev)) {
+ ret = PTR_ERR(csdev);
+ goto err_out;
+ }
+
if (csdev->type == CORESIGHT_DEV_TYPE_SINK ||
csdev->type == CORESIGHT_DEV_TYPE_LINKSINK) {
raw_spin_lock_init(&csdev->perf_sink_id_map.lock);
--
2.34.1
^ permalink raw reply related
* Re: [PATCH v5 5/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics mp15 boards
From: Patrice CHOTARD @ 2026-03-25 14:25 UTC (permalink / raw)
To: Alexandre Torgue, Marek Vasut, Jagan Teki
Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel, kernel,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin,
Patrick Delaunay, Christoph Niedermaier
In-Reply-To: <20260123-upstream_uboot_properties-v5-5-5167929d5af5@foss.st.com>
Hi Jagan, Marek
Any remarks on these Engicam MicroGEA/ICORE/DHCOM/DHCOR dt update ?
Thanks
Patrice
On 1/23/26 11:14, Patrice Chotard wrote:
> The bootph-all flag was introduced in dt-schema
> (dtschema/schemas/bootph.yaml) to define node usage across
> different boot phases.
>
> To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be
> present in all boot stages, so add missing bootph-all phase flag
> to these nodes to support SD boot.
>
> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
> ---
> arch/arm/boot/dts/st/stm32mp151.dtsi | 2 +-
> arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts | 19 +++
> .../st/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts | 1 +
> .../dts/st/stm32mp157a-icore-stm32mp1-ctouch2.dts | 25 +++
> .../dts/st/stm32mp157a-icore-stm32mp1-edimm2.2.dts | 26 ++++
> .../boot/dts/st/stm32mp157a-icore-stm32mp1.dtsi | 100 ++++++++++++
> ...m32mp157a-microgea-stm32mp1-microdev2.0-of7.dts | 27 ++++
> .../stm32mp157a-microgea-stm32mp1-microdev2.0.dts | 27 ++++
> .../boot/dts/st/stm32mp157a-microgea-stm32mp1.dtsi | 97 ++++++++++++
> arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts | 5 +
> arch/arm/boot/dts/st/stm32mp157c-dk2.dts | 1 +
> arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts | 19 +++
> arch/arm/boot/dts/st/stm32mp157c-ed1.dts | 151 ++++++++++++++++++
> arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts | 5 +
> arch/arm/boot/dts/st/stm32mp157c-ev1.dts | 38 +++++
> arch/arm/boot/dts/st/stm32mp157c-lxa-mc1.dts | 1 +
> arch/arm/boot/dts/st/stm32mp157c-odyssey-som.dtsi | 119 ++++++++++++++
> arch/arm/boot/dts/st/stm32mp157c-odyssey.dts | 21 +++
> arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts | 1 +
> arch/arm/boot/dts/st/stm32mp157f-dk2-scmi.dtsi | 5 +
> arch/arm/boot/dts/st/stm32mp157f-dk2.dts | 1 +
> arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi | 1 +
> arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi | 172 +++++++++++++++++++++
> .../boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi | 55 +++++++
> .../boot/dts/st/stm32mp15xx-dhcor-drc-compact.dtsi | 50 ++++++
> arch/arm/boot/dts/st/stm32mp15xx-dhcor-som.dtsi | 157 +++++++++++++++++++
> .../boot/dts/st/stm32mp15xx-dhcor-testbench.dtsi | 50 ++++++
> arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi | 122 +++++++++++++++
> 28 files changed, 1297 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/st/stm32mp151.dtsi b/arch/arm/boot/dts/st/stm32mp151.dtsi
> index b1b568dfd126..ada55b2c1aa2 100644
> --- a/arch/arm/boot/dts/st/stm32mp151.dtsi
> +++ b/arch/arm/boot/dts/st/stm32mp151.dtsi
> @@ -30,7 +30,7 @@ arm-pmu {
> interrupt-parent = <&intc>;
> };
>
> - psci {
> + psci: psci {
> compatible = "arm,psci-1.0";
> method = "smc";
> };
> diff --git a/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts
> index 847b360f02fc..b81b6e168b67 100644
> --- a/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts
> +++ b/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts
> @@ -65,6 +65,7 @@ &m4_rproc {
> &optee {
> interrupt-parent = <&intc>;
> interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
> + bootph-some-ram;
> };
>
> &rcc {
> @@ -85,3 +86,21 @@ &rng1 {
> &rtc {
> clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
> };
> +
> +&scmi {
> + bootph-some-ram;
> +};
> +
> +&uart4 {
> + bootph-all;
> +};
> +
> +&uart4_pins_a {
> + bootph-all;
> + pins1 {
> + bootph-all;
> + };
> + pins2 {
> + bootph-all;
> + };
> +};
> diff --git a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts
> index df97e03d2a5a..4ad1313efca9 100644
> --- a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts
> +++ b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2-of10.dts
> @@ -92,6 +92,7 @@ bridge_out: endpoint {
> };
>
> <dc {
> + bootph-some-ram;
> status = "okay";
>
> port {
> diff --git a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2.dts b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2.dts
> index 60ce4425a7fd..ac4e313ca371 100644
> --- a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2.dts
> +++ b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-ctouch2.dts
> @@ -35,15 +35,40 @@ &sdmmc1 {
> pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
> st,neg-edge;
> vmmc-supply = <&v3v3>;
> + bootph-all;
> status = "okay";
> };
>
> +&sdmmc1_b4_pins_a {
> + bootph-all;
> + pins1 {
> + bootph-all;
> + };
> +
> + pins2 {
> + bootph-all;
> + };
> +};
> +
> &uart4 {
> pinctrl-names = "default", "sleep", "idle";
> pinctrl-0 = <&uart4_pins_a>;
> pinctrl-1 = <&uart4_sleep_pins_a>;
> pinctrl-2 = <&uart4_idle_pins_a>;
> + bootph-all;
> /delete-property/dmas;
> /delete-property/dma-names;
> status = "okay";
> };
> +
> +&uart4_pins_a {
> + bootph-all;
> + pins1 {
> + bootph-all;
> + };
> +
> + pins2 {
> + bootph-all;
> + bias-pull-up;
> + };
> +};
> diff --git a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-edimm2.2.dts b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-edimm2.2.dts
> index f8e404346396..cc24a29fba15 100644
> --- a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-edimm2.2.dts
> +++ b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1-edimm2.2.dts
> @@ -92,6 +92,7 @@ bridge_out_panel: endpoint {
> };
>
> <dc {
> + bootph-some-ram;
> status = "okay";
>
> port {
> @@ -110,15 +111,40 @@ &sdmmc1 {
> pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
> st,neg-edge;
> vmmc-supply = <&v3v3>;
> + bootph-all;
> status = "okay";
> };
>
> +&sdmmc1_b4_pins_a {
> + bootph-all;
> + pins1 {
> + bootph-all;
> + };
> +
> + pins2 {
> + bootph-all;
> + };
> +};
> +
> &uart4 {
> pinctrl-names = "default", "sleep", "idle";
> pinctrl-0 = <&uart4_pins_a>;
> pinctrl-1 = <&uart4_sleep_pins_a>;
> pinctrl-2 = <&uart4_idle_pins_a>;
> + bootph-all;
> /delete-property/dmas;
> /delete-property/dma-names;
> status = "okay";
> };
> +
> +&uart4_pins_a {
> + bootph-all;
> + pins1 {
> + bootph-all;
> + };
> +
> + pins2 {
> + bootph-all;
> + bias-pull-up;
> + };
> +};
> diff --git a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1.dtsi b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1.dtsi
> index 569a7e940ecc..db93934019d1 100644
> --- a/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1.dtsi
> +++ b/arch/arm/boot/dts/st/stm32mp157a-icore-stm32mp1.dtsi
> @@ -61,6 +61,7 @@ vddcore: regulator-vddcore {
> regulator-min-microvolt = <1200000>;
> regulator-max-microvolt = <1200000>;
> regulator-always-on;
> + bootph-all;
> };
>
> vdd: regulator-vdd {
> @@ -69,6 +70,7 @@ vdd: regulator-vdd {
> regulator-min-microvolt = <3300000>;
> regulator-max-microvolt = <3300000>;
> regulator-always-on;
> + bootph-all;
> };
>
> vdd_usb: regulator-vdd-usb {
> @@ -77,6 +79,7 @@ vdd_usb: regulator-vdd-usb {
> regulator-min-microvolt = <3300000>;
> regulator-max-microvolt = <3300000>;
> regulator-always-on;
> + bootph-all;
> };
>
> vdda: regulator-vdda {
> @@ -85,6 +88,7 @@ vdda: regulator-vdda {
> regulator-min-microvolt = <3300000>;
> regulator-max-microvolt = <3300000>;
> regulator-always-on;
> + bootph-all;
> };
>
> vdd_ddr: regulator-vdd-ddr {
> @@ -93,6 +97,7 @@ vdd_ddr: regulator-vdd-ddr {
> regulator-min-microvolt = <1350000>;
> regulator-max-microvolt = <1350000>;
> regulator-always-on;
> + bootph-all;
> };
>
> vtt_ddr: regulator-vtt-ddr {
> @@ -102,6 +107,7 @@ vtt_ddr: regulator-vtt-ddr {
> regulator-max-microvolt = <675000>;
> regulator-always-on;
> vin-supply = <&vdd>;
> + bootph-all;
> };
>
> vref_ddr: regulator-vref-ddr {
> @@ -111,6 +117,7 @@ vref_ddr: regulator-vref-ddr {
> regulator-max-microvolt = <675000>;
> regulator-always-on;
> vin-supply = <&vdd>;
> + bootph-all;
> };
>
> vdd_sd: regulator-vdd-sd {
> @@ -119,6 +126,7 @@ vdd_sd: regulator-vdd-sd {
> regulator-min-microvolt = <3300000>;
> regulator-max-microvolt = <3300000>;
> regulator-always-on;
> + bootph-all;
> };
>
> v3v3: regulator-v3v3 {
> @@ -127,6 +135,7 @@ v3v3: regulator-v3v3 {
> regulator-min-microvolt = <3300000>;
> regulator-max-microvolt = <3300000>;
> regulator-always-on;
> + bootph-all;
> };
>
> v2v8: regulator-v2v8 {
> @@ -136,6 +145,7 @@ v2v8: regulator-v2v8 {
> regulator-max-microvolt = <2800000>;
> regulator-always-on;
> vin-supply = <&v3v3>;
> + bootph-all;
> };
>
> v1v8: regulator-v1v8 {
> @@ -145,13 +155,86 @@ v1v8: regulator-v1v8 {
> regulator-max-microvolt = <1800000>;
> regulator-always-on;
> vin-supply = <&v3v3>;
> + bootph-all;
> };
> };
>
> +&bsec {
> + bootph-all;
> +};
> +
> +&clk_hse {
> + bootph-all;
> +};
> +
> +&clk_hsi {
> + bootph-all;
> +};
> +
> +&clk_lse {
> + bootph-all;
> +};
> +
> +&clk_lsi {
> + bootph-all;
> +};
> +
> +&clk_csi {
> + bootph-all;
> +};
> +
> &dts {
> status = "okay";
> };
>
> +&gpioa {
> + bootph-all;
> +};
> +
> +&gpiob {
> + bootph-all;
> +};
> +
> +&gpioc {
> + bootph-all;
> +};
> +
> +&gpiod {
> + bootph-all;
> +};
> +
> +&gpioe {
> + bootph-all;
> +};
> +
> +&gpiof {
> + bootph-all;
> +};
> +
> +&gpiog {
> + bootph-all;
> +};
> +
> +&gpioh {
> + bootph-all;
> +};
> +
> +&gpioi {
> + bootph-all;
> +};
> +
> +&gpioj {
> + bootph-all;
> +};
> +
> +&gpiok {
> + bootph-all;
> +};
> +
> +&gpioz {
> + bootph-all;
> +};
> +
> &i2c2 {
> i2c-scl-falling-time-ns = <20>;
> i2c-scl-rising-time-ns = <185>;
> @@ -167,6 +250,7 @@ &ipcc {
>
> &iwdg2 {
> timeout-sec = <32>;
> + bootph-all;
> status = "okay";
> };
>
> @@ -180,6 +264,22 @@ &m4_rproc {
> status = "okay";
> };
>
> +&pinctrl {
> + bootph-all;
> +};
> +
> +&pinctrl_z {
> + bootph-all;
> +};
> +
> +&psci {
> + bootph-some-ram;
> +};
> +
> +&rcc {
> + bootph-all;
> +};
> +
> &rng1 {
> status = "okay";
> };
> diff --git a/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts b/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
> index 5116a7785201..7bfd7da4a8db 100644
> --- a/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
> +++ b/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dts
> @@ -78,6 +78,7 @@ &i2c2 {
> <dc {
> pinctrl-names = "default";
> pinctrl-0 = <<dc_pins>;
> + bootph-some-ram;
> status = "okay";
>
> port {
> @@ -134,19 +135,45 @@ &sdmmc1 {
> pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
> st,neg-edge;
> vmmc-supply = <&vdd>;
> + bootph-all;
> status = "okay";
> };
>
> +&sdmmc1_b4_pins_a {
> + bootph-all;
> +
> + pins1 {
> + bootph-all;
> + };
> +
> + pins2 {
> + bootph-all;
> + };
> +};
> +
> &uart4 {
> pinctrl-names = "default", "sleep", "idle";
> pinctrl-0 = <&uart4_pins_a>;
> pinctrl-1 = <&uart4_sleep_pins_a>;
> pinctrl-2 = <&uart4_idle_pins_a>;
> + bootph-all;
> /delete-property/dmas;
> /delete-property/dma-names;
> status = "okay";
> };
>
> +&uart4_pins_a {
> + bootph-all;
> +
> + pins1 {
> + bootph-all;
> + };
> +
> + pins2 {
> + bootph-all;
> + };
> +};
> +
> /* J31: RS323 */
> &uart8 {
> pinctrl-names = "default";
> diff --git a/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0.dts b/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0.dts
> index d949559be020..a1f79659d7c5 100644
> --- a/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0.dts
> +++ b/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1-microdev2.0.dts
> @@ -36,19 +36,46 @@ &sdmmc1 {
> pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
> st,neg-edge;
> vmmc-supply = <&vdd>;
> + bootph-all;
> status = "okay";
> };
>
> +&sdmmc1_b4_pins_a {
> + bootph-all;
> +
> + pins1 {
> + bootph-all;
> + };
> +
> + pins2 {
> + bootph-all;
> + };
> +};
> +
> &uart4 {
> pinctrl-names = "default", "sleep", "idle";
> pinctrl-0 = <&uart4_pins_a>;
> pinctrl-1 = <&uart4_sleep_pins_a>;
> pinctrl-2 = <&uart4_idle_pins_a>;
> + bootph-all;
> /delete-property/dmas;
> /delete-property/dma-names;
> status = "okay";
> };
>
> +&uart4_pins_a {
> + bootph-all;
> +
> + pins1 {
> + bootph-all;
> + };
> +
> + pins2 {
> + bootph-all;
> + bias-pull-up;
> + };
> +};
> +
> /* J31: RS323 */
> &uart8 {
> pinctrl-names = "default";
> diff --git a/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1.dtsi b/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1.dtsi
> index a75f50cf7123..4f6f4712d634 100644
> --- a/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1.dtsi
> +++ b/arch/arm/boot/dts/st/stm32mp157a-microgea-stm32mp1.dtsi
> @@ -61,6 +61,7 @@ vin: regulator-vin {
> regulator-min-microvolt = <5000000>;
> regulator-max-microvolt = <5000000>;
> regulator-always-on;
> + bootph-all;
> };
>
> vddcore: regulator-vddcore {
> @@ -70,6 +71,7 @@ vddcore: regulator-vddcore {
> regulator-max-microvolt = <1200000>;
> regulator-always-on;
> vin-supply = <&vin>;
> + bootph-all;
> };
>
> vdd: regulator-vdd {
> @@ -79,6 +81,7 @@ vdd: regulator-vdd {
> regulator-max-microvolt = <3300000>;
> regulator-always-on;
> vin-supply = <&vin>;
> + bootph-all;
> };
>
> vddq_ddr: regulator-vddq-ddr {
> @@ -88,9 +91,34 @@ vddq_ddr: regulator-vddq-ddr {
> regulator-max-microvolt = <1350000>;
> regulator-always-on;
> vin-supply = <&vin>;
> + bootph-all;
> };
> };
>
> +&bsec {
> + bootph-all;
> +};
> +
> +&clk_hse {
> + bootph-all;
> +};
> +
> +&clk_hsi {
> + bootph-all;
> +};
> +
> +&clk_lse {
> + bootph-all;
> +};
> +
> +&clk_lsi {
> + bootph-all;
> +};
> +
> +&clk_csi {
> + bootph-all;
> +};
> +
> &dts {
> status = "okay";
> };
> @@ -113,12 +141,61 @@ nand@0 {
> };
> };
>
> +&gpioa {
> + bootph-all;
> +};
> +
> +&gpiob {
> + bootph-all;
> +};
> +
> +&gpioc {
> + bootph-all;
> +};
> +
> +&gpiod {
> + bootph-all;
> +};
> +
> +&gpioe {
> + bootph-all;
> +};
> +
> +&gpiof {
> + bootph-all;
> +};
> +
> +&gpiog {
> + bootph-all;
> +};
> +
> +&gpioh {
> + bootph-all;
> +};
> +
> +&gpioi {
> + bootph-all;
> +};
> +
> +&gpioj {
> + bootph-all;
> +};
> +
> +&gpiok {
> + bootph-all;
> +};
> +
> +&gpioz {
> + bootph-all;
> +};
> +
> &ipcc {
> status = "okay";
> };
>
> &iwdg2 {
> timeout-sec = <32>;
> + bootph-all;
> status = "okay";
> };
>
> @@ -132,6 +209,26 @@ &m4_rproc {
> status = "okay";
> };
>
> +&pinctrl {
> + bootph-all;
> +};
> +
> +&pinctrl_z {
> + bootph-all;
> +};
> +
> +&psci {
> + bootph-some-ram;
> +};
> +
> +&pwr_regulators {
> + bootph-all;
> +};
> +
> +&rcc {
> + bootph-all;
> +};
> +
> &rng1 {
> status = "okay";
> };
> diff --git a/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts b/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts
> index 43280289759d..e192d033626e 100644
> --- a/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts
> +++ b/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts
> @@ -71,6 +71,7 @@ &m4_rproc {
> &optee {
> interrupt-parent = <&intc>;
> interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
> + bootph-some-ram;
> };
>
> &rcc {
> @@ -91,3 +92,7 @@ &rng1 {
> &rtc {
> clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
> };
> +
> +&scmi {
> + bootph-some-ram;
> +};
> diff --git a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts
> index 1ec3b8f2faa9..bf9fdf0d611c 100644
> --- a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts
> +++ b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts
> @@ -80,6 +80,7 @@ touchscreen@38 {
> };
>
> <dc {
> + bootph-some-ram;
> status = "okay";
>
> port {
> diff --git a/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts
> index 6f27d794d270..f053a70cb254 100644
> --- a/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts
> +++ b/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts
> @@ -70,6 +70,7 @@ &m4_rproc {
> &optee {
> interrupt-parent = <&intc>;
> interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
> + bootph-some-ram;
> };
>
> &rcc {
> @@ -90,3 +91,21 @@ &rng1 {
> &rtc {
> clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
> };
> +
> +&scmi {
> + bootph-some-ram;
> +};
> +
> +&uart4 {
> + bootph-all;
> +};
> +
> +&uart4_pins_a {
> + bootph-all;
> + pins1 {
> + bootph-all;
> + };
> + pins2 {
> + bootph-all;
> + };
> +};
> diff --git a/arch/arm/boot/dts/st/stm32mp157c-ed1.dts b/arch/arm/boot/dts/st/stm32mp157c-ed1.dts
> index f6c478dbd041..86919bb642fa 100644
> --- a/arch/arm/boot/dts/st/stm32mp157c-ed1.dts
> +++ b/arch/arm/boot/dts/st/stm32mp157c-ed1.dts
> @@ -132,6 +132,31 @@ channel@6 {
> };
> };
>
> +
> +&bsec {
> + bootph-all;
> +};
> +
> +&clk_hse {
> + bootph-all;
> +};
> +
> +&clk_hsi {
> + bootph-all;
> +};
> +
> +&clk_lse {
> + bootph-all;
> +};
> +
> +&clk_lsi {
> + bootph-all;
> +};
> +
> +&clk_csi {
> + bootph-all;
> +};
> +
> &crc1 {
> status = "okay";
> };
> @@ -157,6 +182,54 @@ &dts {
> status = "okay";
> };
>
> +&gpioa {
> + bootph-all;
> +};
> +
> +&gpiob {
> + bootph-all;
> +};
> +
> +&gpioc {
> + bootph-all;
> +};
> +
> +&gpiod {
> + bootph-all;
> +};
> +
> +&gpioe {
> + bootph-all;
> +};
> +
> +&gpiof {
> + bootph-all;
> +};
> +
> +&gpiog {
> + bootph-all;
> +};
> +
> +&gpioh {
> + bootph-all;
> +};
> +
> +&gpioi {
> + bootph-all;
> +};
> +
> +&gpioj {
> + bootph-all;
> +};
> +
> +&gpiok {
> + bootph-all;
> +};
> +
> +&gpioz {
> + bootph-all;
> +};
> +
> &hash1 {
> status = "okay";
> };
> @@ -168,7 +241,9 @@ &i2c4 {
> i2c-scl-rising-time-ns = <185>;
> i2c-scl-falling-time-ns = <20>;
> clock-frequency = <400000>;
> + bootph-all;
> status = "okay";
> +
> /* spare dmas for other usage */
> /delete-property/dmas;
> /delete-property/dma-names;
> @@ -179,6 +254,7 @@ pmic: stpmic@33 {
> interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
> interrupt-controller;
> #interrupt-cells = <2>;
> + bootph-all;
> status = "okay";
>
> regulators {
> @@ -314,12 +390,20 @@ watchdog {
> };
> };
>
> +&i2c4_pins_a {
> + bootph-all;
> + pins {
> + bootph-all;
> + };
> +};
> +
> &ipcc {
> status = "okay";
> };
>
> &iwdg2 {
> timeout-sec = <32>;
> + bootph-all;
> status = "okay";
> };
>
> @@ -335,9 +419,26 @@ &m4_rproc {
> status = "okay";
> };
>
> +&pinctrl {
> + bootph-all;
> +};
> +
> +&pinctrl_z {
> + bootph-all;
> +};
> +
> +&psci {
> + bootph-some-ram;
> +};
> +
> &pwr_regulators {
> vdd-supply = <&vdd>;
> vdd_3v3_usbfs-supply = <&vdd_usb>;
> + bootph-all;
> +};
> +
> +&rcc {
> + bootph-all;
> };
>
> &rng1 {
> @@ -365,9 +466,30 @@ &sdmmc1 {
> sd-uhs-sdr25;
> sd-uhs-sdr50;
> sd-uhs-ddr50;
> + bootph-pre-ram;
> status = "okay";
> };
>
> +&sdmmc1_b4_pins_a {
> + bootph-pre-ram;
> + pins1 {
> + bootph-pre-ram;
> + };
> + pins2 {
> + bootph-pre-ram;
> + };
> +};
> +
> +&sdmmc1_dir_pins_a {
> + bootph-pre-ram;
> + pins1 {
> + bootph-pre-ram;
> + };
> + pins2 {
> + bootph-pre-ram;
> + };
> +};
> +
> &sdmmc2 {
> pinctrl-names = "default", "opendrain", "sleep";
> pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
> @@ -381,9 +503,27 @@ &sdmmc2 {
> vmmc-supply = <&v3v3>;
> vqmmc-supply = <&vdd>;
> mmc-ddr-3_3v;
> + bootph-pre-ram;
> status = "okay";
> };
>
> +&sdmmc2_b4_pins_a {
> + bootph-pre-ram;
> + pins1 {
> + bootph-pre-ram;
> + };
> + pins2 {
> + bootph-pre-ram;
> + };
> +};
> +
> +&sdmmc2_d47_pins_a {
> + bootph-pre-ram;
> + pins {
> + bootph-pre-ram;
> + };
> +};
> +
> &timers6 {
> status = "okay";
> /* spare dmas for other usage */
> @@ -399,11 +539,22 @@ &uart4 {
> pinctrl-0 = <&uart4_pins_a>;
> pinctrl-1 = <&uart4_sleep_pins_a>;
> pinctrl-2 = <&uart4_idle_pins_a>;
> + bootph-all;
> /delete-property/dmas;
> /delete-property/dma-names;
> status = "okay";
> };
>
> +&uart4_pins_a {
> + bootph-all;
> + pins1 {
> + bootph-all;
> + };
> + pins2 {
> + bootph-all;
> + };
> +};
> +
> &usbotg_hs {
> vbus-supply = <&vbus_otg>;
> };
> diff --git a/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts
> index 6ae391bffee5..17295d67ab85 100644
> --- a/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts
> +++ b/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts
> @@ -75,6 +75,7 @@ &m4_rproc {
> &optee {
> interrupt-parent = <&intc>;
> interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
> + bootph-some-ram;
> };
>
> &rcc {
> @@ -95,3 +96,7 @@ &rng1 {
> &rtc {
> clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
> };
> +
> +&scmi {
> + bootph-some-ram;
> +};
> diff --git a/arch/arm/boot/dts/st/stm32mp157c-ev1.dts b/arch/arm/boot/dts/st/stm32mp157c-ev1.dts
> index 8f99c30f1af1..d43bddc42ad9 100644
> --- a/arch/arm/boot/dts/st/stm32mp157c-ev1.dts
> +++ b/arch/arm/boot/dts/st/stm32mp157c-ev1.dts
> @@ -231,6 +231,7 @@ &i2c5 {
> };
>
> <dc {
> + bootph-some-ram;
> status = "okay";
>
> port {
> @@ -262,6 +263,7 @@ &qspi_bk2_sleep_pins_a
> reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
> #address-cells = <1>;
> #size-cells = <0>;
> + bootph-pre-ram;
> status = "okay";
>
> flash0: flash@0 {
> @@ -271,6 +273,7 @@ flash0: flash@0 {
> spi-max-frequency = <108000000>;
> #address-cells = <1>;
> #size-cells = <1>;
> + bootph-pre-ram;
> };
>
> flash1: flash@1 {
> @@ -283,6 +286,41 @@ flash1: flash@1 {
> };
> };
>
> +&qspi_clk_pins_a {
> + bootph-pre-ram;
> + pins {
> + bootph-pre-ram;
> + };
> +};
> +
> +&qspi_bk1_pins_a {
> + bootph-pre-ram;
> + pins {
> + bootph-pre-ram;
> + };
> +};
> +
> +&qspi_cs1_pins_a {
> + bootph-pre-ram;
> + pins {
> + bootph-pre-ram;
> + };
> +};
> +
> +&qspi_bk2_pins_a {
> + bootph-pre-ram;
> + pins {
> + bootph-pre-ram;
> + };
> +};
> +
> +&qspi_cs2_pins_a {
> + bootph-pre-ram;
> + pins {
> + bootph-pre-ram;
> + };
> +};
> +
> &sdmmc3 {
> pinctrl-names = "default", "opendrain", "sleep";
> pinctrl-0 = <&sdmmc3_b4_pins_a>;
> diff --git a/arch/arm/boot/dts/st/stm32mp157c-lxa-mc1.dts b/arch/arm/boot/dts/st/stm32mp157c-lxa-mc1.dts
> index eada9cf257be..9f513045c559 100644
> --- a/arch/arm/boot/dts/st/stm32mp157c-lxa-mc1.dts
> +++ b/arch/arm/boot/dts/st/stm32mp157c-lxa-mc1.dts
> @@ -158,6 +158,7 @@ <dc {
> pinctrl-names = "default", "sleep";
> pinctrl-0 = <<dc_pins_c>;
> pinctrl-1 = <<dc_sleep_pins_c>;
> + bootph-some-ram;
> status = "okay";
>
> port {
> diff --git a/arch/arm/boot/dts/st/stm32mp157c-odyssey-som.dtsi b/arch/arm/boot/dts/st/stm32mp157c-odyssey-som.dtsi
> index cf7485251490..1c5517f57ecd 100644
> --- a/arch/arm/boot/dts/st/stm32mp157c-odyssey-som.dtsi
> +++ b/arch/arm/boot/dts/st/stm32mp157c-odyssey-som.dtsi
> @@ -75,11 +75,84 @@ led-blue {
> };
> };
>
> +&bsec {
> + bootph-all;
> +};
> +
> +&clk_hse {
> + bootph-all;
> +};
> +
> +&clk_hsi {
> + bootph-all;
> +};
> +
> +&clk_lse {
> + bootph-all;
> +};
> +
> +&clk_lsi {
> + bootph-all;
> +};
> +
> +&clk_csi {
> + bootph-all;
> +};
> +
> +&gpioa {
> + bootph-all;
> +};
> +
> +&gpiob {
> + bootph-all;
> +};
> +
> +&gpioc {
> + bootph-all;
> +};
> +
> +&gpiod {
> + bootph-all;
> +};
> +
> +&gpioe {
> + bootph-all;
> +};
> +
> +&gpiof {
> + bootph-all;
> +};
> +
> +&gpiog {
> + bootph-all;
> +};
> +
> +&gpioh {
> + bootph-all;
> +};
> +
> +&gpioi {
> + bootph-all;
> +};
> +
> +&gpioj {
> + bootph-all;
> +};
> +
> +&gpiok {
> + bootph-all;
> +};
> +
> +&gpioz {
> + bootph-all;
> +};
> +
> &i2c2 {
> pinctrl-names = "default";
> pinctrl-0 = <&i2c2_pins_a>;
> i2c-scl-rising-time-ns = <185>;
> i2c-scl-falling-time-ns = <20>;
> + bootph-all;
> status = "okay";
> /* spare dmas for other usage */
> /delete-property/dmas;
> @@ -91,6 +164,7 @@ pmic: stpmic@33 {
> interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
> interrupt-controller;
> #interrupt-cells = <2>;
> + bootph-all;
>
> regulators {
> compatible = "st,stpmic1-regulators";
> @@ -218,12 +292,20 @@ watchdog {
> };
> };
>
> +&i2c2_pins_a {
> + bootph-all;
> + pins {
> + bootph-all;
> + };
> +};
> +
> &ipcc {
> status = "okay";
> };
>
> &iwdg2 {
> timeout-sec = <32>;
> + bootph-all;
> status = "okay";
> };
>
> @@ -237,6 +319,26 @@ &m4_rproc {
> status = "okay";
> };
>
> +&pinctrl {
> + bootph-all;
> +};
> +
> +&pinctrl_z {
> + bootph-all;
> +};
> +
> +&psci {
> + bootph-some-ram;
> +};
> +
> +&pwr_regulators {
> + bootph-all;
> +};
> +
> +&rcc {
> + bootph-all;
> +};
> +
> &rng1 {
> status = "okay";
> };
> @@ -258,6 +360,23 @@ &sdmmc2 {
> vmmc-supply = <&v3v3>;
> vqmmc-supply = <&vdd>;
> mmc-ddr-3_3v;
> + bootph-pre-ram;
> status = "okay";
> };
>
> +&sdmmc2_b4_pins_a {
> + bootph-pre-ram;
> + pins1 {
> + bootph-pre-ram;
> + };
> + pins2 {
> + bootph-pre-ram;
> + };
> +};
> +
> +&sdmmc2_d47_pins_d {
> + bootph-pre-ram;
> + pins {
> + bootph-pre-ram;
> + };
> +};
> diff --git a/arch/arm/boot/dts/st/stm32mp157c-odyssey.dts b/arch/arm/boot/dts/st/stm32mp157c-odyssey.dts
> index a8b3f7a54703..92bc25b3f563 100644
> --- a/arch/arm/boot/dts/st/stm32mp157c-odyssey.dts
> +++ b/arch/arm/boot/dts/st/stm32mp157c-odyssey.dts
> @@ -75,14 +75,35 @@ &sdmmc1 {
> st,neg-edge;
> bus-width = <4>;
> vmmc-supply = <&v3v3>;
> + bootph-pre-ram;
> status = "okay";
> };
>
> +&sdmmc1_b4_pins_a {
> + bootph-pre-ram;
> + pins1 {
> + bootph-pre-ram;
> + };
> + pins2 {
> + bootph-pre-ram;
> + };
> +};
> +
> &uart4 {
> pinctrl-names = "default";
> pinctrl-0 = <&uart4_pins_a>;
> + bootph-all;
> /delete-property/dmas;
> /delete-property/dma-names;
> status = "okay";
> };
>
> +&uart4_pins_a {
> + bootph-all;
> + pins1 {
> + bootph-all;
> + };
> + pins2 {
> + bootph-all;
> + };
> +};
> diff --git a/arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts b/arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts
> index 36e6055b5665..b404ea3752d9 100644
> --- a/arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts
> +++ b/arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts
> @@ -131,6 +131,7 @@ i2s2_endpoint: endpoint {
> };
>
> <dc {
> + bootph-some-ram;
> status = "okay";
>
> port {
> diff --git a/arch/arm/boot/dts/st/stm32mp157f-dk2-scmi.dtsi b/arch/arm/boot/dts/st/stm32mp157f-dk2-scmi.dtsi
> index 89de85a2eff3..5d29c2154b46 100644
> --- a/arch/arm/boot/dts/st/stm32mp157f-dk2-scmi.dtsi
> +++ b/arch/arm/boot/dts/st/stm32mp157f-dk2-scmi.dtsi
> @@ -87,6 +87,7 @@ &mdma1 {
> &optee {
> interrupt-parent = <&intc>;
> interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
> + bootph-some-ram;
> };
>
> &pwr_regulators {
> @@ -114,6 +115,10 @@ &rtc {
> clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
> };
>
> +&scmi {
> + bootph-some-ram;
> +};
> +
> &scmi_reguls {
> scmi_vddcore: regulator@3 {
> reg = <VOLTD_SCMI_STPMIC1_BUCK1>;
> diff --git a/arch/arm/boot/dts/st/stm32mp157f-dk2.dts b/arch/arm/boot/dts/st/stm32mp157f-dk2.dts
> index 8fa61e54d026..4d857b3575fd 100644
> --- a/arch/arm/boot/dts/st/stm32mp157f-dk2.dts
> +++ b/arch/arm/boot/dts/st/stm32mp157f-dk2.dts
> @@ -97,6 +97,7 @@ stpmic@33 {
> };
>
> <dc {
> + bootph-some-ram;
> status = "okay";
>
> port {
> diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi
> index 5c77202ee196..2e02cd8e7e0d 100644
> --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi
> +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi
> @@ -201,6 +201,7 @@ <dc {
> pinctrl-names = "default", "sleep";
> pinctrl-0 = <<dc_pins_b>;
> pinctrl-1 = <<dc_sleep_pins_b>;
> + bootph-some-ram;
> status = "okay";
>
> port {
> diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi
> index 4cc633683c6b..2c40ceaf1f33 100644
> --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi
> +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-som.dtsi
> @@ -103,6 +103,10 @@ channel@1 {
> };
> };
>
> +&bsec {
> + bootph-all;
> +};
> +
> &crc1 {
> status = "okay";
> };
> @@ -121,6 +125,26 @@ dac2: dac@2 {
> };
> };
>
> +&clk_hse {
> + bootph-all;
> +};
> +
> +&clk_hsi {
> + bootph-all;
> +};
> +
> +&clk_lse {
> + bootph-all;
> +};
> +
> +&clk_lsi {
> + bootph-all;
> +};
> +
> +&clk_csi {
> + bootph-all;
> +};
> +
> &dts {
> status = "okay";
> };
> @@ -190,6 +214,7 @@ &gpioa {
> "", "", "DHCOM-K", "",
> "", "", "", "",
> "", "", "", "";
> + bootph-all;
> };
>
> &gpiob {
> @@ -197,6 +222,7 @@ &gpiob {
> "", "", "", "",
> "DHCOM-Q", "", "", "",
> "", "", "", "";
> + bootph-all;
> };
>
> &gpioc {
> @@ -204,6 +230,7 @@ &gpioc {
> "", "", "DHCOM-E", "",
> "", "", "", "",
> "", "", "", "";
> + bootph-all;
> };
>
> &gpiod {
> @@ -211,6 +238,7 @@ &gpiod {
> "", "", "DHCOM-B", "",
> "", "", "", "DHCOM-F",
> "DHCOM-D", "", "", "";
> + bootph-all;
> };
>
> &gpioe {
> @@ -218,6 +246,7 @@ &gpioe {
> "", "", "DHCOM-P", "",
> "", "", "", "",
> "", "", "", "";
> + bootph-all;
> };
>
> &gpiof {
> @@ -225,6 +254,7 @@ &gpiof {
> "", "", "", "",
> "", "", "", "",
> "", "", "", "";
> + bootph-all;
> };
>
> &gpiog {
> @@ -232,6 +262,7 @@ &gpiog {
> "", "", "", "",
> "DHCOM-L", "", "", "",
> "", "", "", "";
> + bootph-all;
> };
>
> &gpioh {
> @@ -239,6 +270,7 @@ &gpioh {
> "", "", "", "DHCOM-N",
> "DHCOM-J", "DHCOM-W", "DHCOM-V", "DHCOM-U",
> "DHCOM-T", "", "DHCOM-S", "";
> + bootph-all;
> };
>
> &gpioi {
> @@ -246,6 +278,20 @@ &gpioi {
> "DHCOM-R", "DHCOM-M", "", "",
> "", "", "", "",
> "", "", "", "";
> + bootph-all;
> +};
> +
> +&gpioj {
> + bootph-all;
> +
> +};
> +
> +&gpiok {
> + bootph-all;
> +};
> +
> +&gpioz {
> + bootph-all;
> };
>
> &i2c4 {
> @@ -253,6 +299,8 @@ &i2c4 {
> pinctrl-0 = <&i2c4_pins_a>;
> i2c-scl-rising-time-ns = <185>;
> i2c-scl-falling-time-ns = <20>;
> + bootph-all;
> + bootph-pre-ram;
> status = "okay";
> /* spare dmas for other usage */
> /delete-property/dmas;
> @@ -269,6 +317,8 @@ pmic: stpmic@33 {
> interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
> interrupt-controller;
> #interrupt-cells = <2>;
> + bootph-all;
> + bootph-pre-ram;
>
> regulators {
> compatible = "st,stpmic1-regulators";
> @@ -279,6 +329,7 @@ regulators {
> ldo6-supply = <&v3v3>;
> pwr_sw1-supply = <&bst_out>;
> pwr_sw2-supply = <&bst_out>;
> + bootph-pre-ram;
>
> vddcore: buck1 {
> regulator-name = "vddcore";
> @@ -409,12 +460,20 @@ eeprom@50 {
> };
> };
>
> +&i2c4_pins_a {
> + bootph-all;
> + pins {
> + bootph-all;
> + };
> +};
> +
> &ipcc {
> status = "okay";
> };
>
> &iwdg2 {
> timeout-sec = <32>;
> + bootph-all;
> status = "okay";
> };
>
> @@ -428,9 +487,22 @@ &m4_rproc {
> status = "okay";
> };
>
> +&pinctrl {
> + bootph-all;
> +};
> +
> +&pinctrl_z {
> + bootph-all;
> +};
> +
> +&psci {
> + bootph-some-ram;
> +};
> +
> &pwr_regulators {
> vdd-supply = <&vdd>;
> vdd_3v3_usbfs-supply = <&vdd_usb>;
> + bootph-all;
> };
>
> &qspi {
> @@ -444,6 +516,7 @@ &qspi_bk1_sleep_pins_a
> reg = <0x58003000 0x1000>, <0x70000000 0x4000000>;
> #address-cells = <1>;
> #size-cells = <0>;
> + bootph-pre-ram;
> status = "okay";
>
> flash0: flash@0 {
> @@ -453,6 +526,28 @@ flash0: flash@0 {
> spi-max-frequency = <108000000>;
> #address-cells = <1>;
> #size-cells = <1>;
> + bootph-pre-ram;
> + };
> +};
> +
> +&qspi_clk_pins_a {
> + bootph-pre-ram;
> + pins {
> + bootph-pre-ram;
> + };
> +};
> +
> +&qspi_bk1_pins_a {
> + bootph-pre-ram;
> + pins {
> + bootph-pre-ram;
> + };
> +};
> +
> +&qspi_cs1_pins_a {
> + bootph-pre-ram;
> + pins {
> + bootph-pre-ram;
> };
> };
>
> @@ -469,6 +564,15 @@ &rcc {
> assigned-clocks = <&rcc CK_MCO2>, <&rcc PLL4_P>;
> assigned-clock-parents = <&rcc PLL4_P>;
> assigned-clock-rates = <50000000>, <100000000>;
> + bootph-all;
> +};
> +
> +®11 {
> + bootph-pre-ram;
> +};
> +
> +®18 {
> + bootph-pre-ram;
> };
>
> &rng1 {
> @@ -495,6 +599,7 @@ &sdmmc1 {
> st,ckin-gpios = <&gpioe 4 0>;
> bus-width = <4>;
> vmmc-supply = <&vdd_sd>;
> + bootph-pre-ram;
> status = "okay";
> };
>
> @@ -504,11 +609,24 @@ &sdmmc1_b4_pins_a {
> * - optional on SoMs with SD voltage translator
> * - mandatory on SoMs without SD voltage translator
> */
> + bootph-pre-ram;
> pins1 {
> bias-pull-up;
> + bootph-pre-ram;
> };
> pins2 {
> bias-pull-up;
> + bootph-pre-ram;
> + };
> +};
> +
> +&sdmmc1_dir_pins_a {
> + bootph-pre-ram;
> + pins1 {
> + bootph-pre-ram;
> + };
> + pins2 {
> + bootph-pre-ram;
> };
> };
>
> @@ -525,9 +643,24 @@ &sdmmc2 {
> vmmc-supply = <&v3v3>;
> vqmmc-supply = <&v3v3>;
> mmc-ddr-3_3v;
> + bootph-pre-ram;
> status = "okay";
> };
>
> +&sdmmc2_b4_pins_a {
> + bootph-pre-ram;
> + pins {
> + bootph-pre-ram;
> + };
> +};
> +
> +&sdmmc2_d47_pins_a {
> + bootph-pre-ram;
> + pins {
> + bootph-pre-ram;
> + };
> +};
> +
> &sdmmc3 {
> pinctrl-names = "default", "opendrain", "sleep";
> pinctrl-0 = <&sdmmc3_b4_pins_a>;
> @@ -545,7 +678,46 @@ &sdmmc3 {
> &uart4 {
> pinctrl-names = "default";
> pinctrl-0 = <&uart4_pins_a>;
> + bootph-all;
> /delete-property/dmas;
> /delete-property/dma-names;
> status = "okay";
> };
> +
> +&uart4_pins_a {
> + bootph-all;
> + pins1 {
> + bootph-all;
> + };
> + pins2 {
> + bootph-all;
> + };
> +};
> +
> +&usb33 {
> + bootph-pre-ram;
> +};
> +
> +&usbotg_hs_pins_a {
> + bootph-pre-ram;
> +};
> +
> +&usbotg_hs {
> + bootph-pre-ram;
> +};
> +
> +&usbphyc {
> + bootph-pre-ram;
> +};
> +
> +&usbphyc_port0 {
> + bootph-pre-ram;
> +};
> +
> +&usbphyc_port1 {
> + bootph-pre-ram;
> +};
> +
> +&vdd_usb {
> + bootph-pre-ram;
> +};
> diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi
> index aceeff6c38ba..e7e2203ab11a 100644
> --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi
> +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-avenger96.dtsi
> @@ -355,6 +355,7 @@ <dc {
> pinctrl-names = "default", "sleep";
> pinctrl-0 = <<dc_pins_d>;
> pinctrl-1 = <<dc_sleep_pins_d>;
> + bootph-some-ram;
> status = "okay";
>
> port {
> @@ -402,9 +403,30 @@ &sdmmc1 {
> bus-width = <4>;
> vmmc-supply = <&vdd_sd>;
> vqmmc-supply = <&sd_switch>;
> + bootph-pre-ram;
> status = "okay";
> };
>
> +&sdmmc1_b4_pins_a {
> + bootph-pre-ram;
> + pins1 {
> + bootph-pre-ram;
> + };
> + pins2 {
> + bootph-pre-ram;
> + };
> +};
> +
> +&sdmmc1_dir_pins_b {
> + bootph-pre-ram;
> + pins1 {
> + bootph-pre-ram;
> + };
> + pins2 {
> + bootph-pre-ram;
> + };
> +};
> +
> &sdmmc2 {
> pinctrl-names = "default", "opendrain", "sleep";
> pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>;
> @@ -418,9 +440,27 @@ &sdmmc2 {
> st,neg-edge;
> vmmc-supply = <&v3v3>;
> vqmmc-supply = <&vdd_io>;
> + bootph-pre-ram;
> status = "okay";
> };
>
> +&sdmmc2_b4_pins_a {
> + bootph-pre-ram;
> + pins1 {
> + bootph-pre-ram;
> + };
> + pins2 {
> + bootph-pre-ram;
> + };
> +};
> +
> +&sdmmc2_d47_pins_c {
> + bootph-pre-ram;
> + pins {
> + bootph-pre-ram;
> + };
> +};
> +
> &sdmmc3 {
> pinctrl-names = "default", "opendrain", "sleep";
> pinctrl-0 = <&sdmmc3_b4_pins_b>;
> @@ -455,11 +495,22 @@ &uart4 {
> label = "LS-UART1";
> pinctrl-names = "default";
> pinctrl-0 = <&uart4_pins_b>;
> + bootph-all;
> /delete-property/dmas;
> /delete-property/dma-names;
> status = "okay";
> };
>
> +&uart4_pins_b {
> + bootph-all;
> + pins1 {
> + bootph-all;
> + };
> + pins2 {
> + bootph-all;
> + };
> +};
> +
> &uart7 {
> /* On Low speed expansion header */
> label = "LS-UART0";
> @@ -512,3 +563,7 @@ &usbphyc_port0 {
> &usbphyc_port1 {
> phy-supply = <&vdd_usb>;
> };
> +
> +&vdd_io {
> + bootph-pre-ram;
> +};
> diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-drc-compact.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-drc-compact.dtsi
> index bc4ddcbdd5cf..9c6a04b4c2e3 100644
> --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-drc-compact.dtsi
> +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-drc-compact.dtsi
> @@ -231,9 +231,30 @@ &sdmmc1 { /* MicroSD */
> bus-width = <4>;
> vmmc-supply = <&vdd>;
> vqmmc-supply = <&vdd>;
> + bootph-pre-ram;
> status = "okay";
> };
>
> +&sdmmc1_b4_pins_a {
> + bootph-pre-ram;
> + pins1 {
> + bootph-pre-ram;
> + };
> + pins2 {
> + bootph-pre-ram;
> + };
> +};
> +
> +&sdmmc1_dir_pins_b {
> + bootph-pre-ram;
> + pins1 {
> + bootph-pre-ram;
> + };
> + pins2 {
> + bootph-pre-ram;
> + };
> +};
> +
> &sdmmc2 { /* eMMC */
> pinctrl-names = "default", "opendrain", "sleep";
> pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>;
> @@ -246,9 +267,27 @@ &sdmmc2 { /* eMMC */
> st,neg-edge;
> vmmc-supply = <&v3v3>;
> vqmmc-supply = <&vdd>;
> + bootph-pre-ram;
> status = "okay";
> };
>
> +&sdmmc2_b4_pins_a {
> + bootph-pre-ram;
> + pins1 {
> + bootph-pre-ram;
> + };
> + pins2 {
> + bootph-pre-ram;
> + };
> +};
> +
> +&sdmmc2_d47_pins_c {
> + bootph-pre-ram;
> + pins {
> + bootph-pre-ram;
> + };
> +};
> +
> &sdmmc3 { /* SDIO Wi-Fi */
> pinctrl-names = "default", "opendrain", "sleep";
> pinctrl-0 = <&sdmmc3_b4_pins_a>;
> @@ -276,11 +315,22 @@ &uart4 {
> label = "UART0";
> pinctrl-names = "default";
> pinctrl-0 = <&uart4_pins_d>;
> + bootph-all;
> /delete-property/dmas;
> /delete-property/dma-names;
> status = "okay";
> };
>
> +&uart4_pins_d {
> + bootph-all;
> + pins1 {
> + bootph-all;
> + };
> + pins2 {
> + bootph-all;
> + };
> +};
> +
> &uart5 { /* X11 UART */
> label = "X11-UART5";
> pinctrl-names = "default";
> diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-som.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-som.dtsi
> index 89881a26c614..3d469e29d41a 100644
> --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-som.dtsi
> +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-som.dtsi
> @@ -63,6 +63,30 @@ retram: retram@38000000 {
> };
> };
>
> +&bsec {
> + bootph-all;
> +};
> +
> +&clk_hse {
> + bootph-all;
> +};
> +
> +&clk_hsi {
> + bootph-all;
> +};
> +
> +&clk_lse {
> + bootph-all;
> +};
> +
> +&clk_lsi {
> + bootph-all;
> +};
> +
> +&clk_csi {
> + bootph-all;
> +};
> +
> &crc1 {
> status = "okay";
> };
> @@ -71,11 +95,61 @@ &dts {
> status = "okay";
> };
>
> +&gpioa {
> + bootph-all;
> +};
> +
> +&gpiob {
> + bootph-all;
> +};
> +
> +&gpioc {
> + bootph-all;
> +};
> +
> +&gpiod {
> + bootph-all;
> +};
> +
> +&gpioe {
> + bootph-all;
> +};
> +
> +&gpiof {
> + bootph-all;
> +};
> +
> +&gpiog {
> + bootph-all;
> +};
> +
> +&gpioh {
> + bootph-all;
> +};
> +
> +&gpioi {
> + bootph-all;
> +};
> +
> +&gpioj {
> + bootph-all;
> +};
> +
> +&gpiok {
> + bootph-all;
> +};
> +
> +&gpioz {
> + bootph-all;
> +};
> +
> &i2c4 {
> pinctrl-names = "default";
> pinctrl-0 = <&i2c4_pins_a>;
> i2c-scl-rising-time-ns = <185>;
> i2c-scl-falling-time-ns = <20>;
> + bootph-all;
> + bootph-pre-ram;
> status = "okay";
> /delete-property/dmas;
> /delete-property/dma-names;
> @@ -86,6 +160,8 @@ pmic: stpmic@33 {
> interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
> interrupt-controller;
> #interrupt-cells = <2>;
> + bootph-all;
> + bootph-pre-ram;
> status = "okay";
>
> regulators {
> @@ -98,6 +174,7 @@ regulators {
> ldo6-supply = <&v3v3>;
> pwr_sw1-supply = <&bst_out>;
> pwr_sw2-supply = <&bst_out>;
> + bootph-pre-ram;
>
> vddcore: buck1 {
> regulator-name = "vddcore";
> @@ -215,12 +292,20 @@ watchdog {
> };
> };
>
> +&i2c4_pins_a {
> + bootph-all;
> + pins {
> + bootph-all;
> + };
> +};
> +
> &ipcc {
> status = "okay";
> };
>
> &iwdg2 {
> timeout-sec = <32>;
> + bootph-all;
> status = "okay";
> };
>
> @@ -234,9 +319,23 @@ &m4_rproc {
> status = "okay";
> };
>
> +&pinctrl {
> + bootph-all;
> +};
> +
> +&pinctrl_z {
> + bootph-all;
> +};
> +
> +&psci {
> + bootph-some-ram;
> +};
> +
> &pwr_regulators {
> vdd-supply = <&vdd>;
> vdd_3v3_usbfs-supply = <&vdd_usb>;
> + bootph-all;
> + bootph-pre-ram;
> };
>
> &qspi {
> @@ -250,6 +349,7 @@ &qspi_bk1_sleep_pins_a
> reg = <0x58003000 0x1000>, <0x70000000 0x200000>;
> #address-cells = <1>;
> #size-cells = <0>;
> + bootph-pre-ram;
> status = "okay";
>
> flash0: flash@0 {
> @@ -262,6 +362,35 @@ flash0: flash@0 {
> };
> };
>
> +&qspi_clk_pins_a {
> + bootph-pre-ram;
> + pins {
> + bootph-pre-ram;
> + };
> +};
> +
> +&qspi_bk1_pins_a {
> + bootph-pre-ram;
> + pins {
> + bootph-pre-ram;
> + };
> +};
> +
> +&qspi_cs1_pins_a {
> + bootph-pre-ram;
> + pins {
> + bootph-pre-ram;
> + };
> +};
> +
> +®11 {
> + bootph-pre-ram;
> +};
> +
> +®18 {
> + bootph-pre-ram;
> +};
> +
> &rng1 {
> status = "okay";
> };
> @@ -269,3 +398,31 @@ &rng1 {
> &rtc {
> status = "okay";
> };
> +
> +&usb33 {
> + bootph-pre-ram;
> +};
> +
> +&usbotg_hs_pins_a {
> + bootph-pre-ram;
> +};
> +
> +&usbotg_hs {
> + bootph-pre-ram;
> +};
> +
> +&usbphyc {
> + bootph-pre-ram;
> +};
> +
> +&usbphyc_port0 {
> + bootph-pre-ram;
> +};
> +
> +&usbphyc_port1 {
> + bootph-pre-ram;
> +};
> +
> +&vdd_usb {
> + bootph-pre-ram;
> +};
> diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-testbench.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-testbench.dtsi
> index 6e79c4b6fe32..3b5debd0ffc9 100644
> --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcor-testbench.dtsi
> +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcor-testbench.dtsi
> @@ -131,9 +131,30 @@ &sdmmc1 {
> bus-width = <4>;
> vmmc-supply = <&vdd_sd>;
> vqmmc-supply = <&sd_switch>;
> + bootph-pre-ram;
> status = "okay";
> };
>
> +&sdmmc1_b4_pins_a {
> + bootph-pre-ram;
> + pins1 {
> + bootph-pre-ram;
> + };
> + pins2 {
> + bootph-pre-ram;
> + };
> +};
> +
> +&sdmmc1_dir_pins_b {
> + bootph-pre-ram;
> + pins1 {
> + bootph-pre-ram;
> + };
> + pins2 {
> + bootph-pre-ram;
> + };
> +};
> +
> &sdmmc2 {
> pinctrl-names = "default", "opendrain", "sleep";
> pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>;
> @@ -147,17 +168,46 @@ &sdmmc2 {
> st,neg-edge;
> vmmc-supply = <&v3v3>;
> vqmmc-supply = <&v3v3>;
> + bootph-pre-ram;
> status = "okay";
> };
>
> +&sdmmc2_b4_pins_a {
> + bootph-pre-ram;
> + pins1 {
> + bootph-pre-ram;
> + };
> + pins2 {
> + bootph-pre-ram;
> + };
> +};
> +
> +&sdmmc2_d47_pins_c {
> + bootph-pre-ram;
> + pins {
> + bootph-pre-ram;
> + };
> +};
> +
> &uart4 {
> pinctrl-names = "default";
> pinctrl-0 = <&uart4_pins_b>;
> + bootph-all;
> /delete-property/dmas;
> /delete-property/dma-names;
> status = "okay";
> };
>
> +&uart4_pins_b {
> + bootph-all;
> + pins1 {
> + bootph-all;
> + };
> + pins2 {
> + bootph-all;
> + };
> +};
> +
> &uart7 {
> pinctrl-names = "default";
> pinctrl-0 = <&uart7_pins_a>;
> diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi
> index 8cea6facd27b..62d6417ed422 100644
> --- a/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi
> +++ b/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi
> @@ -129,6 +129,10 @@ channel@19 {
> };
> };
>
> +&bsec {
> + bootph-all;
> +};
> +
> &cec {
> pinctrl-names = "default", "sleep";
> pinctrl-0 = <&cec_pins_b>;
> @@ -136,6 +140,26 @@ &cec {
> status = "okay";
> };
>
> +&clk_hse {
> + bootph-all;
> +};
> +
> +&clk_hsi {
> + bootph-all;
> +};
> +
> +&clk_lse {
> + bootph-all;
> +};
> +
> +&clk_lsi {
> + bootph-all;
> +};
> +
> +&clk_csi {
> + bootph-all;
> +};
> +
> &crc1 {
> status = "okay";
> };
> @@ -144,6 +168,54 @@ &dts {
> status = "okay";
> };
>
> +&gpioa {
> + bootph-all;
> +};
> +
> +&gpiob {
> + bootph-all;
> +};
> +
> +&gpioc {
> + bootph-all;
> +};
> +
> +&gpiod {
> + bootph-all;
> +};
> +
> +&gpioe {
> + bootph-all;
> +};
> +
> +&gpiof {
> + bootph-all;
> +};
> +
> +&gpiog {
> + bootph-all;
> +};
> +
> +&gpioh {
> + bootph-all;
> +};
> +
> +&gpioi {
> + bootph-all;
> +};
> +
> +&gpioj {
> + bootph-all;
> +};
> +
> +&gpiok {
> + bootph-all;
> +};
> +
> +&gpioz {
> + bootph-all;
> +};
> +
> ðernet0 {
> status = "okay";
> pinctrl-0 = <ðernet0_rgmii_pins_a>;
> @@ -249,6 +321,7 @@ &i2c4 {
> i2c-scl-rising-time-ns = <185>;
> i2c-scl-falling-time-ns = <20>;
> clock-frequency = <400000>;
> + bootph-all;
> status = "okay";
> /* spare dmas for other usage */
> /delete-property/dmas;
> @@ -284,6 +357,7 @@ pmic: stpmic@33 {
> interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>;
> interrupt-controller;
> #interrupt-cells = <2>;
> + bootph-all;
> status = "okay";
>
> regulators {
> @@ -422,6 +496,13 @@ watchdog {
> };
> };
>
> +&i2c4_pins_a {
> + bootph-all;
> + pins {
> + bootph-all;
> + };
> +};
> +
> &i2c5 {
> pinctrl-names = "default", "sleep";
> pinctrl-0 = <&i2c5_pins_a>;
> @@ -458,6 +539,7 @@ &ipcc {
>
> &iwdg2 {
> timeout-sec = <32>;
> + bootph-all;
> status = "okay";
> };
>
> @@ -465,6 +547,7 @@ <dc {
> pinctrl-names = "default", "sleep";
> pinctrl-0 = <<dc_pins_a>;
> pinctrl-1 = <<dc_sleep_pins_a>;
> + bootph-some-ram;
> status = "okay";
>
> port {
> @@ -486,9 +569,26 @@ &m4_rproc {
> status = "okay";
> };
>
> +&pinctrl {
> + bootph-all;
> +};
> +
> +&pinctrl_z {
> + bootph-all;
> +};
> +
> +&psci {
> + bootph-some-ram;
> +};
> +
> &pwr_regulators {
> vdd-supply = <&vdd>;
> vdd_3v3_usbfs-supply = <&vdd_usb>;
> + bootph-all;
> +};
> +
> +&rcc {
> + bootph-all;
> };
>
> &rng1 {
> @@ -553,9 +653,20 @@ &sdmmc1 {
> st,neg-edge;
> bus-width = <4>;
> vmmc-supply = <&v3v3>;
> + bootph-pre-ram;
> status = "okay";
> };
>
> +&sdmmc1_b4_pins_a {
> + bootph-pre-ram;
> + pins1 {
> + bootph-pre-ram;
> + };
> + pins2 {
> + bootph-pre-ram;
> + };
> +};
> +
> &sdmmc3 {
> pinctrl-names = "default", "opendrain", "sleep";
> pinctrl-0 = <&sdmmc3_b4_pins_a>;
> @@ -676,11 +787,22 @@ &uart4 {
> pinctrl-0 = <&uart4_pins_a>;
> pinctrl-1 = <&uart4_sleep_pins_a>;
> pinctrl-2 = <&uart4_idle_pins_a>;
> + bootph-all;
> /delete-property/dmas;
> /delete-property/dma-names;
> status = "okay";
> };
>
> +&uart4_pins_a {
> + bootph-all;
> + pins1 {
> + bootph-all;
> + };
> + pins2 {
> + bootph-all;
> + };
> +};
> +
> &uart7 {
> pinctrl-names = "default", "sleep", "idle";
> pinctrl-0 = <&uart7_pins_c>;
>
^ permalink raw reply
* Re: [PATCH RESEND v2] arm64: dts: rockchip: configure hdmirx in Rock 5 ITX
From: Pedro Alves @ 2026-03-25 14:24 UTC (permalink / raw)
To: Heiko Stuebner
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel
In-Reply-To: <3407927.44csPzL39Z@phil>
Hi,
On 24/03/2026 14:18, Heiko Stuebner wrote:
> Am Montag, 23. März 2026, 10:25:33 Mitteleuropäische Normalzeit schrieb Pedro Alves:
>> +&hdmi_receiver {
>> + pinctrl-0 = <&hdmim1_rx_cec &hdmim1_rx_hpdin &hdmim1_rx_scl &hdmim1_rx_sda &hdmirx_det>;
>> + pinctrl-names = "default";
>> + hpd-gpios = <&gpio1 RK_PC6 GPIO_ACTIVE_LOW>;
>
> as said before, please also add a pinctrl setting for this pin.
>
> gpio1_c6 is not part of the main hdmirx set of pins, hence needs an
> additional pinctrl entry to configure it as gpio and possibly set any
> additional pull settings.
>
> And yes the pinctrl-driver does "implcitly" set the gpio-mode when
> a gpio is requested, but our more modern approach is to always have
> a real pinctrl entry even for gpios.
I am probably getting confused by what you are asking here, but I don't
understand what exactly I should add. There was already a pinctrl for
hdmirx_det (which is what the gpio1_c6 pin is) present in the file,
hence why I did not add it in this patch:
&pinctrl {
/* ... */
hdmirx {
hdmirx_det: hdmirx-det {
rockchip,pins = <1 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
/* ... */
};
Looking at the other boards, they do the same thing, but they call it
hdmirx-5v-detection instead, but as discussed in v1 of this patch I
ended up keeping the det naming to match the schematics.
Sorry if I am missing something, I don't have much experience with this,
so I would really appreciate some extra information.
Thank you,
Pedro
^ permalink raw reply
* Re: [PATCH 3/4] arm64: dts: renesas: Drop KSZ9131 PHY C22 compatible string
From: Geert Uytterhoeven @ 2026-03-25 14:23 UTC (permalink / raw)
To: Marek Vasut
Cc: linux-arm-kernel, Biju Das, Conor Dooley, Krzysztof Kozlowski,
Lad Prabhakar, Magnus Damm, Rob Herring, devicetree, linux-kernel,
linux-renesas-soc
In-Reply-To: <20260313164008.40933-4-marek.vasut+renesas@mailbox.org>
On Fri, 13 Mar 2026 at 17:40, Marek Vasut
<marek.vasut+renesas@mailbox.org> wrote:
> Microchip KSZ9131 PHY schema indicates that compatible string
> "ethernet-phy-id0022.1640" must not be followed by any other
> compatible string. Drop trailing "ethernet-phy-ieee802.3-c22"
> to match the schema.
>
> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v7.1.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH 2/4] arm64: dts: renesas: Drop RTL8211F PHY C22 compatible string
From: Geert Uytterhoeven @ 2026-03-25 14:23 UTC (permalink / raw)
To: Marek Vasut
Cc: linux-arm-kernel, Biju Das, Conor Dooley, Krzysztof Kozlowski,
Lad Prabhakar, Magnus Damm, Rob Herring, devicetree, linux-kernel,
linux-renesas-soc
In-Reply-To: <20260313164008.40933-3-marek.vasut+renesas@mailbox.org>
On Fri, 13 Mar 2026 at 17:40, Marek Vasut
<marek.vasut+renesas@mailbox.org> wrote:
> Realtek RTL8211F PHY schema indicates that compatible string
> "ethernet-phy-id001c.c916" must not be followed by any other
> compatible string. Drop trailing "ethernet-phy-ieee802.3-c22"
> to match the schema.
>
> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v7.1.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [RFC PATCH] dmaengine: xilinx_dma: Fix per-channel direction reporting via device_caps
From: Rahul Navale @ 2026-03-25 14:22 UTC (permalink / raw)
To: dmaengine
Cc: Rahul Navale, dev, linux-arm-kernel, linux-kernel, vkoul,
Frank.Li, michal.simek, suraj.gupta2, thomas.gessler,
radhey.shyam.pandey, tomi.valkeinen, rahulnavale04, marex, marex
In-Reply-To: <DGHGTCJRRZCW.9TGXQW44V6RR@folker-schwesinger.de>
From: Rahul Navale <rahul.navale@ifm.com>
@Xilinx/AMD maintainers:
Quick status: the ASoC playback regression is still present.
when 7e01511443c3 ("dmaengine: xilinx_dma: Set dma_device directions")
is present. Reverting 7e01511443c3 restores normal playback.
Could you please advice the next steps / preferred fix direction to address
this regression upstream?
Thanks,
Rahul
^ permalink raw reply
* Re: [PATCH 1/4] arm64: dts: renesas: Drop RTL8211E PHY C22 compatible string
From: Geert Uytterhoeven @ 2026-03-25 14:22 UTC (permalink / raw)
To: Marek Vasut
Cc: linux-arm-kernel, Biju Das, Conor Dooley, Krzysztof Kozlowski,
Lad Prabhakar, Magnus Damm, Rob Herring, devicetree, linux-kernel,
linux-renesas-soc
In-Reply-To: <20260313164008.40933-2-marek.vasut+renesas@mailbox.org>
On Fri, 13 Mar 2026 at 17:40, Marek Vasut
<marek.vasut+renesas@mailbox.org> wrote:
> Realtek RTL8211E PHY schema indicates that compatible string
> "ethernet-phy-id001c.c915" must not be followed by any other
> compatible string. Drop trailing "ethernet-phy-ieee802.3-c22"
> to match the schema.
>
> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v7.1.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH v5 4/6] ARM: dts: stm32: Add boot phase tags for STMicroelectronics mp13 boards
From: Patrice CHOTARD @ 2026-03-25 14:18 UTC (permalink / raw)
To: Alexandre Torgue, Marek Vasut
Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel, kernel,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin,
Patrick Delaunay, Christoph Niedermaier
In-Reply-To: <20260123-upstream_uboot_properties-v5-4-5167929d5af5@foss.st.com>
Hi Marek
Have you some remarks about DHCOR DT update ?
Thanks
Patrice
On 1/23/26 11:14, Patrice Chotard wrote:
> The bootph-all flag was introduced in dt-schema
> (dtschema/schemas/bootph.yaml) to define node usage across
> different boot phases.
>
> To ensure SD boot, timer, gpio, syscfg, clock and uart nodes need to be
> present in all boot stages, so add missing bootph-all phase flag
> to these nodes to support SD boot.
>
> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
> ---
> arch/arm/boot/dts/st/stm32mp131.dtsi | 4 +-
> arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts | 21 ++++
> arch/arm/boot/dts/st/stm32mp135f-dk.dts | 101 ++++++++++++++++
> arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi | 145 +++++++++++++++++++----
> 4 files changed, 247 insertions(+), 24 deletions(-)
>
> diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi
> index fd730aa37c22..80c97bc830eb 100644
> --- a/arch/arm/boot/dts/st/stm32mp131.dtsi
> +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi
> @@ -30,7 +30,7 @@ arm-pmu {
> };
>
> firmware {
> - optee {
> + optee: optee {
> method = "smc";
> compatible = "linaro,optee-tz";
> interrupt-parent = <&intc>;
> @@ -85,7 +85,7 @@ intc: interrupt-controller@a0021000 {
> <0xa0022000 0x2000>;
> };
>
> - psci {
> + psci: psci {
> compatible = "arm,psci-1.0";
> method = "smc";
> };
> diff --git a/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts b/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts
> index 9902849ed040..526ab2e1a93c 100644
> --- a/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts
> +++ b/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts
> @@ -350,6 +350,21 @@ timer@12 {
> };
> };
>
> +&uart4 {
> + bootph-all;
> +};
> +
> +&uart4_pins_b {
> + bootph-all;
> +
> + pins1 {
> + bootph-all;
> + };
> + pins2 {
> + bootph-all;
> + };
> +};
> +
> &usart1 { /* Expansion connector: RX:pin33 TX:pin37 */
> pinctrl-names = "default", "sleep", "idle";
> pinctrl-0 = <&usart1_pins_b>;
> @@ -367,6 +382,10 @@ &usart2 { /* Expansion connector: RX:pin10 TX:pin8 RTS:pin11 CTS:pin36 */
> status = "okay";
> };
>
> +&usbphyc {
> + bootph-all;
> +};
> +
> &usbh_ehci {
> phys = <&usbphyc_port0>;
> status = "okay";
> @@ -432,6 +451,7 @@ connector {
>
> /* LDO2 is expansion connector 3V3 supply on STM32MP13xx DHCOR DHSBC rev.200 */
> &vdd_ldo2 {
> + bootph-all;
> regulator-always-on;
> regulator-boot-on;
> regulator-min-microvolt = <3300000>;
> @@ -440,6 +460,7 @@ &vdd_ldo2 {
>
> /* LDO5 is carrier board 3V3 supply on STM32MP13xx DHCOR DHSBC rev.200 */
> &vdd_sd {
> + bootph-all;
> regulator-always-on;
> regulator-boot-on;
> regulator-min-microvolt = <3300000>;
> diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts b/arch/arm/boot/dts/st/stm32mp135f-dk.dts
> index 9764a6bfa5b4..83bc5ea90c3a 100644
> --- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts
> +++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts
> @@ -161,6 +161,10 @@ channel@12 {
> };
> };
>
> +&bsec {
> + bootph-all;
> +};
> +
> &crc1 {
> status = "okay";
> };
> @@ -208,6 +212,42 @@ phy0_eth1: ethernet-phy@0 {
> };
> };
>
> +&gpioa {
> + bootph-all;
> +};
> +
> +&gpiob {
> + bootph-all;
> +};
> +
> +&gpioc {
> + bootph-all;
> +};
> +
> +&gpiod {
> + bootph-all;
> +};
> +
> +&gpioe {
> + bootph-all;
> +};
> +
> +&gpiof {
> + bootph-all;
> +};
> +
> +&gpiog {
> + bootph-all;
> +};
> +
> +&gpioh {
> + bootph-all;
> +};
> +
> +&gpioi {
> + bootph-all;
> +};
> +
> &i2c1 {
> pinctrl-names = "default", "sleep";
> pinctrl-0 = <&i2c1_pins_a>;
> @@ -342,6 +382,7 @@ goodix: goodix-ts@5d {
>
> &iwdg2 {
> timeout-sec = <32>;
> + bootph-all;
> status = "okay";
> };
>
> @@ -349,6 +390,7 @@ <dc {
> pinctrl-names = "default", "sleep";
> pinctrl-0 = <<dc_pins_a>;
> pinctrl-1 = <<dc_sleep_pins_a>;
> + bootph-some-ram;
> status = "okay";
>
> port {
> @@ -358,6 +400,22 @@ ltdc_out_rgb: endpoint {
> };
> };
>
> +&optee {
> + bootph-all;
> +};
> +
> +&pinctrl {
> + bootph-all;
> +};
> +
> +&psci {
> + bootph-some-ram;
> +};
> +
> +&rcc {
> + bootph-all;
> +};
> +
> &rtc {
> pinctrl-names = "default";
> pinctrl-0 = <&rtc_rsvd_pins_a>;
> @@ -369,6 +427,14 @@ rtc_lsco_pins_a: rtc-lsco-0 {
> };
> };
>
> +&scmi {
> + bootph-all;
> +};
> +
> +&scmi_clk {
> + bootph-all;
> +};
> +
> &scmi_regu {
> scmi_vdd_adc: regulator@10 {
> reg = <VOLTD_SCMI_STPMIC1_LDO1>;
> @@ -392,6 +458,10 @@ scmi_v3v3_sw: regulator@19 {
> };
> };
>
> +&scmi_reset {
> + bootph-all;
> +};
> +
> &sdmmc1 {
> pinctrl-names = "default", "opendrain", "sleep";
> pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>;
> @@ -402,9 +472,24 @@ &sdmmc1 {
> st,neg-edge;
> bus-width = <4>;
> vmmc-supply = <&scmi_vdd_sd>;
> + bootph-pre-ram;
> status = "okay";
> };
>
> +&sdmmc1_b4_pins_a {
> + bootph-pre-ram;
> + pins {
> + bootph-pre-ram;
> + };
> +};
> +
> +&sdmmc1_clk_pins_a {
> + bootph-pre-ram;
> + pins {
> + bootph-pre-ram;
> + };
> +};
> +
> /* Wifi */
> &sdmmc2 {
> pinctrl-names = "default", "opendrain", "sleep";
> @@ -436,6 +521,10 @@ &spi5 {
> status = "disabled";
> };
>
> +&syscfg {
> + bootph-all;
> +};
> +
> &timers3 {
> /delete-property/dmas;
> /delete-property/dma-names;
> @@ -517,9 +606,20 @@ &uart4 {
> pinctrl-2 = <&uart4_idle_pins_a>;
> /delete-property/dmas;
> /delete-property/dma-names;
> + bootph-all;
> status = "okay";
> };
>
> +&uart4_pins_a {
> + bootph-all;
> + pins1 {
> + bootph-all;
> + };
> + pins2 {
> + bootph-all;
> + };
> +};
> +
> &uart8 {
> pinctrl-names = "default", "sleep", "idle";
> pinctrl-0 = <&uart8_pins_a>;
> @@ -583,6 +683,7 @@ usbotg_hs_ep: endpoint {
> };
>
> &usbphyc {
> + bootph-all;
> status = "okay";
> };
>
> diff --git a/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi b/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi
> index c18156807027..4efaca84a72c 100644
> --- a/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi
> +++ b/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi
> @@ -54,6 +54,46 @@ vin: vin {
> };
> };
>
> +&bsec {
> + bootph-all;
> +};
> +
> +&gpioa {
> + bootph-all;
> +};
> +
> +&gpiob {
> + bootph-all;
> +};
> +
> +&gpioc {
> + bootph-all;
> +};
> +
> +&gpiod {
> + bootph-all;
> +};
> +
> +&gpioe {
> + bootph-all;
> +};
> +
> +&gpiof {
> + bootph-all;
> +};
> +
> +&gpiog {
> + bootph-all;
> +};
> +
> +&gpioh {
> + bootph-all;
> +};
> +
> +&gpioi {
> + bootph-all;
> +};
> +
> &i2c3 {
> i2c-scl-rising-time-ns = <96>;
> i2c-scl-falling-time-ns = <3>;
> @@ -216,9 +256,18 @@ eeprom0wl: eeprom@58 {
>
> &iwdg2 {
> timeout-sec = <32>;
> + bootph-all;
> status = "okay";
> };
>
> +&pinctrl {
> + bootph-all;
> +};
> +
> +&psci {
> + bootph-some-ram;
> +};
> +
> &qspi {
> pinctrl-names = "default", "sleep";
> pinctrl-0 = <&qspi_clk_pins_a
> @@ -229,6 +278,7 @@ &qspi_bk1_sleep_pins_a
> &qspi_cs1_sleep_pins_a>;
> #address-cells = <1>;
> #size-cells = <0>;
> + bootph-all;
> status = "okay";
>
> flash0: flash@0 {
> @@ -238,37 +288,35 @@ flash0: flash@0 {
> spi-max-frequency = <108000000>;
> #address-cells = <1>;
> #size-cells = <1>;
> + bootph-all;
> };
> };
>
> -/* Console UART */
> -&uart4 {
> - pinctrl-names = "default", "sleep", "idle";
> - pinctrl-0 = <&uart4_pins_b>;
> - pinctrl-1 = <&uart4_sleep_pins_b>;
> - pinctrl-2 = <&uart4_idle_pins_b>;
> - /delete-property/dmas;
> - /delete-property/dma-names;
> - status = "okay";
> +&qspi_clk_pins_a {
> + bootph-all;
> + pins {
> + bootph-all;
> + };
> };
>
> -/* Bluetooth */
> -&uart7 {
> - pinctrl-names = "default", "sleep", "idle";
> - pinctrl-0 = <&uart7_pins_a>;
> - pinctrl-1 = <&uart7_sleep_pins_a>;
> - pinctrl-2 = <&uart7_idle_pins_a>;
> - uart-has-rtscts;
> - status = "okay";
> +&qspi_bk1_pins_a {
> + bootph-all;
> + pins {
> + bootph-all;
> + };
> +};
>
> - bluetooth {
> - compatible = "infineon,cyw43439-bt", "brcm,bcm4329-bt";
> - max-speed = <3000000>;
> - device-wakeup-gpios = <&gpiog 9 GPIO_ACTIVE_HIGH>;
> - shutdown-gpios = <&gpioi 2 GPIO_ACTIVE_HIGH>;
> +&qspi_cs1_pins_a {
> + bootph-all;
> + pins {
> + bootph-all;
> };
> };
>
> +&rcc {
> + bootph-all;
> +};
> +
> /* SDIO WiFi */
> &sdmmc1 {
> pinctrl-names = "default", "opendrain", "sleep";
> @@ -312,3 +360,56 @@ &sdmmc2 {
> vqmmc-supply = <&vdd>;
> status = "okay";
> };
> +
> +&syscfg {
> + bootph-all;
> +};
> +
> +/* Console UART */
> +&uart4 {
> + pinctrl-names = "default", "sleep", "idle";
> + pinctrl-0 = <&uart4_pins_b>;
> + pinctrl-1 = <&uart4_sleep_pins_b>;
> + pinctrl-2 = <&uart4_idle_pins_b>;
> + /delete-property/dmas;
> + /delete-property/dma-names;
> + status = "okay";
> +};
> +
> +/* Bluetooth */
> +&uart7 {
> + pinctrl-names = "default", "sleep", "idle";
> + pinctrl-0 = <&uart7_pins_a>;
> + pinctrl-1 = <&uart7_sleep_pins_a>;
> + pinctrl-2 = <&uart7_idle_pins_a>;
> + uart-has-rtscts;
> + status = "okay";
> +
> + bluetooth {
> + compatible = "infineon,cyw43439-bt", "brcm,bcm4329-bt";
> + max-speed = <3000000>;
> + device-wakeup-gpios = <&gpiog 9 GPIO_ACTIVE_HIGH>;
> + shutdown-gpios = <&gpioi 2 GPIO_ACTIVE_HIGH>;
> + };
> +};
> +
> +&vdd {
> + bootph-all;
> +};
> +
> +&vddcpu {
> + bootph-all;
> +};
> +
> +
> +&vddcore {
> + bootph-all;
> +};
> +
> +&vdd_ddr {
> + bootph-all;
> +};
> +
> +&vref_ddr {
> + bootph-all;
> +};
>
^ permalink raw reply
* Re: [PATCH v4 19/21] uio: replace deprecated mmap hook with mmap_prepare in uio_info
From: Vlastimil Babka (SUSE) @ 2026-03-25 14:13 UTC (permalink / raw)
To: Lorenzo Stoakes (Oracle), Andrew Morton
Cc: Jonathan Corbet, Clemens Ladisch, Arnd Bergmann,
Greg Kroah-Hartman, K . Y . Srinivasan, Haiyang Zhang, Wei Liu,
Dexuan Cui, Long Li, Alexander Shishkin, Maxime Coquelin,
Alexandre Torgue, Miquel Raynal, Richard Weinberger,
Vignesh Raghavendra, Bodo Stroesser, Martin K . Petersen,
David Howells, Marc Dionne, Alexander Viro, Christian Brauner,
Jan Kara, David Hildenbrand, Liam R . Howlett, Mike Rapoport,
Suren Baghdasaryan, Michal Hocko, Jann Horn, Pedro Falcato,
linux-kernel, linux-doc, linux-hyperv, linux-stm32,
linux-arm-kernel, linux-mtd, linux-staging, linux-scsi,
target-devel, linux-afs, linux-fsdevel, linux-mm, Ryan Roberts
In-Reply-To: <157583e4477705b496896c7acd4ac88a937b8fa6.1774045440.git.ljs@kernel.org>
On 3/20/26 23:39, Lorenzo Stoakes (Oracle) wrote:
> The f_op->mmap interface is deprecated, so update uio_info to use its
> successor, mmap_prepare.
>
> Therefore, replace the uio_info->mmap hook with a new
> uio_info->mmap_prepare hook, and update its one user, target_core_user,
> to both specify this new mmap_prepare hook and also to use the new
> vm_ops->mapped() hook to continue to maintain a correct udev->kref
> refcount.
>
> Then update uio_mmap() to utilise the mmap_prepare compatibility layer to
> invoke this callback from the uio mmap invocation.
>
> Signed-off-by: Lorenzo Stoakes (Oracle) <ljs@kernel.org>
Acked-by: Vlastimil Babka (SUSE) <vbabka@kernel.org>
> ---
> drivers/target/target_core_user.c | 26 ++++++++++++++++++--------
> drivers/uio/uio.c | 10 ++++++++--
> include/linux/uio_driver.h | 4 ++--
> 3 files changed, 28 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/target/target_core_user.c b/drivers/target/target_core_user.c
> index af95531ddd35..edc2afd5f4ee 100644
> --- a/drivers/target/target_core_user.c
> +++ b/drivers/target/target_core_user.c
> @@ -1860,6 +1860,17 @@ static struct page *tcmu_try_get_data_page(struct tcmu_dev *udev, uint32_t dpi)
> return NULL;
> }
>
> +static int tcmu_vma_mapped(unsigned long start, unsigned long end, pgoff_t pgoff,
> + const struct file *file, void **vm_private_data)
> +{
> + struct tcmu_dev *udev = *vm_private_data;
> +
> + pr_debug("vma_mapped\n");
This looked like testing leftover at first, but it matches
tcmu_vma_open()/close() (in case anyone else wonders).
> +
> + kref_get(&udev->kref);
> + return 0;
> +}
> +
^ permalink raw reply
* Re: [PATCH v2 0/7] iommu/arm-smmu-v3: Quarantine device upon ATC invalidation timeout
From: Jason Gunthorpe @ 2026-03-25 14:12 UTC (permalink / raw)
To: Tian, Kevin
Cc: Nicolin Chen, will@kernel.org, robin.murphy@arm.com,
joro@8bytes.org, bhelgaas@google.com, rafael@kernel.org,
lenb@kernel.org, praan@google.com, baolu.lu@linux.intel.com,
xueshuai@linux.alibaba.com, linux-arm-kernel@lists.infradead.org,
iommu@lists.linux.dev, linux-kernel@vger.kernel.org,
linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org,
Vikram Sethi
In-Reply-To: <BN9PR11MB5276DBF0624E0EAEDC54874A8C49A@BN9PR11MB5276.namprd11.prod.outlook.com>
On Wed, Mar 25, 2026 at 06:55:40AM +0000, Tian, Kevin wrote:
> > I think this is more of a feature (RAS support for SMMUv3) than a
> > specific fix.
> >
>
> Not a RAS guy, but below is what I got from AI:
>
> "
> RAS improvements typically involve better error reporting, graceful
> degradation, or improved recovery - but they usually don't involve
> scenarios where the system continues operating with compromised
> security assumptions."
Right, so currently there is no RAS in smmuv3, if it hits this error
it continues with "compromised security assumptions". Adding RAS
support is to avoid this.
Jason
^ permalink raw reply
* Re: [PATCH] arm64: dts: st: omit unused pinctrl groups from stm32mp25 dtb files
From: Alexandre TORGUE @ 2026-03-25 14:05 UTC (permalink / raw)
To: Amelie Delaunay, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Maxime Coquelin
Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel
In-Reply-To: <20260311-mp25_pinctrl_omit-v1-1-5a3d40046b10@foss.st.com>
Dear Amélie
On 3/11/26 12:30, Amelie Delaunay wrote:
> stm32mp25-pinctrl.dtsi gathers all pinctrl groups from current and future
> STM32MP25-based boards. Some groups may remain unused by any board,
> resulting in wasted binary space.
> Adding /omit-if-no-ref/ to the groups will remove unused groups from the
> device tree blobs.
>
> Use the following regex to update the file:
> 's/^\t[^:]\+: [^ ]\+ {$/\t\/omit-if-no-ref\/\n&/'
> Also, merge the duplicated pinctrl_z node.
>
> Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
> ---
> arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 44 +++++++++++++++++++++++++--
> 1 file changed, 42 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
> index c34cd33cd855..a7ac9d08484c 100644
> --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
> +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
Applied on stm32-next.
Regards
Alex
^ permalink raw reply
* [PATCH v9 10/11] drm: xlnx: zynqmp: Add support for X403
From: Tomi Valkeinen @ 2026-03-25 14:01 UTC (permalink / raw)
To: Vishal Sagar, Anatoliy Klymenko, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Laurent Pinchart,
Michal Simek, Simon Ser
Cc: dri-devel, linux-kernel, linux-arm-kernel, Geert Uytterhoeven,
Dmitry Baryshkov, Pekka Paalanen, Tomi Valkeinen
In-Reply-To: <20260325-xilinx-formats-v9-0-d03b7e3752e4@ideasonboard.com>
Add support for X403 format.
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Vishal Sagar <vishal.sagar@amd.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
---
drivers/gpu/drm/xlnx/zynqmp_disp.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c b/drivers/gpu/drm/xlnx/zynqmp_disp.c
index 99bc68481020..eed0215ba7c7 100644
--- a/drivers/gpu/drm/xlnx/zynqmp_disp.c
+++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c
@@ -317,6 +317,11 @@ static const struct zynqmp_disp_format avbuf_vid_fmts[] = {
.buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YONLY_10,
.swap = false,
.sf = scaling_factors_101010,
+ }, {
+ .drm_fmt = DRM_FORMAT_X403,
+ .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV24_10,
+ .swap = false,
+ .sf = scaling_factors_101010,
},
};
--
2.43.0
^ permalink raw reply related
* [PATCH v9 11/11] drm: xlnx: zynqmp: Add support for XVUY2101010
From: Tomi Valkeinen @ 2026-03-25 14:01 UTC (permalink / raw)
To: Vishal Sagar, Anatoliy Klymenko, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Laurent Pinchart,
Michal Simek, Simon Ser
Cc: dri-devel, linux-kernel, linux-arm-kernel, Geert Uytterhoeven,
Dmitry Baryshkov, Pekka Paalanen, Tomi Valkeinen
In-Reply-To: <20260325-xilinx-formats-v9-0-d03b7e3752e4@ideasonboard.com>
Add support for XVUY2101010 format.
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Vishal Sagar <vishal.sagar@amd.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
---
drivers/gpu/drm/xlnx/zynqmp_disp.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c b/drivers/gpu/drm/xlnx/zynqmp_disp.c
index eed0215ba7c7..9408f77d45dc 100644
--- a/drivers/gpu/drm/xlnx/zynqmp_disp.c
+++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c
@@ -322,6 +322,11 @@ static const struct zynqmp_disp_format avbuf_vid_fmts[] = {
.buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV24_10,
.swap = false,
.sf = scaling_factors_101010,
+ }, {
+ .drm_fmt = DRM_FORMAT_XVUY2101010,
+ .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YUV444_10,
+ .swap = false,
+ .sf = scaling_factors_101010,
},
};
--
2.43.0
^ permalink raw reply related
* [PATCH v9 09/11] drm: xlnx: zynqmp: Add support for Y8 and XYYY2101010
From: Tomi Valkeinen @ 2026-03-25 14:01 UTC (permalink / raw)
To: Vishal Sagar, Anatoliy Klymenko, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Laurent Pinchart,
Michal Simek, Simon Ser
Cc: dri-devel, linux-kernel, linux-arm-kernel, Geert Uytterhoeven,
Dmitry Baryshkov, Pekka Paalanen, Tomi Valkeinen
In-Reply-To: <20260325-xilinx-formats-v9-0-d03b7e3752e4@ideasonboard.com>
Add support for Y8 and XYYY2101010 formats. We also need to add new csc
matrices for these y-only formats.
Reviewed-by: Vishal Sagar <vishal.sagar@amd.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
---
drivers/gpu/drm/xlnx/zynqmp_disp.c | 27 ++++++++++++++++++++++++++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c b/drivers/gpu/drm/xlnx/zynqmp_disp.c
index 40deca67b83b..99bc68481020 100644
--- a/drivers/gpu/drm/xlnx/zynqmp_disp.c
+++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c
@@ -307,6 +307,16 @@ static const struct zynqmp_disp_format avbuf_vid_fmts[] = {
.buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_10,
.swap = false,
.sf = scaling_factors_101010,
+ }, {
+ .drm_fmt = DRM_FORMAT_Y8,
+ .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_MONO,
+ .swap = false,
+ .sf = scaling_factors_888,
+ }, {
+ .drm_fmt = DRM_FORMAT_XYYY2101010,
+ .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YONLY_10,
+ .swap = false,
+ .sf = scaling_factors_101010,
},
};
@@ -697,6 +707,17 @@ static const u32 csc_sdtv_to_rgb_offsets[] = {
0x0, 0x1800, 0x1800
};
+/* In Y-only mode the single Y channel is on the third column */
+static const u16 csc_sdtv_to_rgb_yonly_matrix[] = {
+ 0x0, 0x0, 0x1000,
+ 0x0, 0x0, 0x1000,
+ 0x0, 0x0, 0x1000,
+};
+
+static const u32 csc_sdtv_to_rgb_yonly_offsets[] = {
+ 0x0, 0x0, 0x0
+};
+
/**
* zynqmp_disp_blend_set_output_format - Set the output format of the blender
* @disp: Display controller
@@ -846,7 +867,11 @@ static void zynqmp_disp_blend_layer_enable(struct zynqmp_disp *disp,
ZYNQMP_DISP_V_BLEND_LAYER_CONTROL(layer->id),
val);
- if (layer->drm_fmt->is_yuv) {
+ if (layer->drm_fmt->format == DRM_FORMAT_Y8 ||
+ layer->drm_fmt->format == DRM_FORMAT_XYYY2101010) {
+ coeffs = csc_sdtv_to_rgb_yonly_matrix;
+ offsets = csc_sdtv_to_rgb_yonly_offsets;
+ } else if (layer->drm_fmt->is_yuv) {
coeffs = csc_sdtv_to_rgb_matrix;
offsets = csc_sdtv_to_rgb_offsets;
} else {
--
2.43.0
^ permalink raw reply related
* [PATCH v9 07/11] drm: xlnx: zynqmp: Use drm helpers when calculating buffer sizes
From: Tomi Valkeinen @ 2026-03-25 14:01 UTC (permalink / raw)
To: Vishal Sagar, Anatoliy Klymenko, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Laurent Pinchart,
Michal Simek, Simon Ser
Cc: dri-devel, linux-kernel, linux-arm-kernel, Geert Uytterhoeven,
Dmitry Baryshkov, Pekka Paalanen, Tomi Valkeinen
In-Reply-To: <20260325-xilinx-formats-v9-0-d03b7e3752e4@ideasonboard.com>
Use drm helpers, drm_format_info_plane_width(),
drm_format_info_plane_height() and drm_format_info_min_pitch() to
calculate sizes for the DMA.
This cleans up the code, but also makes it possible to support more
complex formats (like P030, XV20).
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
---
drivers/gpu/drm/xlnx/zynqmp_disp.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c b/drivers/gpu/drm/xlnx/zynqmp_disp.c
index 9a8f38230cb4..12a8d643915f 100644
--- a/drivers/gpu/drm/xlnx/zynqmp_disp.c
+++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c
@@ -1116,16 +1116,19 @@ int zynqmp_disp_layer_update(struct zynqmp_disp_layer *layer,
return 0;
for (i = 0; i < info->num_planes; i++) {
- unsigned int width = state->crtc_w / (i ? info->hsub : 1);
- unsigned int height = state->crtc_h / (i ? info->vsub : 1);
struct zynqmp_disp_layer_dma *dma = &layer->dmas[i];
struct dma_async_tx_descriptor *desc;
dma_addr_t dma_addr;
+ unsigned int width;
+ unsigned int height;
+
+ width = drm_format_info_plane_width(info, state->crtc_w, i);
+ height = drm_format_info_plane_height(info, state->crtc_h, i);
dma_addr = drm_fb_dma_get_gem_addr(state->fb, state, i);
dma->xt.numf = height;
- dma->sgl.size = width * info->cpp[i];
+ dma->sgl.size = drm_format_info_min_pitch(info, i, width);
dma->sgl.icg = state->fb->pitches[i] - dma->sgl.size;
dma->xt.src_start = dma_addr;
dma->xt.frame_size = 1;
--
2.43.0
^ permalink raw reply related
* [PATCH v9 03/11] drm/fourcc: Add DRM_FORMAT_Y8
From: Tomi Valkeinen @ 2026-03-25 14:01 UTC (permalink / raw)
To: Vishal Sagar, Anatoliy Klymenko, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Laurent Pinchart,
Michal Simek, Simon Ser
Cc: dri-devel, linux-kernel, linux-arm-kernel, Geert Uytterhoeven,
Dmitry Baryshkov, Pekka Paalanen, Tomi Valkeinen, Pekka Paalanen,
Dmitry Baryshkov
In-Reply-To: <20260325-xilinx-formats-v9-0-d03b7e3752e4@ideasonboard.com>
Add greyscale Y8 format.
The 8-bit greyscale format has been discussed before, and the earlier
guidance was to use DRM_FORMAT_R8, as a single-channel 8-bit pixel.
However, adding DRM_FORMAT_Y8 makes sense, we can mark it as 'is_yuv' in
the drm_format_info, and this can help the drivers handle e.g.
full/limited range. This will distinguish two single-channel formats:
R8, which is a RGB format with the same value for all components, and
Y8, which is a Y-only YCbCr format, with Cb and Cr being neutral.
Acked-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Pekka Paalanen <pekka.paalanen@collabora.com>
Reviewed-by: Vishal Sagar <vishal.sagar@amd.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
---
drivers/gpu/drm/drm_fourcc.c | 1 +
include/uapi/drm/drm_fourcc.h | 9 +++++++++
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index 4fd37226b647..a8ea1f3660cb 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -275,6 +275,7 @@ const struct drm_format_info *__drm_format_info(u32 format)
{ .format = DRM_FORMAT_YVU422, .depth = 0, .num_planes = 3, .cpp = { 1, 1, 1 }, .hsub = 2, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_YUV444, .depth = 0, .num_planes = 3, .cpp = { 1, 1, 1 }, .hsub = 1, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_YVU444, .depth = 0, .num_planes = 3, .cpp = { 1, 1, 1 }, .hsub = 1, .vsub = 1, .is_yuv = true },
+ { .format = DRM_FORMAT_Y8, .depth = 8, .num_planes = 1, .cpp = { 1, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_NV12, .depth = 0, .num_planes = 2, .cpp = { 1, 2, 0 }, .hsub = 2, .vsub = 2, .is_yuv = true },
{ .format = DRM_FORMAT_NV21, .depth = 0, .num_planes = 2, .cpp = { 1, 2, 0 }, .hsub = 2, .vsub = 2, .is_yuv = true },
{ .format = DRM_FORMAT_NV16, .depth = 0, .num_planes = 2, .cpp = { 1, 2, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 10cc13bdb495..02205ec4a75a 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -458,6 +458,15 @@ extern "C" {
#define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */
#define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */
+/*
+ * Y-only (greyscale) formats
+ *
+ * The Y-only formats are handled similarly to the YCbCr formats in the display
+ * pipeline, with the Cb and Cr implicitly neutral (0.0 in nominal values). This
+ * also means that COLOR_RANGE property applies to the Y-only formats.
+ */
+
+#define DRM_FORMAT_Y8 fourcc_code('G', 'R', 'E', 'Y') /* 8-bit Y-only */
/*
* Format Modifiers:
--
2.43.0
^ permalink raw reply related
* [PATCH v9 05/11] drm/fourcc: Add DRM_FORMAT_X403
From: Tomi Valkeinen @ 2026-03-25 14:01 UTC (permalink / raw)
To: Vishal Sagar, Anatoliy Klymenko, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Laurent Pinchart,
Michal Simek, Simon Ser
Cc: dri-devel, linux-kernel, linux-arm-kernel, Geert Uytterhoeven,
Dmitry Baryshkov, Pekka Paalanen, Tomi Valkeinen
In-Reply-To: <20260325-xilinx-formats-v9-0-d03b7e3752e4@ideasonboard.com>
Add X403, a 3 plane 10 bits per component non-subsampled YCbCr format.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Vishal Sagar <vishal.sagar@amd.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
---
drivers/gpu/drm/drm_fourcc.c | 3 +++
include/uapi/drm/drm_fourcc.h | 9 +++++++++
2 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index 4fc1880603bc..de8c98b166f1 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -388,6 +388,9 @@ const struct drm_format_info *__drm_format_info(u32 format)
{ .format = DRM_FORMAT_XYYY2101010, .depth = 0, .num_planes = 1,
.char_per_block = { 4, 0, 0 }, .block_w = { 3, 0, 0 }, .block_h = { 1, 0, 0 },
.hsub = 1, .vsub = 1, .is_yuv = true },
+ { .format = DRM_FORMAT_X403, .depth = 0, .num_planes = 3,
+ .char_per_block = { 4, 4, 4 }, .block_w = { 3, 3, 3 }, .block_h = { 1, 1, 1 },
+ .hsub = 1, .vsub = 1, .is_yuv = true },
};
unsigned int i;
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index c6d4754ec202..385da5942716 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -402,6 +402,15 @@ extern "C" {
*/
#define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1')
+/*
+ * 3 plane non-subsampled (444) YCbCr
+ * 10 bpc, 30 bits per sample image data in a single contiguous buffer.
+ * index 0: Y plane, [31:0] x:Y2:Y1:Y0 [2:10:10:10] little endian
+ * index 1: Cb plane, [31:0] x:Cb2:Cb1:Cb0 [2:10:10:10] little endian
+ * index 2: Cr plane, [31:0] x:Cr2:Cr1:Cr0 [2:10:10:10] little endian
+ */
+#define DRM_FORMAT_X403 fourcc_code('X', '4', '0', '3')
+
/*
* 3 plane YCbCr LSB aligned
* In order to use these formats in a similar fashion to MSB aligned ones
--
2.43.0
^ permalink raw reply related
* [PATCH v9 08/11] drm: xlnx: zynqmp: Add support for P030 & XV20
From: Tomi Valkeinen @ 2026-03-25 14:01 UTC (permalink / raw)
To: Vishal Sagar, Anatoliy Klymenko, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Laurent Pinchart,
Michal Simek, Simon Ser
Cc: dri-devel, linux-kernel, linux-arm-kernel, Geert Uytterhoeven,
Dmitry Baryshkov, Pekka Paalanen, Tomi Valkeinen
In-Reply-To: <20260325-xilinx-formats-v9-0-d03b7e3752e4@ideasonboard.com>
Add support for P030 & XV20 formats.
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Vishal Sagar <vishal.sagar@amd.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
---
drivers/gpu/drm/xlnx/zynqmp_disp.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/xlnx/zynqmp_disp.c b/drivers/gpu/drm/xlnx/zynqmp_disp.c
index 12a8d643915f..40deca67b83b 100644
--- a/drivers/gpu/drm/xlnx/zynqmp_disp.c
+++ b/drivers/gpu/drm/xlnx/zynqmp_disp.c
@@ -297,6 +297,16 @@ static const struct zynqmp_disp_format avbuf_vid_fmts[] = {
.buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_420,
.swap = true,
.sf = scaling_factors_888,
+ }, {
+ .drm_fmt = DRM_FORMAT_P030,
+ .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_420_10,
+ .swap = false,
+ .sf = scaling_factors_101010,
+ }, {
+ .drm_fmt = DRM_FORMAT_XV20,
+ .buf_fmt = ZYNQMP_DISP_AV_BUF_FMT_NL_VID_YV16CI_10,
+ .swap = false,
+ .sf = scaling_factors_101010,
},
};
--
2.43.0
^ permalink raw reply related
* [PATCH v9 06/11] drm/fourcc: Add DRM_FORMAT_XVUY2101010
From: Tomi Valkeinen @ 2026-03-25 14:01 UTC (permalink / raw)
To: Vishal Sagar, Anatoliy Klymenko, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Laurent Pinchart,
Michal Simek, Simon Ser
Cc: dri-devel, linux-kernel, linux-arm-kernel, Geert Uytterhoeven,
Dmitry Baryshkov, Pekka Paalanen, Tomi Valkeinen
In-Reply-To: <20260325-xilinx-formats-v9-0-d03b7e3752e4@ideasonboard.com>
Add XVUY2101010, a 10 bits per component YCbCr format in a 32 bit
container.
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Vishal Sagar <vishal.sagar@amd.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
---
drivers/gpu/drm/drm_fourcc.c | 1 +
include/uapi/drm/drm_fourcc.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index de8c98b166f1..c4ce7ee74dea 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -288,6 +288,7 @@ const struct drm_format_info *__drm_format_info(u32 format)
{ .format = DRM_FORMAT_VYUY, .depth = 0, .num_planes = 1, .cpp = { 2, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_XYUV8888, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_VUY888, .depth = 0, .num_planes = 1, .cpp = { 3, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
+ { .format = DRM_FORMAT_XVUY2101010, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_AYUV, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 1, .vsub = 1, .has_alpha = true, .is_yuv = true },
{ .format = DRM_FORMAT_Y210, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
{ .format = DRM_FORMAT_Y212, .depth = 0, .num_planes = 1, .cpp = { 4, 0, 0 }, .hsub = 2, .vsub = 1, .is_yuv = true },
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 385da5942716..2c8f5d637e16 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -264,6 +264,7 @@ extern "C" {
#define DRM_FORMAT_XVUY8888 fourcc_code('X', 'V', 'U', 'Y') /* [31:0] X:Cr:Cb:Y 8:8:8:8 little endian */
#define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */
#define DRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */
+#define DRM_FORMAT_XVUY2101010 fourcc_code('X', 'Y', '3', '0') /* [31:0] x:Cr:Cb:Y 2:10:10:10 little endian */
/*
* packed Y2xx indicate for each component, xx valid data occupy msb
--
2.43.0
^ permalink raw reply related
* [PATCH v9 04/11] drm/fourcc: Add DRM_FORMAT_XYYY2101010
From: Tomi Valkeinen @ 2026-03-25 14:01 UTC (permalink / raw)
To: Vishal Sagar, Anatoliy Klymenko, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Laurent Pinchart,
Michal Simek, Simon Ser
Cc: dri-devel, linux-kernel, linux-arm-kernel, Geert Uytterhoeven,
Dmitry Baryshkov, Pekka Paalanen, Tomi Valkeinen, Pekka Paalanen
In-Reply-To: <20260325-xilinx-formats-v9-0-d03b7e3752e4@ideasonboard.com>
Add XYYY2101010 ("YPA4"), a 10 bit greyscale format, with 3 pixels
packed into 32-bit container, and two bits of padding.
The fourcc for the format is 'YPA4', which comes from Y - Y only, P -
packed, A - 10 (as in 0xA), 4 - 4 bytes.
Reviewed-by: Vishal Sagar <vishal.sagar@amd.com>
Reviewed-by: Pekka Paalanen <pekka.paalanen@collabora.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
---
drivers/gpu/drm/drm_fourcc.c | 3 +++
include/uapi/drm/drm_fourcc.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index a8ea1f3660cb..4fc1880603bc 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -385,6 +385,9 @@ const struct drm_format_info *__drm_format_info(u32 format)
{ .format = DRM_FORMAT_XV20, .depth = 0, .num_planes = 2,
.char_per_block = { 4, 8, 0 }, .block_w = { 3, 3, 0 }, .block_h = { 1, 1, 0 },
.hsub = 2, .vsub = 1, .is_yuv = true },
+ { .format = DRM_FORMAT_XYYY2101010, .depth = 0, .num_planes = 1,
+ .char_per_block = { 4, 0, 0 }, .block_w = { 3, 0, 0 }, .block_h = { 1, 0, 0 },
+ .hsub = 1, .vsub = 1, .is_yuv = true },
};
unsigned int i;
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 02205ec4a75a..c6d4754ec202 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -467,6 +467,7 @@ extern "C" {
*/
#define DRM_FORMAT_Y8 fourcc_code('G', 'R', 'E', 'Y') /* 8-bit Y-only */
+#define DRM_FORMAT_XYYY2101010 fourcc_code('Y', 'P', 'A', '4') /* [31:0] x:Y2:Y1:Y0 2:10:10:10 little endian */
/*
* Format Modifiers:
--
2.43.0
^ permalink raw reply related
* [PATCH v9 01/11] drm/fourcc: Add warning for bad bpp
From: Tomi Valkeinen @ 2026-03-25 14:01 UTC (permalink / raw)
To: Vishal Sagar, Anatoliy Klymenko, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Laurent Pinchart,
Michal Simek, Simon Ser
Cc: dri-devel, linux-kernel, linux-arm-kernel, Geert Uytterhoeven,
Dmitry Baryshkov, Pekka Paalanen, Tomi Valkeinen
In-Reply-To: <20260325-xilinx-formats-v9-0-d03b7e3752e4@ideasonboard.com>
drm_format_info_bpp() cannot be used for formats which do not have an
integer bits-per-pixel in a pixel block.
E.g. DRM_FORMAT_P030's plane 0 has three 10-bit pixels (Y components),
and two padding bits, in a 4 byte block. That is 10.666... bits per
pixel when considering the whole 4 byte block, which is what
drm_format_info_bpp() does. Thus a driver that supports such formats
cannot use drm_format_info_bpp(),
It is a driver bug if this happens, but so handle wrong calls by
printing a warning and returning 0.
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
---
drivers/gpu/drm/drm_fourcc.c | 14 +++++++++++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index e0d533611040..e662aea9d105 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -491,12 +491,20 @@ EXPORT_SYMBOL(drm_format_info_block_height);
*/
unsigned int drm_format_info_bpp(const struct drm_format_info *info, int plane)
{
+ unsigned int block_size;
+
if (!info || plane < 0 || plane >= info->num_planes)
return 0;
- return info->char_per_block[plane] * 8 /
- (drm_format_info_block_width(info, plane) *
- drm_format_info_block_height(info, plane));
+ block_size = drm_format_info_block_width(info, plane) *
+ drm_format_info_block_height(info, plane);
+
+ if (info->char_per_block[plane] * 8 % block_size) {
+ pr_warn("unable to return an integer bpp\n");
+ return 0;
+ }
+
+ return info->char_per_block[plane] * 8 / block_size;
}
EXPORT_SYMBOL(drm_format_info_bpp);
--
2.43.0
^ permalink raw reply related
* [PATCH v9 02/11] drm/fourcc: Add DRM_FORMAT_XV20
From: Tomi Valkeinen @ 2026-03-25 14:01 UTC (permalink / raw)
To: Vishal Sagar, Anatoliy Klymenko, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Laurent Pinchart,
Michal Simek, Simon Ser
Cc: dri-devel, linux-kernel, linux-arm-kernel, Geert Uytterhoeven,
Dmitry Baryshkov, Pekka Paalanen, Tomi Valkeinen,
Dmitry Baryshkov
In-Reply-To: <20260325-xilinx-formats-v9-0-d03b7e3752e4@ideasonboard.com>
Add a new pixel format, DRM_FORMAT_XV20 ("XV20")
XV20 is 2 plane 10 bit per component YCbCr 2x1 subsampled format. XV20
is similar to the already existing P030 format, which is 2x2 subsampled.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Vishal Sagar <vishal.sagar@amd.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
---
drivers/gpu/drm/drm_fourcc.c | 3 +++
include/uapi/drm/drm_fourcc.h | 7 +++++++
2 files changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/drm_fourcc.c b/drivers/gpu/drm/drm_fourcc.c
index e662aea9d105..4fd37226b647 100644
--- a/drivers/gpu/drm/drm_fourcc.c
+++ b/drivers/gpu/drm/drm_fourcc.c
@@ -381,6 +381,9 @@ const struct drm_format_info *__drm_format_info(u32 format)
{ .format = DRM_FORMAT_S416, .depth = 0, .num_planes = 3,
.char_per_block = { 2, 2, 2 }, .block_w = { 1, 1, 1 }, .block_h = { 1, 1, 1 },
.hsub = 1, .vsub = 1, .is_yuv = true},
+ { .format = DRM_FORMAT_XV20, .depth = 0, .num_planes = 2,
+ .char_per_block = { 4, 8, 0 }, .block_w = { 3, 3, 0 }, .block_h = { 1, 1, 0 },
+ .hsub = 2, .vsub = 1, .is_yuv = true },
};
unsigned int i;
diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index c89aede3cb12..10cc13bdb495 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -322,6 +322,13 @@ extern "C" {
#define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8')
#define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8')
+/*
+ * 2 plane 10 bit per component YCrCb
+ * index 0 = Y plane, [31:0] x:Y2:Y1:Y0 2:10:10:10 little endian
+ * index 1 = Cb:Cr plane, [63:0] x:Cr2:Cb2:Cr1:x:Cb1:Cr0:Cb0 2:10:10:10:2:10:10:10 little endian
+ */
+#define DRM_FORMAT_XV20 fourcc_code('X', 'V', '2', '0') /* 2x1 subsampled Cr:Cb plane 2:10:10:10 */
+
/*
* 2 plane YCbCr
* index 0 = Y plane, [7:0] Y
--
2.43.0
^ permalink raw reply related
* [PATCH v9 00/11] drm: Add new pixel formats for Xilinx Zynqmp
From: Tomi Valkeinen @ 2026-03-25 14:01 UTC (permalink / raw)
To: Vishal Sagar, Anatoliy Klymenko, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Laurent Pinchart,
Michal Simek, Simon Ser
Cc: dri-devel, linux-kernel, linux-arm-kernel, Geert Uytterhoeven,
Dmitry Baryshkov, Pekka Paalanen, Tomi Valkeinen, Pekka Paalanen,
Dmitry Baryshkov
Add new DRM pixel formats and add support for those in the Xilinx zynqmp
display driver.
All other formats except XVUY2101010 are already supported in upstream
gstreamer, but gstreamer's kmssink does not have the support yet, as it
obviously cannot support the formats without kernel having the formats.
Xilinx has support for these formats in their BSP kernel, and Xilinx has
a branch here, adding the support to gstreamer kmssink:
https://github.com/Xilinx/gst-plugins-bad.git xlnx-rebase-v1.18.5
New formats added:
DRM_FORMAT_Y8
- 8-bit Y-only
- fourcc: "GREY"
- gstreamer: GRAY8
DRM_FORMAT_XYYY2101010
- 10-bit Y-only, three pixels packed into 32-bits
- fourcc: "YPA4"
- gstreamer: GRAY10_LE32
DRM_FORMAT_XV20
- Like NV16, but with 10-bit components
- fourcc: "XV20"
- gstreamer: NV16_10LE32
DRM_FORMAT_X403
- 10-bit planar 4:4:4, with three samples packed into 32-bits
- fourcc: "X403"
- gstreamer: Y444_10LE32
XVUY2101010
- 10-bit 4:4:4, one pixel in 32 bits
- fourcc: "XY30"
Some notes:
I know the 8-bit greyscale format has been discussed before, and the
guidance was to use DRM_FORMAT_R8. While I'm not totally against that, I
would argue that adding DRM_FORMAT_Y8 makes sense, as:
1) We can mark it as 'is_yuv' in the drm_format_info, and this can help
the drivers handle e.g. full/limited range. Probably some hardware
handles grayscale as a value used for all RGB components, in which case
R8 makes sense, but when the hardware handles the Y-only pixels as YCbCr,
where Cb and Cr are "neutral", it makes more sense to consider the
format as an YUV format rather than RGB.
2) We can have the same fourcc as in v4l2. While not strictly necessary,
it's a constant source of confusion when the fourccs differ.
3) It (possibly) makes more sense for the user to use Y8/GREY format
instead of R8, as, in my experience, the documentation usually refers
to gray(scale) format or Y-only format.
I have made some adjustments to the formats compared to the Xilinx's
branch. E.g. The DRM_FORMAT_XYYY2101010 format in Xilinx's kmssink uses
fourcc "Y10 ", and DRM_FORMAT_Y10. I didn't like those, as the format is
a packed format, three 10-bit pixels in a 32-bit container, and I think
Y10 means a 10-bit pixel in a 16-bit container. Xilinx also has XV15
format (similar to XV20, but 2x2 subsampled), which already exists in
the kernel as P030.
Generally speaking, if someone has good ideas for the format define
names or fourccs, speak up, as it's not easy to invent good names =).
That said, keeping them the same as in the Xilinx trees will, of course,
be slightly easier for the users of Xilinx platforms.
Note: Earlier versions of the series had DRM_FORMAT_Y10_P32, which is
now DRM_FORMAT_XYYY2101010, and DRM_FORMAT_XV15, which is now removed as
P030 already exists.
[1] https://lore.kernel.org/all/20250109150310.219442-26-tzimmermann%40suse.de/
[2] git@github.com:tomba/kmsxx.git xilinx
[3] git@github.com:tomba/pykms.git xilinx
[4] git@github.com:tomba/pixutils.git xilinx
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
---
Changes in v9:
- Drop DRM_FORMAT_XV15 as DRM_FORMAT_P030 already exists
- Rename DRM_FORMAT_Y10_P32 to DRM_FORMAT_XYYY2101010
- I kept the Reviewed-bys related to the above, although one could say
renaming the format names is a substantial change. Ping me if you want
me to drop the Rb and re-send.
- Link to v8: https://lore.kernel.org/r/20260128-xilinx-formats-v8-0-9ea8adb70269@ideasonboard.com
Changes in v8:
- Expand the "drm/fourcc: Add DRM_FORMAT_Y8" commit description to
explain the rationale
- Add comment to "drm: xlnx: zynqmp: Add support for Y8 and Y10_P32"
explainig the Y-only matrix
- Remove extra blank line
- Link to v7: https://lore.kernel.org/r/20251201-xilinx-formats-v7-0-1e1558adfefc@ideasonboard.com
Changes in v7:
- Added Reviewed-bys
- Rebased on v6.18
- Link to v6: https://lore.kernel.org/r/20251001-xilinx-formats-v6-0-014b076b542a@ideasonboard.com
Changes in v6:
- Added tags for reviews
- Rebased on v6.17
- Link to v5: https://lore.kernel.org/r/20250425-xilinx-formats-v5-0-c74263231630@ideasonboard.com
Changes in v5:
- Add comment about Y-only formats, clarifying how the display pipeline
handles them (they're handled as YCbCr, with Cb and Cr as "neutral")
- Clarify X403 format in the patch description
- Set unused Y-only CSC offsets to 0 (instead of 0x1800).
- Add R-bs
- Link to v4: https://lore.kernel.org/r/20250326-xilinx-formats-v4-0-322a300c6d72@ideasonboard.com
Changes in v4:
- Reformat the drm_format_info entries a bit
- Calculate block size only once in drm_format_info_bpp()
- Declare local variables in separate lines
- Add review tags
- Fix commit message referring to Y10_LE32 (should be Y10_P32)
- Link to v3: https://lore.kernel.org/r/20250212-xilinx-formats-v3-0-90d0fe106995@ideasonboard.com
Changes in v3:
- Drop "drm: xlnx: zynqmp: Fix max dma segment size". It is already
pushed.
- Add XVUY2101010 format.
- Rename DRM_FORMAT_Y10_LE32 to DRM_FORMAT_Y10_P32.
- Link to v2: https://lore.kernel.org/r/20250115-xilinx-formats-v2-0-160327ca652a@ideasonboard.com
Changes in v2:
- I noticed V4L2 already has fourcc Y10P, referring to MIPI-style packed
Y10 format. So I changed Y10_LE32 fourcc to YPA4. If logic has any
relevance here, P means packed, A means 10, 4 means "in 4 bytes".
- Added tags to "Fix max dma segment size" patch
- Updated description for "Add warning for bad bpp"
- Link to v1: https://lore.kernel.org/r/20241204-xilinx-formats-v1-0-0bf2c5147db1@ideasonboard.com
---
Tomi Valkeinen (11):
drm/fourcc: Add warning for bad bpp
drm/fourcc: Add DRM_FORMAT_XV20
drm/fourcc: Add DRM_FORMAT_Y8
drm/fourcc: Add DRM_FORMAT_XYYY2101010
drm/fourcc: Add DRM_FORMAT_X403
drm/fourcc: Add DRM_FORMAT_XVUY2101010
drm: xlnx: zynqmp: Use drm helpers when calculating buffer sizes
drm: xlnx: zynqmp: Add support for P030 & XV20
drm: xlnx: zynqmp: Add support for Y8 and XYYY2101010
drm: xlnx: zynqmp: Add support for X403
drm: xlnx: zynqmp: Add support for XVUY2101010
drivers/gpu/drm/drm_fourcc.c | 25 +++++++++++++++--
drivers/gpu/drm/xlnx/zynqmp_disp.c | 56 +++++++++++++++++++++++++++++++++++---
include/uapi/drm/drm_fourcc.h | 27 ++++++++++++++++++
3 files changed, 101 insertions(+), 7 deletions(-)
---
base-commit: 11439c4635edd669ae435eec308f4ab8a0804808
change-id: 20241120-xilinx-formats-f71901621833
Best regards,
--
Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
^ permalink raw reply
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