* Re: [PATCH 4/4] arm64: dts: renesas: Fix KSZ9131 PHY bogus txdv-skew-psec property
From: Geert Uytterhoeven @ 2026-03-25 14:29 UTC (permalink / raw)
To: Marek Vasut
Cc: linux-arm-kernel, Biju Das, Conor Dooley, Krzysztof Kozlowski,
Lad Prabhakar, Magnus Damm, Rob Herring, devicetree, linux-kernel,
linux-renesas-soc
In-Reply-To: <20260313164008.40933-5-marek.vasut+renesas@mailbox.org>
On Fri, 13 Mar 2026 at 17:40, Marek Vasut
<marek.vasut+renesas@mailbox.org> wrote:
> The KSZ9131 schema does not document "txdv-skew-psec" property, neither
> does the kernel driver support this property. It does however document
> and support "txen-skew-psec" property. Fix what is likely a copy-paste
> error from the matching "rxdv-skew-psec" property, use "txen-skew-psec"
> property instead of "txdv-skew-psec" property.
>
> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v7.1.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH v3 0/9] mtd: rawnand: sunxi: Fixes user data length for H6
From: Miquel Raynal @ 2026-03-25 14:29 UTC (permalink / raw)
To: Richard Weinberger, Vignesh Raghavendra, Jernej Skrabec,
Samuel Holland, Chen-Yu Tsai, Richard Genoud
Cc: Wentao Liang, Maxime Ripard, Boris Brezillon, Thomas Petazzoni,
linux-mtd, linux-arm-kernel, linux-sunxi, linux-kernel
In-Reply-To: <20260317142437.580204-1-richard.genoud@bootlin.com>
On Tue, 17 Mar 2026 15:24:28 +0100, Richard Genoud wrote:
> This series introduces the correct usage of user data length for
> H6/H616.
> If the older SoCs must use a fixed value of 4 user data bytes for each
> ECC step, the H6 can have a different value for each step.
>
> In the first round, the behavior was kept as the one used by A10.
> But we have multiple choices:
> - do like A10 like before (and not use all OOB)
> - do like the vendor kernel (different from A10, but not using all OOB)
> - use the whole OOB for user data bytes
>
> [...]
Applied to nand/next, thanks!
[1/9] mtd: rawnand: sunxi: sunxi_nand_ooblayout_free code clarification
commit: 87f9c59f896fd46d45be76d8a8286a6916ce1f1a
[2/9] mtd: rawnand: sunxi: fix sunxi_nfc_hw_ecc_read_extra_oob
commit: 848c13996c55fe4ea6bf5acc3ce6c8c5c944b5f6
[3/9] mtd: rawnand: sunxi: do not count BBM bytes twice
commit: 8fa72836be11ea70cbfa43f7f2253fa57ccc6ecd
[4/9] mtd: rawnand: sunxi: replace hard coded value by a define - take2
commit: e3fd963da4c7469757d4f7741157fc5e23da47ed
[5/9] mtd: rawnand: sunxi: make the code more self-explanatory
commit: 548f87ed47479e08203bc576cb5020f537e49bce
[6/9] mtd: rawnand: sunxi: remove dead code
commit: 2781542caf681ce52f213152104fb7669263651c
[7/9] mtd: rawnand: sunxi: change error prone variable name
commit: a1c967f5d6a568dd24583917774e0178b8e39221
[8/9] mtd: rawnand: sunxi: fix typos in comments
commit: a22f40d9eb1ef587a8201fde3f004173fd8b5e8e
[9/9] mtd: rawnand: sunxi: introduce maximize variable user data length
commit: 54dcd6aa69db541529a083b31f106ef7d147fea1
Patche(s) should be available on mtd/linux.git and will be
part of the next PR (provided that no robot complains by then).
Kind regards,
Miquèl
^ permalink raw reply
* Re: [PATCH 0/4] arm64: dts: renesas: Fix PHY C22 compatible strings
From: Geert Uytterhoeven @ 2026-03-25 14:32 UTC (permalink / raw)
To: Marek Vasut
Cc: Biju Das, Marek Vasut, linux-arm-kernel@lists.infradead.org,
Conor Dooley, Geert Uytterhoeven, Krzysztof Kozlowski,
Prabhakar Mahadev Lad, magnus.damm, Rob Herring,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-renesas-soc@vger.kernel.org
In-Reply-To: <15b47af5-1249-4911-b9de-7ee177740314@mailbox.org>
Hi Marek,
On Mon, 16 Mar 2026 at 13:37, Marek Vasut <marek.vasut@mailbox.org> wrote:
> On 3/16/26 10:11 AM, Biju Das wrote:
> >> There is also Marek's older series ([1][2], as Marek doesn't do cover letters ;-).
>
> You seem to be commenting on a 0/4 cover letter here ...
Ha, the exception to the general rule ;-)
> >> [1] "[PATCH 1/2] ARM: dts: renesas: Drop ethernet-phy-ieee802.3-c22 from PHY compatible string on all
> >> RZ boards"
> >> https://lore.kernel.org/20240630034649.173229-1-marex@denx.de/
> >> [2] "[PATCH 2/2] arm64: dts: renesas: Drop ethernet-phy-ieee802.3-c22 from PHY compatible string on
> >> all RZ boards"
> >> https://lore.kernel.org/20240630034649.173229-2-marex@denx.de
> >
> > I haven't seen these patches.
>
> They are deprecated.
>
> > It does not cover all the SoCs/boards. If Marek want to take over, He can send next version
> > covering all Renesas boards + binding change.
> Isn't this series effectively exactly that ?
I believe we still have e.g. the KSZ8041 and KSZ9031 PHY nodes to fix,
for both RZ and R-Car boards? Some of them were covered by [1] and
[2] above.
Thanks!
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH v2] KVM: arm64: Prevent the host from using an smc with imm16 != 0
From: Marc Zyngier @ 2026-03-25 14:33 UTC (permalink / raw)
To: Mark Rutland
Cc: Sebastian Ene, kvmarm, linux-arm-kernel, linux-kernel,
android-kvm, catalin.marinas, joey.gouly, oupton, suzuki.poulose,
tabba, vdonnefort, will, yuzenghui
In-Reply-To: <acPi5V0DgGcgHNGO@J2N7QTR9R3>
On Wed, 25 Mar 2026 13:28:05 +0000,
Mark Rutland <mark.rutland@arm.com> wrote:
>
> On Wed, Mar 25, 2026 at 11:31:38AM +0000, Sebastian Ene wrote:
> > The ARM Service Calling Convention (SMCCC) specifies that the function
> > identifier and parameters should be passed in registers, leaving the
> > 16-bit immediate field of the SMC instruction un-handled.
>
> That's not quite right; the SMCCC spec says callers must use immediate
> 0.
>
> See https://developer.arm.com/documentation/den0028/h/ section 2.10
> ("SME and HVC immediate value"), which says:
>
> | • For all compliant calls, an SMC or HVC immediate value of zero must be
> | used.
> | • Nonzero immediate values in SMC instructions are reserved.
> | • Nonzero immediate values in HVC instructions are designated for use by
> | hypervisor vendors.
>
> > Currently, our pKVM handler ignores the immediate value, which could lead
> > to non-compliant software relying on implementation-defined behavior.
> > Enforce the host kernel running under pKVM to use an immediate value
> > of 0 by decoding the ISS from the ESR_EL2 and return a not supported
> > error code back to the caller.
>
> From my PoV, it'd be fine to turn a non-zero immediate into an UNDEF:
I disagree. If SMC can be handled at all, then it cannot UNDEF based
on the immediate -- the is no provision for that in the architecture.
If it can UNDEF, then it must UNDEF always (as if SCR_EL3.SMD == 1).
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
^ permalink raw reply
* Re: [PATCH v4 4/9] media: Add P010 video format
From: Sven Püschel @ 2026-03-25 14:34 UTC (permalink / raw)
To: Benjamin Gaignard, hverkuil, ezequiel, p.zabel, mchehab, shawnguo,
s.hauer, festevam, gregkh, mripard, paul.kocialkowski, wens,
jernej.skrabec, emil.l.velikov, andrzej.p, jc, jernej.skrabec,
nicolas, cphealy
Cc: kernel, linux-imx, linux-media, linux-rockchip, linux-arm-kernel,
linux-kernel
In-Reply-To: <20210625141143.577998-5-benjamin.gaignard@collabora.com>
Hi Benjamin,
On 6/25/21 4:11 PM, Benjamin Gaignard wrote:
> P010 is a YUV format with 10-bits per pixel with interleaved UV.
>
> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
> ---
> Note that P010 is already known in GStreamer, only the mapping with
> v4l2 pixel format is missing.
>
> version 2:
> - Add documentation about P010 padding
> - Fix the number of bits per component (16)
>
> .../media/v4l/pixfmt-yuv-planar.rst | 78 ++++++++++++++++++-
> drivers/media/v4l2-core/v4l2-common.c | 1 +
> drivers/media/v4l2-core/v4l2-ioctl.c | 1 +
> include/uapi/linux/videodev2.h | 1 +
> 4 files changed, 79 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst b/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst
> index 090c091affd2..af400d37c8fd 100644
> --- a/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst
> +++ b/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst
> @@ -100,8 +100,13 @@ All components are stored with the same number of bits per component.
> - Cb, Cr
> - No
> - 64x32 macroblocks
> -
> - Horizontal Z order
> + * - V4L2_PIX_FMT_P010
> + - 'P010'
> + - 16
> + - 4:2:0
> + - Cb, Cr
> + - No
> + - Linear
> * - V4L2_PIX_FMT_NV12MT_16X16
> - 'VM12'
> - 8
> @@ -171,6 +176,7 @@ horizontally.
> .. _V4L2-PIX-FMT-NV21:
> .. _V4L2-PIX-FMT-NV12M:
> .. _V4L2-PIX-FMT-NV21M:
> +.. _V4L2-PIX-FMT-P010:
>
> NV12, NV21, NV12M and NV21M
> ---------------------------
> @@ -470,6 +476,74 @@ number of lines as the luma plane.
> - Cb\ :sub:`33`
> - Cr\ :sub:`33`
>
> +.. _V4L2_PIX_FMT_P010:
> +
> +P010
> +----
> +
> +The number of bytes in one luminance row must be divisible by 16,
> +which means there will be padded 0 in the right edge when necessary.
> +
> +.. raw:: latex
> +
> + \begingroup
> + \small
> + \setlength{\tabcolsep}{2pt}
> +
> +.. tabularcolumns:: |p{2.6cm}|p{0.70cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|p{0.22cm}|
> +
> +.. flat-table:: P010 16 Bits per component
> + :header-rows: 2
> + :stub-columns: 0
> +
> + * - Identifier
> + - Code
> + - :cspan:`7` Byte 0 in memory
> +
> + - :cspan:`7` Byte 1
> + * -
> + -
> + - 7
> + - 6
> + - 5
> + - 4
> + - 3
> + - 2
> + - 1
> + - 0
> +
> + - 7
> + - 6
> + - 5
> + - 4
> + - 3
> + - 2
> + - 1
> + - 0
> + * - ``V4L2_PIX_FMT_P010``
> + - 'P010'
> +
> + - Y\ :sub:`9`
> + - Y\ :sub:`8`
> + - Y\ :sub:`7`
> + - Y\ :sub:`6`
> + - Y\ :sub:`5`
> + - Y\ :sub:`4`
> + - Y\ :sub:`3`
> + - Y\ :sub:`2`
> +
> + - Y\ :sub:`1`
> + - Y\ :sub:`0`
> + - 0
> + - 0
> + - 0
> + - 0
> + - 0
> + - 0
> +
> +.. raw:: latex
> +
> + \endgroup
>
> Fully Planar YUV Formats
> ========================
> diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c
> index 04af03285a20..37b5d82359dd 100644
> --- a/drivers/media/v4l2-core/v4l2-common.c
> +++ b/drivers/media/v4l2-core/v4l2-common.c
> @@ -266,6 +266,7 @@ const struct v4l2_format_info *v4l2_format_info(u32 format)
> { .format = V4L2_PIX_FMT_NV61, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 2, .vdiv = 1 },
> { .format = V4L2_PIX_FMT_NV24, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 1, .vdiv = 1 },
> { .format = V4L2_PIX_FMT_NV42, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 1, .vdiv = 1 },
> + { .format = V4L2_PIX_FMT_P010, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 2, 2, 0, 0 }, .hdiv = 2, .vdiv = 1 },
Just stumbled on this. Shouldn't the bpp be 2, 4 (instead of 2,2) and
the vdiv also 2, given that it's basically NV12 with 10bit data
contained in 16bit values [1]? Or did I miss something?
[1]
https://docs.kernel.org/userspace-api/media/v4l/pixfmt-yuv-planar.html#p010-and-tiled-p010
Sincerely
Sven
>
> { .format = V4L2_PIX_FMT_YUV410, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 }, .hdiv = 4, .vdiv = 4 },
> { .format = V4L2_PIX_FMT_YVU410, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 3, .bpp = { 1, 1, 1, 0 }, .hdiv = 4, .vdiv = 4 },
> diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c
> index 05d5db3d85e5..0044987a727a 100644
> --- a/drivers/media/v4l2-core/v4l2-ioctl.c
> +++ b/drivers/media/v4l2-core/v4l2-ioctl.c
> @@ -1282,6 +1282,7 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt)
> case V4L2_PIX_FMT_NV61: descr = "Y/CrCb 4:2:2"; break;
> case V4L2_PIX_FMT_NV24: descr = "Y/CbCr 4:4:4"; break;
> case V4L2_PIX_FMT_NV42: descr = "Y/CrCb 4:4:4"; break;
> + case V4L2_PIX_FMT_P010: descr = "10-bit Y/CrCb 4:2:0"; break;
> case V4L2_PIX_FMT_NV12M: descr = "Y/CbCr 4:2:0 (N-C)"; break;
> case V4L2_PIX_FMT_NV21M: descr = "Y/CrCb 4:2:0 (N-C)"; break;
> case V4L2_PIX_FMT_NV16M: descr = "Y/CbCr 4:2:2 (N-C)"; break;
> diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h
> index 9260791b8438..e5f7acde0730 100644
> --- a/include/uapi/linux/videodev2.h
> +++ b/include/uapi/linux/videodev2.h
> @@ -602,6 +602,7 @@ struct v4l2_pix_format {
> #define V4L2_PIX_FMT_NV24 v4l2_fourcc('N', 'V', '2', '4') /* 24 Y/CbCr 4:4:4 */
> #define V4L2_PIX_FMT_NV42 v4l2_fourcc('N', 'V', '4', '2') /* 24 Y/CrCb 4:4:4 */
> #define V4L2_PIX_FMT_HM12 v4l2_fourcc('H', 'M', '1', '2') /* 8 YUV 4:2:0 16x16 macroblocks */
> +#define V4L2_PIX_FMT_P010 v4l2_fourcc('P', '0', '1', '0') /* 15 Y/CbCr 4:2:0 10-bit per pixel*/
>
> /* two non contiguous planes - one Y, one Cr + Cb interleaved */
> #define V4L2_PIX_FMT_NV12M v4l2_fourcc('N', 'M', '1', '2') /* 12 Y/CbCr 4:2:0 */
^ permalink raw reply
* Re: [PATCH v6 1/5] mm: rmap: support batched checks of the references for large folios
From: Lorenzo Stoakes (Oracle) @ 2026-03-25 14:36 UTC (permalink / raw)
To: David Hildenbrand (Arm)
Cc: Baolin Wang, Barry Song, akpm, catalin.marinas, will,
lorenzo.stoakes, ryan.roberts, Liam.Howlett, vbabka, rppt, surenb,
mhocko, riel, harry.yoo, jannh, willy, dev.jain, linux-mm,
linux-arm-kernel, linux-kernel
In-Reply-To: <86f611cb-1292-44e4-b629-6503135d33ca@kernel.org>
On Mon, Mar 16, 2026 at 03:15:18PM +0100, David Hildenbrand (Arm) wrote:
> On 3/16/26 07:25, Baolin Wang wrote:
> >
> >
> > On 3/10/26 4:17 PM, David Hildenbrand (Arm) wrote:
> >> On 3/10/26 02:37, Baolin Wang wrote:
> >>>
> >>>
> >>>
> >>> I understand your point. I’m concerned that I can’t test this patch on
> >>> every architecture to validate the benefits. Anyway, let me try this on
> >>> my X86 machine first.
> >>
> >> In any case, please make that a follow-up patch :)
> >
> > Sure. However, after investigating RISC‑V and x86, I found that
> > ptep_clear_flush_young() does not flush the TLB on these architectures:
> >
> > int ptep_clear_flush_young(struct vm_area_struct *vma,
> > unsigned long address, pte_t *ptep)
> > {
> > /*
> > * On x86 CPUs, clearing the accessed bit without a TLB flush
> > * doesn't cause data corruption. [ It could cause incorrect
> > * page aging and the (mistaken) reclaim of hot pages, but the
> > * chance of that should be relatively low. ]
> > *
> > * So as a performance optimization don't flush the TLB when
> > * clearing the accessed bit, it will eventually be flushed by
> > * a context switch or a VM operation anyway. [ In the rare
> > * event of it not getting flushed for a long time the delay
> > * shouldn't really matter because there's no real memory
> > * pressure for swapout to react to. ]
> > */
> > return ptep_test_and_clear_young(vma, address, ptep);
> > }
>
> You'd probably want an arch helper then, that tells you whether
> a flush_tlb_range() after ptep_test_and_clear_young() is required.
>
> Or some special flush_tlb_range() helper.
>
> I agree that it requires more work.
Sorry unclear here - does the series need more work or does a follow up patch
need more work?
As this is in mm-stable afaict.
Thanks, Lorenzo
>
> --
> Cheers,
>
> David
^ permalink raw reply
* Re: [EXT] Re: [PATCH v4 3/4] clocksource/drivers/timer-mediatek: Convert timer-mediatek to a loadable module
From: Daniel Lezcano @ 2026-03-25 14:42 UTC (permalink / raw)
To: Zhipeng Wang
Cc: daniel.lezcano@linaro.org, tglx@kernel.org, shawnguo@kernel.org,
s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com,
matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com,
linux-kernel@vger.kernel.org, imx@lists.linux.dev,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, chun-hung.wu@mediatek.com,
walter.chang@mediatek.com, jstultz@google.com,
amergnat@baylibre.com, Aisheng Dong, Jindong Yue, Xuegang Liu,
Greg Kroah-Hartman
In-Reply-To: <AS8PR04MB84206959C00CFDC4C85B8BC2EB46A@AS8PR04MB8420.eurprd04.prod.outlook.com>
Hi Zhipeng,
On 3/10/26 09:41, Zhipeng Wang wrote:
>>
>>
>> Hi Zhipeng,
>>
>> On 3/9/26 06:31, Zhipeng Wang wrote:
>>> Hello Daniel,
>>>
>>> I'd be very happy to collaborate on this!
>>
>> Great, let me see if I can cook a patch in the next days
>>
>>> My availability: I can dedicate time to work on this over the next few weeks.
>> I'm happy to help with:
>>> - Testing the new macros with IMX timer drivers
>>> - Converting existing drivers as examples
>>> - Reviewing and testing patches
>>> - Documentation
>>
>> That's awesome, thanks
>>
>>> My understanding is that, based on your RFC, we should use two macros —
>> TIMER_OF_DECLARE_PDEV and TIMER_OF_DECLARE_PLATFORM_DRIVER.
>>
>> Yes, but also sort out the existing TIMER_OF_DECLARE macro vs MODULE in
>> order to prevent #ifdef MODULE in the drivers
>>
> Hi Daniel,
>
> Yes, that's our goal.
>
> I'll test the new macros (TIMER_OF_DECLARE_PLATFORM_DRIVER and
> TIMER_OF_DECLARE_EARLY_PLATFORM_DRIVER) with the IMX timer drivers
> once the patches are available.
I think I have an idea on how to achieve that. That will result in the
removal of TIMER_OF_DECLARE() when all drivers will be changed to use
the new macro.
The #ifdef MODULE macro is set when the driver is compiled as a module.
So we can do something like:
#ifdef MODULE
#define TIMER_OF_DECLARE_PDEV(name, compat, data, fn) \
OF_DECLARE_1_RET(timer_pdev, name, compat, data, fn)
#else
#define TIMER_OF_DECLARE_PDEV(__name, compat, data, fn) \
OF_DECLARE_1_RET(of_pdev_timer_match_table,
__name, compat, data, fn)
static struct platform_driver __##__name##_timer_driver = {
.probe = __##__name##_timer_probe,
.driver = {
.name = name,
.of_match_table = of_pdev_timer_match_table,
},
};
module_platform_driver(__##__name##_timer_driver);
#endif
So we deal with two tables, one for platform device non module and one
module for modules.
The first one is called by the timer-of init routine. The other one is
called by the probe function.
The drawback will be the match table will be common to all timer
drivers. So probe will be a bit slower. May be there is an area of
optimization here.
^ permalink raw reply
* Re: [PATCH net-next 2/2] net: phy: Introduce Airoha AN8801/R Gigabit Ethernet PHY driver
From: Louis-Alexis Eyraud @ 2026-03-25 14:44 UTC (permalink / raw)
To: Russell King (Oracle)
Cc: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
AngeloGioacchino Del Regno, Andrew Lunn, Heiner Kallweit,
kevin-kw.huang, macpaul.lin, matthias.bgg, kernel, netdev,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel
In-Reply-To: <aaheilkwpQ90xMmR@shell.armlinux.org.uk>
Hi Russell,
On Wed, 2026-03-04 at 16:32 +0000, Russell King (Oracle) wrote:
> On Wed, Mar 04, 2026 at 10:35:29AM +0100, Louis-Alexis Eyraud wrote:
> > +static void an8801r_get_wol(struct phy_device *phydev,
> > + struct ethtool_wolinfo *wol)
> > +{
> > + u32 reg_val;
> > +
> > + air_buckpbus_reg_read(phydev,
> > AN8801_BPBUS_REG_WAKEUP_CTL1, ®_val);
> > +
> > + wol->supported = WAKE_MAGIC;
> > +
> > + if (reg_val & AN8801_WOL_WAKE_MAGIC_EN)
> > + wol->wolopts |= WAKE_MAGIC;
> > + else
> > + wol->wolopts &= ~WAKE_MAGIC;
>
> Please only support WoL if you know that the PHY has been wired up in
> such a way to allow it to actually wake the system. The PHY itself
> merely supporting WoL is insufficient.
>
> Please look at my recent change to realtek_main.c in commit
> b826bf795564 ("net: phy: realtek: fix RTL8211F wake-on-lan support")
> to see a possible way to achieve this.
>
First, sorry for the delay, and thank you for pointing out this commit.
It indeed showed me what the WoL implementation for this PHY driver was
missing, not only for the get_wol/set_wol but also elsewhere in the
driver.
So for v2, I've reworked in a similar way the get_wol/set_wol, the
interrupt handling (to process differently the magic packet and the
link change interrupts) and also added custom probe, suspend and resume
callbacks (to be able to disable link change interrupt during suspend
time and enable it again after resume if the user has enabled the WoL
setting, like you did for RTL8211F).
I had a bit of trouble make it work right. At first I could not read
properly the PHY buckpbus registers in the suspend callback, and adding
a delay at resume time was needed as a workaround to make the WoL
behaviour work consistently. But in the end I found out it was the
Ethernet interface pinctrl config for sleep state in my board
devicetree that caused me those issues.
It works fine now without any workaround.
> > +static int an8801r_config_init(struct phy_device *phydev)
> > +{
> > + u8 led_default_function[AN8801R_NUM_LEDS] = { 0 };
> > + int prev_page, ret;
> > +
> > + ret = an8801r_of_init_leds(phydev, led_default_function);
> > + if (ret)
> > + return ret;
> > +
> > + /* Disable Low Power Mode (LPM) */
> > + ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
> > AN8801_REG_PHY_INTERNAL0,
> > + FIELD_PREP(AN8801_PHY_INTFUNC_MASK,
> > 0x1e));
> > + if (ret)
> > + return ret;
> > +
> > + ret = phy_write_mmd(phydev, MDIO_MMD_VEND2,
> > AN8801_REG_PHY_INTERNAL1,
> > + FIELD_PREP(AN8801_PHY_INTFUNC_MASK,
> > 0x2));
> > + if (ret)
> > + return ret;
> > +
> > + /* Disable EEE by default */
> > + ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
> > 0);
> > + if (ret)
> > + return ret;
>
> Are you sure this is safe, e.g. over a suspend/resume, and doesn't
> cause the hardware vs software state to desync?
While reworking PHY WoL support, I've tested removing this EEE
disabling done during driver initial config and I did not notice any
particular issue, especially during suspend/resume sequences. Still
unsure why the downstream driver disabled it in first place.
The EEE support seems working fine too from what ethtool reports on my
board, so I'll remove the lines from v2.
>
> > +
> > + prev_page = phy_select_page(phydev,
> > AIR_PHY_PAGE_EXTENDED_1);
> > + if (prev_page < 0)
> > + return prev_page;
>
> No, this is buggy. Please read the phy_select_page() documentation to
> find out why.
>
> > +
> > + /* Set the PHY to perform auto-downshift after 3 auto-
> > negotiation
> > + * attempts
> > + */
> > + __phy_write(phydev, AN8801_EXT_REG_PHY,
> > + FIELD_PREP(AN8801_EXT_PHY_CTRL1, 0x1d) |
> > + FIELD_PREP(AN8801_EXT_PHY_DOWNSHIFT_CTL, 1) |
> > + AN8801_EXT_PHY_DOWNSHIFT_EN);
> > +
> > + ret = phy_restore_page(phydev, prev_page, ret);
> > + if (ret)
> > + return ret;
>
> However, the bug could've been avoided by using the appropriate
> accessor:
>
> ret = phy_write_paged(phydev, AIR_PHY_PAGE_EXTENDED_1,
> AN8801_EXT_REG_PHY,
> FIELD_PREP(AN8801_EXT_PHY_CTRL1, 0x1d)
> |
>
> FIELD_PREP(AN8801_EXT_PHY_DOWNSHIFT_CTL, 1) |
> AN8801_EXT_PHY_DOWNSHIFT_EN);
> if (ret < 0)
> return ret;
thanks for catching this bug.
I've replaced for v2 the __phy_write call by phy_write_paged cas you
suggested.
> > +static int an8801r_read_status(struct phy_device *phydev)
> > +{
> > + int prev_speed, ret;
> > + u32 val;
> > +
> > + prev_speed = phydev->speed;
> > +
> > + ret = genphy_read_status(phydev);
> > + if (ret)
> > + return ret;
> > +
> > + if (!phydev->link)
> > + return 0;
> > +
> > + if (prev_speed != phydev->speed) {
>
> Maybe:
>
> if (phydev->link && prev_speed != phydev->speed) {
>
> ?
Ack.
Thanks again for the review.
Regards,
Louis-Alexis
>
> Thanks.
^ permalink raw reply
* [PATCH] arm: dts: mediatek: mt6589: Add Arm Generic Timer node
From: Akari Tsuyukusa @ 2026-03-25 14:45 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, matthias.bgg, angelogioacchino.delregno
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-mediatek,
Akari Tsuyukusa
Add the Arm Generic Timer node to the MT6589 SoC.
"arm,cpu-registers-not-fw-configured;" is required
because the bootloader does not initialize the Arm Generic Timer.
Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com>
---
arch/arm/boot/dts/mediatek/mt6589.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/mediatek/mt6589.dtsi b/arch/arm/boot/dts/mediatek/mt6589.dtsi
index c6babc8ad2ba..46dea445742b 100644
--- a/arch/arm/boot/dts/mediatek/mt6589.dtsi
+++ b/arch/arm/boot/dts/mediatek/mt6589.dtsi
@@ -42,6 +42,17 @@ cpu@3 {
};
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ clock-frequency = <13000000>;
+ arm,cpu-registers-not-fw-configured;
+ };
+
clocks {
#address-cells = <1>;
#size-cells = <1>;
--
2.53.0
^ permalink raw reply related
* Re: [PATCH v2 0/9] Enable display support for STM32MP257F-DK and STM32MP235F-DK
From: Alexandre TORGUE @ 2026-03-25 14:45 UTC (permalink / raw)
To: Raphael Gallais-Pou, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Maxime Coquelin, Christophe Roullier
Cc: Philippe Cornu, Yannick Fertre, Raphaël Gallais-Pou,
devicetree, linux-stm32, linux-arm-kernel, linux-kernel
In-Reply-To: <20260210-display-v2-0-0592bd514958@foss.st.com>
Hello Raph
On 2/10/26 11:03, Raphael Gallais-Pou wrote:
> This series aims to add and enable sufficient LVDS display support for
> STM32MP257F-DK and STM32MP235F-DK boards.
>
> Signed-off-by: Raphael Gallais-Pou <raphael.gallais-pou@foss.st.com>
> ---
> Changes in v2:
> - Added support for STM32MP235F-DK. A second series would have dependant
> to the v1 of this series due to the pinctrl. Better send it though
> one push to reduce dependencies.
> - Link to v1:
> https://lore.kernel.org/r/20260205-master-v1-0-fe6399aa3aab@foss.st.com/
>
> ---
> Raphael Gallais-Pou (9):
> arm64: dts: st: add i2c2 pins for stm32mp25
> arm64: dts: st: add ltdc support on stm32mp231
> arm64: dts: st: add ltdc support on stm32mp235
> arm64: dts: st: add lvds support on stm32mp235
> arm64: dts: st: add clock-cells to syscfg node on stm32mp231
> arm64: dts: st: describe power supplies for stm32mp235f-dk board
> arm64: dts: st: enable display support on stm32mp235f-dk board
> arm64: dts: st: describe power supplies for stm32mp257f-dk board
> arm64: dts: st: enable display support on stm32mp257f-dk board
>
> arch/arm64/boot/dts/st/stm32mp231.dtsi | 19 +++++
> arch/arm64/boot/dts/st/stm32mp235.dtsi | 18 ++++
> arch/arm64/boot/dts/st/stm32mp235f-dk.dts | 117 +++++++++++++++++++++++++
> arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 17 ++++
> arch/arm64/boot/dts/st/stm32mp257f-dk.dts | 118 ++++++++++++++++++++++++++
> 5 files changed, 289 insertions(+)
> ---
> base-commit: 05f7e89ab9731565d8a62e3b5d1ec206485eeb0b
> change-id: 20260209-display-516c2cedc734
>
> Best regards,
Series applied on stm32-next.
Thanks
Alex
^ permalink raw reply
* [PATCH v3 1/6] dt-bindings: arm: fsl: add Verdin iMX95
From: Ernest Van Hoecke @ 2026-03-25 14:46 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: Ernest Van Hoecke, Emanuele Ghidoli, Francesco Dolcini,
devicetree, linux-kernel, imx, linux-arm-kernel,
Krzysztof Kozlowski
In-Reply-To: <20260325-verdin-imx95-upstream-frank-li-base-v3-0-b2b5221a8077@toradex.com>
From: Ernest Van Hoecke <ernest.vanhoecke@toradex.com>
Add DT compatible strings for the Verdin i.MX95 SoM and its supported
carrier boards: the Verdin Development Board, and the Dahlia, Ivy,
Mallow and Yavia carrier boards.
Link: https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95
Link: https://www.toradex.com/products/carrier-board/verdin-development-board-kit
Link: https://www.toradex.com/products/carrier-board/dahlia-carrier-board-kit
Link: https://www.toradex.com/products/carrier-board/ivy-carrier-board
Link: https://www.toradex.com/products/carrier-board/mallow-carrier-board
Link: https://www.toradex.com/products/carrier-board/yavia
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Ernest Van Hoecke <ernest.vanhoecke@toradex.com>
---
v3: no changes
v2: Added Krzysztof's reviewed-by
v1: https://lore.kernel.org/all/20260305-verdin-imx95-upstream-frank-li-base-v1-1-823fad02def9@toradex.com/
---
Documentation/devicetree/bindings/arm/fsl.yaml | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index 5716d701292c..f0701143b237 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -1477,6 +1477,30 @@ properties:
- const: toradex,smarc-imx95 # Toradex SMARC iMX95 Module
- const: fsl,imx95
+ - description: Toradex Boards with Verdin iMX95 Modules
+ items:
+ - enum:
+ - toradex,verdin-imx95-nonwifi-dahlia # Verdin iMX95 Module on Dahlia
+ - toradex,verdin-imx95-nonwifi-dev # Verdin iMX95 Module on Verdin Development Board
+ - toradex,verdin-imx95-nonwifi-ivy # Verdin iMX95 Module on Ivy
+ - toradex,verdin-imx95-nonwifi-mallow # Verdin iMX95 Module on Mallow
+ - toradex,verdin-imx95-nonwifi-yavia # Verdin iMX95 Module on Yavia
+ - const: toradex,verdin-imx95-nonwifi # Verdin iMX95 Module without Wi-Fi / BT
+ - const: toradex,verdin-imx95 # Verdin iMX95 Module
+ - const: fsl,imx95
+
+ - description: Toradex Boards with Verdin iMX95 Wi-Fi / BT Modules
+ items:
+ - enum:
+ - toradex,verdin-imx95-wifi-dahlia # Verdin iMX95 Wi-Fi / BT Module on Dahlia
+ - toradex,verdin-imx95-wifi-dev # Verdin iMX95 Wi-Fi / BT Module on Verdin Development B.
+ - toradex,verdin-imx95-wifi-ivy # Verdin iMX95 Wi-Fi / BT Module on Ivy
+ - toradex,verdin-imx95-wifi-mallow # Verdin iMX95 Wi-Fi / BT Module on Mallow
+ - toradex,verdin-imx95-wifi-yavia # Verdin iMX95 Wi-Fi / BT Module on Yavia
+ - const: toradex,verdin-imx95-wifi # Verdin iMX95 Wi-Fi / BT Module
+ - const: toradex,verdin-imx95 # Verdin iMX95 Module
+ - const: fsl,imx95
+
- description: i.MXRT1050 based Boards
items:
- enum:
--
2.43.0
^ permalink raw reply related
* [PATCH v3 0/6] arm64: dts: freescale: add Verdin iMX95
From: Ernest Van Hoecke @ 2026-03-25 14:46 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: Ernest Van Hoecke, Emanuele Ghidoli, Francesco Dolcini,
devicetree, linux-kernel, imx, linux-arm-kernel,
Krzysztof Kozlowski
This patch series adds support for the Toradex Verdin i.MX95 SoM and its
currently available carrier boards: the Verdin Development Board, and
the Dahlia, Ivy, Mallow and Yavia carrier boards.
The module consists of an NXP i.MX95 family SoC, up to 16GB LPDDR4x RAM,
up to 128GB of storage, a USB 3.2 OTG and USB 2.0 Host, a Gigabit
Ethernet PHY, an I2C EEPROM and Temperature Sensor, an RX8130 RTC, an
I3C bus, one Quad lane CSI interface, one Quad lane DSI or CSI
interface, one LVDS interface (one or two channels), and some optional
addons: TPM 2.0, and a WiFi/BT module.
Link: https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95
Link: https://www.toradex.com/products/carrier-board/verdin-development-board-kit
Link: https://www.toradex.com/de/products/carrier-board/dahlia-carrier-board-kit
Link: https://www.toradex.com/products/carrier-board/ivy-carrier-board
Link: https://www.toradex.com/products/carrier-board/mallow-carrier-board
Link: https://www.toradex.com/products/carrier-board/yavia
---
Changes in v3:
- Rebased
- Link to v2: https://lore.kernel.org/r/20260313-verdin-imx95-upstream-frank-li-base-v2-0-bd488be7c699@toradex.com
Changes in v2:
- Fixed imx95-verdin.dtsi, imx95-verdin-dahlia.dtsi and imx95-verdin-ivy.dtsi node order
Link to v1: https://lore.kernel.org/r/20260305-verdin-imx95-upstream-frank-li-base-v1-0-823fad02def9@toradex.com
---
Ernest Van Hoecke (6):
dt-bindings: arm: fsl: add Verdin iMX95
arm64: dts: freescale: Add Verdin iMX95 support
arm64: dts: freescale: imx95-verdin: Add Dahlia carrier board
arm64: dts: freescale: imx95-verdin: Add Ivy carrier board
arm64: dts: freescale: imx95-verdin: Add Mallow carrier board
arm64: dts: freescale: imx95-verdin: Add Yavia carrier board
Documentation/devicetree/bindings/arm/fsl.yaml | 24 +
arch/arm64/boot/dts/freescale/Makefile | 10 +
.../boot/dts/freescale/imx95-verdin-dahlia.dtsi | 270 +++++
.../arm64/boot/dts/freescale/imx95-verdin-dev.dtsi | 250 +++++
.../arm64/boot/dts/freescale/imx95-verdin-ivy.dtsi | 515 +++++++++
.../boot/dts/freescale/imx95-verdin-mallow.dtsi | 223 ++++
.../dts/freescale/imx95-verdin-nonwifi-dahlia.dts | 21 +
.../dts/freescale/imx95-verdin-nonwifi-dev.dts | 21 +
.../dts/freescale/imx95-verdin-nonwifi-ivy.dts | 21 +
.../dts/freescale/imx95-verdin-nonwifi-mallow.dts | 21 +
.../dts/freescale/imx95-verdin-nonwifi-yavia.dts | 21 +
.../boot/dts/freescale/imx95-verdin-nonwifi.dtsi | 16 +
.../dts/freescale/imx95-verdin-wifi-dahlia.dts | 21 +
.../boot/dts/freescale/imx95-verdin-wifi-dev.dts | 21 +
.../boot/dts/freescale/imx95-verdin-wifi-ivy.dts | 21 +
.../dts/freescale/imx95-verdin-wifi-mallow.dts | 21 +
.../boot/dts/freescale/imx95-verdin-wifi-yavia.dts | 21 +
.../boot/dts/freescale/imx95-verdin-wifi.dtsi | 50 +
.../boot/dts/freescale/imx95-verdin-yavia.dtsi | 217 ++++
arch/arm64/boot/dts/freescale/imx95-verdin.dtsi | 1162 ++++++++++++++++++++
20 files changed, 2947 insertions(+)
---
base-commit: b4c2be6e5620c5054299aaf63e89412f08ab60d8
change-id: 20260305-verdin-imx95-upstream-frank-li-base-b57ab97c55c1
Best regards,
--
Ernest Van Hoecke <ernest.vanhoecke@toradex.com>
^ permalink raw reply
* [PATCH v3 3/6] arm64: dts: freescale: imx95-verdin: Add Dahlia carrier board
From: Ernest Van Hoecke @ 2026-03-25 14:46 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: Ernest Van Hoecke, Emanuele Ghidoli, Francesco Dolcini,
devicetree, linux-kernel, imx, linux-arm-kernel
In-Reply-To: <20260325-verdin-imx95-upstream-frank-li-base-v3-0-b2b5221a8077@toradex.com>
From: Ernest Van Hoecke <ernest.vanhoecke@toradex.com>
Add support for the Verdin i.MX95 mated with the Verdin Dahlia carrier
board.
Link: https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95
Link: https://www.toradex.com/products/carrier-board/dahlia-carrier-board-kit
Signed-off-by: Ernest Van Hoecke <ernest.vanhoecke@toradex.com>
---
v3: Rebased
v2: Reordered nodes alphanumerically by node name
v1: https://lore.kernel.org/all/20260305-verdin-imx95-upstream-frank-li-base-v1-3-823fad02def9@toradex.com/
---
arch/arm64/boot/dts/freescale/Makefile | 2 +
.../boot/dts/freescale/imx95-verdin-dahlia.dtsi | 270 +++++++++++++++++++++
.../dts/freescale/imx95-verdin-nonwifi-dahlia.dts | 21 ++
.../dts/freescale/imx95-verdin-wifi-dahlia.dts | 21 ++
4 files changed, 314 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index c46059cd2331..bcf54b4ed66c 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -497,7 +497,9 @@ dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk-sof.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-toradex-smarc-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-tqma9596sa-mb-smarc-2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-var-dart-sonata.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-dahlia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-dev.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-dahlia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-dev.dtb
imx95-15x15-evk-pcie0-ep-dtbs = imx95-15x15-evk.dtb imx-pcie0-ep.dtbo
diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-dahlia.dtsi b/arch/arm64/boot/dts/freescale/imx95-verdin-dahlia.dtsi
new file mode 100644
index 000000000000..889b71aa3de0
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx95-verdin-dahlia.dtsi
@@ -0,0 +1,270 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) Toradex
+ *
+ * Common dtsi for Verdin iMX95 SoM on Dahlia carrier board
+ *
+ * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95
+ * https://www.toradex.com/products/carrier-board/dahlia-carrier-board-kit
+ */
+
+/ {
+ aliases {
+ eeprom1 = &carrier_eeprom;
+ };
+
+ reg_1v8_sw: regulator-1v8-sw {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "On-carrier +V1.8_SW";
+ };
+
+ reg_pcie: regulator-pcie {
+ compatible = "regulator-fixed";
+ /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
+ gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-boot-on;
+ regulator-name = "PCIE_1_PWR_EN";
+ };
+
+ reg_usb_hub: regulator-usb-hub {
+ compatible = "regulator-fixed";
+ /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
+ gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-boot-on;
+ regulator-name = "HUB_PWR_EN";
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,bitclock-master = <&codec_dai>;
+ simple-audio-card,format = "i2s";
+ simple-audio-card,frame-master = <&codec_dai>;
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,name = "verdin-wm8904";
+ simple-audio-card,routing =
+ "Headphone Jack", "HPOUTL",
+ "Headphone Jack", "HPOUTR",
+ "IN2L", "Line In Jack",
+ "IN2R", "Line In Jack",
+ "Microphone Jack", "MICBIAS",
+ "IN1L", "Microphone Jack";
+ simple-audio-card,widgets =
+ "Microphone", "Microphone Jack",
+ "Headphone", "Headphone Jack",
+ "Line", "Line In Jack";
+
+ codec_dai: simple-audio-card,codec {
+ sound-dai = <&wm8904_1a>;
+ };
+
+ simple-audio-card,cpu {
+ sound-dai = <&sai3>;
+ };
+ };
+};
+
+/* Verdin ADC_1, ADC_2, ADC_3 and ADC_4 */
+&adc1 {
+ status = "okay";
+};
+
+/* Verdin ETH_1 (On-module PHY) */
+&enetc_port0 {
+ status = "okay";
+};
+
+/* Verdin CAN_1 */
+&flexcan1 {
+ status = "okay";
+};
+
+/* Verdin CAN_2 */
+&flexcan2 {
+ status = "okay";
+};
+
+/* Verdin QSPI_1 */
+&flexspi1 {
+ status = "okay";
+};
+
+&gpio1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
+};
+
+&gpio2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio1>,
+ <&pinctrl_gpio2>,
+ <&pinctrl_gpio3>;
+};
+
+&gpio3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio6>;
+};
+
+&gpio4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio5>;
+};
+
+&gpio5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio4>;
+};
+
+/* Verdin I2C_3_HDMI */
+&i3c2 {
+ status = "okay";
+};
+
+/* Verdin I2C_2_DSI */
+&lpi2c3 {
+ status = "okay";
+};
+
+/* Verdin I2C_1 */
+&lpi2c4 {
+ status = "okay";
+
+ wm8904_1a: audio-codec@1a {
+ compatible = "wlf,wm8904";
+ reg = <0x1a>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai3_mclk>;
+ clocks = <&scmi_clk IMX95_CLK_SAI3>;
+ clock-names = "mclk";
+ #sound-dai-cells = <0>;
+ AVDD-supply = <®_1v8_sw>;
+ CPVDD-supply = <®_1v8_sw>;
+ DBVDD-supply = <®_1v8_sw>;
+ DCVDD-supply = <®_1v8_sw>;
+ MICVDD-supply = <®_1v8_sw>;
+ };
+
+ /* Current measurement into module VCC */
+ hwmon@40 {
+ compatible = "ti,ina219";
+ reg = <0x40>;
+ shunt-resistor = <10000>;
+ };
+
+ temperature-sensor@4f {
+ compatible = "ti,tmp75c";
+ reg = <0x4f>;
+ };
+
+ carrier_eeprom: eeprom@57 {
+ compatible = "st,24c02", "atmel,24c02";
+ reg = <0x57>;
+ pagesize = <16>;
+ };
+};
+
+/* Verdin I2C_4_CSI */
+&lpi2c5 {
+ status = "okay";
+};
+
+/* Verdin UART_3, used as the Linux console */
+&lpuart1 {
+ status = "okay";
+};
+
+/* Verdin UART_4 */
+&lpuart2 {
+ status = "okay";
+};
+
+/* Verdin UART_1 */
+&lpuart7 {
+ status = "okay";
+};
+
+/* Verdin UART_2 */
+&lpuart8 {
+ status = "okay";
+};
+
+/* Verdin PCIE_1 */
+&pcie0 {
+ vpcie-supply = <®_pcie>;
+
+ status = "okay";
+};
+
+/* We support turning off sleep moci on Dahlia */
+®_force_sleep_moci {
+ status = "disabled";
+};
+
+/* Verdin I2S_1 */
+&sai3 {
+ status = "okay";
+};
+
+/* Verdin PWM_1 */
+&tpm4 {
+ status = "okay";
+};
+
+/* Verdin PWM_2 */
+&tpm5 {
+ status = "okay";
+};
+
+/* Verdin PWM_3_DSI */
+&tpm6 {
+ status = "okay";
+};
+
+/* Verdin USB_1 */
+&usb2 {
+ status = "okay";
+};
+
+/* Verdin USB_2 */
+&usb3 {
+ fsl,permanently-attached;
+
+ status = "okay";
+};
+
+&usb3_dwc3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb_hub_3_0: usb-hub@1 {
+ compatible = "usb424,5744";
+ reg = <1>;
+ peer-hub = <&usb_hub_2_0>;
+ vdd-supply = <®_usb_hub>;
+ };
+
+ usb_hub_2_0: usb-hub@2 {
+ compatible = "usb424,2744";
+ reg = <2>;
+ peer-hub = <&usb_hub_3_0>;
+ vdd-supply = <®_usb_hub>;
+ };
+};
+
+&usb3_phy {
+ status = "okay";
+};
+
+/* Verdin SD_1 */
+&usdhc2 {
+ status = "okay";
+};
+
+/* Verdin CTRL_WAKE1_MICO# */
+&verdin_gpio_keys {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-dahlia.dts b/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-dahlia.dts
new file mode 100644
index 000000000000..16975ae12fcb
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-dahlia.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) Toradex
+ *
+ * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95
+ * https://www.toradex.com/products/carrier-board/dahlia-carrier-board-kit
+ */
+
+/dts-v1/;
+
+#include "imx95-verdin.dtsi"
+#include "imx95-verdin-nonwifi.dtsi"
+#include "imx95-verdin-dahlia.dtsi"
+
+/ {
+ model = "Toradex Verdin iMX95 on Dahlia Board";
+ compatible = "toradex,verdin-imx95-nonwifi-dahlia",
+ "toradex,verdin-imx95-nonwifi",
+ "toradex,verdin-imx95",
+ "fsl,imx95";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-wifi-dahlia.dts b/arch/arm64/boot/dts/freescale/imx95-verdin-wifi-dahlia.dts
new file mode 100644
index 000000000000..bafbe1179ec8
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx95-verdin-wifi-dahlia.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) Toradex
+ *
+ * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95
+ * https://www.toradex.com/products/carrier-board/dahlia-carrier-board-kit
+ */
+
+/dts-v1/;
+
+#include "imx95-verdin.dtsi"
+#include "imx95-verdin-wifi.dtsi"
+#include "imx95-verdin-dahlia.dtsi"
+
+/ {
+ model = "Toradex Verdin iMX95 WB on Dahlia Board";
+ compatible = "toradex,verdin-imx95-wifi-dahlia",
+ "toradex,verdin-imx95-wifi",
+ "toradex,verdin-imx95",
+ "fsl,imx95";
+};
--
2.43.0
^ permalink raw reply related
* [PATCH v3 5/6] arm64: dts: freescale: imx95-verdin: Add Mallow carrier board
From: Ernest Van Hoecke @ 2026-03-25 14:46 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: Ernest Van Hoecke, Emanuele Ghidoli, Francesco Dolcini,
devicetree, linux-kernel, imx, linux-arm-kernel
In-Reply-To: <20260325-verdin-imx95-upstream-frank-li-base-v3-0-b2b5221a8077@toradex.com>
From: Ernest Van Hoecke <ernest.vanhoecke@toradex.com>
Add support for the Verdin i.MX95 SoM mated with the Mallow carrier
board.
Link: https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95
Link: https://www.toradex.com/products/carrier-board/mallow-carrier-board
Signed-off-by: Ernest Van Hoecke <ernest.vanhoecke@toradex.com>
---
v3: no changes
v2: no changes
v1: https://lore.kernel.org/all/20260305-verdin-imx95-upstream-frank-li-base-v1-5-823fad02def9@toradex.com/
---
arch/arm64/boot/dts/freescale/Makefile | 2 +
.../boot/dts/freescale/imx95-verdin-mallow.dtsi | 223 +++++++++++++++++++++
.../dts/freescale/imx95-verdin-nonwifi-mallow.dts | 21 ++
.../dts/freescale/imx95-verdin-wifi-mallow.dts | 21 ++
4 files changed, 267 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 4417b4a3d245..10417fc895de 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -500,9 +500,11 @@ dtb-$(CONFIG_ARCH_MXC) += imx95-var-dart-sonata.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-dahlia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-ivy.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-mallow.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-dahlia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-ivy.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-mallow.dtb
imx95-15x15-evk-pcie0-ep-dtbs = imx95-15x15-evk.dtb imx-pcie0-ep.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk-pcie0-ep.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-mallow.dtsi b/arch/arm64/boot/dts/freescale/imx95-verdin-mallow.dtsi
new file mode 100644
index 000000000000..53506b7550f5
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx95-verdin-mallow.dtsi
@@ -0,0 +1,223 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) Toradex
+ *
+ * Common dtsi for Verdin iMX95 SoM on Mallow carrier board
+ *
+ * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95
+ * https://www.toradex.com/products/carrier-board/mallow-carrier-board
+ */
+
+#include <dt-bindings/leds/common.h>
+
+/ {
+ aliases {
+ eeprom1 = &carrier_eeprom;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi1_clk_gpio>,
+ <&pinctrl_qspi1_cs_gpio>,
+ <&pinctrl_qspi1_io0_gpio>,
+ <&pinctrl_qspi1_io1_gpio>;
+
+ /* SODIMM 52 - USER_LED_1_RED */
+ led-0 {
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_DEBUG;
+ function-enumerator = <1>;
+ gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* SODIMM 54 - USER_LED_1_GREEN */
+ led-1 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_DEBUG;
+ function-enumerator = <1>;
+ gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* SODIMM 56 - USER_LED_2_RED */
+ led-2 {
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_DEBUG;
+ function-enumerator = <2>;
+ gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* SODIMM 58 - USER_LED_2_GREEN */
+ led-3 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_DEBUG;
+ function-enumerator = <2>;
+ gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+/* Verdin ADC_1, ADC_2, ADC_3 and ADC_4 */
+&adc1 {
+ status = "okay";
+};
+
+/* Verdin ETH_1 (On-module PHY) */
+&enetc_port0 {
+ status = "okay";
+};
+
+/* Verdin CAN_1 */
+&flexcan1 {
+ status = "okay";
+};
+
+/* Verdin CAN_2 */
+&flexcan2 {
+ status = "okay";
+};
+
+&gpio1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
+};
+
+&gpio2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio1>,
+ <&pinctrl_gpio2>,
+ <&pinctrl_gpio3>;
+};
+
+&gpio3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio6>;
+};
+
+&gpio4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio5>;
+};
+
+&gpio5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio4>;
+};
+
+/* Verdin I2C_3_HDMI */
+&i3c2 {
+ status = "okay";
+};
+
+/* Verdin I2C_2_DSI */
+&lpi2c3 {
+ status = "okay";
+};
+
+/* Verdin I2C_1 */
+&lpi2c4 {
+ status = "okay";
+
+ temperature-sensor@4f {
+ compatible = "ti,tmp1075";
+ reg = <0x4f>;
+ };
+
+ carrier_eeprom: eeprom@57 {
+ compatible = "st,24c02", "atmel,24c02";
+ reg = <0x57>;
+ pagesize = <16>;
+ };
+};
+
+/* Verdin I2C_4_CSI */
+&lpi2c5 {
+ status = "okay";
+};
+
+/* Verdin SPI_1 */
+&lpspi6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpspi6>,
+ <&pinctrl_spi1_cs>,
+ <&pinctrl_qspi1_cs2_gpio>;
+ cs-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>,
+ <&som_gpio_expander 13 GPIO_ACTIVE_LOW>,
+ <&gpio5 11 GPIO_ACTIVE_LOW>;
+
+ tpm@2 {
+ compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
+ reg = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi1_dqs_gpio>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
+ spi-max-frequency = <18500000>;
+ };
+};
+
+/* Verdin UART_3, used as the Linux console */
+&lpuart1 {
+ status = "okay";
+};
+
+/* Verdin UART_4 */
+&lpuart2 {
+ status = "okay";
+};
+
+/* Verdin UART_1 */
+&lpuart7 {
+ status = "okay";
+};
+
+/* Verdin UART_2 */
+&lpuart8 {
+ status = "okay";
+};
+
+/* Verdin PCIE_1 */
+&pcie0 {
+ status = "okay";
+};
+
+/* Verdin PWM_1 */
+&tpm4 {
+ status = "okay";
+};
+
+/* Verdin PWM_2 */
+&tpm5 {
+ status = "okay";
+};
+
+/* Verdin PWM_3_DSI */
+&tpm6 {
+ status = "okay";
+};
+
+/* Verdin USB_1 */
+&usb2 {
+ status = "okay";
+};
+
+/* Verdin USB_2 */
+&usb3 {
+ fsl,permanently-attached;
+
+ status = "okay";
+};
+
+&usb3_phy {
+ status = "okay";
+};
+
+/* Verdin SD_1 */
+&usdhc2 {
+ status = "okay";
+};
+
+/* Verdin CTRL_WAKE1_MICO# */
+&verdin_gpio_keys {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-mallow.dts b/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-mallow.dts
new file mode 100644
index 000000000000..5a9c0e4a79c9
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-mallow.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) Toradex
+ *
+ * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95
+ * https://www.toradex.com/products/carrier-board/mallow-carrier-board
+ */
+
+/dts-v1/;
+
+#include "imx95-verdin.dtsi"
+#include "imx95-verdin-nonwifi.dtsi"
+#include "imx95-verdin-mallow.dtsi"
+
+/ {
+ model = "Toradex Verdin iMX95 on Mallow Board";
+ compatible = "toradex,verdin-imx95-nonwifi-mallow",
+ "toradex,verdin-imx95-nonwifi",
+ "toradex,verdin-imx95",
+ "fsl,imx95";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-wifi-mallow.dts b/arch/arm64/boot/dts/freescale/imx95-verdin-wifi-mallow.dts
new file mode 100644
index 000000000000..eaa67a39be1c
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx95-verdin-wifi-mallow.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) Toradex
+ *
+ * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95
+ * https://www.toradex.com/products/carrier-board/mallow-carrier-board
+ */
+
+/dts-v1/;
+
+#include "imx95-verdin.dtsi"
+#include "imx95-verdin-wifi.dtsi"
+#include "imx95-verdin-mallow.dtsi"
+
+/ {
+ model = "Toradex Verdin iMX95 WB on Mallow Board";
+ compatible = "toradex,verdin-imx95-wifi-mallow",
+ "toradex,verdin-imx95-wifi",
+ "toradex,verdin-imx95",
+ "fsl,imx95";
+};
--
2.43.0
^ permalink raw reply related
* [PATCH v3 6/6] arm64: dts: freescale: imx95-verdin: Add Yavia carrier board
From: Ernest Van Hoecke @ 2026-03-25 14:46 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: Ernest Van Hoecke, Emanuele Ghidoli, Francesco Dolcini,
devicetree, linux-kernel, imx, linux-arm-kernel
In-Reply-To: <20260325-verdin-imx95-upstream-frank-li-base-v3-0-b2b5221a8077@toradex.com>
From: Ernest Van Hoecke <ernest.vanhoecke@toradex.com>
Add support for the Verdin i.MX95 SoM mated with the Yavia carrier
board.
Link: https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95
Link: https://www.toradex.com/products/carrier-board/yavia
Signed-off-by: Ernest Van Hoecke <ernest.vanhoecke@toradex.com>
---
v3: no changes
v2: no changes
v1: https://lore.kernel.org/all/20260305-verdin-imx95-upstream-frank-li-base-v1-6-823fad02def9@toradex.com/
---
arch/arm64/boot/dts/freescale/Makefile | 2 +
.../dts/freescale/imx95-verdin-nonwifi-yavia.dts | 21 ++
.../boot/dts/freescale/imx95-verdin-wifi-yavia.dts | 21 ++
.../boot/dts/freescale/imx95-verdin-yavia.dtsi | 217 +++++++++++++++++++++
4 files changed, 261 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 10417fc895de..5bee7c83a724 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -501,10 +501,12 @@ dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-dahlia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-ivy.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-mallow.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-yavia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-dahlia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-ivy.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-mallow.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-yavia.dtb
imx95-15x15-evk-pcie0-ep-dtbs = imx95-15x15-evk.dtb imx-pcie0-ep.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk-pcie0-ep.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-yavia.dts b/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-yavia.dts
new file mode 100644
index 000000000000..4f7b4e3a518b
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-yavia.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) Toradex
+ *
+ * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95
+ * https://www.toradex.com/products/carrier-board/yavia
+ */
+
+/dts-v1/;
+
+#include "imx95-verdin.dtsi"
+#include "imx95-verdin-nonwifi.dtsi"
+#include "imx95-verdin-yavia.dtsi"
+
+/ {
+ model = "Toradex Verdin iMX95 on Yavia Board";
+ compatible = "toradex,verdin-imx95-nonwifi-yavia",
+ "toradex,verdin-imx95-nonwifi",
+ "toradex,verdin-imx95",
+ "fsl,imx95";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-wifi-yavia.dts b/arch/arm64/boot/dts/freescale/imx95-verdin-wifi-yavia.dts
new file mode 100644
index 000000000000..43d35b770db2
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx95-verdin-wifi-yavia.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) Toradex
+ *
+ * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95
+ * https://www.toradex.com/products/carrier-board/yavia
+ */
+
+/dts-v1/;
+
+#include "imx95-verdin.dtsi"
+#include "imx95-verdin-wifi.dtsi"
+#include "imx95-verdin-yavia.dtsi"
+
+/ {
+ model = "Toradex Verdin iMX95 WB on Yavia Board";
+ compatible = "toradex,verdin-imx95-wifi-yavia",
+ "toradex,verdin-imx95-wifi",
+ "toradex,verdin-imx95",
+ "fsl,imx95";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-yavia.dtsi b/arch/arm64/boot/dts/freescale/imx95-verdin-yavia.dtsi
new file mode 100644
index 000000000000..6403ae584e70
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx95-verdin-yavia.dtsi
@@ -0,0 +1,217 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) Toradex
+ *
+ * Common dtsi for Verdin iMX95 SoM on Yavia carrier board
+ *
+ * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95
+ * https://www.toradex.com/products/carrier-board/yavia
+ */
+
+#include <dt-bindings/leds/common.h>
+
+/ {
+ aliases {
+ eeprom1 = &carrier_eeprom;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi1_clk_gpio>,
+ <&pinctrl_qspi1_cs_gpio>,
+ <&pinctrl_qspi1_io0_gpio>,
+ <&pinctrl_qspi1_io1_gpio>,
+ <&pinctrl_qspi1_io2_gpio>,
+ <&pinctrl_qspi1_io3_gpio>;
+
+ /* SODIMM 52 - LD1_RED */
+ led-0 {
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_DEBUG;
+ function-enumerator = <1>;
+ gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
+ };
+ /* SODIMM 54 - LD1_GREEN */
+ led-1 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_DEBUG;
+ function-enumerator = <1>;
+ gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>;
+ };
+ /* SODIMM 56 - LD1_BLUE */
+ led-2 {
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_DEBUG;
+ function-enumerator = <1>;
+ gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>;
+ };
+ /* SODIMM 58 - LD2_RED */
+ led-3 {
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_DEBUG;
+ function-enumerator = <2>;
+ gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+ };
+ /* SODIMM 60 - LD2_GREEN */
+ led-4 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_DEBUG;
+ function-enumerator = <2>;
+ gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
+ };
+ /* SODIMM 62 - LD2_BLUE */
+ led-5 {
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_DEBUG;
+ function-enumerator = <2>;
+ gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
+ };
+ };
+};
+
+/* Verdin ADC_1, ADC_2, ADC_3 and ADC_4 */
+&adc1 {
+ status = "okay";
+};
+
+/* Verdin ETH_1 (On-module PHY) */
+&enetc_port0 {
+ status = "okay";
+};
+
+/* Verdin CAN_1 */
+&flexcan1 {
+ status = "okay";
+};
+
+/* Verdin CAN_2 */
+&flexcan2 {
+ status = "okay";
+};
+
+&gpio1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
+};
+
+&gpio2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio1>,
+ <&pinctrl_gpio2>,
+ <&pinctrl_gpio3>;
+};
+
+&gpio3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio6>;
+};
+
+&gpio4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio5>;
+};
+
+&gpio5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio4>,
+ <&pinctrl_qspi1_cs2_gpio>,
+ <&pinctrl_qspi1_dqs_gpio>;
+};
+
+/* Verdin I2C_3_HDMI */
+&i3c2 {
+ status = "okay";
+};
+
+/* Verdin I2C_2_DSI */
+&lpi2c3 {
+ status = "okay";
+};
+
+/* Verdin I2C_1 */
+&lpi2c4 {
+ status = "okay";
+
+ temperature-sensor@4f {
+ compatible = "ti,tmp75c";
+ reg = <0x4f>;
+ };
+
+ carrier_eeprom: eeprom@57 {
+ compatible = "st,24c02", "atmel,24c02";
+ reg = <0x57>;
+ pagesize = <16>;
+ };
+};
+
+/* Verdin I2C_4_CSI */
+&lpi2c5 {
+ status = "okay";
+};
+
+/* Verdin UART_3, used as the Linux console */
+&lpuart1 {
+ status = "okay";
+};
+
+/* Verdin UART_4 */
+&lpuart2 {
+ status = "okay";
+};
+
+/* Verdin UART_1 */
+&lpuart7 {
+ status = "okay";
+};
+
+/* Verdin UART_2 */
+&lpuart8 {
+ status = "okay";
+};
+
+/* Verdin PCIE_1 */
+&pcie0 {
+ status = "okay";
+};
+
+/* Verdin PWM_1 */
+&tpm4 {
+ status = "okay";
+};
+
+/* Verdin PWM_2 */
+&tpm5 {
+ status = "okay";
+};
+
+/* Verdin PWM_3_DSI */
+&tpm6 {
+ status = "okay";
+};
+
+/* Verdin USB_1 */
+&usb2 {
+ status = "okay";
+};
+
+/* Verdin USB_2 */
+&usb3 {
+ fsl,permanently-attached;
+
+ status = "okay";
+};
+
+&usb3_phy {
+ status = "okay";
+};
+
+/* Verdin SD_1 */
+&usdhc2 {
+ status = "okay";
+};
+
+/* Verdin CTRL_WAKE1_MICO# */
+&verdin_gpio_keys {
+ status = "okay";
+};
--
2.43.0
^ permalink raw reply related
* [PATCH v3 4/6] arm64: dts: freescale: imx95-verdin: Add Ivy carrier board
From: Ernest Van Hoecke @ 2026-03-25 14:46 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: Ernest Van Hoecke, Emanuele Ghidoli, Francesco Dolcini,
devicetree, linux-kernel, imx, linux-arm-kernel
In-Reply-To: <20260325-verdin-imx95-upstream-frank-li-base-v3-0-b2b5221a8077@toradex.com>
From: Ernest Van Hoecke <ernest.vanhoecke@toradex.com>
Add support for the Verdin i.MX95 SoM mated with the Ivy carrier board.
Link: https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95
Link: https://www.toradex.com/products/carrier-board/ivy-carrier-board
Signed-off-by: Ernest Van Hoecke <ernest.vanhoecke@toradex.com>
---
v3: no changes
v2: Reordered nodes alphanumerically by node name
v1: https://lore.kernel.org/all/20260305-verdin-imx95-upstream-frank-li-base-v1-4-823fad02def9@toradex.com/
---
arch/arm64/boot/dts/freescale/Makefile | 2 +
.../arm64/boot/dts/freescale/imx95-verdin-ivy.dtsi | 515 +++++++++++++++++++++
.../dts/freescale/imx95-verdin-nonwifi-ivy.dts | 21 +
.../boot/dts/freescale/imx95-verdin-wifi-ivy.dts | 21 +
4 files changed, 559 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index bcf54b4ed66c..4417b4a3d245 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -499,8 +499,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx95-tqma9596sa-mb-smarc-2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-var-dart-sonata.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-dahlia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-dev.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-ivy.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-dahlia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-dev.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-ivy.dtb
imx95-15x15-evk-pcie0-ep-dtbs = imx95-15x15-evk.dtb imx-pcie0-ep.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk-pcie0-ep.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-ivy.dtsi b/arch/arm64/boot/dts/freescale/imx95-verdin-ivy.dtsi
new file mode 100644
index 000000000000..8337c8b25f05
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx95-verdin-ivy.dtsi
@@ -0,0 +1,515 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) Toradex
+ *
+ * Common dtsi for Verdin iMX95 SoM on Ivy carrier board
+ *
+ * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95
+ * https://www.toradex.com/products/carrier-board/ivy-carrier-board
+ */
+
+#include <dt-bindings/mux/mux.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/net/ti-dp83867.h>
+
+/ {
+ aliases {
+ eeprom1 = &carrier_eeprom;
+ };
+
+ ain1-current {
+ compatible = "io-channel-mux";
+ channels = "", "ain1_current";
+ io-channels = <&ain1_current_unmanaged>;
+ io-channel-names = "parent";
+ mux-controls = <&ain1_mode_mux_ctrl>;
+ settle-time-us = <1000>;
+ };
+
+ ain1-voltage {
+ compatible = "io-channel-mux";
+ channels = "ain1_voltage", "";
+ io-channels = <&ain1_voltage_unmanaged 0>;
+ io-channel-names = "parent";
+ mux-controls = <&ain1_mode_mux_ctrl>;
+ settle-time-us = <1000>;
+ };
+
+ ain2-current {
+ compatible = "io-channel-mux";
+ channels = "", "ain2_current";
+ io-channels = <&ain2_current_unmanaged>;
+ io-channel-names = "parent";
+ mux-controls = <&ain2_mode_mux_ctrl>;
+ settle-time-us = <1000>;
+ };
+
+ ain2-voltage {
+ compatible = "io-channel-mux";
+ channels = "ain2_voltage", "";
+ io-channels = <&ain2_voltage_unmanaged 0>;
+ io-channel-names = "parent";
+ mux-controls = <&ain2_mode_mux_ctrl>;
+ settle-time-us = <1000>;
+ };
+
+ /* AIN1 Current w/o AIN1_MODE gpio control */
+ ain1_current_unmanaged: current-sense-shunt-ain1 {
+ compatible = "current-sense-shunt";
+ #io-channel-cells = <0>;
+ io-channels = <&ivy_adc1 1>;
+ shunt-resistor-micro-ohms = <100000000>;
+ };
+
+ /* AIN2 Current w/o AIN2_MODE gpio control */
+ ain2_current_unmanaged: current-sense-shunt-ain2 {
+ compatible = "current-sense-shunt";
+ #io-channel-cells = <0>;
+ io-channels = <&ivy_adc2 1>;
+ shunt-resistor-micro-ohms = <100000000>;
+ };
+
+ /* Ivy Power Supply Input Voltage */
+ ivy-1v8-voltage {
+ compatible = "voltage-divider";
+ /* Verdin ADC_4 */
+ io-channels = <&adc1 3>;
+ full-ohms = <39000>; /* 12k + 27k */
+ output-ohms = <27000>;
+ };
+
+ ivy-3v3-voltage {
+ compatible = "voltage-divider";
+ /* Verdin ADC_3 */
+ io-channels = <&adc1 2>;
+ full-ohms = <54000>; /* 27k + 27k */
+ output-ohms = <27000>;
+ };
+
+ ivy-5v-voltage {
+ compatible = "voltage-divider";
+ /* Verdin ADC_2 */
+ io-channels = <&adc1 1>;
+ full-ohms = <39000>; /* 27k + 12k */
+ output-ohms = <12000>;
+ };
+
+ ivy-input-voltage {
+ compatible = "voltage-divider";
+ /* Verdin ADC_1 */
+ io-channels = <&adc1 0>;
+ full-ohms = <204700>; /* 200k + 4.7k */
+ output-ohms = <4700>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ivy_leds>;
+
+ /* D7 Blue - SODIMM 30 - LEDs.GPIO1 */
+ led-0 {
+ color = <LED_COLOR_ID_BLUE>;
+ default-state = "off";
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <1>;
+ gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* D7 Green - SODIMM 32 - LEDs.GPIO2 */
+ led-1 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <1>;
+ gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* D7 Red - SODIMM 34 - LEDs.GPIO3 */
+ led-2 {
+ color = <LED_COLOR_ID_RED>;
+ default-state = "off";
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <1>;
+ gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* D8 Blue - SODIMM 36 - LEDs.GPIO4 */
+ led-3 {
+ color = <LED_COLOR_ID_BLUE>;
+ default-state = "off";
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <2>;
+ gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* D8 Green - SODIMM 54 - LEDs.GPIO5 */
+ led-4 {
+ color = <LED_COLOR_ID_GREEN>;
+ default-state = "off";
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <2>;
+ gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* D8 Red - SODIMM 44 - LEDs.GPIO6 */
+ led-5 {
+ color = <LED_COLOR_ID_RED>;
+ default-state = "off";
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <2>;
+ gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* D9 Blue - SODIMM 46 - LEDs.GPIO7 */
+ led-6 {
+ color = <LED_COLOR_ID_BLUE>;
+ default-state = "off";
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <3>;
+ gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* D9 Red - SODIMM 48 - LEDs.GPIO8 */
+ led-7 {
+ color = <LED_COLOR_ID_RED>;
+ default-state = "off";
+ function = LED_FUNCTION_STATUS;
+ function-enumerator = <3>;
+ gpios = <&gpio5 7 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ /* AIN1_MODE - SODIMM 216 */
+ ain1_mode_mux_ctrl: mux-controller-0 {
+ compatible = "gpio-mux";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio5>;
+ #mux-control-cells = <0>;
+ mux-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
+ };
+
+ /* AIN2_MODE - SODIMM 218 */
+ ain2_mode_mux_ctrl: mux-controller-1 {
+ compatible = "gpio-mux";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio6>;
+ #mux-control-cells = <0>;
+ mux-gpios = <&gpio3 27 GPIO_ACTIVE_HIGH>;
+ };
+
+ reg_3v2_ain1: regulator-3v2-ain1 {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <3200000>;
+ regulator-min-microvolt = <3200000>;
+ regulator-name = "+3V2_AIN1";
+ };
+
+ reg_3v2_ain2: regulator-3v2-ain2 {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <3200000>;
+ regulator-min-microvolt = <3200000>;
+ regulator-name = "+3V2_AIN2";
+ };
+
+ /* AIN1 Voltage w/o AIN1_MODE gpio control */
+ ain1_voltage_unmanaged: voltage-divider-ain1 {
+ compatible = "voltage-divider";
+ #io-channel-cells = <1>;
+ io-channels = <&ivy_adc1 0>;
+ full-ohms = <19>;
+ output-ohms = <1>;
+ };
+
+ /* AIN2 Voltage w/o AIN2_MODE gpio control */
+ ain2_voltage_unmanaged: voltage-divider-ain2 {
+ compatible = "voltage-divider";
+ #io-channel-cells = <1>;
+ io-channels = <&ivy_adc2 0>;
+ full-ohms = <19>;
+ output-ohms = <1>;
+ };
+};
+
+/* Verdin ADC_1, ADC_2, ADC_3 and ADC_4 */
+&adc1 {
+ status = "okay";
+};
+
+/* Verdin ETH_1 (On-module PHY) */
+&enetc_port0 {
+ status = "okay";
+};
+
+/* Verdin ETH_2_RGMII */
+&enetc_port1 {
+ phy-handle = <ðphy2>;
+ phy-mode = "rgmii-id";
+
+ status = "okay";
+};
+
+/* Verdin CAN_1 */
+&flexcan1 {
+ status = "okay";
+};
+
+/* Verdin CAN_2 */
+&flexcan2 {
+ status = "okay";
+};
+
+&gpio1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
+ gpio-line-names = "";
+};
+
+&gpio2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio2>,
+ <&pinctrl_gpio3>;
+ gpio-line-names =
+ "", /* 0 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "", /* 10 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "GPIO2", /* Verdin GPIO_2 - SODIMM 208 */
+ "",
+ "", /* 20 */
+ "",
+ "",
+ "",
+ "GPIO3", /* Verdin GPIO_3 - SODIMM 210 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "", /* 30 */
+ "";
+};
+
+&gpio3 {
+ gpio-line-names = "";
+};
+
+&gpio4 {
+ gpio-line-names = "";
+};
+
+&gpio5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi1_cs2_gpio>,
+ <&pinctrl_qspi1_dqs_gpio>,
+ <&pinctrl_qspi1_io0_gpio>,
+ <&pinctrl_qspi1_io1_gpio>,
+ <&pinctrl_qspi1_io2_gpio>,
+ <&pinctrl_qspi1_io3_gpio>;
+ gpio-line-names =
+ "DIGI_1", /* SODIMM 56 */
+ "DIGI_2", /* SODIMM 58 */
+ "REL1", /* SODIMM 60 */
+ "REL2", /* SODIMM 62 */
+ "",
+ "",
+ "",
+ "",
+ "REL4", /* SODIMM 66 */
+ "",
+ "", /* 10 */
+ "REL3", /* SODIMM 64 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "";
+};
+
+/* Verdin I2C_1 */
+&lpi2c4 {
+ status = "okay";
+
+ temperature-sensor@4f {
+ compatible = "ti,tmp1075";
+ reg = <0x4f>;
+ };
+
+ carrier_eeprom: eeprom@57 {
+ compatible = "st,24c02", "atmel,24c02";
+ reg = <0x57>;
+ pagesize = <16>;
+ };
+};
+
+/* Verdin I2C_4_CSI */
+&lpi2c5 {
+ status = "okay";
+
+ ivy_adc1: adc@40 {
+ compatible = "ti,ads1119";
+ reg = <0x40>;
+ interrupt-parent = <&som_gpio_expander>;
+ interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
+ avdd-supply = <®_3v2_ain1>;
+ dvdd-supply = <®_3v2_ain1>;
+ vref-supply = <®_3v2_ain1>;
+ #address-cells = <1>;
+ #io-channel-cells = <1>;
+ #size-cells = <0>;
+
+ /* AIN1 0-33V Voltage Input */
+ channel@0 {
+ reg = <0>;
+ diff-channels = <0 1>;
+ };
+
+ /* AIN1 0-20mA Current Input */
+ channel@1 {
+ reg = <1>;
+ diff-channels = <2 3>;
+ };
+ };
+
+ ivy_adc2: adc@41 {
+ compatible = "ti,ads1119";
+ reg = <0x41>;
+ interrupt-parent = <&som_gpio_expander>;
+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+ avdd-supply = <®_3v2_ain2>;
+ dvdd-supply = <®_3v2_ain2>;
+ vref-supply = <®_3v2_ain2>;
+ #address-cells = <1>;
+ #io-channel-cells = <1>;
+ #size-cells = <0>;
+
+ /* AIN2 0-33V Voltage Input */
+ channel@0 {
+ reg = <0>;
+ diff-channels = <0 1>;
+ };
+
+ /* AIN2 0-20mA Current Input */
+ channel@1 {
+ reg = <1>;
+ diff-channels = <2 3>;
+ };
+ };
+};
+
+/* Verdin SPI_1 */
+&lpspi6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpspi6>,
+ <&pinctrl_spi1_cs>,
+ <&pinctrl_gpio1>,
+ <&pinctrl_gpio4>;
+ cs-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>,
+ <&som_gpio_expander 13 GPIO_ACTIVE_LOW>,
+ <&gpio2 0 GPIO_ACTIVE_LOW>,
+ <&gpio5 12 GPIO_ACTIVE_LOW>;
+
+ tpm@2 {
+ compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
+ reg = <2>;
+ spi-max-frequency = <18500000>;
+ };
+
+ fram@3 {
+ compatible = "fujitsu,mb85rs256", "atmel,at25";
+ reg = <3>;
+ address-width = <16>;
+ size = <32768>;
+ spi-max-frequency = <33000000>;
+ pagesize = <1>;
+ };
+};
+
+/* Verdin UART_3, used as the Linux console */
+&lpuart1 {
+ status = "okay";
+};
+
+/* Verdin UART_1 */
+&lpuart7 {
+ status = "okay";
+};
+
+/* Verdin UART_2, through RS485 transceiver */
+&lpuart8 {
+ rs485-rts-active-low;
+ rs485-rx-during-tx;
+ linux,rs485-enabled-at-boot-time;
+
+ status = "okay";
+};
+
+&netc_emdio {
+ ethphy2: ethernet-phy@2 {
+ reg = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eth2_rgmii_int>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ };
+};
+
+/* Verdin PCIE_1 */
+&pcie0 {
+ status = "okay";
+};
+
+&som_gpio_expander {
+ gpio-line-names = "";
+};
+
+/* Verdin USB_1 */
+&usb2 {
+ status = "okay";
+};
+
+/* Verdin USB_2 */
+&usb3 {
+ fsl,permanently-attached;
+
+ status = "okay";
+};
+
+&usb3_phy {
+ status = "okay";
+};
+
+/* Verdin SD_1 */
+&usdhc2 {
+ status = "okay";
+};
+
+&scmi_iomuxc {
+ pinctrl_ivy_leds: ivyledsgrp {
+ fsl,pins = <IMX95_PAD_GPIO_IO16__GPIO2_IO_BIT16 0x11e>, /* SODIMM 30 */
+ <IMX95_PAD_GPIO_IO26__GPIO2_IO_BIT26 0x11e>, /* SODIMM 32 */
+ <IMX95_PAD_GPIO_IO21__GPIO2_IO_BIT21 0x11e>, /* SODIMM 34 */
+ <IMX95_PAD_GPIO_IO20__GPIO2_IO_BIT20 0x11e>, /* SODIMM 36 */
+ <IMX95_PAD_XSPI1_DATA5__GPIO5_IO_BIT5 0x11e>, /* SODIMM 44 */
+ <IMX95_PAD_XSPI1_DATA4__GPIO5_IO_BIT4 0x11e>, /* SODIMM 46 */
+ <IMX95_PAD_XSPI1_DATA7__GPIO5_IO_BIT7 0x11e>, /* SODIMM 48 */
+ <IMX95_PAD_XSPI1_SS0_B__GPIO5_IO_BIT10 0x11e>; /* SODIMM 54 */
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-ivy.dts b/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-ivy.dts
new file mode 100644
index 000000000000..ebe1aec1ffa4
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-ivy.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) Toradex
+ *
+ * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95
+ * https://www.toradex.com/products/carrier-board/ivy-carrier-board
+ */
+
+/dts-v1/;
+
+#include "imx95-verdin.dtsi"
+#include "imx95-verdin-nonwifi.dtsi"
+#include "imx95-verdin-ivy.dtsi"
+
+/ {
+ model = "Toradex Verdin iMX95 on Ivy Board";
+ compatible = "toradex,verdin-imx95-nonwifi-ivy",
+ "toradex,verdin-imx95-nonwifi",
+ "toradex,verdin-imx95",
+ "fsl,imx95";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-wifi-ivy.dts b/arch/arm64/boot/dts/freescale/imx95-verdin-wifi-ivy.dts
new file mode 100644
index 000000000000..7ff2d03a254d
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx95-verdin-wifi-ivy.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) Toradex
+ *
+ * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95
+ * https://www.toradex.com/products/carrier-board/ivy-carrier-board
+ */
+
+/dts-v1/;
+
+#include "imx95-verdin.dtsi"
+#include "imx95-verdin-wifi.dtsi"
+#include "imx95-verdin-ivy.dtsi"
+
+/ {
+ model = "Toradex Verdin iMX95 WB on Ivy Board";
+ compatible = "toradex,verdin-imx95-wifi-ivy",
+ "toradex,verdin-imx95-wifi",
+ "toradex,verdin-imx95",
+ "fsl,imx95";
+};
--
2.43.0
^ permalink raw reply related
* [PATCH v3 2/6] arm64: dts: freescale: Add Verdin iMX95 support
From: Ernest Van Hoecke @ 2026-03-25 14:46 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: Ernest Van Hoecke, Emanuele Ghidoli, Francesco Dolcini,
devicetree, linux-kernel, imx, linux-arm-kernel
In-Reply-To: <20260325-verdin-imx95-upstream-frank-li-base-v3-0-b2b5221a8077@toradex.com>
From: Ernest Van Hoecke <ernest.vanhoecke@toradex.com>
Add support for the Toradex Verdin iMX95 and its development carrier
board.
The module consists of an NXP i.MX95 family SoC, up to 16GB LPDDR4x RAM,
up to 128GB of storage, a USB 3.2 OTG and USB 2.0 Host, a Gigabit
Ethernet PHY, an I2C EEPROM and Temperature Sensor, an RX8130 RTC, an
I3C bus, one Quad lane CSI interface, one Quad lane DSI or CSI
interface, one LVDS interface (one or two channels), and some optional
addons: TPM 2.0, and a WiFi/BT module.
Link: https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95
Link: https://www.toradex.com/products/carrier-board/verdin-development-board-kit
Co-developed-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
Co-developed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Signed-off-by: Ernest Van Hoecke <ernest.vanhoecke@toradex.com>
---
v3: Rebased
v2: Reordered nodes alphanumerically by node name
v1: https://lore.kernel.org/all/20260305-verdin-imx95-upstream-frank-li-base-v1-2-823fad02def9@toradex.com/
---
arch/arm64/boot/dts/freescale/Makefile | 2 +
.../arm64/boot/dts/freescale/imx95-verdin-dev.dtsi | 250 +++++
.../dts/freescale/imx95-verdin-nonwifi-dev.dts | 21 +
.../boot/dts/freescale/imx95-verdin-nonwifi.dtsi | 16 +
.../boot/dts/freescale/imx95-verdin-wifi-dev.dts | 21 +
.../boot/dts/freescale/imx95-verdin-wifi.dtsi | 50 +
arch/arm64/boot/dts/freescale/imx95-verdin.dtsi | 1162 ++++++++++++++++++++
7 files changed, 1522 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 2da6dc4f8a14..c46059cd2331 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -497,6 +497,8 @@ dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk-sof.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-toradex-smarc-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-tqma9596sa-mb-smarc-2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-var-dart-sonata.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-nonwifi-dev.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx95-verdin-wifi-dev.dtb
imx95-15x15-evk-pcie0-ep-dtbs = imx95-15x15-evk.dtb imx-pcie0-ep.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx95-15x15-evk-pcie0-ep.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-dev.dtsi b/arch/arm64/boot/dts/freescale/imx95-verdin-dev.dtsi
new file mode 100644
index 000000000000..2848f9adf152
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx95-verdin-dev.dtsi
@@ -0,0 +1,250 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) Toradex
+ *
+ * Common dtsi for Verdin iMX95 SoM on development carrier board
+ *
+ * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95
+ * https://www.toradex.com/products/carrier-board/verdin-development-board-kit
+ */
+
+/ {
+ aliases {
+ eeprom1 = &carrier_eeprom;
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,bitclock-master = <&codec_dai>;
+ simple-audio-card,format = "i2s";
+ simple-audio-card,frame-master = <&codec_dai>;
+ simple-audio-card,mclk-fs = <256>;
+ simple-audio-card,name = "verdin-nau8822";
+ simple-audio-card,routing =
+ "Headphones", "LHP",
+ "Headphones", "RHP",
+ "Speaker", "LSPK",
+ "Speaker", "RSPK",
+ "Line Out", "AUXOUT1",
+ "Line Out", "AUXOUT2",
+ "LAUX", "Line In",
+ "RAUX", "Line In",
+ "LMICP", "Mic In",
+ "RMICP", "Mic In";
+ simple-audio-card,widgets =
+ "Headphones", "Headphones",
+ "Line Out", "Line Out",
+ "Speaker", "Speaker",
+ "Microphone", "Mic In",
+ "Line", "Line In";
+
+ codec_dai: simple-audio-card,codec {
+ clocks = <&scmi_clk IMX95_CLK_SAI3>;
+ sound-dai = <&nau8822_1a>;
+ };
+
+ simple-audio-card,cpu {
+ sound-dai = <&sai3>;
+ };
+ };
+};
+
+/* Verdin ADC_1, ADC_2, ADC_3 and ADC_4 */
+&adc1 {
+ status = "okay";
+};
+
+/* Verdin ETH_1 (On-module PHY) */
+&enetc_port0 {
+ status = "okay";
+};
+
+/* Verdin ETH_2_RGMII */
+&enetc_port1 {
+ phy-handle = <ðphy2>;
+ phy-mode = "rgmii-id";
+
+ status = "okay";
+};
+
+/* Verdin CAN_1 */
+&flexcan1 {
+ status = "okay";
+};
+
+/* Verdin CAN_2 */
+&flexcan2 {
+ status = "okay";
+};
+
+/* Verdin QSPI_1 */
+&flexspi1 {
+ status = "okay";
+};
+
+&gpio1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
+};
+
+&gpio2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio1>,
+ <&pinctrl_gpio2>,
+ <&pinctrl_gpio3>;
+};
+
+&gpio3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio6>;
+};
+
+&gpio4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio5>;
+};
+
+&gpio5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio4>;
+};
+
+/* Verdin I2C_3_HDMI */
+&i3c2 {
+ status = "okay";
+};
+
+/* Verdin I2C_2_DSI */
+&lpi2c3 {
+ status = "okay";
+};
+
+/* Verdin I2C_1 */
+&lpi2c4 {
+ status = "okay";
+
+ nau8822_1a: audio-codec@1a {
+ compatible = "nuvoton,nau8822";
+ reg = <0x1a>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai3_mclk>;
+ #sound-dai-cells = <0>;
+ };
+
+ carrier_gpio_expander: gpio@21 {
+ compatible = "nxp,pcal6416";
+ reg = <0x21>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ };
+
+ /* Current measurement into module VCC */
+ hwmon@40 {
+ compatible = "ti,ina219";
+ reg = <0x40>;
+ shunt-resistor = <10000>;
+ };
+
+ temperature-sensor@4f {
+ compatible = "ti,tmp75c";
+ reg = <0x4f>;
+ };
+
+ carrier_eeprom: eeprom@57 {
+ compatible = "st,24c02", "atmel,24c02";
+ reg = <0x57>;
+ pagesize = <16>;
+ };
+};
+
+/* Verdin I2C_4_CSI */
+&lpi2c5 {
+ status = "okay";
+};
+
+/* Verdin UART_3, used as the Linux console */
+&lpuart1 {
+ status = "okay";
+};
+
+/* Verdin UART_4 */
+&lpuart2 {
+ status = "okay";
+};
+
+/* Verdin UART_1, connector X50 through RS485 transceiver */
+&lpuart7 {
+ rs485-rts-active-low;
+ rs485-rx-during-tx;
+ linux,rs485-enabled-at-boot-time;
+
+ status = "okay";
+};
+
+/* Verdin UART_2 */
+&lpuart8 {
+ status = "okay";
+};
+
+&netc_emdio {
+ ethphy2: ethernet-phy@7 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <7>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_eth2_rgmii_int>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
+ micrel,led-mode = <0>;
+ };
+};
+
+/* Verdin PCIE_1 */
+&pcie0 {
+ status = "okay";
+};
+
+/* Verdin I2S_1 */
+&sai3 {
+ status = "okay";
+};
+
+/* Verdin PWM_1 */
+&tpm4 {
+ status = "okay";
+};
+
+/* Verdin PWM_2 */
+&tpm5 {
+ status = "okay";
+};
+
+/* Verdin PWM_3_DSI */
+&tpm6 {
+ status = "okay";
+};
+
+/* Verdin USB_1 */
+&usb2 {
+ status = "okay";
+};
+
+/* Verdin USB_2 */
+&usb3 {
+ fsl,permanently-attached;
+
+ status = "okay";
+};
+
+&usb3_phy {
+ status = "okay";
+};
+
+/* Verdin SD_1 */
+&usdhc2 {
+ status = "okay";
+};
+
+/* Verdin CTRL_WAKE1_MICO# */
+&verdin_gpio_keys {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-dev.dts b/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-dev.dts
new file mode 100644
index 000000000000..97636ec7c26a
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi-dev.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) Toradex
+ *
+ * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95
+ * https://www.toradex.com/products/carrier-board/verdin-development-board-kit
+ */
+
+/dts-v1/;
+
+#include "imx95-verdin.dtsi"
+#include "imx95-verdin-nonwifi.dtsi"
+#include "imx95-verdin-dev.dtsi"
+
+/ {
+ model = "Toradex Verdin iMX95 on Verdin Development Board";
+ compatible = "toradex,verdin-imx95-nonwifi-dev",
+ "toradex,verdin-imx95-nonwifi",
+ "toradex,verdin-imx95",
+ "fsl,imx95";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi.dtsi b/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi.dtsi
new file mode 100644
index 000000000000..7aba22067de5
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx95-verdin-nonwifi.dtsi
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) Toradex
+ *
+ * Common dtsi for Verdin iMX95 SoM non-WB variant
+ *
+ * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95
+ */
+
+/* SDIO on MSP 30, 31, 32, 33, 34, 35 */
+&usdhc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+
+ status = "disabled";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-wifi-dev.dts b/arch/arm64/boot/dts/freescale/imx95-verdin-wifi-dev.dts
new file mode 100644
index 000000000000..345d37247025
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx95-verdin-wifi-dev.dts
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) Toradex
+ *
+ * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95
+ * https://www.toradex.com/products/carrier-board/verdin-development-board-kit
+ */
+
+/dts-v1/;
+
+#include "imx95-verdin.dtsi"
+#include "imx95-verdin-wifi.dtsi"
+#include "imx95-verdin-dev.dtsi"
+
+/ {
+ model = "Toradex Verdin iMX95 WB on Verdin Development Board";
+ compatible = "toradex,verdin-imx95-wifi-dev",
+ "toradex,verdin-imx95-wifi",
+ "toradex,verdin-imx95",
+ "fsl,imx95";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin-wifi.dtsi b/arch/arm64/boot/dts/freescale/imx95-verdin-wifi.dtsi
new file mode 100644
index 000000000000..256c9ed04605
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx95-verdin-wifi.dtsi
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) Toradex
+ *
+ * Common dtsi for Verdin iMX95 SoM WB variant
+ *
+ * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95
+ */
+
+/ {
+ reg_wifi_en: regulator-wifi-en {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wifi_pwr_en>;
+ /* PMIC_EN_WIFI */
+ gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "PDn_MAYA-W260";
+ startup-delay-us = <2000>;
+ };
+};
+
+/* On-module Bluetooth */
+&lpuart6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_bt_uart>;
+ uart-has-rtscts;
+
+ status = "okay";
+
+ som_bt: bluetooth {
+ compatible = "nxp,88w8987-bt";
+ fw-init-baudrate = <3000000>;
+ };
+};
+
+/* On-module Wi-Fi */
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ keep-power-in-suspend;
+ non-removable;
+ vmmc-supply = <®_wifi_en>;
+
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx95-verdin.dtsi
new file mode 100644
index 000000000000..d3737956e2f9
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx95-verdin.dtsi
@@ -0,0 +1,1162 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) Toradex
+ *
+ * Common dtsi for Verdin iMX95 SoM
+ *
+ * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx95
+ */
+
+#include <dt-bindings/net/ti-dp83867.h>
+#include "imx95.dtsi"
+
+/ {
+ aliases {
+ can0 = &flexcan1;
+ can1 = &flexcan2;
+ eeprom0 = &som_eeprom;
+ ethernet0 = &enetc_port0;
+ ethernet1 = &enetc_port1;
+ i2c0 = &lpi2c2;
+ i2c1 = &lpi2c4;
+ i2c2 = &lpi2c3;
+ i2c3 = &i3c2;
+ i2c4 = &lpi2c5;
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc2;
+ mmc2 = &usdhc3;
+ rtc0 = &rtc_i2c;
+ rtc1 = &scmi_bbm;
+ serial0 = &lpuart7;
+ serial1 = &lpuart8;
+ serial2 = &lpuart1;
+ serial3 = &lpuart2;
+ serial4 = &lpuart6;
+ usb0 = &usb2;
+ usb1 = &usb3;
+ };
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+
+ connector {
+ compatible = "gpio-usb-b-connector", "usb-b-connector";
+ /* Verdin USB_1_ID (SODIMM 161) */
+ id-gpios = <&som_gpio_expander 5 GPIO_ACTIVE_HIGH>;
+ label = "USB_1";
+ self-powered;
+ vbus-supply = <®_usb1_vbus>;
+
+ port {
+ usb_dr_connector: endpoint {
+ remote-endpoint = <&usb1_id>;
+ };
+ };
+ };
+
+ verdin_gpio_keys: gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ctrl_wake1_mico>;
+
+ status = "disabled";
+
+ verdin_key_wakeup: key-wakeup {
+ /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */
+ gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+ label = "Wake-Up";
+ linux,code = <KEY_WAKEUP>;
+ wakeup-source;
+ };
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-name = "On-module +V1.8";
+ };
+
+ /*
+ * By default we enable CTRL_SLEEP_MOCI#, this is required to have
+ * peripherals on the carrier board powered.
+ * If more granularity or power saving is required this can be disabled
+ * in the carrier board device tree files.
+ */
+ reg_force_sleep_moci: regulator-force-sleep-moci {
+ compatible = "regulator-fixed";
+ /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
+ gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "CTRL_SLEEP_MOCI#";
+ };
+
+ reg_usb1_vbus: regulator-usb1-vbus {
+ compatible = "regulator-fixed";
+ /* Verdin USB_1_EN (SODIMM 155) */
+ gpios = <&som_gpio_expander 7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-name = "USB_1_EN";
+ };
+
+ reg_usb2_vbus: regulator-usb2-vbus {
+ compatible = "regulator-fixed";
+ /* Verdin USB_2_EN (SODIMM 185) */
+ gpios = <&som_gpio_expander 8 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-name = "USB_2_EN";
+ };
+
+ reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc {
+ compatible = "regulator-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2_vsel>;
+ gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <1800000>;
+ states = <1800000 0x1>,
+ <3300000 0x0>;
+ regulator-name = "PMIC_SD2_VSEL";
+ };
+
+ reg_usdhc2_vmmc: regulator-vmmc-usdhc2 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
+ /* Verdin SD_1_PWR_EN (SODIMM 76) */
+ gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ off-on-delay-us = <100000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "SD_1_PWR_EN";
+ startup-delay-us = <20000>;
+ };
+
+ cm7: remoteproc-cm7 {
+ compatible = "fsl,imx95-cm7";
+ mbox-names = "tx", "rx", "rxdb";
+ mboxes = <&mu7 0 1
+ &mu7 1 1
+ &mu7 3 1>;
+ memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
+ <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>, <&m7_reserved>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ linux_cma: linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0 0x3c000000>;
+ alloc-ranges = <0 0x80000000 0 0x7F000000>;
+ linux,cma-default;
+ };
+
+ m7_reserved: memory@80000000 {
+ reg = <0 0x80000000 0 0x1000000>;
+ no-map;
+ };
+
+ vdev0vring0: vdev0vring0@88000000 {
+ reg = <0 0x88000000 0 0x8000>;
+ no-map;
+ };
+
+ vdev0vring1: vdev0vring1@88008000 {
+ reg = <0 0x88008000 0 0x8000>;
+ no-map;
+ };
+
+ vdev1vring0: vdev1vring0@88010000 {
+ reg = <0 0x88010000 0 0x8000>;
+ no-map;
+ };
+
+ vdev1vring1: vdev1vring1@88018000 {
+ reg = <0 0x88018000 0 0x8000>;
+ no-map;
+ };
+
+ vdevbuffer: vdevbuffer@88020000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x88020000 0 0x100000>;
+ no-map;
+ };
+
+ rsc_table: rsc-table@88220000 {
+ reg = <0 0x88220000 0 0x1000>;
+ no-map;
+ };
+ };
+};
+
+/* Verdin ADC_1, ADC_2, ADC_3 and ADC_4 */
+&adc1 {
+ vref-supply = <®_1p8v>;
+};
+
+/* Verdin ETH_1 (On-module PHY) */
+&enetc_port0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enetc0>;
+ phy-handle = <ðphy1>;
+ phy-mode = "rgmii-id";
+};
+
+/* Verdin ETH_2_RGMII */
+&enetc_port1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enetc1>;
+};
+
+/* Verdin CAN_1 */
+&flexcan1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+};
+
+/* Verdin CAN_2 */
+&flexcan2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+};
+
+/* Verdin QSPI_1 */
+&flexspi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexspi1>;
+};
+
+&gpio1 {
+ gpio-line-names =
+ "", /* 0 */
+ "",
+ "",
+ "",
+ "SODIMM_147",
+ "SODIMM_149",
+ "SODIMM_151",
+ "SODIMM_153",
+ "SODIMM_20",
+ "SODIMM_22",
+ "SODIMM_252", /* 10 */
+ "",
+ "SODIMM_189",
+ "IO_EXP_INT",
+ "SODIMM_256",
+ "";
+
+ status = "okay";
+};
+
+&gpio2 {
+ gpio-line-names =
+ "SODIMM_206", /* 0 */
+ "SODIMM_198",
+ "SODIMM_200",
+ "SODIMM_196",
+ "",
+ "SODIMM_15",
+ "SODIMM_16",
+ "",
+ "SODIMM_131",
+ "SODIMM_129",
+ "SODIMM_135", /* 10 */
+ "SODIMM_133",
+ "SODIMM_139",
+ "SODIMM_137",
+ "SODIMM_143",
+ "SODIMM_141",
+ "SODIMM_30",
+ "SODIMM_38",
+ "SODIMM_208",
+ "SODIMM_19",
+ "SODIMM_36", /* 20 */
+ "SODIMM_34",
+ "SODIMM_93",
+ "SODIMM_95",
+ "SODIMM_210",
+ "SODIMM_24",
+ "SODIMM_32",
+ "SODIMM_26",
+ "SODIMM_53",
+ "SODIMM_55",
+ "SODIMM_12", /* 30 */
+ "SODIMM_14";
+};
+
+&gpio3 {
+ gpio-line-names =
+ "SODIMM_84", /* 0 */
+ "SODIMM_78",
+ "SODIMM_74",
+ "SODIMM_80",
+ "SODIMM_82",
+ "SODIMM_70",
+ "SODIMM_72",
+ "SODIMM_76",
+ "",
+ "",
+ "", /* 10 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "PMIC_SD2_VSEL",
+ "", /* 20 */
+ "",
+ "",
+ "",
+ "",
+ "",
+ "SODIMM_91",
+ "SODIMM_218",
+ "",
+ "",
+ "", /* 30 */
+ "";
+};
+
+&gpio4 {
+ gpio-line-names =
+ "SODIMM_59", /* 0 */
+ "SODIMM_57",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "", /* 10 */
+ "",
+ "",
+ "",
+ "SODIMM_193",
+ "SODIMM_191",
+ "SODIMM_215",
+ "SODIMM_217",
+ "SODIMM_219",
+ "SODIMM_221",
+ "SODIMM_211", /* 20 */
+ "SODIMM_213",
+ "SODIMM_199",
+ "SODIMM_197",
+ "SODIMM_201",
+ "SODIMM_203",
+ "SODIMM_205",
+ "SODIMM_207",
+ "SODIMM_216",
+ "SODIMM_202";
+};
+
+&gpio5 {
+ gpio-line-names =
+ "SODIMM_56", /* 0 */
+ "SODIMM_58",
+ "SODIMM_60",
+ "SODIMM_62",
+ "SODIMM_46",
+ "SODIMM_44",
+ "SODIMM_42",
+ "SODIMM_48",
+ "SODIMM_66",
+ "SODIMM_52",
+ "SODIMM_54", /* 10 */
+ "SODIMM_64",
+ "SODIMM_212",
+ "",
+ "",
+ "",
+ "",
+ "";
+};
+
+/* Verdin I2C_3_HDMI */
+&i3c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i3c2>;
+ i2c-scl-hz = <400000>;
+};
+
+/* CTRL_I2C (On-module I2C) */
+&lpi2c2 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_lpi2c2>, <&pinctrl_io_exp_int>;
+ pinctrl-1 = <&pinctrl_lpi2c2_gpio>, <&pinctrl_io_exp_int>;
+ clock-frequency = <400000>;
+ scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ single-master;
+
+ status = "okay";
+
+ som_gpio_expander: gpio@20 {
+ compatible = "nxp,pcal6416";
+ reg = <0x20>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ interrupt-parent = <&gpio1>;
+ interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
+ #gpio-cells = <2>;
+ gpio-controller;
+
+ gpio-line-names =
+ "SODIMM_220", /* 0 */
+ "SODIMM_222",
+ "SODIMM_17",
+ "SODIMM_21",
+ "SODIMM_244",
+ "SODIMM_161",
+ "SODIMM_157",
+ "SODIMM_155",
+ "SODIMM_185",
+ "SODIMM_187",
+ "USB_RECOV_CTRL#", /* 10 */
+ "ENET1_INT#",
+ "TPM_INT#",
+ "TPM_CS#",
+ "",
+ "";
+
+ /*
+ * Switch USB to default position:
+ * - SoC USB2 -> Verdin USB_1
+ * - SoC USB1 -> Verdin USB_2
+ * Reset configuration:
+ * - SoC USB1 -> Verdin USB_1 (USB recovery)
+ * - SoC USB2 not connected
+ */
+ usb_recov_ctrl: usb-recov-ctrl-hog {
+ gpio-hog;
+ gpios = <10 GPIO_ACTIVE_HIGH>;
+ line-name = "USB_RECOV_CTRL#";
+ output-high;
+ };
+ };
+
+ rtc_i2c: rtc@32 {
+ compatible = "epson,rx8130";
+ reg = <0x32>;
+ };
+
+ temperature-sensor@48 {
+ compatible = "ti,tmp1075";
+ reg = <0x48>;
+ };
+
+ som_eeprom: eeprom@50 {
+ compatible = "st,24c02", "atmel,24c02";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+};
+
+/* Verdin I2C_2_DSI */
+&lpi2c3 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_lpi2c3>;
+ pinctrl-1 = <&pinctrl_lpi2c3_gpio>;
+ clock-frequency = <100000>;
+ scl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ single-master;
+};
+
+/* Verdin I2C_1 */
+&lpi2c4 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_lpi2c4>;
+ pinctrl-1 = <&pinctrl_lpi2c4_gpio>;
+ clock-frequency = <100000>;
+ scl-gpios = <&gpio2 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ single-master;
+};
+
+/* Verdin I2C_4_CSI */
+&lpi2c5 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_lpi2c5>;
+ pinctrl-1 = <&pinctrl_lpi2c5_gpio>;
+ clock-frequency = <100000>;
+ scl-gpios = <&gpio2 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&gpio2 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ single-master;
+};
+
+/* Verdin SPI_1 */
+&lpspi6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpspi6>, <&pinctrl_spi1_cs>;
+ cs-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>,
+ <&som_gpio_expander 13 GPIO_ACTIVE_LOW>;
+
+ status = "okay";
+
+ som_tpm: tpm@1 {
+ compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
+ reg = <0x1>;
+ interrupt-parent = <&som_gpio_expander>;
+ interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
+ /*
+ * Maximum TPM-supported speed is 18.5 MHz, limited to 12 MHz
+ * here as lpspi6's per-clock (twice the max speed) is 24 MHz
+ */
+ spi-max-frequency = <12000000>;
+ };
+};
+
+/* Verdin UART_3, used as the Linux console */
+&lpuart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+};
+
+/* Verdin UART_4 */
+&lpuart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+};
+
+/* Verdin UART_1 */
+&lpuart7 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart7>;
+ uart-has-rtscts;
+};
+
+/* Verdin UART_2 */
+&lpuart8 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart8>;
+ uart-has-rtscts;
+};
+
+&mu7 {
+ status = "okay";
+};
+
+&netc_blk_ctrl {
+ status = "okay";
+};
+
+&netc_bus0 {
+ msi-map = <0x0 &its 0x60 0x1>, //ENETC0 PF
+ <0x10 &its 0x61 0x1>, //ENETC0 VF0
+ <0x20 &its 0x62 0x1>, //ENETC0 VF1
+ <0x40 &its 0x63 0x1>, //ENETC1 PF
+ <0x50 &its 0x65 0x1>, //ENETC1 VF0
+ <0x60 &its 0x66 0x1>, //ENETC1 VF1
+ <0x80 &its 0x64 0x1>, //ENETC2 PF
+ <0xc0 &its 0x67 0x1>; //NETC Timer
+ iommu-map = <0x0 &smmu 0x20 0x1>,
+ <0x10 &smmu 0x21 0x1>,
+ <0x20 &smmu 0x22 0x1>,
+ <0x40 &smmu 0x23 0x1>,
+ <0x50 &smmu 0x25 0x1>,
+ <0x60 &smmu 0x26 0x1>,
+ <0x80 &smmu 0x24 0x1>,
+ <0xc0 &smmu 0x27 0x1>;
+};
+
+/* Verdin ETH_2_RGMII_MDIO, shared between all ethernet ports */
+&netc_emdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_emdio>;
+
+ status = "okay";
+
+ ethphy1: ethernet-phy@0 {
+ reg = <0>;
+ interrupt-parent = <&som_gpio_expander>;
+ interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ };
+};
+
+&netc_timer {
+ status = "okay";
+};
+
+&netcmix_blk_ctrl {
+ status = "okay";
+};
+
+/* Verdin PCIE_1 */
+&pcie0 {
+ /* PCIE_1_RESET# (SODIMM 244) */
+ reset-gpios = <&som_gpio_expander 4 GPIO_ACTIVE_LOW>;
+};
+
+/* Verdin I2S_1 */
+&sai3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sai3>;
+ assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>,
+ <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>,
+ <&scmi_clk IMX95_CLK_AUDIOPLL1>,
+ <&scmi_clk IMX95_CLK_AUDIOPLL2>,
+ <&scmi_clk IMX95_CLK_SAI3>;
+ assigned-clock-parents = <0>, <0>, <0>, <0>,
+ <&scmi_clk IMX95_CLK_AUDIOPLL1>;
+ assigned-clock-rates = <3932160000>,
+ <3612672000>, <393216000>,
+ <361267200>, <12288000>;
+ #sound-dai-cells = <0>;
+ fsl,sai-mclk-direction-output;
+};
+
+&scmi_bbm {
+ linux,code = <KEY_POWER>;
+};
+
+&thermal_zones {
+ /* PF09 Main PMIC */
+ pf09-thermal {
+ polling-delay = <2000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&scmi_sensor 2>;
+
+ trips {
+ trip0 {
+ hysteresis = <2000>;
+ temperature = <155000>;
+ type = "critical";
+ };
+ };
+ };
+
+ /* PF53 VDD_ARM PMIC */
+ pf53-arm-thermal {
+ polling-delay = <2000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&scmi_sensor 4>;
+
+ trips {
+ trip0 {
+ hysteresis = <2000>;
+ temperature = <155000>;
+ type = "critical";
+ };
+ };
+ };
+
+ /* PF53 VDD_SOC PMIC */
+ pf53-soc-thermal {
+ polling-delay = <2000>;
+ polling-delay-passive = <250>;
+ thermal-sensors = <&scmi_sensor 3>;
+
+ trips {
+ trip0 {
+ hysteresis = <2000>;
+ temperature = <155000>;
+ type = "critical";
+ };
+ };
+ };
+};
+
+/* Verdin PWM_1 */
+&tpm4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tpm4>;
+};
+
+/* Verdin PWM_2 */
+&tpm5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tpm5>;
+};
+
+/* Verdin PWM_3_DSI */
+&tpm6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tpm6>;
+};
+
+/* Verdin USB_1 */
+&usb2 {
+ dr_mode = "otg";
+ adp-disable;
+ hnp-disable;
+ srp-disable;
+ usb-role-switch;
+ vbus-supply = <®_usb1_vbus>;
+
+ port {
+ usb1_id: endpoint {
+ remote-endpoint = <&usb_dr_connector>;
+ };
+ };
+};
+
+/* Verdin USB_2 */
+&usb3 {
+ fsl,disable-port-power-control;
+};
+
+&usb3_dwc3 {
+ dr_mode = "host";
+};
+
+&usb3_phy {
+ vbus-supply = <®_usb2_vbus>;
+};
+
+/* On-module eMMC */
+&usdhc1 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ bus-width = <8>;
+ non-removable;
+ no-sdio;
+ no-sd;
+
+ status = "okay";
+};
+
+/* Verdin SD_1 */
+&usdhc2 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>;
+ pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>,<&pinctrl_usdhc2_cd>;
+ pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd>;
+ cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <®_usdhc2_vmmc>;
+ vqmmc-supply = <®_usdhc2_vqmmc>;
+};
+
+&wdog3 {
+ fsl,ext-reset-output;
+
+ status = "okay";
+};
+
+&scmi_iomuxc {
+ /* On-module Bluetooth on WB SKUs, module-specific UART otherwise */
+ pinctrl_bt_uart: btuartgrp {
+ fsl,pins = <IMX95_PAD_GPIO_IO04__LPUART6_TX 0x31e>, /* WiFi_UART_SoC_TXD */
+ <IMX95_PAD_GPIO_IO33__LPUART6_RX 0x31e>, /* WiFi_UART_SoC_RXD */
+ <IMX95_PAD_GPIO_IO34__LPUART6_CTS_B 0x31e>, /* WiFi_UART_SoC_CTS */
+ <IMX95_PAD_GPIO_IO07__LPUART6_RTS_B 0x31e>; /* WiFi_UART_SoC_RTS */
+ };
+
+ /* Verdin CSI_1_MCLK */
+ pinctrl_csi1_mclk: csi1mclkgrp {
+ fsl,pins = <IMX95_PAD_CCM_CLKO1__CCMSRCGPCMIX_TOP_CLKO_1 0x51e>; /* SODIMM 91 */
+ };
+
+ /* Verdin CTRL_SLEEP_MOCI# */
+ pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp {
+ fsl,pins = <IMX95_PAD_SAI1_RXD0__AONMIX_TOP_GPIO1_IO_BIT14 0x51e>; /* SODIMM 256 */
+ };
+
+ /* Verdin CTRL_WAKE1_MICO# */
+ pinctrl_ctrl_wake1_mico: ctrlwake1micogrp {
+ fsl,pins = <IMX95_PAD_PDM_BIT_STREAM1__AONMIX_TOP_GPIO1_IO_BIT10 0x31e>; /* SODIMM 252 */
+ };
+
+ /* Verdin ETH_2_RGMII_MDIO, shared between all ethernet ports */
+ pinctrl_emdio: emdiogrp {
+ fsl,pins = <IMX95_PAD_ENET2_MDC__NETCMIX_TOP_NETC_MDC 0x50e>, /* ENET2_MDC, SODIMM 193 */
+ <IMX95_PAD_ENET2_MDIO__NETCMIX_TOP_NETC_MDIO 0x90e>; /* ENET2_MDIO, SODIMM 191 */
+ };
+
+ /* Verdin ETH_1 (On-module PHY) */
+ pinctrl_enetc0: enetc0grp {
+ fsl,pins = <IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e>, /* ENET1_TX_CTL */
+ <IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e>, /* ENET1_TXC */
+ <IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x50e>, /* ENET1_TDO */
+ <IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x50e>, /* ENET1_TD1 */
+ <IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x50e>, /* ENET1_TD2 */
+ <IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x50e>, /* ENET1_TD3 */
+ <IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e>, /* ENET1_RX_CTL */
+ <IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e>, /* ENET1_RXC */
+ <IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e>, /* ENET1_RD0 */
+ <IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e>, /* ENET1_RD1 */
+ <IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e>, /* ENET1_RD2 */
+ <IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e>; /* ENET1_RD3 */
+ };
+
+ /* Verdin ETH_2_RGMII */
+ pinctrl_enetc1: enetc1grp {
+ fsl,pins = <IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x57e>, /* ENET2_TX_CTL */
+ <IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x58e>, /* ENET2_TXC */
+ <IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x50e>, /* ENET2_TD0 */
+ <IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x50e>, /* ENET2_TD1 */
+ <IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x50e>, /* ENET2_TD2 */
+ <IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x50e>, /* ENET2_TD3 */
+ <IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x57e>, /* ENET2_RX_CTL */
+ <IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x58e>, /* ENET2_RXC */
+ <IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x57e>, /* ENET2_RD0 */
+ <IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x57e>, /* ENET2_RD1 */
+ <IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x57e>, /* ENET2_RD2 */
+ <IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x57e>; /* ENET2_RD3 */
+ };
+
+ /* Verdin ETH_2_RGMII_INT# */
+ pinctrl_eth2_rgmii_int: eth2rgmiiintgrp {
+ fsl,pins = <IMX95_PAD_SAI1_TXC__AONMIX_TOP_GPIO1_IO_BIT12 0x31e>; /* SODIMM 189 */
+ };
+
+ /* Verdin CAN_1 */
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <IMX95_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX 0x39e>, /* SODIMM 20 */
+ <IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX 0x39e>; /* SODIMM 22 */
+ };
+
+ /* Verdin CAN_2 */
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <IMX95_PAD_GPIO_IO25__CAN2_TX 0x39e>, /* SODIMM 24 */
+ <IMX95_PAD_GPIO_IO27__CAN2_RX 0x39e>; /* SODIMM 26 */
+ };
+
+ /* Verdin QSPI_1 */
+ pinctrl_flexspi1: flexspi1grp {
+ fsl,pins = <IMX95_PAD_XSPI1_SS0_B__FLEXSPI1_A_SS0_B 0x3fe>, /* SODIMM 54 */
+ <IMX95_PAD_XSPI1_SS1_B__FLEXSPI1_A_SS1_B 0x3fe>, /* SODIMM 64 */
+ <IMX95_PAD_XSPI1_SCLK__XSPI_CLK 0x3fe>, /* SODIMM 52 */
+ <IMX95_PAD_XSPI1_DATA0__XSPI_DATA_BIT0 0x3fe>, /* SODIMM 56 */
+ <IMX95_PAD_XSPI1_DATA1__XSPI_DATA_BIT1 0x3fe>, /* SODIMM 58 */
+ <IMX95_PAD_XSPI1_DATA2__XSPI_DATA_BIT2 0x3fe>, /* SODIMM 60 */
+ <IMX95_PAD_XSPI1_DATA3__XSPI_DATA_BIT3 0x3fe>, /* SODIMM 62 */
+ <IMX95_PAD_XSPI1_DQS__XSPI_DQS 0x3fe>; /* SODIMM 66 */
+ };
+
+ /* Verdin GPIO_1 */
+ pinctrl_gpio1: gpio1grp {
+ fsl,pins = <IMX95_PAD_GPIO_IO00__GPIO2_IO_BIT0 0x51e>; /* SODIMM 206 */
+ };
+
+ /* Verdin GPIO_2 */
+ pinctrl_gpio2: gpio2grp {
+ fsl,pins = <IMX95_PAD_GPIO_IO18__GPIO2_IO_BIT18 0x51e>; /* SODIMM 208 */
+ };
+
+ /* Verdin GPIO_3 */
+ pinctrl_gpio3: gpio3grp {
+ fsl,pins = <IMX95_PAD_GPIO_IO24__GPIO2_IO_BIT24 0x51e>; /* SODIMM 210 */
+ };
+
+ /* Verdin GPIO_4 */
+ pinctrl_gpio4: gpio4grp {
+ fsl,pins = <IMX95_PAD_GPIO_IO32__GPIO5_IO_BIT12 0x51e>; /* SODIMM 212 */
+ };
+
+ /* Verdin GPIO_5_CSI */
+ pinctrl_gpio5: gpio5grp {
+ fsl,pins = <IMX95_PAD_CCM_CLKO3__GPIO4_IO_BIT28 0x51e>; /* SODIMM 216 */
+ };
+
+ /* Verdin GPIO_6_CSI */
+ pinctrl_gpio6: gpio6grp {
+ fsl,pins = <IMX95_PAD_CCM_CLKO2__GPIO3_IO_BIT27 0x51e>; /* SODIMM 218 */
+ };
+
+ /* Verdin I2S_2_BCLK as GPIO (conflict with Verdin I2S_2) */
+ pinctrl_i2s_2_bclk_gpio: i2s2bclkgpiogrp {
+ fsl,pins = <IMX95_PAD_XSPI1_DATA6__GPIO5_IO_BIT6 0x51e>; /* SODIMM 42 */
+ };
+
+ /* Verdin I2S_2_D_IN as GPIO (conflict with Verdin I2S_2) */
+ pinctrl_i2s_2_d_in_gpio: i2s2dingpiogrp {
+ fsl,pins = <IMX95_PAD_XSPI1_DATA7__GPIO5_IO_BIT7 0x31e>; /* SODIMM 48 */
+ };
+
+ /* Verdin I2S_2_D_OUT as GPIO (conflict with Verdin I2S_2) */
+ pinctrl_i2s_2_d_out_gpio: i2s2doutgpiogrp {
+ fsl,pins = <IMX95_PAD_XSPI1_DATA4__GPIO5_IO_BIT4 0x51e>; /* SODIMM 46 */
+ };
+
+ /* Verdin I2S_2_SYNC as GPIO (conflict with Verdin I2S_2) */
+ pinctrl_i2s_2_sync_gpio: i2s2syncgpiogrp {
+ fsl,pins = <IMX95_PAD_XSPI1_DATA5__GPIO5_IO_BIT5 0x51e>; /* SODIMM 44 */
+ };
+
+ /* Verdin I2C_3_HDMI */
+ pinctrl_i3c2: i3c2cgrp {
+ fsl,pins = <IMX95_PAD_ENET1_MDC__I3C2_SCL 0x40001186>, /* SODIMM 59 */
+ <IMX95_PAD_ENET1_MDIO__I3C2_SDA 0x40001186>; /* SODIMM 57 */
+ };
+
+ pinctrl_io_exp_int: ioexpintgrp {
+ fsl,pins = <IMX95_PAD_SAI1_TXD0__AONMIX_TOP_GPIO1_IO_BIT13 0x31e>; /* IO_EXP_INT */
+ };
+
+ /* CTRL_I2C (On-module I2C) */
+ pinctrl_lpi2c2_gpio: lpi2c2gpiogrp {
+ fsl,pins = <IMX95_PAD_I2C2_SCL__AONMIX_TOP_GPIO1_IO_BIT2 0x40001b9e>, /* CTRL_I2C_SCL */
+ <IMX95_PAD_I2C2_SDA__AONMIX_TOP_GPIO1_IO_BIT3 0x40001b9e>; /* CTRL_I2C_SDA */
+ };
+
+ pinctrl_lpi2c2: lpi2c2grp {
+ fsl,pins = <IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40001b9e>, /* CTRL_I2C_SCL */
+ <IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x40001b9e>; /* CTRL_I2C_SDA */
+ };
+
+ /* Verdin I2C_2_DSI */
+ pinctrl_lpi2c3_gpio: lpi2c3gpiogrp {
+ fsl,pins = <IMX95_PAD_GPIO_IO28__GPIO2_IO_BIT28 0x40001b9e>, /* SODIMM 53 */
+ <IMX95_PAD_GPIO_IO29__GPIO2_IO_BIT29 0x40001b9e>; /* SODIMM 55 */
+ };
+
+ pinctrl_lpi2c3: lpi2c3grp {
+ fsl,pins = <IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x40001b9e>, /* SODIMM 53 */
+ <IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x40001b9e>; /* SODIMM 55 */
+ };
+
+ /* Verdin I2C_1 */
+ pinctrl_lpi2c4_gpio: lpi2c4gpiogrp {
+ fsl,pins = <IMX95_PAD_GPIO_IO31__GPIO2_IO_BIT31 0x40001b9e>, /* SODIMM 14 */
+ <IMX95_PAD_GPIO_IO30__GPIO2_IO_BIT30 0x40001b9e>; /* SODIMM 12 */
+ };
+
+ pinctrl_lpi2c4: lpi2c4grp {
+ fsl,pins = <IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40001b9e>, /* SODIMM 14 */
+ <IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40001b9e>; /* SODIMM 12 */
+ };
+
+ /* Verdin I2C_4_CSI */
+ pinctrl_lpi2c5_gpio: lpi2c5gpiogrp {
+ fsl,pins = <IMX95_PAD_GPIO_IO22__GPIO2_IO_BIT22 0x40001b9e>, /* SODIMM 93 */
+ <IMX95_PAD_GPIO_IO23__GPIO2_IO_BIT23 0x40001b9e>; /* SODIMM 95 */
+ };
+
+ pinctrl_lpi2c5: lpi2c5grp {
+ fsl,pins = <IMX95_PAD_GPIO_IO22__LPI2C5_SDA 0x40001b9e>, /* SODIMM 93 */
+ <IMX95_PAD_GPIO_IO23__LPI2C5_SCL 0x40001b9e>; /* SODIMM 95 */
+ };
+
+ /* Verdin SPI_1 */
+ pinctrl_lpspi6: lpspi6grp {
+ fsl,pins = <IMX95_PAD_GPIO_IO01__LPSPI6_SIN 0x3fe>, /* SODIMM 198 */
+ <IMX95_PAD_GPIO_IO02__LPSPI6_SOUT 0x3fe>, /* SODIMM 200 */
+ <IMX95_PAD_GPIO_IO03__LPSPI6_SCK 0x3fe>; /* SODIMM 196 */
+ };
+
+ /* Verdin QSPI_1_CLK as GPIO (conflict with Verdin QSPI_1 interface) */
+ pinctrl_qspi1_clk_gpio: qspi1clkgpiogrp {
+ fsl,pins = <IMX95_PAD_XSPI1_SCLK__GPIO5_IO_BIT9 0x11e>; /* SODIMM 52 */
+ };
+
+ /* Verdin QSPI_1_CS2# as GPIO (conflict with Verdin QSPI_1 interface) */
+ pinctrl_qspi1_cs2_gpio: qspi1cs2gpiogrp {
+ fsl,pins = <IMX95_PAD_XSPI1_SS1_B__GPIO5_IO_BIT11 0x11e>; /* SODIMM 64 */
+ };
+
+ /* Verdin QSPI_1_CS# as GPIO (conflict with Verdin QSPI_1 interface) */
+ pinctrl_qspi1_cs_gpio: qspi1csgpiogrp {
+ fsl,pins = <IMX95_PAD_XSPI1_SS0_B__GPIO5_IO_BIT10 0x11e>; /* SODIMM 54 */
+ };
+
+ /* Verdin QSPI_1_DQS as GPIO (conflict with Verdin QSPI_1 interface) */
+ pinctrl_qspi1_dqs_gpio: qspi1dqsgpiogrp {
+ fsl,pins = <IMX95_PAD_XSPI1_DQS__GPIO5_IO_BIT8 0x11e>; /* SODIMM 66 */
+ };
+
+ /* Verdin QSPI_1_IO0 as GPIO (conflict with Verdin QSPI_1 interface) */
+ pinctrl_qspi1_io0_gpio: qspi1io0gpiogrp {
+ fsl,pins = <IMX95_PAD_XSPI1_DATA0__GPIO5_IO_BIT0 0x119e>; /* SODIMM 56 */
+ };
+
+ /* Verdin QSPI_1_IO1 as GPIO (conflict with Verdin QSPI_1 interface) */
+ pinctrl_qspi1_io1_gpio: qspi1io1gpiogrp {
+ fsl,pins = <IMX95_PAD_XSPI1_DATA1__GPIO5_IO_BIT1 0x119e>; /* SODIMM 58 */
+ };
+
+ /* Verdin QSPI_1_IO2 as GPIO (conflict with Verdin QSPI_1 interface) */
+ pinctrl_qspi1_io2_gpio: qspi1io2gpiogrp {
+ fsl,pins = <IMX95_PAD_XSPI1_DATA2__GPIO5_IO_BIT2 0x11e>; /* SODIMM 60 */
+ };
+
+ /* Verdin QSPI_1_IO3 as GPIO (conflict with Verdin QSPI_1 interface) */
+ pinctrl_qspi1_io3_gpio: qspi1io3gpiogrp {
+ fsl,pins = <IMX95_PAD_XSPI1_DATA3__GPIO5_IO_BIT3 0x11e>; /* SODIMM 62 */
+ };
+
+ /* Verdin I2S_1 */
+ pinctrl_sai3: sai3grp {
+ fsl,pins = <IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK 0x11e>, /* SODIMM 30 */
+ <IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 0x11e>, /* SODIMM 36 */
+ <IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0 0x11e>, /* SODIMM 34 */
+ <IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC 0x11e>; /* SODIMM 32 */
+ };
+
+ /* Verdin I2S_1_MCLK */
+ pinctrl_sai3_mclk: sai3mclkgrp {
+ fsl,pins = <IMX95_PAD_GPIO_IO17__SAI3_MCLK 0x31e>; /* SODIMM 38 */
+ };
+
+ /* Verdin I2S_2 */
+ pinctrl_sai5: sai5grp {
+ fsl,pins = <IMX95_PAD_XSPI1_DATA4__SAI5_TX_DATA_BIT0 0x11e>, /* SODIMM 46 */
+ <IMX95_PAD_XSPI1_DATA5__SAI5_TX_SYNC 0x11e>, /* SODIMM 44 */
+ <IMX95_PAD_XSPI1_DATA6__SAI5_TX_BCLK 0x11e>, /* SODIMM 42 */
+ <IMX95_PAD_XSPI1_DATA7__SAI5_RX_DATA_BIT0 0x11e>; /* SODIMM 48 */
+ };
+
+ /* Verdin SPI_1_CS */
+ pinctrl_spi1_cs: spi1csgrp {
+ fsl,pins = <IMX95_PAD_CCM_CLKO4__GPIO4_IO_BIT29 0x3fe>; /* SODIMM 202 */
+ };
+
+ /* Verdin PWM_1 */
+ pinctrl_tpm4: tpm4grp {
+ fsl,pins = <IMX95_PAD_GPIO_IO05__TPM4_CH0 0x11e>; /* SODIMM 15 */
+ };
+
+ /* Verdin PWM_2 */
+ pinctrl_tpm5: tpm5grp {
+ fsl,pins = <IMX95_PAD_GPIO_IO06__TPM5_CH0 0x11e>; /* SODIMM 16 */
+ };
+
+ /* Verdin PWM_3_DSI as GPIO */
+ pinctrl_tpm6_gpio: tpm6gpiogrp {
+ fsl,pins = <IMX95_PAD_GPIO_IO19__GPIO2_IO_BIT19 0x51e>; /* SODIMM 19 */
+ };
+
+ /* Verdin PWM_3_DSI */
+ pinctrl_tpm6: tpm6grp {
+ fsl,pins = <IMX95_PAD_GPIO_IO19__TPM6_CH2 0x11e>; /* SODIMM 19 */
+ };
+
+ /* Verdin UART_3, used as the Linux Console */
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e>, /* SODIMM 147 */
+ <IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e>; /* SODIMM 149 */
+ };
+
+ /* Verdin UART_4 */
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART2_RX 0x31e>, /* SODIMM 151 */
+ <IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART2_TX 0x31e>; /* SODIMM 153 */
+ };
+
+ /* Verdin UART_1 */
+ pinctrl_uart7: uart7grp {
+ fsl,pins = <IMX95_PAD_GPIO_IO08__LPUART7_TX 0x31e>, /* SODIMM 131 */
+ <IMX95_PAD_GPIO_IO09__LPUART7_RX 0x31e>, /* SODIMM 129 */
+ <IMX95_PAD_GPIO_IO10__LPUART7_CTS_B 0x31e>, /* SODIMM 135 */
+ <IMX95_PAD_GPIO_IO11__LPUART7_RTS_B 0x31e>; /* SODIMM 133 */
+ };
+
+ /* Verdin UART_2 */
+ pinctrl_uart8: uart8grp {
+ fsl,pins = <IMX95_PAD_GPIO_IO12__LPUART8_TX 0x31e>, /* SODIMM 139 */
+ <IMX95_PAD_GPIO_IO13__LPUART8_RX 0x31e>, /* SODIMM 137 */
+ <IMX95_PAD_GPIO_IO14__LPUART8_CTS_B 0x31e>, /* SODIMM 143 */
+ <IMX95_PAD_GPIO_IO15__LPUART8_RTS_B 0x31e>; /* SODIMM 141 */
+ };
+
+ /* On-module eMMC */
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e>, /* SD1_CLK */
+ <IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e>, /* SD1_CMD */
+ <IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e>, /* SD1_DATA0 */
+ <IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e>, /* SD1_DATA1 */
+ <IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e>, /* SD1_DATA2 */
+ <IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e>, /* SD1_DATA3 */
+ <IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e>, /* SD1_DATA4 */
+ <IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e>, /* SD1_DATA5 */
+ <IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e>, /* SD1_DATA6 */
+ <IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e>, /* SD1_DATA7 */
+ <IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e>; /* SD1_STROBE */
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+ fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe>, /* SD1_CLK */
+ <IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe>, /* SD1_CMD */
+ <IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe>, /* SD1_DATA0 */
+ <IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe>, /* SD1_DATA1 */
+ <IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe>, /* SD1_DATA2 */
+ <IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe>, /* SD1_DATA3 */
+ <IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe>, /* SD1_DATA4 */
+ <IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe>, /* SD1_DATA5 */
+ <IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe>, /* SD1_DATA6 */
+ <IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe>, /* SD1_DATA7 */
+ <IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe>; /* SD1_STROBE */
+ };
+
+ /* Verdin SD_1 */
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e>, /* SODIMM 78 */
+ <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e>, /* SODIMM 74 */
+ <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e>, /* SODIMM 80 */
+ <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e>, /* SODIMM 82 */
+ <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e>, /* SODIMM 70 */
+ <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e>; /* SODIMM 72 */
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe>, /* SODIMM 78 */
+ <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe>, /* SODIMM 74 */
+ <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe>, /* SODIMM 80 */
+ <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe>, /* SODIMM 82 */
+ <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe>, /* SODIMM 70 */
+ <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe>; /* SODIMM 72 */
+ };
+
+ pinctrl_usdhc2_sleep: usdhc2-sleepgrp {
+ fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x400>, /* SODIMM 78 */
+ <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x400>, /* SODIMM 74 */
+ <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x400>, /* SODIMM 80 */
+ <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x400>, /* SODIMM 82 */
+ <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x400>, /* SODIMM 70 */
+ <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x400>; /* SODIMM 72 */
+ };
+
+ /* Verdin SD_1_CD# */
+ pinctrl_usdhc2_cd: usdhc2-cdgrp {
+ fsl,pins = <IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x1100>; /* SODIMM 84 */
+ };
+
+ /* Verdin SD_1_PWR_EN */
+ pinctrl_usdhc2_pwr_en: usdhc2-pwrengrp {
+ fsl,pins = <IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x11e>; /* SODIMM 76 */
+ };
+
+ pinctrl_usdhc2_vsel: usdhc2-vselgrp {
+ fsl,pins = <IMX95_PAD_SD2_VSELECT__GPIO3_IO_BIT19 0x4>; /* PMIC_SD2_VSEL */
+ };
+
+ /* On-module Wi-Fi on WB SKUs, module-specific SDIO otherwise */
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e>, /* SD3_CLK */
+ <IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e>, /* SD3_CMD */
+ <IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e>, /* SD3_DATA0 */
+ <IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e>, /* SD3_DATA1 */
+ <IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e>, /* SD3_DATA2 */
+ <IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e>; /* SD3_DATA3 */
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+ fsl,pins = <IMX95_PAD_SD3_CLK__USDHC3_CLK 0x15fe>, /* SD3_CLK */
+ <IMX95_PAD_SD3_CMD__USDHC3_CMD 0x13fe>, /* SD3_CMD */
+ <IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe>, /* SD3_DATA1 */
+ <IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe>, /* SD3_DATA2 */
+ <IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe>, /* SD3_DATA3 */
+ <IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe>; /* SD3_DATA4 */
+ };
+
+ pinctrl_wifi_pwr_en: wifipwrengrp {
+ fsl,pins = <IMX95_PAD_SAI1_TXFS__AONMIX_TOP_GPIO1_IO_BIT11 0x51e>; /* PMIC_EN_WIFI */
+ };
+};
--
2.43.0
^ permalink raw reply related
* [PATCH v4 03/27] media: v4l2-common: add missing 1 and 2 byte RGB formats to v4l2_format_info
From: Sven Püschel @ 2026-03-25 14:50 UTC (permalink / raw)
To: Jacob Chen, Ezequiel Garcia, Mauro Carvalho Chehab,
Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-media, linux-rockchip, linux-arm-kernel, linux-kernel,
devicetree, kernel, nicolas, sebastian.reichel, Sven Püschel,
Nicolas Dufresne
In-Reply-To: <20260325-spu-rga3-v4-0-e90ec1c61354@pengutronix.de>
Add all missing one and two byte RGB formats to v4l2_format_info. This
allows drivers to more consistently use v4l2_format_info, as it now
covers all currently defined RGB formats.
Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Signed-off-by: Sven Püschel <s.pueschel@pengutronix.de>
---
drivers/media/v4l2-core/v4l2-common.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c
index 49c1ec08e2eb3..58a4b372cf5be 100644
--- a/drivers/media/v4l2-core/v4l2-common.c
+++ b/drivers/media/v4l2-core/v4l2-common.c
@@ -246,8 +246,29 @@ const struct v4l2_format_info *v4l2_format_info(u32 format)
{
static const struct v4l2_format_info formats[] = {
/* RGB formats (1 or 2 bytes per pixel) */
+ { .format = V4L2_PIX_FMT_RGB332, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 1, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
+ { .format = V4L2_PIX_FMT_RGB444, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
+ { .format = V4L2_PIX_FMT_ARGB444, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
+ { .format = V4L2_PIX_FMT_XRGB444, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
+ { .format = V4L2_PIX_FMT_RGBA444, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
+ { .format = V4L2_PIX_FMT_RGBX444, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
+ { .format = V4L2_PIX_FMT_ABGR444, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
+ { .format = V4L2_PIX_FMT_XBGR444, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
+ { .format = V4L2_PIX_FMT_BGRA444, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
+ { .format = V4L2_PIX_FMT_BGRX444, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
{ .format = V4L2_PIX_FMT_RGB555, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
+ { .format = V4L2_PIX_FMT_ARGB555, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
+ { .format = V4L2_PIX_FMT_XRGB555, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
+ { .format = V4L2_PIX_FMT_RGBA555, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
+ { .format = V4L2_PIX_FMT_RGBX555, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
+ { .format = V4L2_PIX_FMT_ABGR555, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
+ { .format = V4L2_PIX_FMT_XBGR555, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
+ { .format = V4L2_PIX_FMT_BGRA555, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
+ { .format = V4L2_PIX_FMT_BGRX555, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
{ .format = V4L2_PIX_FMT_RGB565, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
+ { .format = V4L2_PIX_FMT_RGB555X, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
+ { .format = V4L2_PIX_FMT_ARGB555X, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
+ { .format = V4L2_PIX_FMT_XRGB555X, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
{ .format = V4L2_PIX_FMT_RGB565X, .pixel_enc = V4L2_PIXEL_ENC_RGB, .mem_planes = 1, .comp_planes = 1, .bpp = { 2, 0, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 1, .vdiv = 1 },
/* RGB formats (3 or 4 bytes per pixel) */
--
2.53.0
^ permalink raw reply related
* [PATCH v4 05/27] media: v4l2-common: add v4l2_fill_pixfmt_mp_aligned helper
From: Sven Püschel @ 2026-03-25 14:50 UTC (permalink / raw)
To: Jacob Chen, Ezequiel Garcia, Mauro Carvalho Chehab,
Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-media, linux-rockchip, linux-arm-kernel, linux-kernel,
devicetree, kernel, nicolas, sebastian.reichel, Sven Püschel
In-Reply-To: <20260325-spu-rga3-v4-0-e90ec1c61354@pengutronix.de>
Add a v4l2_fill_pixfmt_mp_aligned helper which allows the user to
specify a custom stride alignment in bytes. This is necessary for
hardware like the Rockchip RGA3, which requires the stride value to be
aligned to a 16 bytes boundary.
The code makes some assumptions about the v4l2 format to simplify the
calculation. They currently hold for all known v4l2 formats.
Signed-off-by: Sven Püschel <s.pueschel@pengutronix.de>
---
drivers/media/v4l2-core/v4l2-common.c | 51 ++++++++++++++++++++++++++---------
include/media/v4l2-common.h | 4 +++
2 files changed, 43 insertions(+), 12 deletions(-)
diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c
index 2b5ccedeb6841..d64d7e76c834d 100644
--- a/drivers/media/v4l2-core/v4l2-common.c
+++ b/drivers/media/v4l2-core/v4l2-common.c
@@ -431,14 +431,28 @@ static inline unsigned int v4l2_format_block_height(const struct v4l2_format_inf
}
static inline unsigned int v4l2_format_plane_stride(const struct v4l2_format_info *info, int plane,
- unsigned int width)
+ unsigned int width, u8 byte_alignment)
{
unsigned int hdiv = plane ? info->hdiv : 1;
unsigned int aligned_width =
ALIGN(width, v4l2_format_block_width(info, plane));
- return DIV_ROUND_UP(aligned_width, hdiv) *
- info->bpp[plane] / info->bpp_div[plane];
+ /*
+ * Formats with a single memory plane derive the stride of the
+ * other planes from the y stride. Due to chroma subsampling this
+ * may cause the other plane strides to break the byte_alignment.
+ * Increase the alignment if necessary to prevent this.
+ *
+ * It assumes the following format properties:
+ * - bpp_div[0] == bpp_div[1]
+ * - The multiplication factor doesn't differ between the non y planes
+ */
+ if (info->mem_planes == 1 && info->comp_planes > 1 && plane == 0)
+ byte_alignment *= info->hdiv * info->bpp[0] / info->bpp[1];
+
+ return ALIGN(DIV_ROUND_UP(aligned_width, hdiv) * info->bpp[plane] /
+ info->bpp_div[plane],
+ byte_alignment);
}
static inline unsigned int v4l2_format_plane_height(const struct v4l2_format_info *info, int plane,
@@ -452,9 +466,10 @@ static inline unsigned int v4l2_format_plane_height(const struct v4l2_format_inf
}
static inline unsigned int v4l2_format_plane_size(const struct v4l2_format_info *info, int plane,
- unsigned int width, unsigned int height)
+ unsigned int width, unsigned int height,
+ u8 stride_alignment)
{
- return v4l2_format_plane_stride(info, plane, width) *
+ return v4l2_format_plane_stride(info, plane, width, stride_alignment) *
v4l2_format_plane_height(info, plane, height);
}
@@ -475,8 +490,9 @@ void v4l2_apply_frmsize_constraints(u32 *width, u32 *height,
}
EXPORT_SYMBOL_GPL(v4l2_apply_frmsize_constraints);
-int v4l2_fill_pixfmt_mp(struct v4l2_pix_format_mplane *pixfmt,
- u32 pixelformat, u32 width, u32 height)
+int v4l2_fill_pixfmt_mp_aligned(struct v4l2_pix_format_mplane *pixfmt,
+ u32 pixelformat, u32 width, u32 height,
+ u8 stride_alignment)
{
const struct v4l2_format_info *info;
struct v4l2_plane_pix_format *plane;
@@ -493,23 +509,34 @@ int v4l2_fill_pixfmt_mp(struct v4l2_pix_format_mplane *pixfmt,
if (info->mem_planes == 1) {
plane = &pixfmt->plane_fmt[0];
- plane->bytesperline = v4l2_format_plane_stride(info, 0, width);
+ plane->bytesperline = v4l2_format_plane_stride(info, 0, width,
+ stride_alignment);
plane->sizeimage = 0;
for (i = 0; i < info->comp_planes; i++)
plane->sizeimage +=
- v4l2_format_plane_size(info, i, width, height);
+ v4l2_format_plane_size(info, i, width, height,
+ stride_alignment);
} else {
for (i = 0; i < info->comp_planes; i++) {
plane = &pixfmt->plane_fmt[i];
plane->bytesperline =
- v4l2_format_plane_stride(info, i, width);
+ v4l2_format_plane_stride(info, i, width,
+ stride_alignment);
plane->sizeimage = plane->bytesperline *
v4l2_format_plane_height(info, i, height);
}
}
return 0;
}
+EXPORT_SYMBOL_GPL(v4l2_fill_pixfmt_mp_aligned);
+
+int v4l2_fill_pixfmt_mp(struct v4l2_pix_format_mplane *pixfmt,
+ u32 pixelformat, u32 width, u32 height)
+{
+ return v4l2_fill_pixfmt_mp_aligned(pixfmt, pixelformat,
+ width, height, 1);
+}
EXPORT_SYMBOL_GPL(v4l2_fill_pixfmt_mp);
int v4l2_fill_pixfmt(struct v4l2_pix_format *pixfmt, u32 pixelformat,
@@ -529,12 +556,12 @@ int v4l2_fill_pixfmt(struct v4l2_pix_format *pixfmt, u32 pixelformat,
pixfmt->width = width;
pixfmt->height = height;
pixfmt->pixelformat = pixelformat;
- pixfmt->bytesperline = v4l2_format_plane_stride(info, 0, width);
+ pixfmt->bytesperline = v4l2_format_plane_stride(info, 0, width, 1);
pixfmt->sizeimage = 0;
for (i = 0; i < info->comp_planes; i++)
pixfmt->sizeimage +=
- v4l2_format_plane_size(info, i, width, height);
+ v4l2_format_plane_size(info, i, width, height, 1);
return 0;
}
EXPORT_SYMBOL_GPL(v4l2_fill_pixfmt);
diff --git a/include/media/v4l2-common.h b/include/media/v4l2-common.h
index 401d8506c24b5..edd416178c333 100644
--- a/include/media/v4l2-common.h
+++ b/include/media/v4l2-common.h
@@ -558,6 +558,10 @@ int v4l2_fill_pixfmt(struct v4l2_pix_format *pixfmt, u32 pixelformat,
u32 width, u32 height);
int v4l2_fill_pixfmt_mp(struct v4l2_pix_format_mplane *pixfmt, u32 pixelformat,
u32 width, u32 height);
+/* @stride_alignment is a power of 2 value in bytes */
+int v4l2_fill_pixfmt_mp_aligned(struct v4l2_pix_format_mplane *pixfmt,
+ u32 pixelformat, u32 width, u32 height,
+ u8 stride_alignment);
/**
* v4l2_get_link_freq - Get link rate from transmitter
--
2.53.0
^ permalink raw reply related
* [PATCH v4 01/27] media: dt-bindings: media: rockchip-rga: add rockchip,rk3588-rga3
From: Sven Püschel @ 2026-03-25 14:50 UTC (permalink / raw)
To: Jacob Chen, Ezequiel Garcia, Mauro Carvalho Chehab,
Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-media, linux-rockchip, linux-arm-kernel, linux-kernel,
devicetree, kernel, nicolas, sebastian.reichel, Sven Püschel
In-Reply-To: <20260325-spu-rga3-v4-0-e90ec1c61354@pengutronix.de>
Add a new compatible for the RGA3 (Raster Graphic Acceleration 3)
peripheral found on the RK3588 SoC. Also specify an iommu property,
as the RGA3 contains the generic rockchip iommu. While other versions
also have an iommu, it's usually specific to them.
The RK3588 contains one RGA2-Enhance core (also contained on the RK3399)
and two RGA3 cores. Both feature a similar functionality of scaling,
cropping and rotating of up to two input images into one output image.
Key differences of the RGA3 are:
- supports 10bit YUV output formats
- supports 8x8 tiles and FBCD as inputs and outputs
- supports BT2020 color space conversion
- max output resolution of (8192-64)x(8192-64)
- MMU can map up to 32G DDR RAM
- fully planar formats (3 planes) are not supported
- max scale up/down factor of 8 (RGA2 allows up to 16)
Signed-off-by: Sven Püschel <s.pueschel@pengutronix.de>
---
Changed in v3/v4:
- Dropped Acked-by: Krzysztof Kozlowski due to the added iommus property
and description adjustments.
---
Documentation/devicetree/bindings/media/rockchip-rga.yaml | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/media/rockchip-rga.yaml b/Documentation/devicetree/bindings/media/rockchip-rga.yaml
index ac17cda65191b..7bd92f7336664 100644
--- a/Documentation/devicetree/bindings/media/rockchip-rga.yaml
+++ b/Documentation/devicetree/bindings/media/rockchip-rga.yaml
@@ -9,7 +9,11 @@ title: Rockchip 2D raster graphic acceleration controller (RGA)
description:
RGA is a standalone 2D raster graphic acceleration unit. It accelerates 2D
graphics operations, such as point/line drawing, image scaling, rotation,
- BitBLT, alpha blending and image blur/sharpness.
+ BitBLT, alpha blending and image blur/sharpness. There exist many versions
+ of this unit that differ in the supported inputs/output formats,
+ the attached IOMMU and the supported operations on the input. As some SoCs
+ include multiple RGA units with different versions, a more specific
+ compatible name to differentiate the concrete unit is used for them.
maintainers:
- Jacob Chen <jacob-chen@iotwrt.com>
@@ -20,6 +24,7 @@ properties:
oneOf:
- const: rockchip,rk3288-rga
- const: rockchip,rk3399-rga
+ - const: rockchip,rk3588-rga3
- items:
- enum:
- rockchip,rk3228-rga
@@ -45,6 +50,9 @@ properties:
power-domains:
maxItems: 1
+ iommus:
+ maxItems: 1
+
resets:
maxItems: 3
--
2.53.0
^ permalink raw reply related
* [PATCH v4 15/27] media: rockchip: rga: prepare cmdbuf on streamon
From: Sven Püschel @ 2026-03-25 14:50 UTC (permalink / raw)
To: Jacob Chen, Ezequiel Garcia, Mauro Carvalho Chehab,
Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-media, linux-rockchip, linux-arm-kernel, linux-kernel,
devicetree, kernel, nicolas, sebastian.reichel, Sven Püschel,
Nicolas Dufresne
In-Reply-To: <20260325-spu-rga3-v4-0-e90ec1c61354@pengutronix.de>
Prepare the command buffer on streamon to reuse it's contents instead of
completely writing it for every frame. Due to the stream settings being
fixed after a streamon we only need to replace the source and destination
addresses for each frame. This reduces the amount of CPU and memory
operations done in each frame.
Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Signed-off-by: Sven Püschel <s.pueschel@pengutronix.de>
---
drivers/media/platform/rockchip/rga/rga-hw.c | 13 +++++++++----
drivers/media/platform/rockchip/rga/rga.c | 13 ++++++++++++-
drivers/media/platform/rockchip/rga/rga.h | 1 +
3 files changed, 22 insertions(+), 5 deletions(-)
diff --git a/drivers/media/platform/rockchip/rga/rga-hw.c b/drivers/media/platform/rockchip/rga/rga-hw.c
index 16380be598e4a..dcd540ed3fd5b 100644
--- a/drivers/media/platform/rockchip/rga/rga-hw.c
+++ b/drivers/media/platform/rockchip/rga/rga-hw.c
@@ -417,8 +417,6 @@ static void rga_cmd_set(struct rga_ctx *ctx,
{
struct rockchip_rga *rga = ctx->rga;
- memset(ctx->cmdbuf_virt, 0, RGA_CMDBUF_SIZE * 4);
-
rga_cmd_set_src_addr(ctx, src->dma_desc_pa);
/*
* Due to hardware bug,
@@ -427,11 +425,9 @@ static void rga_cmd_set(struct rga_ctx *ctx,
rga_cmd_set_src1_addr(ctx, dst->dma_desc_pa);
rga_cmd_set_dst_addr(ctx, dst->dma_desc_pa);
- rga_cmd_set_mode(ctx);
rga_cmd_set_src_info(ctx, &src->offset);
rga_cmd_set_dst_info(ctx, &dst->offset);
- rga_cmd_set_trans_info(ctx);
rga_write(rga, RGA_CMD_BASE, ctx->cmdbuf_phy);
@@ -440,6 +436,14 @@ static void rga_cmd_set(struct rga_ctx *ctx,
PAGE_SIZE, DMA_BIDIRECTIONAL);
}
+static void rga_hw_setup_cmdbuf(struct rga_ctx *ctx)
+{
+ memset(ctx->cmdbuf_virt, 0, RGA_CMDBUF_SIZE * 4);
+
+ rga_cmd_set_mode(ctx);
+ rga_cmd_set_trans_info(ctx);
+}
+
static void rga_hw_start(struct rockchip_rga *rga,
struct rga_vb_buffer *src, struct rga_vb_buffer *dst)
{
@@ -582,6 +586,7 @@ const struct rga_hw rga2_hw = {
.max_height = MAX_HEIGHT,
.stride_alignment = 4,
+ .setup_cmdbuf = rga_hw_setup_cmdbuf,
.start = rga_hw_start,
.handle_irq = rga_handle_irq,
.get_version = rga_get_version,
diff --git a/drivers/media/platform/rockchip/rga/rga.c b/drivers/media/platform/rockchip/rga/rga.c
index 16a663aeef8c9..d111b348255e2 100644
--- a/drivers/media/platform/rockchip/rga/rga.c
+++ b/drivers/media/platform/rockchip/rga/rga.c
@@ -568,6 +568,17 @@ static int vidioc_s_selection(struct file *file, void *priv,
return ret;
}
+static int vidioc_streamon(struct file *file, void *priv,
+ enum v4l2_buf_type type)
+{
+ struct rga_ctx *ctx = file_to_rga_ctx(file);
+ const struct rga_hw *hw = ctx->rga->hw;
+
+ hw->setup_cmdbuf(ctx);
+
+ return v4l2_m2m_streamon(file, ctx->fh.m2m_ctx, type);
+}
+
static const struct v4l2_ioctl_ops rga_ioctl_ops = {
.vidioc_querycap = vidioc_querycap,
@@ -592,7 +603,7 @@ static const struct v4l2_ioctl_ops rga_ioctl_ops = {
.vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
.vidioc_unsubscribe_event = v4l2_event_unsubscribe,
- .vidioc_streamon = v4l2_m2m_ioctl_streamon,
+ .vidioc_streamon = vidioc_streamon,
.vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
.vidioc_g_selection = vidioc_g_selection,
diff --git a/drivers/media/platform/rockchip/rga/rga.h b/drivers/media/platform/rockchip/rga/rga.h
index 38518146910a6..c741213710b32 100644
--- a/drivers/media/platform/rockchip/rga/rga.h
+++ b/drivers/media/platform/rockchip/rga/rga.h
@@ -152,6 +152,7 @@ struct rga_hw {
u32 max_width, max_height;
u8 stride_alignment;
+ void (*setup_cmdbuf)(struct rga_ctx *ctx);
void (*start)(struct rockchip_rga *rga,
struct rga_vb_buffer *src, struct rga_vb_buffer *dst);
bool (*handle_irq)(struct rockchip_rga *rga);
--
2.53.0
^ permalink raw reply related
* [PATCH v4 00/27] media: platform: rga: Add RGA3 support
From: Sven Püschel @ 2026-03-25 14:50 UTC (permalink / raw)
To: Jacob Chen, Ezequiel Garcia, Mauro Carvalho Chehab,
Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-media, linux-rockchip, linux-arm-kernel, linux-kernel,
devicetree, kernel, nicolas, sebastian.reichel, Sven Püschel,
Nicolas Dufresne, Michael Olbrich
This series adds support for the Raster Graphic Acceleration 3 (RGA3)
peripheral, which is included in the RK3588 SoC. The RK3588
contains one RGA2-Enhanced core (which is already implemented by the
rockchip rga driver) and two independent RGA3 cores. They feature
a similar functionality of scaling, cropping and rotating of up to two input
images into one output image. Key differences of the RGA3 are:
- supports 10bit YUV output formats
- supports 8x8 tiles and FBCD as inputs and outputs
- supports BT2020 color space conversion
- max output resolution of (8192-64)x(8192-64)
- MMU can map up to 32G DDR RAM
- fully planar formats (3 planes) are not supported
- max scale up/down factor of 8 (RGA2 allows up to 16)
This patch set adds support for one RGA3 core in the existing
rga m2m driver. The feature set of the PR is limited to scaling,
format and color space conversions between common 8bit RGB/YUV formats.
This already allows a practical usage of the RGA3.
During testing it has been noted that the scaling of the hardware is
slightly incorrect. A test conversion of 128x128 RGBA to 256x256 RGBA
causes a slight shift to the bottom right. The shift is suddle, as it seems
that the image is shifted by about 2px down and right and then cropped to
it's final size (probably caused by the source sampling).
The same behavior has been observed when using the vendor driver
with the librga library.
Furthermore comparing the RGA3 conversion with the GStreamer
videoconvertscale element, the chroma-site is different. A quick testing
didn't reveal a chroma-site that creates the same image with the
GStreamer Element. Also when converting from YUV to RGB the RGB values
differ by 1 or 2. This doesn't seem to be a colorspace conversion issue
but rather a slightly different precision on the calculation.
This was tested on a Radxa Rock 5T. Around 80 fps were measured when
scaling and converting from RGBA 480x360 to NV12 3840x2160 in a single
gstreamer pipeline. Format conversions were tested with a single
gstreamer pipeline converting a fixed input to a given input format.
Afterwards it's piped through the RGA3 and the result is converted back
to rgba and compared against a given hash value (generated after
comparing the output manually to the input).
The patchset also fixes the failing v4l2-compliance tests due to the
missing colorimetry propagation from output to capture:
v4l2-compliance 1.32.0, 64 bits, 64-bit time_t
...
Card type : rga2
...
Total for rockchip-rga device /dev/video0: 48, Succeeded: 48, Failed: 0, Warnings: 0
v4l2-compliance 1.32.0, 64 bits, 64-bit time_t
...
Card type : rga3
...
Total for rockchip-rga device /dev/video1: 48, Succeeded: 48, Failed: 0, Warnings: 0
To distinguish the RGA2 core from the RGA3 cores the Card type is set
accordingly. Scheduling operations between both RGA3 cores to double
the possible frame rate might be a future improvement. Until then
additional RGA3 cores are disabled to only provide one video device to
the user space. This prevents a potential ABI breakage when multi core
support is implemented.
The DTS change at the end is just as a preview, as this series targets
media/next. After it's merged the DTS change will be sent as a new
patch not targeting media.
Patch 1 updates the dtb bindings doc to support the RGA3
Patch 2-5 extend v4l2 common functionality
Patch 6-9 are general cleanups
Patch 10-25 prepare the rga driver for the RGA3
Patch 26 adds RGA3 support to the rga driver
Patch 27 dtsi additions for the RGA3
Signed-off-by: Sven Püschel <s.pueschel@pengutronix.de>
---
Changes in v4:
- Add Nicolas to Cc for potential reviews and Sebastian for the nice
RK3588 mainline status table
- Improved single memory plane y stride alignment adjustments
- Adjusted scaling inaccuracy description
- Dropped required iommu property from the binding yaml
- Fixed binding yaml indentation
- Link to v3: https://lore.kernel.org/r/20260127-spu-rga3-v3-0-77b273067beb@pengutronix.de
Changes in v3:
- Add iommus property to the dtb bindings documentation
- Drop interrupt name from the dtsi
- Added v4l2_format_info for missing 2 byte RGB formats
- Fixed incorrect dt node reference in the binding patch commit message
- Removed now unused depth member of rga_frame
- Replaced RGA3 semi planar bool with v4l2_format_info check
- Calculated x_div/y_div variables instead of storing them
- Limited width/height to even values for YUV formats
- Support all 4 CSC modes: BT601L, BT601F, BT709L, BT2020L
- Note slightly incorrect scaling by the hardware
- Fix stride alignment to bytes
- Use early returns in rga-buf init/cleanup
- Fix incorrect devm_clk_bulk_get with devm_clk_bulk_get_all
- Don't enforce max scaling factor in try_fmt (only in s_fmt)
- Merge single register editing RGA3 functions into the other functions
- Link to v2: https://lore.kernel.org/r/20251203-spu-rga3-v2-0-989a67947f71@pengutronix.de
Changes in v2:
- Removed overclocking (assigning higher clock speeds in the dts)
- Disable the second RGA3 core
- Improved RGA3 feature documentation and code comments
- Don't write the whole command buffer in each frame
- Don't announce CIDs for the RGA3 and error out on s_selection
- Check the max scaling factor of 16 (RGA2) and 8 (RGA3)
- Move stride alignment and alpha checking to v4l2 common
- Register the interrupt as shared for an external IOMMU
- Add IOMMU patch as dependency to fix sporadic hangups
- Link to v1: https://lore.kernel.org/r/20251007-spu-rga3-v1-0-36ad85570402@pengutronix.de
---
Michael Olbrich (1):
media: rockchip: rga: share the interrupt when an external iommu is used
Sven Püschel (26):
media: dt-bindings: media: rockchip-rga: add rockchip,rk3588-rga3
media: v4l2-common: sort RGB formats in v4l2_format_info
media: v4l2-common: add missing 1 and 2 byte RGB formats to v4l2_format_info
media: v4l2-common: add has_alpha to v4l2_format_info
media: v4l2-common: add v4l2_fill_pixfmt_mp_aligned helper
media: rockchip: rga: use clk_bulk api
media: rockchip: rga: use stride for offset calculation
media: rockchip: rga: remove redundant rga_frame variables
media: rockchip: rga: announce and sync colorimetry
media: rockchip: rga: move hw specific parts to a dedicated struct
media: rockchip: rga: avoid odd frame sizes for YUV formats
media: rockchip: rga: calculate x_div/y_div using v4l2_format_info
media: rockchip: rga: move cmdbuf to rga_ctx
media: rockchip: rga: align stride to 4 bytes
media: rockchip: rga: prepare cmdbuf on streamon
media: rockchip: rga: check scaling factor
media: rockchip: rga: use card type to specify rga type
media: rockchip: rga: change offset to dma_addresses
media: rockchip: rga: support external iommus
media: rockchip: rga: remove size from rga_frame
media: rockchip: rga: remove stride from rga_frame
media: rockchip: rga: move rga_fmt to rga-hw.h
media: rockchip: rga: add feature flags
media: rockchip: rga: disable multi-core support
media: rockchip: rga: add rga3 support
arm64: dts: rockchip: add rga3 dt nodes
.../devicetree/bindings/media/rockchip-rga.yaml | 10 +-
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 44 ++
drivers/media/platform/rockchip/rga/Makefile | 2 +-
drivers/media/platform/rockchip/rga/rga-buf.c | 61 ++-
drivers/media/platform/rockchip/rga/rga-hw.c | 358 +++++++++----
drivers/media/platform/rockchip/rga/rga-hw.h | 14 +-
drivers/media/platform/rockchip/rga/rga.c | 577 ++++++++++-----------
drivers/media/platform/rockchip/rga/rga.h | 85 +--
drivers/media/platform/rockchip/rga/rga3-hw.c | 507 ++++++++++++++++++
drivers/media/platform/rockchip/rga/rga3-hw.h | 192 +++++++
drivers/media/v4l2-core/v4l2-common.c | 128 +++--
include/media/v4l2-common.h | 6 +
12 files changed, 1480 insertions(+), 504 deletions(-)
---
base-commit: 0e2c4117c3512cf6b8f54c2c3d37564bfa3ccd67
change-id: 20251001-spu-rga3-8a00e018b120
prerequisite-change-id: 20251126-spu-iommudtefix-cd0c5244c74a:v1
prerequisite-patch-id: 10c6c977c0f71400931941b42da73adcaf63e810
Best regards,
--
Sven Püschel <s.pueschel@pengutronix.de>
^ permalink raw reply
* [PATCH v4 16/27] media: rockchip: rga: check scaling factor
From: Sven Püschel @ 2026-03-25 14:50 UTC (permalink / raw)
To: Jacob Chen, Ezequiel Garcia, Mauro Carvalho Chehab,
Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-media, linux-rockchip, linux-arm-kernel, linux-kernel,
devicetree, kernel, nicolas, sebastian.reichel, Sven Püschel
In-Reply-To: <20260325-spu-rga3-v4-0-e90ec1c61354@pengutronix.de>
Check the scaling factor to avoid potential problems. This is relevant
for the upcoming RGA3 support, as it can hang when the scaling factor
is exceeded.
There are two relevant scenarios that have to be considered to protect
against invalid scaling values:
When the output or capture is already streaming, setting the format on
the other side should consider the max scaling factor and clamp it
accordingly. This is only done in the streaming case, as it otherwise
may unintentionally clamp the value when the application sets the first
format (due to a default format on the other side).
When the format is set on both sides first, then the format won't be
corrected by above means. Therefore the second streamon call has to
check the scaling factor and fail otherwise.
As try functions should only be state aware if specified, the scaling
limitation is only done in s_fmt.
Signed-off-by: Sven Püschel <s.pueschel@pengutronix.de>
---
drivers/media/platform/rockchip/rga/rga-hw.c | 1 +
drivers/media/platform/rockchip/rga/rga-hw.h | 1 +
drivers/media/platform/rockchip/rga/rga.c | 47 ++++++++++++++++++++++++++++
drivers/media/platform/rockchip/rga/rga.h | 1 +
4 files changed, 50 insertions(+)
diff --git a/drivers/media/platform/rockchip/rga/rga-hw.c b/drivers/media/platform/rockchip/rga/rga-hw.c
index dcd540ed3fd5b..7a4070665fed7 100644
--- a/drivers/media/platform/rockchip/rga/rga-hw.c
+++ b/drivers/media/platform/rockchip/rga/rga-hw.c
@@ -584,6 +584,7 @@ const struct rga_hw rga2_hw = {
.max_width = MAX_WIDTH,
.min_height = MIN_HEIGHT,
.max_height = MAX_HEIGHT,
+ .max_scaling_factor = MAX_SCALING_FACTOR,
.stride_alignment = 4,
.setup_cmdbuf = rga_hw_setup_cmdbuf,
diff --git a/drivers/media/platform/rockchip/rga/rga-hw.h b/drivers/media/platform/rockchip/rga/rga-hw.h
index f4752aa823051..fffcab0131225 100644
--- a/drivers/media/platform/rockchip/rga/rga-hw.h
+++ b/drivers/media/platform/rockchip/rga/rga-hw.h
@@ -14,6 +14,7 @@
#define MIN_WIDTH 34
#define MIN_HEIGHT 34
+#define MAX_SCALING_FACTOR 16
#define RGA_TIMEOUT 500
diff --git a/drivers/media/platform/rockchip/rga/rga.c b/drivers/media/platform/rockchip/rga/rga.c
index d111b348255e2..75d05c86b1c00 100644
--- a/drivers/media/platform/rockchip/rga/rga.c
+++ b/drivers/media/platform/rockchip/rga/rga.c
@@ -405,10 +405,36 @@ static int vidioc_s_fmt(struct file *file, void *priv, struct v4l2_format *f)
struct v4l2_pix_format_mplane *pix_fmt = &f->fmt.pix_mp;
struct rga_ctx *ctx = file_to_rga_ctx(file);
struct rockchip_rga *rga = ctx->rga;
+ const struct rga_hw *hw = rga->hw;
struct vb2_queue *vq;
struct rga_frame *frm;
int ret = 0;
int i;
+ struct rga_frame *limit_frm = NULL;
+
+ /* Limit before try_fmt to avoid recalculating the stride */
+ if (V4L2_TYPE_IS_OUTPUT(f->type) &&
+ v4l2_m2m_get_dst_vq(ctx->fh.m2m_ctx)->streaming)
+ limit_frm = &ctx->out;
+ if (V4L2_TYPE_IS_CAPTURE(f->type) &&
+ v4l2_m2m_get_src_vq(ctx->fh.m2m_ctx)->streaming)
+ limit_frm = &ctx->in;
+ if (limit_frm) {
+ const struct v4l2_frmsize_stepwise frmsize = {
+ .min_width = DIV_ROUND_UP(limit_frm->pix.width,
+ hw->max_scaling_factor),
+ .max_width =
+ limit_frm->pix.width * hw->max_scaling_factor,
+ .min_height = DIV_ROUND_UP(limit_frm->pix.height,
+ hw->max_scaling_factor),
+ .max_height =
+ limit_frm->pix.height * hw->max_scaling_factor,
+ .step_width = 1,
+ .step_height = 1,
+ };
+ v4l2_apply_frmsize_constraints(&pix_fmt->width,
+ &pix_fmt->height, &frmsize);
+ }
/* Adjust all values accordingly to the hardware capabilities
* and chosen format.
@@ -568,12 +594,33 @@ static int vidioc_s_selection(struct file *file, void *priv,
return ret;
}
+static bool check_scaling(const struct rga_hw *hw, u32 src_size, u32 dst_size)
+{
+ if (src_size < dst_size)
+ return src_size * hw->max_scaling_factor >= dst_size;
+ else
+ return dst_size * hw->max_scaling_factor >= src_size;
+}
+
static int vidioc_streamon(struct file *file, void *priv,
enum v4l2_buf_type type)
{
struct rga_ctx *ctx = file_to_rga_ctx(file);
const struct rga_hw *hw = ctx->rga->hw;
+ if ((V4L2_TYPE_IS_OUTPUT(type) &&
+ v4l2_m2m_get_dst_vq(ctx->fh.m2m_ctx)->streaming) ||
+ (V4L2_TYPE_IS_CAPTURE(type) &&
+ v4l2_m2m_get_src_vq(ctx->fh.m2m_ctx)->streaming)) {
+ /*
+ * As the other side is already streaming,
+ * check that the max scaling factor isn't exceeded.
+ */
+ if (!check_scaling(hw, ctx->in.pix.width, ctx->out.pix.width) ||
+ !check_scaling(hw, ctx->in.pix.height, ctx->out.pix.height))
+ return -EINVAL;
+ }
+
hw->setup_cmdbuf(ctx);
return v4l2_m2m_streamon(file, ctx->fh.m2m_ctx, type);
diff --git a/drivers/media/platform/rockchip/rga/rga.h b/drivers/media/platform/rockchip/rga/rga.h
index c741213710b32..454af283b1694 100644
--- a/drivers/media/platform/rockchip/rga/rga.h
+++ b/drivers/media/platform/rockchip/rga/rga.h
@@ -150,6 +150,7 @@ struct rga_hw {
size_t cmdbuf_size;
u32 min_width, min_height;
u32 max_width, max_height;
+ u8 max_scaling_factor;
u8 stride_alignment;
void (*setup_cmdbuf)(struct rga_ctx *ctx);
--
2.53.0
^ permalink raw reply related
* [PATCH v4 09/27] media: rockchip: rga: announce and sync colorimetry
From: Sven Püschel @ 2026-03-25 14:50 UTC (permalink / raw)
To: Jacob Chen, Ezequiel Garcia, Mauro Carvalho Chehab,
Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-media, linux-rockchip, linux-arm-kernel, linux-kernel,
devicetree, kernel, nicolas, sebastian.reichel, Sven Püschel,
Nicolas Dufresne
In-Reply-To: <20260325-spu-rga3-v4-0-e90ec1c61354@pengutronix.de>
Announce the capability to adjust the quantization and ycbcr_enc on the
capture side and check if the SET_CSC flag is set when the colorimetry
is changed. Furthermore copy the colorimetry from the output to the
capture side to fix the currently failing v4l2-compliance tests, which
expect exactly this behavior.
Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Signed-off-by: Sven Püschel <s.pueschel@pengutronix.de>
---
drivers/media/platform/rockchip/rga/rga.c | 37 +++++++++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/drivers/media/platform/rockchip/rga/rga.c b/drivers/media/platform/rockchip/rga/rga.c
index ca8d8a53dc251..8c34f73d69764 100644
--- a/drivers/media/platform/rockchip/rga/rga.c
+++ b/drivers/media/platform/rockchip/rga/rga.c
@@ -437,6 +437,15 @@ static int vidioc_enum_fmt(struct file *file, void *priv, struct v4l2_fmtdesc *f
fmt = &formats[f->index];
f->pixelformat = fmt->fourcc;
+ if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE &&
+ f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
+ return 0;
+
+ /* allow changing the quantization and xfer func for YUV formats */
+ if (v4l2_is_format_yuv(v4l2_format_info(f->pixelformat)))
+ f->flags |= V4L2_FMT_FLAG_CSC_QUANTIZATION |
+ V4L2_FMT_FLAG_CSC_YCBCR_ENC;
+
return 0;
}
@@ -459,8 +468,25 @@ static int vidioc_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
static int vidioc_try_fmt(struct file *file, void *priv, struct v4l2_format *f)
{
struct v4l2_pix_format_mplane *pix_fmt = &f->fmt.pix_mp;
+ struct rga_ctx *ctx = file_to_rga_ctx(file);
struct rga_fmt *fmt;
+ if (V4L2_TYPE_IS_CAPTURE(f->type)) {
+ const struct rga_frame *frm;
+
+ frm = rga_get_frame(ctx, f->type);
+ if (IS_ERR(frm))
+ return PTR_ERR(frm);
+
+ if (!(pix_fmt->flags & V4L2_PIX_FMT_FLAG_SET_CSC)) {
+ pix_fmt->quantization = frm->pix.quantization;
+ pix_fmt->ycbcr_enc = frm->pix.ycbcr_enc;
+ }
+ /* disallow values not announced in vidioc_enum_fmt */
+ pix_fmt->colorspace = frm->pix.colorspace;
+ pix_fmt->xfer_func = frm->pix.xfer_func;
+ }
+
fmt = rga_fmt_find(pix_fmt->pixelformat);
if (!fmt)
fmt = &formats[0];
@@ -506,6 +532,17 @@ static int vidioc_s_fmt(struct file *file, void *priv, struct v4l2_format *f)
frm->fmt = rga_fmt_find(pix_fmt->pixelformat);
frm->stride = pix_fmt->plane_fmt[0].bytesperline;
+ /*
+ * Copy colorimetry from output to capture as required by the
+ * v4l2-compliance tests
+ */
+ if (V4L2_TYPE_IS_OUTPUT(f->type)) {
+ ctx->out.pix.colorspace = pix_fmt->colorspace;
+ ctx->out.pix.ycbcr_enc = pix_fmt->ycbcr_enc;
+ ctx->out.pix.quantization = pix_fmt->quantization;
+ ctx->out.pix.xfer_func = pix_fmt->xfer_func;
+ }
+
/* Reset crop settings */
frm->crop.left = 0;
frm->crop.top = 0;
--
2.53.0
^ permalink raw reply related
* [PATCH v4 20/27] media: rockchip: rga: share the interrupt when an external iommu is used
From: Sven Püschel @ 2026-03-25 14:50 UTC (permalink / raw)
To: Jacob Chen, Ezequiel Garcia, Mauro Carvalho Chehab,
Heiko Stuebner, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-media, linux-rockchip, linux-arm-kernel, linux-kernel,
devicetree, kernel, nicolas, sebastian.reichel, Sven Püschel,
Michael Olbrich, Nicolas Dufresne
In-Reply-To: <20260325-spu-rga3-v4-0-e90ec1c61354@pengutronix.de>
From: Michael Olbrich <m.olbrich@pengutronix.de>
The RGA3 and the corresponding iommu share the interrupt. So in that
case, request a shared interrupt so that the iommu driver can request
it as well.
Signed-off-by: Michael Olbrich <m.olbrich@pengutronix.de>
Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Signed-off-by: Sven Püschel <s.pueschel@pengutronix.de>
---
drivers/media/platform/rockchip/rga/rga.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/media/platform/rockchip/rga/rga.c b/drivers/media/platform/rockchip/rga/rga.c
index 5bdc8dc51ab68..eb7b211a99e66 100644
--- a/drivers/media/platform/rockchip/rga/rga.c
+++ b/drivers/media/platform/rockchip/rga/rga.c
@@ -761,7 +761,8 @@ static int rga_probe(struct platform_device *pdev)
goto err_put_clk;
}
- ret = devm_request_irq(rga->dev, irq, rga_isr, 0,
+ ret = devm_request_irq(rga->dev, irq, rga_isr,
+ rga_has_internal_iommu(rga) ? 0 : IRQF_SHARED,
dev_name(rga->dev), rga);
if (ret < 0) {
dev_err(rga->dev, "failed to request irq\n");
--
2.53.0
^ permalink raw reply related
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