* [PATCH v2 2/2] regulator: mt6315: Add regulator supplies
From: Chen-Yu Tsai @ 2026-03-26 8:10 UTC (permalink / raw)
To: Mark Brown, Liam Girdwood, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno
Cc: linux-kernel, Chen-Yu Tsai, linux-arm-kernel, linux-mediatek,
devicetree
In-Reply-To: <20260326081050.1115201-1-wenst@chromium.org>
The MT6315 family of PMICs has 4 buck regulators. Each regulator has a
separate supply.
Add these supplies to the driver.
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
---
drivers/regulator/mt6315-regulator.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/regulator/mt6315-regulator.c b/drivers/regulator/mt6315-regulator.c
index d3f93aae0fc5..231e64fb0596 100644
--- a/drivers/regulator/mt6315-regulator.c
+++ b/drivers/regulator/mt6315-regulator.c
@@ -31,10 +31,11 @@ struct mt6315_chip {
struct regmap *regmap;
};
-#define MT_BUCK(_name, _bid, _vsel) \
+#define MT_BUCK(_name, _bid, _supply, _vsel) \
[_bid] = { \
.desc = { \
.name = _name, \
+ .supply_name = _supply, \
.of_match = of_match_ptr(_name), \
.regulators_node = "regulators", \
.ops = &mt6315_volt_range_ops, \
@@ -190,10 +191,10 @@ static const struct regulator_ops mt6315_volt_range_ops = {
};
static const struct mt6315_regulator_info mt6315_regulators[MT6315_VBUCK_MAX] = {
- MT_BUCK("vbuck1", MT6315_VBUCK1, MT6315_BUCK_TOP_ELR0),
- MT_BUCK("vbuck2", MT6315_VBUCK2, MT6315_BUCK_TOP_ELR2),
- MT_BUCK("vbuck3", MT6315_VBUCK3, MT6315_BUCK_TOP_ELR4),
- MT_BUCK("vbuck4", MT6315_VBUCK4, MT6315_BUCK_TOP_ELR6),
+ MT_BUCK("vbuck1", MT6315_VBUCK1, "pvdd1", MT6315_BUCK_TOP_ELR0),
+ MT_BUCK("vbuck2", MT6315_VBUCK2, "pvdd2", MT6315_BUCK_TOP_ELR2),
+ MT_BUCK("vbuck3", MT6315_VBUCK3, "pvdd3", MT6315_BUCK_TOP_ELR4),
+ MT_BUCK("vbuck4", MT6315_VBUCK4, "pvdd4", MT6315_BUCK_TOP_ELR6),
};
static const struct regmap_config mt6315_regmap_config = {
--
2.53.0.1018.g2bb0e51243-goog
^ permalink raw reply related
* [PATCH v2 1/2] regulator: dt-bindings: mt6315: Add regulator supplies
From: Chen-Yu Tsai @ 2026-03-26 8:10 UTC (permalink / raw)
To: Mark Brown, Liam Girdwood, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno
Cc: linux-kernel, Chen-Yu Tsai, linux-arm-kernel, linux-mediatek,
devicetree
In-Reply-To: <20260326081050.1115201-1-wenst@chromium.org>
The MT6315 family of PMICs has 4 buck regulators. Each regulator has a
separate supply.
Add these supplies to the device tree binding.
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
---
Changes since v1:
- Moved *-supply to top level, same level as compatible
---
.../bindings/regulator/mt6315-regulator.yaml | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/Documentation/devicetree/bindings/regulator/mt6315-regulator.yaml b/Documentation/devicetree/bindings/regulator/mt6315-regulator.yaml
index fa6743bb269d..1c63265907f1 100644
--- a/Documentation/devicetree/bindings/regulator/mt6315-regulator.yaml
+++ b/Documentation/devicetree/bindings/regulator/mt6315-regulator.yaml
@@ -25,6 +25,15 @@ properties:
reg:
maxItems: 1
+ pvdd1-supply:
+ description: Supply for regulator vbuck1
+ pvdd2-supply:
+ description: Supply for regulator vbuck2
+ pvdd3-supply:
+ description: Supply for regulator vbuck3
+ pvdd4-supply:
+ description: Supply for regulator vbuck4
+
regulators:
type: object
description: List of regulators and its properties
@@ -49,8 +58,11 @@ examples:
pmic@6 {
compatible = "mediatek,mt6315-regulator";
reg = <0x6 0>;
+ pvdd1-supply = <&pp4200_z2>;
+ pvdd3-supply = <&pp4200_z2>;
regulators {
+
vbuck1 {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1193750>;
--
2.53.0.1018.g2bb0e51243-goog
^ permalink raw reply related
* [PATCH v2 0/2] regulator: mt6315: add regulator supplies
From: Chen-Yu Tsai @ 2026-03-26 8:10 UTC (permalink / raw)
To: Mark Brown, Liam Girdwood, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Matthias Brugger, AngeloGioacchino Del Regno
Cc: linux-kernel, Chen-Yu Tsai, linux-arm-kernel, linux-mediatek,
devicetree
Hi,
This is v2 of the "Add MT6315 regulator supplies" series.
Changes since v1:
- Link to v1: https://lore.kernel.org/all/20260324053030.4077453-1-wenst@chromium.org/
- Move supplies to top level node, at the same level as the compatible
This series is part of a broader collection of regulator related
cleanups for MediaTek Chromebooks. This one covers the MT6315 PMIC.
Patch 1 adds the names of the power supply inputs to the binding.
Patch 2 adds the supply names from the DT binding change in patch 1
to the regulator descriptions in the driver. This patch has a
checkpatch.pl warnings, but I wonder if it's because the context size
for checking complex macros is not large enough.
Device tree changes will be sent separately. The goal is to get the
regulator tree as complete as possible. This includes adding supply
names to other regulator DT bindings, and adding all the supply links
to the existing DTs.
Please have a look.
Thanks
ChenYu
Chen-Yu Tsai (2):
regulator: dt-bindings: mt6315: Add regulator supplies
regulator: mt6315: Add regulator supplies
.../bindings/regulator/mt6315-regulator.yaml | 12 ++++++++++++
drivers/regulator/mt6315-regulator.c | 11 ++++++-----
2 files changed, 18 insertions(+), 5 deletions(-)
--
2.53.0.1018.g2bb0e51243-goog
^ permalink raw reply
* RE: [PATCH v2] net: stmmac: skip VLAN restore when VLAN hash ops are missing
From: Ovidiu Panait @ 2026-03-26 8:07 UTC (permalink / raw)
To: Maxime Chevallier, Michal Piekos, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Maxime Coquelin,
Alexandre Torgue
Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
In-Reply-To: <abb1c779-b306-42f8-b2b1-aa56bfcebe1b@bootlin.com>
Hi,
>
> Hi,
>
> On 21/03/2026 06:38, Michal Piekos wrote:
> > stmmac_vlan_restore() unconditionally calls stmmac_vlan_update() when
> > NETIF_F_VLAN_FEATURES is set. On platforms where priv->hw->vlan (or
> > ->update_vlan_hash) is not provided, stmmac_update_vlan_hash() returns
> > -EINVAL via stmmac_do_void_callback(), resulting in a spurious
> > "Failed to restore VLANs" error even when no VLAN filtering is in use.
> >
> > Check presence of VLAN HW FILTER flags before stmmac_vlan_update().
> >
> > Tested on Orange Pi Zero 3.
> >
> > Fixes: bd7ad51253a7 ("net: stmmac: Fix VLAN HW state restore")
> > Signed-off-by: Michal Piekos <michal.piekos@mmpsystems.pl>
> > ---
> > This patch fixes a noisy "Failed to restore VLANs" message on platforms
> > where stmmac VLAN hash ops are not implemented.
> > stmmac_vlan_restore() calls stmmac_vlan_update() without checking for
> > VLAN hash ops presence which results in -EINVAL.
>
> I've been seeing the same message on socfpga. My two cents on that is
> that this error messages doesn't bring anything to the table anyways.
>
> As Russell explains, it's either triggered when the vlan op isn't
> implemented (the stmmac callback macro stuff turns that into a -EINVAL),
> or when some capabilities arent present. All in all, it's always stuff
> that users can't really do anything about, as it's HW limitations, I
> think we can simply discard this message.
>
> Also, nothing actually checks what stmmac_vlan_restore() returns, so we
> might as well return void ?
>
I think this is the best solution until the VLAN capabilities handling is
cleaned up.
Michal, please let me know if you will be handling this in v3 or I should
send a fix for it.
Thanks,
Ovidiu
> Maxime
>
> > ---
> > Changes in v2:
> > - Replace check for hash ops with check for HW FILTER flags
> > - Link to v1: https://lore.kernel.org/r/20260314-vlan-restore-error-v1-
> 1-4fc6c3e2115f@mmpsystems.pl
> > ---
> > drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> > index 6827c99bde8c..cfc0ce9cec9c 100644
> > --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> > +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> > @@ -6863,7 +6863,8 @@ static int stmmac_vlan_restore(struct stmmac_priv
> *priv)
> > {
> > int ret;
> >
> > - if (!(priv->dev->features & NETIF_F_VLAN_FEATURES))
> > + if (!(priv->dev->features &
> > + (NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_STAG_FILTER)))
> > return 0;
> >
> > if (priv->hw->num_vlan)
> >
> > ---
> > base-commit: 42bddab0563fe67882b2722620a66dd98c8dbf33
> > change-id: 20260314-vlan-restore-error-f8b3a1c7f50a
> >
> > Best regards,
^ permalink raw reply
* Re: [PATCH v5 phy-next 10/27] scsi: ufs: qcom: keep parallel track of PHY power state
From: Vladimir Oltean @ 2026-03-26 8:04 UTC (permalink / raw)
To: Manivannan Sadhasivam
Cc: linux-phy, Vinod Koul, Neil Armstrong, dri-devel, freedreno,
linux-arm-kernel, linux-arm-msm, linux-can, linux-gpio, linux-ide,
linux-kernel, linux-media, linux-pci, linux-renesas-soc,
linux-riscv, linux-rockchip, linux-samsung-soc, linux-scsi,
linux-sunxi, linux-tegra, linux-usb, netdev, spacemit,
UNGLinuxDriver, James E.J. Bottomley, Martin K. Petersen,
Nitin Rawat
In-Reply-To: <20260325115731.genmq2yew2p4dvbs@skbuf>
[-- Attachment #1: Type: text/plain, Size: 1224 bytes --]
On Wed, Mar 25, 2026 at 01:57:31PM +0200, Vladimir Oltean wrote:
> On Wed, Mar 25, 2026 at 05:21:14PM +0530, Manivannan Sadhasivam wrote:
> > I believe I added the power_count check for phy_exit(). But since that got
> > moved, the check becomes no longer necessary.
>
> FYI, the power_count keeps track of the balance of phy_power_on() and
> phy_power_off() calls, whereas it is the init_count keeps track of
> phy_init() and phy_exit() calls. They are only related to the extent
> that you must respect the phy_init() -> phy_power_on() -> phy_power_off()
> -> phy_exit() sequence. But in any case, both should be considered
> PHY-internal fields. The "Order of API calls" section from
> Documentation/driver-api/phy/phy.rst mentions the order that I just
> described above, and consumers should just ensure they follow that.
Ok, so we can close this topic of "checking the power_count not needed"
by linking to the conversation which spun off here:
https://lore.kernel.org/lkml/20260325120122.265973-1-manivannan.sadhasivam@oss.qualcomm.com/
Mani, I spent some more time to figure out what's really going on with
this unexpected phy_power_off() call. Do you think you could
regression-test the patch attached?
Thanks!
[-- Attachment #2: 0001-scsi-ufs-qcom-don-t-call-phy_power_on-before-phy_ini.patch --]
[-- Type: text/x-diff, Size: 7996 bytes --]
From 50dfff3541566eb094e931bd56c80011f29b9817 Mon Sep 17 00:00:00 2001
From: Vladimir Oltean <vladimir.oltean@nxp.com>
Date: Thu, 26 Mar 2026 10:01:55 +0200
Subject: [PATCH] scsi: ufs: qcom: don't call phy_power_on() before phy_init()
The Qualcomm UFS host controller driver violates the Generic PHY API
expectation, documented in section "Order of API calls" from
Documentation/driver-api/phy/phy.rst, and then tries to hide it.
The expectation is that calls must be made in the phy_init() ->
phy_power_on() -> phy_power_off() -> phy_exit() sequence.
What we actually have is:
ufshcd_init()
-> ufshcd_hba_init()
-> ufshcd_setup_clocks(hba, true)
-> ufshcd_vops_setup_clocks(hba, true, POST_CHANGE)
-> ufs_qcom_setup_clocks(hba, true, POST_CHANGE)
-> phy_power_on(phy)
-> ufshcd_variant_hba_init()
-> ufs_qcom_init()
-> ufs_qcom_setup_clocks(hba, true, POST_CHANGE)
-> phy_power_on(phy)
-> ufshcd_hba_enable()
-> ufshcd_vops_hce_enable_notify()
-> ufs_qcom_hce_enable_notify()
-> ufs_qcom_power_up_sequence()
-> if (phy->power_count) phy_power_off(phy)
-> phy_init(phy)
This "works" because the way that the "phy_power_on was called before
phy_init\n" condition is detected in phy-core.c is if the power_count is
positive at the phy_init() call time.
By having that "if (phy->power_count) phy_power_off(phy)" logic, the
ufs-qcom.c technically sidesteps the test, but actually violates the
Generic PHY API even more (calls phy_power_on() *and* phy_power_off()
before phy_init()).
The reason why I stumbled upon this was that I was trying to remove
dereferences of phy->power_count from drivers. This is a PHY-internal
field, and using it from drivers is highly likely to be incorrect, as
this case showcases rather well.
As commit 77d2fa54a945 ("scsi: ufs: qcom : Refactor phy_power_on/off
calls") shows, this driver tries to couple the PHY power state with the
HBA clocks, for power saving reasons. I won't try to change that, I will
just move the phy_init() call earlier, to ufs_qcom_init().
After the phy_init() movement, ufs_qcom_power_up_sequence() should no
longer need to do either phy_init() nor the conditional phy_power_down().
Because the UFS variant operations are not balanced, but the PHY API
calls need to be, create wrappers for all Generic PHY API calls, and
keep a "phy_initialized" and a "phy_powered_on" boolean, so that we call
these only once, and they properly get paired with their phy_exit()/
phy_power_off() counterparts rather than leave the phy->init_count and
phy->power_count elevated.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
---
Cc: "James E.J. Bottomley" <James.Bottomley@HansenPartnership.com>
Cc: Manivannan Sadhasivam <mani@kernel.org>
Cc: "Martin K. Petersen" <martin.petersen@oracle.com>
Cc: Nitin Rawat <quic_nitirawa@quicinc.com>
v5->v6: rewrite after actually understanding the core issue
v4->v5: patch is new
---
drivers/ufs/host/ufs-qcom.c | 104 ++++++++++++++++++++++++++----------
drivers/ufs/host/ufs-qcom.h | 2 +
2 files changed, 79 insertions(+), 27 deletions(-)
diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index 375fd24ba458..ed067247d72a 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -485,11 +485,70 @@ static u32 ufs_qcom_get_hs_gear(struct ufs_hba *hba)
return UFS_HS_G3;
}
+static int ufs_qcom_phy_init(struct ufs_qcom_host *host)
+{
+ struct phy *phy = host->generic_phy;
+ int err;
+
+ if (host->phy_initialized)
+ return 0;
+
+ err = phy_init(phy);
+ if (err)
+ return err;
+
+ host->phy_initialized = true;
+
+ return 0;
+}
+
+static void ufs_qcom_phy_exit(struct ufs_qcom_host *host)
+{
+ if (host->phy_initialized) {
+ phy_exit(host->generic_phy);
+ host->phy_initialized = false;
+ }
+}
+
+static int ufs_qcom_phy_power_on(struct ufs_qcom_host *host)
+{
+ int err;
+
+ if (host->phy_powered_on)
+ return 0;
+
+ err = phy_power_on(host->generic_phy);
+ if (err)
+ return err;
+
+ host->phy_powered_on = true;
+
+ return 0;
+}
+
+static int ufs_qcom_phy_set_gear(struct ufs_qcom_host *host,
+ enum phy_mode mode)
+{
+ return phy_set_mode_ext(host->generic_phy, mode, host->phy_gear);
+}
+
+static int ufs_qcom_phy_calibrate(struct ufs_qcom_host *host)
+{
+ return phy_calibrate(host->generic_phy);
+}
+
+static void ufs_qcom_phy_power_off(struct ufs_qcom_host *host)
+{
+ if (host->phy_powered_on) {
+ phy_power_off(host->generic_phy);
+ host->phy_powered_on = false;
+ }
+}
+
static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
{
struct ufs_qcom_host *host = ufshcd_get_variant(hba);
struct ufs_host_params *host_params = &host->host_params;
- struct phy *phy = host->generic_phy;
enum phy_mode mode;
int ret;
@@ -508,31 +567,22 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
if (ret)
return ret;
- if (phy->power_count)
- phy_power_off(phy);
-
-
- /* phy initialization - calibrate the phy */
- ret = phy_init(phy);
+ ret = ufs_qcom_phy_set_gear(host, mode);
if (ret) {
- dev_err(hba->dev, "%s: phy init failed, ret = %d\n",
+ dev_err(hba->dev, "%s: phy_set_mode_ext() failed, ret = %d\n",
__func__, ret);
- return ret;
- }
-
- ret = phy_set_mode_ext(phy, mode, host->phy_gear);
- if (ret)
goto out_disable_phy;
+ }
/* power on phy - start serdes and phy's power and clocks */
- ret = phy_power_on(phy);
+ ret = ufs_qcom_phy_power_on(host);
if (ret) {
dev_err(hba->dev, "%s: phy power on failed, ret = %d\n",
__func__, ret);
goto out_disable_phy;
}
- ret = phy_calibrate(phy);
+ ret = ufs_qcom_phy_calibrate(host);
if (ret) {
dev_err(hba->dev, "Failed to calibrate PHY: %d\n", ret);
goto out_disable_phy;
@@ -543,7 +593,7 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)
return 0;
out_disable_phy:
- phy_exit(phy);
+ ufs_qcom_phy_power_off(host);
return ret;
}
@@ -1233,7 +1283,6 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
enum ufs_notify_change_status status)
{
struct ufs_qcom_host *host = ufshcd_get_variant(hba);
- struct phy *phy;
int err;
/*
@@ -1244,8 +1293,6 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
if (!host)
return 0;
- phy = host->generic_phy;
-
switch (status) {
case PRE_CHANGE:
if (on) {
@@ -1263,16 +1310,12 @@ static int ufs_qcom_setup_clocks(struct ufs_hba *hba, bool on,
ufs_qcom_dev_ref_clk_ctrl(host, false);
}
- err = phy_power_off(phy);
- if (err) {
- dev_err(hba->dev, "phy power off failed, ret=%d\n", err);
- return err;
- }
+ ufs_qcom_phy_power_off(host);
}
break;
case POST_CHANGE:
if (on) {
- err = phy_power_on(phy);
+ err = ufs_qcom_phy_power_on(host);
if (err) {
dev_err(hba->dev, "phy power on failed, ret = %d\n", err);
return err;
@@ -1441,6 +1484,13 @@ static int ufs_qcom_init(struct ufs_hba *hba)
if (err)
goto out_variant_clear;
+ err = ufs_qcom_phy_init(host);
+ if (err) {
+ dev_err(hba->dev, "%s: phy_init failed, ret = %d\n",
+ __func__, err);
+ goto out_variant_clear;
+ }
+
ufs_qcom_setup_clocks(hba, true, POST_CHANGE);
ufs_qcom_get_default_testbus_cfg(host);
@@ -1466,8 +1516,8 @@ static void ufs_qcom_exit(struct ufs_hba *hba)
struct ufs_qcom_host *host = ufshcd_get_variant(hba);
ufs_qcom_disable_lane_clks(host);
- phy_power_off(host->generic_phy);
- phy_exit(host->generic_phy);
+ ufs_qcom_phy_power_off(host);
+ ufs_qcom_phy_exit(host);
}
static int ufs_qcom_fw_managed_init(struct ufs_hba *hba)
diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h
index 1111ab34da01..33b1b1521916 100644
--- a/drivers/ufs/host/ufs-qcom.h
+++ b/drivers/ufs/host/ufs-qcom.h
@@ -282,6 +282,8 @@ struct ufs_qcom_host {
struct clk_bulk_data *clks;
u32 num_clks;
bool is_lane_clks_enabled;
+ bool phy_initialized;
+ bool phy_powered_on;
struct icc_path *icc_ddr;
struct icc_path *icc_cpu;
--
2.34.1
^ permalink raw reply related
* Clear CLKREQ# override breaks functionality
From: Franz Schnyder @ 2026-03-26 8:00 UTC (permalink / raw)
To: Hongxing Zhu
Cc: Franz Schnyder, linux-pci@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev,
linux-kernel@vger.kernel.org, Francesco Dolcini,
Manivannan Sadhasivam, Frank Li
Hi Richard,
While integrating the `supports-clkreq` DT property on our iMX95-based
SoM, we had failures in our CI on one of the two M.2 PCIe slots on our
development board.
The failing slot uses a card that does not advertise L1 PM substates.
This issue comes from commit a152a90f5390 ("PCI: imx6: Clear CLKREQ#
override if 'supports-clkreq' DT property is available"), which clears
the CLKREQ# override based only on the DT property.
It seems that clearing the CLKREQ# override should happen only
when the driver knows that the downstream device advertises L1 PM
Substates. Otherwise CLKREQ# should remain asserted to keep compatibility
with cards that do not support L1 PM Substates.
Thoughts?
Kind Regards
Franz
^ permalink raw reply
* Re: [PATCH v2 2/5] clk: mediatek: Add mt8173-mfgtop driver
From: Dan Carpenter @ 2026-03-26 7:58 UTC (permalink / raw)
To: oe-kbuild, Chen-Yu Tsai, Stephen Boyd, Matthias Brugger,
AngeloGioacchino Del Regno, Frank Binns, Matt Coster,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann
Cc: lkp, oe-kbuild-all, Icenowy Zheng, Chen-Yu Tsai, David Airlie,
Simona Vetter, linux-clk, devicetree, linux-mediatek, dri-devel,
linux-arm-kernel, linux-kernel
In-Reply-To: <20260325071951.544031-3-wenst@chromium.org>
Hi Chen-Yu,
kernel test robot noticed the following build warnings:
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Chen-Yu-Tsai/dt-bindings-clock-mediatek-Add-mt8173-mfgtop/20260325-202618
base: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
patch link: https://lore.kernel.org/r/20260325071951.544031-3-wenst%40chromium.org
patch subject: [PATCH v2 2/5] clk: mediatek: Add mt8173-mfgtop driver
config: csky-randconfig-r073-20260326 (https://download.01.org/0day-ci/archive/20260326/202603261444.jANdMbNC-lkp@intel.com/config)
compiler: csky-linux-gcc (GCC) 11.5.0
smatch: v0.5.0-9004-gb810ac53
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Reported-by: Dan Carpenter <dan.carpenter@linaro.org>
| Closes: https://lore.kernel.org/r/202603261444.jANdMbNC-lkp@intel.com/
smatch warnings:
drivers/clk/mediatek/clk-mt8173-mfgtop.c:163 clk_mt8173_mfgtop_probe() warn: missing error code 'ret'
vim +/ret +163 drivers/clk/mediatek/clk-mt8173-mfgtop.c
edc2074329e271 Chen-Yu Tsai 2026-03-25 153 ret = mtk_clk_register_gates(dev, node, mfg_clks, ARRAY_SIZE(mfg_clks),
edc2074329e271 Chen-Yu Tsai 2026-03-25 154 data->clk_data);
edc2074329e271 Chen-Yu Tsai 2026-03-25 155 if (ret) {
edc2074329e271 Chen-Yu Tsai 2026-03-25 156 dev_err_probe(dev, ret, "Failed to register clock gates\n");
edc2074329e271 Chen-Yu Tsai 2026-03-25 157 goto put_pm_runtime;
edc2074329e271 Chen-Yu Tsai 2026-03-25 158 }
edc2074329e271 Chen-Yu Tsai 2026-03-25 159
edc2074329e271 Chen-Yu Tsai 2026-03-25 160 data->clk_26m = clk_hw_get_clk(data->clk_data->hws[CLK_MFG_26M], "26m");
edc2074329e271 Chen-Yu Tsai 2026-03-25 161 if (IS_ERR(data->clk_26m)) {
edc2074329e271 Chen-Yu Tsai 2026-03-25 162 dev_err_probe(dev, PTR_ERR(data->clk_26m), "Failed to get 26 MHz clock\n");
edc2074329e271 Chen-Yu Tsai 2026-03-25 @163 goto unregister_clks;
ret = dev_err_probe() or ret = PTR_ERR(data->clk_26m)?
edc2074329e271 Chen-Yu Tsai 2026-03-25 164 }
edc2074329e271 Chen-Yu Tsai 2026-03-25 165
edc2074329e271 Chen-Yu Tsai 2026-03-25 166 ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, data->clk_data);
edc2074329e271 Chen-Yu Tsai 2026-03-25 167 if (ret) {
edc2074329e271 Chen-Yu Tsai 2026-03-25 168 dev_err_probe(dev, ret, "Failed to add clk OF provider\n");
edc2074329e271 Chen-Yu Tsai 2026-03-25 169 goto put_26m_clk;
edc2074329e271 Chen-Yu Tsai 2026-03-25 170 }
edc2074329e271 Chen-Yu Tsai 2026-03-25 171
edc2074329e271 Chen-Yu Tsai 2026-03-25 172 data->genpd.name = "mfg-top";
edc2074329e271 Chen-Yu Tsai 2026-03-25 173 data->genpd.power_on = clk_mt8173_mfgtop_power_on;
edc2074329e271 Chen-Yu Tsai 2026-03-25 174 data->genpd.power_off = clk_mt8173_mfgtop_power_off;
edc2074329e271 Chen-Yu Tsai 2026-03-25 175 ret = pm_genpd_init(&data->genpd, NULL, true);
edc2074329e271 Chen-Yu Tsai 2026-03-25 176 if (ret) {
edc2074329e271 Chen-Yu Tsai 2026-03-25 177 dev_err_probe(dev, ret, "Failed to add power domain\n");
edc2074329e271 Chen-Yu Tsai 2026-03-25 178 goto del_clk_provider;
edc2074329e271 Chen-Yu Tsai 2026-03-25 179 }
edc2074329e271 Chen-Yu Tsai 2026-03-25 180
edc2074329e271 Chen-Yu Tsai 2026-03-25 181 ret = of_genpd_add_provider_simple(node, &data->genpd);
edc2074329e271 Chen-Yu Tsai 2026-03-25 182 if (ret) {
edc2074329e271 Chen-Yu Tsai 2026-03-25 183 dev_err_probe(dev, ret, "Failed to add power domain OF provider\n");
edc2074329e271 Chen-Yu Tsai 2026-03-25 184 goto remove_pd;
edc2074329e271 Chen-Yu Tsai 2026-03-25 185 }
edc2074329e271 Chen-Yu Tsai 2026-03-25 186
edc2074329e271 Chen-Yu Tsai 2026-03-25 187 ret = of_genpd_add_subdomain(&data->parent_pd, &data->child_pd);
edc2074329e271 Chen-Yu Tsai 2026-03-25 188 if (ret) {
edc2074329e271 Chen-Yu Tsai 2026-03-25 189 dev_err_probe(dev, ret, "Failed to link PM domains\n");
edc2074329e271 Chen-Yu Tsai 2026-03-25 190 goto del_pd_provider;
edc2074329e271 Chen-Yu Tsai 2026-03-25 191 }
edc2074329e271 Chen-Yu Tsai 2026-03-25 192
edc2074329e271 Chen-Yu Tsai 2026-03-25 193 pm_runtime_put(dev);
edc2074329e271 Chen-Yu Tsai 2026-03-25 194 return 0;
edc2074329e271 Chen-Yu Tsai 2026-03-25 195
edc2074329e271 Chen-Yu Tsai 2026-03-25 196 del_pd_provider:
edc2074329e271 Chen-Yu Tsai 2026-03-25 197 of_genpd_del_provider(node);
edc2074329e271 Chen-Yu Tsai 2026-03-25 198 remove_pd:
edc2074329e271 Chen-Yu Tsai 2026-03-25 199 pm_genpd_remove(&data->genpd);
edc2074329e271 Chen-Yu Tsai 2026-03-25 200 del_clk_provider:
edc2074329e271 Chen-Yu Tsai 2026-03-25 201 of_clk_del_provider(node);
edc2074329e271 Chen-Yu Tsai 2026-03-25 202 put_26m_clk:
edc2074329e271 Chen-Yu Tsai 2026-03-25 203 clk_put(data->clk_26m);
edc2074329e271 Chen-Yu Tsai 2026-03-25 204 unregister_clks:
edc2074329e271 Chen-Yu Tsai 2026-03-25 205 mtk_clk_unregister_gates(mfg_clks, ARRAY_SIZE(mfg_clks), data->clk_data);
edc2074329e271 Chen-Yu Tsai 2026-03-25 206 put_pm_runtime:
edc2074329e271 Chen-Yu Tsai 2026-03-25 207 pm_runtime_put(dev);
edc2074329e271 Chen-Yu Tsai 2026-03-25 208 put_of_node:
edc2074329e271 Chen-Yu Tsai 2026-03-25 209 of_node_put(data->parent_pd.np);
edc2074329e271 Chen-Yu Tsai 2026-03-25 210 return ret;
edc2074329e271 Chen-Yu Tsai 2026-03-25 211 }
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply
* [PATCH v2 5/5] arm64: dts: freescale: add i.MX91 9x9 QSB basic support
From: Joy Zou @ 2026-03-26 7:51 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Ye Li, Jacky Bai, Peng Fan
Cc: devicetree, linux-kernel, imx, linux-arm-kernel, Joy Zou,
Daniel Baluta
In-Reply-To: <20260326-b4-imx91-qsb-dts-v2-0-b991b81639e6@nxp.com>
Add i.MX91 9x9 Quick Start Board support.
- Enable ADC1.
- Enable lpuart1.
- Enable network eqos.
- Enable I2C bus and children nodes under I2C bus.
- Enable USB and related nodes.
- Enable uSDHC1 and uSDHC2.
- Enable Watchdog3.
The board description can refer to the following link:
https://www.nxp.com/design/design-center/development-boards-and-designs/IMX91QSB
Signed-off-by: Joy Zou <joy.zou@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
---
Changes in v2:
1. Correct GPIO pin number typo: <&gpio3 00 GPIO_ACTIVE_LOW> to <&gpio3 0 GPIO_ACTIVE_LOW>.
2. Add whitespace before brace in BUCK4 node.
3. Remove one level of indentation for rtc node.
4. Remove clock-frequency property from mdio node.
5. add Reviewed-by tag.
---
arch/arm64/boot/dts/freescale/Makefile | 1 +
arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts | 425 ++++++++++++++++++++++++
2 files changed, 426 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index bae24b53bce6d33a6929d7c6b3f8c1a70911c5d0..382094fa220ab6c388d182be179a82eefed74b45 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -412,6 +412,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqp-mba8xx.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqps-mb-smarc-2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8ulp-9x9-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx91-9x9-qsb.dtb
dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-frdm.dtb
dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-frdm-s.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts b/arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts
new file mode 100644
index 0000000000000000000000000000000000000000..1239bbf579da44ab3f4be2dc566c53a1e5db6c05
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts
@@ -0,0 +1,425 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2026 NXP
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/usb/pd.h>
+#include "imx91.dtsi"
+
+/ {
+ compatible = "fsl,imx91-9x9-qsb", "fsl,imx91";
+ model = "NXP i.MX91 9x9 Quick Start Board";
+
+ aliases {
+ ethernet0 = &fec;
+ ethernet1 = &eqos;
+ gpio0 = &gpio1;
+ gpio1 = &gpio2;
+ gpio2 = &gpio3;
+ i2c0 = &lpi2c1;
+ i2c1 = &lpi2c2;
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc2;
+ rtc0 = &bbnsm_rtc;
+ serial0 = &lpuart1;
+ };
+
+ chosen {
+ stdout-path = &lpuart1;
+ };
+
+ reg_vref_1v8: regulator-adc-vref {
+ compatible = "regulator-fixed";
+ regulator-name = "vref_1v8";
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ };
+
+ reg_usdhc2_vmmc: regulator-usdhc2 {
+ compatible = "regulator-fixed";
+ regulator-name = "VSD_3V3";
+ off-on-delay-us = <12000>;
+ pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+ pinctrl-names = "default";
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reserved-memory {
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0 0x10000000>;
+ linux,cma-default;
+ };
+ };
+};
+
+&adc1 {
+ vref-supply = <®_vref_1v8>;
+ status = "okay";
+};
+
+&eqos {
+ phy-handle = <ðphy1>;
+ phy-mode = "rgmii-id";
+ pinctrl-0 = <&pinctrl_eqos>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <5000000>;
+
+ ethphy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ realtek,clkout-disable;
+ };
+ };
+};
+
+&iomuxc {
+ pinctrl_eqos: eqosgrp {
+ fsl,pins = <
+ MX91_PAD_ENET1_MDC__ENET1_MDC 0x57e
+ MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e
+ MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
+ MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
+ MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
+ MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
+ MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x5fe
+ MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
+ MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e
+ MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x57e
+ MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e
+ MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e
+ MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe
+ MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e
+ >;
+ };
+
+ pinctrl_lpi2c1: lpi2c1grp {
+ fsl,pins = <
+ MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e
+ MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e
+ >;
+ };
+
+ pinctrl_lpi2c2: lpi2c2grp {
+ fsl,pins = <
+ MX91_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e
+ MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e
+ >;
+ };
+
+ pinctrl_pcal6524: pcal6524grp {
+ fsl,pins = <
+ MX91_PAD_CCM_CLKO1__GPIO3_IO26 0x31e
+ >;
+ };
+
+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+ fsl,pins = <
+ MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x31e
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX91_PAD_UART1_RXD__LPUART1_RX 0x31e
+ MX91_PAD_UART1_TXD__LPUART1_TX 0x31e
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX91_PAD_SD1_CLK__USDHC1_CLK 0x1582
+ MX91_PAD_SD1_CMD__USDHC1_CMD 0x1382
+ MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x1382
+ MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x1382
+ MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x1382
+ MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x1382
+ MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x1382
+ MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x1382
+ MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x1382
+ MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x1382
+ MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x1582
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+ fsl,pins = <
+ MX91_PAD_SD1_CLK__USDHC1_CLK 0x158e
+ MX91_PAD_SD1_CMD__USDHC1_CMD 0x138e
+ MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e
+ MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x138e
+ MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x138e
+ MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x138e
+ MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x138e
+ MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x138e
+ MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x138e
+ MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x138e
+ MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x158e
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+ fsl,pins = <
+ MX91_PAD_SD1_CLK__USDHC1_CLK 0x15fe
+ MX91_PAD_SD1_CMD__USDHC1_CMD 0x13fe
+ MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
+ MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
+ MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
+ MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
+ MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
+ MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
+ MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
+ MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
+ MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
+ >;
+ };
+
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ fsl,pins = <
+ MX91_PAD_SD2_CD_B__GPIO3_IO0 0x31e
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX91_PAD_SD2_CLK__USDHC2_CLK 0x1582
+ MX91_PAD_SD2_CMD__USDHC2_CMD 0x1382
+ MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x1382
+ MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x1382
+ MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x1382
+ MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x1382
+ MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e
+ MX91_PAD_SD2_CMD__USDHC2_CMD 0x138e
+ MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x138e
+ MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e
+ MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x138e
+ MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x138e
+ MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ MX91_PAD_SD2_CLK__USDHC2_CLK 0x15fe
+ MX91_PAD_SD2_CMD__USDHC2_CMD 0x13fe
+ MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe
+ MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe
+ MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe
+ MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe
+ MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e
+ >;
+ };
+};
+
+&lpi2c1 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&pinctrl_lpi2c1>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ p3t1085: temperature-sensor@48 {
+ compatible = "nxp,p3t1085";
+ reg = <0x48>;
+ };
+
+ ptn5110: tcpc@50 {
+ compatible = "nxp,ptn5110", "tcpci";
+ reg = <0x50>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
+
+ typec1_con: connector {
+ compatible = "usb-c-connector";
+ data-role = "dual";
+ label = "USB-C";
+ op-sink-microwatt = <15000000>;
+ power-role = "dual";
+ self-powered;
+ sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
+ PDO_VAR(5000, 20000, 3000)>;
+ source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+ try-power-role = "sink";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ typec1_dr_sw: endpoint {
+ remote-endpoint = <&usb1_drd_sw>;
+ };
+ };
+ };
+ };
+ };
+
+ pcf2131: rtc@53 {
+ compatible = "nxp,pcf2131";
+ reg = <0x53>;
+ interrupt-parent = <&pcal6524>;
+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+ };
+};
+
+&lpi2c2 {
+ clock-frequency = <400000>;
+ pinctrl-0 = <&pinctrl_lpi2c2>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ pcal6524: gpio@22 {
+ compatible = "nxp,pcal6524";
+ reg = <0x22>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ interrupt-parent = <&gpio3>;
+ interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ pinctrl-0 = <&pinctrl_pcal6524>;
+ pinctrl-names = "default";
+ };
+
+ pmic@32 {
+ compatible = "nxp,pf9453";
+ reg = <0x32>;
+ interrupt-parent = <&pcal6524>;
+ interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
+
+ regulators {
+ buck1: BUCK1 {
+ regulator-name = "BUCK1";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1140000>;
+ regulator-min-microvolt = <1060000>;
+ };
+
+ buck2: BUCK2 {
+ regulator-name = "BUCK2";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <900000>;
+ regulator-min-microvolt = <610000>;
+ regulator-ramp-delay = <12500>;
+ };
+
+ buck3: BUCK3 {
+ regulator-name = "BUCK3";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3450000>;
+ regulator-min-microvolt = <1650000>;
+ };
+
+ buck4: BUCK4 {
+ regulator-name = "BUCK4";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3450000>;
+ regulator-min-microvolt = <1650000>;
+ };
+
+ ldo1: LDO1 {
+ regulator-name = "LDO1";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <1650000>;
+ };
+
+ ldo2: LDO2 {
+ regulator-name = "LDO2";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1890000>;
+ regulator-min-microvolt = <760000>;
+ };
+
+ ldo_snvs: LDO-SNVS {
+ regulator-name = "LDO-SNVS";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-max-microvolt = <1950000>;
+ regulator-min-microvolt = <1650000>;
+ };
+ };
+ };
+};
+
+&lpuart1 {
+ pinctrl-0 = <&pinctrl_uart1>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&usbotg1 {
+ adp-disable;
+ disable-over-current;
+ dr_mode = "otg";
+ hnp-disable;
+ srp-disable;
+ usb-role-switch;
+ samsung,picophy-dc-vol-level-adjust = <7>;
+ samsung,picophy-pre-emp-curr-control = <3>;
+ status = "okay";
+
+ port {
+ usb1_drd_sw: endpoint {
+ remote-endpoint = <&typec1_dr_sw>;
+ };
+ };
+};
+
+&usdhc1 {
+ bus-width = <8>;
+ non-removable;
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ fsl,tuning-step = <1>;
+ status = "okay";
+};
+
+&usdhc2 {
+ bus-width = <4>;
+ cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
+ no-mmc;
+ no-sdio;
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ vmmc-supply = <®_usdhc2_vmmc>;
+ fsl,tuning-step = <1>;
+ status = "okay";
+};
+
+&wdog3 {
+ fsl,ext-reset-output;
+ status = "okay";
+};
--
2.37.1
^ permalink raw reply related
* [PATCH v2 4/5] arm64: dts: imx93-9x9-qsb: remove unused property clock-frequency from mdio node
From: Joy Zou @ 2026-03-26 7:51 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Ye Li, Jacky Bai, Peng Fan
Cc: devicetree, linux-kernel, imx, linux-arm-kernel, Joy Zou
In-Reply-To: <20260326-b4-imx91-qsb-dts-v2-0-b991b81639e6@nxp.com>
The clock-frequency property is not implemented. Remove it to clean up the
device tree.
Signed-off-by: Joy Zou <joy.zou@nxp.com>
---
arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts b/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts
index 7bcebd702106343bde0f084dec6c38d53a985357..01c11c517986a0642d0fedf79a11889c2bf23ae5 100644
--- a/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts
+++ b/arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts
@@ -228,7 +228,6 @@ mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
- clock-frequency = <5000000>;
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
--
2.37.1
^ permalink raw reply related
* [PATCH v2 3/5] arm64: dts: imx93-11x11-evk: remove unused property clock-frequency from mdio node
From: Joy Zou @ 2026-03-26 7:51 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Ye Li, Jacky Bai, Peng Fan
Cc: devicetree, linux-kernel, imx, linux-arm-kernel, Joy Zou
In-Reply-To: <20260326-b4-imx91-qsb-dts-v2-0-b991b81639e6@nxp.com>
The clock-frequency property is not implemented. Remove it to clean up the
device tree.
Signed-off-by: Joy Zou <joy.zou@nxp.com>
---
arch/arm64/boot/dts/freescale/imx93-11x11-evk-common.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk-common.dtsi b/arch/arm64/boot/dts/freescale/imx93-11x11-evk-common.dtsi
index 7d3fc4ad7b8b7cf213e8ec977589509a7419a04b..f48e7947cf647355c57c82a42a5c0807f53f3a55 100644
--- a/arch/arm64/boot/dts/freescale/imx93-11x11-evk-common.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk-common.dtsi
@@ -187,7 +187,6 @@ mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
- clock-frequency = <5000000>;
ethphy1: ethernet-phy@1 {
reg = <1>;
--
2.37.1
^ permalink raw reply related
* [PATCH v2 2/5] arm64: dts: imx91-11x11-evk: remove unused property clock-frequency from mdio node
From: Joy Zou @ 2026-03-26 7:51 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Ye Li, Jacky Bai, Peng Fan
Cc: devicetree, linux-kernel, imx, linux-arm-kernel, Joy Zou
In-Reply-To: <20260326-b4-imx91-qsb-dts-v2-0-b991b81639e6@nxp.com>
The clock-frequency property is not implemented. Remove it to clean up the
device tree.
Signed-off-by: Joy Zou <joy.zou@nxp.com>
---
arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts
index c083b97476a5155b45ead382da22f8bcfd5a4c79..de524f1921de808ee29895852fcbea37565a7e07 100644
--- a/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts
@@ -195,7 +195,6 @@ mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
- clock-frequency = <5000000>;
ethphy1: ethernet-phy@1 {
reg = <1>;
--
2.37.1
^ permalink raw reply related
* [PATCH v2 1/5] dt-bindings: arm: fsl: add i.MX91 9x9 QSB board
From: Joy Zou @ 2026-03-26 7:51 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Ye Li, Jacky Bai, Peng Fan
Cc: devicetree, linux-kernel, imx, linux-arm-kernel, Joy Zou,
Daniel Baluta, Conor Dooley
In-Reply-To: <20260326-b4-imx91-qsb-dts-v2-0-b991b81639e6@nxp.com>
Add compatible string for i.MX91 9x9 Quick Start Board.
Signed-off-by: Joy Zou <joy.zou@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
Changes in v2:
1. add Reviewed-by and Acked-by tag.
---
Documentation/devicetree/bindings/arm/fsl.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index da2be7114f6417317b3bc904cc5c1953e64e21ea..6a94e0201f704f87df8b5bae0fcae9b2d9133f91 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -1458,6 +1458,7 @@ properties:
- description: i.MX91 based Boards
items:
- enum:
+ - fsl,imx91-9x9-qsb # i.MX91 9x9 QSB Board
- fsl,imx91-11x11-evk # i.MX91 11x11 EVK Board
- fsl,imx91-11x11-frdm # FRDM i.MX91 Development Board
- fsl,imx91-11x11-frdm-s # FRDM i.MX91S Development Board
--
2.37.1
^ permalink raw reply related
* [PATCH v2 0/5] Add i.MX91 9x9 QSB basic support
From: Joy Zou @ 2026-03-26 7:51 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Ye Li, Jacky Bai, Peng Fan
Cc: devicetree, linux-kernel, imx, linux-arm-kernel, Joy Zou,
Daniel Baluta, Conor Dooley
Add i.MX91 9x9 QSB basic support.
Signed-off-by: Joy Zou <joy.zou@nxp.com>
---
Changes in v2:
- Add three new patches to remove the clock-frequency property from mdio node.
- Remove the clock-frequency property from mdio node for patch #5.
- Correct GPIO pin number typo: <&gpio3 00 GPIO_ACTIVE_LOW> to <&gpio3 0 GPIO_ACTIVE_LOW> for patch #5.
- Add whitespace before brace in BUCK4 node for patch #5.
- Remove one level of indentation for rtc node for patch #5.
- Add Acked-by and Reviewed-by tag for patch #1.
- Add Reviewed-by tag for patch #5.
- Link to v1: https://lore.kernel.org/r/20260319-b4-imx91-qsb-dts-v1-0-2eedc01d8af0@nxp.com
---
Joy Zou (5):
dt-bindings: arm: fsl: add i.MX91 9x9 QSB board
arm64: dts: imx91-11x11-evk: remove unused property clock-frequency from mdio node
arm64: dts: imx93-11x11-evk: remove unused property clock-frequency from mdio node
arm64: dts: imx93-9x9-qsb: remove unused property clock-frequency from mdio node
arm64: dts: freescale: add i.MX91 9x9 QSB basic support
Documentation/devicetree/bindings/arm/fsl.yaml | 1 +
arch/arm64/boot/dts/freescale/Makefile | 1 +
arch/arm64/boot/dts/freescale/imx91-11x11-evk.dts | 1 -
arch/arm64/boot/dts/freescale/imx91-9x9-qsb.dts | 425 +++++++++++++++++++++
.../boot/dts/freescale/imx93-11x11-evk-common.dtsi | 1 -
arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts | 1 -
6 files changed, 427 insertions(+), 3 deletions(-)
---
base-commit: 8e42d2514a7e8eb8d740d0ba82339dd6c0b6463f
change-id: 20260319-b4-imx91-qsb-dts-ce089fb28353
Best regards,
--
Joy Zou <joy.zou@nxp.com>
^ permalink raw reply
* Re: [PATCH v2] net: stmmac: skip VLAN restore when VLAN hash ops are missing
From: Maxime Chevallier @ 2026-03-26 7:49 UTC (permalink / raw)
To: Michal Piekos, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Maxime Coquelin, Alexandre Torgue,
Ovidiu Panait
Cc: netdev, linux-stm32, linux-arm-kernel, linux-kernel
In-Reply-To: <20260321-vlan-restore-error-v2-1-45cf56a5223d@mmpsystems.pl>
Hi,
On 21/03/2026 06:38, Michal Piekos wrote:
> stmmac_vlan_restore() unconditionally calls stmmac_vlan_update() when
> NETIF_F_VLAN_FEATURES is set. On platforms where priv->hw->vlan (or
> ->update_vlan_hash) is not provided, stmmac_update_vlan_hash() returns
> -EINVAL via stmmac_do_void_callback(), resulting in a spurious
> "Failed to restore VLANs" error even when no VLAN filtering is in use.
>
> Check presence of VLAN HW FILTER flags before stmmac_vlan_update().
>
> Tested on Orange Pi Zero 3.
>
> Fixes: bd7ad51253a7 ("net: stmmac: Fix VLAN HW state restore")
> Signed-off-by: Michal Piekos <michal.piekos@mmpsystems.pl>
> ---
> This patch fixes a noisy "Failed to restore VLANs" message on platforms
> where stmmac VLAN hash ops are not implemented.
> stmmac_vlan_restore() calls stmmac_vlan_update() without checking for
> VLAN hash ops presence which results in -EINVAL.
I've been seeing the same message on socfpga. My two cents on that is
that this error messages doesn't bring anything to the table anyways.
As Russell explains, it's either triggered when the vlan op isn't
implemented (the stmmac callback macro stuff turns that into a -EINVAL),
or when some capabilities arent present. All in all, it's always stuff
that users can't really do anything about, as it's HW limitations, I
think we can simply discard this message.
Also, nothing actually checks what stmmac_vlan_restore() returns, so we
might as well return void ?
Maxime
> ---
> Changes in v2:
> - Replace check for hash ops with check for HW FILTER flags
> - Link to v1: https://lore.kernel.org/r/20260314-vlan-restore-error-v1-1-4fc6c3e2115f@mmpsystems.pl
> ---
> drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> index 6827c99bde8c..cfc0ce9cec9c 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> @@ -6863,7 +6863,8 @@ static int stmmac_vlan_restore(struct stmmac_priv *priv)
> {
> int ret;
>
> - if (!(priv->dev->features & NETIF_F_VLAN_FEATURES))
> + if (!(priv->dev->features &
> + (NETIF_F_HW_VLAN_CTAG_FILTER | NETIF_F_HW_VLAN_STAG_FILTER)))
> return 0;
>
> if (priv->hw->num_vlan)
>
> ---
> base-commit: 42bddab0563fe67882b2722620a66dd98c8dbf33
> change-id: 20260314-vlan-restore-error-f8b3a1c7f50a
>
> Best regards,
^ permalink raw reply
* Re: [PATCH 1/1] arm64: defconfig: Enable options for CIX Sky1 SoC
From: Yunseong Kim @ 2026-03-26 7:38 UTC (permalink / raw)
To: Krzysztof Kozlowski, Peter Chen, arnd
Cc: geert+renesas, linux-kernel, linux-arm-kernel
In-Reply-To: <c2127a57-3ced-4c0c-a7df-c052cd5dac7e@oss.qualcomm.com>
Hi Krzysztof,
On 3/26/26 4:14 PM, Krzysztof Kozlowski wrote:
> On 26/03/2026 04:39, Peter Chen wrote:
>> Enable pinctrl, gpio, pcie and hda audio support.
>
> Why?
This configuration is required for GPIO functionality on the Radxa Orion O6.
The following issue has been reported on the Debian kernel mailing list:
https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=1131772
> Please search within similar patches for explanation how why this is not
> enough and what should be here.
>
> Best regards,
> Krzysztof
Thank you!
Best regards,
Yunseong Kim
^ permalink raw reply
* [PATCH v2 12/12] arm64: dts: imx8mp-data-modul-edm-sbc: Correct PAD settings for PMIC_nINT
From: Peng Fan (OSS) @ 2026-03-26 7:28 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Laurent Pinchart, Shawn Guo, Daniel Scally, Marco Felsch,
Gilles Talis, Viorel Suman, Shengjiu Wang, Jagan Teki, Manoj Sai,
Matteo Lisi, Ray Chang, Richard Hu, Heiko Schocher, Martyn Welch,
Josua Mayer, Goran Rađenović, Börge Strümpfel,
Christoph Niedermaier, Marek Vasut
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, kernel, Peng Fan
In-Reply-To: <20260326-imx8mp-dts-fix-v2-v2-0-62c4ce727448@nxp.com>
From: Peng Fan <peng.fan@nxp.com>
PMIC_nINT is low level triggered, but the current PAD settings is
PE=0,PUE=0,FSEL_1_FAST_SLEW_RATE=1,SION=1. So PAD needs to be configured
as PULL UP with PULL Enable, no need SION. Correct it.
Fixes: 562d222f23f0f ("arm64: dts: imx8mp: Add support for Data Modul i.MX8M Plus eDM SBC")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts
index 7e46537a22a01d6e66305394edcddd73fdf660da..cb28cf1cdd23fa945906e6f26f6036ceca496c5a 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts
@@ -1001,7 +1001,7 @@ MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_PDM_BIT_STREAM00 0x0
pinctrl_pmic: pmic-grp {
fsl,pins = <
/* PMIC_nINT */
- MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x40000090
+ MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0
>;
};
--
2.37.1
^ permalink raw reply related
* [PATCH v2 11/12] arm64: dts: imx8mp-dhcom-som: Correct PAD settings for PMIC_nINT
From: Peng Fan (OSS) @ 2026-03-26 7:28 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Laurent Pinchart, Shawn Guo, Daniel Scally, Marco Felsch,
Gilles Talis, Viorel Suman, Shengjiu Wang, Jagan Teki, Manoj Sai,
Matteo Lisi, Ray Chang, Richard Hu, Heiko Schocher, Martyn Welch,
Josua Mayer, Goran Rađenović, Börge Strümpfel,
Christoph Niedermaier, Marek Vasut
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, kernel, Peng Fan
In-Reply-To: <20260326-imx8mp-dts-fix-v2-v2-0-62c4ce727448@nxp.com>
From: Peng Fan <peng.fan@nxp.com>
PMIC_nINT is low level triggered, but the current PAD settings is
PE=0,PUE=0,FSEL_1_FAST_SLEW_RATE=1,SION=1. So PAD needs to be configured
as PULL UP with PULL Enable, no need SION. Correct it.
Fixes: 8d6712695bc8e ("arm64: dts: imx8mp: Add support for DH electronics i.MX8M Plus DHCOM and PDK2")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi
index f8303b7e2bd22b9529d5f3063894d1cdd5556d59..0a6a60670f762f1400653d1e7d0f4c0fcaf6bcd4 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi
@@ -989,7 +989,7 @@ MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x22
pinctrl_pmic: dhcom-pmic-grp {
fsl,pins = <
/* PMIC_nINT */
- MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x40000090
+ MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0
>;
};
--
2.37.1
^ permalink raw reply related
* [PATCH v2 10/12] arm64: dts: imx8mp-ultra-mach-sbc: Correct PAD settings for PMIC_nINT
From: Peng Fan (OSS) @ 2026-03-26 7:28 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Laurent Pinchart, Shawn Guo, Daniel Scally, Marco Felsch,
Gilles Talis, Viorel Suman, Shengjiu Wang, Jagan Teki, Manoj Sai,
Matteo Lisi, Ray Chang, Richard Hu, Heiko Schocher, Martyn Welch,
Josua Mayer, Goran Rađenović, Börge Strümpfel,
Christoph Niedermaier, Marek Vasut
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, kernel, Peng Fan
In-Reply-To: <20260326-imx8mp-dts-fix-v2-v2-0-62c4ce727448@nxp.com>
From: Peng Fan <peng.fan@nxp.com>
With commit 5d0efaf47ee90 ("regulator: pca9450: Correct interrupt type"),
there might be interrupt storm for this board. Need to set PAD PUE and PU
together to make pull up work properly.
Fixes: d1c1400bd3b8b ("arm64: dts: imx8mp: Add initial support for Ultratronik imx8mp-ultra-mach-sbc board")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mp-ultra-mach-sbc.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-ultra-mach-sbc.dts b/arch/arm64/boot/dts/freescale/imx8mp-ultra-mach-sbc.dts
index 9ecec1a418781a6f354d73b499b181a573096414..3e6f9c88cc200b72b504640843baefcaa5447c8a 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-ultra-mach-sbc.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-ultra-mach-sbc.dts
@@ -275,7 +275,7 @@ pmic@25 {
reg = <0x25>;
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio1>;
- interrupts = <3 GPIO_ACTIVE_LOW>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
/*
* i.MX 8M Plus Data Sheet for Consumer Products
@@ -739,7 +739,7 @@ MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x40 /* NFC_INT */
pinctrl_pmic: pmic-grp {
fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x40 /* #PMIC_INT */
+ MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 /* #PMIC_INT */
>;
};
--
2.37.1
^ permalink raw reply related
* [PATCH v2 09/12] arm64: dts: imx8mp-sr-som: Correct PAD settings for PMIC_nINT
From: Peng Fan (OSS) @ 2026-03-26 7:28 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Laurent Pinchart, Shawn Guo, Daniel Scally, Marco Felsch,
Gilles Talis, Viorel Suman, Shengjiu Wang, Jagan Teki, Manoj Sai,
Matteo Lisi, Ray Chang, Richard Hu, Heiko Schocher, Martyn Welch,
Josua Mayer, Goran Rađenović, Börge Strümpfel,
Christoph Niedermaier, Marek Vasut
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, kernel, Peng Fan
In-Reply-To: <20260326-imx8mp-dts-fix-v2-v2-0-62c4ce727448@nxp.com>
From: Peng Fan <peng.fan@nxp.com>
With commit 5d0efaf47ee90 ("regulator: pca9450: Correct interrupt type"),
there might be interrupt storm for this board. Need to set PAD PUE and PU
together to make pull up work properly.
Fixes: a009c0c66ecb4 ("arm64: dts: add description for solidrun imx8mp som and cubox-m")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi
index 3cdb0bc0ab721709fc892931ea00a538ec6216ff..c3f7daa773eaf335deb6cc976a5e120abdae5967 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-sr-som.dtsi
@@ -174,7 +174,7 @@ pmic: pmic@25 {
pinctrl-0 = <&pmic_pins>;
pinctrl-names = "default";
interrupt-parent = <&gpio1>;
- interrupts = <3 GPIO_ACTIVE_LOW>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
nxp,i2c-lt-enable;
regulators {
@@ -417,7 +417,7 @@ MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x160
pmic_pins: pinctrl-pmic-grp {
fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
+ MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0
>;
};
--
2.37.1
^ permalink raw reply related
* [PATCH v2 08/12] arm64: dts: imx8mp-nitrogen-som: Correct PAD settings for PMIC_nINT
From: Peng Fan (OSS) @ 2026-03-26 7:28 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Laurent Pinchart, Shawn Guo, Daniel Scally, Marco Felsch,
Gilles Talis, Viorel Suman, Shengjiu Wang, Jagan Teki, Manoj Sai,
Matteo Lisi, Ray Chang, Richard Hu, Heiko Schocher, Martyn Welch,
Josua Mayer, Goran Rađenović, Börge Strümpfel,
Christoph Niedermaier, Marek Vasut
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, kernel, Peng Fan
In-Reply-To: <20260326-imx8mp-dts-fix-v2-v2-0-62c4ce727448@nxp.com>
From: Peng Fan <peng.fan@nxp.com>
With commit 5d0efaf47ee90 ("regulator: pca9450: Correct interrupt type"),
there might be interrupt storm for this board. Need to set PAD PUE and PU
together to make pull up work properly.
Fixes: ab4d874c9f44e ("arm64: dts: imx8mp: Add device tree for Nitrogen8M Plus ENC Carrier Board")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mp-nitrogen-som.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-som.dtsi
index f658309612efff42e7b9e6789a27b164577271bf..8465b36d440ae39a752a6fc364c9746483fa13fb 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-nitrogen-som.dtsi
@@ -296,7 +296,7 @@ MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3
pinctrl_pmic: pmicirqgrp {
fsl,pins = <
- MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x41
+ MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x1c0
>;
};
--
2.37.1
^ permalink raw reply related
* [PATCH v2 07/12] arm64: dts: imx8mp-aristainetos3a-som-v1: Correct PAD settings for PMIC_nINT
From: Peng Fan (OSS) @ 2026-03-26 7:28 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Laurent Pinchart, Shawn Guo, Daniel Scally, Marco Felsch,
Gilles Talis, Viorel Suman, Shengjiu Wang, Jagan Teki, Manoj Sai,
Matteo Lisi, Ray Chang, Richard Hu, Heiko Schocher, Martyn Welch,
Josua Mayer, Goran Rađenović, Börge Strümpfel,
Christoph Niedermaier, Marek Vasut
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, kernel, Peng Fan
In-Reply-To: <20260326-imx8mp-dts-fix-v2-v2-0-62c4ce727448@nxp.com>
From: Peng Fan <peng.fan@nxp.com>
With commit 5d0efaf47ee90 ("regulator: pca9450: Correct interrupt type"),
there might be interrupt storm for this board. Need to set PAD PUE and PU
together to make pull up work properly.
Fixes: eead8f3536d5c ("arm64: dts: imx8mp: add aristainetos3 board support")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mp-aristainetos3a-som-v1.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3a-som-v1.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3a-som-v1.dtsi
index f654d866e58c06245b06348a14ca1b16c6c4550d..e7666e54310be0f4c028491ba4383040d859a901 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3a-som-v1.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-aristainetos3a-som-v1.dtsi
@@ -903,7 +903,7 @@ MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x41
pinctrl_pmic: aristainetos3-pmic-grp {
fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
+ MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0
>;
};
--
2.37.1
^ permalink raw reply related
* [PATCH v2 06/12] arm64: dts: imx8mp-edm-g: Correct PAD settings for PMIC_nINT
From: Peng Fan (OSS) @ 2026-03-26 7:28 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Laurent Pinchart, Shawn Guo, Daniel Scally, Marco Felsch,
Gilles Talis, Viorel Suman, Shengjiu Wang, Jagan Teki, Manoj Sai,
Matteo Lisi, Ray Chang, Richard Hu, Heiko Schocher, Martyn Welch,
Josua Mayer, Goran Rađenović, Börge Strümpfel,
Christoph Niedermaier, Marek Vasut
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, kernel, Peng Fan
In-Reply-To: <20260326-imx8mp-dts-fix-v2-v2-0-62c4ce727448@nxp.com>
From: Peng Fan <peng.fan@nxp.com>
With commit 5d0efaf47ee90 ("regulator: pca9450: Correct interrupt type"),
there might be interrupt storm for this board. Need to set PAD PUE and PU
together to make pull up work properly.
Fixes: 95e882c021c8b ("arm64: dts: imx8mp: Add TechNexion EDM-G-IMX8M-PLUS SOM on WB-EDM-G carrier board")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mp-edm-g.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-edm-g.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-edm-g.dtsi
index 3f1e0837f349fad22b94d553d8153982a87a4577..91b87a7248dd1ff57ef8b401d50cf18f4d54af6c 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-edm-g.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-edm-g.dtsi
@@ -563,7 +563,7 @@ MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x41 /* PCIE RST */
pinctrl_pmic: pmicirqgrp {
fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
+ MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0
>;
};
--
2.37.1
^ permalink raw reply related
* [PATCH v2 05/12] arm64: dts: imx8mp-icore-mx8mp: Correct PAD settings for PMIC_nINT
From: Peng Fan (OSS) @ 2026-03-26 7:28 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Laurent Pinchart, Shawn Guo, Daniel Scally, Marco Felsch,
Gilles Talis, Viorel Suman, Shengjiu Wang, Jagan Teki, Manoj Sai,
Matteo Lisi, Ray Chang, Richard Hu, Heiko Schocher, Martyn Welch,
Josua Mayer, Goran Rađenović, Börge Strümpfel,
Christoph Niedermaier, Marek Vasut
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, kernel, Peng Fan
In-Reply-To: <20260326-imx8mp-dts-fix-v2-v2-0-62c4ce727448@nxp.com>
From: Peng Fan <peng.fan@nxp.com>
With commit 5d0efaf47ee90 ("regulator: pca9450: Correct interrupt type"),
there might be interrupt storm for this board. Need to set PAD PUE and PU
together to make pull up work properly.
Fixes: eefe06b295087 ("arm64: dts: imx8mp: Add Engicam i.Core MX8M Plus SoM")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi
index a6319824ea2eb140843402fcbcd7d2c8a38a1667..69558ffefa9a675ba9177fc579cbd7339994472a 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp.dtsi
@@ -132,7 +132,7 @@ MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
pinctrl_pmic: pmicgrp {
fsl,pins = <
- MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x41
+ MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x1c0
>;
};
--
2.37.1
^ permalink raw reply related
* [PATCH v2 04/12] arm64: dts: imx8mp-ab2: Correct PAD settings for PMIC_nINT
From: Peng Fan (OSS) @ 2026-03-26 7:28 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Laurent Pinchart, Shawn Guo, Daniel Scally, Marco Felsch,
Gilles Talis, Viorel Suman, Shengjiu Wang, Jagan Teki, Manoj Sai,
Matteo Lisi, Ray Chang, Richard Hu, Heiko Schocher, Martyn Welch,
Josua Mayer, Goran Rađenović, Börge Strümpfel,
Christoph Niedermaier, Marek Vasut
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, kernel, Peng Fan
In-Reply-To: <20260326-imx8mp-dts-fix-v2-v2-0-62c4ce727448@nxp.com>
From: Peng Fan <peng.fan@nxp.com>
With commit 5d0efaf47ee90 ("regulator: pca9450: Correct interrupt type"),
there will be interrupt storm for i.MX8MP AB2. Per schematic, there
is no on board PULL-UP resistors for GPIO1_IO03, so need to set PAD
PUE and PU together to make pull up work properly.
Fixes: 7adad1a52c420 ("arm64: dts: imx8mp-ab2: add support for NXP i.MX8MP audio board (version 2)")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mp-ab2.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-ab2.dts b/arch/arm64/boot/dts/freescale/imx8mp-ab2.dts
index 7031a33d85c8fab212e43883db4842b85bd532f1..dbbc0df0e3d1c7161b4210333decd55d70c206f4 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-ab2.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-ab2.dts
@@ -545,7 +545,7 @@ MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_PDM_BIT_STREAM03 0xd6
pinctrl_pmic: pmicgrp {
fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
+ MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0
>;
};
--
2.37.1
^ permalink raw reply related
* [PATCH v2 03/12] arm64: dts: imx8mp-navqp: Correct PAD settings for PMIC_nINT
From: Peng Fan (OSS) @ 2026-03-26 7:28 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Laurent Pinchart, Shawn Guo, Daniel Scally, Marco Felsch,
Gilles Talis, Viorel Suman, Shengjiu Wang, Jagan Teki, Manoj Sai,
Matteo Lisi, Ray Chang, Richard Hu, Heiko Schocher, Martyn Welch,
Josua Mayer, Goran Rađenović, Börge Strümpfel,
Christoph Niedermaier, Marek Vasut
Cc: devicetree, imx, linux-arm-kernel, linux-kernel, kernel, Peng Fan
In-Reply-To: <20260326-imx8mp-dts-fix-v2-v2-0-62c4ce727448@nxp.com>
From: Peng Fan <peng.fan@nxp.com>
With commit 5d0efaf47ee90 ("regulator: pca9450: Correct interrupt type"),
there will be interrupt storm for i.MX8MP NAVQP. Per schematic, there
is no on board PULL-UP resistors for GPIO1_IO03, so need to set PAD
PUE and PU together to make pull up work properly.
Fixes: 682729a9d506d ("arm64: dts: freescale: Add device tree for Emcraft Systems NavQ+ Kit")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mp-navqp.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-navqp.dts b/arch/arm64/boot/dts/freescale/imx8mp-navqp.dts
index 4a4f7c1adc23fe2615d8eb4904d795b46af4ca9f..9dedb9f11145ea842b4e718687dd153489ef4337 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-navqp.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-navqp.dts
@@ -356,7 +356,7 @@ MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3
pinctrl_pmic: pmicgrp {
fsl,pins = <
- MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
+ MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0
>;
};
--
2.37.1
^ permalink raw reply related
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