* Re: [PATCH] KVM: arm64: Treat ID_AA64DFR0_EL1.PMUVer as an unsigned field
From: Marc Zyngier @ 2026-04-21 16:45 UTC (permalink / raw)
To: Jing Zhang
Cc: KVM, KVMARM, ARMLinux, Oliver Upton, Joey Gouly, Suzuki K Poulose,
Zenghui Yu, Paolo Bonzini
In-Reply-To: <20260421164112.2448553-1-jingzhangos@google.com>
On Tue, 21 Apr 2026 17:41:12 +0100,
Jing Zhang <jingzhangos@google.com> wrote:
>
> ID_AA64DFR0_EL1.PMUVer is an unsigned 4-bit field, but was historically
> marked as signed in the cpufeature table. This led
> kvm_init_host_debug_data() to fail detection of PMUv3 implementation on
> systems with PMUv3p8 or newer, as the signed extraction of the field
> (e.g., 0b1000 for PMUv3p8) would result in a negative value.
>
> Fix this by marking the field as unsigned in the ftr_id_aa64dfr0 table
> and updating the KVM initialization code to use unsigned extraction.
> While at it, ensure that both the 'Not Implemented' (0b0000) and
> 'Implementation Defined' (0b1111) values are correctly handled as
> indicating the absence of a standard PMUv3.
>
> Signed-off-by: Jing Zhang <jingzhangos@google.com>
https://lore.kernel.org/all/20260305-james-kvm-pmuver-sign-v2-0-ee80a125af9b@linaro.org/
M.
--
Without deviation from the norm, progress is not possible.
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* Re: [PATCH v3 1/8] dt-bindings: thermal: amlogic: Add support for T7
From: Conor Dooley @ 2026-04-21 17:05 UTC (permalink / raw)
To: Ronald Claveau
Cc: Guillaume La Roque, Rafael J. Wysocki, Daniel Lezcano, Zhang Rui,
Lukasz Luba, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Neil Armstrong, Kevin Hilman, Jerome Brunet, Martin Blumenstingl,
linux-pm, linux-amlogic, devicetree, linux-kernel,
linux-arm-kernel
In-Reply-To: <20260421-add-thermal-t7-vim4-v3-1-a2e7215ed003@aliel.fr>
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On Tue, Apr 21, 2026 at 09:19:43AM +0200, Ronald Claveau wrote:
> Add the amlogic,t7-thermal compatible for the Amlogic T7 thermal sensor.
>
> Unlike existing variants which use a phandle to the ao-secure syscon,
> the T7 relies on a secure monitor interface described by a phandle and
> a sensor index argument.
>
> The T7 integrates multiple thermal sensors, all accessed through the
> same SMC call. The sensor index argument is required to identify which
> sensor's calibration data the secure monitor should return, as a single
> SM_THERMAL_CALIB_READ command serves all of them.
>
> Introduce the amlogic,secure-monitor property as a phandle-array and
> make amlogic,ao-secure or amlogic,secure-monitor conditionally required
> depending on the compatible.
>
> Signed-off-by: Ronald Claveau <linux-kernel-dev@aliel.fr>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable
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* Re: [PATCH v3 1/2] dt-bindings: arm: amlogic: add support for Amediatech X98Q
From: Conor Dooley @ 2026-04-21 17:13 UTC (permalink / raw)
To: christian.koever-draxl
Cc: robh, krzk+dt, conor+dt, neil.armstrong, khilman, jbrunet,
martin.blumenstingl, devicetree, linux-amlogic, linux-arm-kernel,
linux-kernel
In-Reply-To: <20260421155328.26359-2-christian.koever-draxl@student.uibk.ac.at>
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On Tue, Apr 21, 2026 at 05:53:27PM +0200, christian.koever-draxl@student.uibk.ac.at wrote:
> From: Christian Stefan Kövér-Draxl <christian.koever-draxl@student.uibk.ac.at>
>
> Add the board binding for the Amediatech X98Q TV box
>
> Signed-off-by: Christian Stefan Kövér-Draxl <christian.koever-draxl@student.uibk.ac.at>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable
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* Re: [PATCH net v4 2/2] net: airoha: Add missing bits in airoha_qdma_cleanup_tx_queue()
From: Lorenzo Bianconi @ 2026-04-21 17:15 UTC (permalink / raw)
To: Paolo Abeni
Cc: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Simon Horman, linux-arm-kernel, linux-mediatek, netdev
In-Reply-To: <210f5d0b-6232-4c0f-adff-3a97d54159b3@redhat.com>
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> On 4/17/26 8:36 AM, Lorenzo Bianconi wrote:
> > @@ -1055,8 +1058,33 @@ static void airoha_qdma_cleanup_tx_queue(struct airoha_queue *q)
> > e->dma_addr = 0;
> > e->skb = NULL;
> > list_add_tail(&e->list, &q->tx_list);
> > +
> > + /* Reset DMA descriptor */
> > + WRITE_ONCE(desc->ctrl, 0);
> > + WRITE_ONCE(desc->addr, 0);
> > + WRITE_ONCE(desc->data, 0);
> > + WRITE_ONCE(desc->msg0, 0);
> > + WRITE_ONCE(desc->msg1, 0);
> > + WRITE_ONCE(desc->msg2, 0);
>
> Sashiko has some complains on this patch that look legit to me.
>
> Also the pre-existing issues mentioned WRT patch 1/2 makes such patch
> IMHO almost ineffective, I think you should address them in the same series.
>
> Note that you should have commented on sashiko review on the ML, it
> would have saved a significant amount of time on us.
Since this series is marked as 'Changes Requested', it is not clear to me what
next steps are. I guess we have two possible approach here:
1) - Post patch 1/2 ("net: airoha: Move ndesc initialization at
end of airoha_qdma_init_tx()") with the series available upstream
(not merged yet) in [0] where I am fixing similar issues for
airoha_qdma_init_rx_queue() and airoha_qdma_tx_irq_init().
- Post patch 2/2 ("net: airoha: Add missing bits in
airoha_qdma_cleanup_tx_queue()") with a fix for airoha_ndo_stop() waiting
for TX/RX DMA engine to complete before running
airoha_qdma_cleanup_tx_queue().
2) - Since all the issues rised by Sashiko are not strictly related to this
series and they are already fixed in pending patches, just apply the fixes
separately without the needs to repost this series.
Which approach do you prefer?
Regards,
Lorenzo
[0] https://patchwork.kernel.org/project/netdevbpf/cover/20260420-airoha_qdma_init_rx_queue-fix-v2-0-d99347e5c18d@kernel.org/
>
> /P
>
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* Re: [PATCH net v4 2/2] net: airoha: Add missing bits in airoha_qdma_cleanup_tx_queue()
From: Paolo Abeni @ 2026-04-21 17:32 UTC (permalink / raw)
To: Lorenzo Bianconi
Cc: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Simon Horman, linux-arm-kernel, linux-mediatek, netdev
In-Reply-To: <aeewoVjN7EHLZTW_@lore-desk>
On 4/21/26 7:15 PM, Lorenzo Bianconi wrote:
>> On 4/17/26 8:36 AM, Lorenzo Bianconi wrote:
>>> @@ -1055,8 +1058,33 @@ static void airoha_qdma_cleanup_tx_queue(struct airoha_queue *q)
>>> e->dma_addr = 0;
>>> e->skb = NULL;
>>> list_add_tail(&e->list, &q->tx_list);
>>> +
>>> + /* Reset DMA descriptor */
>>> + WRITE_ONCE(desc->ctrl, 0);
>>> + WRITE_ONCE(desc->addr, 0);
>>> + WRITE_ONCE(desc->data, 0);
>>> + WRITE_ONCE(desc->msg0, 0);
>>> + WRITE_ONCE(desc->msg1, 0);
>>> + WRITE_ONCE(desc->msg2, 0);
>>
>> Sashiko has some complains on this patch that look legit to me.
>>
>> Also the pre-existing issues mentioned WRT patch 1/2 makes such patch
>> IMHO almost ineffective, I think you should address them in the same series.
>>
>> Note that you should have commented on sashiko review on the ML, it
>> would have saved a significant amount of time on us.
>
> Since this series is marked as 'Changes Requested', it is not clear to me what
> next steps are. I guess we have two possible approach here:
>
> 1) - Post patch 1/2 ("net: airoha: Move ndesc initialization at
> end of airoha_qdma_init_tx()") with the series available upstream
> (not merged yet) in [0] where I am fixing similar issues for
> airoha_qdma_init_rx_queue() and airoha_qdma_tx_irq_init().
> - Post patch 2/2 ("net: airoha: Add missing bits in
> airoha_qdma_cleanup_tx_queue()") with a fix for airoha_ndo_stop() waiting
> for TX/RX DMA engine to complete before running
> airoha_qdma_cleanup_tx_queue().
>
> 2) - Since all the issues rised by Sashiko are not strictly related to this
> series and they are already fixed in pending patches, just apply the fixes
> separately without the needs to repost this series.
Given the current flood on the ML I think option 2 could be the better.
Note that the tree is currently in Jakub's hands and he can very legitly
disagree.
/P
^ permalink raw reply
* Re: [PATCH v7 1/3] dt-bindings: pinctrl: Add aspeed,ast2700-soc0-pinctrl
From: Conor Dooley @ 2026-04-21 17:57 UTC (permalink / raw)
To: Billy Tsai
Cc: Lee Jones, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Joel Stanley, Andrew Jeffery, Linus Walleij, Bartosz Golaszewski,
Ryan Chen, Andrew Jeffery, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org,
openbmc@lists.ozlabs.org, linux-gpio@vger.kernel.org,
linux-clk@vger.kernel.org
In-Reply-To: <OSQPR06MB725251546BFEB158F9AA1C4D8B2C2@OSQPR06MB7252.apcprd06.prod.outlook.com>
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Billy, Linus,
On Tue, Apr 21, 2026 at 06:15:44AM +0000, Billy Tsai wrote:
> > > > > > > + properties:
> > > > > > > + function:
> > > > > > > + enum:
> > > > > > > + - EMMC
> > > > > > > + - JTAGDDR
> > > > > > > + - JTAGM0
> > > > > > > + - JTAGPCIEA
> > > > > > > + - JTAGPCIEB
> > > > > > > + - JTAGPSP
> > > > > > > + - JTAGSSP
> > > > > > > + - JTAGTSP
> > > > > > > + - JTAGUSB3A
> > > > > > > + - JTAGUSB3B
> > > > > > > + - PCIERC0PERST
> > > > > > > + - PCIERC1PERST
> > > > > > > + - TSPRSTN
> > > > > > > + - UFSCLKI
> > > > > > > + - USB2AD0
> > > > > > > + - USB2AD1
> > > > > > > + - USB2AH
> > > > > > > + - USB2AHP
> > > > > > > + - USB2AHPD0
> > > > > > > + - USB2AXH
> > > > > > > + - USB2AXH2B
> > > > > > > + - USB2AXHD1
> > > > > > > + - USB2AXHP
> > > > > > > + - USB2AXHP2B
> > > > > > > + - USB2AXHPD1
> > > > > > > + - USB2BD0
> > > > > > > + - USB2BD1
> > > > > > > + - USB2BH
> > > > > > > + - USB2BHP
> > > > > > > + - USB2BHPD0
> > > > > > > + - USB2BXH
> > > > > > > + - USB2BXH2A
> > > > > > > + - USB2BXHD1
> > > > > > > + - USB2BXHP
> > > > > > > + - USB2BXHP2A
> > > > > > > + - USB2BXHPD1
> > > > > > > + - USB3AXH
> > > > > > > + - USB3AXH2B
> > > > > > > + - USB3AXHD
> > > > > > > + - USB3AXHP
> > > > > > > + - USB3AXHP2B
> > > > > > > + - USB3AXHPD
> > > > > > > + - USB3BXH
> > > > > > > + - USB3BXH2A
> > > > > > > + - USB3BXHD
> > > > > > > + - USB3BXHP
> > > > > > > + - USB3BXHP2A
> > > > > > > + - USB3BXHPD
> > > > > > > + - VB
> > > > > > > + - VGADDC
> > > > > > > +
> > > > > > > + groups:
> > > > > > > + enum:
> > > > > > > + - EMMCCDN
> > > > > > > + - EMMCG1
> > > > > > > + - EMMCG4
> > > > > > > + - EMMCG8
> > > > > > > + - EMMCWPN
> > > > > > > + - JTAG0
> > > > > > > + - PCIERC0PERST
> > > > > > > + - PCIERC1PERST
> > > > > > > + - TSPRSTN
> > > > > > > + - UFSCLKI
> > > > > > > + - USB2A
> > > > > > > + - USB2AAP
> > > > > > > + - USB2ABP
> > > > > > > + - USB2ADAP
> > > > > > > + - USB2AH
> > > > > > > + - USB2AHAP
> > > > > > > + - USB2B
> > > > > > > + - USB2BAP
> > > > > > > + - USB2BBP
> > > > > > > + - USB2BDBP
> > > > > > > + - USB2BH
> > > > > > > + - USB2BHBP
> > > > > > > + - USB3A
> > > > > > > + - USB3AAP
> > > > > > > + - USB3ABP
> > > > > > > + - USB3B
> > > > > > > + - USB3BAP
> > > > > > > + - USB3BBP
> > > > > > > + - VB0
> > > > > > > + - VB1
> > > > > > > + - VGADDC
> > > > > > > + pins:
> > > > > > > + enum:
> > > > > > > + - AB13
> > > > > > > + - AB14
> > > > > > > + - AC13
> > > > > > > + - AC14
> > > > > > > + - AD13
> > > > > > > + - AD14
> > > > > > > + - AE13
> > > > > > > + - AE14
> > > > > > > + - AE15
> > > > > > > + - AF13
> > > > > > > + - AF14
> > > > > > > + - AF15
>
> > > > > > Why do you have groups and pins?
> > > > > > Is it valid in your device to have groups and pins in the same node?
>
> > > > > The intent is to support both group-based mux selection and
> > > > > configuration, as well as per-pin configuration.
>
> > > > > In our hardware:
> > > > > - `function` + `groups` are used for pinmux selection.
> > > > > - `pins` is used for per-pin configuration (e.g. drive strength,
> > > > > bias settings).
> > > > > - `groups` may also be used for group-level configuration.
>
> > > > > As a result, both `groups` and `pins` may appear in the same node,
> > > > > but they serve different purposes and do not conflict:
> > > > > - `groups` selects the mux function and may apply configuration to
> > > > > the entire group.
> > > > > - `pins` allows overriding or specifying configuration for individual
> > > > > pins.
>
> > > > > In most cases, only one of them is needed, but both are allowed when
> > > > > both group-level and per-pin configuration are required.
>
> > > > To be honest, that sounds like your groups are not sufficiently
> > > > granular and should be reduced such that you can use them for pin
> > > > settings.
>
> > > The intent was to keep the binding flexible, but in practice the mixed
> > > use of `groups` and `pins` in the same node is not expected to be used.
> > >
> > > Given that, I agree this flexibility is unnecessary and makes the
> > > binding semantics less clear. I'll rework the binding to make the
> > > expected usage explicit rather than allowing combinations that do not
> > > correspond to a real use case.
> > >
> > > In particular, I'll split the constraints as follows:
> > >
> > > - For pinmux, the presence of `function` will require `groups`, and
> > > `pins` will not be allowed. This reflects the hardware design, where
> > > the groups are defined by the pins affected by a given mux expression
> > >
> > > - For pin configuration, exactly one of `groups` or `pins` will be
> > > required (using oneOf), so that configuration is applied either at
> > > group level or per-pin, but not both.
> > >
> > >
> > > - if:
> > > required:
> > > - function
> > > then:
> > > required:
> > > - groups
> > > not:
> > > required:
> > > - pins
> > > else:
> > > oneOf:
> > > - required:
> > > - groups
> > > not:
> > > required:
> > > - pins
> > > - required:
> > > - pins
> > > not:
> > > required:
> > > - groups
> > > Does this match what you had in mind?
>
> > It's an improvement I think, but I am wondering why you cannot do
> > without pins entirely and apply pinconf stuff at the group level?
> > Of course that may not be possible with the current groups, but if you
> > made the groups more granular, would it be possible?
>
> Within a given group, it is not always the case that all pins share the
> same configuration requirements (e.g. drive strength or bias settings),
> so applying pinconf purely at the group level would be too restrictive.
Right. That's pretty normal.
> Making the groups more granular to match all possible configuration
> combinations would not reflect the actual mux granularity and would
> significantly increase the number of groups.
>
> For example, we have encountered a timing issue due to the PCB layout,
> where only the eMMC clock pin requires a different drive strength:
>
> # The EMMCG4 group includes pins AC14, AE15, AD14, AE14, AF14, AB13
> # AC14: clock
> # AE15: command
> # AD14–AB13: data
>
> pinconf_emmc_clk: emmc-clk-pinconf {
> pins = "AC14";
> drive-strength = <8>;
> };
>
> In this case, applying pin configuration at the group level would affect
> all pins in the group, which is not desirable. Allowing per-pin
> configuration via `pins` is therefore necessary.
>
> For this reason, `groups` is used for mux selection, while `pins` is
> required to express per-pin configuration where needed.
Right, yeah, I figured your objection to it was because of how
annoyingly small it would make the groups. I suppose the alternative is
going without groups and always using pins.
Having groups and pins seems really suboptimal to me, but there are
some other bindings where this is done. Linus, what is your take on
nodes supporting both? I'm biased towards having a more straightforward
binding but if you think this mix makes sense then I'll defer to your
vastly greater experience with these devices.
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* [PATCH/RFC 00/14] R-Car X5H Ironhide SCMI CPG/MDLC remapping
From: Geert Uytterhoeven @ 2026-04-21 18:11 UTC (permalink / raw)
To: Sudeep Holla, Cristian Marussi, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Magnus Damm, Saravana Kannan, Michael Turquette,
Stephen Boyd, Philipp Zabel, Ulf Hansson, Rafael J . Wysocki,
Kevin Hilman, Florian Fainelli, Wolfram Sang, Marek Vasut,
Kuninori Morimoto
Cc: arm-scmi, linux-arm-kernel, linux-renesas-soc, linux-clk,
devicetree, linux-pm, linux-kernel, Geert Uytterhoeven
Hi all,
TL;DR:
Describe hardware in DT, and perform the mapping to SCMI in Linux.
The Renesas R-Car X5H-based Ironhide board is the first Renesas
SoC/board combination that implements the ARM System Control and
Management Interface (SCMI).
This means Linux can no longer perform various system operations (e.g.
clock, power domain, and reset control) by accessing the hardware
directly. Instead, these operations are abstracted according to various
SCMI sub-protocols, and Linux has to send messages to an SCMI-compliant
firmware running on a System Control Processor (SCP).
More specifically, the R-Car X5H SCP FW SCMI controls access to:
1. Core clocks and module clocks,
2. Module resets,
3. Power domains,
4. System power.
The latter is not relevant for this discussion.
Using SCMI also has an impact on the board DTS: besides the addition of
a firmware/scmi node with protocol-specific subnodes, devices using
SCMI-abstracted system resources now have to refer to these resources
using resource specifiers containing phandles to the SCMI protocol
subnodes, and firmware-specific object IDs[1].
Unfortunately we encountered several issues with this:
- The clock, reset, and power domain IDs are not stable, and may
change from one SCP firmware release to another, causing DTB
incompatibilities,
- There may be different SCP firmware lineages, e.g. proprietary and
certified variants, and FLOSS variants,
- SCMI features and quirks may differ across firmware versions,
- Not all quirks can be handled as SCMI quirks,
- Some core clocks do not support the CLOCK_ATTRIBUTES command, and
thus are not accessible to Linux, while Linux may need them,
requiring dummy clocks,
- Some module clocks are not accessible to Linux, or report a zero
clock rate and have no parent, while several existing drivers need
to know their clock rates,
- SCMI does not support the concept of a clock domain, so existing
drivers can no longer rely on Runtime PM, but need to be changed to
explicit management of functional clocks,
- Some clocks and power domains are critical and must not be disabled,
or even touched,
- Some module resets are reserved, and operating them returns an
error,
- U-Boot IPL (Initial Program Loader) needs a proper hardware
description in DT, not using SCMI.
During last OSSJ/LPC, Marek Vasut pondered if we could keep our own ID
lists stable, and perform a mapping to the IDs used by the actual SCMI
implementation running on the system. This was also briefly discussed
at LPC[2]. After some refining of the initial idea, this series takes a
slightly different approach, by:
1. Describing the actual hardware components in DT, plus a minimum
SCMI glue,
2. Mapping DT hardware descriptions to SCMI-backed objects (or
replacements in case they are unusable), in Linux drivers, based on
the detected firmware version.
This has the following advantages:
1. The DT ABI is stable,
2. Current and future firmware quirks can be handled in driver code,
3. If ever needed, the Clock Pulse Generator (CPG) and Module
Controller (MDLC) drivers can be extended to program the hardware
directly if SCMI is not present,
4. U-Boot IPL can use almost the same DTS; it just needs stripping of
SCMI-related nodes and properties.
This series is based on renesas-drivers-2026-04-14-v7.0, which includes
a.o. the scmi/for-linux-next branch. It consists of multiple parts:
1. Patches 1-3 add various quirks to the SCMI driver code,
2. Patch 4 enables more SCMI protocols on R-Car X5H Ironhide,
3. Patches 5-8 add new interfaces needed by the remapping drivers,
4. Patches 9-10 add DT bindings for the R-Car X5H Clock Pulse Generator
(CPG) and Module Controller (MDLC) blocks,
5. Patches 11-12 add remapping drivers for the R-Car X5H Clock Pulse
Generator (CPG) and Module Controller (MDLC) blocks,
6. Patches 13-14 add DTS description for R-Car X5H Ironhide.
Dependencies:
- Lifting "#define SCMI_MAX_NUM_RATES 16" (e.g. scmi/for-linux-next),
- "[PATCH v4 0/3] soc: renesas: add MFIS driver"[3],
- R-Car X5H MFIS and Ironhide SCMI DTS enablement (not yet posted).
For testing, I have pushed this series and its dependencies to the
topic/rcar-x5h-ironhide-scmi-cpg-mdlc-remapping-v1 branch of
https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git.
With this, Ironhide can boot into a serial console shell from a ramdisk,
without needing any of "clk_ignore_unused" and "pd_ignore_unused".
FTR, alternative locations to do remapping that we considered:
- Inside the SCMI clock, reset, and power-domain drivers,
- Inside the subsystem driver core (e.g. of_parse_clkspec()),
- Inside the OF driver core,
- Inside the DTB.
Remapping inside DT is usually done through a nexus node (see Devicetree
Specification, Section 2.5 Nexus Nodes and Specifier Mapping), using
"<specifier>-map", "<specifier>-map-mask", and
"<specifier>-map-pass-thru" properties. Linux has support for e.g.
remapping interrupts (open-coded in drivers/of/irq.c), and gpios or pwms
(using the of_parse_phandle_with_args_map()) helper. So far there is no
support for remapping clocks or power domains, but at least for clocks
patches have been posted[4]. Then the remapping can be done by adding
e.g. "clocks-map{,-mask,-pass-thru}" properties with translation data
to the CPG/MDLC DT node, using a DT overlay. The DT overlay could be
applied by the firmware or bootloader (e.g. in in fitImage script), or
even by the CPG/MDLC Linux driver at runtime (based on detected SCP
firmware version). Consumer nodes do not need to be modified.
Note that such translations can only support simple cases. If e.g. a
workaround is needed to map a single DT clock to multiple SCMI clocks,
this cannot be done using a simple translation table.
While a DT overlay is quite flexible and can also do other fixup, it is
less user-friendly than doing the remapping in a Linux driver.
Thanks for your comments!
[1] Documentation/devicetree/bindings/firmware/arm,scmi.yaml
[2] "Firmware ABI stability" at Linux Plumbers Conference 2025
https://lpc.events/event/19/contributions/2153/
[3] "[PATCH v4 0/3] soc: renesas: add MFIS driver"
https://lore.kernel.org/20260402112709.13002-1-wsa+renesas@sang-engineering.com/
[4] "[PATCH] clk: Add support for clock nexus dt bindings"
https://lore.kernel.org/20260129201003.288605-1-miquel.raynal@bootlin.com/
Geert Uytterhoeven (14):
firmware: arm_scmi: quirk: Handle bad power domains on R-Car X5H
firmware: arm_scmi: quirk: Handle bad clocks on R-Car X5H
firmware: arm_scmi: quirk: Handle critical clocks on R-Car X5H
arm64: dts: renesas: ironhide: Enable SCMI devpd, sys, and reset
firmware: arm_scmi: Add scmi_get_base_info()
of: property: fw_devlink: Add support for firmware
pmdomain: Make genpd_get_from_provider() public
reset: Add reset_controller_get_provider()
dt-bindings: clock: Document Renesas R-Car X5H Clock Pulse Generator
dt-bindings: power: Document Renesas R-Car X5H Module Controller
clk: renesas: Add R-Car X5H CPG SCMI remapping driver
pmdomain: renesas: Add R-Car X5H MDLC SCMI remapping driver
arm64: dts: renesas: r8a78000: Add CPG/MDLC nodes
arm64: dts: renesas: ironhide: Add CPG/MDLC firmware properties
.../bindings/clock/renesas,r8a78000-cpg.yaml | 62 +
.../bindings/power/renesas,r8a78000-mdlc.yaml | 63 +
.../boot/dts/renesas/r8a78000-ironhide.dts | 130 +++
arch/arm64/boot/dts/renesas/r8a78000.dtsi | 300 ++++-
drivers/clk/renesas/Kconfig | 4 +
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/r8a78000-cpg.c | 335 ++++++
drivers/firmware/arm_scmi/clock.c | 37 +
drivers/firmware/arm_scmi/driver.c | 31 +
drivers/firmware/arm_scmi/power.c | 20 +
drivers/firmware/arm_scmi/quirks.c | 12 +
drivers/firmware/arm_scmi/quirks.h | 4 +
drivers/of/property.c | 2 +
drivers/pmdomain/core.c | 4 +-
drivers/pmdomain/renesas/Kconfig | 4 +
drivers/pmdomain/renesas/Makefile | 1 +
drivers/pmdomain/renesas/r8a78000-mdlc.c | 1021 +++++++++++++++++
drivers/reset/core.c | 11 +
drivers/soc/renesas/Kconfig | 1 +
.../dt-bindings/clock/renesas,r8a78000-cpg.h | 15 +
.../dt-bindings/power/renesas,r8a78000-mdlc.h | 16 +
include/linux/pm_domain.h | 7 +
include/linux/reset-controller.h | 6 +
include/linux/scmi_protocol.h | 8 +
24 files changed, 2068 insertions(+), 27 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/renesas,r8a78000-cpg.yaml
create mode 100644 Documentation/devicetree/bindings/power/renesas,r8a78000-mdlc.yaml
create mode 100644 drivers/clk/renesas/r8a78000-cpg.c
create mode 100644 drivers/pmdomain/renesas/r8a78000-mdlc.c
create mode 100644 include/dt-bindings/clock/renesas,r8a78000-cpg.h
create mode 100644 include/dt-bindings/power/renesas,r8a78000-mdlc.h
--
2.43.0
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [PATCH/RFC 01/14] firmware: arm_scmi: quirk: Handle bad power domains on R-Car X5H
From: Geert Uytterhoeven @ 2026-04-21 18:11 UTC (permalink / raw)
To: Sudeep Holla, Cristian Marussi, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Magnus Damm, Saravana Kannan, Michael Turquette,
Stephen Boyd, Philipp Zabel, Ulf Hansson, Rafael J . Wysocki,
Kevin Hilman, Florian Fainelli, Wolfram Sang, Marek Vasut,
Kuninori Morimoto
Cc: arm-scmi, linux-arm-kernel, linux-renesas-soc, linux-clk,
devicetree, linux-pm, linux-kernel, Geert Uytterhoeven
In-Reply-To: <cover.1776793163.git.geert+renesas@glider.be>
Renesas R-Car X5H SCP FW SDKv4.28.0, v4.31.0, and v4.32.0 advertise a
few power domains that crash the system when touched or powered off.
Add a quirk to prevent such crashes.
As the SCMI power domain IDs are identical for all three versions, the
quirk can be shared.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Preventing power off could be handled in the MDLC driver, but no-touch
cannot.
---
drivers/firmware/arm_scmi/power.c | 20 ++++++++++++++++++++
drivers/firmware/arm_scmi/quirks.c | 3 +++
drivers/firmware/arm_scmi/quirks.h | 1 +
3 files changed, 24 insertions(+)
diff --git a/drivers/firmware/arm_scmi/power.c b/drivers/firmware/arm_scmi/power.c
index bb5062ab8280e02b..81b9035aa5a2eafe 100644
--- a/drivers/firmware/arm_scmi/power.c
+++ b/drivers/firmware/arm_scmi/power.c
@@ -12,6 +12,7 @@
#include "protocols.h"
#include "notify.h"
+#include "quirks.h"
/* Updated only after ALL the mandatory features for that version are merged */
#define SCMI_PROTOCOL_SUPPORTED_VERSION 0x30001
@@ -150,6 +151,23 @@ scmi_power_domain_attributes_get(const struct scmi_protocol_handle *ph,
return ret;
}
+#define QUIRK_RCAR_X5H_4_28_BAD_DOMAINS \
+ ({ \
+ switch (domain) { \
+ /* Do not touch */ \
+ case 29: /* PD_RC08 */ \
+ case 92: /* PD_ACL0 */ \
+ case 116: /* PD_CMN */ \
+ return -EPERM; \
+ \
+ /* Do not power off */ \
+ case 76: /* PD_AC00 */ \
+ if (state == SCMI_POWER_STATE_GENERIC_OFF) \
+ return -EPERM; \
+ break; \
+ } \
+ })
+
static int scmi_power_state_set(const struct scmi_protocol_handle *ph,
u32 domain, u32 state)
{
@@ -157,6 +175,8 @@ static int scmi_power_state_set(const struct scmi_protocol_handle *ph,
struct scmi_xfer *t;
struct scmi_power_set_state *st;
+ SCMI_QUIRK(power_rcar_x5h_4_28_bad_domains, QUIRK_RCAR_X5H_4_28_BAD_DOMAINS);
+
ret = ph->xops->xfer_get_init(ph, POWER_STATE_SET, sizeof(*st), 0, &t);
if (ret)
return ret;
diff --git a/drivers/firmware/arm_scmi/quirks.c b/drivers/firmware/arm_scmi/quirks.c
index 2b38ba3f59a13c9e..c1a2f58505c1a757 100644
--- a/drivers/firmware/arm_scmi/quirks.c
+++ b/drivers/firmware/arm_scmi/quirks.c
@@ -172,6 +172,8 @@ struct scmi_quirk {
/* Global Quirks Definitions */
DEFINE_SCMI_QUIRK(clock_rates_triplet_out_of_spec, NULL, NULL, NULL);
DEFINE_SCMI_QUIRK(perf_level_get_fc_force, "Qualcomm", NULL, "0x20000-");
+DEFINE_SCMI_QUIRK(power_rcar_x5h_4_28_bad_domains, "Renesas", NULL,
+ "0x10a0000-0x10e0000", "renesas,r8a78000");
/*
* Quirks Pointers Array
@@ -182,6 +184,7 @@ DEFINE_SCMI_QUIRK(perf_level_get_fc_force, "Qualcomm", NULL, "0x20000-");
static struct scmi_quirk *scmi_quirks_table[] = {
__DECLARE_SCMI_QUIRK_ENTRY(clock_rates_triplet_out_of_spec),
__DECLARE_SCMI_QUIRK_ENTRY(perf_level_get_fc_force),
+ __DECLARE_SCMI_QUIRK_ENTRY(power_rcar_x5h_4_28_bad_domains),
NULL
};
diff --git a/drivers/firmware/arm_scmi/quirks.h b/drivers/firmware/arm_scmi/quirks.h
index d8ba60b956522d04..108c8d11f6043a61 100644
--- a/drivers/firmware/arm_scmi/quirks.h
+++ b/drivers/firmware/arm_scmi/quirks.h
@@ -48,5 +48,6 @@ static inline void scmi_quirks_enable(struct device *dev, const char *vend,
/* Quirk delarations */
DECLARE_SCMI_QUIRK(clock_rates_triplet_out_of_spec);
DECLARE_SCMI_QUIRK(perf_level_get_fc_force);
+DECLARE_SCMI_QUIRK(power_rcar_x5h_4_28_bad_domains);
#endif /* _SCMI_QUIRKS_H */
--
2.43.0
^ permalink raw reply related
* [PATCH/RFC 02/14] firmware: arm_scmi: quirk: Handle bad clocks on R-Car X5H
From: Geert Uytterhoeven @ 2026-04-21 18:11 UTC (permalink / raw)
To: Sudeep Holla, Cristian Marussi, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Magnus Damm, Saravana Kannan, Michael Turquette,
Stephen Boyd, Philipp Zabel, Ulf Hansson, Rafael J . Wysocki,
Kevin Hilman, Florian Fainelli, Wolfram Sang, Marek Vasut,
Kuninori Morimoto
Cc: arm-scmi, linux-arm-kernel, linux-renesas-soc, linux-clk,
devicetree, linux-pm, linux-kernel, Geert Uytterhoeven
In-Reply-To: <cover.1776793163.git.geert+renesas@glider.be>
Renesas R-Car X5H SCP FW SDKv4.28.0, v4.31.0, and v4.32.0 expose a few
clocks that do not support the CLOCK_ATTRIBUTES or CLOCK_DESCRIBE_RATES
command. Since commit 0d8b0c8068a8ff5f ("firmware: arm_scmi: Harden
clock protocol initialization") in scmi/for-linux-next (next-20260319
and later), scmi_clock_attributes_get() or
scmi_clock_describe_rates_get() failures are no longer ignored, but
prevent the SCMI clock driver from initializing.
Hence add a quirk to ignore such failures, like before. As the quirk
handling is harmless for unaffected systems, make it generic for all
R-Car X5H systems using SCP FW SDKv4.28.0 or later.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/firmware/arm_scmi/clock.c | 14 ++++++++++++++
drivers/firmware/arm_scmi/quirks.c | 3 +++
drivers/firmware/arm_scmi/quirks.h | 1 +
3 files changed, 18 insertions(+)
diff --git a/drivers/firmware/arm_scmi/clock.c b/drivers/firmware/arm_scmi/clock.c
index ce6f968925af38c0..d530882a0bac88c3 100644
--- a/drivers/firmware/arm_scmi/clock.c
+++ b/drivers/firmware/arm_scmi/clock.c
@@ -1232,6 +1232,18 @@ static const struct scmi_protocol_events clk_protocol_events = {
.num_events = ARRAY_SIZE(clk_events),
};
+#define QUIRK_RCAR_X5H_NO_ATTRIBUTES \
+ ({ \
+ if (ret == -EREMOTEIO || ret == -EOPNOTSUPP) \
+ continue; \
+ })
+
+#define QUIRK_RCAR_X5H_NO_RATES \
+ ({ \
+ if (ret == -EOPNOTSUPP) \
+ ret = 0; \
+ })
+
static int scmi_clock_protocol_init(const struct scmi_protocol_handle *ph)
{
int clkid, ret;
@@ -1256,10 +1268,12 @@ static int scmi_clock_protocol_init(const struct scmi_protocol_handle *ph)
for (clkid = 0; clkid < cinfo->num_clocks; clkid++) {
cinfo->clkds[clkid].id = clkid;
ret = scmi_clock_attributes_get(ph, clkid, cinfo);
+ SCMI_QUIRK(clock_rcar_x5h_no_attributes, QUIRK_RCAR_X5H_NO_ATTRIBUTES);
if (ret)
return ret;
ret = scmi_clock_describe_rates_get(ph, clkid, cinfo);
+ SCMI_QUIRK(clock_rcar_x5h_no_attributes, QUIRK_RCAR_X5H_NO_RATES);
if (ret)
return ret;
}
diff --git a/drivers/firmware/arm_scmi/quirks.c b/drivers/firmware/arm_scmi/quirks.c
index c1a2f58505c1a757..e27c21b14220ab5f 100644
--- a/drivers/firmware/arm_scmi/quirks.c
+++ b/drivers/firmware/arm_scmi/quirks.c
@@ -171,6 +171,8 @@ struct scmi_quirk {
/* Global Quirks Definitions */
DEFINE_SCMI_QUIRK(clock_rates_triplet_out_of_spec, NULL, NULL, NULL);
+DEFINE_SCMI_QUIRK(clock_rcar_x5h_no_attributes, "Renesas", NULL, "0x10a0000-",
+ "renesas,r8a78000");
DEFINE_SCMI_QUIRK(perf_level_get_fc_force, "Qualcomm", NULL, "0x20000-");
DEFINE_SCMI_QUIRK(power_rcar_x5h_4_28_bad_domains, "Renesas", NULL,
"0x10a0000-0x10e0000", "renesas,r8a78000");
@@ -183,6 +185,7 @@ DEFINE_SCMI_QUIRK(power_rcar_x5h_4_28_bad_domains, "Renesas", NULL,
*/
static struct scmi_quirk *scmi_quirks_table[] = {
__DECLARE_SCMI_QUIRK_ENTRY(clock_rates_triplet_out_of_spec),
+ __DECLARE_SCMI_QUIRK_ENTRY(clock_rcar_x5h_no_attributes),
__DECLARE_SCMI_QUIRK_ENTRY(perf_level_get_fc_force),
__DECLARE_SCMI_QUIRK_ENTRY(power_rcar_x5h_4_28_bad_domains),
NULL
diff --git a/drivers/firmware/arm_scmi/quirks.h b/drivers/firmware/arm_scmi/quirks.h
index 108c8d11f6043a61..67818b6cf0909f8e 100644
--- a/drivers/firmware/arm_scmi/quirks.h
+++ b/drivers/firmware/arm_scmi/quirks.h
@@ -47,6 +47,7 @@ static inline void scmi_quirks_enable(struct device *dev, const char *vend,
/* Quirk delarations */
DECLARE_SCMI_QUIRK(clock_rates_triplet_out_of_spec);
+DECLARE_SCMI_QUIRK(clock_rcar_x5h_no_attributes);
DECLARE_SCMI_QUIRK(perf_level_get_fc_force);
DECLARE_SCMI_QUIRK(power_rcar_x5h_4_28_bad_domains);
--
2.43.0
^ permalink raw reply related
* [PATCH/RFC 03/14] firmware: arm_scmi: quirk: Handle critical clocks on R-Car X5H
From: Geert Uytterhoeven @ 2026-04-21 18:11 UTC (permalink / raw)
To: Sudeep Holla, Cristian Marussi, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Magnus Damm, Saravana Kannan, Michael Turquette,
Stephen Boyd, Philipp Zabel, Ulf Hansson, Rafael J . Wysocki,
Kevin Hilman, Florian Fainelli, Wolfram Sang, Marek Vasut,
Kuninori Morimoto
Cc: arm-scmi, linux-arm-kernel, linux-renesas-soc, linux-clk,
devicetree, linux-pm, linux-kernel, Geert Uytterhoeven
In-Reply-To: <cover.1776793163.git.geert+renesas@glider.be>
Renesas R-Car X5H SCP FW SDKv4.28.0, v4.31.0, and v4.32.0 advertise a
few clocks that crash the system when disabled. Add quirks to prevent
such crashes.
As SCMI clock IDs are identical for SDKv4.31.0 and v4.32.0, the quirk
for these two versions can be shared.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Some of these could be handled by improving hardware descriptions in DT,
or by the CPG and MDLC drivers.
---
drivers/firmware/arm_scmi/clock.c | 23 +++++++++++++++++++++++
drivers/firmware/arm_scmi/quirks.c | 6 ++++++
drivers/firmware/arm_scmi/quirks.h | 2 ++
3 files changed, 31 insertions(+)
diff --git a/drivers/firmware/arm_scmi/clock.c b/drivers/firmware/arm_scmi/clock.c
index d530882a0bac88c3..4fec8c3216df7a51 100644
--- a/drivers/firmware/arm_scmi/clock.c
+++ b/drivers/firmware/arm_scmi/clock.c
@@ -920,6 +920,26 @@ scmi_clock_config_set_v2(const struct scmi_protocol_handle *ph, u32 clk_id,
return ret;
}
+#define QUIRK_RCAR_X5H_4_28_CRIT_CLOCKS \
+ ({ \
+ switch (clk_id) { \
+ case 468: /* MDLC_INTAP0 */ \
+ case 498: /* MDLC_APRTMGINT0 */ \
+ case 840: /* CLK_ZD_APU0 */ \
+ return -EPERM; \
+ } \
+ })
+
+#define QUIRK_RCAR_X5H_4_31_CRIT_CLOCKS \
+ ({ \
+ switch (clk_id) { \
+ case 464: /* MDLC_INTAP0 */ \
+ case 494: /* MDLC_APRTMGINT0 */ \
+ case 836: /* CLK_ZD_APU0 */ \
+ return -EPERM; \
+ } \
+ })
+
static int scmi_clock_enable(const struct scmi_protocol_handle *ph, u32 clk_id,
bool atomic)
{
@@ -950,6 +970,9 @@ static int scmi_clock_disable(const struct scmi_protocol_handle *ph, u32 clk_id,
if (clk->state_ctrl_forbidden)
return -EACCES;
+ SCMI_QUIRK(clock_rcar_x5h_4_28_crit_clocks, QUIRK_RCAR_X5H_4_28_CRIT_CLOCKS);
+ SCMI_QUIRK(clock_rcar_x5h_4_31_crit_clocks, QUIRK_RCAR_X5H_4_31_CRIT_CLOCKS);
+
return ci->clock_config_set(ph, clk_id, CLK_STATE_DISABLE,
NULL_OEM_TYPE, 0, atomic);
}
diff --git a/drivers/firmware/arm_scmi/quirks.c b/drivers/firmware/arm_scmi/quirks.c
index e27c21b14220ab5f..4ca6d06f85ebc7b2 100644
--- a/drivers/firmware/arm_scmi/quirks.c
+++ b/drivers/firmware/arm_scmi/quirks.c
@@ -173,6 +173,10 @@ struct scmi_quirk {
DEFINE_SCMI_QUIRK(clock_rates_triplet_out_of_spec, NULL, NULL, NULL);
DEFINE_SCMI_QUIRK(clock_rcar_x5h_no_attributes, "Renesas", NULL, "0x10a0000-",
"renesas,r8a78000");
+DEFINE_SCMI_QUIRK(clock_rcar_x5h_4_28_crit_clocks, "Renesas", NULL, "0x10a0000",
+ "renesas,r8a78000");
+DEFINE_SCMI_QUIRK(clock_rcar_x5h_4_31_crit_clocks, "Renesas", NULL,
+ "0x10d0000-0x10e0000", "renesas,r8a78000");
DEFINE_SCMI_QUIRK(perf_level_get_fc_force, "Qualcomm", NULL, "0x20000-");
DEFINE_SCMI_QUIRK(power_rcar_x5h_4_28_bad_domains, "Renesas", NULL,
"0x10a0000-0x10e0000", "renesas,r8a78000");
@@ -186,6 +190,8 @@ DEFINE_SCMI_QUIRK(power_rcar_x5h_4_28_bad_domains, "Renesas", NULL,
static struct scmi_quirk *scmi_quirks_table[] = {
__DECLARE_SCMI_QUIRK_ENTRY(clock_rates_triplet_out_of_spec),
__DECLARE_SCMI_QUIRK_ENTRY(clock_rcar_x5h_no_attributes),
+ __DECLARE_SCMI_QUIRK_ENTRY(clock_rcar_x5h_4_28_crit_clocks),
+ __DECLARE_SCMI_QUIRK_ENTRY(clock_rcar_x5h_4_31_crit_clocks),
__DECLARE_SCMI_QUIRK_ENTRY(perf_level_get_fc_force),
__DECLARE_SCMI_QUIRK_ENTRY(power_rcar_x5h_4_28_bad_domains),
NULL
diff --git a/drivers/firmware/arm_scmi/quirks.h b/drivers/firmware/arm_scmi/quirks.h
index 67818b6cf0909f8e..56adb5fa87de0127 100644
--- a/drivers/firmware/arm_scmi/quirks.h
+++ b/drivers/firmware/arm_scmi/quirks.h
@@ -48,6 +48,8 @@ static inline void scmi_quirks_enable(struct device *dev, const char *vend,
/* Quirk delarations */
DECLARE_SCMI_QUIRK(clock_rates_triplet_out_of_spec);
DECLARE_SCMI_QUIRK(clock_rcar_x5h_no_attributes);
+DECLARE_SCMI_QUIRK(clock_rcar_x5h_4_28_crit_clocks);
+DECLARE_SCMI_QUIRK(clock_rcar_x5h_4_31_crit_clocks);
DECLARE_SCMI_QUIRK(perf_level_get_fc_force);
DECLARE_SCMI_QUIRK(power_rcar_x5h_4_28_bad_domains);
--
2.43.0
^ permalink raw reply related
* [PATCH/RFC 04/14] arm64: dts: renesas: ironhide: Enable SCMI devpd, sys, and reset
From: Geert Uytterhoeven @ 2026-04-21 18:11 UTC (permalink / raw)
To: Sudeep Holla, Cristian Marussi, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Magnus Damm, Saravana Kannan, Michael Turquette,
Stephen Boyd, Philipp Zabel, Ulf Hansson, Rafael J . Wysocki,
Kevin Hilman, Florian Fainelli, Wolfram Sang, Marek Vasut,
Kuninori Morimoto
Cc: arm-scmi, linux-arm-kernel, linux-renesas-soc, linux-clk,
devicetree, linux-pm, linux-kernel, Geert Uytterhoeven
In-Reply-To: <cover.1776793163.git.geert+renesas@glider.be>
SCP FW SDKv4.28.0 and later for Renesas R-Car X5H Ironhide not only
implements the SCMI base and clock management protocols, but also the
SCMI power domain, system power, and reset domain management protocols.
Enable support for the latter by adding the corresponding SCMI protocol
subnodes.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts b/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts
index e2470257d2f32a03..2fb9557a7eb9dbb7 100644
--- a/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts
+++ b/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts
@@ -31,10 +31,24 @@ scmi: scmi {
#address-cells = <1>;
#size-cells = <0>;
+ scmi_devpd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi_sys: protocol@12 {
+ reg = <0x12>;
+ };
+
scmi_clk: protocol@14 {
reg = <0x14>;
#clock-cells = <1>;
};
+
+ scmi_reset: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
};
};
--
2.43.0
^ permalink raw reply related
* [PATCH/RFC 05/14] firmware: arm_scmi: Add scmi_get_base_info()
From: Geert Uytterhoeven @ 2026-04-21 18:11 UTC (permalink / raw)
To: Sudeep Holla, Cristian Marussi, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Magnus Damm, Saravana Kannan, Michael Turquette,
Stephen Boyd, Philipp Zabel, Ulf Hansson, Rafael J . Wysocki,
Kevin Hilman, Florian Fainelli, Wolfram Sang, Marek Vasut,
Kuninori Morimoto
Cc: arm-scmi, linux-arm-kernel, linux-renesas-soc, linux-clk,
devicetree, linux-pm, linux-kernel, Geert Uytterhoeven
In-Reply-To: <cover.1776793163.git.geert+renesas@glider.be>
Currently non-SCMI drivers cannot find out what the specific versions of
each SCMI provider implementation on the running system are.
However, different versions may use different ABIs (e.g. different clock
IDs), or behave different, requiring remapping or workarounds in other
drivers.
Add a public function to obtain base protocol information for the
selected SCMI provider. This will be used by the R-Car X5H Clock Pulse
Generator and Module Controller drivers.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/firmware/arm_scmi/driver.c | 31 ++++++++++++++++++++++++++++++
include/linux/scmi_protocol.h | 8 ++++++++
2 files changed, 39 insertions(+)
diff --git a/drivers/firmware/arm_scmi/driver.c b/drivers/firmware/arm_scmi/driver.c
index 3e0d975ec94c4485..dfa8961775aa952d 100644
--- a/drivers/firmware/arm_scmi/driver.c
+++ b/drivers/firmware/arm_scmi/driver.c
@@ -3504,6 +3504,37 @@ int scmi_inflight_count(const struct scmi_handle *handle)
}
}
+/**
+ * scmi_get_base_info() - Get SCMI base protocol information
+ *
+ * @of_node: pointer to a device node for an SCMI provider
+ * @version: pointer to write base protocol information
+ *
+ * Check if an SCMI device has been instantiated for the passed device node
+ * pointer, and, if found, return its base info.
+
+ * Return: 0 on Success or -ENOENT.
+ */
+int scmi_get_base_info(struct device_node *of_node,
+ struct scmi_base_info *version)
+{
+ struct scmi_info *info;
+ int ret = -ENOENT;
+
+ mutex_lock(&scmi_list_mutex);
+ list_for_each_entry(info, &scmi_list, node) {
+ if (info->dev->of_node == of_node) {
+ *version = info->version;
+ ret = 0;
+ break;
+ }
+ }
+ mutex_unlock(&scmi_list_mutex);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(scmi_get_base_info);
+
static int __init scmi_driver_init(void)
{
scmi_quirks_initialize();
diff --git a/include/linux/scmi_protocol.h b/include/linux/scmi_protocol.h
index 49cc39e0cbca5a0b..52eba920de264bd7 100644
--- a/include/linux/scmi_protocol.h
+++ b/include/linux/scmi_protocol.h
@@ -972,6 +972,8 @@ struct scmi_driver {
int scmi_driver_register(struct scmi_driver *driver,
struct module *owner, const char *mod_name);
void scmi_driver_unregister(struct scmi_driver *driver);
+int scmi_get_base_info(struct device_node *of_node,
+ struct scmi_base_info *version);
#else
static inline int
scmi_driver_register(struct scmi_driver *driver, struct module *owner,
@@ -981,6 +983,12 @@ scmi_driver_register(struct scmi_driver *driver, struct module *owner,
}
static inline void scmi_driver_unregister(struct scmi_driver *driver) {}
+
+static inline int scmi_get_base_info(struct device_node *of_node,
+ struct scmi_base_info *version)
+{
+ return -ENOENT;
+}
#endif /* CONFIG_ARM_SCMI_PROTOCOL */
#define scmi_register(driver) \
--
2.43.0
^ permalink raw reply related
* [PATCH/RFC 06/14] of: property: fw_devlink: Add support for firmware
From: Geert Uytterhoeven @ 2026-04-21 18:11 UTC (permalink / raw)
To: Sudeep Holla, Cristian Marussi, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Magnus Damm, Saravana Kannan, Michael Turquette,
Stephen Boyd, Philipp Zabel, Ulf Hansson, Rafael J . Wysocki,
Kevin Hilman, Florian Fainelli, Wolfram Sang, Marek Vasut,
Kuninori Morimoto
Cc: arm-scmi, linux-arm-kernel, linux-renesas-soc, linux-clk,
devicetree, linux-pm, linux-kernel, Geert Uytterhoeven
In-Reply-To: <cover.1776793163.git.geert+renesas@glider.be>
Let fw_devlink create device links between consumers and suppliers of
firmware, and enforce these dependencies.
This prevents probing of drivers before the firmware they depend on
becomes available, thus avoiding unneeded probe deferrals.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Written for the upcoming R-Car X5H Clock Pulse Generator and Module
Controller drivers and their dependency on SCMI, but the existing
Raspberry Pi power domain driver should benefit from this, too.
---
drivers/of/property.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/of/property.c b/drivers/of/property.c
index 136946f8b746f745..34aeba20040348d6 100644
--- a/drivers/of/property.c
+++ b/drivers/of/property.c
@@ -1378,6 +1378,7 @@ DEFINE_SIMPLE_PROP(dmas, "dmas", "#dma-cells")
DEFINE_SIMPLE_PROP(power_domains, "power-domains", "#power-domain-cells")
DEFINE_SIMPLE_PROP(hwlocks, "hwlocks", "#hwlock-cells")
DEFINE_SIMPLE_PROP(extcon, "extcon", NULL)
+DEFINE_SIMPLE_PROP(firmware, "firmware", NULL)
DEFINE_SIMPLE_PROP(nvmem_cells, "nvmem-cells", "#nvmem-cell-cells")
DEFINE_SIMPLE_PROP(phys, "phys", "#phy-cells")
DEFINE_SIMPLE_PROP(wakeup_parent, "wakeup-parent", NULL)
@@ -1527,6 +1528,7 @@ static const struct supplier_bindings of_supplier_bindings[] = {
{ .parse_prop = parse_power_domains, },
{ .parse_prop = parse_hwlocks, },
{ .parse_prop = parse_extcon, },
+ { .parse_prop = parse_firmware, },
{ .parse_prop = parse_nvmem_cells, },
{ .parse_prop = parse_phys, },
{ .parse_prop = parse_wakeup_parent, },
--
2.43.0
^ permalink raw reply related
* [PATCH/RFC 07/14] pmdomain: Make genpd_get_from_provider() public
From: Geert Uytterhoeven @ 2026-04-21 18:11 UTC (permalink / raw)
To: Sudeep Holla, Cristian Marussi, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Magnus Damm, Saravana Kannan, Michael Turquette,
Stephen Boyd, Philipp Zabel, Ulf Hansson, Rafael J . Wysocki,
Kevin Hilman, Florian Fainelli, Wolfram Sang, Marek Vasut,
Kuninori Morimoto
Cc: arm-scmi, linux-arm-kernel, linux-renesas-soc, linux-clk,
devicetree, linux-pm, linux-kernel, Geert Uytterhoeven
In-Reply-To: <cover.1776793163.git.geert+renesas@glider.be>
Unlike the corresponding function in the clock subsystem
(of_clk_get_from_provider()), genpd_get_from_provider() is private, and
thus cannot be used by PM Domain drivers.
Make it public, so it be used by the R-Car X5H Module Controller driver.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pmdomain/core.c | 4 ++--
include/linux/pm_domain.h | 7 +++++++
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/pmdomain/core.c b/drivers/pmdomain/core.c
index 4d32fc676aaf53cf..23c7cd480a7e026d 100644
--- a/drivers/pmdomain/core.c
+++ b/drivers/pmdomain/core.c
@@ -2900,8 +2900,7 @@ EXPORT_SYMBOL_GPL(of_genpd_del_provider);
* Returns a valid pointer to struct generic_pm_domain on success or ERR_PTR()
* on failure.
*/
-static struct generic_pm_domain *genpd_get_from_provider(
- const struct of_phandle_args *genpdspec)
+struct generic_pm_domain *genpd_get_from_provider(const struct of_phandle_args *genpdspec)
{
struct generic_pm_domain *genpd = ERR_PTR(-ENOENT);
struct of_genpd_provider *provider;
@@ -2923,6 +2922,7 @@ static struct generic_pm_domain *genpd_get_from_provider(
return genpd;
}
+EXPORT_SYMBOL_GPL(genpd_get_from_provider);
/**
* of_genpd_add_device() - Add a device to an I/O PM domain
diff --git a/include/linux/pm_domain.h b/include/linux/pm_domain.h
index b299dc0128d65ee5..568aebf51d830210 100644
--- a/include/linux/pm_domain.h
+++ b/include/linux/pm_domain.h
@@ -458,6 +458,7 @@ int of_genpd_add_provider_simple(struct device_node *np,
int of_genpd_add_provider_onecell(struct device_node *np,
struct genpd_onecell_data *data);
void of_genpd_del_provider(struct device_node *np);
+struct generic_pm_domain *genpd_get_from_provider(const struct of_phandle_args *genpdspec);
int of_genpd_add_device(const struct of_phandle_args *args, struct device *dev);
int of_genpd_add_subdomain(const struct of_phandle_args *parent_spec,
const struct of_phandle_args *subdomain_spec);
@@ -488,6 +489,12 @@ static inline int of_genpd_add_provider_onecell(struct device_node *np,
static inline void of_genpd_del_provider(struct device_node *np) {}
+static inline struct generic_pm_domain *genpd_get_from_provider(
+ const struct of_phandle_args *genpdspec)
+{
+ return ERR_PTR(-ENODEV);
+}
+
static inline int of_genpd_add_device(const struct of_phandle_args *args,
struct device *dev)
{
--
2.43.0
^ permalink raw reply related
* [PATCH/RFC 08/14] reset: Add reset_controller_get_provider()
From: Geert Uytterhoeven @ 2026-04-21 18:11 UTC (permalink / raw)
To: Sudeep Holla, Cristian Marussi, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Magnus Damm, Saravana Kannan, Michael Turquette,
Stephen Boyd, Philipp Zabel, Ulf Hansson, Rafael J . Wysocki,
Kevin Hilman, Florian Fainelli, Wolfram Sang, Marek Vasut,
Kuninori Morimoto
Cc: arm-scmi, linux-arm-kernel, linux-renesas-soc, linux-clk,
devicetree, linux-pm, linux-kernel, Geert Uytterhoeven
In-Reply-To: <cover.1776793163.git.geert+renesas@glider.be>
The reset subsystem differs from the clock subsystem in multiple ways:
1. It does not provide a public way to lookup resets from a reset
provider (clock has of_clk_get_from_provider()),
2. The xlate callback does not return a reset object, but merely an
index, which is converted to a reset object by the reset core.
Hence add a public helper reset_controller_get_provider(), which just
returns the provider, and will be used by the R-Car X5H Module
Controller driver.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/reset/core.c | 11 +++++++++++
include/linux/reset-controller.h | 6 ++++++
2 files changed, 17 insertions(+)
diff --git a/drivers/reset/core.c b/drivers/reset/core.c
index 38e189d04d09b270..57c427bb33b322e2 100644
--- a/drivers/reset/core.c
+++ b/drivers/reset/core.c
@@ -1135,6 +1135,17 @@ __reset_find_rcdev(const struct fwnode_reference_args *args, bool gpio_fallback)
return NULL;
}
+struct reset_controller_dev *
+reset_controller_get_provider(struct fwnode_handle *fwnode)
+{
+ struct fwnode_reference_args args = { .fwnode = fwnode };
+
+ guard(mutex)(&reset_list_mutex);
+
+ return __reset_find_rcdev(&args, false);
+}
+EXPORT_SYMBOL_GPL(reset_controller_get_provider);
+
struct reset_control *
__fwnode_reset_control_get(struct fwnode_handle *fwnode, const char *id, int index,
enum reset_control_flags flags)
diff --git a/include/linux/reset-controller.h b/include/linux/reset-controller.h
index 52a5a4e81f184407..0c17a36466115ba6 100644
--- a/include/linux/reset-controller.h
+++ b/include/linux/reset-controller.h
@@ -74,6 +74,7 @@ void reset_controller_unregister(struct reset_controller_dev *rcdev);
struct device;
int devm_reset_controller_register(struct device *dev,
struct reset_controller_dev *rcdev);
+struct reset_controller_dev *reset_controller_get_provider(struct fwnode_handle *fwnode);
#else
static inline int reset_controller_register(struct reset_controller_dev *rcdev)
{
@@ -89,6 +90,11 @@ static inline int devm_reset_controller_register(struct device *dev,
{
return 0;
}
+
+static inline struct reset_controller_dev *reset_controller_get_provider(struct fwnode_handle *fwnode)
+{
+ return NULL;
+}
#endif
#endif
--
2.43.0
^ permalink raw reply related
* [PATCH/RFC 09/14] dt-bindings: clock: Document Renesas R-Car X5H Clock Pulse Generator
From: Geert Uytterhoeven @ 2026-04-21 18:11 UTC (permalink / raw)
To: Sudeep Holla, Cristian Marussi, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Magnus Damm, Saravana Kannan, Michael Turquette,
Stephen Boyd, Philipp Zabel, Ulf Hansson, Rafael J . Wysocki,
Kevin Hilman, Florian Fainelli, Wolfram Sang, Marek Vasut,
Kuninori Morimoto
Cc: arm-scmi, linux-arm-kernel, linux-renesas-soc, linux-clk,
devicetree, linux-pm, linux-kernel, Geert Uytterhoeven
In-Reply-To: <cover.1776793163.git.geert+renesas@glider.be>
Document support for the Renesas R-Car X5H Clock Pulse Generator,
and add definitions for a very limited and preliminary set of clocks.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
.../bindings/clock/renesas,r8a78000-cpg.yaml | 62 +++++++++++++++++++
.../dt-bindings/clock/renesas,r8a78000-cpg.h | 15 +++++
2 files changed, 77 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/renesas,r8a78000-cpg.yaml
create mode 100644 include/dt-bindings/clock/renesas,r8a78000-cpg.h
diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a78000-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,r8a78000-cpg.yaml
new file mode 100644
index 0000000000000000..fc499e7cf52e4f0c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,r8a78000-cpg.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/renesas,r8a78000-cpg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas R-Car X5H Clock Pulse Generator
+
+maintainers:
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+
+description:
+ The R-Car X5H Clock Pulse Generator (CLK CONTROL) consists of oscillators,
+ PLL circuits, clock dividers and clock control circuits. It provides various
+ clocks for other modules.
+
+properties:
+ compatible:
+ const: renesas,r8a78000-cpg
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: extal
+ - const: extalr
+
+ '#clock-cells':
+ description:
+ The single clock specifier cell must be the clock number, as defined in
+ <dt-bindings/clock/renesas,r8a78000-cpg.h>.
+ const: 1
+
+ firmware:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Reference to the SCMI firmware device node on systems where SCMI must be
+ used instead of direct hardware access.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@c1320000 {
+ compatible = "renesas,r8a78000-cpg";
+ reg = <0xc1320000 0x10000>;
+ clocks = <&extal_clk>, <&extalr_clk>;
+ clock-names = "extal", "extalr";
+ #clock-cells = <1>;
+ firmware = <&scmi>;
+ };
diff --git a/include/dt-bindings/clock/renesas,r8a78000-cpg.h b/include/dt-bindings/clock/renesas,r8a78000-cpg.h
new file mode 100644
index 0000000000000000..8c8bc4d1feac6d26
--- /dev/null
+++ b/include/dt-bindings/clock/renesas,r8a78000-cpg.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2026 Glider bv
+ */
+#ifndef __DT_BINDINGS_CLOCK_RENESAS_R8A78000_CPG_H__
+#define __DT_BINDINGS_CLOCK_RENESAS_R8A78000_CPG_H__
+
+/* R-Car X5H CPG Clocks */
+
+// FIXME Preliminary
+#define R8A78000_CPG_SGASYNCD4_PERW_BUS 0
+#define R8A78000_CPG_SGASYNCD16_PERW_BUS 1
+#define R8A78000_CPG_MSOCK_PERW_BUS 2
+
+#endif /* __DT_BINDINGS_CLOCK_RENESAS_R8A78000_CPG_H__ */
--
2.43.0
^ permalink raw reply related
* [PATCH/RFC 10/14] dt-bindings: power: Document Renesas R-Car X5H Module Controller
From: Geert Uytterhoeven @ 2026-04-21 18:11 UTC (permalink / raw)
To: Sudeep Holla, Cristian Marussi, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Magnus Damm, Saravana Kannan, Michael Turquette,
Stephen Boyd, Philipp Zabel, Ulf Hansson, Rafael J . Wysocki,
Kevin Hilman, Florian Fainelli, Wolfram Sang, Marek Vasut,
Kuninori Morimoto
Cc: arm-scmi, linux-arm-kernel, linux-renesas-soc, linux-clk,
devicetree, linux-pm, linux-kernel, Geert Uytterhoeven
In-Reply-To: <cover.1776793163.git.geert+renesas@glider.be>
Document support for Renesas R-Car X5H Module Controllers, and
add definitions for power domains not backed by registers.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
.../bindings/power/renesas,r8a78000-mdlc.yaml | 63 +++++++++++++++++++
.../dt-bindings/power/renesas,r8a78000-mdlc.h | 16 +++++
2 files changed, 79 insertions(+)
create mode 100644 Documentation/devicetree/bindings/power/renesas,r8a78000-mdlc.yaml
create mode 100644 include/dt-bindings/power/renesas,r8a78000-mdlc.h
diff --git a/Documentation/devicetree/bindings/power/renesas,r8a78000-mdlc.yaml b/Documentation/devicetree/bindings/power/renesas,r8a78000-mdlc.yaml
new file mode 100644
index 0000000000000000..c3075bb308962f59
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/renesas,r8a78000-mdlc.yaml
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/power/renesas,r8a78000-mdlc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas R-Car X5H Module Controller
+
+maintainers:
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+
+description:
+ Each instance of the R-Car X5H Module Controller (MODULE CONTROL) provides
+ Power Gating for up to 64 Power Domains, and Module Standby and Reset for up
+ to 256 modules in the Power Domain of each Module hierarchy.
+
+properties:
+ compatible:
+ const: renesas,r8a78000-mdlc
+
+ reg:
+ maxItems: 1
+
+ '#power-domain-cells':
+ description: |
+ - The first power domain specifier cell must be either the Module
+ Power Domain Gating (MPDG) register index (0x00-0x3f) from the
+ datasheet, or a Power Domain number, as defined in
+ <dt-bindings/power/renesas,r8a78000-mdlc.h>,
+ - The second power domain specifier cell must be the module number
+ (0x00-0xff), composed of the Module System Reset (MSRES) register index
+ in the high nibble, and the Module Reset Destination bitfield index in
+ the low nibble.
+ const: 2
+
+ '#reset-cells':
+ description:
+ The single reset specifier cell must be the module number (0x00-0xff).
+ const: 1
+
+ firmware:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Reference to the SCMI firmware device node on systems where SCMI must be
+ used instead of direct hardware access.
+
+required:
+ - compatible
+ - reg
+ - '#power-domain-cells'
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ system-controller@c3060000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0xc3060000 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ firmware = <&scmi>;
+ };
diff --git a/include/dt-bindings/power/renesas,r8a78000-mdlc.h b/include/dt-bindings/power/renesas,r8a78000-mdlc.h
new file mode 100644
index 0000000000000000..31aa4935a7c5cf94
--- /dev/null
+++ b/include/dt-bindings/power/renesas,r8a78000-mdlc.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2026 Glider bv
+ */
+#ifndef __DT_BINDINGS_POWER_RENESAS_R8A78000_MDLC_H__
+#define __DT_BINDINGS_POWER_RENESAS_R8A78000_MDLC_H__
+
+/* R-Car X5H MDLC Power Domains */
+
+#define R8A78000_MDLC_PD_AON 0x40
+#define R8A78000_MDLC_PD_SCP 0x41
+#define R8A78000_MDLC_PD_APL 0x42
+#define R8A78000_MDLC_PD_CMN 0x43
+#define R8A78000_MDLC_PD_ACL 0x44
+
+#endif /* __DT_BINDINGS_POWER_RENESAS_R8A78000_MDLC_H__ */
--
2.43.0
^ permalink raw reply related
* [PATCH/RFC 11/14] clk: renesas: Add R-Car X5H CPG SCMI remapping driver
From: Geert Uytterhoeven @ 2026-04-21 18:11 UTC (permalink / raw)
To: Sudeep Holla, Cristian Marussi, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Magnus Damm, Saravana Kannan, Michael Turquette,
Stephen Boyd, Philipp Zabel, Ulf Hansson, Rafael J . Wysocki,
Kevin Hilman, Florian Fainelli, Wolfram Sang, Marek Vasut,
Kuninori Morimoto
Cc: arm-scmi, linux-arm-kernel, linux-renesas-soc, linux-clk,
devicetree, linux-pm, linux-kernel, Geert Uytterhoeven
In-Reply-To: <cover.1776793163.git.geert+renesas@glider.be>
Add a proof-of-concept Clock Pulse Generator driver for the R-Car X5H
(R8A78000) SoC, using tables to remap from hardware clock IDs to SCMI
clock IDs.
Some SCMI clocks do not support the SCMI CLOCK_ATTRIBUTES command, and
are thus not usable from Linux. Register a bunch of fixed-rate clocks,
and use them as replacements for SCMI clocks that are known to be
unusable.
For now this contains preliminary support for SCP FW SDKv4.28.0,
v4.31.0, and v4.32.0. As SCMI clock IDs are identical for SDKv4.31.0
and v4.32.0, r8a78000_cpg_fw_4_31_0[] applies to both of them.
Suggested-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/clk/renesas/Kconfig | 4 +
drivers/clk/renesas/Makefile | 1 +
drivers/clk/renesas/r8a78000-cpg.c | 335 +++++++++++++++++++++++++++++
3 files changed, 340 insertions(+)
create mode 100644 drivers/clk/renesas/r8a78000-cpg.c
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index 0203ecbb38825f13..f0482bdfc4616cfa 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -34,6 +34,7 @@ config CLK_RENESAS
select CLK_R8A779F0 if ARCH_R8A779F0
select CLK_R8A779G0 if ARCH_R8A779G0
select CLK_R8A779H0 if ARCH_R8A779H0
+ select CLK_R8A78000 if ARCH_R8A78000
select CLK_R9A06G032 if ARCH_R9A06G032
select CLK_R9A07G043 if ARCH_R9A07G043
select CLK_R9A07G044 if ARCH_R9A07G044
@@ -176,6 +177,9 @@ config CLK_R8A779H0
bool "R-Car V4M clock support" if COMPILE_TEST
select CLK_RCAR_GEN4_CPG
+config CLK_R8A78000
+ bool "R-Car X5H clock support" if COMPILE_TEST
+
config CLK_R9A06G032
bool "RZ/N1D clock support" if COMPILE_TEST
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile
index bd2bed91ab291d72..4f76f8c402ffe9a3 100644
--- a/drivers/clk/renesas/Makefile
+++ b/drivers/clk/renesas/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o
obj-$(CONFIG_CLK_R8A779F0) += r8a779f0-cpg-mssr.o
obj-$(CONFIG_CLK_R8A779G0) += r8a779g0-cpg-mssr.o
obj-$(CONFIG_CLK_R8A779H0) += r8a779h0-cpg-mssr.o
+obj-$(CONFIG_CLK_R8A78000) += r8a78000-cpg.o
obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
obj-$(CONFIG_CLK_R9A07G043) += r9a07g043-cpg.o
obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o
diff --git a/drivers/clk/renesas/r8a78000-cpg.c b/drivers/clk/renesas/r8a78000-cpg.c
new file mode 100644
index 0000000000000000..844d909bbee2adbb
--- /dev/null
+++ b/drivers/clk/renesas/r8a78000-cpg.c
@@ -0,0 +1,335 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * R-Car X5H Clock Pulse Generator
+ *
+ * Copyright (C) 2026 Glider bv
+ */
+
+#include <linux/cleanup.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/dev_printk.h>
+#include <linux/module.h>
+#include <linux/mod_devicetable.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/scmi_protocol.h>
+#include <linux/slab.h>
+
+#include <dt-bindings/clock/renesas,r8a78000-cpg.h>
+
+struct clk_map_in {
+ int dt_id; /* DT binding clock ID */
+ u32 fw_id; /* SCMI firmware clock ID */
+};
+
+struct clk_map {
+ int dt_id; /* DT binding clock ID */
+ u32 fw_id; /* SCMI firmware clock ID */
+ struct clk_hw *hw;
+};
+
+struct fw_map {
+ u32 impl_ver;
+ const struct clk_map_in *map;
+};
+
+enum fixed_clk {
+ FIXED_CLK_66M,
+ FIXED_CLK_266M,
+ NUM_FIXED_CLKS
+};
+
+static const unsigned long fixed_clk_rates[NUM_FIXED_CLKS] = {
+ [FIXED_CLK_66M] = 66666000,
+ [FIXED_CLK_266M] = 266660000,
+};
+
+#define FIXED_CLK_OFFSET 0x80000000
+#define FIXED_CLK(rate) FIXED_CLK_OFFSET + FIXED_CLK_ ## rate
+
+/**
+ * struct r8a78000_cpg_priv - Clock Pulse Generator Private Data
+ *
+ * @dev: CPG device
+ * @scmi_clk_np: Device node in DT for the SCMI firmware clock protocol
+ * @map: Mapping from DT clock IDs to SCMI clocks
+ * @fixed_hws: Fixed rate clocks used to replace SCMI clocks that do not
+ * support the SCMI CLOCK_ATTRIBUTES command
+ */
+struct r8a78000_cpg_priv {
+ struct device *dev;
+ struct device_node *scmi_clk_np;
+ const struct clk_map *map;
+ struct clk_hw *fixed_hws[NUM_FIXED_CLKS];
+};
+
+static const struct clk_map *clk_map_find(const struct clk_map *map, u32 id)
+{
+ if (!map)
+ return NULL;
+
+ for (; map->dt_id >= 0; map++) {
+ if (map->dt_id == id)
+ return map;
+ }
+
+ return NULL;
+}
+
+static struct clk_hw *r8a78000_clk_get(struct of_phandle_args *spec,
+ void *data)
+{
+ struct r8a78000_cpg_priv *priv = data;
+ struct device *dev = priv->dev;
+ const struct clk_map *map;
+ struct clk_hw *hw;
+ u32 id;
+
+ if (spec->args_count != 1)
+ return ERR_PTR(-EINVAL);
+
+ id = spec->args[0];
+
+ map = clk_map_find(priv->map, id);
+ if (!map) {
+ dev_err(dev, "Unknown clock %u\n", id);
+ return ERR_PTR(-ENOENT);
+ }
+
+ if (map->fw_id < FIXED_CLK_OFFSET)
+ dev_dbg(dev, "Mapping DT clock %u to SCMI clock %u\n", id,
+ map->fw_id);
+ else
+ dev_dbg(dev, "Mapping DT clock %u to fixed clock %u\n", id,
+ map->fw_id - FIXED_CLK_OFFSET);
+
+ hw = map->hw;
+ if (!hw) {
+ /* CLOCK_ATTRIBUTES is not supported */
+ dev_err(dev, "Clock %u is not available\n", id);
+ return ERR_PTR(-ENOENT);
+ }
+
+ dev_dbg(dev, "clock %u is %s at %lu Hz\n", id, clk_hw_get_name(hw),
+ clk_hw_get_rate(hw));
+
+ return hw;
+}
+
+static struct device_node *scmi_find_proto(struct device_node *scmi, u32 proto)
+{
+ for_each_available_child_of_node_scoped(scmi, child) {
+ u32 reg;
+
+ if (of_property_read_u32(child, "reg", ®))
+ continue;
+
+ if (reg == proto)
+ return_ptr(child);
+ }
+
+ return NULL;
+}
+
+static void unregister_fixed_clks(void *data)
+{
+ struct r8a78000_cpg_priv *priv = data;
+
+ for (unsigned int i = 0; i < ARRAY_SIZE(priv->fixed_hws); i++)
+ clk_hw_unregister_fixed_rate(priv->fixed_hws[i]);
+}
+
+static int register_fixed_clks(struct r8a78000_cpg_priv *priv)
+{
+ struct device *dev = priv->dev;
+ unsigned long rate;
+ struct clk_hw *hw;
+ const char *name;
+
+ for (unsigned int i = 0; i < ARRAY_SIZE(fixed_clk_rates); i++) {
+ rate = fixed_clk_rates[i];
+ name = devm_kasprintf(dev, GFP_KERNEL, "cpg-%lu", rate);
+ if (!name)
+ return -ENOMEM;
+
+ hw = clk_hw_register_fixed_rate(dev, name, NULL, 0, rate);
+ if (IS_ERR(hw)) {
+ while (i-- > 0)
+ clk_hw_unregister_fixed_rate(priv->fixed_hws[i]);
+ return PTR_ERR(hw);
+ }
+
+ priv->fixed_hws[i] = hw;
+ }
+
+ return devm_add_action_or_reset(dev, unregister_fixed_clks, priv);
+}
+
+static const struct clk_map *fill_clk_map(struct r8a78000_cpg_priv *priv,
+ const struct clk_map_in *map_in)
+{
+ struct of_phandle_args scmi_spec;
+ struct device *dev = priv->dev;
+ struct clk_map *map;
+ struct clk_hw *hw;
+ struct clk *clk;
+ unsigned int i;
+
+ for (i = 0; map_in[i].dt_id >= 0; i++) { }
+
+ map = devm_kcalloc(dev, i + 1, sizeof(*map), GFP_KERNEL);
+ if (!map)
+ return ERR_PTR(-ENOMEM);
+
+ for (i = 0; ; i++) {
+ map[i].dt_id = map_in[i].dt_id;
+ if (map[i].dt_id < 0)
+ break;
+
+ map[i].fw_id = map_in[i].fw_id;
+ if (map[i].fw_id >= FIXED_CLK_OFFSET) {
+ enum fixed_clk idx = map[i].fw_id - FIXED_CLK_OFFSET;
+
+ map[i].hw = priv->fixed_hws[idx];
+ continue;
+ }
+
+ scmi_spec.np = priv->scmi_clk_np;
+ scmi_spec.args_count = 1;
+ scmi_spec.args[0] = map[i].fw_id;
+
+ clk = of_clk_get_from_provider(&scmi_spec);
+ if (IS_ERR(clk))
+ return dev_err_cast_probe(dev, clk,
+ "Failed to get SCMI clock %u\n",
+ map[i].fw_id);
+
+ hw = __clk_get_hw(clk);
+ if (IS_ERR(hw))
+ return dev_err_cast_probe(dev, hw,
+ "Failed to get SCMI clock hw %u\n",
+ map[i].fw_id);
+
+ if (!hw) {
+ /* CLOCK_ATTRIBUTES is not supported */
+ dev_warn(dev, "SCMI clock %u is NULL\n", map[i].fw_id);
+ continue;
+ }
+
+ dev_dbg(priv->dev, "SCMI clock %u is %s at %lu Hz\n",
+ map[i].fw_id, clk_hw_get_name(hw), clk_hw_get_rate(hw));
+
+ map[i].hw = hw;
+ }
+
+ return map;
+}
+
+static int r8a78000_cpg_probe(struct platform_device *pdev)
+{
+ struct device_node *scmi __free(device_node) = NULL;
+ struct device *dev = &pdev->dev;
+ struct scmi_base_info version;
+ const struct fw_map *fw_map;
+ struct r8a78000_cpg_priv *priv;
+ int ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->dev = dev;
+
+ scmi = of_parse_phandle(dev->of_node, "firmware", 0);
+ if (!scmi) {
+ dev_err(dev, "Cannot find SCMI firmware node\n");
+ return -ENODEV;
+ }
+
+ priv->scmi_clk_np = scmi_find_proto(scmi, SCMI_PROTOCOL_CLOCK);
+ if (!priv->scmi_clk_np) {
+ dev_err(dev, "Cannot find SCMI clock management protocol\n");
+ return -ENODEV;
+ }
+
+ ret = scmi_get_base_info(scmi, &version);
+ if (ret) {
+ return dev_err_probe(dev, -EPROBE_DEFER,
+ "SCMI not yet available\n");
+ }
+
+ if (strcmp(version.vendor_id, "Renesas") ||
+ strcmp(version.sub_vendor_id, "None")) {
+ return dev_err_probe(dev, -ENODEV,
+ "Unsupported SCMI firmware %s/%s\n",
+ version.vendor_id, version.sub_vendor_id);
+ }
+
+ for (fw_map = of_device_get_match_data(dev); fw_map->map; fw_map++) {
+ if (fw_map->impl_ver == version.impl_ver)
+ break;
+ }
+
+ if (!fw_map->map) {
+ return dev_err_probe(dev, -ENODEV,
+ "Unsupported SCMI version 0x%08x\n",
+ version.impl_ver);
+ }
+
+ ret = register_fixed_clks(priv);
+ if (ret)
+ return ret;
+
+ /*
+ * We cannot do lazy look-up in r8a78000_clk_get(), as that function is
+ * called with of_clk_mutex already held.
+ */
+ priv->map = fill_clk_map(priv, fw_map->map);
+ if (IS_ERR(priv->map))
+ return PTR_ERR(priv->map);
+
+ return devm_of_clk_add_hw_provider(dev, r8a78000_clk_get, priv);
+}
+
+static const struct clk_map_in r8a78000_cpg_fw_4_28_0[] = {
+ { R8A78000_CPG_SGASYNCD4_PERW_BUS, FIXED_CLK(266M) },
+ { R8A78000_CPG_SGASYNCD16_PERW_BUS, FIXED_CLK(66M) },
+ { R8A78000_CPG_MSOCK_PERW_BUS, 1671 },
+ { -1 }
+};
+
+static const struct clk_map_in r8a78000_cpg_fw_4_31_0[] = {
+ { R8A78000_CPG_SGASYNCD4_PERW_BUS, FIXED_CLK(266M) },
+ { R8A78000_CPG_SGASYNCD16_PERW_BUS, FIXED_CLK(66M) },
+ { R8A78000_CPG_MSOCK_PERW_BUS, 1667 },
+ { -1 }
+};
+
+static const struct fw_map r8a78000_cpg_fw_map[] = {
+ { 0x010a0000, r8a78000_cpg_fw_4_28_0 }, /* SCP FW SDKv4.28.0 */
+ { 0x010d0000, r8a78000_cpg_fw_4_31_0 }, /* SCP FW SDKv4.31.0 */
+ { 0x010e0000, r8a78000_cpg_fw_4_31_0 }, /* SCP FW SDKv4.32.0 */
+ { 0, NULL }
+};
+
+static const struct of_device_id r8a78000_cpg_match[] = {
+ {
+ .compatible = "renesas,r8a78000-cpg",
+ .data = &r8a78000_cpg_fw_map,
+ },
+ { /* sentinel */ }
+};
+
+static struct platform_driver r8a78000_cpg_driver = {
+ .probe = r8a78000_cpg_probe,
+ .driver = {
+ .name = "r8a78000-cpg",
+ .of_match_table = r8a78000_cpg_match,
+ .suppress_bind_attrs = true,
+ },
+};
+
+builtin_platform_driver(r8a78000_cpg_driver)
+
+MODULE_DESCRIPTION("R-Car X5H CPG Driver");
--
2.43.0
^ permalink raw reply related
* [PATCH/RFC 13/14] arm64: dts: renesas: r8a78000: Add CPG/MDLC nodes
From: Geert Uytterhoeven @ 2026-04-21 18:11 UTC (permalink / raw)
To: Sudeep Holla, Cristian Marussi, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Magnus Damm, Saravana Kannan, Michael Turquette,
Stephen Boyd, Philipp Zabel, Ulf Hansson, Rafael J . Wysocki,
Kevin Hilman, Florian Fainelli, Wolfram Sang, Marek Vasut,
Kuninori Morimoto
Cc: arm-scmi, linux-arm-kernel, linux-renesas-soc, linux-clk,
devicetree, linux-pm, linux-kernel, Geert Uytterhoeven
In-Reply-To: <cover.1776793163.git.geert+renesas@glider.be>
Add device nodes for the Clock Pulse Generator (CPG) and Module Control
(MDLC) blocks on the R-Car X5H (R8A78000) SoC.
Convert all (H)SCIF serial ports from dummy to CPG clocks, and link them
to an MDLC for power domains and resets.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Add all MDLC nodes from the start, or only when used/tested?
---
arch/arm64/boot/dts/renesas/r8a78000.dtsi | 300 ++++++++++++++++++++--
1 file changed, 275 insertions(+), 25 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
index 11922b1ac73b3af5..640b622435569461 100644
--- a/arch/arm64/boot/dts/renesas/r8a78000.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
@@ -5,6 +5,8 @@
* Copyright (C) 2025 Renesas Electronics Corp.
*/
+#include <dt-bindings/clock/renesas,r8a78000-cpg.h>
+#include <dt-bindings/power/renesas,r8a78000-mdlc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
@@ -636,23 +638,6 @@ L3_CA720_7: cache-controller-37 {
};
};
- /*
- * In the early phase, there is no clock control support,
- * so assume that the clocks are enabled by default.
- * Therefore, dummy clocks are used.
- */
- dummy_clk_sgasyncd16: dummy-clk-sgasyncd16 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <66666000>;
- };
-
- dummy_clk_sgasyncd4: dummy-clk-sgasyncd4 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <266660000>;
- };
-
extal_clk: extal-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -813,8 +798,12 @@ scif0: serial@c0700000 {
"renesas,rcar-gen5-scif", "renesas,scif";
reg = <0 0xc0700000 0 0x40>;
interrupts = <GIC_ESPI 10 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
+ clocks = <&cpg R8A78000_CPG_SGASYNCD16_PERW_BUS>,
+ <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>,
+ <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x40>;
+ resets = <&mdlc_perw 0x40>;
status = "disabled";
};
@@ -823,8 +812,12 @@ scif1: serial@c0704000 {
"renesas,rcar-gen5-scif", "renesas,scif";
reg = <0 0xc0704000 0 0x40>;
interrupts = <GIC_ESPI 11 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
+ clocks = <&cpg R8A78000_CPG_SGASYNCD16_PERW_BUS>,
+ <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>,
+ <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x41>;
+ resets = <&mdlc_perw 0x41>;
status = "disabled";
};
@@ -833,8 +826,12 @@ scif3: serial@c0708000 {
"renesas,rcar-gen5-scif", "renesas,scif";
reg = <0 0xc0708000 0 0x40>;
interrupts = <GIC_ESPI 12 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
+ clocks = <&cpg R8A78000_CPG_SGASYNCD16_PERW_BUS>,
+ <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>,
+ <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x42>;
+ resets = <&mdlc_perw 0x42>;
status = "disabled";
};
@@ -843,8 +840,12 @@ scif4: serial@c070c000 {
"renesas,rcar-gen5-scif", "renesas,scif";
reg = <0 0xc070c000 0 0x40>;
interrupts = <GIC_ESPI 13 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&dummy_clk_sgasyncd16>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
+ clocks = <&cpg R8A78000_CPG_SGASYNCD16_PERW_BUS>,
+ <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>,
+ <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x43>;
+ resets = <&mdlc_perw 0x43>;
status = "disabled";
};
@@ -853,8 +854,12 @@ hscif0: serial@c0710000 {
"renesas,rcar-gen5-hscif", "renesas,hscif";
reg = <0 0xc0710000 0 0x60>;
interrupts = <GIC_ESPI 14 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
+ clocks = <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>,
+ <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>,
+ <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x54>;
+ resets = <&mdlc_perw 0x54>;
status = "disabled";
};
@@ -863,8 +868,12 @@ hscif1: serial@c0714000 {
"renesas,rcar-gen5-hscif", "renesas,hscif";
reg = <0 0xc0714000 0 0x60>;
interrupts = <GIC_ESPI 15 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
+ clocks = <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>,
+ <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>,
+ <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x55>;
+ resets = <&mdlc_perw 0x55>;
status = "disabled";
};
@@ -873,8 +882,12 @@ hscif2: serial@c0718000 {
"renesas,rcar-gen5-hscif", "renesas,hscif";
reg = <0 0xc0718000 0 0x60>;
interrupts = <GIC_ESPI 16 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
+ clocks = <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>,
+ <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>,
+ <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x56>;
+ resets = <&mdlc_perw 0x56>;
status = "disabled";
};
@@ -883,8 +896,12 @@ hscif3: serial@c071c000 {
"renesas,rcar-gen5-hscif", "renesas,hscif";
reg = <0 0xc071c000 0 0x60>;
interrupts = <GIC_ESPI 17 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&dummy_clk_sgasyncd4>, <&dummy_clk_sgasyncd4>, <&scif_clk>;
+ clocks = <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>,
+ <&cpg R8A78000_CPG_SGASYNCD4_PERW_BUS>,
+ <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
+ power-domains = <&mdlc_perw R8A78000_MDLC_PD_APL 0x57>;
+ resets = <&mdlc_perw 0x57>;
status = "disabled";
};
@@ -897,6 +914,239 @@ scp_sram: sram@c1000000 {
/* scp-sram node must be set per board file */
};
+
+ cpg: clock-controller@c1320000 {
+ compatible = "renesas,r8a78000-cpg";
+ reg = <0 0xc1320000 0 0x10000>;
+ clocks = <&extal_clk>, <&extalr_clk>;
+ clock-names = "extal", "extalr";
+ #clock-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_vipn: system-controller@c3060000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xc3060000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_vips: system-controller@c3460000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xc3460000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_vio: system-controller@c5000000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xc5000000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_pere: system-controller@c08f0000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xc08f0000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_perw: system-controller@c05d0000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xc05d0000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_ddr0: system-controller@e8000000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xe8000000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_ddr1: system-controller@e8080000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xe8080000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_ddr2: system-controller@e8100000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xe8100000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_ddr3: system-controller@e8180000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xe8180000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_ddr4: system-controller@e8200000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xe8200000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_ddr5: system-controller@e8280000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xe8280000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_ddr6: system-controller@e8300000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xe8300000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_ddr7: system-controller@e8380000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xe8380000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_hscn: system-controller@c9c90000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xc9c90000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_rt: system-controller@19440000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0x19440000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_top: system-controller@c6480000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xc6480000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_hscs: system-controller@de200000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xde200000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_imn: system-controller@c1990000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xc1990000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_ims: system-controller@c1d90000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xc1d90000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_gpc: system-controller@cb510000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xcb510000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_dsp: system-controller@cbe90000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xcbe90000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_mm: system-controller@e9980000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xe9980000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_npu0: system-controller@d2c30000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xd2c30000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_npu1: system-controller@d6c30000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xd6c30000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_cmnn: system-controller@ca410000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xca410000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_cmns: system-controller@ca510000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xca510000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_scp: system-controller@c1330000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xc1330000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
+
+ mdlc_aon: system-controller@c1338000 {
+ compatible = "renesas,r8a78000-mdlc";
+ reg = <0 0xc1338000 0 0x1000>;
+ #power-domain-cells = <2>;
+ #reset-cells = <1>;
+ bootph-all;
+ };
};
timer {
--
2.43.0
^ permalink raw reply related
* [PATCH/RFC 12/14] pmdomain: renesas: Add R-Car X5H MDLC SCMI remapping driver
From: Geert Uytterhoeven @ 2026-04-21 18:11 UTC (permalink / raw)
To: Sudeep Holla, Cristian Marussi, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Magnus Damm, Saravana Kannan, Michael Turquette,
Stephen Boyd, Philipp Zabel, Ulf Hansson, Rafael J . Wysocki,
Kevin Hilman, Florian Fainelli, Wolfram Sang, Marek Vasut,
Kuninori Morimoto
Cc: arm-scmi, linux-arm-kernel, linux-renesas-soc, linux-clk,
devicetree, linux-pm, linux-kernel, Geert Uytterhoeven
In-Reply-To: <cover.1776793163.git.geert+renesas@glider.be>
Add a proof-of-concept Module Controller driver for the R-Car X5H
(R8A78000) SoC, using tables to remap from hardware power domain,
module, and reset IDs to SCMI power domains, clocks, and resets.
Note that SCMI clocks representing hardware modules are fake clocks,
with a zero clock rate, that can just be enabled and disabled.
Hence these are controlled from the clock domain's start/stop callbacks.
For now this contains preliminary support for SCP FW SDKv4.28.0,
v4.31.0, and v4.32.0:
- As the SCMI power domain IDs are idential for all three versions,
r8a78000_mdlc_*_power_fw_4_28_0[] apply to all of them,
- As the SCMI clock and reset IDs are identical for the last two
versions (except for the addition of two reset IDs in v4.32.0),
r8a78000_mdlc_fw_4_31_0[] applies to both of them.
Note that v4.32 has two new reset IDs without corresponding clock IDs,
so "/* SCMI clock and reset IDs are identical */" is no longer 100%
true. However, these new resets seem to be meant for board control, not
SoC control.
Suggested-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
drivers/pmdomain/renesas/Kconfig | 4 +
drivers/pmdomain/renesas/Makefile | 1 +
drivers/pmdomain/renesas/r8a78000-mdlc.c | 1021 ++++++++++++++++++++++
drivers/soc/renesas/Kconfig | 1 +
4 files changed, 1027 insertions(+)
create mode 100644 drivers/pmdomain/renesas/r8a78000-mdlc.c
diff --git a/drivers/pmdomain/renesas/Kconfig b/drivers/pmdomain/renesas/Kconfig
index b507c3e0d723efc6..f2f52d3c29a083f1 100644
--- a/drivers/pmdomain/renesas/Kconfig
+++ b/drivers/pmdomain/renesas/Kconfig
@@ -13,6 +13,10 @@ config SYSC_RMOBILE
bool "System Controller support for R-Mobile" if COMPILE_TEST
# SoC
+config MDLC_R8A78000
+ bool "Module Controller support for R8A78000 (R-Car X5H)" if COMPILE_TEST
+ select RESET_CONTROLLER
+
config SYSC_R8A7742
bool "System Controller support for R8A7742 (RZ/G1H)" if COMPILE_TEST
select SYSC_RCAR
diff --git a/drivers/pmdomain/renesas/Makefile b/drivers/pmdomain/renesas/Makefile
index 0391e6e67440a786..17849aad37a5ac4f 100644
--- a/drivers/pmdomain/renesas/Makefile
+++ b/drivers/pmdomain/renesas/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
# SoC
+obj-$(CONFIG_MDLC_R8A78000) += r8a78000-mdlc.o
obj-$(CONFIG_SYSC_R8A7742) += r8a7742-sysc.o
obj-$(CONFIG_SYSC_R8A7743) += r8a7743-sysc.o
obj-$(CONFIG_SYSC_R8A7745) += r8a7745-sysc.o
diff --git a/drivers/pmdomain/renesas/r8a78000-mdlc.c b/drivers/pmdomain/renesas/r8a78000-mdlc.c
new file mode 100644
index 0000000000000000..74d2509657e97dbf
--- /dev/null
+++ b/drivers/pmdomain/renesas/r8a78000-mdlc.c
@@ -0,0 +1,1021 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * R-Car X5H Module Controller
+ *
+ * Copyright (C) 2026 Glider bv
+ */
+
+#include <linux/cleanup.h>
+#include <linux/clk.h>
+#include <linux/dev_printk.h>
+#include <linux/module.h>
+#include <linux/mod_devicetable.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pm_clock.h>
+#include <linux/pm_domain.h>
+#include <linux/reset-controller.h>
+#include <linux/scmi_protocol.h>
+#include <linux/slab.h>
+
+#include <dt-bindings/power/renesas,r8a78000-mdlc.h>
+
+struct power_map_in {
+ int hw_id; /* Hardware power domain ID */
+ u32 fw_id; /* SCMI firmware power domain ID */
+};
+
+struct power_map {
+ int hw_id; /* Hardware power domain ID */
+ u32 fw_id; /* SCMI firmware power domain ID */
+ struct generic_pm_domain *genpd;
+};
+
+struct mod_map {
+ int hw_id; /* Hardware module ID */
+ u32 fw_id; /* SCMI clock and reset IDs are identical */
+};
+
+struct r8a78000_mdlc_info {
+ u32 base;
+ const struct power_map_in *power_map;
+ const struct mod_map *mod_map;
+};
+
+struct fw_map {
+ u32 impl_ver;
+ const struct r8a78000_mdlc_info *info;
+};
+
+/**
+ * struct r8a78000_mdlc_priv - Module Controller Private Data
+ *
+ * @link: Link into list of MDLC instances
+ * @genpd_data: PM domain provider data
+ * @rcdev: Reset controller entity
+ * @dev: MDLC device
+ * @np: Device node in DT representing the MDLC
+ * @scmi_power_np: Device node in DT for the SCMI firmware power protocol
+ * @scmi_clk_np: Device node in DT for the SCMI firmware clock protocol
+ * @scmi_reset_np: Device node in DT for the SCMI firmware reset protocol
+ * @scmi_rcdev: SCMI reset controller entity
+ * @power_map: Mapping from hardware power domain IDs to SCMI power domains
+ * @mod_map: Mapping from hardware module IDs to SCMI clocks and resets
+ */
+struct r8a78000_mdlc_priv {
+ struct hlist_node link;
+ struct genpd_onecell_data genpd_data;
+ struct reset_controller_dev rcdev;
+ struct device *dev;
+ struct device_node *np;
+ struct device_node *scmi_power_np;
+ struct device_node *scmi_clk_np;
+ struct device_node *scmi_reset_np;
+ struct reset_controller_dev *scmi_rcdev;
+ const struct power_map *power_map;
+ const struct mod_map *mod_map;
+};
+
+static struct generic_pm_domain *r8a78000_genpd_always_on;
+static HLIST_HEAD(r8a78000_mdlc_list);
+static DEFINE_MUTEX(r8a78000_mdlc_lock); /* protects the two above */
+
+static const struct power_map *power_map_find(const struct power_map *map,
+ u32 id)
+{
+ if (!map)
+ return NULL;
+
+ for (; map->hw_id >= 0; map++) {
+ if (map->hw_id == id)
+ return map;
+ }
+
+ return NULL;
+}
+
+static struct generic_pm_domain *r8a78000_genpd_xlate(
+ const struct of_phandle_args *spec, void *data)
+{
+ struct r8a78000_mdlc_priv *priv = container_of(data,
+ struct r8a78000_mdlc_priv, genpd_data);
+ struct generic_pm_domain *genpd;
+ struct device *dev = priv->dev;
+ const struct power_map *map;
+ u32 id;
+
+ if (spec->args_count != 2)
+ return ERR_PTR(-EINVAL);
+
+ id = spec->args[0];
+
+ if (id >= R8A78000_MDLC_PD_AON) {
+ dev_dbg(dev, "Mapping HW power domain %u to always-on domain\n",
+ id);
+ return r8a78000_genpd_always_on;
+ }
+
+ map = power_map_find(priv->power_map, id);
+ if (!map) {
+ dev_err(dev, "Unknown power domain %u\n", id);
+ return ERR_PTR(-ENOENT);
+ }
+
+ dev_dbg(dev, "Mapping HW power domain %u to SCMI power domain %u\n", id,
+ map->fw_id);
+
+ genpd = map->genpd;
+
+ return genpd;
+}
+
+#define rcdev_to_priv(_rcdev) \
+ container_of(_rcdev, struct r8a78000_mdlc_priv, rcdev)
+
+static const struct mod_map *mod_map_find(const struct mod_map *map, u32 id)
+{
+ if (!map)
+ return NULL;
+
+ for (; map->hw_id >= 0; map++) {
+ if (map->hw_id == id)
+ return map;
+ }
+
+ return NULL;
+}
+
+static int r8a78000_mdlc_reset_xlate(struct reset_controller_dev *rcdev,
+ const struct of_phandle_args *spec)
+{
+ struct r8a78000_mdlc_priv *priv = rcdev_to_priv(rcdev);
+ struct device *dev = priv->dev;
+ const struct mod_map *map;
+ u32 id;
+
+ if (spec->args_count != 1)
+ return -EINVAL;
+
+ id = spec->args[0];
+
+ map = mod_map_find(priv->mod_map, id);
+ if (!map) {
+ dev_err(dev, "Unknown reset %u\n", id);
+ return -ENOENT;
+ }
+
+ dev_dbg(dev, "Mapping HW reset %u to SCMI reset %u\n", id, map->fw_id);
+
+ return map->fw_id;
+}
+
+#define DEFINE_MDLC_RESET_WRAPPER(op) \
+ static int r8a78000_mdlc_ ## op(struct reset_controller_dev *rcdev, \
+ unsigned long id) \
+ { \
+ struct r8a78000_mdlc_priv *priv = rcdev_to_priv(rcdev); \
+ int ret; \
+ \
+ if (!priv->scmi_rcdev->ops->op) \
+ return -ENOTSUPP; \
+ \
+ ret = priv->scmi_rcdev->ops->op(priv->scmi_rcdev, id); \
+ if (ret == -EOPNOTSUPP) \
+ dev_dbg(priv->dev, \
+ "%s: Ignoring unsupported reset %lu\n", \
+ __func__, id); \
+ return ret == -EOPNOTSUPP ? 0 : ret; \
+ }
+
+DEFINE_MDLC_RESET_WRAPPER(reset)
+DEFINE_MDLC_RESET_WRAPPER(assert)
+DEFINE_MDLC_RESET_WRAPPER(deassert)
+DEFINE_MDLC_RESET_WRAPPER(status)
+
+static const struct reset_control_ops r8a78000_mdlc_reset_ops = {
+ .reset = r8a78000_mdlc_reset,
+ .assert = r8a78000_mdlc_assert,
+ .deassert = r8a78000_mdlc_deassert,
+ .status = r8a78000_mdlc_status,
+};
+
+static struct device_node *scmi_find_proto(struct device_node *scmi, u32 proto)
+{
+ for_each_available_child_of_node_scoped(scmi, child) {
+ u32 reg;
+
+ if (of_property_read_u32(child, "reg", ®))
+ continue;
+
+ if (reg == proto)
+ return_ptr(child);
+ }
+
+ return NULL;
+}
+
+static int r8a78000_mdlc_attach_dev(struct generic_pm_domain *domain,
+ struct device *dev)
+{
+ struct of_phandle_args pd_spec, scmi_spec;
+ struct device_node *np = dev->of_node;
+ struct r8a78000_mdlc_priv *priv;
+ const struct mod_map *map;
+ unsigned int id;
+ struct clk *clk;
+ int ret;
+
+ ret = of_parse_phandle_with_args(np, "power-domains",
+ "#power-domain-cells", 0, &pd_spec);
+ if (ret < 0)
+ return ret;
+
+ if (pd_spec.args_count != 2) {
+ of_node_put(pd_spec.np);
+ return -EINVAL;
+ }
+
+ scoped_guard(mutex, &r8a78000_mdlc_lock) {
+ hlist_for_each_entry(priv, &r8a78000_mdlc_list, link) {
+ if (priv->np == pd_spec.np)
+ break;
+ }
+ }
+
+ if (!priv) {
+ dev_err(dev, "%s: MDLC %pOF not found\n", __func__, pd_spec.np);
+ of_node_put(pd_spec.np);
+ return -ENODEV;
+ }
+
+ id = pd_spec.args[1];
+ of_node_put(pd_spec.np);
+
+ map = mod_map_find(priv->mod_map, id);
+ if (!map) {
+ dev_err(dev, "Unknown module %u\n", id);
+ return -ENOENT;
+ }
+
+ dev_dbg(dev, "Mapping HW module %u to SCMI clock %u\n", id, map->fw_id);
+
+ scmi_spec.np = priv->scmi_clk_np;
+ scmi_spec.args_count = 1;
+ scmi_spec.args[0] = map->fw_id;
+
+ clk = of_clk_get_from_provider(&scmi_spec);
+ if (IS_ERR(clk)) {
+ dev_err(dev, "Cannot get SCMI clock %u: %pe\n", map->fw_id,
+ clk);
+ return PTR_ERR(clk);
+ }
+
+ dev_dbg(dev, "SCMI clock %u is %pC\n", map->fw_id, clk);
+
+ if (!clk) {
+ /* Ignore missing SCMI module clocks */
+ return 0;
+ }
+
+ ret = pm_clk_create(dev);
+ if (ret)
+ goto fail_put;
+
+ ret = pm_clk_add_clk(dev, clk);
+ if (ret)
+ goto fail_destroy;
+
+ return 0;
+
+fail_destroy:
+ pm_clk_destroy(dev);
+fail_put:
+ clk_put(clk);
+ return ret;
+}
+
+static void r8a78000_mdlc_detach_dev(struct generic_pm_domain *domain,
+ struct device *dev)
+{
+ if (!pm_clk_no_clocks(dev))
+ pm_clk_destroy(dev);
+}
+
+static const struct power_map *fill_power_map(struct r8a78000_mdlc_priv *priv,
+ const struct power_map_in *map_in)
+{
+ struct of_phandle_args scmi_spec;
+ struct generic_pm_domain *genpd;
+ struct device *dev = priv->dev;
+ struct power_map *map;
+ unsigned int i;
+
+ if (!map_in)
+ return NULL;
+
+ for (i = 0; map_in[i].hw_id >= 0; i++) { }
+
+ map = devm_kcalloc(dev, i + 1, sizeof(*map), GFP_KERNEL);
+ if (!map)
+ return ERR_PTR(-ENOMEM);
+
+ for (i = 0; ; i++) {
+ map[i].hw_id = map_in[i].hw_id;
+ if (map[i].hw_id < 0)
+ break;
+
+ map[i].fw_id = map_in[i].fw_id;
+
+ scmi_spec.np = priv->scmi_power_np;
+ scmi_spec.args_count = 1;
+ scmi_spec.args[0] = map[i].fw_id;
+
+ genpd = genpd_get_from_provider(&scmi_spec);
+ if (IS_ERR(genpd))
+ return dev_err_cast_probe(dev, genpd,
+ "Failed to get SCMI power domain %u\n",
+ map[i].fw_id);
+
+ dev_dbg(dev, "SCMI power domain %u is %s\n", map[i].fw_id,
+ genpd->name);
+
+ map[i].genpd = genpd;
+
+ /* Hook up clock domain support */
+ genpd->attach_dev = r8a78000_mdlc_attach_dev;
+ genpd->detach_dev = r8a78000_mdlc_detach_dev;
+ /* Setting flags this late has no impact, but does not hurt */
+ genpd->flags |= GENPD_FLAG_PM_CLK;
+ genpd->dev_ops.stop = pm_clk_suspend;
+ genpd->dev_ops.start = pm_clk_resume;
+ }
+
+ return map;
+}
+
+static void r8a78000_mdlc_unlink(void *data)
+{
+ struct r8a78000_mdlc_priv *priv = data;
+
+ scoped_guard(mutex, &r8a78000_mdlc_lock) {
+ hlist_del(&priv->link);
+ }
+}
+
+static void r8a78000_genpd_del_provider(void *data)
+{
+ of_genpd_del_provider(data);
+}
+
+static int r8a78000_genpd_always_on_singleton(struct device *dev)
+{
+ struct generic_pm_domain *genpd;
+ int ret;
+
+ guard(mutex)(&r8a78000_mdlc_lock);
+
+ if (r8a78000_genpd_always_on)
+ return 0;
+
+ genpd = kzalloc_obj(*genpd);
+ if (!genpd)
+ return -ENOMEM;
+
+ genpd->name = "always-on";
+ genpd->attach_dev = r8a78000_mdlc_attach_dev;
+ genpd->detach_dev = r8a78000_mdlc_detach_dev;
+ genpd->flags |= GENPD_FLAG_PM_CLK;
+
+ ret = pm_genpd_init(genpd, &pm_domain_always_on_gov, false);
+ if (ret) {
+ kfree(genpd);
+ return dev_err_probe(dev, ret,
+ "Failed to create always-on domain\n");
+ }
+
+ r8a78000_genpd_always_on = genpd;
+ return 0;
+}
+
+static int r8a78000_mdlc_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct device_node *scmi __free(device_node) = NULL;
+ const struct r8a78000_mdlc_info *info;
+ struct r8a78000_mdlc_priv *priv;
+ struct scmi_base_info version;
+ const struct fw_map *fw_map;
+ struct resource *res;
+ int ret;
+
+ ret = r8a78000_genpd_always_on_singleton(dev);
+ if (ret)
+ return ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->dev = dev;
+ priv->np = np;
+
+ scmi = of_parse_phandle(dev->of_node, "firmware", 0);
+ if (!scmi) {
+ dev_err(dev, "Cannot find SCMI firmware node\n");
+ return -ENODEV;
+ }
+
+ priv->scmi_power_np = scmi_find_proto(scmi, SCMI_PROTOCOL_POWER);
+ if (!priv->scmi_power_np) {
+ dev_err(dev,
+ "Cannot find SCMI power domain management protocol\n");
+ return -ENODEV;
+ }
+
+ priv->scmi_clk_np = scmi_find_proto(scmi, SCMI_PROTOCOL_CLOCK);
+ if (!priv->scmi_clk_np) {
+ dev_err(dev, "Cannot find SCMI clock management protocol\n");
+ return -ENODEV;
+ }
+
+ priv->scmi_reset_np = scmi_find_proto(scmi, SCMI_PROTOCOL_RESET);
+ if (!priv->scmi_reset_np) {
+ dev_err(dev, "Cannot find SCMI reset management protocol\n");
+ return -ENODEV;
+ }
+
+ ret = scmi_get_base_info(scmi, &version);
+ if (ret) {
+ return dev_err_probe(dev, -EPROBE_DEFER,
+ "SCMI not yet available\n");
+ }
+
+ if (strcmp(version.vendor_id, "Renesas") ||
+ strcmp(version.sub_vendor_id, "None")) {
+ return dev_err_probe(dev, -ENODEV,
+ "Unsupported SCMI firmware %s/%s\n",
+ version.vendor_id, version.sub_vendor_id);
+ }
+
+ priv->scmi_rcdev = reset_controller_get_provider(of_fwnode_handle(priv->scmi_reset_np));
+ if (!priv->scmi_rcdev)
+ return dev_err_probe(dev, -EPROBE_DEFER,
+ "SCMI reset not yet available\n");
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res)
+ return -ENODEV;
+
+ for (fw_map = of_device_get_match_data(dev); fw_map->info; fw_map++) {
+ if (fw_map->impl_ver == version.impl_ver)
+ break;
+ }
+
+ if (!fw_map->info) {
+ return dev_err_probe(dev, -ENODEV,
+ "Unsupported SCMI version 0x%08x\n",
+ version.impl_ver);
+ }
+
+ for (info = fw_map->info; info->base; info++) {
+ if (info->base == res->start)
+ break;
+ }
+
+ if (!info->base) {
+ dev_warn(dev, "Unsupported MDLC instance 0x%pa\n", &res->start);
+ return -ENODEV;
+ }
+
+ /*
+ * We cannot do lazy look-up in r8a78000_genpd_xlate(), as that
+ * function is called with of_genpd_mutex already held.
+ */
+ priv->power_map = fill_power_map(priv, info->power_map);
+ if (IS_ERR(priv->power_map))
+ return PTR_ERR(priv->power_map);
+
+ priv->mod_map = info->mod_map;
+
+ scoped_guard(mutex, &r8a78000_mdlc_lock) {
+ hlist_add_head(&priv->link, &r8a78000_mdlc_list);
+ }
+
+ ret = devm_add_action_or_reset(dev, r8a78000_mdlc_unlink, priv);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to add action\n");
+
+ // FIXME genpd_add_provider() would be sufficient, but is private
+ /* Note that no actual domains are registered, just need translation */
+ priv->genpd_data.xlate = r8a78000_genpd_xlate;
+ ret = of_genpd_add_provider_onecell(np, &priv->genpd_data);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "Failed to register genpd provider\n");
+
+ ret = devm_add_action_or_reset(dev, r8a78000_genpd_del_provider, np);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "failed to add unregister action\n");
+
+ priv->rcdev.ops = &r8a78000_mdlc_reset_ops;
+ priv->rcdev.of_node = np;
+ priv->rcdev.of_reset_n_cells = 1;
+ priv->rcdev.of_xlate = r8a78000_mdlc_reset_xlate;
+
+ ret = devm_reset_controller_register(dev, &priv->rcdev);
+ if (ret)
+ return dev_err_probe(dev, ret,
+ "Failed to register reset controller\n");
+
+ return 0;
+}
+
+// FIXME We don't need all of them from the start; only add when used/tested
+static const struct power_map_in r8a78000_mdlc_pere_power_fw_4_28_0[] = {
+ { 0, 12 }, /* PD_UFS0 */
+ { 1, 13 }, /* PD_UFS1 */
+ { -1 },
+};
+
+static const struct mod_map r8a78000_mdlc_pere_mod_fw_4_28_0[] = {
+ { 0x30, 197 }, /* PERE_GPIODM0 */
+ // No CLOCK_ATTRIBUTES { 0x31, 198 }, /* PERE_GPIODM1 */
+ // No CLOCK_ATTRIBUTES { 0x32, 199 }, /* PERE_GPIODM2 */
+ // No CLOCK_ATTRIBUTES { 0x33, 200 }, /* PERE_GPIODM3 */
+ { 0x40, 201 }, /* RPC */
+ { 0x60, 202 }, /* UFS0 */
+ { 0x61, 203 }, /* UFS1 */
+ { 0x70, 204 }, /* SDHI0 */
+ { -1 },
+};
+
+static const struct mod_map r8a78000_mdlc_perw_mod_fw_4_28_0[] = {
+ { 0x30, 205 }, /* PERW_GPIODM0 */
+ // No CLOCK_ATTRIBUTES { 0x31, 206 }, /* PERW_GPIODM1 */
+ // No CLOCK_ATTRIBUTES { 0x32, 207 }, /* PERW_GPIODM2 */
+ // No CLOCK_ATTRIBUTES { 0x33, 208 }, /* PERW_GPIODM3 */
+ { 0x40, 209 }, /* SCIF0 */
+ { 0x41, 210 }, /* SCIF1 */
+ { 0x42, 211 }, /* SCIF3 */
+ { 0x43, 212 }, /* SCIF4 */
+ { 0x44, 213 }, /* I2C1 */
+ { 0x45, 214 }, /* I2C2 */
+ { 0x46, 215 }, /* I2C3 */
+ { 0x47, 216 }, /* I2C4 */
+ { 0x48, 217 }, /* I2C5 */
+ { 0x49, 218 }, /* I2C6 */
+ { 0x4a, 219 }, /* I2C7 */
+ { 0x4b, 220 }, /* I2C8 */
+ { 0x4c, 221 }, /* I3C0 */
+ { 0x4d, 222 }, /* I3C1 */
+ { 0x4e, 223 }, /* I3C2 */
+ { 0x4f, 224 }, /* MSI4 */
+ { 0x50, 225 }, /* MSI5 */
+ { 0x51, 226 }, /* MSI6 */
+ { 0x52, 227 }, /* MSI7 */
+ /*
+ * HSCIF0 is protected:
+ * - CLOCK_ATTRIBUTES is not supported, so clk is NULL
+ * - Reset operations fail with -EOPNOTSUPP
+ */
+ { 0x54, 228 }, /* HSCIF0 */
+ { 0x55, 229 }, /* HSCIF1 */
+ { 0x56, 230 }, /* HSCIF2 */
+ { 0x57, 231 }, /* HSCIF3 */
+ { 0x58, 232 }, /* DRI00 */
+ { 0x59, 233 }, /* DRI01 */
+ { 0x5a, 234 }, /* DRI10 */
+ { 0x5b, 235 }, /* DRI11 */
+ { 0x5c, 236 }, /* DRI20 */
+ { 0x5d, 237 }, /* DRI21 */
+ { 0x5e, 238 }, /* DRI30 */
+ { 0x5f, 239 }, /* DRI31 */
+ { 0x60, 240 }, /* DRI40 */
+ { 0x61, 241 }, /* DRI41 */
+ { 0x62, 242 }, /* DRI50 */
+ { 0x63, 243 }, /* DRI51 */
+ { 0x64, 244 }, /* DRI60 */
+ { 0x65, 245 }, /* DRI61 */
+ { 0x66, 246 }, /* DRI70 */
+ { 0x67, 247 }, /* DRI71 */
+ { 0x70, 248 }, /* PWM0 */
+ { 0x72, 249 }, /* TMU1 */
+ { 0x73, 250 }, /* TMU2 */
+ { 0x74, 251 }, /* TMU3 */
+ { 0x75, 252 }, /* TMU4 */
+ { 0x76, 253 }, /* TPU0 */
+ { 0x90, 254 }, /* ADG0 */
+ { 0x91, 255 }, /* ADG1 */
+ { 0x92, 256 }, /* SSI0 */
+ { 0x93, 257 }, /* SSI00 */
+ { 0x94, 258 }, /* SSI01 */
+ { 0x95, 259 }, /* SSI02 */
+ { 0x96, 260 }, /* SSI03 */
+ { 0x97, 261 }, /* SSI04 */
+ { 0x98, 262 }, /* SSI05 */
+ { 0x99, 263 }, /* SSI06 */
+ { 0x9a, 264 }, /* SSI07 */
+ { 0x9b, 265 }, /* SSI08 */
+ { 0x9c, 266 }, /* SSI09 */
+ { 0x9d, 267 }, /* SSI1 */
+ { 0x9e, 268 }, /* SSI10 */
+ { 0x9f, 269 }, /* SSI11 */
+ { 0xa0, 270 }, /* SSI12 */
+ { 0xa1, 271 }, /* SSI13 */
+ { 0xa2, 272 }, /* SSI14 */
+ { 0xa3, 273 }, /* SSI15 */
+ { 0xa4, 274 }, /* SSI16 */
+ { 0xa5, 275 }, /* SSI17 */
+ { 0xa6, 276 }, /* SSI18 */
+ { 0xa7, 277 }, /* SSI19 */
+ { 0xa8, 278 }, /* SCU0 */
+ { 0xa9, 279 }, /* SRC00 */
+ { 0xaa, 280 }, /* SRC01 */
+ { 0xab, 281 }, /* SRC02 */
+ { 0xac, 282 }, /* SRC03 */
+ { 0xad, 283 }, /* SRC04 */
+ { 0xae, 284 }, /* SRC05 */
+ { 0xaf, 285 }, /* SRC06 */
+ { 0xb0, 286 }, /* SRC07 */
+ { 0xb1, 287 }, /* SRC08 */
+ { 0xb2, 288 }, /* SRC09 */
+ { 0xb3, 289 }, /* SCU00 */
+ { 0xb4, 290 }, /* SCU01 */
+ { 0xb5, 291 }, /* DVC00 */
+ { 0xb6, 292 }, /* DVC01 */
+ { 0xb7, 293 }, /* SCU1 */
+ { 0xb8, 294 }, /* SRC10 */
+ { 0xb9, 295 }, /* SRC11 */
+ { 0xba, 296 }, /* SRC12 */
+ { 0xbb, 297 }, /* SRC13 */
+ { 0xbc, 298 }, /* SRC14 */
+ { 0xbd, 299 }, /* SRC15 */
+ { 0xbe, 300 }, /* SRC16 */
+ { 0xbf, 301 }, /* SRC17 */
+ { 0xc0, 302 }, /* SRC18 */
+ { 0xc1, 303 }, /* SRC19 */
+ { 0xc2, 304 }, /* SCU10 */
+ { 0xc3, 305 }, /* SCU11 */
+ { 0xc4, 306 }, /* DVC10 */
+ { 0xc5, 307 }, /* DVC11 */
+ { 0xc6, 308 }, /* APD00 */
+ { 0xc7, 309 }, /* APD01 */
+ { 0xc8, 310 }, /* APD10 */
+ { 0xc9, 311 }, /* APD11 */
+ { 0xca, 312 }, /* APD02 */
+ { 0xcb, 313 }, /* APD12 */
+ { -1 },
+};
+
+static const struct r8a78000_mdlc_info r8a78000_mdlc_fw_4_28_0[] = {
+ {
+ .base = 0xc3060000 /* mdlc_vipn */,
+ /* FIXME .power_map = r8a78000_mdlc_vipn_power_fw_4_28_0, */
+ /* FIXME .mod_map = r8a78000_mdlc_vipn_mod_fw_4_28_0, */
+ }, {
+ .base = 0xc3460000 /* mdlc_vips */,
+ /* FIXME .power_map = r8a78000_mdlc_vips_power_fw_4_28_0, */
+ /* FIXME .mod_map = r8a78000_mdlc_vips_mod_fw_4_28_0, */
+ }, {
+ .base = 0xc5000000 /* mdlc_vio */,
+ /* FIXME .power_map = r8a78000_mdlc_vio_power_fw_4_28_0, */
+ /* FIXME .mod_map = r8a78000_mdlc_vio_mod_fw_4_28_0, */
+ }, {
+ .base = 0xc08f0000 /* mdlc_pere */,
+ .power_map = r8a78000_mdlc_pere_power_fw_4_28_0,
+ .mod_map = r8a78000_mdlc_pere_mod_fw_4_28_0,
+ }, {
+ .base = 0xc05d0000 /* mdlc_perw */,
+ .mod_map = r8a78000_mdlc_perw_mod_fw_4_28_0,
+// FIXME We don't need all of them from the start; only add when used/tested
+#if 0
+ }, {
+ .base = 0xe8000000 /* mdlc_ddr0 */,
+ }, {
+ .base = 0xe8080000 /* mdlc_ddr1 */,
+ }, {
+ .base = 0xe8100000 /* mdlc_ddr2 */,
+ }, {
+ .base = 0xe8180000 /* mdlc_ddr3 */,
+ }, {
+ .base = 0xe8200000 /* mdlc_ddr4 */,
+ }, {
+ .base = 0xe8280000 /* mdlc_ddr5 */,
+ }, {
+ .base = 0xe8300000 /* mdlc_ddr6 */,
+ }, {
+ .base = 0xe8380000 /* mdlc_ddr7 */,
+ }, {
+ .base = 0xc9c90000 /* mdlc_hscn */,
+ /* FIXME .power_map = r8a78000_mdlc_hscn_power_fw_4_28_0, */
+ /* FIXME .mod_map = r8a78000_mdlc_hscn_mod_fw_4_28_0, */
+ }, {
+ .base = 0x19440000 /* mdlc_rt */,
+ /* FIXME .power_map = r8a78000_mdlc_rt_power_fw_4_28_0, */
+ /* FIXME .mod_map = r8a78000_mdlc_rt_mod_fw_4_28_0, */
+ }, {
+ .base = 0xc6480000 /* mdlc_top */,
+ /* FIXME .mod_map = r8a78000_mdlc_top_mod_fw_4_28_0, */
+ }, {
+ .base = 0xde200000 /* mdlc_hscs */,
+ /* FIXME .power_map = r8a78000_mdlc_hscs_power_fw_4_28_0, */
+ /* FIXME .mod_map = r8a78000_mdlc_hscs_mod_fw_4_28_0, */
+ }, {
+ .base = 0xc1990000 /* mdlc_imn */,
+ /* FIXME .power_map = r8a78000_mdlc_imn_power_fw_4_28_0, */
+ /* FIXME .mod_map = r8a78000_mdlc_imn_mod_fw_4_28_0, */
+ }, {
+ .base = 0xc1d90000 /* mdlc_ims */,
+ /* FIXME .power_map = r8a78000_mdlc_ims_power_fw_4_28_0, */
+ /* FIXME .mod_map = r8a78000_mdlc_ims_mod_fw_4_28_0, */
+ }, {
+ .base = 0xcb510000 /* mdlc_gpc */,
+ /* FIXME .power_map = r8a78000_mdlc_gpc_power_fw_4_28_0, */
+ /* FIXME .mod_map = r8a78000_mdlc_gpc_mod_fw_4_28_0, */
+ }, {
+ .base = 0xcbe90000 /* mdlc_dsp */,
+ /* FIXME .power_map = r8a78000_mdlc_dsp_power_fw_4_28_0, */
+ /* FIXME .mod_map = r8a78000_mdlc_dsp_mod_fw_4_28_0, */
+ }, {
+ .base = 0xe9980000 /* mdlc_mm */,
+ /* FIXME .mod_map = r8a78000_mdlc_mm_mod_fw_4_28_0, */
+ }, {
+ .base = 0xd2c30000 /* mdlc_npu0 */,
+ /* FIXME .power_map = r8a78000_mdlc_npu0_power_fw_4_28_0, */
+ /* FIXME .mod_map = r8a78000_mdlc_npu0_mod_fw_4_28_0, */
+ }, {
+ .base = 0xd6c30000 /* mdlc_npu1 */,
+ /* FIXME .power_map = r8a78000_mdlc_npu1_power_fw_4_28_0, */
+ /* FIXME .mod_map = r8a78000_mdlc_npu1_mod_fw_4_28_0, */
+ }, {
+ .base = 0xca410000 /* mdlc_cmnn */,
+ /* FIXME .power_map = r8a78000_mdlc_cmnn_power_fw_4_28_0, */
+ /* FIXME .mod_map = r8a78000_mdlc_cmnn_mod_fw_4_28_0, */
+ }, {
+ .base = 0xca510000 /* mdlc_cmns */,
+ /* FIXME .power_map = r8a78000_mdlc_cmns_power_fw_4_28_0, */
+ /* FIXME .mod_map = r8a78000_mdlc_cmns_mod_fw_4_28_0, */
+ }, {
+ .base = 0xc1330000 /* mdlc_scp */,
+ /* FIXME .mod_map = r8a78000_mdlc_scp_mod_fw_4_28_0, */
+ }, {
+ .base = 0xc1338000 /* mdlc_aon */,
+ /* FIXME .mod_map = r8a78000_mdlc_aon_mod_fw_4_28_0, */
+#endif
+ },
+ { 0 }
+};
+
+static const struct mod_map r8a78000_mdlc_pere_mod_fw_4_31_0[] = {
+ { 0x30, 193 }, /* PERE_GPIODM0 */
+ // No CLOCK_ATTRIBUTES { 0x31, 194 }, /* PERE_GPIODM1 */
+ // No CLOCK_ATTRIBUTES { 0x32, 195 }, /* PERE_GPIODM2 */
+ // No CLOCK_ATTRIBUTES { 0x33, 196 }, /* PERE_GPIODM3 */
+ { 0x40, 197 }, /* RPC */
+ { 0x60, 198 }, /* UFS0 */
+ { 0x61, 199 }, /* UFS1 */
+ { 0x70, 200 }, /* SDHI0 */
+ { -1 },
+};
+
+static const struct mod_map r8a78000_mdlc_perw_mod_fw_4_31_0[] = {
+ { 0x30, 201 }, /* PERW_GPIODM0 */
+ // No CLOCK_ATTRIBUTES { 0x31, 202 }, /* PERW_GPIODM1 */
+ // No CLOCK_ATTRIBUTES { 0x32, 203 }, /* PERW_GPIODM2 */
+ // No CLOCK_ATTRIBUTES { 0x33, 204 }, /* PERW_GPIODM3 */
+ { 0x40, 205 }, /* SCIF0 */
+ { 0x41, 206 }, /* SCIF1 */
+ { 0x42, 207 }, /* SCIF3 */
+ { 0x43, 208 }, /* SCIF4 */
+ { 0x44, 209 }, /* I2C1 */
+ { 0x45, 210 }, /* I2C2 */
+ { 0x46, 211 }, /* I2C3 */
+ { 0x47, 212 }, /* I2C4 */
+ { 0x48, 213 }, /* I2C5 */
+ { 0x49, 214 }, /* I2C6 */
+ { 0x4a, 215 }, /* I2C7 */
+ { 0x4b, 216 }, /* I2C8 */
+ { 0x4c, 217 }, /* I3C0 */
+ { 0x4d, 218 }, /* I3C1 */
+ { 0x4e, 219 }, /* I3C2 */
+ { 0x4f, 220 }, /* MSI4 */
+ { 0x50, 221 }, /* MSI5 */
+ { 0x51, 222 }, /* MSI6 */
+ { 0x52, 223 }, /* MSI7 */
+ { 0x54, 224 }, /* HSCIF0 */
+ { 0x55, 225 }, /* HSCIF1 */
+ { 0x56, 226 }, /* HSCIF2 */
+ { 0x57, 227 }, /* HSCIF3 */
+ { 0x58, 228 }, /* DRI00 */
+ { 0x59, 229 }, /* DRI01 */
+ { 0x5a, 230 }, /* DRI10 */
+ { 0x5b, 231 }, /* DRI11 */
+ { 0x5c, 232 }, /* DRI20 */
+ { 0x5d, 233 }, /* DRI21 */
+ { 0x5e, 234 }, /* DRI30 */
+ { 0x5f, 235 }, /* DRI31 */
+ { 0x60, 236 }, /* DRI40 */
+ { 0x61, 237 }, /* DRI41 */
+ { 0x62, 238 }, /* DRI50 */
+ { 0x63, 239 }, /* DRI51 */
+ { 0x64, 240 }, /* DRI60 */
+ { 0x65, 241 }, /* DRI61 */
+ { 0x66, 242 }, /* DRI70 */
+ { 0x67, 243 }, /* DRI71 */
+ { 0x70, 244 }, /* PWM0 */
+ { 0x72, 245 }, /* TMU1 */
+ { 0x73, 246 }, /* TMU2 */
+ { 0x74, 247 }, /* TMU3 */
+ { 0x75, 248 }, /* TMU4 */
+ { 0x76, 249 }, /* TPU0 */
+ { 0x90, 250 }, /* ADG0 */
+ { 0x91, 251 }, /* ADG1 */
+ { 0x92, 252 }, /* SSI0 */
+ { 0x93, 253 }, /* SSI00 */
+ { 0x94, 254 }, /* SSI01 */
+ { 0x95, 255 }, /* SSI02 */
+ { 0x96, 256 }, /* SSI03 */
+ { 0x97, 257 }, /* SSI04 */
+ { 0x98, 258 }, /* SSI05 */
+ { 0x99, 259 }, /* SSI06 */
+ { 0x9a, 260 }, /* SSI07 */
+ { 0x9b, 261 }, /* SSI08 */
+ { 0x9c, 262 }, /* SSI09 */
+ { 0x9d, 263 }, /* SSI1 */
+ { 0x9e, 264 }, /* SSI10 */
+ { 0x9f, 265 }, /* SSI11 */
+ { 0xa0, 266 }, /* SSI12 */
+ { 0xa1, 267 }, /* SSI13 */
+ { 0xa2, 268 }, /* SSI14 */
+ { 0xa3, 269 }, /* SSI15 */
+ { 0xa4, 270 }, /* SSI16 */
+ { 0xa5, 271 }, /* SSI17 */
+ { 0xa6, 272 }, /* SSI18 */
+ { 0xa7, 273 }, /* SSI19 */
+ { 0xa8, 274 }, /* SCU0 */
+ { 0xa9, 275 }, /* SRC00 */
+ { 0xaa, 276 }, /* SRC01 */
+ { 0xab, 277 }, /* SRC02 */
+ { 0xac, 278 }, /* SRC03 */
+ { 0xad, 279 }, /* SRC04 */
+ { 0xae, 280 }, /* SRC05 */
+ { 0xaf, 281 }, /* SRC06 */
+ { 0xb0, 282 }, /* SRC07 */
+ { 0xb1, 283 }, /* SRC08 */
+ { 0xb2, 284 }, /* SRC09 */
+ { 0xb3, 285 }, /* SCU00 */
+ { 0xb4, 286 }, /* SCU01 */
+ { 0xb5, 287 }, /* DVC00 */
+ { 0xb6, 288 }, /* DVC01 */
+ { 0xb7, 289 }, /* SCU1 */
+ { 0xb8, 290 }, /* SRC10 */
+ { 0xb9, 291 }, /* SRC11 */
+ { 0xba, 292 }, /* SRC12 */
+ { 0xbb, 293 }, /* SRC13 */
+ { 0xbc, 294 }, /* SRC14 */
+ { 0xbd, 295 }, /* SRC15 */
+ { 0xbe, 296 }, /* SRC16 */
+ { 0xbf, 297 }, /* SRC17 */
+ { 0xc0, 298 }, /* SRC18 */
+ { 0xc1, 299 }, /* SRC19 */
+ { 0xc2, 300 }, /* SCU10 */
+ { 0xc3, 301 }, /* SCU11 */
+ { 0xc4, 302 }, /* DVC10 */
+ { 0xc5, 303 }, /* DVC11 */
+ { 0xc6, 304 }, /* APD00 */
+ { 0xc7, 305 }, /* APD01 */
+ { 0xc8, 306 }, /* APD10 */
+ { 0xc9, 307 }, /* APD11 */
+ { 0xca, 308 }, /* APD02 */
+ { 0xcb, 309 }, /* APD12 */
+ { -1 },
+};
+
+static const struct r8a78000_mdlc_info r8a78000_mdlc_fw_4_31_0[] = {
+ {
+ .base = 0xc3060000 /* mdlc_vipn */,
+ /* FIXME .power_map = r8a78000_mdlc_vipn_power_fw_4_28_0, */
+ /* FIXME .mod_map = r8a78000_mdlc_vipn_mod_fw_4_31_0, */
+ }, {
+ .base = 0xc3460000 /* mdlc_vips */,
+ /* FIXME .power_map = r8a78000_mdlc_vips_power_fw_4_28_0, */
+ /* FIXME .mod_map = r8a78000_mdlc_vips_mod_fw_4_31_0, */
+ }, {
+ .base = 0xc5000000 /* mdlc_vio */,
+ /* FIXME .power_map = r8a78000_mdlc_vio_power_fw_4_28_0, */
+ /* FIXME .mod_map = r8a78000_mdlc_vio_mod_fw_4_31_0, */
+ }, {
+ .base = 0xc08f0000 /* mdlc_pere */,
+ .power_map = r8a78000_mdlc_pere_power_fw_4_28_0,
+ .mod_map = r8a78000_mdlc_pere_mod_fw_4_31_0,
+ }, {
+ .base = 0xc05d0000 /* mdlc_perw */,
+ .mod_map = r8a78000_mdlc_perw_mod_fw_4_31_0,
+// FIXME We don't need all of them from the start; only add when used/tested
+#if 0
+ }, {
+ .base = 0xe8000000 /* mdlc_ddr0 */,
+ }, {
+ .base = 0xe8080000 /* mdlc_ddr1 */,
+ }, {
+ .base = 0xe8100000 /* mdlc_ddr2 */,
+ }, {
+ .base = 0xe8180000 /* mdlc_ddr3 */,
+ }, {
+ .base = 0xe8200000 /* mdlc_ddr4 */,
+ }, {
+ .base = 0xe8280000 /* mdlc_ddr5 */,
+ }, {
+ .base = 0xe8300000 /* mdlc_ddr6 */,
+ }, {
+ .base = 0xe8380000 /* mdlc_ddr7 */,
+ }, {
+ .base = 0xc9c90000 /* mdlc_hscn */,
+ /* FIXME .power_map = r8a78000_mdlc_hscn_power_fw_4_28_0, */
+ /* FIXME .mod_map = r8a78000_mdlc_hscn_mod_fw_4_31_0, */
+ }, {
+ .base = 0x19440000 /* mdlc_rt */,
+ /* FIXME .power_map = r8a78000_mdlc_rt_power_fw_4_28_0, */
+ /* FIXME .mod_map = r8a78000_mdlc_rt_mod_fw_4_31_0, */
+ }, {
+ .base = 0xc6480000 /* mdlc_top */,
+ /* FIXME .mod_map = r8a78000_mdlc_top_mod_fw_4_31_0, */
+ }, {
+ .base = 0xde200000 /* mdlc_hscs */,
+ /* FIXME .power_map = r8a78000_mdlc_hscs_power_fw_4_28_0, */
+ /* FIXME .mod_map = r8a78000_mdlc_hscs_mod_fw_4_31_0, */
+ }, {
+ .base = 0xc1990000 /* mdlc_imn */,
+ /* FIXME .power_map = r8a78000_mdlc_imn_power_fw_4_28_0, */
+ /* FIXME .mod_map = r8a78000_mdlc_imn_mod_fw_4_31_0, */
+ }, {
+ .base = 0xc1d90000 /* mdlc_ims */,
+ /* FIXME .power_map = r8a78000_mdlc_ims_power_fw_4_28_0, */
+ /* FIXME .mod_map = r8a78000_mdlc_ims_mod_fw_4_31_0, */
+ }, {
+ .base = 0xcb510000 /* mdlc_gpc */,
+ /* FIXME .power_map = r8a78000_mdlc_gpc_power_fw_4_28_0, */
+ /* FIXME .mod_map = r8a78000_mdlc_gpc_mod_fw_4_31_0, */
+ }, {
+ .base = 0xcbe90000 /* mdlc_dsp */,
+ /* FIXME .power_map = r8a78000_mdlc_dsp_power_fw_4_28_0, */
+ /* FIXME .mod_map = r8a78000_mdlc_dsp_mod_fw_4_31_0, */
+ }, {
+ .base = 0xe9980000 /* mdlc_mm */,
+ /* FIXME .mod_map = r8a78000_mdlc_mm_mod_fw_4_31_0, */
+ }, {
+ .base = 0xd2c30000 /* mdlc_npu0 */,
+ /* FIXME .power_map = r8a78000_mdlc_npu0_power_fw_4_28_0, */
+ /* FIXME .mod_map = r8a78000_mdlc_npu0_mod_fw_4_31_0, */
+ }, {
+ .base = 0xd6c30000 /* mdlc_npu1 */,
+ /* FIXME .power_map = r8a78000_mdlc_npu1_power_fw_4_28_0, */
+ /* FIXME .mod_map = r8a78000_mdlc_npu1_mod_fw_4_31_0, */
+ }, {
+ .base = 0xca410000 /* mdlc_cmnn */,
+ /* FIXME .power_map = r8a78000_mdlc_cmnn_power_fw_4_28_0, */
+ /* FIXME .mod_map = r8a78000_mdlc_cmnn_mod_fw_4_31_0, */
+ }, {
+ .base = 0xca510000 /* mdlc_cmns */,
+ /* FIXME .power_map = r8a78000_mdlc_cmns_power_fw_4_28_0, */
+ /* FIXME .mod_map = r8a78000_mdlc_cmns_mod_fw_4_31_0, */
+ }, {
+ .base = 0xc1330000 /* mdlc_scp */,
+ /* FIXME .mod_map = r8a78000_mdlc_scp_mod_fw_4_31_0, */
+ }, {
+ .base = 0xc1338000 /* mdlc_aon */,
+ /* FIXME .mod_map = r8a78000_mdlc_aon_mod_fw_4_31_0, */
+#endif
+ },
+ { 0 }
+};
+
+static const struct fw_map r8a78000_mdlc_fw_map[] = {
+ { 0x010a0000, r8a78000_mdlc_fw_4_28_0 }, /* SCP FW SDKv4.28.0 */
+ { 0x010d0000, r8a78000_mdlc_fw_4_31_0 }, /* SCP FW SDKv4.31.0 */
+ { 0x010e0000, r8a78000_mdlc_fw_4_31_0 }, /* SCP FW SDKv4.32.0 */
+ { 0, NULL }
+};
+
+static const struct of_device_id r8a78000_mdlc_match[] = {
+ {
+ .compatible = "renesas,r8a78000-mdlc",
+ .data = &r8a78000_mdlc_fw_map,
+ },
+ { /* sentinel */ }
+};
+
+static struct platform_driver r8a78000_mdlc_driver = {
+ .probe = r8a78000_mdlc_probe,
+ .driver = {
+ .name = "r8a78000-mdlc",
+ .of_match_table = r8a78000_mdlc_match,
+ .suppress_bind_attrs = true,
+ },
+};
+
+builtin_platform_driver(r8a78000_mdlc_driver)
+
+MODULE_DESCRIPTION("R-Car X5H MDLC Driver");
diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig
index 2ab150d04bb1f1ef..d4055250de72f1fe 100644
--- a/drivers/soc/renesas/Kconfig
+++ b/drivers/soc/renesas/Kconfig
@@ -358,6 +358,7 @@ config ARCH_R8A78000
default y if ARCH_RENESAS
default ARCH_RENESAS
select ARCH_RCAR_GEN5
+ select MDLC_R8A78000
help
This enables support for the Renesas R-Car X5H SoC.
--
2.43.0
^ permalink raw reply related
* [PATCH/RFC 14/14] arm64: dts: renesas: ironhide: Add CPG/MDLC firmware properties
From: Geert Uytterhoeven @ 2026-04-21 18:11 UTC (permalink / raw)
To: Sudeep Holla, Cristian Marussi, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Magnus Damm, Saravana Kannan, Michael Turquette,
Stephen Boyd, Philipp Zabel, Ulf Hansson, Rafael J . Wysocki,
Kevin Hilman, Florian Fainelli, Wolfram Sang, Marek Vasut,
Kuninori Morimoto
Cc: arm-scmi, linux-arm-kernel, linux-renesas-soc, linux-clk,
devicetree, linux-pm, linux-kernel, Geert Uytterhoeven
In-Reply-To: <cover.1776793163.git.geert+renesas@glider.be>
Link the various Clock Pulse Generator (CPG) and Module Controller
(MDLC) device nodes to their SCMI provider.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
.../boot/dts/renesas/r8a78000-ironhide.dts | 116 ++++++++++++++++++
1 file changed, 116 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts b/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts
index 2fb9557a7eb9dbb7..c6d1a9b5ba433c54 100644
--- a/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts
+++ b/arch/arm64/boot/dts/renesas/r8a78000-ironhide.dts
@@ -99,6 +99,10 @@ memory@1e00000000 {
};
};
+&cpg {
+ firmware = <&scmi>;
+};
+
&extal_clk {
clock-frequency = <16666600>;
};
@@ -112,6 +116,118 @@ &hscif0 {
status = "okay";
};
+&mdlc_aon {
+ firmware = <&scmi>;
+};
+
+&mdlc_cmnn {
+ firmware = <&scmi>;
+};
+
+&mdlc_cmns {
+ firmware = <&scmi>;
+};
+
+&mdlc_ddr0 {
+ firmware = <&scmi>;
+};
+
+&mdlc_ddr1 {
+ firmware = <&scmi>;
+};
+
+&mdlc_ddr2 {
+ firmware = <&scmi>;
+};
+
+&mdlc_ddr3 {
+ firmware = <&scmi>;
+};
+
+&mdlc_ddr4 {
+ firmware = <&scmi>;
+};
+
+&mdlc_ddr5 {
+ firmware = <&scmi>;
+};
+
+&mdlc_ddr6 {
+ firmware = <&scmi>;
+};
+
+&mdlc_ddr7 {
+ firmware = <&scmi>;
+};
+
+&mdlc_dsp {
+ firmware = <&scmi>;
+};
+
+&mdlc_gpc {
+ firmware = <&scmi>;
+};
+
+&mdlc_hscn {
+ firmware = <&scmi>;
+};
+
+&mdlc_hscs {
+ firmware = <&scmi>;
+};
+
+&mdlc_imn {
+ firmware = <&scmi>;
+};
+
+&mdlc_ims {
+ firmware = <&scmi>;
+};
+
+&mdlc_mm {
+ firmware = <&scmi>;
+};
+
+&mdlc_npu0 {
+ firmware = <&scmi>;
+};
+
+&mdlc_npu1 {
+ firmware = <&scmi>;
+};
+
+&mdlc_pere {
+ firmware = <&scmi>;
+};
+
+&mdlc_perw {
+ firmware = <&scmi>;
+};
+
+&mdlc_rt {
+ firmware = <&scmi>;
+};
+
+&mdlc_scp {
+ firmware = <&scmi>;
+};
+
+&mdlc_top {
+ firmware = <&scmi>;
+};
+
+&mdlc_vio {
+ firmware = <&scmi>;
+};
+
+&mdlc_vipn {
+ firmware = <&scmi>;
+};
+
+&mdlc_vips {
+ firmware = <&scmi>;
+};
+
&mfis_scp {
status = "okay";
};
--
2.43.0
^ permalink raw reply related
* Re: tpm: spi: do not call blocking ops when !TASK_RUNNING; during shutdown
From: Jarkko Sakkinen @ 2026-04-21 18:28 UTC (permalink / raw)
To: Peng Fan
Cc: Stefan Wahren, Peter Huewe, Jason Gunthorpe,
linux-arm-kernel@lists.infradead.org,
linux-integrity@vger.kernel.org, kernel@pengutronix.de, Frank Li,
Sascha Hauer, imx@lists.linux.dev
In-Reply-To: <PAXPR04MB84598325136E394E0A7D94D6882C2@PAXPR04MB8459.eurprd04.prod.outlook.com>
On Tue, Apr 21, 2026 at 09:04:43AM +0000, Peng Fan wrote:
> > Subject: tpm: spi: do not call blocking ops when !TASK_RUNNING;
> > during shutdown
> >
> > Hi,
> > we use a custom i.MX93 board, which based on Phytec Phycore i.MX93
> > with a TPM connected via SPI. If I enable
> > CONFIG_DEBUG_ATOMIC_SLEEP=y in our kernel config with mainline
> > kernel 6.18.23 and reboot our board, I will get the following warning:
> > ffff0000000d8000
>
> The issue seems at drivers/char/tpm/tpm_tis_core.c
> 94 rc = wait_event_interruptible_timeout(*queue,
> 95 wait_for_tpm_stat_cond(chip, sts_mask, check_cancel,
> 96 &canceled),
> 97 timeout);
>
> wait_event_interruptible_timeout set task to !TASK_RUNNING,
> but wait_for_tpm_stat_cond still calls into mutex_lock.
>
> Regards
> Peng
>
> > [ 43.422135] Call trace:
> > [ 43.424570] __might_sleep+0x74/0x7c (P)
> > [ 43.428487] mutex_lock+0x24/0x80
> > [ 43.431797] spi_bus_lock+0x20/0x50
> > [ 43.435281] tpm_tis_spi_transfer_full+0x70/0x2c4
> > [ 43.439979] tpm_tis_spi_read_bytes+0x3c/0x48
> > [ 43.444321] tpm_tis_status+0x58/0xf8
> > [ 43.447978] wait_for_tpm_stat_cond+0x30/0x90
> > [ 43.452329] wait_for_tpm_stat+0x1cc/0x2e0
> > [ 43.456419] tpm_tis_send_data+0xdc/0x334
> > [ 43.460423] tpm_tis_send_main+0x74/0x160
> > [ 43.464427] tpm_tis_send+0xd4/0x13c
> > [ 43.467998] tpm_transmit+0xc4/0x3c4
> > [ 43.471569] tpm_transmit_cmd+0x38/0xd4
> > [ 43.475399] tpm2_shutdown+0x6c/0xa4
> > [ 43.478970] tpm_class_shutdown+0x60/0x88
> > [ 43.482974] device_shutdown+0x130/0x25c
> > [ 43.486891] kernel_restart+0x44/0xa4
> > [ 43.490549] __do_sys_reboot+0x114/0x254
> > [ 43.494466] __arm64_sys_reboot+0x24/0x30
> > [ 43.498470] invoke_syscall+0x48/0x10c
> > [ 43.502214] el0_svc_common.constprop.0+0x40/0xe0
> > [ 43.506911] do_el0_svc+0x1c/0x28
> > [ 43.510222] el0_svc+0x34/0xec
> > [ 43.513273] el0t_64_sync_handler+0xa0/0xe4
> > [ 43.517441] el0t_64_sync+0x198/0x19c
> >
> > Best regards
On travel this week but thanks for the report. Investigating next weeek
In the meantime, patches are welcome (whcih I will review next week).
Br, Jarkko
^ permalink raw reply
* Re: [PATCH v7 2/3] dt-bindings: mfd: aspeed,ast2x00-scu: Describe AST2700 SCU0
From: Rob Herring @ 2026-04-21 18:39 UTC (permalink / raw)
To: Billy Tsai
Cc: Lee Jones, Krzysztof Kozlowski, Conor Dooley, Joel Stanley,
Andrew Jeffery, Linus Walleij, Bartosz Golaszewski, Ryan Chen,
Andrew Jeffery, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel, openbmc, linux-gpio, linux-clk
In-Reply-To: <20260416-upstream_pinctrl-v7-2-d72762253163@aspeedtech.com>
On Thu, Apr 16, 2026 at 03:29:44PM +0800, Billy Tsai wrote:
> AST2700 consists of two interconnected SoC instances, each with its own
> System Control Unit (SCU). The SCU0 provides pin control, interrupt
> controllers, clocks, resets, and address-space mappings for the
> Secondary and Tertiary Service Processors (SSP and TSP).
>
> Describe the SSP/TSP address mappings using the standard
> memory-region and memory-region-names properties.
>
> Disallow legacy child nodes that are not present on AST2700, including
> p2a-control and smp-memram. The latter is unnecessary as software can
> access the scratch registers via the SCU syscon.
>
> Also allow the AST2700 SoC0 pin controller to be described as a child
> node of the SCU0, and add an example illustrating the SCU0 layout,
> including reserved-memory, interrupt controllers, and pinctrl.
>
> Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com>
> ---
> .../bindings/mfd/aspeed,ast2x00-scu.yaml | 113 +++++++++++++++++++++
> 1 file changed, 113 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
> index a87f31fce019..215ff59b38ea 100644
> --- a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
> +++ b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml
> @@ -46,6 +46,17 @@ properties:
> '#reset-cells':
> const: 1
>
> + memory-region:
> + items:
> + - description: Region mapped through the first SSP address window.
> + - description: Region mapped through the second SSP address window.
> + - description: Region mapped through the TSP address window.
blank line
> + memory-region-names:
> + items:
> + - const: ssp-0
> + - const: ssp-1
> + - const: tsp
> +
> patternProperties:
> '^p2a-control@[0-9a-f]+$':
> description: >
> @@ -87,6 +98,7 @@ patternProperties:
> - aspeed,ast2400-pinctrl
> - aspeed,ast2500-pinctrl
> - aspeed,ast2600-pinctrl
> + - aspeed,ast2700-soc0-pinctrl
>
> required:
> - compatible
> @@ -156,6 +168,30 @@ required:
> - '#clock-cells'
> - '#reset-cells'
>
> +allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + anyOf:
> + - const: aspeed,ast2700-scu0
> + - const: aspeed,ast2700-scu1
More simply expressed as:
contains:
enum:
- aspeed,ast2700-scu0
- aspeed,ast2700-scu1
> + then:
> + patternProperties:
> + '^p2a-control@[0-9a-f]+$': false
> + '^smp-memram@[0-9a-f]+$': false
^ permalink raw reply
* Re: [PATCH] dt-bindings: Remove the redundant 'type: boolean'
From: Rob Herring (Arm) @ 2026-04-21 18:41 UTC (permalink / raw)
To: phucduc.bui
Cc: linusw, zyw, zhangqing, devicetree, alexandre.belloni, heiko,
gene_chen, linux-input, nick, dmitry.torokhov, gregkh,
claudiu.beznea, linux-arm-kernel, linux-usb, nicolas.ferre,
conor+dt, krzk+dt, lee
In-Reply-To: <20260417021858.6582-1-phucduc.bui@gmail.com>
On Fri, 17 Apr 2026 09:18:58 +0700, phucduc.bui@gmail.com wrote:
> From: bui duc phuc <phucduc.bui@gmail.com>
>
> The 'wakeup-source' property already has its type defined in the core
> schema. Remove the redundant 'type: boolean' from the binding file to
> clean up the binding files.
>
> Signed-off-by: bui duc phuc <phucduc.bui@gmail.com>
> ---
> Documentation/devicetree/bindings/input/atmel,maxtouch.yaml | 3 +--
> Documentation/devicetree/bindings/mfd/rockchip,rk816.yaml | 3 +--
> Documentation/devicetree/bindings/usb/richtek,rt1711h.yaml | 3 +--
> 3 files changed, 3 insertions(+), 6 deletions(-)
>
Applied, thanks!
^ permalink raw reply
* [PATCH] Change manual bitfield manipulation to use FIELD_PREP()
From: Gabriel Jacob Perin @ 2026-04-21 19:31 UTC (permalink / raw)
To: claudiu.beznea, andrei.simion, lgirdwood, broonie, perex, tiwai,
nicolas.ferre, alexandre.belloni
Cc: carlos.albmr, Gabriel Jacob Perin, linux-sound, linux-arm-kernel
Co-developed-by: Carlos Alberto Marques Rabelo <carlos.albmr@usp.br>
Signed-off-by: Carlos Alberto Marques Rabelo <carlos.albmr@usp.br>
Signed-off-by: Gabriel Jacob Perin <gabrieljp@usp.br>
---
sound/soc/atmel/atmel-classd.c | 41 ++++++++++++++++++----------------
1 file changed, 22 insertions(+), 19 deletions(-)
diff --git a/sound/soc/atmel/atmel-classd.c b/sound/soc/atmel/atmel-classd.c
index 1f8c60d2d..6693bdcbb 100644
--- a/sound/soc/atmel/atmel-classd.c
+++ b/sound/soc/atmel/atmel-classd.c
@@ -11,6 +11,7 @@
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
+#include <linux/bitfield.h>
#include <linux/string_choices.h>
#include <sound/core.h>
#include <sound/dmaengine_pcm.h>
@@ -236,34 +237,34 @@ static int atmel_classd_component_probe(struct snd_soc_component *component)
u32 mask, val;
mask = CLASSD_MR_PWMTYP_MASK;
- val = pdata->pwm_type << CLASSD_MR_PWMTYP_SHIFT;
+ val = FIELD_PREP(CLASSD_MR_PWMTYP_MASK, pdata->pwm_type);
mask |= CLASSD_MR_NON_OVERLAP_MASK;
if (pdata->non_overlap_enable) {
- val |= (CLASSD_MR_NON_OVERLAP_EN
- << CLASSD_MR_NON_OVERLAP_SHIFT);
+ val |= FIELD_PREP(CLASSD_MR_NON_OVERLAP_MASK,
+ CLASSD_MR_NON_OVERLAP_EN);
mask |= CLASSD_MR_NOVR_VAL_MASK;
switch (pdata->non_overlap_time) {
case 5:
- val |= (CLASSD_MR_NOVR_VAL_5NS
- << CLASSD_MR_NOVR_VAL_SHIFT);
+ val |= FIELD_PREP(CLASSD_MR_NOVR_VAL_MASK,
+ CLASSD_MR_NOVR_VAL_5NS);
break;
case 10:
- val |= (CLASSD_MR_NOVR_VAL_10NS
- << CLASSD_MR_NOVR_VAL_SHIFT);
+ val |= FIELD_PREP(CLASSD_MR_NOVR_VAL_MASK,
+ CLASSD_MR_NOVR_VAL_10NS);
break;
case 15:
- val |= (CLASSD_MR_NOVR_VAL_15NS
- << CLASSD_MR_NOVR_VAL_SHIFT);
+ val |= FIELD_PREP(CLASSD_MR_NOVR_VAL_MASK,
+ CLASSD_MR_NOVR_VAL_15NS);
break;
case 20:
- val |= (CLASSD_MR_NOVR_VAL_20NS
- << CLASSD_MR_NOVR_VAL_SHIFT);
+ val |= FIELD_PREP(CLASSD_MR_NOVR_VAL_MASK,
+ CLASSD_MR_NOVR_VAL_20NS);
break;
default:
- val |= (CLASSD_MR_NOVR_VAL_10NS
- << CLASSD_MR_NOVR_VAL_SHIFT);
+ val |= FIELD_PREP(CLASSD_MR_NOVR_VAL_MASK,
+ CLASSD_MR_NOVR_VAL_10NS);
dev_warn(component->dev,
"non-overlapping value %d is invalid, the default value 10 is specified\n",
pdata->non_overlap_time);
@@ -370,8 +371,10 @@ atmel_classd_cpu_dai_hw_params(struct snd_pcm_substream *substream,
return ret;
mask = CLASSD_INTPMR_DSP_CLK_FREQ_MASK | CLASSD_INTPMR_FRAME_MASK;
- val = (sample_rates[best].dsp_clk << CLASSD_INTPMR_DSP_CLK_FREQ_SHIFT)
- | (sample_rates[best].sample_rate << CLASSD_INTPMR_FRAME_SHIFT);
+ val = FIELD_PREP(CLASSD_INTPMR_DSP_CLK_FREQ_MASK,
+ sample_rates[best].dsp_clk) |
+ FIELD_PREP(CLASSD_INTPMR_FRAME_MASK,
+ sample_rates[best].sample_rate);
snd_soc_component_update_bits(component, CLASSD_INTPMR, mask, val);
@@ -395,8 +398,8 @@ static int atmel_classd_cpu_dai_prepare(struct snd_pcm_substream *substream,
snd_soc_component_update_bits(component, CLASSD_MR,
CLASSD_MR_LEN_MASK | CLASSD_MR_REN_MASK,
- (CLASSD_MR_LEN_DIS << CLASSD_MR_LEN_SHIFT)
- |(CLASSD_MR_REN_DIS << CLASSD_MR_REN_SHIFT));
+ FIELD_PREP(CLASSD_MR_LEN_MASK, CLASSD_MR_LEN_DIS) |
+ FIELD_PREP(CLASSD_MR_REN_MASK, CLASSD_MR_REN_DIS));
return 0;
}
@@ -418,8 +421,8 @@ static int atmel_classd_cpu_dai_trigger(struct snd_pcm_substream *substream,
case SNDRV_PCM_TRIGGER_STOP:
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
- val = (CLASSD_MR_LEN_DIS << CLASSD_MR_LEN_SHIFT)
- | (CLASSD_MR_REN_DIS << CLASSD_MR_REN_SHIFT);
+ val = FIELD_PREP(CLASSD_MR_LEN_MASK, CLASSD_MR_LEN_DIS) |
+ FIELD_PREP(CLASSD_MR_REN_MASK, CLASSD_MR_REN_DIS);
break;
default:
return -EINVAL;
--
2.25.1
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