* [PATCH v5 3/6] dt-bindings: display: mediatek: ccorr: Add support for MT8196
From: Jay Liu @ 2026-04-27 11:20 UTC (permalink / raw)
To: Chun-Kuang Hu, Philipp Zabel, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno
Cc: dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Jay Liu, Krzysztof Kozlowski
In-Reply-To: <20260427112131.23423-1-jay.liu@mediatek.com>
Add a compatible string for the CCORR IP found in the MT8196 SoC.
Each CCORR IP of this SoC is fully compatible with the ones found
in MT8192.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Jay Liu <jay.liu@mediatek.com>
---
.../devicetree/bindings/display/mediatek/mediatek,ccorr.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
index 5c5068128d0c..a97e758f6571 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ccorr.yaml
@@ -34,6 +34,7 @@ properties:
- mediatek,mt8186-disp-ccorr
- mediatek,mt8188-disp-ccorr
- mediatek,mt8195-disp-ccorr
+ - mediatek,mt8196-disp-ccorr
- const: mediatek,mt8192-disp-ccorr
reg:
--
2.46.0
^ permalink raw reply related
* [PATCH v5 5/6] drm/mediatek: Support multiple CCORR component
From: Jay Liu @ 2026-04-27 11:20 UTC (permalink / raw)
To: Chun-Kuang Hu, Philipp Zabel, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno
Cc: dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Jay Liu
In-Reply-To: <20260427112131.23423-1-jay.liu@mediatek.com>
Add CCORR component support for MT8196.
CCORR is a hardware module that optimizes the visual effects of images
by adjusting the color matrix, enabling features such as night light.
The 8196 SoC has two CCORR hardware units, which must be chained together
in a fixed order in the display path to display the image correctly.
the `mtk_ccorr_ctm_set` API only utilizes one of these units. To prevent
the unused CCORR unit from inadvertently taking effect, we need to block
it in the mtk_crtc.c.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Jay Liu <jay.liu@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_crtc.c | 5 ++++-
drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 3 ++-
drivers/gpu/drm/mediatek/mtk_ddp_comp.h | 7 ++++---
drivers/gpu/drm/mediatek/mtk_disp_ccorr.c | 6 ++++--
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 2 +-
5 files changed, 15 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_crtc.c b/drivers/gpu/drm/mediatek/mtk_crtc.c
index fcb16f3f7b23..09b260a9a4ee 100644
--- a/drivers/gpu/drm/mediatek/mtk_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_crtc.c
@@ -872,11 +872,14 @@ static void mtk_crtc_atomic_flush(struct drm_crtc *crtc,
{
struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
int i;
+ bool ctm_set = false;
if (crtc->state->color_mgmt_changed)
for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
- mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state);
+ /* only set ctm once for the pipeline with two CCORR components */
+ if (!ctm_set)
+ ctm_set = mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state);
}
mtk_crtc_update_config(mtk_crtc, !!mtk_crtc->event);
}
diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
index 9672ea1f91a2..5cbc4b995d66 100644
--- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
@@ -458,7 +458,8 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_DRM_ID_MAX]
[DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal },
[DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal },
[DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL },
- [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr },
+ [DDP_COMPONENT_CCORR0] = { MTK_DISP_CCORR, 0, &ddp_ccorr },
+ [DDP_COMPONENT_CCORR1] = { MTK_DISP_CCORR, 1, &ddp_ccorr },
[DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color },
[DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color },
[DDP_COMPONENT_DITHER0] = { MTK_DISP_DITHER, 0, &ddp_dither },
diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
index 3f3d43f4330d..7244b55f6732 100644
--- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
@@ -77,7 +77,7 @@ struct mtk_ddp_comp_funcs {
struct drm_crtc_state *state);
void (*bgclr_in_on)(struct device *dev);
void (*bgclr_in_off)(struct device *dev);
- void (*ctm_set)(struct device *dev,
+ bool (*ctm_set)(struct device *dev,
struct drm_crtc_state *state);
struct device * (*dma_dev_get)(struct device *dev);
u32 (*get_blend_modes)(struct device *dev);
@@ -254,11 +254,12 @@ static inline void mtk_ddp_comp_bgclr_in_off(struct mtk_ddp_comp *comp)
comp->funcs->bgclr_in_off(comp->dev);
}
-static inline void mtk_ddp_ctm_set(struct mtk_ddp_comp *comp,
+static inline bool mtk_ddp_ctm_set(struct mtk_ddp_comp *comp,
struct drm_crtc_state *state)
{
if (comp->funcs && comp->funcs->ctm_set)
- comp->funcs->ctm_set(comp->dev, state);
+ return comp->funcs->ctm_set(comp->dev, state);
+ return false;
}
static inline struct device *mtk_ddp_comp_dma_dev_get(struct mtk_ddp_comp *comp)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
index 6d7bf4afa78d..ac59d81dbb26 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c
@@ -80,7 +80,7 @@ void mtk_ccorr_stop(struct device *dev)
writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN);
}
-void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state)
+bool mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state)
{
struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev);
struct drm_property_blob *blob = state->ctm;
@@ -92,7 +92,7 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state)
u32 matrix_bits = ccorr->data->matrix_bits;
if (!blob)
- return;
+ return false;
ctm = (struct drm_color_ctm *)blob->data;
input = ctm->matrix;
@@ -110,6 +110,8 @@ void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state)
&ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_3);
mtk_ddp_write(cmdq_pkt, coeffs[8] << 16,
&ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_4);
+
+ return true;
}
static int mtk_disp_ccorr_bind(struct device *dev, struct device *master,
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 679d413bf10b..4203c28c38ce 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -22,7 +22,7 @@ void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state);
void mtk_aal_start(struct device *dev);
void mtk_aal_stop(struct device *dev);
-void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state);
+bool mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state);
int mtk_ccorr_clk_enable(struct device *dev);
void mtk_ccorr_clk_disable(struct device *dev);
void mtk_ccorr_config(struct device *dev, unsigned int w,
--
2.46.0
^ permalink raw reply related
* [PATCH v5 4/6] dt-bindings: display: mediatek: tdshp: Add support for MT8196
From: Jay Liu @ 2026-04-27 11:20 UTC (permalink / raw)
To: Chun-Kuang Hu, Philipp Zabel, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno
Cc: dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Jay Liu
In-Reply-To: <20260427112131.23423-1-jay.liu@mediatek.com>
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset="y", Size: 1643 bytes --]
Add tdshp hardware description for MediaTek MT8196 SoC
Signed-off-by: Jay Liu <jay.liu@mediatek.com>
---
.../display/mediatek/mediatek,tdshp.yaml | 46 +++++++++++++++++++
1 file changed, 46 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,tdshp.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,tdshp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,tdshp.yaml
new file mode 100644
index 000000000000..50b24cc22420
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,tdshp.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,tdshp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek display 2D sharpness processor
+
+maintainers:
+ - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+ - Philipp Zabel <p.zabel@pengutronix.de>
+
+description: |
+ MediaTek display 2D sharpness processor, namely TDSHP, provides a
+ operation used to adjust sharpness in display system.
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt8196-disp-tdshp
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ tdshp@321e0000 {
+ compatible = "mediatek,mt8196-disp-tdshp";
+ reg = <0 0x321e0000 0 0x1000>;
+ clocks = <&dispsys_config_clk 107>;
+ };
+ };
--
2.46.0
^ permalink raw reply related
* [PATCH v5 6/6] drm/mediatek: Add TDSHP component support for MT8196
From: Jay Liu @ 2026-04-27 11:20 UTC (permalink / raw)
To: Chun-Kuang Hu, Philipp Zabel, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno
Cc: dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Jay Liu, CK Hu
In-Reply-To: <20260427112131.23423-1-jay.liu@mediatek.com>
Add TDSHP component support for MT8196.
TDSHP is a hardware module designed to enhance the sharpness and
clarity of displayed images by analyzing and improving edges and
fine details in frames.
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Jay Liu <jay.liu@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 49 +++++++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_ddp_comp.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 +
3 files changed, 52 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
index 5cbc4b995d66..bd2b288938bf 100644
--- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
@@ -57,6 +57,14 @@
#define POSTMASK_RELAY_MODE BIT(0)
#define DISP_REG_POSTMASK_SIZE 0x0030
+#define DISP_REG_TDSHP_CTRL 0x0100
+#define DISP_TDSHP_CTRL_EN BIT(0)
+#define DISP_REG_TDSHP_CFG 0x0110
+#define DISP_TDSHP_RELAY_MODE BIT(0)
+#define DISP_REG_TDSHP_INPUT_SIZE 0x0120
+#define DISP_REG_TDSHP_OUTPUT_OFFSET 0x0124
+#define DISP_REG_TDSHP_OUTPUT_SIZE 0x0128
+
#define DISP_REG_UFO_START 0x0000
#define UFO_BYPASS BIT(2)
@@ -261,6 +269,37 @@ static void mtk_postmask_stop(struct device *dev)
writel_relaxed(0x0, priv->regs + DISP_REG_POSTMASK_EN);
}
+static void mtk_disp_tdshp_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+ mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs,
+ DISP_REG_TDSHP_INPUT_SIZE);
+ mtk_ddp_write(cmdq_pkt, w << 16 | h, &priv->cmdq_reg, priv->regs,
+ DISP_REG_TDSHP_OUTPUT_SIZE);
+ mtk_ddp_write(cmdq_pkt, 0x0, &priv->cmdq_reg, priv->regs,
+ DISP_REG_TDSHP_OUTPUT_OFFSET);
+
+ mtk_ddp_write(cmdq_pkt, DISP_TDSHP_RELAY_MODE, &priv->cmdq_reg,
+ priv->regs, DISP_REG_TDSHP_CFG);
+}
+
+static void mtk_disp_tdshp_start(struct device *dev)
+{
+ struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+ writel(DISP_TDSHP_CTRL_EN, priv->regs + DISP_REG_TDSHP_CTRL);
+}
+
+static void mtk_disp_tdshp_stop(struct device *dev)
+{
+ struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+ writel(0, priv->regs + DISP_REG_TDSHP_CTRL);
+}
+
static void mtk_ufoe_start(struct device *dev)
{
struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
@@ -268,6 +307,14 @@ static void mtk_ufoe_start(struct device *dev)
writel(UFO_BYPASS, priv->regs + DISP_REG_UFO_START);
}
+static const struct mtk_ddp_comp_funcs ddp_tdshp = {
+ .clk_enable = mtk_ddp_clk_enable,
+ .clk_disable = mtk_ddp_clk_disable,
+ .config = mtk_disp_tdshp_config,
+ .start = mtk_disp_tdshp_start,
+ .stop = mtk_disp_tdshp_stop,
+};
+
static const struct mtk_ddp_comp_funcs ddp_aal = {
.clk_enable = mtk_aal_clk_enable,
.clk_disable = mtk_aal_clk_disable,
@@ -441,6 +488,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_POSTMASK] = "postmask",
[MTK_DISP_PWM] = "pwm",
[MTK_DISP_RDMA] = "rdma",
+ [MTK_DISP_TDSHP] = "tdshp",
[MTK_DISP_UFOE] = "ufoe",
[MTK_DISP_WDMA] = "wdma",
[MTK_DP_INTF] = "dp-intf",
@@ -496,6 +544,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_DRM_ID_MAX]
[DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma },
[DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma },
[DDP_COMPONENT_RDMA4] = { MTK_DISP_RDMA, 4, &ddp_rdma },
+ [DDP_COMPONENT_TDSHP0] = { MTK_DISP_TDSHP, 0, &ddp_tdshp },
[DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe },
[DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL },
[DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL },
diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
index 7244b55f6732..cf79b6f689d0 100644
--- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
@@ -38,6 +38,7 @@ enum mtk_ddp_comp_type {
MTK_DISP_POSTMASK,
MTK_DISP_PWM,
MTK_DISP_RDMA,
+ MTK_DISP_TDSHP,
MTK_DISP_UFOE,
MTK_DISP_WDMA,
MTK_DPI,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index c86a3f54f35b..1006834780e4 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -794,6 +794,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_RDMA },
{ .compatible = "mediatek,mt8195-disp-rdma",
.data = (void *)MTK_DISP_RDMA },
+ { .compatible = "mediatek,mt8196-disp-tdshp",
+ .data = (void *)MTK_DISP_TDSHP },
{ .compatible = "mediatek,mt8173-disp-ufoe",
.data = (void *)MTK_DISP_UFOE },
{ .compatible = "mediatek,mt8173-disp-wdma",
--
2.46.0
^ permalink raw reply related
* [PATCH v2] iio: adc: meson-saradc: fix calibration buffer leak on error
From: Felix Gu @ 2026-04-27 11:26 UTC (permalink / raw)
To: Jonathan Cameron, David Lechner, Nuno Sá, Andy Shevchenko,
Neil Armstrong, Kevin Hilman, Jerome Brunet, Martin Blumenstingl,
Rosen Penev
Cc: linux-iio, linux-arm-kernel, linux-amlogic, linux-kernel,
Jonathan Cameron, Felix Gu
meson_sar_adc_temp_sensor_init() allocates a buffer with
nvmem_cell_read(), but the old code leaked it if
syscon_regmap_lookup_by_phandle() failed.
Fix this by adding missing kfree(buf).
Fixes: d6f2eac64403 ("iio: adc: meson: no devm for nvmem_cell_get")
Signed-off-by: Felix Gu <ustc.gu@gmail.com>
---
Changes in v2:
- Switch to a minimal fix according to Jonathan's comment.
- Link to v1: https://lore.kernel.org/r/20260426-meson_saradc-v1-1-6e96b2982c43@gmail.com
---
drivers/iio/adc/meson_saradc.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/iio/adc/meson_saradc.c b/drivers/iio/adc/meson_saradc.c
index 23991a3612bd..000e39ca5c62 100644
--- a/drivers/iio/adc/meson_saradc.c
+++ b/drivers/iio/adc/meson_saradc.c
@@ -817,9 +817,11 @@ static int meson_sar_adc_temp_sensor_init(struct iio_dev *indio_dev)
}
priv->tsc_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "amlogic,hhi-sysctrl");
- if (IS_ERR(priv->tsc_regmap))
+ if (IS_ERR(priv->tsc_regmap)) {
+ kfree(buf);
return dev_err_probe(dev, PTR_ERR(priv->tsc_regmap),
"failed to get amlogic,hhi-sysctrl regmap\n");
+ }
trimming_bits = priv->param->temperature_trimming_bits;
trimming_mask = BIT(trimming_bits) - 1;
---
base-commit: 7080e32d3f09d8688c4a87d81bdcc71f7f606b16
change-id: 20260425-meson_saradc-54abc52d9b31
Best regards,
--
Felix Gu <ustc.gu@gmail.com>
^ permalink raw reply related
* Re: [PATCH] iio: adc: mt6359: fix unchecked return value in mt6358_read_imp
From: Salah Triki @ 2026-04-27 11:31 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Jonathan Cameron, David Lechner, Nuno Sá, Andy Shevchenko,
Matthias Brugger, AngeloGioacchino Del Regno, linux-iio,
linux-kernel, linux-arm-kernel, linux-mediatek
In-Reply-To: <ae8pAGBGGOvsURka@ashevche-desk.local>
On Mon, Apr 27, 2026 at 12:14:40PM +0300, Andy Shevchenko wrote:
> On Mon, Apr 27, 2026 at 09:54:57AM +0100, Salah Triki wrote:
> > In mt6358_read_imp(), the return value of regmap_read() is currently
> > ignored. This is problematic because if the bus read fails the variable
> > val_v remains uninitialized.
> >
> > The function subsequently assigns this uninitialized stack value to
> > *vbat, leading to incorrect measurement results being reported to
> > the IIO subsystem without any error indication.
> >
> > Update the function to check the return value of regmap_read(). Ensure
> > that mt6358_stop_imp_conv() is still called to clean up the hardware
> > state before returning the error code.
>
> Sounds like this deserves a Fixes tag, but the problem is that the whole driver
> is written like this. Why does having this fixed make it special?
>
> --
> With Best Regards,
> Andy Shevchenko
>
>
You are right, Andy. I noticed that several other functions in this driver
share the same issue. I will send a V2 that addresses all unchecked
regmap_read() calls in this file and I will include the Fixes tag. Thanks
for the feedback.
Best Regards
Salah Triki
^ permalink raw reply
* Re: [PATCH] KVM: arm64: Validate the FF-A memory access descriptor placement
From: Sebastian Ene @ 2026-04-27 11:36 UTC (permalink / raw)
To: Sudeep Holla
Cc: Marc Zyngier, oupton, will, ayrton, catalin.marinas, joey.gouly,
korneld, kvmarm, linux-arm-kernel, linux-kernel, android-kvm,
mrigendra.chaubey, perlarsen, suzuki.poulose, yuzenghui, stable
In-Reply-To: <20260423-just-mega-starfish-22309c@sudeepholla>
On Thu, Apr 23, 2026 at 10:55:34AM +0100, Sudeep Holla wrote:
> On Thu, Apr 23, 2026 at 09:17:49AM +0000, Sebastian Ene wrote:
> > On Wed, Apr 22, 2026 at 08:29:06PM +0100, Sudeep Holla wrote:
>
> [...]
>
> > Hello Sudeep,
> >
> > > That's just the current choice in the driver and can be changed in the future.
> > >
> > > > and makes use of the same assumption in: ffa_mem_desc_offset().
> > > > https://elixir.bootlin.com/linux/v7.0/source/include/linux/arm_ffa.h#L448
> > >
> > > Again this is just in the transmit path of the message the driver is
> > > constructing and hence it is a simple choice rather than wrong assumption.
> > >
> > > > The later one seems wrong IMO. because we should compute the offset
> > > > based on the value stored in ep_mem_offset and not adding it up with
> > > > sizeof(struct ffa_mem_region).
> > > >
> > >
> > > Sorry what am I missing as the driver is building these descriptors to
> > > send it across to SPMC, we are populating the field and it will be 0
> > > before it is initialised
> >
> > Right, what I meant is having something like this since this function is not limited
> > to the driver scope and using it from other components would imply relying on the
> > assumption: 'ep_mem_offset == sizeof(struct ffa_mem_region)'. We will also have to validate
> > that the `ep_mem_offset` doesn't point outside of the mailbox designated buffer.
> >
>
> Sure, we can extend the function itself or add addition helper to get the
> functionality you are looking for the validation.
>
Thanks, would it be ok to BUG_ON if the offset is out of range here ?
(we would probably have to pass the size of the buf as well in this
function)
> > ---
> > diff --git a/include/linux/arm_ffa.h b/include/linux/arm_ffa.h
> > index 81e603839c4a..62d67dae8b70 100644
> > --- a/include/linux/arm_ffa.h
> > +++ b/include/linux/arm_ffa.h
> > @@ -445,7 +445,7 @@ ffa_mem_desc_offset(struct ffa_mem_region *buf, int count, u32 ffa_version)
> > if (!FFA_MEM_REGION_HAS_EP_MEM_OFFSET(ffa_version))
> > offset += offsetof(struct ffa_mem_region, ep_mem_offset);
> > else
> > - offset += sizeof(struct ffa_mem_region);
> > + offset += buf->ep_mem_offset;
> >
> > return offset;
> > }
> > ---
> >
> > And then move `ffa_mem_region_additional_setup` to be called earlier before `ffa_mem_desc_offset`:
> > (so that it can setup the value for ep_mem_offset)
> >
> > ---
> > diff --git a/drivers/firmware/arm_ffa/driver.c b/drivers/firmware/arm_ffa/driver.c
> > index f2f94d4d533e..66de59c88aff 100644
> > --- a/drivers/firmware/arm_ffa/driver.c
> > +++ b/drivers/firmware/arm_ffa/driver.c
> > @@ -691,6 +691,8 @@ ffa_setup_and_transmit(u32 func_id, void *buffer, u32 max_fragsize,
> > mem_region->flags = args->flags;
> > mem_region->sender_id = drv_info->vm_id;
> > mem_region->attributes = ffa_memory_attributes_get(func_id);
> > +
> > + ffa_mem_region_additional_setup(drv_info->version, mem_region);
>
> Ah this could do the trick. I need to check if all the usages are covered
> though.
>
I looked a bit at the call paths and I think we can use it like this.
Please let me know if you found it differently. I would like to re-spin
another version of this patch.
> > composite_offset = ffa_mem_desc_offset(buffer, args->nattrs,
> > drv_info->version);
> >
> > @@ -708,7 +710,6 @@ ffa_setup_and_transmit(u32 func_id, void *buffer, u32 max_fragsize,
> > }
> > mem_region->handle = 0;
> > mem_region->ep_count = args->nattrs;
> > - ffa_mem_region_additional_setup(drv_info->version, mem_region);
> > ---
> >
> > >
> > > > Maybe this should be the fix instead and not the one in pKVM ? What do
> > > > you think ?
> > > >
> > >
> > > Can you share the diff you have in mind to understand your concern better
> > > or are you referring to this patch itself.
> >
> > Sure, please let me know if you think this is wrong. I might have misunderstood it.
> >
>
> Nope, the patch helped to understand it quicker. Thanks for that.
>
> > >
> > > > The current implementation in pKVM makes use of the
> > > > ffa_mem_desc_offset() to validate the first EMAD. If a compromised host
> > > > places an EMAD at a different offset than sizeof(struct ffa_mem_region),
> > > > then pKVM will not validate that EMAD.
> > > >
> > >
> > > Calling the host as compromised if it chooses a different offset seems bit
> > > of extreme here. I am no sure if I am missing to understand something here.
> > >
> >
> > Sorry for not explaining it, in pKVM model we don't trust the host kernel so
> > we can assume that everything that doesn't pass the hypervisor validation(in
> > this case the ff-a memory transaction) can be a potential attack that wants
> > to compromise EL2.
> >
>
> I am aware of the principle in general, but this example with different offset
> can't be assumed as comprised host if the offset + size is well within the
> Tx buffer size boundaries. That should be the way for you to cross check for
> any compromise IHMO.
>
I agree, it cannot be assumed as a compromised host it can be perferctly
normal with another driver that places it at a different offset; that's
why I suggested patching ffa_mem_desc_offset instead and doing the
ep_mem_offset validation there.
> --
> Regards,
> Sudeep
Thanks,
Sebastian
^ permalink raw reply
* Re: [PATCH] arm64: dts: rockchip: fix rk809 interrupt pin on rk3566-roc-pc
From: Heiko Stuebner @ 2026-04-27 11:41 UTC (permalink / raw)
To: guoweix
Cc: robh, krzk+dt, conor+dt, f.kardame, pgwipeout, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel, guoweix
In-Reply-To: <tencent_CF3170E7191769F8FB22C55A0F952E82E105@qq.com>
Hi,
Am Mittwoch, 8. April 2026, 17:09:44 Mitteleuropäische Sommerzeit schrieb guoweix:
> The RK809 PMIC interrupt pin on the Firefly ROC-RK3566-PC (Station M2)
> is physically connected to GPIO0_A3 (RK_PA3) according to the board's
> schematic.
>
> Currently, the PMIC node incorrectly specifies RK_PA7 for the interrupt,
> which prevents the PMIC from correctly signaling interrupts. (Note that
> the pinctrl node 'pmic_int' correctly configures RK_PA3).
>
> Fix this by updating the interrupts property to use RK_PA3.
>
> Fixes: 30ac9b4e25d8 ("arm64: dts: rockchip: add dts for Firefly Station M2 rk3566")
>
> Signed-off-by: guoweix <2298701336@qq.com>
Could you use the more standard naming of "given name + surname" please?
For example with:
git commit --amend --author="givenname surname <2298701336@qq.com>"
Or setting user.name in your .gitconfig.
Patch otherwise looks good.
Thanks a lot
Heiko
> ---
> arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts
> index 7e499064e035..985770e3a5e2 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts
> +++ b/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts
> @@ -245,7 +245,7 @@ rk809: pmic@20 {
> compatible = "rockchip,rk809";
> reg = <0x20>;
> interrupt-parent = <&gpio0>;
> - interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>;
> + interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
> clock-output-names = "rk808-clkout1", "rk808-clkout2";
> assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
> assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
>
^ permalink raw reply
* [PATCH] PCI: imx6: Keep Root Port MSI capability also for i.MX6Q
From: Soeren Moch @ 2026-04-27 11:58 UTC (permalink / raw)
To: Richard Zhu
Cc: Soeren Moch, stable, Manivannan Sadhasivam, Lucas Stach,
Bjorn Helgaas, Frank Li, Fabio Estevam, linux-pci,
linux-arm-kernel, imx, linux-kernel
Also on the NXP i.MX6Q chipset MSIs from the endpoints won't be received by
the iMSI-RX MSI controller if the Root Port MSI capability is disabled.
Even though the Root Port MSIs won't be received by the iMSI-RX controller
due to design, this chipset has some weird hardware bug that prevents
the endpoint MSIs from reaching when the Root Port MSI capability is
disabled.
Hence, always keep the Root Port MSI capability for this chipset.
Note that by keeping Root Port MSI capability, Root Port MSIs such as AER,
PME and others won't be received by default. So users need to use
workarounds such as passing 'pcie_pme=nomsi' cmdline param.
Fixes: 3a4e8302e72f ("PCI: imx6: Keep Root Port MSI capability with iMSI-RX to work around hardware bug")
Cc: <stable@vger.kernel.org> # 7.0.x
Signed-off-by: Soeren Moch <smoch@web.de>
---
Cc: Manivannan Sadhasivam <mani@kernel.org>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Frank Li <Frank.Li@nxp.com>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: linux-pci@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: imx@lists.linux.dev
Cc: linux-kernel@vger.kernel.org
Tested on a tbs2910 board [1]
[1] arch/arm/boot/dts/nxp/imx/imx6q-tbs2910.dts
---
drivers/pci/controller/dwc/pci-imx6.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 6d6a1688e7eb..3d461bdef967 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -1865,7 +1865,8 @@ static const struct imx_pcie_drvdata drvdata[] = {
.flags = IMX_PCIE_FLAG_IMX_PHY |
IMX_PCIE_FLAG_SPEED_CHANGE_WORKAROUND |
IMX_PCIE_FLAG_BROKEN_SUSPEND |
- IMX_PCIE_FLAG_SUPPORTS_SUSPEND,
+ IMX_PCIE_FLAG_SUPPORTS_SUSPEND |
+ IMX_PCIE_FLAG_KEEP_MSI_CAP,
.dbi_length = 0x200,
.gpr = "fsl,imx6q-iomuxc-gpr",
.ltssm_off = IOMUXC_GPR12,
--
2.43.0
^ permalink raw reply related
* [PATCH v2 0/5] POE sigreturn fix and extra tests
From: Kevin Brodsky @ 2026-04-27 12:03 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Kevin Brodsky, Andrew Morton, Catalin Marinas,
David Hildenbrand (Arm), Joey Gouly, Mark Brown, Shuah Khan,
Will Deacon, linux-kselftest, linux-mm, linux-kernel
Commit 2e8a1acea859 ("arm64: signal: Improve POR_EL0 handling to
avoid uaccess failures") introduced special handling for EL0 registers
that impact uaccess. This did not however handle the case where a signal
handler removes the relevant record (poe_context for POE) from the
signal frame; this is clearly not typical behaviour but it is legal.
That commit resulted in arbitrary data from the kernel stack being
written to POR_EL0 in that case.
Patch 1 fixes this by tracking which fields in struct user_access_state
are actually valid. This restores the original behaviour, where POR_EL0
is left untouched if poe_context is removed.
The remaining patches add new tests to the arm64 signal kselftests to
check that POR_EL0 is reset and restored (or preserved) as expected.
Patch 2 fixes an issue found by Sashiko while reusing some code for
the new tests.
Signed-off-by: Kevin Brodsky <kevin.brodsky@arm.com>
---
v1..v2:
- Patch 1: introduced accessors and moved to using {} for zero-init
[Will]
- Patch 1: removed change in setup_sigframe() - using the new flag
isn't actually more consistent than checking system_supports_poe()
and doesn't play well with the new accessors
- Patch 5: fixed the size passed to get_header(), as reported by
Sashiko. Added patch 2 to fix the issue where I had originally
found it.
- Patch 4: improved commit title [Mark]
- Collected R-b
v1: https://lore.kernel.org/all/20260421144252.1440365-1-kevin.brodsky@arm.com/
---
To: linux-arm-kernel@lists.infradead.org
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: David Hildenbrand (Arm) <david@kernel.org>
Cc: Joey Gouly <joey.gouly@arm.com>
Cc: Mark Brown <broonie@kernel.org>
Cc: Shuah Khan <shuah@kernel.org>
Cc: Will Deacon <will@kernel.org>
Cc: linux-kselftest@vger.kernel.org
Cc: linux-mm@kvack.org
Cc: linux-kernel@vger.kernel.org
---
Kevin Brodsky (5):
arm64: signal: Preserve POR_EL0 if poe_context is missing
selftests/mm: Fix resv_sz when parsing arm64 signal frame
kselftest/arm64: Add POE as a feature in the signal tests
kselftest/arm64: Move/add POE helpers to test_signals_utils.h
kselftest/arm64: Add tests for POR_EL0 save/reset/restore
arch/arm64/kernel/signal.c | 54 ++++++++++++----
.../testing/selftests/arm64/signal/test_signals.h | 2 +
.../selftests/arm64/signal/test_signals_utils.c | 3 +
.../selftests/arm64/signal/test_signals_utils.h | 16 +++++
.../signal/testcases/poe_missing_poe_context.c | 73 ++++++++++++++++++++++
.../selftests/arm64/signal/testcases/poe_restore.c | 64 +++++++++++++++++++
.../selftests/arm64/signal/testcases/poe_siginfo.c | 15 -----
tools/testing/selftests/mm/pkey-arm64.h | 3 +-
8 files changed, 203 insertions(+), 27 deletions(-)
---
base-commit: 028ef9c96e96197026887c0f092424679298aae8
change-id: 20260423-poe_signal-809193c5225d
^ permalink raw reply
* [PATCH v2 1/5] arm64: signal: Preserve POR_EL0 if poe_context is missing
From: Kevin Brodsky @ 2026-04-27 12:03 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Kevin Brodsky, Andrew Morton, Catalin Marinas,
David Hildenbrand (Arm), Joey Gouly, Mark Brown, Shuah Khan,
Will Deacon, linux-kselftest, linux-mm, linux-kernel
In-Reply-To: <20260427-poe_signal-v2-0-2bd9d6f16ab4@arm.com>
Commit 2e8a1acea859 ("arm64: signal: Improve POR_EL0 handling to
avoid uaccess failures") delayed the write to POR_EL0 in
rt_sigreturn to avoid spurious uaccess failures. This change however
relies on the poe_context frame record being present: on a system
supporting POE, calling sigreturn without a poe_context record now
results in writing arbitrary data from the kernel stack into POR_EL0.
Fix this by adding a __valid_fields member to struct
user_access_state, and zeroing the struct on allocation.
restore_poe_context() then indicates that the por_el0 field is valid
by setting the corresponding bit in __valid_fields, and
restore_user_access_state() only touches POR_EL0 if there is a valid
value to set it to. This is in line with how POR_EL0 was originally
handled; all frame records are currently optional, except
fpsimd_context.
To ensure that __valid_fields is kept in sync, fields (currently
just por_el0) are now accessed via accessors and prefixed with __ to
discourage direct access.
Fixes: 2e8a1acea859 ("arm64: signal: Improve POR_EL0 handling to avoid uaccess failures")
Reported-by: Will Deacon <will@kernel.org>
Signed-off-by: Kevin Brodsky <kevin.brodsky@arm.com>
---
arch/arm64/kernel/signal.c | 54 ++++++++++++++++++++++++++++++++++++----------
1 file changed, 43 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/kernel/signal.c b/arch/arm64/kernel/signal.c
index 08ffc5a5aea4..38e6fa204c17 100644
--- a/arch/arm64/kernel/signal.c
+++ b/arch/arm64/kernel/signal.c
@@ -67,6 +67,9 @@ struct rt_sigframe_user_layout {
unsigned long end_offset;
};
+#define TERMINATOR_SIZE round_up(sizeof(struct _aarch64_ctx), 16)
+#define EXTRA_CONTEXT_SIZE round_up(sizeof(struct extra_context), 16)
+
/*
* Holds any EL0-controlled state that influences unprivileged memory accesses.
* This includes both accesses done in userspace and uaccess done in the kernel.
@@ -74,13 +77,35 @@ struct rt_sigframe_user_layout {
* This state needs to be carefully managed to ensure that it doesn't cause
* uaccess to fail when setting up the signal frame, and the signal handler
* itself also expects a well-defined state when entered.
+ *
+ * The struct should be zero-initialised. Its members should only be accessed
+ * via the accessors below. __valid_fields tracks which of the fields are valid
+ * (have been set to some value).
*/
struct user_access_state {
- u64 por_el0;
+ unsigned int __valid_fields;
+ u64 __por_el0;
};
-#define TERMINATOR_SIZE round_up(sizeof(struct _aarch64_ctx), 16)
-#define EXTRA_CONTEXT_SIZE round_up(sizeof(struct extra_context), 16)
+#define UA_STATE_HAS_POR_EL0 BIT(0)
+
+static void set_ua_state_por_el0(struct user_access_state *ua_state,
+ u64 por_el0)
+{
+ ua_state->__por_el0 = por_el0;
+ ua_state->__valid_fields |= UA_STATE_HAS_POR_EL0;
+}
+
+static int get_ua_state_por_el0(const struct user_access_state *ua_state,
+ u64 *por_el0)
+{
+ if (ua_state->__valid_fields & UA_STATE_HAS_POR_EL0) {
+ *por_el0 = ua_state->__por_el0;
+ return 0;
+ }
+
+ return -ENOENT;
+}
/*
* Save the user access state into ua_state and reset it to disable any
@@ -94,7 +119,7 @@ static void save_reset_user_access_state(struct user_access_state *ua_state)
for (int pkey = 0; pkey < arch_max_pkey(); pkey++)
por_enable_all |= POR_ELx_PERM_PREP(pkey, POE_RWX);
- ua_state->por_el0 = read_sysreg_s(SYS_POR_EL0);
+ set_ua_state_por_el0(ua_state, read_sysreg_s(SYS_POR_EL0));
write_sysreg_s(por_enable_all, SYS_POR_EL0);
/*
* No ISB required as we can tolerate spurious Overlay faults -
@@ -122,8 +147,10 @@ static void set_handler_user_access_state(void)
*/
static void restore_user_access_state(const struct user_access_state *ua_state)
{
- if (system_supports_poe())
- write_sysreg_s(ua_state->por_el0, SYS_POR_EL0);
+ u64 por_el0;
+
+ if (get_ua_state_por_el0(ua_state, &por_el0) == 0)
+ write_sysreg_s(por_el0, SYS_POR_EL0);
}
static void init_user_layout(struct rt_sigframe_user_layout *user)
@@ -333,11 +360,16 @@ static int restore_fpmr_context(struct user_ctxs *user)
static int preserve_poe_context(struct poe_context __user *ctx,
const struct user_access_state *ua_state)
{
- int err = 0;
+ int err;
+ u64 por_el0;
+
+ err = get_ua_state_por_el0(ua_state, &por_el0);
+ if (WARN_ON_ONCE(err))
+ return err;
__put_user_error(POE_MAGIC, &ctx->head.magic, err);
__put_user_error(sizeof(*ctx), &ctx->head.size, err);
- __put_user_error(ua_state->por_el0, &ctx->por_el0, err);
+ __put_user_error(por_el0, &ctx->por_el0, err);
return err;
}
@@ -353,7 +385,7 @@ static int restore_poe_context(struct user_ctxs *user,
__get_user_error(por_el0, &(user->poe->por_el0), err);
if (!err)
- ua_state->por_el0 = por_el0;
+ set_ua_state_por_el0(ua_state, por_el0);
return err;
}
@@ -1095,7 +1127,7 @@ SYSCALL_DEFINE0(rt_sigreturn)
{
struct pt_regs *regs = current_pt_regs();
struct rt_sigframe __user *frame;
- struct user_access_state ua_state;
+ struct user_access_state ua_state = {};
/* Always make any pending restarted system calls return -EINTR */
current->restart_block.fn = do_no_restart_syscall;
@@ -1507,7 +1539,7 @@ static int setup_rt_frame(int usig, struct ksignal *ksig, sigset_t *set,
{
struct rt_sigframe_user_layout user;
struct rt_sigframe __user *frame;
- struct user_access_state ua_state;
+ struct user_access_state ua_state = {};
int err = 0;
fpsimd_save_and_flush_current_state();
--
2.51.2
^ permalink raw reply related
* [PATCH v2 3/5] kselftest/arm64: Add POE as a feature in the signal tests
From: Kevin Brodsky @ 2026-04-27 12:03 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Kevin Brodsky, Andrew Morton, Catalin Marinas,
David Hildenbrand (Arm), Joey Gouly, Mark Brown, Shuah Khan,
Will Deacon, linux-kselftest, linux-mm, linux-kernel
In-Reply-To: <20260427-poe_signal-v2-0-2bd9d6f16ab4@arm.com>
Add the POE feature to the signal tests framework, to allow tests to
require it.
Reviewed-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Kevin Brodsky <kevin.brodsky@arm.com>
---
tools/testing/selftests/arm64/signal/test_signals.h | 2 ++
tools/testing/selftests/arm64/signal/test_signals_utils.c | 3 +++
2 files changed, 5 insertions(+)
diff --git a/tools/testing/selftests/arm64/signal/test_signals.h b/tools/testing/selftests/arm64/signal/test_signals.h
index ee75a2c25ce7..c7c343494cb8 100644
--- a/tools/testing/selftests/arm64/signal/test_signals.h
+++ b/tools/testing/selftests/arm64/signal/test_signals.h
@@ -36,6 +36,7 @@ enum {
FSME_FA64_BIT,
FSME2_BIT,
FGCS_BIT,
+ FPOE_BIT,
FMAX_END
};
@@ -45,6 +46,7 @@ enum {
#define FEAT_SME_FA64 (1UL << FSME_FA64_BIT)
#define FEAT_SME2 (1UL << FSME2_BIT)
#define FEAT_GCS (1UL << FGCS_BIT)
+#define FEAT_POE (1UL << FPOE_BIT)
/*
* A descriptor used to describe and configure a test case.
diff --git a/tools/testing/selftests/arm64/signal/test_signals_utils.c b/tools/testing/selftests/arm64/signal/test_signals_utils.c
index 5d3621921cfe..4b12dbd7669d 100644
--- a/tools/testing/selftests/arm64/signal/test_signals_utils.c
+++ b/tools/testing/selftests/arm64/signal/test_signals_utils.c
@@ -31,6 +31,7 @@ static char const *const feats_names[FMAX_END] = {
" FA64 ",
" SME2 ",
" GCS ",
+ " POE ",
};
#define MAX_FEATS_SZ 128
@@ -341,6 +342,8 @@ int test_init(struct tdescr *td)
td->feats_supported |= FEAT_SME2;
if (getauxval(AT_HWCAP) & HWCAP_GCS)
td->feats_supported |= FEAT_GCS;
+ if (getauxval(AT_HWCAP2) & HWCAP2_POE)
+ td->feats_supported |= FEAT_POE;
if (feats_ok(td)) {
if (td->feats_required & td->feats_supported)
fprintf(stderr,
--
2.51.2
^ permalink raw reply related
* [PATCH v2 4/5] kselftest/arm64: Move/add POE helpers to test_signals_utils.h
From: Kevin Brodsky @ 2026-04-27 12:03 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Kevin Brodsky, Andrew Morton, Catalin Marinas,
David Hildenbrand (Arm), Joey Gouly, Mark Brown, Shuah Khan,
Will Deacon, linux-kselftest, linux-mm, linux-kernel
In-Reply-To: <20260427-poe_signal-v2-0-2bd9d6f16ab4@arm.com>
In preparation to adding further POE signal tests, move
get_por_el0() to test_signals_utils.h and add set_por_el0().
Reviewed-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Kevin Brodsky <kevin.brodsky@arm.com>
---
.../testing/selftests/arm64/signal/test_signals_utils.h | 16 ++++++++++++++++
.../selftests/arm64/signal/testcases/poe_siginfo.c | 15 ---------------
2 files changed, 16 insertions(+), 15 deletions(-)
diff --git a/tools/testing/selftests/arm64/signal/test_signals_utils.h b/tools/testing/selftests/arm64/signal/test_signals_utils.h
index 36fc12b3cd60..2c7b8c64a35a 100644
--- a/tools/testing/selftests/arm64/signal/test_signals_utils.h
+++ b/tools/testing/selftests/arm64/signal/test_signals_utils.h
@@ -57,6 +57,22 @@ static inline __attribute__((always_inline)) uint64_t get_gcspr_el0(void)
return val;
}
+#define SYS_POR_EL0 "S3_3_C10_C2_4"
+
+static inline uint64_t get_por_el0(void)
+{
+ uint64_t val;
+
+ asm volatile("mrs %0, " SYS_POR_EL0 "\n" : "=r"(val));
+
+ return val;
+}
+
+static inline void set_por_el0(uint64_t val)
+{
+ asm volatile("msr " SYS_POR_EL0 ", %0\n" :: "r"(val));
+}
+
static inline bool feats_ok(struct tdescr *td)
{
if (td->feats_incompatible & td->feats_supported)
diff --git a/tools/testing/selftests/arm64/signal/testcases/poe_siginfo.c b/tools/testing/selftests/arm64/signal/testcases/poe_siginfo.c
index 36bd9940ee05..e15fedf4da6e 100644
--- a/tools/testing/selftests/arm64/signal/testcases/poe_siginfo.c
+++ b/tools/testing/selftests/arm64/signal/testcases/poe_siginfo.c
@@ -21,21 +21,6 @@ static union {
char buf[1024 * 128];
} context;
-#define SYS_POR_EL0 "S3_3_C10_C2_4"
-
-static uint64_t get_por_el0(void)
-{
- uint64_t val;
-
- asm volatile(
- "mrs %0, " SYS_POR_EL0 "\n"
- : "=r"(val)
- :
- : );
-
- return val;
-}
-
int poe_present(struct tdescr *td, siginfo_t *si, ucontext_t *uc)
{
struct _aarch64_ctx *head = GET_BUF_RESV_HEAD(context);
--
2.51.2
^ permalink raw reply related
* [PATCH v2 2/5] selftests/mm: Fix resv_sz when parsing arm64 signal frame
From: Kevin Brodsky @ 2026-04-27 12:03 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Kevin Brodsky, Andrew Morton, Catalin Marinas,
David Hildenbrand (Arm), Joey Gouly, Mark Brown, Shuah Khan,
Will Deacon, linux-kselftest, linux-mm, linux-kernel
In-Reply-To: <20260427-poe_signal-v2-0-2bd9d6f16ab4@arm.com>
get_header() wants the size of the reserved area in struct
sigcontext, but instead we pass it the size of the entire struct.
This could in theory result in an out-of-bounds read (if the signal
frame is malformed).
Fix this using one of the existing macros from
tools/testing/selftests/arm64/signal/testcases/testcases.h.
This issue was reported by Sashiko on a patch that copied this
portion of the code.
Link: https://sashiko.dev/#/patchset/20260421144252.1440365-1-kevin.brodsky%40arm.com
Fixes: f5b5ea51f78f ("selftests: mm: make protection_keys test work on arm64")
Signed-off-by: Kevin Brodsky <kevin.brodsky@arm.com>
---
tools/testing/selftests/mm/pkey-arm64.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/tools/testing/selftests/mm/pkey-arm64.h b/tools/testing/selftests/mm/pkey-arm64.h
index 8e9685e03c44..c5a78a2f211d 100644
--- a/tools/testing/selftests/mm/pkey-arm64.h
+++ b/tools/testing/selftests/mm/pkey-arm64.h
@@ -130,9 +130,10 @@ static inline u64 get_pkey_bits(u64 reg, int pkey)
static inline void aarch64_write_signal_pkey(ucontext_t *uctxt, u64 pkey)
{
struct _aarch64_ctx *ctx = GET_UC_RESV_HEAD(uctxt);
+ size_t resv_size = GET_UCP_RESV_SIZE(uctxt);
struct poe_context *poe_ctx =
(struct poe_context *) get_header(ctx, POE_MAGIC,
- sizeof(uctxt->uc_mcontext), NULL);
+ resv_size, NULL);
if (poe_ctx)
poe_ctx->por_el0 = pkey;
}
--
2.51.2
^ permalink raw reply related
* [PATCH v2 5/5] kselftest/arm64: Add tests for POR_EL0 save/reset/restore
From: Kevin Brodsky @ 2026-04-27 12:03 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Kevin Brodsky, Andrew Morton, Catalin Marinas,
David Hildenbrand (Arm), Joey Gouly, Mark Brown, Shuah Khan,
Will Deacon, linux-kselftest, linux-mm, linux-kernel
In-Reply-To: <20260427-poe_signal-v2-0-2bd9d6f16ab4@arm.com>
POR_EL0 is expected to be:
- Saved in the poe_context record
- Reset to POR_EL0_INIT when invoking the signal handler
- Restored from poe_context when returning from the signal handler
Add a new test, poe_restore, to check that the save/reset/restore
mechanism is working as intended. See commit 2e8a1acea859 ("arm64:
signal: Improve POR_EL0 handling to avoid uaccess failures") for
more details.
This commit did not handle the case where poe_context is missing
correctly. This was recently fixed; add a new test,
poe_missing_poe_context, to check this case.
Note: td->pass is only set to true at the very end, as an unexpected
signal may occur in case of failure (especially in
poe_missing_poe_context if POR_EL0 is restored to an invalid value).
Failures are tracked with a global, failed_check.
Signed-off-by: Kevin Brodsky <kevin.brodsky@arm.com>
---
.../signal/testcases/poe_missing_poe_context.c | 73 ++++++++++++++++++++++
.../selftests/arm64/signal/testcases/poe_restore.c | 64 +++++++++++++++++++
2 files changed, 137 insertions(+)
diff --git a/tools/testing/selftests/arm64/signal/testcases/poe_missing_poe_context.c b/tools/testing/selftests/arm64/signal/testcases/poe_missing_poe_context.c
new file mode 100644
index 000000000000..3f22d8cf6106
--- /dev/null
+++ b/tools/testing/selftests/arm64/signal/testcases/poe_missing_poe_context.c
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2026 Arm Ltd
+ *
+ * Verify that the POR_EL0 register is left untouched on sigreturn if the
+ * POE frame record is missing.
+ */
+
+#include <asm/sigcontext.h>
+
+#include "test_signals_utils.h"
+#include "testcases.h"
+
+#define POR_EL0_INIT 0x07ul
+#define POR_EL0_CUSTOM 0x77ul
+
+static bool failed_check;
+
+static bool modify_por_el0(struct tdescr *td)
+{
+ set_por_el0(POR_EL0_CUSTOM);
+
+ return true;
+}
+
+static int signal_remove_poe_context(struct tdescr *td, siginfo_t *si,
+ ucontext_t *uc)
+{
+ struct _aarch64_ctx *ctx = GET_UC_RESV_HEAD(uc);
+ size_t resv_size = GET_UCP_RESV_SIZE(uc);
+ struct _aarch64_ctx *poe_ctx_head;
+
+ poe_ctx_head = get_header(ctx, POE_MAGIC, resv_size, NULL);
+ if (!poe_ctx_head) {
+ fprintf(stderr, "Missing poe_context record\n");
+ failed_check = true;
+ return 0;
+ }
+
+ /*
+ * Actually removing the record would require moving down the next
+ * records. An easier option is to turn it into an ESR record, which is
+ * ignored by sigreturn().
+ */
+ poe_ctx_head->magic = ESR_MAGIC;
+
+ return 0;
+}
+
+static void check_por_el0_preserved(struct tdescr *td)
+{
+ uint64_t por_el0 = get_por_el0();
+
+ if (por_el0 == POR_EL0_INIT) {
+ fprintf(stderr, "POR_EL0 preserved\n");
+ } else {
+ fprintf(stderr, "POR_EL0 unexpectedly set to %lx\n", por_el0);
+ failed_check = true;
+ }
+
+ td->pass = !failed_check;
+}
+
+struct tdescr tde = {
+ .name = "POR_EL0 missing poe_context",
+ .descr = "Remove poe_context record and check POR_EL0 is preserved",
+ .feats_required = FEAT_POE,
+ .timeout = 3,
+ .sig_trig = SIGUSR1,
+ .init = modify_por_el0,
+ .run = signal_remove_poe_context,
+ .check_result = check_por_el0_preserved,
+};
diff --git a/tools/testing/selftests/arm64/signal/testcases/poe_restore.c b/tools/testing/selftests/arm64/signal/testcases/poe_restore.c
new file mode 100644
index 000000000000..9f9a61a4214d
--- /dev/null
+++ b/tools/testing/selftests/arm64/signal/testcases/poe_restore.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2026 Arm Ltd
+ *
+ * Verify that the POR_EL0 register is saved and restored as expected on signal
+ * entry/return.
+ */
+
+#include <asm/sigcontext.h>
+
+#include "test_signals_utils.h"
+#include "testcases.h"
+
+#define POR_EL0_INIT 0x07ul
+#define POR_EL0_CUSTOM 0x77ul
+
+static bool failed_check;
+
+static bool modify_por_el0(struct tdescr *td)
+{
+ set_por_el0(POR_EL0_CUSTOM);
+
+ return true;
+}
+
+static int signal_check_por_el0_reset(struct tdescr *td, siginfo_t *si,
+ ucontext_t *uc)
+{
+ uint64_t signal_por_el0 = get_por_el0();
+
+ if (signal_por_el0 != POR_EL0_INIT) {
+ fprintf(stderr, "POR_EL0 is %lx in signal handler (expected %lx)\n",
+ signal_por_el0, POR_EL0_INIT);
+ failed_check = true;
+ }
+
+ return 0;
+}
+
+static void check_por_el0_restored(struct tdescr *td)
+{
+ uint64_t por_el0 = get_por_el0();
+
+ if (por_el0 == POR_EL0_CUSTOM) {
+ fprintf(stderr, "POR_EL0 restored\n");
+ } else {
+ fprintf(stderr, "POR_EL0 was %lx but is now %lx\n",
+ POR_EL0_CUSTOM, por_el0);
+ failed_check = true;
+ }
+
+ td->pass = !failed_check;
+}
+
+struct tdescr tde = {
+ .name = "POR_EL0 restore",
+ .descr = "Validate that POR_EL0 is saved/restored on signal entry/return",
+ .feats_required = FEAT_POE,
+ .timeout = 3,
+ .sig_trig = SIGUSR1,
+ .init = modify_por_el0,
+ .run = signal_check_por_el0_reset,
+ .check_result = check_por_el0_restored,
+};
--
2.51.2
^ permalink raw reply related
* Re: [PATCH v8 6/6] arm64: dts: rockchip: Add Orange Pi 5 Pro board support
From: Alexey Charkov @ 2026-04-27 12:19 UTC (permalink / raw)
To: Dennis Gilmore
Cc: Heiko Stuebner, Andrzej Hajda, Neil Armstrong, Robert Foss,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Laurent Pinchart,
Jonas Karlman, Jernej Skrabec, Maxime Ripard, devicetree,
linux-rockchip, linux-arm-kernel, dri-devel, linux-kernel
In-Reply-To: <20260425031011.2529364-7-dennis@ausil.us>
On Sat, Apr 25, 2026 at 7:10 AM Dennis Gilmore <dennis@ausil.us> wrote:
>
> Add device tree for the Xunlong Orange Pi 5 Pro (RK3588S).
>
> - eMMC module, you can optionally solder a SPI NOR in place and turn
> off the eMMC
> - PCIe-attached NIC (pcie2x1l2)
> - PCIe NVMe slot (pcie2x1l1)
> - AP6256 WiFi (BCM43456) via SDIO with mmc-pwrseq
> - BCM4345C5 Bluetooth
> - es8388 audio
> - USB 2.0 and USB 3.0
> - Two HDMI ports, the second is connected to the SoC's DP controller
> driven through a Lontium LT8711UXD bridge.
>
> Vendors schematics are available at:
> https://drive.google.com/file/d/1qs1DratHuh7C6J6MEtQIwUsiSrg8qgTi/view
>
> Signed-off-by: Dennis Gilmore <dennis@ausil.us>
> ---
> arch/arm64/boot/dts/rockchip/Makefile | 1 +
> .../dts/rockchip/rk3588s-orangepi-5-pro.dts | 440 ++++++++++++++++++
> 2 files changed, 441 insertions(+)
> create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5-pro.dts
Reviewed-by: Alexey Charkov <alchark@gmail.com>
Best regards,
Alexey
^ permalink raw reply
* [PATCH v6 0/4] firmware: ti_sci: Introduce BOARDCFG_MANAGED mode for Jacinto family
From: Thomas Richard (TI) @ 2026-04-27 12:21 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Santosh Shilimkar, Michael Turquette,
Stephen Boyd
Cc: Gregory CLEMENT, richard.genoud, Udit Kumar, Abhash Kumar,
Thomas Petazzoni, linux-arm-kernel, linux-kernel, linux-clk,
Thomas Richard (TI), Dhruva Gole, Kendall Willis
This is the 6th iteration of this series. The only changes are in sci-clk
driver. As suggested by Brian, during restore_context(), the set_parent()
operation is done only for clocks which have more than one parent. Also the
rate returned by recalc_rate() is saved. And I added Kendall's RB tag.
Best Regards,
Thomas
Signed-off-by: Thomas Richard (TI) <thomas.richard@bootlin.com>
---
Changes in v6:
- rebase on v7.1-rc1.
- add Kendall's RB tag.
- sci-clk: call set_parent() during restore_context() only for clocks which
have more than one parent.
- sci-clk: save also rate returned by recalc_rate().
- Link to v5: https://lore.kernel.org/r/20260407-ti-sci-jacinto-s2r-restore-irq-v5-0-97b28f2d93f9@bootlin.com
Changes in v5:
- rebase on v7.0-rc7.
- add Dhruva's RB tag.
- use kzalloc_obj() in ti_sci driver.
- Link to v4: https://lore.kernel.org/r/20260204-ti-sci-jacinto-s2r-restore-irq-v4-0-67820af39eac@bootlin.com
Changes in v4:
- rebase on linux-next next-20260202.
- fix BOARDCFG_MANAGED value.
- add MSG_FLAG_CAPS_LPM_IRQ_CONTEXT_LOST firmware capability.
- add MSG_FLAG_CAPS_LPM_CLK_CONTEXT_LOST firmware capability.
- Link to v3: https://lore.kernel.org/r/20251205-ti-sci-jacinto-s2r-restore-irq-v3-0-d06963974ad4@bootlin.com
Changes in v3:
- rebased on linux-next
- sci-clk: context_restore() operation restores also rate.
- Link to v2: https://lore.kernel.org/r/20251127-ti-sci-jacinto-s2r-restore-irq-v2-0-a487fa3ff221@bootlin.com
Changes in v2:
- ti_sci: use hlist to store IRQs.
- sci-clk: add context_restore operation
- ti_sci: restore clock parents during resume
- Link to v1: https://lore.kernel.org/r/20251017-ti-sci-jacinto-s2r-restore-irq-v1-0-34d4339d247a@bootlin.com
---
Thomas Richard (TI) (4):
firmware: ti_sci: add BOARDCFG_MANAGED mode support
firmware: ti_sci: add support for restoring IRQs during resume
clk: keystone: sci-clk: add restore_context() operation
firmware: ti_sci: add support for restoring clock context during resume
drivers/clk/keystone/sci-clk.c | 44 +++++++++--
drivers/firmware/ti_sci.c | 164 ++++++++++++++++++++++++++++++++++++++---
drivers/firmware/ti_sci.h | 6 ++
3 files changed, 194 insertions(+), 20 deletions(-)
---
base-commit: 0b8124777bdaeed16d8165f1e6f621d3df6e85a3
change-id: 20251010-ti-sci-jacinto-s2r-restore-irq-428e008fd10c
Best regards,
--
Thomas Richard (TI) <thomas.richard@bootlin.com>
^ permalink raw reply
* [PATCH v6 3/4] clk: keystone: sci-clk: add restore_context() operation
From: Thomas Richard (TI) @ 2026-04-27 12:21 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Santosh Shilimkar, Michael Turquette,
Stephen Boyd
Cc: Gregory CLEMENT, richard.genoud, Udit Kumar, Abhash Kumar,
Thomas Petazzoni, linux-arm-kernel, linux-kernel, linux-clk,
Thomas Richard (TI), Dhruva Gole, Kendall Willis
In-Reply-To: <20260427-ti-sci-jacinto-s2r-restore-irq-v6-0-72c6468cb2ab@bootlin.com>
Implement the restore_context() operation to restore the clock rate and the
clock parent state. The clock rate is saved in sci_clk struct during
set_rate() and recalc_rate() operations. The parent index is saved in
sci_clk struct during set_parent() operation. During clock registration,
the core retrieves each clock’s parent using get_parent() operation to
ensure the internal clock tree reflects the actual hardware state,
including any configurations made by the bootloader. So we also save the
parent index in get_parent().
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Kendall Willis <k-willis@ti.com>
Signed-off-by: Thomas Richard (TI) <thomas.richard@bootlin.com>
---
drivers/clk/keystone/sci-clk.c | 44 ++++++++++++++++++++++++++++++++++--------
1 file changed, 36 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/keystone/sci-clk.c b/drivers/clk/keystone/sci-clk.c
index 9d5071223f4c..b090edf5f82e 100644
--- a/drivers/clk/keystone/sci-clk.c
+++ b/drivers/clk/keystone/sci-clk.c
@@ -47,6 +47,8 @@ struct sci_clk_provider {
* @node: Link for handling clocks probed via DT
* @cached_req: Cached requested freq for determine rate calls
* @cached_res: Cached result freq for determine rate calls
+ * @parent_id: Parent index for this clock
+ * @rate: Clock rate
*/
struct sci_clk {
struct clk_hw hw;
@@ -58,6 +60,8 @@ struct sci_clk {
struct list_head node;
unsigned long cached_req;
unsigned long cached_res;
+ u8 parent_id;
+ unsigned long rate;
};
#define to_sci_clk(_hw) container_of(_hw, struct sci_clk, hw)
@@ -150,6 +154,8 @@ static unsigned long sci_clk_recalc_rate(struct clk_hw *hw,
return 0;
}
+ clk->rate = freq;
+
return freq;
}
@@ -210,10 +216,15 @@ static int sci_clk_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct sci_clk *clk = to_sci_clk(hw);
+ int ret;
- return clk->provider->ops->set_freq(clk->provider->sci, clk->dev_id,
- clk->clk_id, rate / 10 * 9, rate,
- rate / 10 * 11);
+ ret = clk->provider->ops->set_freq(clk->provider->sci, clk->dev_id,
+ clk->clk_id, rate / 10 * 9, rate,
+ rate / 10 * 11);
+ if (!ret)
+ clk->rate = rate;
+
+ return ret;
}
/**
@@ -237,9 +248,9 @@ static u8 sci_clk_get_parent(struct clk_hw *hw)
return 0;
}
- parent_id = parent_id - clk->clk_id - 1;
+ clk->parent_id = (u8)(parent_id - clk->clk_id - 1);
- return (u8)parent_id;
+ return clk->parent_id;
}
/**
@@ -252,12 +263,28 @@ static u8 sci_clk_get_parent(struct clk_hw *hw)
static int sci_clk_set_parent(struct clk_hw *hw, u8 index)
{
struct sci_clk *clk = to_sci_clk(hw);
+ int ret;
clk->cached_req = 0;
- return clk->provider->ops->set_parent(clk->provider->sci, clk->dev_id,
- clk->clk_id,
- index + 1 + clk->clk_id);
+ ret = clk->provider->ops->set_parent(clk->provider->sci, clk->dev_id,
+ clk->clk_id,
+ index + 1 + clk->clk_id);
+ if (!ret)
+ clk->parent_id = index;
+
+ return ret;
+}
+
+static void sci_clk_restore_context(struct clk_hw *hw)
+{
+ struct sci_clk *clk = to_sci_clk(hw);
+
+ if (clk->num_parents > 1)
+ sci_clk_set_parent(hw, clk->parent_id);
+
+ if (clk->rate)
+ sci_clk_set_rate(hw, clk->rate, 0);
}
static const struct clk_ops sci_clk_ops = {
@@ -269,6 +296,7 @@ static const struct clk_ops sci_clk_ops = {
.set_rate = sci_clk_set_rate,
.get_parent = sci_clk_get_parent,
.set_parent = sci_clk_set_parent,
+ .restore_context = sci_clk_restore_context,
};
/**
--
2.53.0
^ permalink raw reply related
* [PATCH v6 2/4] firmware: ti_sci: add support for restoring IRQs during resume
From: Thomas Richard (TI) @ 2026-04-27 12:21 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Santosh Shilimkar, Michael Turquette,
Stephen Boyd
Cc: Gregory CLEMENT, richard.genoud, Udit Kumar, Abhash Kumar,
Thomas Petazzoni, linux-arm-kernel, linux-kernel, linux-clk,
Thomas Richard (TI), Dhruva Gole, Kendall Willis
In-Reply-To: <20260427-ti-sci-jacinto-s2r-restore-irq-v6-0-72c6468cb2ab@bootlin.com>
Some DM-Firmware are not able to restore the IRQ context after a
suspend-resume. The IRQ_CONTEXT_LOST firmware capability has been
introduced to identify this characteristic. In this case the
responsibility is delegated to the ti_sci driver, which maintains an
internal list of all requested IRQs. This list is updated on each
set()/free() operation, and all IRQs are restored during the resume_noirq()
phase.
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Kendall Willis <k-willis@ti.com>
Signed-off-by: Thomas Richard (TI) <thomas.richard@bootlin.com>
---
drivers/firmware/ti_sci.c | 153 ++++++++++++++++++++++++++++++++++++++++++----
drivers/firmware/ti_sci.h | 2 +
2 files changed, 144 insertions(+), 11 deletions(-)
diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
index eaeaaae94142..b5c4324287b0 100644
--- a/drivers/firmware/ti_sci.c
+++ b/drivers/firmware/ti_sci.c
@@ -12,6 +12,7 @@
#include <linux/cpu.h>
#include <linux/debugfs.h>
#include <linux/export.h>
+#include <linux/hashtable.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
@@ -87,6 +88,16 @@ struct ti_sci_desc {
int max_msg_size;
};
+/**
+ * struct ti_sci_irq - Description of allocated irqs
+ * @node: Link to hash table
+ * @desc: Description of the irq
+ */
+struct ti_sci_irq {
+ struct hlist_node node;
+ struct ti_sci_msg_req_manage_irq desc;
+};
+
/**
* struct ti_sci_info - Structure representing a TI SCI instance
* @dev: Device pointer
@@ -101,6 +112,7 @@ struct ti_sci_desc {
* @chan_rx: Receive mailbox channel
* @minfo: Message info
* @node: list head
+ * @irqs: List of allocated irqs
* @host_id: Host ID
* @fw_caps: FW/SoC low power capabilities
* @users: Number of users of this instance
@@ -117,6 +129,7 @@ struct ti_sci_info {
struct mbox_chan *chan_tx;
struct mbox_chan *chan_rx;
struct ti_sci_xfers_info minfo;
+ DECLARE_HASHTABLE(irqs, 8);
struct list_head node;
u8 host_id;
u64 fw_caps;
@@ -2301,6 +2314,32 @@ static int ti_sci_manage_irq(const struct ti_sci_handle *handle,
return ret;
}
+/**
+ * ti_sci_irq_hash() - Helper API to compute irq hash for the hash table.
+ * @irq: irq to hash
+ *
+ * Return: the computed hash value.
+ */
+static int ti_sci_irq_hash(struct ti_sci_msg_req_manage_irq *irq)
+{
+ return irq->src_id ^ irq->src_index;
+}
+
+/**
+ * ti_sci_irq_equal() - Helper API to compare two irqs (generic headers are not
+ * compared)
+ * @irq_a: irq_a to compare
+ * @irq_b: irq_b to compare
+ *
+ * Return: true if the two irqs are equal, else false.
+ */
+static bool ti_sci_irq_equal(struct ti_sci_msg_req_manage_irq *irq_a,
+ struct ti_sci_msg_req_manage_irq *irq_b)
+{
+ return !memcmp(&irq_a->valid_params, &irq_b->valid_params,
+ sizeof(*irq_a) - sizeof(irq_a->hdr));
+}
+
/**
* ti_sci_set_irq() - Helper api to configure the irq route between the
* requested source and destination
@@ -2324,15 +2363,43 @@ static int ti_sci_set_irq(const struct ti_sci_handle *handle, u32 valid_params,
u16 dst_host_irq, u16 ia_id, u16 vint,
u16 global_event, u8 vint_status_bit, u8 s_host)
{
+ struct ti_sci_info *info = handle_to_ti_sci_info(handle);
+ struct ti_sci_msg_req_manage_irq *desc;
+ struct ti_sci_irq *irq;
+ int ret;
+
pr_debug("%s: IRQ set with valid_params = 0x%x from src = %d, index = %d, to dst = %d, irq = %d,via ia_id = %d, vint = %d, global event = %d,status_bit = %d\n",
__func__, valid_params, src_id, src_index,
dst_id, dst_host_irq, ia_id, vint, global_event,
vint_status_bit);
- return ti_sci_manage_irq(handle, valid_params, src_id, src_index,
- dst_id, dst_host_irq, ia_id, vint,
- global_event, vint_status_bit, s_host,
- TI_SCI_MSG_SET_IRQ);
+ ret = ti_sci_manage_irq(handle, valid_params, src_id, src_index,
+ dst_id, dst_host_irq, ia_id, vint,
+ global_event, vint_status_bit, s_host,
+ TI_SCI_MSG_SET_IRQ);
+
+ if (ret || !(info->fw_caps & MSG_FLAG_CAPS_LPM_IRQ_CONTEXT_LOST))
+ return ret;
+
+ irq = kzalloc_obj(*irq, GFP_KERNEL);
+ if (!irq)
+ return -ENOMEM;
+
+ desc = &irq->desc;
+ desc->valid_params = valid_params;
+ desc->src_id = src_id;
+ desc->src_index = src_index;
+ desc->dst_id = dst_id;
+ desc->dst_host_irq = dst_host_irq;
+ desc->ia_id = ia_id;
+ desc->vint = vint;
+ desc->global_event = global_event;
+ desc->vint_status_bit = vint_status_bit;
+ desc->secondary_host = s_host;
+
+ hash_add(info->irqs, &irq->node, ti_sci_irq_hash(desc));
+
+ return 0;
}
/**
@@ -2358,15 +2425,46 @@ static int ti_sci_free_irq(const struct ti_sci_handle *handle, u32 valid_params,
u16 dst_host_irq, u16 ia_id, u16 vint,
u16 global_event, u8 vint_status_bit, u8 s_host)
{
+ struct ti_sci_info *info = handle_to_ti_sci_info(handle);
+ struct ti_sci_msg_req_manage_irq irq_desc;
+ struct ti_sci_irq *this_irq;
+ struct hlist_node *tmp_node;
+ int ret;
+
pr_debug("%s: IRQ release with valid_params = 0x%x from src = %d, index = %d, to dst = %d, irq = %d,via ia_id = %d, vint = %d, global event = %d,status_bit = %d\n",
__func__, valid_params, src_id, src_index,
dst_id, dst_host_irq, ia_id, vint, global_event,
vint_status_bit);
- return ti_sci_manage_irq(handle, valid_params, src_id, src_index,
- dst_id, dst_host_irq, ia_id, vint,
- global_event, vint_status_bit, s_host,
- TI_SCI_MSG_FREE_IRQ);
+ ret = ti_sci_manage_irq(handle, valid_params, src_id, src_index,
+ dst_id, dst_host_irq, ia_id, vint,
+ global_event, vint_status_bit, s_host,
+ TI_SCI_MSG_FREE_IRQ);
+
+ if (ret || !(info->fw_caps & MSG_FLAG_CAPS_LPM_IRQ_CONTEXT_LOST))
+ return ret;
+
+ irq_desc.valid_params = valid_params;
+ irq_desc.src_id = src_id;
+ irq_desc.src_index = src_index;
+ irq_desc.dst_id = dst_id;
+ irq_desc.dst_host_irq = dst_host_irq;
+ irq_desc.ia_id = ia_id;
+ irq_desc.vint = vint;
+ irq_desc.global_event = global_event;
+ irq_desc.vint_status_bit = vint_status_bit;
+ irq_desc.secondary_host = s_host;
+
+ hash_for_each_possible_safe(info->irqs, this_irq, tmp_node, node,
+ ti_sci_irq_hash(&irq_desc)) {
+ if (ti_sci_irq_equal(&irq_desc, &this_irq->desc)) {
+ hlist_del(&this_irq->node);
+ kfree(this_irq);
+ return 0;
+ }
+ }
+
+ return 0;
}
/**
@@ -3847,7 +3945,10 @@ static int ti_sci_suspend_noirq(struct device *dev)
static int ti_sci_resume_noirq(struct device *dev)
{
struct ti_sci_info *info = dev_get_drvdata(dev);
- int ret = 0;
+ struct ti_sci_msg_req_manage_irq *irq_desc;
+ struct ti_sci_irq *irq;
+ struct hlist_node *tmp_node;
+ int ret = 0, i;
u32 source;
u64 time;
u8 pin;
@@ -3859,6 +3960,32 @@ static int ti_sci_resume_noirq(struct device *dev)
return ret;
}
+ switch (pm_suspend_target_state) {
+ case PM_SUSPEND_MEM:
+ if (info->fw_caps & MSG_FLAG_CAPS_LPM_IRQ_CONTEXT_LOST) {
+ hash_for_each_safe(info->irqs, i, tmp_node, irq, node) {
+ irq_desc = &irq->desc;
+ ret = ti_sci_manage_irq(&info->handle,
+ irq_desc->valid_params,
+ irq_desc->src_id,
+ irq_desc->src_index,
+ irq_desc->dst_id,
+ irq_desc->dst_host_irq,
+ irq_desc->ia_id,
+ irq_desc->vint,
+ irq_desc->global_event,
+ irq_desc->vint_status_bit,
+ irq_desc->secondary_host,
+ TI_SCI_MSG_SET_IRQ);
+ if (ret)
+ return ret;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+
ret = ti_sci_msg_cmd_lpm_wake_reason(&info->handle, &source, &time, &pin, &mode);
/* Do not fail to resume on error as the wake reason is not critical */
if (!ret)
@@ -4014,13 +4141,14 @@ static int ti_sci_probe(struct platform_device *pdev)
}
ti_sci_msg_cmd_query_fw_caps(&info->handle, &info->fw_caps);
- dev_dbg(dev, "Detected firmware capabilities: %s%s%s%s%s%s\n",
+ dev_dbg(dev, "Detected firmware capabilities: %s%s%s%s%s%s%s\n",
info->fw_caps & MSG_FLAG_CAPS_GENERIC ? "Generic" : "",
info->fw_caps & MSG_FLAG_CAPS_LPM_PARTIAL_IO ? " Partial-IO" : "",
info->fw_caps & MSG_FLAG_CAPS_LPM_DM_MANAGED ? " DM-Managed" : "",
info->fw_caps & MSG_FLAG_CAPS_LPM_ABORT ? " LPM-Abort" : "",
info->fw_caps & MSG_FLAG_CAPS_IO_ISOLATION ? " IO-Isolation" : "",
- info->fw_caps & MSG_FLAG_CAPS_LPM_BOARDCFG_MANAGED ? " BoardConfig-Managed" : ""
+ info->fw_caps & MSG_FLAG_CAPS_LPM_BOARDCFG_MANAGED ? " BoardConfig-Managed" : "",
+ info->fw_caps & MSG_FLAG_CAPS_LPM_IRQ_CONTEXT_LOST ? " IRQ-Context-Lost" : ""
);
ti_sci_setup_ops(info);
@@ -4053,6 +4181,9 @@ static int ti_sci_probe(struct platform_device *pdev)
list_add_tail(&info->node, &ti_sci_list);
mutex_unlock(&ti_sci_list_mutex);
+ if (info->fw_caps & MSG_FLAG_CAPS_LPM_IRQ_CONTEXT_LOST)
+ hash_init(info->irqs);
+
ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
if (ret) {
dev_err(dev, "platform_populate failed %pe\n", ERR_PTR(ret));
diff --git a/drivers/firmware/ti_sci.h b/drivers/firmware/ti_sci.h
index d90de59e29eb..67f16e8c69a1 100644
--- a/drivers/firmware/ti_sci.h
+++ b/drivers/firmware/ti_sci.h
@@ -151,6 +151,7 @@ struct ti_sci_msg_req_reboot {
* MSG_FLAG_CAPS_LPM_ABORT: Abort entry to LPM
* MSG_FLAG_CAPS_IO_ISOLATION: IO Isolation support
* MSG_FLAG_CAPS_LPM_BOARDCFG_MANAGED: LPM config done statically for the DM via boardcfg
+ * MSG_FLAG_CAPS_LPM_IRQ_CONTEXT_LOST: DM is not able to restore IRQ context
*
* Response to a generic message with message type TI_SCI_MSG_QUERY_FW_CAPS
* providing currently available SOC/firmware capabilities. SoC that don't
@@ -164,6 +165,7 @@ struct ti_sci_msg_resp_query_fw_caps {
#define MSG_FLAG_CAPS_LPM_ABORT TI_SCI_MSG_FLAG(9)
#define MSG_FLAG_CAPS_IO_ISOLATION TI_SCI_MSG_FLAG(7)
#define MSG_FLAG_CAPS_LPM_BOARDCFG_MANAGED TI_SCI_MSG_FLAG(12)
+#define MSG_FLAG_CAPS_LPM_IRQ_CONTEXT_LOST TI_SCI_MSG_FLAG(14)
#define MSG_MASK_CAPS_LPM GENMASK_ULL(4, 1)
u64 fw_caps;
} __packed;
--
2.53.0
^ permalink raw reply related
* [PATCH v6 4/4] firmware: ti_sci: add support for restoring clock context during resume
From: Thomas Richard (TI) @ 2026-04-27 12:21 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Santosh Shilimkar, Michael Turquette,
Stephen Boyd
Cc: Gregory CLEMENT, richard.genoud, Udit Kumar, Abhash Kumar,
Thomas Petazzoni, linux-arm-kernel, linux-kernel, linux-clk,
Thomas Richard (TI), Dhruva Gole, Kendall Willis
In-Reply-To: <20260427-ti-sci-jacinto-s2r-restore-irq-v6-0-72c6468cb2ab@bootlin.com>
Some DM-Firmware are not able to restore the clock rates and the clock
parents after a suspend-resume. The CLK_CONTEXT_LOST firmware capability
has been introduced to identify this characteristic. In this case the
responsibility is therefore delegated to the ti_sci driver, which uses
clk_restore_context() to trigger the context_restore() operation for all
registered clocks, including those managed by the sci-clk. The sci-clk
driver implements the context_restore() operation to ensure rates and clock
parents are correctly restored.
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Kendall Willis <k-willis@ti.com>
Signed-off-by: Thomas Richard (TI) <thomas.richard@bootlin.com>
---
drivers/firmware/ti_sci.c | 9 +++++++--
drivers/firmware/ti_sci.h | 2 ++
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
index b5c4324287b0..0148bafd71a0 100644
--- a/drivers/firmware/ti_sci.c
+++ b/drivers/firmware/ti_sci.c
@@ -9,6 +9,7 @@
#define pr_fmt(fmt) "%s: " fmt, __func__
#include <linux/bitmap.h>
+#include <linux/clk.h>
#include <linux/cpu.h>
#include <linux/debugfs.h>
#include <linux/export.h>
@@ -3981,6 +3982,9 @@ static int ti_sci_resume_noirq(struct device *dev)
return ret;
}
}
+
+ if (info->fw_caps & MSG_FLAG_CAPS_LPM_CLK_CONTEXT_LOST)
+ clk_restore_context();
break;
default:
break;
@@ -4141,14 +4145,15 @@ static int ti_sci_probe(struct platform_device *pdev)
}
ti_sci_msg_cmd_query_fw_caps(&info->handle, &info->fw_caps);
- dev_dbg(dev, "Detected firmware capabilities: %s%s%s%s%s%s%s\n",
+ dev_dbg(dev, "Detected firmware capabilities: %s%s%s%s%s%s%s%s\n",
info->fw_caps & MSG_FLAG_CAPS_GENERIC ? "Generic" : "",
info->fw_caps & MSG_FLAG_CAPS_LPM_PARTIAL_IO ? " Partial-IO" : "",
info->fw_caps & MSG_FLAG_CAPS_LPM_DM_MANAGED ? " DM-Managed" : "",
info->fw_caps & MSG_FLAG_CAPS_LPM_ABORT ? " LPM-Abort" : "",
info->fw_caps & MSG_FLAG_CAPS_IO_ISOLATION ? " IO-Isolation" : "",
info->fw_caps & MSG_FLAG_CAPS_LPM_BOARDCFG_MANAGED ? " BoardConfig-Managed" : "",
- info->fw_caps & MSG_FLAG_CAPS_LPM_IRQ_CONTEXT_LOST ? " IRQ-Context-Lost" : ""
+ info->fw_caps & MSG_FLAG_CAPS_LPM_IRQ_CONTEXT_LOST ? " IRQ-Context-Lost" : "",
+ info->fw_caps & MSG_FLAG_CAPS_LPM_CLK_CONTEXT_LOST ? " Clk-Context-Lost" : ""
);
ti_sci_setup_ops(info);
diff --git a/drivers/firmware/ti_sci.h b/drivers/firmware/ti_sci.h
index 67f16e8c69a1..2d75667a6723 100644
--- a/drivers/firmware/ti_sci.h
+++ b/drivers/firmware/ti_sci.h
@@ -152,6 +152,7 @@ struct ti_sci_msg_req_reboot {
* MSG_FLAG_CAPS_IO_ISOLATION: IO Isolation support
* MSG_FLAG_CAPS_LPM_BOARDCFG_MANAGED: LPM config done statically for the DM via boardcfg
* MSG_FLAG_CAPS_LPM_IRQ_CONTEXT_LOST: DM is not able to restore IRQ context
+ * MSG_FLAG_CAPS_LPM_CLK_CONTEXT_LOST: DM is not able to restore Clock context
*
* Response to a generic message with message type TI_SCI_MSG_QUERY_FW_CAPS
* providing currently available SOC/firmware capabilities. SoC that don't
@@ -166,6 +167,7 @@ struct ti_sci_msg_resp_query_fw_caps {
#define MSG_FLAG_CAPS_IO_ISOLATION TI_SCI_MSG_FLAG(7)
#define MSG_FLAG_CAPS_LPM_BOARDCFG_MANAGED TI_SCI_MSG_FLAG(12)
#define MSG_FLAG_CAPS_LPM_IRQ_CONTEXT_LOST TI_SCI_MSG_FLAG(14)
+#define MSG_FLAG_CAPS_LPM_CLK_CONTEXT_LOST TI_SCI_MSG_FLAG(15)
#define MSG_MASK_CAPS_LPM GENMASK_ULL(4, 1)
u64 fw_caps;
} __packed;
--
2.53.0
^ permalink raw reply related
* [PATCH v6 1/4] firmware: ti_sci: add BOARDCFG_MANAGED mode support
From: Thomas Richard (TI) @ 2026-04-27 12:21 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Santosh Shilimkar, Michael Turquette,
Stephen Boyd
Cc: Gregory CLEMENT, richard.genoud, Udit Kumar, Abhash Kumar,
Thomas Petazzoni, linux-arm-kernel, linux-kernel, linux-clk,
Thomas Richard (TI), Dhruva Gole, Kendall Willis
In-Reply-To: <20260427-ti-sci-jacinto-s2r-restore-irq-v6-0-72c6468cb2ab@bootlin.com>
In BOARDCFG_MANAGED mode, the low power mode configuration is done
statically for the DM via the boardcfg. Constraints are not supported, and
prepare_sleep() is not needed.
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Kendall Willis <k-willis@ti.com>
Signed-off-by: Thomas Richard (TI) <thomas.richard@bootlin.com>
---
drivers/firmware/ti_sci.c | 10 +++++++---
drivers/firmware/ti_sci.h | 2 ++
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
index dd9911b1cc11..eaeaaae94142 100644
--- a/drivers/firmware/ti_sci.c
+++ b/drivers/firmware/ti_sci.c
@@ -3772,8 +3772,11 @@ static int ti_sci_prepare_system_suspend(struct ti_sci_info *info)
return ti_sci_cmd_prepare_sleep(&info->handle,
TISCI_MSG_VALUE_SLEEP_MODE_DM_MANAGED,
0, 0, 0);
+ } else if (info->fw_caps & MSG_FLAG_CAPS_LPM_BOARDCFG_MANAGED) {
+ /* Nothing to do in the BOARDCFG_MANAGED mode */
+ return 0;
} else {
- /* DM Managed is not supported by the firmware. */
+ /* DM Managed and BoardCfg Managed are not supported by the firmware. */
dev_err(info->dev, "Suspend to memory is not supported by the firmware\n");
return -EOPNOTSUPP;
}
@@ -4011,12 +4014,13 @@ static int ti_sci_probe(struct platform_device *pdev)
}
ti_sci_msg_cmd_query_fw_caps(&info->handle, &info->fw_caps);
- dev_dbg(dev, "Detected firmware capabilities: %s%s%s%s%s\n",
+ dev_dbg(dev, "Detected firmware capabilities: %s%s%s%s%s%s\n",
info->fw_caps & MSG_FLAG_CAPS_GENERIC ? "Generic" : "",
info->fw_caps & MSG_FLAG_CAPS_LPM_PARTIAL_IO ? " Partial-IO" : "",
info->fw_caps & MSG_FLAG_CAPS_LPM_DM_MANAGED ? " DM-Managed" : "",
info->fw_caps & MSG_FLAG_CAPS_LPM_ABORT ? " LPM-Abort" : "",
- info->fw_caps & MSG_FLAG_CAPS_IO_ISOLATION ? " IO-Isolation" : ""
+ info->fw_caps & MSG_FLAG_CAPS_IO_ISOLATION ? " IO-Isolation" : "",
+ info->fw_caps & MSG_FLAG_CAPS_LPM_BOARDCFG_MANAGED ? " BoardConfig-Managed" : ""
);
ti_sci_setup_ops(info);
diff --git a/drivers/firmware/ti_sci.h b/drivers/firmware/ti_sci.h
index 4616127e33ff..d90de59e29eb 100644
--- a/drivers/firmware/ti_sci.h
+++ b/drivers/firmware/ti_sci.h
@@ -150,6 +150,7 @@ struct ti_sci_msg_req_reboot {
* MSG_FLAG_CAPS_LPM_DM_MANAGED: LPM can be managed by DM
* MSG_FLAG_CAPS_LPM_ABORT: Abort entry to LPM
* MSG_FLAG_CAPS_IO_ISOLATION: IO Isolation support
+ * MSG_FLAG_CAPS_LPM_BOARDCFG_MANAGED: LPM config done statically for the DM via boardcfg
*
* Response to a generic message with message type TI_SCI_MSG_QUERY_FW_CAPS
* providing currently available SOC/firmware capabilities. SoC that don't
@@ -162,6 +163,7 @@ struct ti_sci_msg_resp_query_fw_caps {
#define MSG_FLAG_CAPS_LPM_DM_MANAGED TI_SCI_MSG_FLAG(5)
#define MSG_FLAG_CAPS_LPM_ABORT TI_SCI_MSG_FLAG(9)
#define MSG_FLAG_CAPS_IO_ISOLATION TI_SCI_MSG_FLAG(7)
+#define MSG_FLAG_CAPS_LPM_BOARDCFG_MANAGED TI_SCI_MSG_FLAG(12)
#define MSG_MASK_CAPS_LPM GENMASK_ULL(4, 1)
u64 fw_caps;
} __packed;
--
2.53.0
^ permalink raw reply related
* Re: [PATCH] ARM: dts: rockchip: Remove invalid properies from rk3288-veyron-analog-audio
From: Heiko Stuebner @ 2026-04-27 12:23 UTC (permalink / raw)
To: Fabio Estevam
Cc: Heiko Stuebner, robh, krzk+dt, conor+dt, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel, Fabio Estevam
In-Reply-To: <20260404195008.1951910-1-festevam@gmail.com>
On Sat, 04 Apr 2026 16:50:08 -0300, Fabio Estevam wrote:
> The 'rockchip,mic-det-gpios' property is not documented anywhere.
>
> The 'rockchip,hp-det-gpios' property is not a valid property for the
> 'rockchip,rockchip-audio-max98090' compatible.
>
> Remove both invalid properties.
>
> [...]
Applied, thanks!
[1/1] ARM: dts: rockchip: Remove invalid properies from rk3288-veyron-analog-audio
commit: 44a024778eeba377d7ac882d15e27ba784e0f647
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
^ permalink raw reply
* Re: [PATCH] MAINTAINERS: Add Rockchip keyword matching
From: Heiko Stuebner @ 2026-04-27 12:23 UTC (permalink / raw)
To: Sebastian Reichel
Cc: Heiko Stuebner, linux-kernel, linux-arm-kernel, linux-rockchip
In-Reply-To: <20260327-maintainers-rockchip-keyword-v1-1-7f4634f761a6@collabora.com>
On Fri, 27 Mar 2026 15:21:06 +0100, Sebastian Reichel wrote:
> Add keyword based matching for 'ARM/Rockchip SoC support'. This will
> match rockchip, Rockchip, RockChip and ROCKCHIP separated by any
> whitespace character or underscores.
>
> The goal is to match arm64 defconfig patches, which should go through
> the Rockchip tree as they right now only match the LKML and thus are
> easily lost. The keyword matching is quite good for this, since it
> also applies to the commit message and the config options itself might
> not give any hint about being relevant for Rockchip.
>
> [...]
Applied, thanks!
[1/1] MAINTAINERS: Add Rockchip keyword matching
commit: 803d2de23a9703705c1ed73b0c9f57e8db2c9c75
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
^ permalink raw reply
* Re: [PATCH v2 0/2] arm64: dts: rockchip: fix Ethernet PHY on Theobroma PX30 devices
From: Heiko Stuebner @ 2026-04-27 12:23 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Quentin Schulz
Cc: Heiko Stuebner, Andrew Lunn, Heiko Stuebner, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel, Quentin Schulz,
stable
In-Reply-To: <20260421-px30-eth-phy-v2-0-68c375b120fd@cherry.de>
On Tue, 21 Apr 2026 11:45:04 +0200, Quentin Schulz wrote:
> This removes the reliance on the bootloader setting up the Ethernet PHY
> for the Linux kernel to be able to use Ethernet.
>
> This is due to the HW default of the PHY reset line being active and the
> MDIO auto-detection mechanism not controlling a PHY's reset line such
> that we need to hardcode the PHY ID in the compatible property for it to
> be usable by the kernel, regardless of what the bootloader is doing.
>
> [...]
Applied, thanks!
[1/2] arm64: dts: rockchip: fix Ethernet PHY not found on PX30 Cobra
commit: 6598ed3586a4b1cc79423666e66b9861631a6c7e
[2/2] arm64: dts: rockchip: fix Ethernet PHY not found on PX30 Ringneck
commit: ae653cb854f36d1555681ce70ca3d80d0ec73516
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
^ permalink raw reply
* Re: [PATCH v6] arm64: dts: rockchip: rock-3b: Model PI6C20100 as gated-fixed-clock
From: Heiko Stuebner @ 2026-04-27 12:23 UTC (permalink / raw)
To: MidG971
Cc: Heiko Stuebner, linux-rockchip, linux-arm-kernel, devicetree,
shawn.lin, jonas
In-Reply-To: <20260327091128.2458-1-midgy971@gmail.com>
On Fri, 27 Mar 2026 10:11:28 +0100, MidG971 wrote:
> The Radxa ROCK 3B uses a PI6C20100 PCIe reference clock buffer to
> provide a 100MHz reference clock to the PCIe 3.0 PHY and controllers.
> This chip is currently modeled only as a fixed regulator
> (vcc3v3_pi6c_03), with no clock output representation.
>
> The PI6C20100 is a clock generator, not a power supply. Model it
> properly as a gated-fixed-clock, following the pattern established
> for the Rock 5 ITX and other boards with similar PCIe clock buffer
> chips.
>
> [...]
Applied, thanks!
[1/1] arm64: dts: rockchip: rock-3b: Model PI6C20100 as gated-fixed-clock
commit: 8df9160f6a50dbdae8ec287d429efc9d2d9001bd
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
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