* [PATCH v3 11/11] mtd: spinand: winbond: Add support for continuous reads on W25NxxJW
From: Miquel Raynal @ 2026-04-29 17:56 UTC (permalink / raw)
To: Mark Brown, Richard Weinberger, Vignesh Raghavendra,
Michael Walle, Miquel Raynal, Takahiro Kuwano, Lorenzo Bianconi,
Ray Liu, Chin-Ting Kuo, Cédric Le Goater, Joel Stanley,
Andrew Jeffery, Avi Fishman, Tomer Maimon, Tali Perry,
Patrick Venture, Nancy Yuen, Benjamin Fair, Maxime Coquelin,
Alexandre Torgue, Jonathan Neuschäfer
Cc: Pratyush Yadav, Thomas Petazzoni, Steam Lin, Santhosh Kumar K,
linux-spi, linux-kernel, linux-mtd, linux-arm-kernel,
linux-aspeed, openbmc, linux-stm32
In-Reply-To: <20260429-winbond-v6-18-rc1-cont-read-v3-0-0f38b3c229ad@bootlin.com>
As for the W35NxxJW family, add support for W25N{01,02}JW continuous
read support. Similar operations require to be done, such as setting a
specific bit in a configuration register, and providing a set of read
variants without the address cycles.
As read from cache variants are badly supported by SPI memory
controllers, we create a new set of read from cache templates with a
fake address cycle and just enough dummy cycles. There are two
unsupported configurations (which would require 4.5 dummy bytes), so we
just do not provide them.
The same extra value in the ECC is possible as with the W35NxxJW family,
so we reference the same helper to retrieve the ECC status.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
All variants have been validated on a Nuvoton MA35D1 platform.
---
drivers/mtd/nand/spi/winbond.c | 108 +++++++++++++++++++++++++++++++++++++----
1 file changed, 98 insertions(+), 10 deletions(-)
diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c
index ffbcd25b0366..578f702528ee 100644
--- a/drivers/mtd/nand/spi/winbond.c
+++ b/drivers/mtd/nand/spi/winbond.c
@@ -46,6 +46,62 @@
SPI_MEM_OP_DATA_IN(len, buf, 1), \
SPI_MEM_OP_MAX_FREQ(freq))
+#define WINBOND_CONT_READ_FROM_CACHE_1S_1D_1D_OP(ndummy, buf, len, freq) \
+ SPI_MEM_OP(SPI_MEM_OP_CMD(0x0d, 1), \
+ SPI_MEM_DTR_OP_ADDR(2, 0, 1), \
+ SPI_MEM_DTR_OP_DUMMY(ndummy, 1), \
+ SPI_MEM_DTR_OP_DATA_IN(len, buf, 1), \
+ SPI_MEM_OP_MAX_FREQ(freq))
+
+#define WINBOND_CONT_READ_FROM_CACHE_1S_1S_2S_OP(ndummy, buf, len, freq) \
+ SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \
+ SPI_MEM_OP_ADDR(1, 0, 1), \
+ SPI_MEM_OP_DUMMY(ndummy - 1, 1), \
+ SPI_MEM_OP_DATA_IN(len, buf, 2), \
+ SPI_MEM_OP_MAX_FREQ(freq))
+
+#define WINBOND_CONT_READ_FROM_CACHE_1S_2S_2S_OP(ndummy, buf, len, freq) \
+ SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), \
+ SPI_MEM_OP_ADDR(1, 0, 2), \
+ SPI_MEM_OP_DUMMY(ndummy - 1, 2), \
+ SPI_MEM_OP_DATA_IN(len, buf, 2), \
+ SPI_MEM_OP_MAX_FREQ(freq))
+
+#define WINBOND_CONT_READ_FROM_CACHE_1S_2D_2D_OP(ndummy, buf, len, freq) \
+ SPI_MEM_OP(SPI_MEM_OP_CMD(0xbd, 1), \
+ SPI_MEM_DTR_OP_ADDR(1, 0, 2), \
+ SPI_MEM_DTR_OP_DUMMY(ndummy - 1, 2), \
+ SPI_MEM_DTR_OP_DATA_IN(len, buf, 2), \
+ SPI_MEM_OP_MAX_FREQ(freq))
+
+#define WINBOND_CONT_READ_FROM_CACHE_1S_1S_4S_OP(ndummy, buf, len, freq) \
+ SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \
+ SPI_MEM_OP_ADDR(1, 0, 1), \
+ SPI_MEM_OP_DUMMY(ndummy - 1, 1), \
+ SPI_MEM_OP_DATA_IN(len, buf, 4), \
+ SPI_MEM_OP_MAX_FREQ(freq))
+
+#define WINBOND_CONT_READ_FROM_CACHE_1S_1D_4D_OP(ndummy, buf, len, freq) \
+ SPI_MEM_OP(SPI_MEM_OP_CMD(0x6d, 1), \
+ SPI_MEM_DTR_OP_ADDR(1, 0, 1), \
+ SPI_MEM_DTR_OP_DUMMY(ndummy - 1, 1), \
+ SPI_MEM_DTR_OP_DATA_IN(len, buf, 4), \
+ SPI_MEM_OP_MAX_FREQ(freq))
+
+#define WINBOND_CONT_READ_FROM_CACHE_1S_4S_4S_OP(ndummy, buf, len, freq) \
+ SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1), \
+ SPI_MEM_OP_ADDR(1, 0, 4), \
+ SPI_MEM_OP_DUMMY(ndummy - 1, 4), \
+ SPI_MEM_OP_DATA_IN(len, buf, 4), \
+ SPI_MEM_OP_MAX_FREQ(freq))
+
+#define WINBOND_CONT_READ_FROM_CACHE_1S_4D_4D_OP(ndummy, buf, len, freq) \
+ SPI_MEM_OP(SPI_MEM_OP_CMD(0xed, 1), \
+ SPI_MEM_DTR_OP_ADDR(1, 0, 4), \
+ SPI_MEM_DTR_OP_DUMMY(ndummy - 1, 4), \
+ SPI_MEM_DTR_OP_DATA_IN(len, buf, 4), \
+ SPI_MEM_OP_MAX_FREQ(freq))
+
#define WINBOND_CONT_READ_FROM_CACHE_1S_1S_8S_OP(ndummy, buf, len, freq) \
SPI_MEM_OP(SPI_MEM_OP_CMD(0x8b, 1), \
SPI_MEM_OP_ADDR(1, 0, 1), \
@@ -133,6 +189,20 @@ static SPINAND_OP_VARIANTS(read_cache_dual_quad_dtr_variants,
SPINAND_PAGE_READ_FROM_CACHE_FAST_1S_1S_1S_OP(0, 1, NULL, 0, 0),
SPINAND_PAGE_READ_FROM_CACHE_1S_1S_1S_OP(0, 1, NULL, 0, 54 * HZ_PER_MHZ));
+static SPINAND_OP_VARIANTS(cont_read_cache_dual_quad_dtr_variants,
+ WINBOND_CONT_READ_FROM_CACHE_1S_4D_4D_OP(11, NULL, 0, 80 * HZ_PER_MHZ),
+ WINBOND_CONT_READ_FROM_CACHE_1S_1D_4D_OP(5, NULL, 0, 80 * HZ_PER_MHZ),
+ WINBOND_CONT_READ_FROM_CACHE_1S_4S_4S_OP(7, NULL, 0, 0),
+ WINBOND_CONT_READ_FROM_CACHE_1S_4S_4S_OP(6, NULL, 0, 104 * HZ_PER_MHZ),
+ WINBOND_CONT_READ_FROM_CACHE_1S_1S_4S_OP(4, NULL, 0, 0),
+ WINBOND_CONT_READ_FROM_CACHE_1S_2D_2D_OP(6, NULL, 0, 80 * HZ_PER_MHZ),
+ /* The 1S_1D_2D variant would require 4.5 dummy bytes, this is not possible */
+ WINBOND_CONT_READ_FROM_CACHE_1S_2S_2S_OP(5, NULL, 0, 0),
+ WINBOND_CONT_READ_FROM_CACHE_1S_2S_2S_OP(4, NULL, 0, 104 * HZ_PER_MHZ),
+ WINBOND_CONT_READ_FROM_CACHE_1S_1S_2S_OP(4, NULL, 0, 0),
+ /* The 1S_1D_1D variant would require 4.5 dummy bytes, this is not possible */
+ WINBOND_CONT_READ_FROM_CACHE_FAST_1S_1S_1S_OP(4, NULL, 0, 0));
+
static SPINAND_OP_VARIANTS(read_cache_variants,
SPINAND_PAGE_READ_FROM_CACHE_1S_4S_4S_OP(0, 2, NULL, 0, 0),
SPINAND_PAGE_READ_FROM_CACHE_1S_1S_4S_OP(0, 1, NULL, 0, 0),
@@ -445,11 +515,25 @@ static int w25n0xjw_hs_cfg(struct spinand_device *spinand,
if (iface != SSDR)
return -EOPNOTSUPP;
+ /*
+ * At this stage, we do not yet know the continuous read template, nor
+ * if there is going to be one. Let's assume the continuous read
+ * template will be selected with the same heuristics as the buffered
+ * read variant, as there cannot be a HS configuration mismatch between
+ * them.
+ */
op = spinand->op_templates->read_cache;
return w25n0xjw_set_sr4_hs(spinand, w25n0xjw_op_needs_hs(op));
}
+static int w25n0xjw_set_cont_read(struct spinand_device *spinand, bool enable)
+{
+ u8 mask = enable ? 0 : WINBOND_CFG_BUF_READ;
+
+ return spinand_upd_cfg(spinand, WINBOND_CFG_BUF_READ, mask);
+}
+
static int w35n0xjw_write_vcr(struct spinand_device *spinand, u8 reg, u8 val)
{
struct spi_mem_op op = SPINAND_OP(spinand, winbond_write_vcr,
@@ -580,12 +664,14 @@ static const struct spinand_info winbond_spinand_table[] = {
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xbc, 0x21),
NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
NAND_ECCREQ(1, 512),
- SPINAND_INFO_OP_VARIANTS(&read_cache_dual_quad_dtr_variants,
- &write_cache_variants,
- &update_cache_variants),
+ SPINAND_INFO_OP_VARIANTS_WITH_CONT(&read_cache_dual_quad_dtr_variants,
+ &write_cache_variants,
+ &update_cache_variants,
+ &cont_read_cache_dual_quad_dtr_variants),
SPINAND_HAS_QE_BIT,
- SPINAND_ECCINFO(&w25n01jw_ooblayout, NULL),
- SPINAND_CONFIGURE_CHIP(w25n0xjw_hs_cfg)),
+ SPINAND_ECCINFO(&w25n01jw_ooblayout, w25w35nxxjw_ecc_get_status),
+ SPINAND_CONFIGURE_CHIP(w25n0xjw_hs_cfg),
+ SPINAND_CONT_READ(w25n0xjw_set_cont_read)),
SPINAND_INFO("W25N01KV", /* 3.3V */
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xae, 0x21),
NAND_MEMORG(1, 2048, 96, 64, 1024, 20, 1, 1, 1),
@@ -624,12 +710,14 @@ static const struct spinand_info winbond_spinand_table[] = {
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xbf, 0x22),
NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 2, 1),
NAND_ECCREQ(1, 512),
- SPINAND_INFO_OP_VARIANTS(&read_cache_dual_quad_dtr_variants,
- &write_cache_variants,
- &update_cache_variants),
+ SPINAND_INFO_OP_VARIANTS_WITH_CONT(&read_cache_dual_quad_dtr_variants,
+ &write_cache_variants,
+ &update_cache_variants,
+ &cont_read_cache_dual_quad_dtr_variants),
SPINAND_HAS_QE_BIT,
- SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL),
- SPINAND_CONFIGURE_CHIP(w25n0xjw_hs_cfg)),
+ SPINAND_ECCINFO(&w25m02gv_ooblayout, w25w35nxxjw_ecc_get_status),
+ SPINAND_CONFIGURE_CHIP(w25n0xjw_hs_cfg),
+ SPINAND_CONT_READ(w25n0xjw_set_cont_read)),
SPINAND_INFO("W25N02KV", /* 3.3V */
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x22),
NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
--
2.53.0
^ permalink raw reply related
* [PATCH v3 10/11] mtd: spinand: winbond: Create a helper to detect the need for the HS bit
From: Miquel Raynal @ 2026-04-29 17:56 UTC (permalink / raw)
To: Mark Brown, Richard Weinberger, Vignesh Raghavendra,
Michael Walle, Miquel Raynal, Takahiro Kuwano, Lorenzo Bianconi,
Ray Liu, Chin-Ting Kuo, Cédric Le Goater, Joel Stanley,
Andrew Jeffery, Avi Fishman, Tomer Maimon, Tali Perry,
Patrick Venture, Nancy Yuen, Benjamin Fair, Maxime Coquelin,
Alexandre Torgue, Jonathan Neuschäfer
Cc: Pratyush Yadav, Thomas Petazzoni, Steam Lin, Santhosh Kumar K,
linux-spi, linux-kernel, linux-mtd, linux-arm-kernel,
linux-aspeed, openbmc, linux-stm32
In-Reply-To: <20260429-winbond-v6-18-rc1-cont-read-v3-0-0f38b3c229ad@bootlin.com>
The logic is not complex but might be reused to cleanup a bit the
section by moving it to a dedicated helper.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/mtd/nand/spi/winbond.c | 31 +++++++++++++++++--------------
1 file changed, 17 insertions(+), 14 deletions(-)
diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c
index b30a343a6672..ffbcd25b0366 100644
--- a/drivers/mtd/nand/spi/winbond.c
+++ b/drivers/mtd/nand/spi/winbond.c
@@ -421,30 +421,33 @@ static int w25n0xjw_set_sr4_hs(struct spinand_device *spinand, bool enable)
return spinand_write_reg_op(spinand, W25N0XJW_SR4, sr4);
}
+/*
+ * SDR dual and quad I/O operations over 104MHz require the HS bit to
+ * enable a few more dummy cycles.
+ */
+static bool w25n0xjw_op_needs_hs(const struct spi_mem_op *op)
+{
+ if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr)
+ return false;
+ else if (op->cmd.buswidth != 1 || op->addr.buswidth == 1)
+ return false;
+ else if (op->max_freq && op->max_freq <= 104 * HZ_PER_MHZ)
+ return false;
+
+ return true;
+}
+
static int w25n0xjw_hs_cfg(struct spinand_device *spinand,
enum spinand_bus_interface iface)
{
const struct spi_mem_op *op;
- bool hs;
if (iface != SSDR)
return -EOPNOTSUPP;
- /*
- * SDR dual and quad I/O operations over 104MHz require the HS bit to
- * enable a few more dummy cycles.
- */
op = spinand->op_templates->read_cache;
- if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr)
- hs = false;
- else if (op->cmd.buswidth != 1 || op->addr.buswidth == 1)
- hs = false;
- else if (op->max_freq && op->max_freq <= 104 * HZ_PER_MHZ)
- hs = false;
- else
- hs = true;
- return w25n0xjw_set_sr4_hs(spinand, hs);
+ return w25n0xjw_set_sr4_hs(spinand, w25n0xjw_op_needs_hs(op));
}
static int w35n0xjw_write_vcr(struct spinand_device *spinand, u8 reg, u8 val)
--
2.53.0
^ permalink raw reply related
* [PATCH v3 09/11] mtd: spinand: winbond: Create a helper to write the HS bit
From: Miquel Raynal @ 2026-04-29 17:56 UTC (permalink / raw)
To: Mark Brown, Richard Weinberger, Vignesh Raghavendra,
Michael Walle, Miquel Raynal, Takahiro Kuwano, Lorenzo Bianconi,
Ray Liu, Chin-Ting Kuo, Cédric Le Goater, Joel Stanley,
Andrew Jeffery, Avi Fishman, Tomer Maimon, Tali Perry,
Patrick Venture, Nancy Yuen, Benjamin Fair, Maxime Coquelin,
Alexandre Torgue, Jonathan Neuschäfer
Cc: Pratyush Yadav, Thomas Petazzoni, Steam Lin, Santhosh Kumar K,
linux-spi, linux-kernel, linux-mtd, linux-arm-kernel,
linux-aspeed, openbmc, linux-stm32
In-Reply-To: <20260429-winbond-v6-18-rc1-cont-read-v3-0-0f38b3c229ad@bootlin.com>
Updating the HS bit is not complex but implies reading, setting/clearing
a bit and writing. Clean a bit this section by moving this logic in its
own helper.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/mtd/nand/spi/winbond.c | 34 ++++++++++++++++++----------------
1 file changed, 18 insertions(+), 16 deletions(-)
diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c
index 6c11f59a9f8d..b30a343a6672 100644
--- a/drivers/mtd/nand/spi/winbond.c
+++ b/drivers/mtd/nand/spi/winbond.c
@@ -404,13 +404,28 @@ static int w25w35nxxjw_ecc_get_status(struct spinand_device *spinand, u8 status)
return -EINVAL;
}
+static int w25n0xjw_set_sr4_hs(struct spinand_device *spinand, bool enable)
+{
+ int ret;
+ u8 sr4;
+
+ ret = spinand_read_reg_op(spinand, W25N0XJW_SR4, &sr4);
+ if (ret)
+ return ret;
+
+ if (enable)
+ sr4 |= W25N0XJW_SR4_HS;
+ else
+ sr4 &= ~W25N0XJW_SR4_HS;
+
+ return spinand_write_reg_op(spinand, W25N0XJW_SR4, sr4);
+}
+
static int w25n0xjw_hs_cfg(struct spinand_device *spinand,
enum spinand_bus_interface iface)
{
const struct spi_mem_op *op;
bool hs;
- u8 sr4;
- int ret;
if (iface != SSDR)
return -EOPNOTSUPP;
@@ -429,20 +444,7 @@ static int w25n0xjw_hs_cfg(struct spinand_device *spinand,
else
hs = true;
- ret = spinand_read_reg_op(spinand, W25N0XJW_SR4, &sr4);
- if (ret)
- return ret;
-
- if (hs)
- sr4 |= W25N0XJW_SR4_HS;
- else
- sr4 &= ~W25N0XJW_SR4_HS;
-
- ret = spinand_write_reg_op(spinand, W25N0XJW_SR4, sr4);
- if (ret)
- return ret;
-
- return 0;
+ return w25n0xjw_set_sr4_hs(spinand, hs);
}
static int w35n0xjw_write_vcr(struct spinand_device *spinand, u8 reg, u8 val)
--
2.53.0
^ permalink raw reply related
* [PATCH v3 07/11] mtd: spinand: winbond: Ensure chips are ordered by density
From: Miquel Raynal @ 2026-04-29 17:56 UTC (permalink / raw)
To: Mark Brown, Richard Weinberger, Vignesh Raghavendra,
Michael Walle, Miquel Raynal, Takahiro Kuwano, Lorenzo Bianconi,
Ray Liu, Chin-Ting Kuo, Cédric Le Goater, Joel Stanley,
Andrew Jeffery, Avi Fishman, Tomer Maimon, Tali Perry,
Patrick Venture, Nancy Yuen, Benjamin Fair, Maxime Coquelin,
Alexandre Torgue, Jonathan Neuschäfer
Cc: Pratyush Yadav, Thomas Petazzoni, Steam Lin, Santhosh Kumar K,
linux-spi, linux-kernel, linux-mtd, linux-arm-kernel,
linux-aspeed, openbmc, linux-stm32
In-Reply-To: <20260429-winbond-v6-18-rc1-cont-read-v3-0-0f38b3c229ad@bootlin.com>
All W35N0xJW chips have been added in a row, move the definition of the
2 and 4 Gb variants so their respective locations in the table.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/mtd/nand/spi/winbond.c | 44 +++++++++++++++++++++---------------------
1 file changed, 22 insertions(+), 22 deletions(-)
diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c
index ad22774096e6..f4d4ffaa1f62 100644
--- a/drivers/mtd/nand/spi/winbond.c
+++ b/drivers/mtd/nand/spi/winbond.c
@@ -511,28 +511,6 @@ static const struct spinand_info winbond_spinand_table[] = {
SPINAND_INFO_VENDOR_OPS(&winbond_w35_ops),
SPINAND_ECCINFO(&w35n01jw_ooblayout, NULL),
SPINAND_CONFIGURE_CHIP(w35n0xjw_vcr_cfg)),
- SPINAND_INFO("W35N02JW", /* 1.8V */
- SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xdf, 0x22),
- NAND_MEMORG(1, 4096, 128, 64, 512, 10, 1, 2, 1),
- NAND_ECCREQ(1, 512),
- SPINAND_INFO_OP_VARIANTS(&read_cache_octal_variants,
- &write_cache_octal_variants,
- &update_cache_octal_variants),
- 0,
- SPINAND_INFO_VENDOR_OPS(&winbond_w35_ops),
- SPINAND_ECCINFO(&w35n01jw_ooblayout, NULL),
- SPINAND_CONFIGURE_CHIP(w35n0xjw_vcr_cfg)),
- SPINAND_INFO("W35N04JW", /* 1.8V */
- SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xdf, 0x23),
- NAND_MEMORG(1, 4096, 128, 64, 512, 10, 1, 4, 1),
- NAND_ECCREQ(1, 512),
- SPINAND_INFO_OP_VARIANTS(&read_cache_octal_variants,
- &write_cache_octal_variants,
- &update_cache_octal_variants),
- 0,
- SPINAND_INFO_VENDOR_OPS(&winbond_w35_ops),
- SPINAND_ECCINFO(&w35n01jw_ooblayout, NULL),
- SPINAND_CONFIGURE_CHIP(w35n0xjw_vcr_cfg)),
/* 2G-bit densities */
SPINAND_INFO("W25M02GV", /* 2x1G-bit 3.3V */
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xab, 0x21),
@@ -573,6 +551,17 @@ static const struct spinand_info winbond_spinand_table[] = {
&update_cache_variants),
0,
SPINAND_ECCINFO(&w25n02kv_ooblayout, w25n02kv_ecc_get_status)),
+ SPINAND_INFO("W35N02JW", /* 1.8V */
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xdf, 0x22),
+ NAND_MEMORG(1, 4096, 128, 64, 512, 10, 1, 2, 1),
+ NAND_ECCREQ(1, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_octal_variants,
+ &write_cache_octal_variants,
+ &update_cache_octal_variants),
+ 0,
+ SPINAND_INFO_VENDOR_OPS(&winbond_w35_ops),
+ SPINAND_ECCINFO(&w35n01jw_ooblayout, NULL),
+ SPINAND_CONFIGURE_CHIP(w35n0xjw_vcr_cfg)),
/* 4G-bit densities */
SPINAND_INFO("W25N04KV", /* 3.3V */
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x23),
@@ -592,6 +581,17 @@ static const struct spinand_info winbond_spinand_table[] = {
&update_cache_variants),
0,
SPINAND_ECCINFO(&w25n02kv_ooblayout, w25n02kv_ecc_get_status)),
+ SPINAND_INFO("W35N04JW", /* 1.8V */
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xdf, 0x23),
+ NAND_MEMORG(1, 4096, 128, 64, 512, 10, 1, 4, 1),
+ NAND_ECCREQ(1, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_octal_variants,
+ &write_cache_octal_variants,
+ &update_cache_octal_variants),
+ 0,
+ SPINAND_INFO_VENDOR_OPS(&winbond_w35_ops),
+ SPINAND_ECCINFO(&w35n01jw_ooblayout, NULL),
+ SPINAND_CONFIGURE_CHIP(w35n0xjw_vcr_cfg)),
};
static int winbond_spinand_init(struct spinand_device *spinand)
--
2.53.0
^ permalink raw reply related
* [PATCH v3 08/11] mtd: spinand: winbond: Add support for continuous reads on W35NxxJW
From: Miquel Raynal @ 2026-04-29 17:56 UTC (permalink / raw)
To: Mark Brown, Richard Weinberger, Vignesh Raghavendra,
Michael Walle, Miquel Raynal, Takahiro Kuwano, Lorenzo Bianconi,
Ray Liu, Chin-Ting Kuo, Cédric Le Goater, Joel Stanley,
Andrew Jeffery, Avi Fishman, Tomer Maimon, Tali Perry,
Patrick Venture, Nancy Yuen, Benjamin Fair, Maxime Coquelin,
Alexandre Torgue, Jonathan Neuschäfer
Cc: Pratyush Yadav, Thomas Petazzoni, Steam Lin, Santhosh Kumar K,
linux-spi, linux-kernel, linux-mtd, linux-arm-kernel,
linux-aspeed, openbmc, linux-stm32
In-Reply-To: <20260429-winbond-v6-18-rc1-cont-read-v3-0-0f38b3c229ad@bootlin.com>
W35N{01,02,04}JW support being read continuously under certain
circumstances. A bit must be set in their configuration register, and
a specific read from cache operation, a bit shorter than usual because
it no longer requires the address cycles, must be used for the occasion.
Setting the "enable" bit is already supported by the core, aside from
the subtlety of making sure the HFREQ bit is also set in octal DTR mode
above 90MHz. However, handling two different read from cache templates
involves creating a list of read from cache variants adapted the
continuous reads, ie. without address cycles.
Unfortunately, these operations, despite being very close to their
original read from cache cousins, are often unsupported by smart SPI
controller drivers because reading from cache historically allowed
changing the offset at which the host would start by providing a 2-byte
column address. In order to prevent issues with this, it has been
decided to implement these variants with a single "ignored" address byte
(respectively two in the octal DTR case), further reducing the amount of
dummy cycles needed before the first bit of data.
Enabling continuous reads has a side effect: the ECC status register now
may also return the value b11, which means that more than 1
uncorrectable error happened during the read. This non standard
behaviour requires to re-implement, almost identically the "get ECC"
helper from the core, with just an extra case for this value (it is
prefixed "w25w35nxxjw" because all these chips have the same behaviour).
Speed gain is substantial, see below. The flash_speed -C benchmark has
been run on a TI AM62A7 LP SK with CPU power management disabled,
mounted with a W35N01JW chip.
1S-8S-8S:
1 page read speed is 15058 KiB/s
2 page read speed is 15058 KiB/s
3 page read speed is 16800 KiB/s
4 page read speed is 17066 KiB/s
5 page read speed is 18461 KiB/s
6 page read speed is 18461 KiB/s
7 page read speed is 19384 KiB/s
8 page read speed is 19692 KiB/s
9 page read speed is 19384 KiB/s
10 page read speed is 20000 KiB/s
11 page read speed is 20000 KiB/s
12 page read speed is 20000 KiB/s
13 page read speed is 20800 KiB/s
14 page read speed is 20363 KiB/s
15 page read speed is 20000 KiB/s
16 page read speed is 19692 KiB/s
32 page read speed is 19692 KiB/s
64 page read speed is 19692 KiB/s
8D-8D-8D:
1 page read speed is 23272 KiB/s
2 page read speed is 23272 KiB/s
3 page read speed is 28000 KiB/s
4 page read speed is 32000 KiB/s
5 page read speed is 34285 KiB/s
6 page read speed is 34285 KiB/s
7 page read speed is 36000 KiB/s
8 page read speed is 36571 KiB/s
9 page read speed is 36000 KiB/s
10 page read speed is 34285 KiB/s
11 page read speed is 36666 KiB/s
12 page read speed is 40000 KiB/s
13 page read speed is 41600 KiB/s
14 page read speed is 37333 KiB/s
15 page read speed is 40000 KiB/s
16 page read speed is 36571 KiB/s
32 page read speed is 42666 KiB/s
64 page read speed is 42666 KiB/s
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
Not all configurations have been tested/validated yet.
---
drivers/mtd/nand/spi/winbond.c | 126 ++++++++++++++++++++++++++++++++++++-----
1 file changed, 111 insertions(+), 15 deletions(-)
diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c
index f4d4ffaa1f62..6c11f59a9f8d 100644
--- a/drivers/mtd/nand/spi/winbond.c
+++ b/drivers/mtd/nand/spi/winbond.c
@@ -15,9 +15,11 @@
#define SPINAND_MFR_WINBOND 0xEF
+#define WINBOND_CFG_HFREQ BIT(0)
#define WINBOND_CFG_BUF_READ BIT(3)
#define W25N04KV_STATUS_ECC_5_8_BITFLIPS (3 << 4)
+#define W25W35NXXJW_STATUS_ECC_MULT_UNCOR (3 << 4)
#define W25N0XJW_SR4 0xD0
#define W25N0XJW_SR4_HS BIT(2)
@@ -29,6 +31,49 @@
#define W35N01JW_VCR_IO_MODE_OCTAL_DDR 0xC7
#define W35N01JW_VCR_DUMMY_CLOCK_REG 0x01
+/*
+ * Winbond chips ignore the address bytes during continuous reads, and
+ * because the dummy cycles are enough they indicate dropping the
+ * address cycles from the continuous read from cache variants. This is
+ * very poorly supported by SPI controller drivers which are "wired" to
+ * always at least provide the column. Keep using address cycles, but
+ * reduce the number of dummy cycles accordingly.
+ */
+#define WINBOND_CONT_READ_FROM_CACHE_FAST_1S_1S_1S_OP(ndummy, buf, len, freq) \
+ SPI_MEM_OP(SPI_MEM_OP_CMD(0x0b, 1), \
+ SPI_MEM_OP_ADDR(1, 0, 1), \
+ SPI_MEM_OP_DUMMY(ndummy - 1, 1), \
+ SPI_MEM_OP_DATA_IN(len, buf, 1), \
+ SPI_MEM_OP_MAX_FREQ(freq))
+
+#define WINBOND_CONT_READ_FROM_CACHE_1S_1S_8S_OP(ndummy, buf, len, freq) \
+ SPI_MEM_OP(SPI_MEM_OP_CMD(0x8b, 1), \
+ SPI_MEM_OP_ADDR(1, 0, 1), \
+ SPI_MEM_OP_DUMMY(ndummy - 1, 1), \
+ SPI_MEM_OP_DATA_IN(len, buf, 8), \
+ SPI_MEM_OP_MAX_FREQ(freq))
+
+#define WINBOND_CONT_READ_FROM_CACHE_1S_1D_8D_OP(ndummy, buf, len, freq) \
+ SPI_MEM_OP(SPI_MEM_OP_CMD(0x9d, 1), \
+ SPI_MEM_DTR_OP_ADDR(1, 0, 1), \
+ SPI_MEM_DTR_OP_DUMMY(ndummy - 1, 1), \
+ SPI_MEM_DTR_OP_DATA_IN(len, buf, 8), \
+ SPI_MEM_OP_MAX_FREQ(freq))
+
+#define WINBOND_CONT_READ_FROM_CACHE_1S_8S_8S_OP(ndummy, buf, len, freq) \
+ SPI_MEM_OP(SPI_MEM_OP_CMD(0xcb, 1), \
+ SPI_MEM_OP_ADDR(1, 0, 8), \
+ SPI_MEM_OP_DUMMY(ndummy - 1, 8), \
+ SPI_MEM_OP_DATA_IN(len, buf, 8), \
+ SPI_MEM_OP_MAX_FREQ(freq))
+
+#define WINBOND_CONT_READ_FROM_CACHE_8D_8D_8D_OP(ndummy, buf, len, freq) \
+ SPI_MEM_OP(SPI_MEM_DTR_OP_RPT_CMD(0x9d, 8), \
+ SPI_MEM_DTR_OP_ADDR(2, 0, 8), \
+ SPI_MEM_DTR_OP_DUMMY(ndummy - 2, 8), \
+ SPI_MEM_DTR_OP_DATA_IN(len, buf, 8), \
+ SPI_MEM_OP_MAX_FREQ(freq))
+
/*
* "X2" in the core is equivalent to "dual output" in the datasheets,
* "X4" in the core is equivalent to "quad output" in the datasheets.
@@ -49,6 +94,19 @@ static SPINAND_OP_VARIANTS(read_cache_octal_variants,
SPINAND_PAGE_READ_FROM_CACHE_FAST_1S_1S_1S_OP(0, 1, NULL, 0, 0),
SPINAND_PAGE_READ_FROM_CACHE_1S_1S_1S_OP(0, 1, NULL, 0, 0));
+static SPINAND_OP_VARIANTS(cont_read_cache_octal_variants,
+ WINBOND_CONT_READ_FROM_CACHE_8D_8D_8D_OP(24, NULL, 0, 120 * HZ_PER_MHZ),
+ WINBOND_CONT_READ_FROM_CACHE_8D_8D_8D_OP(16, NULL, 0, 86 * HZ_PER_MHZ),
+ WINBOND_CONT_READ_FROM_CACHE_1S_1D_8D_OP(3, NULL, 0, 120 * HZ_PER_MHZ),
+ WINBOND_CONT_READ_FROM_CACHE_1S_1D_8D_OP(2, NULL, 0, 105 * HZ_PER_MHZ),
+ WINBOND_CONT_READ_FROM_CACHE_1S_8S_8S_OP(20, NULL, 0, 0),
+ WINBOND_CONT_READ_FROM_CACHE_1S_8S_8S_OP(16, NULL, 0, 162 * HZ_PER_MHZ),
+ WINBOND_CONT_READ_FROM_CACHE_1S_8S_8S_OP(12, NULL, 0, 124 * HZ_PER_MHZ),
+ WINBOND_CONT_READ_FROM_CACHE_1S_8S_8S_OP(8, NULL, 0, 86 * HZ_PER_MHZ),
+ WINBOND_CONT_READ_FROM_CACHE_1S_1S_8S_OP(2, NULL, 0, 0),
+ WINBOND_CONT_READ_FROM_CACHE_1S_1S_8S_OP(1, NULL, 0, 133 * HZ_PER_MHZ),
+ WINBOND_CONT_READ_FROM_CACHE_FAST_1S_1S_1S_OP(1, NULL, 0, 0));
+
static SPINAND_OP_VARIANTS(write_cache_octal_variants,
SPINAND_PROG_LOAD_8D_8D_8D_OP(true, 0, NULL, 0),
SPINAND_PROG_LOAD_1S_8S_8S_OP(true, 0, NULL, 0),
@@ -326,6 +384,26 @@ static int w25n02kv_ecc_get_status(struct spinand_device *spinand,
return -EINVAL;
}
+static int w25w35nxxjw_ecc_get_status(struct spinand_device *spinand, u8 status)
+{
+ switch (status & STATUS_ECC_MASK) {
+ case STATUS_ECC_NO_BITFLIPS:
+ return 0;
+
+ case STATUS_ECC_HAS_BITFLIPS:
+ return 1;
+
+ case STATUS_ECC_UNCOR_ERROR:
+ case W25W35NXXJW_STATUS_ECC_MULT_UNCOR:
+ return -EBADMSG;
+
+ default:
+ break;
+ }
+
+ return -EINVAL;
+}
+
static int w25n0xjw_hs_cfg(struct spinand_device *spinand,
enum spinand_bus_interface iface)
{
@@ -451,6 +529,18 @@ static int w35n0xjw_vcr_cfg(struct spinand_device *spinand,
return 0;
}
+static int w35n0xjw_set_cont_read(struct spinand_device *spinand, bool enable)
+{
+ const struct spi_mem_op *cont_op = spinand->op_templates->cont_read_cache;
+ u8 mask = enable ? 0 : WINBOND_CFG_BUF_READ;
+
+ if (cont_op && enable && spinand_op_is_odtr(cont_op) &&
+ cont_op->max_freq >= 90 * HZ_PER_MHZ)
+ mask |= WINBOND_CFG_HFREQ;
+
+ return spinand_upd_cfg(spinand, WINBOND_CFG_BUF_READ | WINBOND_CFG_HFREQ, mask);
+}
+
static const struct spinand_info winbond_spinand_table[] = {
/* 512M-bit densities */
SPINAND_INFO("W25N512GW", /* 1.8V */
@@ -504,13 +594,15 @@ static const struct spinand_info winbond_spinand_table[] = {
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xdc, 0x21),
NAND_MEMORG(1, 4096, 128, 64, 512, 10, 1, 1, 1),
NAND_ECCREQ(1, 512),
- SPINAND_INFO_OP_VARIANTS(&read_cache_octal_variants,
- &write_cache_octal_variants,
- &update_cache_octal_variants),
+ SPINAND_INFO_OP_VARIANTS_WITH_CONT(&read_cache_octal_variants,
+ &write_cache_octal_variants,
+ &update_cache_octal_variants,
+ &cont_read_cache_octal_variants),
0,
SPINAND_INFO_VENDOR_OPS(&winbond_w35_ops),
- SPINAND_ECCINFO(&w35n01jw_ooblayout, NULL),
- SPINAND_CONFIGURE_CHIP(w35n0xjw_vcr_cfg)),
+ SPINAND_ECCINFO(&w35n01jw_ooblayout, w25w35nxxjw_ecc_get_status),
+ SPINAND_CONFIGURE_CHIP(w35n0xjw_vcr_cfg),
+ SPINAND_CONT_READ(w35n0xjw_set_cont_read)),
/* 2G-bit densities */
SPINAND_INFO("W25M02GV", /* 2x1G-bit 3.3V */
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xab, 0x21),
@@ -555,13 +647,15 @@ static const struct spinand_info winbond_spinand_table[] = {
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xdf, 0x22),
NAND_MEMORG(1, 4096, 128, 64, 512, 10, 1, 2, 1),
NAND_ECCREQ(1, 512),
- SPINAND_INFO_OP_VARIANTS(&read_cache_octal_variants,
- &write_cache_octal_variants,
- &update_cache_octal_variants),
+ SPINAND_INFO_OP_VARIANTS_WITH_CONT(&read_cache_octal_variants,
+ &write_cache_octal_variants,
+ &update_cache_octal_variants,
+ &cont_read_cache_octal_variants),
0,
SPINAND_INFO_VENDOR_OPS(&winbond_w35_ops),
- SPINAND_ECCINFO(&w35n01jw_ooblayout, NULL),
- SPINAND_CONFIGURE_CHIP(w35n0xjw_vcr_cfg)),
+ SPINAND_ECCINFO(&w35n01jw_ooblayout, w25w35nxxjw_ecc_get_status),
+ SPINAND_CONFIGURE_CHIP(w35n0xjw_vcr_cfg),
+ SPINAND_CONT_READ(w35n0xjw_set_cont_read)),
/* 4G-bit densities */
SPINAND_INFO("W25N04KV", /* 3.3V */
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x23),
@@ -585,13 +679,15 @@ static const struct spinand_info winbond_spinand_table[] = {
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xdf, 0x23),
NAND_MEMORG(1, 4096, 128, 64, 512, 10, 1, 4, 1),
NAND_ECCREQ(1, 512),
- SPINAND_INFO_OP_VARIANTS(&read_cache_octal_variants,
- &write_cache_octal_variants,
- &update_cache_octal_variants),
+ SPINAND_INFO_OP_VARIANTS_WITH_CONT(&read_cache_octal_variants,
+ &write_cache_octal_variants,
+ &update_cache_octal_variants,
+ &cont_read_cache_octal_variants),
0,
SPINAND_INFO_VENDOR_OPS(&winbond_w35_ops),
- SPINAND_ECCINFO(&w35n01jw_ooblayout, NULL),
- SPINAND_CONFIGURE_CHIP(w35n0xjw_vcr_cfg)),
+ SPINAND_ECCINFO(&w35n01jw_ooblayout, w25w35nxxjw_ecc_get_status),
+ SPINAND_CONFIGURE_CHIP(w35n0xjw_vcr_cfg),
+ SPINAND_CONT_READ(w35n0xjw_set_cont_read)),
};
static int winbond_spinand_init(struct spinand_device *spinand)
--
2.53.0
^ permalink raw reply related
* [PATCH v3 06/11] mtd: spinand: Use secondary ops for continuous reads
From: Miquel Raynal @ 2026-04-29 17:56 UTC (permalink / raw)
To: Mark Brown, Richard Weinberger, Vignesh Raghavendra,
Michael Walle, Miquel Raynal, Takahiro Kuwano, Lorenzo Bianconi,
Ray Liu, Chin-Ting Kuo, Cédric Le Goater, Joel Stanley,
Andrew Jeffery, Avi Fishman, Tomer Maimon, Tali Perry,
Patrick Venture, Nancy Yuen, Benjamin Fair, Maxime Coquelin,
Alexandre Torgue, Jonathan Neuschäfer
Cc: Pratyush Yadav, Thomas Petazzoni, Steam Lin, Santhosh Kumar K,
linux-spi, linux-kernel, linux-mtd, linux-arm-kernel,
linux-aspeed, openbmc, linux-stm32
In-Reply-To: <20260429-winbond-v6-18-rc1-cont-read-v3-0-0f38b3c229ad@bootlin.com>
In case a chip supports continuous reads, but uses a slightly different
cache operation for these, it may provide a secondary operation template
which will be used only during continuous cache read operations.
From a vendor driver point of view, enabling this feature implies
providing a new set of templates for these continuous read
operations. The core will automatically pick the fastest variant,
depending on the hardware capabilities.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/mtd/nand/spi/core.c | 61 ++++++++++++++++++++++++++++++++++++++++++++-
include/linux/mtd/spinand.h | 12 +++++++++
2 files changed, 72 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
index a66510747b31..45c3afb9cceb 100644
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -489,6 +489,11 @@ static int spinand_read_from_cache_op(struct spinand_device *spinand,
rdesc = spinand->dirmaps[req->pos.plane].rdesc;
+ if (spinand->op_templates->cont_read_cache && req->continuous)
+ rdesc->info.op_tmpl = &rdesc->info.secondary_op_tmpl;
+ else
+ rdesc->info.op_tmpl = &rdesc->info.primary_op_tmpl;
+
if (nand->ecc.engine->integration == NAND_ECC_ENGINE_INTEGRATION_PIPELINED &&
req->mode != MTD_OPS_RAW)
rdesc->info.op_tmpl->data.ecc = true;
@@ -1221,6 +1226,7 @@ static struct spi_mem_dirmap_desc *spinand_create_rdesc(
* its spi controller, use regular reading
*/
spinand->cont_read_possible = false;
+ memset(&info->secondary_op_tmpl, 0, sizeof(info->secondary_op_tmpl));
info->length = nanddev_page_size(nand) +
nanddev_per_page_oobsize(nand);
@@ -1237,11 +1243,24 @@ static int spinand_create_dirmap(struct spinand_device *spinand,
struct nand_device *nand = spinand_to_nand(spinand);
struct spi_mem_dirmap_info info = { 0 };
struct spi_mem_dirmap_desc *desc;
- bool enable_ecc = false;
+ bool enable_ecc = false, secondary_op = false;
if (nand->ecc.engine->integration == NAND_ECC_ENGINE_INTEGRATION_PIPELINED)
enable_ecc = true;
+ if (spinand->cont_read_possible && spinand->op_templates->cont_read_cache)
+ secondary_op = true;
+
+ /*
+ * Continuous read implies that only the main data is retrieved, backed
+ * by an on-die ECC engine. It is not possible to use a pipelind ECC
+ * engine with continuous read.
+ */
+ if (enable_ecc && secondary_op) {
+ secondary_op = false;
+ spinand->cont_read_possible = false;
+ }
+
/* The plane number is passed in MSB just above the column address */
info.offset = plane << fls(nand->memorg.pagesize);
@@ -1259,6 +1278,10 @@ static int spinand_create_dirmap(struct spinand_device *spinand,
/* Read descriptor */
info.primary_op_tmpl = *spinand->op_templates->read_cache;
info.primary_op_tmpl.data.ecc = enable_ecc;
+ if (secondary_op) {
+ info.secondary_op_tmpl = *spinand->op_templates->cont_read_cache;
+ info.secondary_op_tmpl.data.ecc = enable_ecc;
+ }
desc = spinand_create_rdesc(spinand, &info);
if (IS_ERR(desc))
return PTR_ERR(desc);
@@ -1607,6 +1630,33 @@ int spinand_match_and_init(struct spinand_device *spinand,
if (ret)
return ret;
+ if (info->op_variants.cont_read_cache) {
+ op = spinand_select_op_variant(spinand, SSDR,
+ info->op_variants.cont_read_cache);
+ if (op) {
+ const struct spi_mem_op *read_op;
+
+ read_op = spinand->ssdr_op_templates.read_cache;
+
+ /*
+ * Sometimes the fastest continuous read variant may not
+ * be supported. In this case, prefer to use the fastest
+ * read from cache variant and disable continuous reads.
+ */
+ if (read_op->cmd.buswidth > op->cmd.buswidth ||
+ (read_op->cmd.dtr && !op->cmd.dtr) ||
+ read_op->addr.buswidth > op->addr.buswidth ||
+ (read_op->addr.dtr && !op->addr.dtr) ||
+ read_op->data.buswidth > op->data.buswidth ||
+ (read_op->data.dtr && !op->data.dtr))
+ spinand->cont_read_possible = false;
+ else
+ spinand->ssdr_op_templates.cont_read_cache = op;
+ } else {
+ spinand->cont_read_possible = false;
+ }
+ }
+
/* I/O variants selection with octo-spi DDR commands (optional) */
ret = spinand_init_odtr_instruction_set(spinand);
@@ -1629,6 +1679,15 @@ int spinand_match_and_init(struct spinand_device *spinand,
info->op_variants.update_cache);
spinand->odtr_op_templates.update_cache = op;
+ if (info->op_variants.cont_read_cache) {
+ op = spinand_select_op_variant(spinand, ODTR,
+ info->op_variants.cont_read_cache);
+ if (op)
+ spinand->odtr_op_templates.cont_read_cache = op;
+ else
+ spinand->cont_read_possible = false;
+ }
+
return 0;
}
diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h
index 896e9b5de0c4..4ff3f3383d46 100644
--- a/include/linux/mtd/spinand.h
+++ b/include/linux/mtd/spinand.h
@@ -576,6 +576,7 @@ enum spinand_bus_interface {
* @op_variants.read_cache: variants of the read-cache operation
* @op_variants.write_cache: variants of the write-cache operation
* @op_variants.update_cache: variants of the update-cache operation
+ * @op_variants.cont_read_cache: variants of the continuous read-cache operation
* @vendor_ops: vendor specific operations
* @select_target: function used to select a target/die. Required only for
* multi-die chips
@@ -600,6 +601,7 @@ struct spinand_info {
const struct spinand_op_variants *read_cache;
const struct spinand_op_variants *write_cache;
const struct spinand_op_variants *update_cache;
+ const struct spinand_op_variants *cont_read_cache;
} op_variants;
const struct spinand_op_variants *vendor_ops;
int (*select_target)(struct spinand_device *spinand,
@@ -629,6 +631,14 @@ struct spinand_info {
.update_cache = __update, \
}
+#define SPINAND_INFO_OP_VARIANTS_WITH_CONT(__read, __write, __update, __cont_read) \
+ { \
+ .read_cache = __read, \
+ .write_cache = __write, \
+ .update_cache = __update, \
+ .cont_read_cache = __cont_read, \
+ }
+
#define SPINAND_INFO_VENDOR_OPS(__ops) \
.vendor_ops = __ops
@@ -700,6 +710,7 @@ struct spinand_dirmap {
* @read_cache: read cache op template
* @write_cache: write cache op template
* @update_cache: update cache op template
+ * @cont_read_cache: continuous read cache op template (optional)
*/
struct spinand_mem_ops {
struct spi_mem_op reset;
@@ -714,6 +725,7 @@ struct spinand_mem_ops {
const struct spi_mem_op *read_cache;
const struct spi_mem_op *write_cache;
const struct spi_mem_op *update_cache;
+ const struct spi_mem_op *cont_read_cache;
};
/**
--
2.53.0
^ permalink raw reply related
* [PATCH v3 05/11] spi: spi-mem: Create a secondary read operation
From: Miquel Raynal @ 2026-04-29 17:56 UTC (permalink / raw)
To: Mark Brown, Richard Weinberger, Vignesh Raghavendra,
Michael Walle, Miquel Raynal, Takahiro Kuwano, Lorenzo Bianconi,
Ray Liu, Chin-Ting Kuo, Cédric Le Goater, Joel Stanley,
Andrew Jeffery, Avi Fishman, Tomer Maimon, Tali Perry,
Patrick Venture, Nancy Yuen, Benjamin Fair, Maxime Coquelin,
Alexandre Torgue, Jonathan Neuschäfer
Cc: Pratyush Yadav, Thomas Petazzoni, Steam Lin, Santhosh Kumar K,
linux-spi, linux-kernel, linux-mtd, linux-arm-kernel,
linux-aspeed, openbmc, linux-stm32
In-Reply-To: <20260429-winbond-v6-18-rc1-cont-read-v3-0-0f38b3c229ad@bootlin.com>
In some situations, direct mappings may need to use different
operation templates.
For instance, when enabling continuous reads, Winbond SPI NANDs no
longer expect address cycles because they would be ignoring them
otherwise. Hence, right after the command opcode, they start counting
dummy cycles, followed by the data cycles as usual.
This breaks the assumptions of "reads from cache" always being done
identically once the best variant has been picked up, across the
lifetime of the system.
In order to support this feature, we must give direct mapping more than
a single operation template to use, in order to switch to using
secondary operations upon request by the upper layer.
Create the concept of optional secondary operation template, which may
or may not be fulfilled by the SPI NAND and SPI NOR cores. If the
underlying SPI controller does not leverage any kind of direct mapping
acceleration, the feature has no impact and can be freely
used. Otherwise, the controller driver needs to opt-in for using this
feature, if supported.
The condition checked to know whether a secondary operation has been
provided or not is to look for a non zero opcode to limit the creation
of extra variables. In practice, the opcode 0x00 exist, but is not
related to any cache related operation.
Acked-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
The choice of defining two variables named primary and secondary instead
of using an array of templates is on purpose, to simplify the reading. I
find less obvious the use of an array here but this is personal taste.
---
drivers/spi/spi-mem.c | 17 +++++++++++++++++
include/linux/spi/spi-mem.h | 5 +++++
2 files changed, 22 insertions(+)
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index e2eaa1ba4ff6..f64eda9bbd9f 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -713,6 +713,23 @@ spi_mem_dirmap_create(struct spi_mem *mem,
if (info->primary_op_tmpl.data.dir == SPI_MEM_NO_DATA)
return ERR_PTR(-EINVAL);
+ /* Apply similar constraints to the secondary template */
+ if (info->secondary_op_tmpl.cmd.opcode) {
+ if (!info->secondary_op_tmpl.addr.nbytes ||
+ info->secondary_op_tmpl.addr.nbytes > 8)
+ return ERR_PTR(-EINVAL);
+
+ if (info->secondary_op_tmpl.data.dir == SPI_MEM_NO_DATA)
+ return ERR_PTR(-EINVAL);
+
+ if (!spi_mem_supports_op(mem, &info->secondary_op_tmpl))
+ return ERR_PTR(-EOPNOTSUPP);
+
+ if (ctlr->mem_ops && ctlr->mem_ops->dirmap_create &&
+ !spi_mem_controller_is_capable(ctlr, secondary_op_tmpl))
+ return ERR_PTR(-EOPNOTSUPP);
+ }
+
desc = kzalloc_obj(*desc);
if (!desc)
return ERR_PTR(-ENOMEM);
diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h
index 9a96ddace3eb..2012a3b2ef91 100644
--- a/include/linux/spi/spi-mem.h
+++ b/include/linux/spi/spi-mem.h
@@ -227,6 +227,8 @@ struct spi_mem_op {
* struct spi_mem_dirmap_info - Direct mapping information
* @op_tmpl: operation template that should be used by the direct mapping when
* the memory device is accessed
+ * @secondary_op_tmpl: secondary template, may be used as an alternative to the
+ * primary template (decided by the upper layer)
* @offset: absolute offset this direct mapping is pointing to
* @length: length in byte of this direct mapping
*
@@ -239,6 +241,7 @@ struct spi_mem_op {
struct spi_mem_dirmap_info {
struct spi_mem_op *op_tmpl;
struct spi_mem_op primary_op_tmpl;
+ struct spi_mem_op secondary_op_tmpl;
u64 offset;
u64 length;
};
@@ -382,12 +385,14 @@ struct spi_controller_mem_ops {
* @swap16: Supports swapping bytes on a 16 bit boundary when configured in
* Octal DTR
* @per_op_freq: Supports per operation frequency switching
+ * @secondary_op_tmpl: Supports leveraging a secondary memory operation template
*/
struct spi_controller_mem_caps {
bool dtr;
bool ecc;
bool swap16;
bool per_op_freq;
+ bool secondary_op_tmpl;
};
#define spi_mem_controller_is_capable(ctlr, cap) \
--
2.53.0
^ permalink raw reply related
* [PATCH v3 04/11] spi: spi-mem: Transform the read operation template
From: Miquel Raynal @ 2026-04-29 17:56 UTC (permalink / raw)
To: Mark Brown, Richard Weinberger, Vignesh Raghavendra,
Michael Walle, Miquel Raynal, Takahiro Kuwano, Lorenzo Bianconi,
Ray Liu, Chin-Ting Kuo, Cédric Le Goater, Joel Stanley,
Andrew Jeffery, Avi Fishman, Tomer Maimon, Tali Perry,
Patrick Venture, Nancy Yuen, Benjamin Fair, Maxime Coquelin,
Alexandre Torgue, Jonathan Neuschäfer
Cc: Pratyush Yadav, Thomas Petazzoni, Steam Lin, Santhosh Kumar K,
linux-spi, linux-kernel, linux-mtd, linux-arm-kernel,
linux-aspeed, openbmc, linux-stm32
In-Reply-To: <20260429-winbond-v6-18-rc1-cont-read-v3-0-0f38b3c229ad@bootlin.com>
As of now, we only use a single operation template when creating SPI
memory direct mappings. With the idea to extend this possibility to 2,
rename the template to reflect that we are currently setting the
"primary" operation, and create a pointer in the same structure to point
to it.
From a user point of view, the op_tmpl name remains but becomes a
pointer, leading to minor changes in both the SPI NAND and SPI NOR
cores.
There is no functional change.
Acked-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/mtd/nand/spi/core.c | 15 ++++++++-------
drivers/mtd/spi-nor/core.c | 22 ++++++++++++----------
drivers/spi/spi-airoha-snfi.c | 6 +++---
drivers/spi/spi-aspeed-smc.c | 4 ++--
drivers/spi/spi-intel.c | 6 +++---
drivers/spi/spi-mem.c | 15 ++++++++-------
drivers/spi/spi-mxic.c | 18 +++++++++---------
drivers/spi/spi-npcm-fiu.c | 16 ++++++++--------
drivers/spi/spi-rpc-if.c | 8 ++++----
drivers/spi/spi-stm32-ospi.c | 6 +++---
drivers/spi/spi-stm32-qspi.c | 6 +++---
drivers/spi/spi-wpcm-fiu.c | 2 +-
include/linux/spi/spi-mem.h | 3 ++-
13 files changed, 66 insertions(+), 61 deletions(-)
diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
index 663f5d6a6bd7..a66510747b31 100644
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -491,9 +491,9 @@ static int spinand_read_from_cache_op(struct spinand_device *spinand,
if (nand->ecc.engine->integration == NAND_ECC_ENGINE_INTEGRATION_PIPELINED &&
req->mode != MTD_OPS_RAW)
- rdesc->info.op_tmpl.data.ecc = true;
+ rdesc->info.op_tmpl->data.ecc = true;
else
- rdesc->info.op_tmpl.data.ecc = false;
+ rdesc->info.op_tmpl->data.ecc = false;
if (spinand->flags & SPINAND_HAS_READ_PLANE_SELECT_BIT)
column |= req->pos.plane << fls(nanddev_page_size(nand));
@@ -586,9 +586,9 @@ static int spinand_write_to_cache_op(struct spinand_device *spinand,
if (nand->ecc.engine->integration == NAND_ECC_ENGINE_INTEGRATION_PIPELINED &&
req->mode != MTD_OPS_RAW)
- wdesc->info.op_tmpl.data.ecc = true;
+ wdesc->info.op_tmpl->data.ecc = true;
else
- wdesc->info.op_tmpl.data.ecc = false;
+ wdesc->info.op_tmpl->data.ecc = false;
if (spinand->flags & SPINAND_HAS_PROG_PLANE_SELECT_BIT)
column |= req->pos.plane << fls(nanddev_page_size(nand));
@@ -1247,7 +1247,8 @@ static int spinand_create_dirmap(struct spinand_device *spinand,
/* Write descriptor */
info.length = nanddev_page_size(nand) + nanddev_per_page_oobsize(nand);
- info.op_tmpl.data.ecc = enable_ecc;
+ info.primary_op_tmpl = *spinand->op_templates->update_cache;
+ info.primary_op_tmpl.data.ecc = enable_ecc;
desc = devm_spi_mem_dirmap_create(&spinand->spimem->spi->dev,
spinand->spimem, &info);
if (IS_ERR(desc))
@@ -1256,8 +1257,8 @@ static int spinand_create_dirmap(struct spinand_device *spinand,
spinand->dirmaps[plane].wdesc = desc;
/* Read descriptor */
- info.op_tmpl = *spinand->op_templates->read_cache;
- info.op_tmpl.data.ecc = enable_ecc;
+ info.primary_op_tmpl = *spinand->op_templates->read_cache;
+ info.primary_op_tmpl.data.ecc = enable_ecc;
desc = spinand_create_rdesc(spinand, &info);
if (IS_ERR(desc))
return PTR_ERR(desc);
diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index 5dd0b3cb5250..a7bc458edc5c 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -3641,14 +3641,15 @@ EXPORT_SYMBOL_GPL(spi_nor_scan);
static int spi_nor_create_read_dirmap(struct spi_nor *nor)
{
struct spi_mem_dirmap_info info = {
- .op_tmpl = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 0),
- SPI_MEM_OP_ADDR(nor->addr_nbytes, 0, 0),
- SPI_MEM_OP_DUMMY(nor->read_dummy, 0),
- SPI_MEM_OP_DATA_IN(0, NULL, 0)),
+ .op_tmpl = &info.primary_op_tmpl,
+ .primary_op_tmpl = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 0),
+ SPI_MEM_OP_ADDR(nor->addr_nbytes, 0, 0),
+ SPI_MEM_OP_DUMMY(nor->read_dummy, 0),
+ SPI_MEM_OP_DATA_IN(0, NULL, 0)),
.offset = 0,
.length = nor->params->size,
};
- struct spi_mem_op *op = &info.op_tmpl;
+ struct spi_mem_op *op = info.op_tmpl;
spi_nor_spimem_setup_op(nor, op, nor->read_proto);
@@ -3672,14 +3673,15 @@ static int spi_nor_create_read_dirmap(struct spi_nor *nor)
static int spi_nor_create_write_dirmap(struct spi_nor *nor)
{
struct spi_mem_dirmap_info info = {
- .op_tmpl = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 0),
- SPI_MEM_OP_ADDR(nor->addr_nbytes, 0, 0),
- SPI_MEM_OP_NO_DUMMY,
- SPI_MEM_OP_DATA_OUT(0, NULL, 0)),
+ .op_tmpl = &info.primary_op_tmpl,
+ .primary_op_tmpl = SPI_MEM_OP(SPI_MEM_OP_CMD(nor->program_opcode, 0),
+ SPI_MEM_OP_ADDR(nor->addr_nbytes, 0, 0),
+ SPI_MEM_OP_NO_DUMMY,
+ SPI_MEM_OP_DATA_OUT(0, NULL, 0)),
.offset = 0,
.length = nor->params->size,
};
- struct spi_mem_op *op = &info.op_tmpl;
+ struct spi_mem_op *op = info.op_tmpl;
if (nor->program_opcode == SPINOR_OP_AAI_WP && nor->sst_write_second)
op->addr.nbytes = 0;
diff --git a/drivers/spi/spi-airoha-snfi.c b/drivers/spi/spi-airoha-snfi.c
index 7b6c09f91fef..95bfde7c8e7f 100644
--- a/drivers/spi/spi-airoha-snfi.c
+++ b/drivers/spi/spi-airoha-snfi.c
@@ -546,7 +546,7 @@ static int airoha_snand_dirmap_create(struct spi_mem_dirmap_desc *desc)
if (desc->info.length > SPI_NAND_CACHE_SIZE)
return -E2BIG;
- if (!airoha_snand_supports_op(desc->mem, &desc->info.op_tmpl))
+ if (!airoha_snand_supports_op(desc->mem, desc->info.op_tmpl))
return -EOPNOTSUPP;
return 0;
@@ -572,7 +572,7 @@ static ssize_t airoha_snand_dirmap_read(struct spi_mem_dirmap_desc *desc,
* DUALIO and QUADIO opcodes are not supported by the spi controller,
* replace them with supported opcodes.
*/
- opcode = desc->info.op_tmpl.cmd.opcode;
+ opcode = desc->info.op_tmpl->cmd.opcode;
switch (opcode) {
case SPI_NAND_OP_READ_FROM_CACHE_SINGLE:
case SPI_NAND_OP_READ_FROM_CACHE_SINGLE_FAST:
@@ -761,7 +761,7 @@ static ssize_t airoha_snand_dirmap_write(struct spi_mem_dirmap_desc *desc,
/* minimum oob size is 64 */
bytes = round_up(offs + len, 64);
- opcode = desc->info.op_tmpl.cmd.opcode;
+ opcode = desc->info.op_tmpl->cmd.opcode;
switch (opcode) {
case SPI_NAND_OP_PROGRAM_LOAD_SINGLE:
case SPI_NAND_OP_PROGRAM_LOAD_RAMDOM_SINGLE:
diff --git a/drivers/spi/spi-aspeed-smc.c b/drivers/spi/spi-aspeed-smc.c
index c21323e07d3c..c20a33734f5c 100644
--- a/drivers/spi/spi-aspeed-smc.c
+++ b/drivers/spi/spi-aspeed-smc.c
@@ -697,7 +697,7 @@ static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
{
struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->controller);
struct aspeed_spi_chip *chip = &aspi->chips[spi_get_chipselect(desc->mem->spi, 0)];
- struct spi_mem_op *op = &desc->info.op_tmpl;
+ struct spi_mem_op *op = desc->info.op_tmpl;
u32 ctl_val;
int ret = 0;
@@ -769,7 +769,7 @@ static ssize_t aspeed_spi_dirmap_read(struct spi_mem_dirmap_desc *desc,
if (chip->ahb_window_size < offset + len || chip->force_user_mode) {
int ret;
- ret = aspeed_spi_read_user(chip, &desc->info.op_tmpl, offset, len, buf);
+ ret = aspeed_spi_read_user(chip, desc->info.op_tmpl, offset, len, buf);
if (ret < 0)
return ret;
} else {
diff --git a/drivers/spi/spi-intel.c b/drivers/spi/spi-intel.c
index 1775ad39e633..7494b921a743 100644
--- a/drivers/spi/spi-intel.c
+++ b/drivers/spi/spi-intel.c
@@ -814,7 +814,7 @@ static int intel_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
struct intel_spi *ispi = spi_controller_get_devdata(desc->mem->spi->controller);
const struct intel_spi_mem_op *iop;
- iop = intel_spi_match_mem_op(ispi, &desc->info.op_tmpl);
+ iop = intel_spi_match_mem_op(ispi, desc->info.op_tmpl);
if (!iop)
return -EOPNOTSUPP;
@@ -827,7 +827,7 @@ static ssize_t intel_spi_dirmap_read(struct spi_mem_dirmap_desc *desc, u64 offs,
{
struct intel_spi *ispi = spi_controller_get_devdata(desc->mem->spi->controller);
const struct intel_spi_mem_op *iop = desc->priv;
- struct spi_mem_op op = desc->info.op_tmpl;
+ struct spi_mem_op op = *desc->info.op_tmpl;
int ret;
/* Fill in the gaps */
@@ -844,7 +844,7 @@ static ssize_t intel_spi_dirmap_write(struct spi_mem_dirmap_desc *desc, u64 offs
{
struct intel_spi *ispi = spi_controller_get_devdata(desc->mem->spi->controller);
const struct intel_spi_mem_op *iop = desc->priv;
- struct spi_mem_op op = desc->info.op_tmpl;
+ struct spi_mem_op op = *desc->info.op_tmpl;
int ret;
op.addr.val = offs;
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index a09371a075d2..e2eaa1ba4ff6 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -647,7 +647,7 @@ EXPORT_SYMBOL_GPL(spi_mem_calc_op_duration);
static ssize_t spi_mem_no_dirmap_read(struct spi_mem_dirmap_desc *desc,
u64 offs, size_t len, void *buf)
{
- struct spi_mem_op op = desc->info.op_tmpl;
+ struct spi_mem_op op = *desc->info.op_tmpl;
int ret;
op.addr.val = desc->info.offset + offs;
@@ -667,7 +667,7 @@ static ssize_t spi_mem_no_dirmap_read(struct spi_mem_dirmap_desc *desc,
static ssize_t spi_mem_no_dirmap_write(struct spi_mem_dirmap_desc *desc,
u64 offs, size_t len, const void *buf)
{
- struct spi_mem_op op = desc->info.op_tmpl;
+ struct spi_mem_op op = *desc->info.op_tmpl;
int ret;
op.addr.val = desc->info.offset + offs;
@@ -706,11 +706,11 @@ spi_mem_dirmap_create(struct spi_mem *mem,
int ret = -ENOTSUPP;
/* Make sure the number of address cycles is between 1 and 8 bytes. */
- if (!info->op_tmpl.addr.nbytes || info->op_tmpl.addr.nbytes > 8)
+ if (!info->primary_op_tmpl.addr.nbytes || info->primary_op_tmpl.addr.nbytes > 8)
return ERR_PTR(-EINVAL);
/* data.dir should either be SPI_MEM_DATA_IN or SPI_MEM_DATA_OUT. */
- if (info->op_tmpl.data.dir == SPI_MEM_NO_DATA)
+ if (info->primary_op_tmpl.data.dir == SPI_MEM_NO_DATA)
return ERR_PTR(-EINVAL);
desc = kzalloc_obj(*desc);
@@ -719,6 +719,7 @@ spi_mem_dirmap_create(struct spi_mem *mem,
desc->mem = mem;
desc->info = *info;
+ desc->info.op_tmpl = &desc->info.primary_op_tmpl;
if (ctlr->mem_ops && ctlr->mem_ops->dirmap_create) {
ret = spi_mem_access_start(mem);
if (ret) {
@@ -733,7 +734,7 @@ spi_mem_dirmap_create(struct spi_mem *mem,
if (ret) {
desc->nodirmap = true;
- if (!spi_mem_supports_op(desc->mem, &desc->info.op_tmpl))
+ if (!spi_mem_supports_op(desc->mem, &desc->info.primary_op_tmpl))
ret = -EOPNOTSUPP;
else
ret = 0;
@@ -857,7 +858,7 @@ ssize_t spi_mem_dirmap_read(struct spi_mem_dirmap_desc *desc,
struct spi_controller *ctlr = desc->mem->spi->controller;
ssize_t ret;
- if (desc->info.op_tmpl.data.dir != SPI_MEM_DATA_IN)
+ if (desc->info.op_tmpl->data.dir != SPI_MEM_DATA_IN)
return -EINVAL;
if (!len)
@@ -903,7 +904,7 @@ ssize_t spi_mem_dirmap_write(struct spi_mem_dirmap_desc *desc,
struct spi_controller *ctlr = desc->mem->spi->controller;
ssize_t ret;
- if (desc->info.op_tmpl.data.dir != SPI_MEM_DATA_OUT)
+ if (desc->info.op_tmpl->data.dir != SPI_MEM_DATA_OUT)
return -EINVAL;
if (!len)
diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c
index b0e7fc828a50..83b688e65284 100644
--- a/drivers/spi/spi-mxic.c
+++ b/drivers/spi/spi-mxic.c
@@ -403,20 +403,20 @@ static ssize_t mxic_spi_mem_dirmap_read(struct spi_mem_dirmap_desc *desc,
if (WARN_ON(offs + desc->info.offset + len > U32_MAX))
return -EINVAL;
- writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0, desc->info.op_tmpl.data.swap16),
+ writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0, desc->info.op_tmpl->data.swap16),
mxic->regs + HC_CFG);
- writel(mxic_spi_mem_prep_op_cfg(&desc->info.op_tmpl, len),
+ writel(mxic_spi_mem_prep_op_cfg(desc->info.op_tmpl, len),
mxic->regs + LRD_CFG);
writel(desc->info.offset + offs, mxic->regs + LRD_ADDR);
len = min_t(size_t, len, mxic->linear.size);
writel(len, mxic->regs + LRD_RANGE);
- writel(LMODE_CMD0(desc->info.op_tmpl.cmd.opcode) |
+ writel(LMODE_CMD0(desc->info.op_tmpl->cmd.opcode) |
LMODE_SLV_ACT(spi_get_chipselect(desc->mem->spi, 0)) |
LMODE_EN,
mxic->regs + LRD_CTRL);
- if (mxic->ecc.use_pipelined_conf && desc->info.op_tmpl.data.ecc) {
+ if (mxic->ecc.use_pipelined_conf && desc->info.op_tmpl->data.ecc) {
ret = mxic_ecc_process_data_pipelined(mxic->ecc.pipelined_engine,
NAND_PAGE_READ,
mxic->linear.dma + offs);
@@ -448,20 +448,20 @@ static ssize_t mxic_spi_mem_dirmap_write(struct spi_mem_dirmap_desc *desc,
if (WARN_ON(offs + desc->info.offset + len > U32_MAX))
return -EINVAL;
- writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0, desc->info.op_tmpl.data.swap16),
+ writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0, desc->info.op_tmpl->data.swap16),
mxic->regs + HC_CFG);
- writel(mxic_spi_mem_prep_op_cfg(&desc->info.op_tmpl, len),
+ writel(mxic_spi_mem_prep_op_cfg(desc->info.op_tmpl, len),
mxic->regs + LWR_CFG);
writel(desc->info.offset + offs, mxic->regs + LWR_ADDR);
len = min_t(size_t, len, mxic->linear.size);
writel(len, mxic->regs + LWR_RANGE);
- writel(LMODE_CMD0(desc->info.op_tmpl.cmd.opcode) |
+ writel(LMODE_CMD0(desc->info.op_tmpl->cmd.opcode) |
LMODE_SLV_ACT(spi_get_chipselect(desc->mem->spi, 0)) |
LMODE_EN,
mxic->regs + LWR_CTRL);
- if (mxic->ecc.use_pipelined_conf && desc->info.op_tmpl.data.ecc) {
+ if (mxic->ecc.use_pipelined_conf && desc->info.op_tmpl->data.ecc) {
ret = mxic_ecc_process_data_pipelined(mxic->ecc.pipelined_engine,
NAND_PAGE_WRITE,
mxic->linear.dma + offs);
@@ -509,7 +509,7 @@ static int mxic_spi_mem_dirmap_create(struct spi_mem_dirmap_desc *desc)
if (desc->info.offset + desc->info.length > U32_MAX)
return -EINVAL;
- if (!mxic_spi_mem_supports_op(desc->mem, &desc->info.op_tmpl))
+ if (!mxic_spi_mem_supports_op(desc->mem, desc->info.op_tmpl))
return -EOPNOTSUPP;
return 0;
diff --git a/drivers/spi/spi-npcm-fiu.c b/drivers/spi/spi-npcm-fiu.c
index 6617751009c3..4b825044038b 100644
--- a/drivers/spi/spi-npcm-fiu.c
+++ b/drivers/spi/spi-npcm-fiu.c
@@ -299,11 +299,11 @@ static ssize_t npcm_fiu_direct_read(struct spi_mem_dirmap_desc *desc,
for (i = 0 ; i < len ; i++)
*(buf_rx + i) = ioread8(src + i);
} else {
- if (desc->info.op_tmpl.addr.buswidth != fiu->drd_op.addr.buswidth ||
- desc->info.op_tmpl.dummy.nbytes != fiu->drd_op.dummy.nbytes ||
- desc->info.op_tmpl.cmd.opcode != fiu->drd_op.cmd.opcode ||
- desc->info.op_tmpl.addr.nbytes != fiu->drd_op.addr.nbytes)
- npcm_fiu_set_drd(fiu, &desc->info.op_tmpl);
+ if (desc->info.op_tmpl->addr.buswidth != fiu->drd_op.addr.buswidth ||
+ desc->info.op_tmpl->dummy.nbytes != fiu->drd_op.dummy.nbytes ||
+ desc->info.op_tmpl->cmd.opcode != fiu->drd_op.cmd.opcode ||
+ desc->info.op_tmpl->addr.nbytes != fiu->drd_op.addr.nbytes)
+ npcm_fiu_set_drd(fiu, desc->info.op_tmpl);
memcpy_fromio(buf_rx, src, len);
}
@@ -609,7 +609,7 @@ static int npcm_fiu_dirmap_create(struct spi_mem_dirmap_desc *desc)
}
if (!fiu->spix_mode &&
- desc->info.op_tmpl.data.dir == SPI_MEM_DATA_OUT) {
+ desc->info.op_tmpl->data.dir == SPI_MEM_DATA_OUT) {
desc->nodirmap = true;
return 0;
}
@@ -644,9 +644,9 @@ static int npcm_fiu_dirmap_create(struct spi_mem_dirmap_desc *desc)
NPCM_FIU_CFG_FIU_FIX);
}
- if (desc->info.op_tmpl.data.dir == SPI_MEM_DATA_IN) {
+ if (desc->info.op_tmpl->data.dir == SPI_MEM_DATA_IN) {
if (!fiu->spix_mode)
- npcm_fiu_set_drd(fiu, &desc->info.op_tmpl);
+ npcm_fiu_set_drd(fiu, desc->info.op_tmpl);
else
npcm_fiux_set_direct_rd(fiu);
diff --git a/drivers/spi/spi-rpc-if.c b/drivers/spi/spi-rpc-if.c
index 6edc0c4db854..1ef7bd91b3b3 100644
--- a/drivers/spi/spi-rpc-if.c
+++ b/drivers/spi/spi-rpc-if.c
@@ -83,7 +83,7 @@ static ssize_t xspi_spi_mem_dirmap_write(struct spi_mem_dirmap_desc *desc,
if (offs + desc->info.offset + len > U32_MAX)
return -EINVAL;
- rpcif_spi_mem_prepare(desc->mem->spi, &desc->info.op_tmpl, &offs, &len);
+ rpcif_spi_mem_prepare(desc->mem->spi, desc->info.op_tmpl, &offs, &len);
return xspi_dirmap_write(rpc->dev, offs, len, buf);
}
@@ -97,7 +97,7 @@ static ssize_t rpcif_spi_mem_dirmap_read(struct spi_mem_dirmap_desc *desc,
if (offs + desc->info.offset + len > U32_MAX)
return -EINVAL;
- rpcif_spi_mem_prepare(desc->mem->spi, &desc->info.op_tmpl, &offs, &len);
+ rpcif_spi_mem_prepare(desc->mem->spi, desc->info.op_tmpl, &offs, &len);
return rpcif_dirmap_read(rpc->dev, offs, len, buf);
}
@@ -110,13 +110,13 @@ static int rpcif_spi_mem_dirmap_create(struct spi_mem_dirmap_desc *desc)
if (desc->info.offset + desc->info.length > U32_MAX)
return -EINVAL;
- if (!rpcif_spi_mem_supports_op(desc->mem, &desc->info.op_tmpl))
+ if (!rpcif_spi_mem_supports_op(desc->mem, desc->info.op_tmpl))
return -EOPNOTSUPP;
if (!rpc->dirmap)
return -EOPNOTSUPP;
- if (!rpc->xspi && desc->info.op_tmpl.data.dir != SPI_MEM_DATA_IN)
+ if (!rpc->xspi && desc->info.op_tmpl->data.dir != SPI_MEM_DATA_IN)
return -EOPNOTSUPP;
return 0;
diff --git a/drivers/spi/spi-stm32-ospi.c b/drivers/spi/spi-stm32-ospi.c
index 4461c6e24b9e..5f5b3cd5d725 100644
--- a/drivers/spi/spi-stm32-ospi.c
+++ b/drivers/spi/spi-stm32-ospi.c
@@ -602,11 +602,11 @@ static int stm32_ospi_dirmap_create(struct spi_mem_dirmap_desc *desc)
{
struct stm32_ospi *ospi = spi_controller_get_devdata(desc->mem->spi->controller);
- if (desc->info.op_tmpl.data.dir == SPI_MEM_DATA_OUT)
+ if (desc->info.op_tmpl->data.dir == SPI_MEM_DATA_OUT)
return -EOPNOTSUPP;
/* Should never happen, as mm_base == null is an error probe exit condition */
- if (!ospi->mm_base && desc->info.op_tmpl.data.dir == SPI_MEM_DATA_IN)
+ if (!ospi->mm_base && desc->info.op_tmpl->data.dir == SPI_MEM_DATA_IN)
return -EOPNOTSUPP;
if (!ospi->mm_size)
@@ -633,7 +633,7 @@ static ssize_t stm32_ospi_dirmap_read(struct spi_mem_dirmap_desc *desc,
* spi_mem_op template with offs, len and *buf in order to get
* all needed transfer information into struct spi_mem_op
*/
- memcpy(&op, &desc->info.op_tmpl, sizeof(struct spi_mem_op));
+ memcpy(&op, desc->info.op_tmpl, sizeof(struct spi_mem_op));
dev_dbg(ospi->dev, "%s len = 0x%zx offs = 0x%llx buf = 0x%p\n", __func__, len, offs, buf);
op.data.nbytes = len;
diff --git a/drivers/spi/spi-stm32-qspi.c b/drivers/spi/spi-stm32-qspi.c
index df1bbacec90a..e2a6a6eaf9b2 100644
--- a/drivers/spi/spi-stm32-qspi.c
+++ b/drivers/spi/spi-stm32-qspi.c
@@ -506,11 +506,11 @@ static int stm32_qspi_dirmap_create(struct spi_mem_dirmap_desc *desc)
{
struct stm32_qspi *qspi = spi_controller_get_devdata(desc->mem->spi->controller);
- if (desc->info.op_tmpl.data.dir == SPI_MEM_DATA_OUT)
+ if (desc->info.op_tmpl->data.dir == SPI_MEM_DATA_OUT)
return -EOPNOTSUPP;
/* should never happen, as mm_base == null is an error probe exit condition */
- if (!qspi->mm_base && desc->info.op_tmpl.data.dir == SPI_MEM_DATA_IN)
+ if (!qspi->mm_base && desc->info.op_tmpl->data.dir == SPI_MEM_DATA_IN)
return -EOPNOTSUPP;
if (!qspi->mm_size)
@@ -536,7 +536,7 @@ static ssize_t stm32_qspi_dirmap_read(struct spi_mem_dirmap_desc *desc,
* spi_mem_op template with offs, len and *buf in order to get
* all needed transfer information into struct spi_mem_op
*/
- memcpy(&op, &desc->info.op_tmpl, sizeof(struct spi_mem_op));
+ memcpy(&op, desc->info.op_tmpl, sizeof(struct spi_mem_op));
dev_dbg(qspi->dev, "%s len = 0x%zx offs = 0x%llx buf = 0x%p\n", __func__, len, offs, buf);
op.data.nbytes = len;
diff --git a/drivers/spi/spi-wpcm-fiu.c b/drivers/spi/spi-wpcm-fiu.c
index 0e26ff178505..cd78e927953d 100644
--- a/drivers/spi/spi-wpcm-fiu.c
+++ b/drivers/spi/spi-wpcm-fiu.c
@@ -377,7 +377,7 @@ static int wpcm_fiu_dirmap_create(struct spi_mem_dirmap_desc *desc)
struct wpcm_fiu_spi *fiu = spi_controller_get_devdata(desc->mem->spi->controller);
int cs = spi_get_chipselect(desc->mem->spi, 0);
- if (desc->info.op_tmpl.data.dir != SPI_MEM_DATA_IN)
+ if (desc->info.op_tmpl->data.dir != SPI_MEM_DATA_IN)
return -EOPNOTSUPP;
/*
diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h
index c8e207522223..9a96ddace3eb 100644
--- a/include/linux/spi/spi-mem.h
+++ b/include/linux/spi/spi-mem.h
@@ -237,7 +237,8 @@ struct spi_mem_op {
* direction is directly encoded in the ->op_tmpl.data.dir field.
*/
struct spi_mem_dirmap_info {
- struct spi_mem_op op_tmpl;
+ struct spi_mem_op *op_tmpl;
+ struct spi_mem_op primary_op_tmpl;
u64 offset;
u64 length;
};
--
2.53.0
^ permalink raw reply related
* [PATCH v3 03/11] mtd: spinand: Drop ECC dirmaps
From: Miquel Raynal @ 2026-04-29 17:56 UTC (permalink / raw)
To: Mark Brown, Richard Weinberger, Vignesh Raghavendra,
Michael Walle, Miquel Raynal, Takahiro Kuwano, Lorenzo Bianconi,
Ray Liu, Chin-Ting Kuo, Cédric Le Goater, Joel Stanley,
Andrew Jeffery, Avi Fishman, Tomer Maimon, Tali Perry,
Patrick Venture, Nancy Yuen, Benjamin Fair, Maxime Coquelin,
Alexandre Torgue, Jonathan Neuschäfer
Cc: Pratyush Yadav, Thomas Petazzoni, Steam Lin, Santhosh Kumar K,
linux-spi, linux-kernel, linux-mtd, linux-arm-kernel,
linux-aspeed, openbmc, linux-stm32
In-Reply-To: <20260429-winbond-v6-18-rc1-cont-read-v3-0-0f38b3c229ad@bootlin.com>
Direct mappings are very static concepts, which allow us to reuse a
template to perform reads or writes in a very efficient manner after a
single initialization. With the introduction of pipelined ECC engines
for SPI controllers, the need to differentiate between an operation with
and without correction has arised. The chosen solution at that time has
been to create new direct mappings for these operations, jumping from 2
to 4 dirmaps per target. Enabling ECC was done by choosing the correct
dirmap.
Today, we need to further parametrize dirmaps. With the goal to enable
continuous reads on a wider range of devices, we will need more
flexibility regarding the read from cache operation template to pick at
run time, for instance to use shorter "continuous read from cache"
variants.
We could create other direct mappings, but it would increase the matrix
by a power of two, bringing the theoretical number of dirmaps to
8 (read/write, ecc, shorter read variants) per target. This grow is not
sustainable, so let's change how dirmaps work - a little bit.
Operations already carry an ECC parameter, use it to indicate whether
error correction is required or not. In practice this change happens
only at the core level, SPI controller drivers do not care about the
direct mapping structure in this case, they just pick whatever is in the
template as a base. As a result, we allow the core to dynamically change
the content of the templates.
He who can do more can do less, so during the checking steps, make sure
to enable the ECC requirement just for the time of the checks.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/mtd/nand/spi/core.c | 52 +++++++++++++++++----------------------------
include/linux/mtd/spinand.h | 2 --
2 files changed, 20 insertions(+), 34 deletions(-)
diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
index 1c3ac9ad650e..663f5d6a6bd7 100644
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -487,10 +487,13 @@ static int spinand_read_from_cache_op(struct spinand_device *spinand,
}
}
- if (req->mode == MTD_OPS_RAW)
- rdesc = spinand->dirmaps[req->pos.plane].rdesc;
+ rdesc = spinand->dirmaps[req->pos.plane].rdesc;
+
+ if (nand->ecc.engine->integration == NAND_ECC_ENGINE_INTEGRATION_PIPELINED &&
+ req->mode != MTD_OPS_RAW)
+ rdesc->info.op_tmpl.data.ecc = true;
else
- rdesc = spinand->dirmaps[req->pos.plane].rdesc_ecc;
+ rdesc->info.op_tmpl.data.ecc = false;
if (spinand->flags & SPINAND_HAS_READ_PLANE_SELECT_BIT)
column |= req->pos.plane << fls(nanddev_page_size(nand));
@@ -579,10 +582,13 @@ static int spinand_write_to_cache_op(struct spinand_device *spinand,
req->ooblen);
}
- if (req->mode == MTD_OPS_RAW)
- wdesc = spinand->dirmaps[req->pos.plane].wdesc;
+ wdesc = spinand->dirmaps[req->pos.plane].wdesc;
+
+ if (nand->ecc.engine->integration == NAND_ECC_ENGINE_INTEGRATION_PIPELINED &&
+ req->mode != MTD_OPS_RAW)
+ wdesc->info.op_tmpl.data.ecc = true;
else
- wdesc = spinand->dirmaps[req->pos.plane].wdesc_ecc;
+ wdesc->info.op_tmpl.data.ecc = false;
if (spinand->flags & SPINAND_HAS_PROG_PLANE_SELECT_BIT)
column |= req->pos.plane << fls(nanddev_page_size(nand));
@@ -1231,12 +1237,17 @@ static int spinand_create_dirmap(struct spinand_device *spinand,
struct nand_device *nand = spinand_to_nand(spinand);
struct spi_mem_dirmap_info info = { 0 };
struct spi_mem_dirmap_desc *desc;
+ bool enable_ecc = false;
+
+ if (nand->ecc.engine->integration == NAND_ECC_ENGINE_INTEGRATION_PIPELINED)
+ enable_ecc = true;
/* The plane number is passed in MSB just above the column address */
info.offset = plane << fls(nand->memorg.pagesize);
+ /* Write descriptor */
info.length = nanddev_page_size(nand) + nanddev_per_page_oobsize(nand);
- info.op_tmpl = *spinand->op_templates->update_cache;
+ info.op_tmpl.data.ecc = enable_ecc;
desc = devm_spi_mem_dirmap_create(&spinand->spimem->spi->dev,
spinand->spimem, &info);
if (IS_ERR(desc))
@@ -1244,38 +1255,15 @@ static int spinand_create_dirmap(struct spinand_device *spinand,
spinand->dirmaps[plane].wdesc = desc;
+ /* Read descriptor */
info.op_tmpl = *spinand->op_templates->read_cache;
+ info.op_tmpl.data.ecc = enable_ecc;
desc = spinand_create_rdesc(spinand, &info);
if (IS_ERR(desc))
return PTR_ERR(desc);
spinand->dirmaps[plane].rdesc = desc;
- if (nand->ecc.engine->integration != NAND_ECC_ENGINE_INTEGRATION_PIPELINED) {
- spinand->dirmaps[plane].wdesc_ecc = spinand->dirmaps[plane].wdesc;
- spinand->dirmaps[plane].rdesc_ecc = spinand->dirmaps[plane].rdesc;
-
- return 0;
- }
-
- info.length = nanddev_page_size(nand) + nanddev_per_page_oobsize(nand);
- info.op_tmpl = *spinand->op_templates->update_cache;
- info.op_tmpl.data.ecc = true;
- desc = devm_spi_mem_dirmap_create(&spinand->spimem->spi->dev,
- spinand->spimem, &info);
- if (IS_ERR(desc))
- return PTR_ERR(desc);
-
- spinand->dirmaps[plane].wdesc_ecc = desc;
-
- info.op_tmpl = *spinand->op_templates->read_cache;
- info.op_tmpl.data.ecc = true;
- desc = spinand_create_rdesc(spinand, &info);
- if (IS_ERR(desc))
- return PTR_ERR(desc);
-
- spinand->dirmaps[plane].rdesc_ecc = desc;
-
return 0;
}
diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h
index e1f19664bb25..896e9b5de0c4 100644
--- a/include/linux/mtd/spinand.h
+++ b/include/linux/mtd/spinand.h
@@ -684,8 +684,6 @@ struct spinand_info {
struct spinand_dirmap {
struct spi_mem_dirmap_desc *wdesc;
struct spi_mem_dirmap_desc *rdesc;
- struct spi_mem_dirmap_desc *wdesc_ecc;
- struct spi_mem_dirmap_desc *rdesc_ecc;
};
/**
--
2.53.0
^ permalink raw reply related
* [PATCH v3 01/11] mtd: spinand: Drop a too strong limitation
From: Miquel Raynal @ 2026-04-29 17:56 UTC (permalink / raw)
To: Mark Brown, Richard Weinberger, Vignesh Raghavendra,
Michael Walle, Miquel Raynal, Takahiro Kuwano, Lorenzo Bianconi,
Ray Liu, Chin-Ting Kuo, Cédric Le Goater, Joel Stanley,
Andrew Jeffery, Avi Fishman, Tomer Maimon, Tali Perry,
Patrick Venture, Nancy Yuen, Benjamin Fair, Maxime Coquelin,
Alexandre Torgue, Jonathan Neuschäfer
Cc: Pratyush Yadav, Thomas Petazzoni, Steam Lin, Santhosh Kumar K,
linux-spi, linux-kernel, linux-mtd, linux-arm-kernel,
linux-aspeed, openbmc, linux-stm32
In-Reply-To: <20260429-winbond-v6-18-rc1-cont-read-v3-0-0f38b3c229ad@bootlin.com>
Since continuous reads may sometimes not be able to go past an erase
block boundary, it has been decided not to attempt longer reads and if
the user request is bigger, it will be split across eraseblocks.
As these request will anyway be handled correctly, there is no reason to
filter out cases where we would go over a target or a die, so drop this
limitation which had a side effect: any request to read more than the
content of an eraseblock would simply not benefit from the continuous
read feature.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/mtd/nand/spi/core.c | 19 ++++++-------------
1 file changed, 6 insertions(+), 13 deletions(-)
diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
index 66c90419f6d5..fba3cc213c88 100644
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -878,6 +878,12 @@ static int spinand_mtd_continuous_page_read(struct mtd_info *mtd, loff_t from,
* Each data read must be a multiple of 4-bytes and full pages should be read;
* otherwise, the data output might get out of sequence from one read command
* to another.
+ *
+ * Continuous reads never cross LUN boundaries. Some devices don't
+ * support crossing planes boundaries. Some devices don't even support
+ * crossing blocks boundaries. The common case being to read through UBI,
+ * we will very rarely read two consequent blocks or more, so let's only enable
+ * continuous reads when reading within the same erase block.
*/
nanddev_io_for_each_block(nand, NAND_PAGE_READ, from, ops, &iter) {
ret = spinand_select_target(spinand, iter.req.pos.target);
@@ -968,19 +974,6 @@ static bool spinand_use_cont_read(struct mtd_info *mtd, loff_t from,
nanddev_offs_to_pos(nand, from, &start_pos);
nanddev_offs_to_pos(nand, from + ops->len - 1, &end_pos);
- /*
- * Continuous reads never cross LUN boundaries. Some devices don't
- * support crossing planes boundaries. Some devices don't even support
- * crossing blocks boundaries. The common case being to read through UBI,
- * we will very rarely read two consequent blocks or more, so it is safer
- * and easier (can be improved) to only enable continuous reads when
- * reading within the same erase block.
- */
- if (start_pos.target != end_pos.target ||
- start_pos.plane != end_pos.plane ||
- start_pos.eraseblock != end_pos.eraseblock)
- return false;
-
return start_pos.page < end_pos.page;
}
--
2.53.0
^ permalink raw reply related
* [PATCH v3 02/11] mtd: spinand: Expose spinand_op_is_odtr()
From: Miquel Raynal @ 2026-04-29 17:56 UTC (permalink / raw)
To: Mark Brown, Richard Weinberger, Vignesh Raghavendra,
Michael Walle, Miquel Raynal, Takahiro Kuwano, Lorenzo Bianconi,
Ray Liu, Chin-Ting Kuo, Cédric Le Goater, Joel Stanley,
Andrew Jeffery, Avi Fishman, Tomer Maimon, Tali Perry,
Patrick Venture, Nancy Yuen, Benjamin Fair, Maxime Coquelin,
Alexandre Torgue, Jonathan Neuschäfer
Cc: Pratyush Yadav, Thomas Petazzoni, Steam Lin, Santhosh Kumar K,
linux-spi, linux-kernel, linux-mtd, linux-arm-kernel,
linux-aspeed, openbmc, linux-stm32
In-Reply-To: <20260429-winbond-v6-18-rc1-cont-read-v3-0-0f38b3c229ad@bootlin.com>
This helper is going to be needed in a vendor driver, so expose it.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/mtd/nand/spi/core.c | 2 +-
include/linux/mtd/spinand.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
index fba3cc213c88..1c3ac9ad650e 100644
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -1400,7 +1400,7 @@ static void spinand_manufacturer_cleanup(struct spinand_device *spinand)
return spinand->manufacturer->ops->cleanup(spinand);
}
-static bool spinand_op_is_odtr(const struct spi_mem_op *op)
+bool spinand_op_is_odtr(const struct spi_mem_op *op)
{
return op->cmd.dtr && op->cmd.buswidth == 8;
}
diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h
index 58abd306ebe3..e1f19664bb25 100644
--- a/include/linux/mtd/spinand.h
+++ b/include/linux/mtd/spinand.h
@@ -862,6 +862,8 @@ static inline void spinand_set_of_node(struct spinand_device *spinand,
nanddev_set_of_node(&spinand->base, np);
}
+bool spinand_op_is_odtr(const struct spi_mem_op *op);
+
int spinand_match_and_init(struct spinand_device *spinand,
const struct spinand_info *table,
unsigned int table_size,
--
2.53.0
^ permalink raw reply related
* [PATCH v3 00/11] mtd: spinand: Winbond continuous read support
From: Miquel Raynal @ 2026-04-29 17:56 UTC (permalink / raw)
To: Mark Brown, Richard Weinberger, Vignesh Raghavendra,
Michael Walle, Miquel Raynal, Takahiro Kuwano, Lorenzo Bianconi,
Ray Liu, Chin-Ting Kuo, Cédric Le Goater, Joel Stanley,
Andrew Jeffery, Avi Fishman, Tomer Maimon, Tali Perry,
Patrick Venture, Nancy Yuen, Benjamin Fair, Maxime Coquelin,
Alexandre Torgue, Jonathan Neuschäfer
Cc: Pratyush Yadav, Thomas Petazzoni, Steam Lin, Santhosh Kumar K,
linux-spi, linux-kernel, linux-mtd, linux-arm-kernel,
linux-aspeed, openbmc, linux-stm32
Hello,
TLDR: I dropped v2 from my tree due to build issues with SPI
controllers which I forgot about due to my testing configuration being
minimal. This is just a respin of the same series, fixing the spi
controller drivers which I initially missed.
SPI NAND continuous read support has already been added a few releases
ago, but only Macronix chips were benefiting from this support. Winbond
chips also have a continuous read feature, which is slightly more
complex to use in the scope of the Linux kernel, because they these
chips expect a different read from cache operation once in continuous
mode.
In order to be more flexible, this series changes the logic behind
dirmaps. Direct mappings used to be very static, not flexible. I am
proposing to change this and turn them in to slightly more dynamic
interfaces, where for instance we can:
- Enable/disable the correction (was previously handled by creating yet
another pair of direct mappings per target).
- Select one or another variant for the cache operations.
I propose to name the variants available in a direct mapping "primary"
and "secondary", and let the upper layer (SPI NOR or SPI NAND) point to
the one that needs to be used for the operation. Controller drivers
should not really care about this change, expect the fact that they
should not keep a static representation of the template on their
side. Because of that, I am creating a capability boolean to flag
drivers that support this capability (the flag is ignored in the
nodirmap case).
This series is now sent as v2 following a former RFC (link below).
Here is a benchmark with the faster Winbond chip I have, W35N02JW on a
TI AM62a7 LP SK featuring the Cadence QSPI controller, clocked at
25MHz. Speed gain for a 10-page read is about +32% in octal SDR mode,
+47% for a 10-page read in octal DTR mode and up to +83% for a entire
block read!
1S-8S-8S, no continuous read:
64 page read speed is 15058 KiB/s
1S-8S-8S, with continuous reads:
1 page read speed is 15058 KiB/s
2 page read speed is 15058 KiB/s
3 page read speed is 16800 KiB/s
4 page read speed is 17066 KiB/s
5 page read speed is 18461 KiB/s
6 page read speed is 18461 KiB/s
7 page read speed is 19384 KiB/s
8 page read speed is 19692 KiB/s
9 page read speed is 19384 KiB/s
10 page read speed is 20000 KiB/s
11 page read speed is 20000 KiB/s
12 page read speed is 20000 KiB/s
13 page read speed is 20800 KiB/s
14 page read speed is 20363 KiB/s
15 page read speed is 20000 KiB/s
16 page read speed is 19692 KiB/s
32 page read speed is 19692 KiB/s
64 page read speed is 19692 KiB/s
8D-8D-8D, no continuous read:
64 page read speed is 23272 KiB/s
8D-8D-8D, with continuous read:
1 page read speed is 23272 KiB/s
2 page read speed is 23272 KiB/s
3 page read speed is 28000 KiB/s
4 page read speed is 32000 KiB/s
5 page read speed is 34285 KiB/s
6 page read speed is 34285 KiB/s
7 page read speed is 36000 KiB/s
8 page read speed is 36571 KiB/s
9 page read speed is 36000 KiB/s
10 page read speed is 34285 KiB/s
11 page read speed is 36666 KiB/s
12 page read speed is 40000 KiB/s
13 page read speed is 41600 KiB/s
14 page read speed is 37333 KiB/s
15 page read speed is 40000 KiB/s
16 page read speed is 36571 KiB/s
32 page read speed is 42666 KiB/s
64 page read speed is 42666 KiB/s
On the Nuvoton platform, the speed gain is real, even though it is less
impressive:
1 page read speed is 1802 KiB/s
2 page read speed is 1882 KiB/s
3 page read speed is 1938 KiB/s
4 page read speed is 1939 KiB/s
5 page read speed is 1935 KiB/s
6 page read speed is 1967 KiB/s
7 page read speed is 1968 KiB/s
8 page read speed is 1969 KiB/s
9 page read speed is 1968 KiB/s
10 page read speed is 2000 KiB/s
11 page read speed is 2000 KiB/s
12 page read speed is 2000 KiB/s
13 page read speed is 2000 KiB/s
14 page read speed is 2000 KiB/s
15 page read speed is 2000 KiB/s
16 page read speed is 2000 KiB/s
32 page read speed is 2000 KiB/s
64 page read speed is 2000 KiB/s
Thanks!
Miquèl
---
Changes in v3:
- The API change in spi-mem has been applied to all SPI controller drivers
(fixing build failures on drivers I was not building in my test
config).
That is the only change.
- Link to v2: https://lore.kernel.org/r/20260326-winbond-v6-18-rc1-cont-read-v2-0-643de97a68a3@bootlin.com
Changes in v2:
- Rebased on v7.0-rc1.
- Collected tags.
- I manually tested the integrity of the data by manually disabling all
possible variants one after the other using a 2 page read scenario. All
worked except the fastest 8D-8D-8D variant (the first one in the list)
which triggered the CS deassert issue on the Cadence controller. This
issue is orthogonal to this patchset, a follow-up series will be sent
to disable continuous reads on this controller.
- All continuous read variants for the W25NxxJW chips have been tested
on the MA35D1 platform (which lead to several fixes) and the
W35NxxJW chips have been tested on TI AM62a7 LP SK.
- Several changes have been operated in the core to stabilize the
feature when a secondary op is used.
- A couple of helpers have been created to cleanup the winbond.c driver.
- Link to v1: https://lore.kernel.org/r/20251205-winbond-v6-18-rc1-cont-read-v1-0-01bc48631c73@bootlin.com
---
Miquel Raynal (11):
mtd: spinand: Drop a too strong limitation
mtd: spinand: Expose spinand_op_is_odtr()
mtd: spinand: Drop ECC dirmaps
spi: spi-mem: Transform the read operation template
spi: spi-mem: Create a secondary read operation
mtd: spinand: Use secondary ops for continuous reads
mtd: spinand: winbond: Ensure chips are ordered by density
mtd: spinand: winbond: Add support for continuous reads on W35NxxJW
mtd: spinand: winbond: Create a helper to write the HS bit
mtd: spinand: winbond: Create a helper to detect the need for the HS bit
mtd: spinand: winbond: Add support for continuous reads on W25NxxJW
drivers/mtd/nand/spi/core.c | 135 ++++++++++++------
drivers/mtd/nand/spi/winbond.c | 317 ++++++++++++++++++++++++++++++++---------
drivers/mtd/spi-nor/core.c | 22 +--
drivers/spi/spi-airoha-snfi.c | 6 +-
drivers/spi/spi-aspeed-smc.c | 4 +-
drivers/spi/spi-intel.c | 6 +-
drivers/spi/spi-mem.c | 32 ++++-
drivers/spi/spi-mxic.c | 18 +--
drivers/spi/spi-npcm-fiu.c | 16 +--
drivers/spi/spi-rpc-if.c | 8 +-
drivers/spi/spi-stm32-ospi.c | 6 +-
drivers/spi/spi-stm32-qspi.c | 6 +-
drivers/spi/spi-wpcm-fiu.c | 2 +-
include/linux/mtd/spinand.h | 16 ++-
include/linux/spi/spi-mem.h | 8 +-
15 files changed, 435 insertions(+), 167 deletions(-)
---
base-commit: 1e0fe839f8c4bade7b9dc358fb8eef5b2f43af49
change-id: 20251204-winbond-v6-18-rc1-cont-read-664791ddb263
Best regards,
--
Miquel Raynal <miquel.raynal@bootlin.com>
^ permalink raw reply
* Re: [PATCH v13 3/4] gpio: rpmsg: add generic rpmsg GPIO driver
From: Padhi, Beleswar @ 2026-04-29 17:55 UTC (permalink / raw)
To: Shenwei Wang, Mathieu Poirier
Cc: Andrew Lunn, Linus Walleij, Bartosz Golaszewski, Jonathan Corbet,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
Frank Li, Sascha Hauer, Shuah Khan, linux-gpio@vger.kernel.org,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
Pengutronix Kernel Team, Fabio Estevam, Peng Fan,
devicetree@vger.kernel.org, linux-remoteproc@vger.kernel.org,
imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
dl-linux-imx, Bartosz Golaszewski
In-Reply-To: <PAXPR04MB9185F2F6DDB55AC56C92D63B89342@PAXPR04MB9185.eurprd04.prod.outlook.com>
On 4/29/2026 10:23 PM, Shenwei Wang wrote:
>
>> -----Original Message-----
>> From: Mathieu Poirier <mathieu.poirier@linaro.org>
>> Sent: Wednesday, April 29, 2026 10:42 AM
>> To: Shenwei Wang <shenwei.wang@nxp.com>
>> Cc: Andrew Lunn <andrew@lunn.ch>; Padhi, Beleswar <b-padhi@ti.com>; Linus
>> Walleij <linusw@kernel.org>; Bartosz Golaszewski <brgl@kernel.org>; Jonathan
>> Corbet <corbet@lwn.net>; Rob Herring <robh@kernel.org>; Krzysztof Kozlowski
>> <krzk+dt@kernel.org>; Conor Dooley <conor+dt@kernel.org>; Bjorn Andersson
>> <andersson@kernel.org>; Frank Li <frank.li@nxp.com>; Sascha Hauer
>> <s.hauer@pengutronix.de>; Shuah Khan <skhan@linuxfoundation.org>; linux-
>> gpio@vger.kernel.org; linux-doc@vger.kernel.org; linux-kernel@vger.kernel.org;
>> Pengutronix Kernel Team <kernel@pengutronix.de>; Fabio Estevam
>> <festevam@gmail.com>; Peng Fan <peng.fan@nxp.com>;
>> devicetree@vger.kernel.org; linux-remoteproc@vger.kernel.org;
>> imx@lists.linux.dev; linux-arm-kernel@lists.infradead.org; dl-linux-imx <linux-
>> imx@nxp.com>; Bartosz Golaszewski <brgl@bgdev.pl>
>> Subject: [EXT] Re: [PATCH v13 3/4] gpio: rpmsg: add generic rpmsg GPIO driver
>> On Tue, Apr 28, 2026 at 03:24:59PM +0000, Shenwei Wang wrote:
>>>
>>>> -----Original Message-----
>>>> From: Andrew Lunn <andrew@lunn.ch>
>>>> Sent: Monday, April 27, 2026 3:49 PM
>>>> To: Shenwei Wang <shenwei.wang@nxp.com>
>>>> Cc: Padhi, Beleswar <b-padhi@ti.com>; Linus Walleij
>>>> <linusw@kernel.org>; Bartosz Golaszewski <brgl@kernel.org>; Jonathan
>>>> Corbet <corbet@lwn.net>; Rob Herring <robh@kernel.org>; Krzysztof
>>>> Kozlowski <krzk+dt@kernel.org>; Conor Dooley <conor+dt@kernel.org>;
>>>> Bjorn Andersson <andersson@kernel.org>; Mathieu Poirier
>>>> <mathieu.poirier@linaro.org>; Frank Li <frank.li@nxp.com>; Sascha
>>>> Hauer <s.hauer@pengutronix.de>; Shuah Khan
>>>> <skhan@linuxfoundation.org>; linux-gpio@vger.kernel.org; linux-
>>>> doc@vger.kernel.org; linux-kernel@vger.kernel.org; Pengutronix
>>>> Kernel Team <kernel@pengutronix.de>; Fabio Estevam
>>>> <festevam@gmail.com>; Peng Fan <peng.fan@nxp.com>;
>>>> devicetree@vger.kernel.org; linux- remoteproc@vger.kernel.org;
>>>> imx@lists.linux.dev; linux-arm- kernel@lists.infradead.org;
>>>> dl-linux-imx <linux-imx@nxp.com>; Bartosz Golaszewski
>>>> <brgl@bgdev.pl>
>>>> Subject: [EXT] Re: [PATCH v13 3/4] gpio: rpmsg: add generic rpmsg
>>>> GPIO driver
>>>>>> struct virtio_gpio_response {
>>>>>> __u8 status;
>>>>>> __u8 value;
>>>>>> };
>>>>> It is the same message format. Please see the message definition
>>>> (GET_DIRECTION) below:
>>>>
>>>>> + +-----+-----+-----+-----+-----+----+
>>>>> + |0x00 |0x01 |0x02 |0x03 |0x04 |0x05|
>>>>> + | 1 | 2 |port |line | err | dir|
>>>>> + +-----+-----+-----+-----+-----+----+
>>>> Sorry, but i don't see how two u8 vs six u8 are the same message format.
>>>>
>>> Some changes to the message format are necessary.
>>>
>>> Virtio uses two communication channels (virtqueues): one for requests and
>> replies, and a second one for events.
>>> In contrast, rpmsg provides only a single communication channel, so a
>>> type field is required to distinguish between different kinds of messages.
>>>
>>> Since rpmsg replies and events share the same message format, an additional
>> line is introduced to handle both cases.
>>> Finally, rpmsg supports multiple GPIO controllers, so a port field is added to
>> uniquely identify the target controller.
>>
>> I have commented on this before - RPMSG is already providing multiplexing
>> capability by way of endpoints. There is no need for a port field. One endpoint,
>> one GPIO controller.
>>
> You still need a way to let the remote side know which port the endpoint maps to,
About this, we only need to do this because you are defining the gpio
controller instances "statically" in the device tree. I understand gpio
nodes can act as providers, but I do not see any device referencing the
gpio nodes you are defining in the device tree. If that is the case, you
can completely remove the nodes from device tree, and "dynamically"
announce the existence of these nodes from the firmware itself
(similar to what is done for rpmsg-tty currently). In response to that
announce message, Linux could send the "ept" it allocated for the
controller. That way, Linux only cares about "ept" and there is no need
to maintain port 'idx' info anywhere in the Linux side anymore.
Thanks,
Beleswar
^ permalink raw reply
* [PATCH 2/2] irqchip: ti-sci-inta: add runtime PM and system sleep support
From: Rahul Sharma @ 2026-04-29 17:49 UTC (permalink / raw)
To: peter.ujfalusi, vkoul, Frank.Li, nm, kristo, ssantosh, tglx
Cc: linux-arm-kernel, dmaengine, linux-kernel
In-Reply-To: <20260429174904.4049243-1-r-sharma3@ti.com>
Register runtime PM callbacks and enable runtime PM via
devm_pm_runtime_enable() in probe.
runtime_suspend is a no-op; IRQ routing context is preserved by TI SCI
firmware across power-gate cycles.
runtime_resume restores VINT_ENABLE_SET for each active event bit,
skipping IRQs with irqd_irq_masked set to avoid re-enabling
intentionally disabled interrupts.
System sleep reuses these callbacks via pm_runtime_force_suspend/resume
as late/early sleep ops. This ensures MMIO writes in runtime_resume
happen after genpd restores the power domain (dpm_resume_noirq),
avoiding writes to a powered-off device.
Signed-off-by: Rahul Sharma <r-sharma3@ti.com>
---
drivers/irqchip/irq-ti-sci-inta.c | 49 +++++++++++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/drivers/irqchip/irq-ti-sci-inta.c b/drivers/irqchip/irq-ti-sci-inta.c
index f1eb2f92f0ca..0d4451b208c1 100644
--- a/drivers/irqchip/irq-ti-sci-inta.c
+++ b/drivers/irqchip/irq-ti-sci-inta.c
@@ -18,6 +18,7 @@
#include <linux/of.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
#include <linux/irqchip/chained_irq.h>
#include <linux/soc/ti/ti_sci_inta_msi.h>
#include <linux/soc/ti/ti_sci_protocol.h>
@@ -720,11 +721,58 @@ static int ti_sci_inta_irq_domain_probe(struct platform_device *pdev)
INIT_LIST_HEAD(&inta->vint_list);
mutex_init(&inta->vint_mutex);
+ dev_set_drvdata(dev, inta);
+
+ ret = devm_pm_runtime_enable(dev);
+ if (ret)
+ return ret;
+
dev_info(dev, "Interrupt Aggregator domain %d created\n", inta->ti_sci_id);
return 0;
}
+static int ti_sci_inta_runtime_suspend(struct device *dev)
+{
+ return 0;
+}
+
+static int ti_sci_inta_runtime_resume(struct device *dev)
+{
+ struct ti_sci_inta_irq_domain *inta = dev_get_drvdata(dev);
+ struct ti_sci_inta_vint_desc *vint_desc;
+ int bit;
+
+ mutex_lock(&inta->vint_mutex);
+ list_for_each_entry(vint_desc, &inta->vint_list, list) {
+ for_each_set_bit(bit, vint_desc->event_map, MAX_EVENTS_PER_VINT) {
+ unsigned int virq;
+ struct irq_data *data;
+
+ virq = irq_find_mapping(vint_desc->domain,
+ vint_desc->events[bit].hwirq);
+ if (!virq)
+ continue;
+ data = irq_get_irq_data(virq);
+ if (!data || irqd_irq_masked(data))
+ continue;
+ writeq_relaxed(BIT(bit), inta->base +
+ vint_desc->vint_id * 0x1000 +
+ VINT_ENABLE_SET_OFFSET);
+ }
+ }
+ mutex_unlock(&inta->vint_mutex);
+
+ return 0;
+}
+
+static const struct dev_pm_ops ti_sci_inta_pm_ops = {
+ SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+ pm_runtime_force_resume)
+ SET_RUNTIME_PM_OPS(ti_sci_inta_runtime_suspend,
+ ti_sci_inta_runtime_resume, NULL)
+};
+
static const struct of_device_id ti_sci_inta_irq_domain_of_match[] = {
{ .compatible = "ti,sci-inta", },
{ /* sentinel */ },
@@ -736,6 +784,7 @@ static struct platform_driver ti_sci_inta_irq_domain_driver = {
.driver = {
.name = "ti-sci-inta",
.of_match_table = ti_sci_inta_irq_domain_of_match,
+ .pm = pm_ptr(&ti_sci_inta_pm_ops),
},
};
module_platform_driver(ti_sci_inta_irq_domain_driver);
--
2.34.1
^ permalink raw reply related
* [PATCH 0/2] Add runtime PM support to K3 UDMA and K3 INTA
From: Rahul Sharma @ 2026-04-29 17:49 UTC (permalink / raw)
To: peter.ujfalusi, vkoul, Frank.Li, nm, kristo, ssantosh, tglx
Cc: linux-arm-kernel, dmaengine, linux-kernel
This series adds runtime PM support to the TI K3 UDMA DMA engine driver
and the TI SCI Interrupt Aggregator (INTA) irqchip driver on K3 SoCs.
Runtime PM callbacks are registered via SET_RUNTIME_PM_OPS and enabled
in probe via devm_pm_runtime_enable(). System sleep is handled by
delegating to pm_runtime_force_suspend/resume as late/early sleep ops,
keeping the PM runtime state machine consistent across system sleep
transitions and ensuring correct sequencing with power domain restoration
by genpd.
Rahul Sharma (2):
dma: ti: k3-udma: enable runtime PM support
irqchip: ti-sci-inta: add runtime PM and system sleep support
drivers/dma/ti/k3-udma.c | 46 ++++++++++++++++++++++-------
drivers/irqchip/irq-ti-sci-inta.c | 49 +++++++++++++++++++++++++++++++
2 files changed, 85 insertions(+), 10 deletions(-)
--
2.34.1
^ permalink raw reply
* [PATCH 1/2] dma: ti: k3-udma: enable runtime PM support
From: Rahul Sharma @ 2026-04-29 17:49 UTC (permalink / raw)
To: peter.ujfalusi, vkoul, Frank.Li, nm, kristo, ssantosh, tglx
Cc: linux-arm-kernel, dmaengine, linux-kernel
In-Reply-To: <20260429174904.4049243-1-r-sharma3@ti.com>
Rename udma_pm_suspend/resume to udma_runtime_suspend/resume and
register them as runtime PM callbacks via SET_RUNTIME_PM_OPS. Enable
runtime PM in probe via devm_pm_runtime_enable().
System sleep is handled by reusing the same callbacks via
pm_runtime_force_suspend/resume as late/early sleep ops, keeping the
PM runtime state machine consistent across system sleep transitions.
Hold a runtime PM reference for the lifetime of each allocated channel
(acquired in alloc_chan_resources, released in free_chan_resources) to
ensure the device stays powered while DMA is in use.
Signed-off-by: Rahul Sharma <r-sharma3@ti.com>
---
drivers/dma/ti/k3-udma.c | 46 +++++++++++++++++++++++++++++++---------
1 file changed, 36 insertions(+), 10 deletions(-)
diff --git a/drivers/dma/ti/k3-udma.c b/drivers/dma/ti/k3-udma.c
index c964ebfcf3b6..47a4d45f4c09 100644
--- a/drivers/dma/ti/k3-udma.c
+++ b/drivers/dma/ti/k3-udma.c
@@ -28,6 +28,7 @@
#include <linux/soc/ti/ti_sci_inta_msi.h>
#include <linux/dma/k3-event-router.h>
#include <linux/dma/ti-cppi5.h>
+#include <linux/pm_runtime.h>
#include "../virt-dma.h"
#include "k3-udma.h"
@@ -2189,6 +2190,10 @@ static int udma_alloc_chan_resources(struct dma_chan *chan)
u32 irq_udma_idx;
int ret;
+ ret = pm_runtime_resume_and_get(ud->dev);
+ if (ret)
+ return ret;
+
uc->dma_dev = ud->dev;
if (uc->config.pkt_mode || uc->config.dir == DMA_MEM_TO_MEM) {
@@ -2382,6 +2387,7 @@ static int udma_alloc_chan_resources(struct dma_chan *chan)
uc->use_dma_pool = false;
}
+ pm_runtime_put(ud->dev);
return ret;
}
@@ -2393,6 +2399,10 @@ static int bcdma_alloc_chan_resources(struct dma_chan *chan)
u32 irq_udma_idx, irq_ring_idx;
int ret;
+ ret = pm_runtime_resume_and_get(ud->dev);
+ if (ret)
+ return ret;
+
/* Only TR mode is supported */
uc->config.pkt_mode = false;
@@ -2412,7 +2422,7 @@ static int bcdma_alloc_chan_resources(struct dma_chan *chan)
ret = bcdma_alloc_bchan_resources(uc);
if (ret)
- return ret;
+ goto err_res_free;
irq_ring_idx = uc->bchan->id + oes->bcdma_bchan_ring;
irq_udma_idx = uc->bchan->id + oes->bcdma_bchan_data;
@@ -2427,7 +2437,7 @@ static int bcdma_alloc_chan_resources(struct dma_chan *chan)
ret = udma_alloc_tx_resources(uc);
if (ret) {
uc->config.remote_thread_id = -1;
- return ret;
+ goto err_res_free;
}
uc->config.src_thread = ud->psil_base + uc->tchan->id;
@@ -2447,7 +2457,7 @@ static int bcdma_alloc_chan_resources(struct dma_chan *chan)
ret = udma_alloc_rx_resources(uc);
if (ret) {
uc->config.remote_thread_id = -1;
- return ret;
+ goto err_res_free;
}
uc->config.src_thread = uc->config.remote_thread_id;
@@ -2463,7 +2473,8 @@ static int bcdma_alloc_chan_resources(struct dma_chan *chan)
/* Can not happen */
dev_err(uc->ud->dev, "%s: chan%d invalid direction (%u)\n",
__func__, uc->id, uc->config.dir);
- return -EINVAL;
+ ret = -EINVAL;
+ goto err_res_free;
}
/* check if the channel configuration was successful */
@@ -2576,6 +2587,7 @@ static int bcdma_alloc_chan_resources(struct dma_chan *chan)
uc->use_dma_pool = false;
}
+ pm_runtime_put(ud->dev);
return ret;
}
@@ -2605,6 +2617,10 @@ static int pktdma_alloc_chan_resources(struct dma_chan *chan)
u32 irq_ring_idx;
int ret;
+ ret = pm_runtime_resume_and_get(ud->dev);
+ if (ret)
+ return ret;
+
/*
* Make sure that the completion is in a known state:
* No teardown, the channel is idle
@@ -2622,7 +2638,7 @@ static int pktdma_alloc_chan_resources(struct dma_chan *chan)
ret = udma_alloc_tx_resources(uc);
if (ret) {
uc->config.remote_thread_id = -1;
- return ret;
+ goto err_res_free;
}
uc->config.src_thread = ud->psil_base + uc->tchan->id;
@@ -2641,7 +2657,7 @@ static int pktdma_alloc_chan_resources(struct dma_chan *chan)
ret = udma_alloc_rx_resources(uc);
if (ret) {
uc->config.remote_thread_id = -1;
- return ret;
+ goto err_res_free;
}
uc->config.src_thread = uc->config.remote_thread_id;
@@ -2656,7 +2672,8 @@ static int pktdma_alloc_chan_resources(struct dma_chan *chan)
/* Can not happen */
dev_err(uc->ud->dev, "%s: chan%d invalid direction (%u)\n",
__func__, uc->id, uc->config.dir);
- return -EINVAL;
+ ret = -EINVAL;
+ goto err_res_free;
}
/* check if the channel configuration was successful */
@@ -2745,6 +2762,7 @@ static int pktdma_alloc_chan_resources(struct dma_chan *chan)
dma_pool_destroy(uc->hdesc_pool);
uc->use_dma_pool = false;
+ pm_runtime_put(ud->dev);
return ret;
}
@@ -4123,6 +4141,8 @@ static void udma_free_chan_resources(struct dma_chan *chan)
dma_pool_destroy(uc->hdesc_pool);
uc->use_dma_pool = false;
}
+
+ pm_runtime_put(ud->dev);
}
static struct platform_driver udma_driver;
@@ -5644,6 +5664,11 @@ static int udma_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, ud);
+ /* Enable runtime PM */
+ ret = devm_pm_runtime_enable(dev);
+ if (ret)
+ return ret;
+
ret = of_dma_controller_register(dev->of_node, udma_of_xlate, ud);
if (ret) {
dev_err(dev, "failed to register of_dma controller\n");
@@ -5653,7 +5678,7 @@ static int udma_probe(struct platform_device *pdev)
return ret;
}
-static int __maybe_unused udma_pm_suspend(struct device *dev)
+static int udma_runtime_suspend(struct device *dev)
{
struct udma_dev *ud = dev_get_drvdata(dev);
struct dma_device *dma_dev = &ud->ddev;
@@ -5675,7 +5700,7 @@ static int __maybe_unused udma_pm_suspend(struct device *dev)
return 0;
}
-static int __maybe_unused udma_pm_resume(struct device *dev)
+static int udma_runtime_resume(struct device *dev)
{
struct udma_dev *ud = dev_get_drvdata(dev);
struct dma_device *dma_dev = &ud->ddev;
@@ -5701,7 +5726,8 @@ static int __maybe_unused udma_pm_resume(struct device *dev)
}
static const struct dev_pm_ops udma_pm_ops = {
- SET_LATE_SYSTEM_SLEEP_PM_OPS(udma_pm_suspend, udma_pm_resume)
+ SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
+ SET_RUNTIME_PM_OPS(udma_runtime_suspend, udma_runtime_resume, NULL)
};
static struct platform_driver udma_driver = {
--
2.34.1
^ permalink raw reply related
* Re: [RFC PATCH] mmc: host: sdhci-iproc: implement the .hw_reset callback
From: Meagan Lloyd @ 2026-04-29 17:46 UTC (permalink / raw)
To: Florian Fainelli, Scott Branden
Cc: rjui, sbranden, linux-arm-kernel, tgopinath, adrian.hunter,
linux-mmc, kernel-list
In-Reply-To: <e1ba9b6d-0ad8-4336-a5f9-ad4777ef54e0@broadcom.com>
On 4/15/2026 1:44 PM, Florian Fainelli wrote:
> On 4/15/26 13:43, Meagan Lloyd wrote:
>>
>> On 4/15/2026 1:23 PM, Scott Branden wrote:
>>> Hi Meagan,
>>>
>>> On Wed, Apr 15, 2026 at 11:08 AM Meagan Lloyd <
>>> meaganlloyd@linux.microsoft.com> wrote:
>>>
>>>> On 4/13/2026 10:43 AM, Florian Fainelli wrote:
>>>>> On 4/13/26 10:38, Meagan Lloyd wrote:
>>>>>> On 3/27/2026 3:21 PM, Meagan Lloyd wrote:
>>>>>>> Implement the .hw_reset callback so that the eMMC can be reset as
>>>>>>> needed
>>>>>>> given cap-mmc-hw-reset is set in the devicetree and the
>>>>>>> functionality is
>>>>>>> enabled on the eMMC.
>>>>>>>
>>>>>>> Signed-off-by: Meagan Lloyd <meaganlloyd@linux.microsoft.com>
>>>>>>> ---
>>>>>>>
>>>>>>> SDHCI_POWER_CONTROL[4] (SD Host Controller Standard) has been
>>>>>>> repurposed
>>>>>>> on my Broadcomm processor to be eMMC hardware reset
>>>>>>> (SDIO*_eMMCSDXC_CTRL[12], HRESET).
>>>>>>>
>>>>>>> Can you confirm this repurposed bit is consistent across the
>>>>>>> Broadcomm
>>>>>>> iProc processors and thus the .hw_reset callback can be uniformly
>>>>>>> applied in this driver?
>>>>>> Hi Ray & Scott,
>>>>>>
>>>>>> I hope you're doing well. This bit looks to have been repurposed
>>>>>> from
>>>>>> the SD Host Controller Standard's VDD2 Power Control to being
>>>>>> used for
>>>>>> toggling the hardware reset signal to eMMCs. Can you verify that it
>>>>>> applies across the iProc processors so that I may finalize this
>>>>>> patch?
>>>>> Which iProc process are you using? If you are not sure this applies
>>>>> broadly, can you at least make it specific to the SoC you are using?
>>>> Yes, if it comes to that I can. I think it's overkill to roll a new
>>>> compat string/associated structures over this small change, hence
>>>> checking with Broadcomm iProc maintainers on this thread.
>>>>
>>> Which iProc processor are you using? You will have to check with
>>> RaspberryPI as I think they use this driver as well.
>>> If that family also supports it then you probably don't need a
>>> compatibility string.
>>
>> The processor I am using is the BCM58732. Can you help direct me to
>> someone who could comment from the RaspberryPi side?
>>
>
> I will take care of that.
Thanks, Florian. Let me know what you find out :)
^ permalink raw reply
* Re: [PATCH v4 13/15] arm64: mm: Unmap kernel data/bss entirely from the linear map
From: Ard Biesheuvel @ 2026-04-29 17:37 UTC (permalink / raw)
To: Kevin Brodsky, Ard Biesheuvel, linux-arm-kernel
Cc: linux-kernel, Will Deacon, Catalin Marinas, Mark Rutland,
Ryan Roberts, Anshuman Khandual, Liz Prucka, Seth Jenkins,
Kees Cook, Mike Rapoport, David Hildenbrand, Andrew Morton,
linux-mm, linux-hardening
In-Reply-To: <15555e9f-65ab-4811-b20c-8ada90bdc9d0@arm.com>
On Wed, 29 Apr 2026, at 15:55, Kevin Brodsky wrote:
> On 27/04/2026 17:34, Ard Biesheuvel wrote:
>> From: Ard Biesheuvel <ardb@kernel.org>
>>
>> The linear aliases of the kernel text and rodata are mapped read-only in
>> the linear map as well. Given that the contents of these regions are
>> mostly identical to the version in the loadable image, mapping them
>> read-only and leaving their contents visible is a reasonable hardening
>> measure.
>>
>> Data and bss, however, are now also mapped read-only but the contents of
>> these regions are more likely to contain data that we'd rather not leak.
>
> That sounds like a good rationale but I wonder, is there anything
> stopping us from unmapping text/rodata as well?
>
There is the zero page now, which may be accessed via
'page_address(ZERO_PAGE(0))'. Also, anything that dereferences page tables
(like /sys/kernel/debug/kernel_page_tables) will expect to have read-only
access to swapper_pg_dir.
>> So let's unmap these entirely in the linear map when the kernel is
>> running normally.
>>
>> When going into hibernation or waking up from it, these regions need to
>> be mapped, so map the region initially, and toggle the valid bit so
>> map/unmap the region as needed.
>
> Doesn't safe_copy_page() already handle that? I suppose this is an
> optimisation to avoid modifying the linear map for every page, but if so
> it would be good to spell it out.
>
Uhm, good question.
When hibernate was first implemented for arm64, we had to bring back the
linear alias of the kernel image, and when I started working on this, I
hadn't realised that we have safe_copy_page() now which should take care
of this even if the linear alias is invalid.
However, if I remove this handling, things breaks mysteriously, and it
is a bit tricky to debug so it may take me some time to answer this
question. In any case, I will address this in the next revision, and
put you on cc.
>> Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
>> ---
>> arch/arm64/mm/mmu.c | 44 ++++++++++++++++----
>> 1 file changed, 37 insertions(+), 7 deletions(-)
>>
>> diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
>> index 9361b7efb848..a464f3d2d2df 100644
>> --- a/arch/arm64/mm/mmu.c
>> +++ b/arch/arm64/mm/mmu.c
>> @@ -24,6 +24,7 @@
>> #include <linux/mm.h>
>> #include <linux/vmalloc.h>
>> #include <linux/set_memory.h>
>> +#include <linux/suspend.h>
>> #include <linux/kfence.h>
>> #include <linux/pkeys.h>
>> #include <linux/mm_inline.h>
>> @@ -1040,6 +1041,31 @@ static void __init __map_memblock(phys_addr_t start, phys_addr_t end,
>> end - start, prot, early_pgtable_alloc, flags);
>> }
>>
>> +static void remap_linear_data_alias(bool unmap)
>> +{
>> + set_memory_valid((unsigned long)lm_alias(__init_end),
>> + (unsigned long)(__fixmap_pgdir_start - __init_end) / PAGE_SIZE,
>> + !unmap);
>> +}
>> +
>> +static int arm64_hibernate_pm_notify(struct notifier_block *nb,
>> + unsigned long mode, void *unused)
>> +{
>> + switch (mode) {
>> + default:
>> + break;
>> + case PM_POST_HIBERNATION:
>> + case PM_POST_RESTORE:
>> + remap_linear_data_alias(true);
>> + break;
>> + case PM_HIBERNATION_PREPARE:
>> + case PM_RESTORE_PREPARE:
>> + remap_linear_data_alias(false);
>> + break;
>> + }
>> + return 0;
>> +}
>> +
>> void __init mark_linear_text_alias_ro(void)
>> {
>> /*
>> @@ -1048,6 +1074,16 @@ void __init mark_linear_text_alias_ro(void)
>> update_mapping_prot(__pa_symbol(_text), (unsigned long)lm_alias(_text),
>> (unsigned long)__init_begin - (unsigned long)_text,
>> pgprot_tagged(PAGE_KERNEL_RO));
>> +
>> + remap_linear_data_alias(true);
>
> It's really hard to know what this does without looking at the function.
> How about mark_linear_data_alias_valid(false)?
>
Sure.
>> +
>> + if (IS_ENABLED(CONFIG_HIBERNATION)) {
>> + static struct notifier_block nb = {
>> + .notifier_call = arm64_hibernate_pm_notify
>> + };
>> +
>> + register_pm_notifier(&nb);
>> + }
>> }
>>
>> #ifdef CONFIG_KFENCE
>> @@ -1162,7 +1198,7 @@ static void __init map_mem(void)
>>
>> /* Map the kernel data/bss so it can be remapped later */
>> __map_memblock(init_end, kernel_end, pgprot_tagged(PAGE_KERNEL),
>> - flags);
>> + flags | NO_BLOCK_MAPPINGS);
>
> Might be an obvious question but why do we need this?
>
set_memory_valid() only works on regions that are mapped down to pages.
^ permalink raw reply
* Re: [PATCH v13 3/4] gpio: rpmsg: add generic rpmsg GPIO driver
From: Mathieu Poirier @ 2026-04-29 17:33 UTC (permalink / raw)
To: Shenwei Wang
Cc: Andrew Lunn, Padhi, Beleswar, Linus Walleij, Bartosz Golaszewski,
Jonathan Corbet, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Frank Li, Sascha Hauer, Shuah Khan,
linux-gpio@vger.kernel.org, linux-doc@vger.kernel.org,
linux-kernel@vger.kernel.org, Pengutronix Kernel Team,
Fabio Estevam, Peng Fan, devicetree@vger.kernel.org,
linux-remoteproc@vger.kernel.org, imx@lists.linux.dev,
linux-arm-kernel@lists.infradead.org, dl-linux-imx,
Bartosz Golaszewski
In-Reply-To: <PAXPR04MB9185F2F6DDB55AC56C92D63B89342@PAXPR04MB9185.eurprd04.prod.outlook.com>
On Wed, 29 Apr 2026 at 10:53, Shenwei Wang <shenwei.wang@nxp.com> wrote:
>
>
>
> > -----Original Message-----
> > From: Mathieu Poirier <mathieu.poirier@linaro.org>
> > Sent: Wednesday, April 29, 2026 10:42 AM
> > To: Shenwei Wang <shenwei.wang@nxp.com>
> > Cc: Andrew Lunn <andrew@lunn.ch>; Padhi, Beleswar <b-padhi@ti.com>; Linus
> > Walleij <linusw@kernel.org>; Bartosz Golaszewski <brgl@kernel.org>; Jonathan
> > Corbet <corbet@lwn.net>; Rob Herring <robh@kernel.org>; Krzysztof Kozlowski
> > <krzk+dt@kernel.org>; Conor Dooley <conor+dt@kernel.org>; Bjorn Andersson
> > <andersson@kernel.org>; Frank Li <frank.li@nxp.com>; Sascha Hauer
> > <s.hauer@pengutronix.de>; Shuah Khan <skhan@linuxfoundation.org>; linux-
> > gpio@vger.kernel.org; linux-doc@vger.kernel.org; linux-kernel@vger.kernel.org;
> > Pengutronix Kernel Team <kernel@pengutronix.de>; Fabio Estevam
> > <festevam@gmail.com>; Peng Fan <peng.fan@nxp.com>;
> > devicetree@vger.kernel.org; linux-remoteproc@vger.kernel.org;
> > imx@lists.linux.dev; linux-arm-kernel@lists.infradead.org; dl-linux-imx <linux-
> > imx@nxp.com>; Bartosz Golaszewski <brgl@bgdev.pl>
> > Subject: [EXT] Re: [PATCH v13 3/4] gpio: rpmsg: add generic rpmsg GPIO driver
> > On Tue, Apr 28, 2026 at 03:24:59PM +0000, Shenwei Wang wrote:
> > >
> > >
> > > > -----Original Message-----
> > > > From: Andrew Lunn <andrew@lunn.ch>
> > > > Sent: Monday, April 27, 2026 3:49 PM
> > > > To: Shenwei Wang <shenwei.wang@nxp.com>
> > > > Cc: Padhi, Beleswar <b-padhi@ti.com>; Linus Walleij
> > > > <linusw@kernel.org>; Bartosz Golaszewski <brgl@kernel.org>; Jonathan
> > > > Corbet <corbet@lwn.net>; Rob Herring <robh@kernel.org>; Krzysztof
> > > > Kozlowski <krzk+dt@kernel.org>; Conor Dooley <conor+dt@kernel.org>;
> > > > Bjorn Andersson <andersson@kernel.org>; Mathieu Poirier
> > > > <mathieu.poirier@linaro.org>; Frank Li <frank.li@nxp.com>; Sascha
> > > > Hauer <s.hauer@pengutronix.de>; Shuah Khan
> > > > <skhan@linuxfoundation.org>; linux-gpio@vger.kernel.org; linux-
> > > > doc@vger.kernel.org; linux-kernel@vger.kernel.org; Pengutronix
> > > > Kernel Team <kernel@pengutronix.de>; Fabio Estevam
> > > > <festevam@gmail.com>; Peng Fan <peng.fan@nxp.com>;
> > > > devicetree@vger.kernel.org; linux- remoteproc@vger.kernel.org;
> > > > imx@lists.linux.dev; linux-arm- kernel@lists.infradead.org;
> > > > dl-linux-imx <linux-imx@nxp.com>; Bartosz Golaszewski
> > > > <brgl@bgdev.pl>
> > > > Subject: [EXT] Re: [PATCH v13 3/4] gpio: rpmsg: add generic rpmsg
> > > > GPIO driver
> > > > > > struct virtio_gpio_response {
> > > > > > __u8 status;
> > > > > > __u8 value;
> > > > > > };
> > > >
> > > > > It is the same message format. Please see the message definition
> > > > (GET_DIRECTION) below:
> > > >
> > > > > + +-----+-----+-----+-----+-----+----+
> > > > > + |0x00 |0x01 |0x02 |0x03 |0x04 |0x05|
> > > > > + | 1 | 2 |port |line | err | dir|
> > > > > + +-----+-----+-----+-----+-----+----+
> > > >
> > > > Sorry, but i don't see how two u8 vs six u8 are the same message format.
> > > >
> > >
> > > Some changes to the message format are necessary.
> > >
> > > Virtio uses two communication channels (virtqueues): one for requests and
> > replies, and a second one for events.
> > > In contrast, rpmsg provides only a single communication channel, so a
> > > type field is required to distinguish between different kinds of messages.
> > >
> > > Since rpmsg replies and events share the same message format, an additional
> > line is introduced to handle both cases.
> > >
> > > Finally, rpmsg supports multiple GPIO controllers, so a port field is added to
> > uniquely identify the target controller.
> >
> > I have commented on this before - RPMSG is already providing multiplexing
> > capability by way of endpoints. There is no need for a port field. One endpoint,
> > one GPIO controller.
> >
>
> You still need a way to let the remote side know which port the endpoint maps to, either
> by embedding the port information in the message (the current way), or by sending it
> separately.
>
An endpoint is created with every namespace request. There should be
one namespace request for every GPIO controller, which yields a unique
endpoint for each controller and eliminates the need for an extra
field to identify them.
> Shenwei
>
> > >
> > > Shenwei
> > >
> > > > Andrew
^ permalink raw reply
* [PATCH v3 0/4] usb: dwc3: xilinx: Add Versal2 MMI USB 3.2 controller support
From: Radhey Shyam Pandey @ 2026-04-29 17:30 UTC (permalink / raw)
To: gregkh, robh, krzk+dt, conor+dt, michal.simek, Thinh.Nguyen,
p.zabel
Cc: linux-usb, devicetree, linux-arm-kernel, linux-kernel, git,
Radhey Shyam Pandey
This series introduces support for the Multimedia Integrated (MMI) USB
3.2 Dual-Role Device (DRD) controller on Xilinx Versal2 platforms.
The controller supports SSP(10-Gbps), SuperSpeed, high-speed, full-speed
and low-speed operation modes.
USB2 and USB3 PHY support Physical connectivity via the Type-C
connectivity. DWC3 wrapper IP IO space is in SLCR so reg is made
optional.
The driver is required for the clock, reset and platform specific
initialization (coherency/TX_DEEMPH etc). In this initial version typec
reversibility is not implemented and it is assumed that USB3 PHY TCA mux
programming is done by MMI configuration data object (CDOs) and TI PD
controller is configured using external tiva programmer on VEK385
evaluation board.
Changes for v3:
- Return -ENODEV from probe if device_get_match_data() is NULL.
- Replace map_resource with no_mem_map (Versal2 MMI only; others default
MMIO map).
- Add PHY warm-reset assert delay.
- Loop all num_usb3_ports with one de-emphasis value.
- Set default as DWC3_LCSR_TX_DEEMPH_UNSPECIFIED default and only set
snps,lcsr-tx-deemph when not unspecified.
Changes for v2:
- DT binding: fix MHz spacing (SI convention), reorder description
before $ref in xlnx,usb-syscon, restore zynqmp-dwc3 example and add
versal2-mmi-dwc3 example, fix node name for no-reg case, use 1/1
address/size configuration and lowercase hex in syscon offsets.
- Split config struct refactoring (device_get_match_data,dwc3_xlnx_config)
into a separate preparatory patch.
- Fix error message capitalization to lowercase per kernel convention.
- Rename property snps,lcsr_tx_deemph to snps,lcsr-tx-deemph (hyphens).
- Fix double space in comment and missing blank line in core.h.
- Use platform data instead of of_device_is_compatible() check for
deemphasis support.
Link: https://lore.kernel.org/all/20251119193036.2666877-1-radhey.shyam.pandey@amd.com/ [v1]
Radhey Shyam Pandey (4):
dt-bindings: usb: dwc3-xilinx: Add MMI USB support on Versal Gen2
platform
usb: dwc3: xilinx: Introduce dwc3_xlnx_config for per-platform data
usb: dwc3: xilinx: Add Versal2 MMI USB 3.2 controller support
usb: dwc3: xilinx: Add support to program MMI USB TX deemphasis
.../devicetree/bindings/usb/dwc3-xilinx.yaml | 70 +++++++++++-
drivers/usb/dwc3/core.c | 24 ++++
drivers/usb/dwc3/core.h | 14 +++
drivers/usb/dwc3/dwc3-xilinx.c | 103 +++++++++++++++---
4 files changed, 193 insertions(+), 18 deletions(-)
base-commit: 3b3bea6d4b9c162f9e555905d96b8c1da67ecd5b
--
2.43.0
^ permalink raw reply
* [PATCH v3 2/4] usb: dwc3: xilinx: Introduce dwc3_xlnx_config for per-platform data
From: Radhey Shyam Pandey @ 2026-04-29 17:30 UTC (permalink / raw)
To: gregkh, robh, krzk+dt, conor+dt, michal.simek, Thinh.Nguyen,
p.zabel
Cc: linux-usb, devicetree, linux-arm-kernel, linux-kernel, git,
Radhey Shyam Pandey
In-Reply-To: <20260429173050.1772377-1-radhey.shyam.pandey@amd.com>
Replace the direct pltfm_init function pointer in struct dwc3_xlnx with
a const pointer to a new struct dwc3_xlnx_config. This groups
per-platform configuration in one place and allows future patches to add
platform-specific fields (e.g. tx_deemph) without growing dwc3_xlnx.
While at it, switch from of_match_node() to device_get_match_data() to
simplify the match data lookup.
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
---
Changes for v3:
- Add check if dwc3_config exists.
Changes for v2:
- New patch, split from "Add Versal2 MMI USB 3.2 controller support".
- Use device_get_match_data() instead of of_match_node().
---
drivers/usb/dwc3/dwc3-xilinx.c | 31 +++++++++++++++++++++++--------
1 file changed, 23 insertions(+), 8 deletions(-)
diff --git a/drivers/usb/dwc3/dwc3-xilinx.c b/drivers/usb/dwc3/dwc3-xilinx.c
index f41b0da5e89d..af0ccd060c8b 100644
--- a/drivers/usb/dwc3/dwc3-xilinx.c
+++ b/drivers/usb/dwc3/dwc3-xilinx.c
@@ -12,6 +12,7 @@
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/platform_device.h>
+#include <linux/property.h>
#include <linux/dma-mapping.h>
#include <linux/gpio/consumer.h>
#include <linux/of_platform.h>
@@ -41,12 +42,18 @@
#define XLNX_USB_FPD_POWER_PRSNT 0x80
#define FPD_POWER_PRSNT_OPTION BIT(0)
+struct dwc3_xlnx;
+
+struct dwc3_xlnx_config {
+ int (*pltfm_init)(struct dwc3_xlnx *data);
+};
+
struct dwc3_xlnx {
int num_clocks;
struct clk_bulk_data *clks;
struct device *dev;
void __iomem *regs;
- int (*pltfm_init)(struct dwc3_xlnx *data);
+ const struct dwc3_xlnx_config *dwc3_config;
struct phy *usb3_phy;
};
@@ -241,14 +248,22 @@ static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx *priv_data)
return ret;
}
+static const struct dwc3_xlnx_config zynqmp_config = {
+ .pltfm_init = dwc3_xlnx_init_zynqmp,
+};
+
+static const struct dwc3_xlnx_config versal_config = {
+ .pltfm_init = dwc3_xlnx_init_versal,
+};
+
static const struct of_device_id dwc3_xlnx_of_match[] = {
{
.compatible = "xlnx,zynqmp-dwc3",
- .data = &dwc3_xlnx_init_zynqmp,
+ .data = &zynqmp_config,
},
{
.compatible = "xlnx,versal-dwc3",
- .data = &dwc3_xlnx_init_versal,
+ .data = &versal_config,
},
{ /* Sentinel */ }
};
@@ -284,7 +299,6 @@ static int dwc3_xlnx_probe(struct platform_device *pdev)
struct dwc3_xlnx *priv_data;
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
- const struct of_device_id *match;
void __iomem *regs;
int ret;
@@ -296,9 +310,10 @@ static int dwc3_xlnx_probe(struct platform_device *pdev)
if (IS_ERR(regs))
return dev_err_probe(dev, PTR_ERR(regs), "failed to map registers\n");
- match = of_match_node(dwc3_xlnx_of_match, pdev->dev.of_node);
-
- priv_data->pltfm_init = match->data;
+ priv_data->dwc3_config = device_get_match_data(dev);
+ if (!priv_data->dwc3_config)
+ return dev_err_probe(dev, -ENODEV,
+ "missing dwc3 platform configuration\n");
priv_data->regs = regs;
priv_data->dev = dev;
@@ -314,7 +329,7 @@ static int dwc3_xlnx_probe(struct platform_device *pdev)
if (ret)
return ret;
- ret = priv_data->pltfm_init(priv_data);
+ ret = priv_data->dwc3_config->pltfm_init(priv_data);
if (ret)
goto err_clk_put;
--
2.43.0
^ permalink raw reply related
* [PATCH v3 1/4] dt-bindings: usb: dwc3-xilinx: Add MMI USB support on Versal Gen2 platform
From: Radhey Shyam Pandey @ 2026-04-29 17:30 UTC (permalink / raw)
To: gregkh, robh, krzk+dt, conor+dt, michal.simek, Thinh.Nguyen,
p.zabel
Cc: linux-usb, devicetree, linux-arm-kernel, linux-kernel, git,
Radhey Shyam Pandey
In-Reply-To: <20260429173050.1772377-1-radhey.shyam.pandey@amd.com>
The Versal Gen2 platform includes two distinct USB controllers. The
versal2-dwc3 device represents a standalone USB 2.0 controller, while
versal2-mmi-dwc3 represents the Multimedia Integrated (MMI) USB 3.2
Gen 2x1 Dual-Role (DRD) controller. The MMI controller natively supports
USB 3.2 host and device operation over type-c, operating in a Gen2x1
configuration with a maximum data rate of 10 Gbps per direction.
Introduce a new compatibility string in <vendor>,<soc>-<subsystem>-<ip>
format to uniquely distinguish the MMI USB controller. The USB wrapper
registers reside in the MMI UDH system-level control registers (SLCR)
block, so instead of a dedicated reg property, add xlnx,usb-syscon
phandle with four cells specifying register offsets for USB2 PHY, USB3
PHY, USB DRD, and USB power configuration within the SLCR.
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
---
Changes for v3:
- Modify commit description to explain that there are two different
USB controllers and difference between versal2-dwc3 and
versal2-mmi-dwc3. Suggested by Krzysztof.
Changes for v2:
- Add blank line after compatible as suggested by Krzysztof.
- Retain the mmi suffix in the compatible string, as this USB 3.2 Gen2
IP from Synopsys is part of the dedicated Multimedia Interface. The
Versal Gen2 platform also includes a separate USB 2.0 controller,
and the mmi suffix uniquely distinguishes between the two USB
controllers. MMI is an independent subsystem particularly targeted for
deployment in Multi-Media related applications. The MMI block include
following submodules: UDH: USB3.2 Gen 2x1 Dual Role Device, DisplayPort
Transmit Controller, Security Module (ESM) for DisplayPort and HDMI
Controllers, DP AUX-I2C PHY.
- For MMI USB define parent address space i.e UDH block.
- Fix inconsistent MHz spacing to use SI convention with spaces.
- Move description before $ref and items in xlnx,usb-syscon property.
- Restore original zynqmp-dwc3 example, add new versal2-mmi-dwc3 example.
- Use 'usb' node name (without unit address) for versal2 example since
it has no reg property.
- Use 1/1 address/size configuration in versal2 example, use lowercase
hex in syscon offsets.
---
.../devicetree/bindings/usb/dwc3-xilinx.yaml | 70 ++++++++++++++++++-
1 file changed, 67 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml
index d6823ef5f9a7..5e31b961aff7 100644
--- a/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml
+++ b/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml
@@ -15,6 +15,8 @@ properties:
- enum:
- xlnx,zynqmp-dwc3
- xlnx,versal-dwc3
+ - xlnx,versal2-mmi-dwc3
+
reg:
maxItems: 1
@@ -37,8 +39,9 @@ properties:
A list of phandle and clock-specifier pairs for the clocks
listed in clock-names.
items:
- - description: Master/Core clock, has to be >= 125 MHz
- for SS operation and >= 60MHz for HS operation.
+ - description: Master/Core clock, has to be >= 156.25 MHz in SSP
+ mode, >= 125 MHz for SS operation and >= 60 MHz for HS
+ operation.
- description: Clock source to core during PHY power down.
clock-names:
@@ -79,6 +82,20 @@ properties:
description: GPIO used for the reset ulpi-phy
maxItems: 1
+ xlnx,usb-syscon:
+ description:
+ Phandle to the MMI UDH system-level control register (SLCR) syscon
+ node, with four cells specifying the register offsets for USB2 PHY,
+ USB3 PHY, USB DRD, and USB power configuration respectively.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to MMI UDH SLCR syscon node
+ - description: USB2 PHY register offset within SLCR
+ - description: USB3 PHY register offset within SLCR
+ - description: USB DRD register offset within SLCR
+ - description: USB power register offset within SLCR
+
# Required child node:
patternProperties:
@@ -87,7 +104,6 @@ patternProperties:
required:
- compatible
- - reg
- "#address-cells"
- "#size-cells"
- ranges
@@ -104,6 +120,7 @@ allOf:
contains:
enum:
- xlnx,versal-dwc3
+ - xlnx,versal2-mmi-dwc3
then:
properties:
resets:
@@ -117,6 +134,26 @@ allOf:
reset-names:
minItems: 3
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - xlnx,zynqmp-dwc3
+ - xlnx,versal-dwc3
+ then:
+ required:
+ - reg
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: xlnx,versal2-mmi-dwc3
+ then:
+ required:
+ - xlnx,usb-syscon
+
additionalProperties: false
examples:
@@ -156,3 +193,30 @@ examples:
};
};
};
+ - |
+ #include <dt-bindings/power/xlnx-zynqmp-power.h>
+ #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
+ #include <dt-bindings/phy/phy.h>
+ usb {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "xlnx,versal2-mmi-dwc3";
+ clocks = <&zynqmp_clk 32>, <&zynqmp_clk 34>;
+ clock-names = "bus_clk", "ref_clk";
+ power-domains = <&zynqmp_firmware PD_USB_0>;
+ resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>;
+ reset-names = "usb_crst";
+ phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
+ phy-names = "usb3-phy";
+ xlnx,usb-syscon = <&udh_slcr 0x005c 0x0070 0x00c4 0x00f8>;
+ ranges;
+
+ usb@fe200000 {
+ compatible = "snps,dwc3";
+ reg = <0xfe200000 0x40000>;
+ interrupt-names = "host", "otg";
+ interrupts = <0 65 4>, <0 69 4>;
+ dr_mode = "host";
+ dma-coherent;
+ };
+ };
--
2.43.0
^ permalink raw reply related
* [PATCH v3 3/4] usb: dwc3: xilinx: Add Versal2 MMI USB 3.2 controller support
From: Radhey Shyam Pandey @ 2026-04-29 17:30 UTC (permalink / raw)
To: gregkh, robh, krzk+dt, conor+dt, michal.simek, Thinh.Nguyen,
p.zabel
Cc: linux-usb, devicetree, linux-arm-kernel, linux-kernel, git,
Radhey Shyam Pandey
In-Reply-To: <20260429173050.1772377-1-radhey.shyam.pandey@amd.com>
Multimedia integrated (MMI) USB3.2 DRD IP is usb3.1 gen2 controller
which support following speed SSP (10-Gbps), SuperSpeed(5-Gbps),
high-speed(480-Mbps), full-speed(12-Mbps), and low-speed(1.5-Mbps)
operation modes.
USB2 and USB3 PHY support physical connectivity via the Type-C
connectivity. The MMI USB controller does not have a dedicated wrapper
register space, so ioremap is skipped via the config flag.
The driver handles clock and reset initialization. In this initial
version typec reversibility is not implemented and it is assumed that
USB3 PHY TCA mux programming is done by MMI configuration data object
(CDOs) and TI PD controller is configured using external tiva programmer
on VEK385 evaluation board.
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
---
Changes for v3:
- Remove mention of xlnx,usb-syscon phandle from version history.
- Rename map_resource to no_mem_map.
- Add assert delay.
- Rephrase commit description.
Changes for v2:
- Split config struct refactoring into separate patch (2/4).
- Remove unused regmap/syscon fields and parsing code; defer to
patch that first consumes them.
- Fix error message capitalization to lowercase ("reset", "deassert").
---
drivers/usb/dwc3/dwc3-xilinx.c | 56 ++++++++++++++++++++++++++++++----
1 file changed, 50 insertions(+), 6 deletions(-)
diff --git a/drivers/usb/dwc3/dwc3-xilinx.c b/drivers/usb/dwc3/dwc3-xilinx.c
index af0ccd060c8b..b601cca485ed 100644
--- a/drivers/usb/dwc3/dwc3-xilinx.c
+++ b/drivers/usb/dwc3/dwc3-xilinx.c
@@ -46,6 +46,7 @@ struct dwc3_xlnx;
struct dwc3_xlnx_config {
int (*pltfm_init)(struct dwc3_xlnx *data);
+ bool no_mem_map;
};
struct dwc3_xlnx {
@@ -93,6 +94,35 @@ static void dwc3_xlnx_set_coherency(struct dwc3_xlnx *priv_data, u32 coherency_o
}
}
+static int dwc3_xlnx_init_versal2(struct dwc3_xlnx *priv_data)
+{
+ struct device *dev = priv_data->dev;
+ struct reset_control *crst;
+ int ret;
+
+ crst = devm_reset_control_get_optional_exclusive(dev, NULL);
+ if (IS_ERR(crst))
+ return dev_err_probe(dev, PTR_ERR(crst),
+ "failed to get reset signal\n");
+
+ /* assert and deassert reset */
+ ret = reset_control_assert(crst);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "failed to assert reset\n");
+
+ /*
+ * PHY databook requires >= 10 ns warm reset assert time; 1 us provides
+ * safe margin for bus latency variations.
+ */
+ udelay(1);
+
+ ret = reset_control_deassert(crst);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "failed to deassert reset\n");
+
+ return 0;
+}
+
static int dwc3_xlnx_init_versal(struct dwc3_xlnx *priv_data)
{
struct device *dev = priv_data->dev;
@@ -256,6 +286,11 @@ static const struct dwc3_xlnx_config versal_config = {
.pltfm_init = dwc3_xlnx_init_versal,
};
+static const struct dwc3_xlnx_config versal2_config = {
+ .pltfm_init = dwc3_xlnx_init_versal2,
+ .no_mem_map = true,
+};
+
static const struct of_device_id dwc3_xlnx_of_match[] = {
{
.compatible = "xlnx,zynqmp-dwc3",
@@ -265,6 +300,10 @@ static const struct of_device_id dwc3_xlnx_of_match[] = {
.compatible = "xlnx,versal-dwc3",
.data = &versal_config,
},
+ {
+ .compatible = "xlnx,versal2-mmi-dwc3",
+ .data = &versal2_config,
+ },
{ /* Sentinel */ }
};
MODULE_DEVICE_TABLE(of, dwc3_xlnx_of_match);
@@ -299,22 +338,27 @@ static int dwc3_xlnx_probe(struct platform_device *pdev)
struct dwc3_xlnx *priv_data;
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
- void __iomem *regs;
int ret;
priv_data = devm_kzalloc(dev, sizeof(*priv_data), GFP_KERNEL);
if (!priv_data)
return -ENOMEM;
- regs = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(regs))
- return dev_err_probe(dev, PTR_ERR(regs), "failed to map registers\n");
-
priv_data->dwc3_config = device_get_match_data(dev);
if (!priv_data->dwc3_config)
return dev_err_probe(dev, -ENODEV,
"missing dwc3 platform configuration\n");
- priv_data->regs = regs;
+
+ if (!priv_data->dwc3_config->no_mem_map) {
+ void __iomem *regs;
+
+ regs = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(regs))
+ return dev_err_probe(dev, PTR_ERR(regs),
+ "failed to map registers\n");
+ priv_data->regs = regs;
+ }
+
priv_data->dev = dev;
platform_set_drvdata(pdev, priv_data);
--
2.43.0
^ permalink raw reply related
* [PATCH v3 4/4] usb: dwc3: xilinx: Add support to program MMI USB TX deemphasis
From: Radhey Shyam Pandey @ 2026-04-29 17:30 UTC (permalink / raw)
To: gregkh, robh, krzk+dt, conor+dt, michal.simek, Thinh.Nguyen,
p.zabel
Cc: linux-usb, devicetree, linux-arm-kernel, linux-kernel, git,
Radhey Shyam Pandey
In-Reply-To: <20260429173050.1772377-1-radhey.shyam.pandey@amd.com>
Introduces support for programming the 18-bit TX deemphasis value that
drives the pipe_TxDeemph signal, as defined in the PIPE4 specification.
The configured value is recommended by Synopsys and is intended for
standard (non-compliance) operation. These Gen2 equalization settings
have been validated through both internal and external compliance
testing. By applying this setting, the stability of USB 3.2 enumeration
is improved and now SuperSpeedPlus devices are consistently recognized as
USB 3.2 Gen2 by the MMI USB Host controller.
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
--
Changes for v3:
- Define DWC3_LCSR_TX_DEEMPH(n) and multiport handling. Thinh: Please
review on this offset calculation as MMI USB IP support single usb3
port.
- Default set the tx_deemph to the DWC3_LCSR_TX_DEEMPH_UNSPECIFIED.
Changes for v2:
- Don't use compatible check for deemphasis programming.
- Rename property "snps,lcsr_tx_deemph" to "snps,lcsr-tx-deemph"
(hyphens per kernel convention).
- Fix double space in LCSR_TX_DEEMPH register comment.
- Add blank line between register offset define and "Bit fields" section.
---
drivers/usb/dwc3/core.c | 24 ++++++++++++++++++++++++
drivers/usb/dwc3/core.h | 14 ++++++++++++++
drivers/usb/dwc3/dwc3-xilinx.c | 20 +++++++++++++++++---
3 files changed, 55 insertions(+), 3 deletions(-)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 58899b1fa96d..426e30563caf 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -646,6 +646,22 @@ static void dwc3_config_soc_bus(struct dwc3 *dwc)
reg |= DWC3_GSBUSCFG0_REQINFO(dwc->gsbuscfg0_reqinfo);
dwc3_writel(dwc, DWC3_GSBUSCFG0, reg);
}
+
+ /*
+ * The csr_tx_deemph setting is common across the controller and
+ * is configured per port using DWC3_LCSR_TX_DEEMPH(port).
+ */
+ if (dwc->csr_tx_deemph_field_1 != DWC3_LCSR_TX_DEEMPH_UNSPECIFIED) {
+ unsigned int port;
+ u32 reg;
+
+ for (port = 0; port < dwc->num_usb3_ports; port++) {
+ reg = dwc3_readl(dwc, DWC3_LCSR_TX_DEEMPH(port));
+ reg &= ~DWC3_LCSR_TX_DEEMPH_MASK(~0);
+ reg |= DWC3_LCSR_TX_DEEMPH_MASK(dwc->csr_tx_deemph_field_1);
+ dwc3_writel(dwc, DWC3_LCSR_TX_DEEMPH(port), reg);
+ }
+ }
}
static int dwc3_core_ulpi_init(struct dwc3 *dwc)
@@ -1691,6 +1707,7 @@ static void dwc3_core_exit_mode(struct dwc3 *dwc)
static void dwc3_get_software_properties(struct dwc3 *dwc,
const struct dwc3_properties *properties)
{
+ u32 csr_tx_deemph_field_1;
struct device *tmpdev;
u16 gsbuscfg0_reqinfo;
int ret;
@@ -1699,6 +1716,7 @@ static void dwc3_get_software_properties(struct dwc3 *dwc,
dwc->needs_full_reinit = true;
dwc->gsbuscfg0_reqinfo = DWC3_GSBUSCFG0_REQINFO_UNSPECIFIED;
+ dwc->csr_tx_deemph_field_1 = DWC3_LCSR_TX_DEEMPH_UNSPECIFIED;
if (properties->gsbuscfg0_reqinfo !=
DWC3_GSBUSCFG0_REQINFO_UNSPECIFIED) {
@@ -1716,6 +1734,12 @@ static void dwc3_get_software_properties(struct dwc3 *dwc,
&gsbuscfg0_reqinfo);
if (!ret)
dwc->gsbuscfg0_reqinfo = gsbuscfg0_reqinfo;
+
+ ret = device_property_read_u32(tmpdev,
+ "snps,lcsr-tx-deemph",
+ &csr_tx_deemph_field_1);
+ if (!ret)
+ dwc->csr_tx_deemph_field_1 = csr_tx_deemph_field_1;
}
}
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index e0dee9d28740..ab68c6d7b021 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -181,6 +181,12 @@
#define DWC3_LLUCTL(n) (0xd024 + ((n) * 0x80))
+/*
+ * LCSR TX deemphasis register for USB3 port @n.
+ * Offset stride matches DWC3_LLUCTL.
+ */
+#define DWC3_LCSR_TX_DEEMPH(n) (0xd060 + ((n) * 0x80))
+
/* Bit fields */
/* Global SoC Bus Configuration INCRx Register 0 */
@@ -198,6 +204,10 @@
#define DWC3_GSBUSCFG0_REQINFO(n) (((n) & 0xffff) << 16)
#define DWC3_GSBUSCFG0_REQINFO_UNSPECIFIED 0xffffffff
+/* LCSR_TX_DEEMPH Register: setting TX deemphasis used in normal operation in gen2 */
+#define DWC3_LCSR_TX_DEEMPH_MASK(n) ((n) & 0x3ffff)
+#define DWC3_LCSR_TX_DEEMPH_UNSPECIFIED 0xffffffff
+
/* Global Debug LSP MUX Select */
#define DWC3_GDBGLSPMUX_ENDBC BIT(15) /* Host only */
#define DWC3_GDBGLSPMUX_HOSTSELECT(n) ((n) & 0x3fff)
@@ -1185,6 +1195,9 @@ struct dwc3_glue_ops {
* @wakeup_pending_funcs: Indicates whether any interface has requested for
* function wakeup in bitmap format where bit position
* represents interface_id.
+ * @csr_tx_deemph_field_1: stores TX deemphasis used in Gen2 operation.
+ * The csr_tx_deemph setting is applied to each
+ * USB3 port.
*/
struct dwc3 {
struct work_struct drd_work;
@@ -1424,6 +1437,7 @@ struct dwc3 {
struct dentry *debug_root;
u32 gsbuscfg0_reqinfo;
u32 wakeup_pending_funcs;
+ u32 csr_tx_deemph_field_1;
};
#define INCRX_BURST_MODE 0
diff --git a/drivers/usb/dwc3/dwc3-xilinx.c b/drivers/usb/dwc3/dwc3-xilinx.c
index b601cca485ed..7c6111a9ca44 100644
--- a/drivers/usb/dwc3/dwc3-xilinx.c
+++ b/drivers/usb/dwc3/dwc3-xilinx.c
@@ -25,6 +25,8 @@
#include <linux/phy/phy.h>
+#include "core.h"
+
/* USB phy reset mask register */
#define XLNX_USB_PHY_RST_EN 0x001C
#define XLNX_PHY_RST_MASK 0x1
@@ -41,12 +43,14 @@
#define PIPE_CLK_SELECT 0
#define XLNX_USB_FPD_POWER_PRSNT 0x80
#define FPD_POWER_PRSNT_OPTION BIT(0)
+#define XLNX_MMI_USB_TX_DEEMPH_DEF 0x8c45
struct dwc3_xlnx;
struct dwc3_xlnx_config {
int (*pltfm_init)(struct dwc3_xlnx *data);
bool no_mem_map;
+ u32 tx_deemph;
};
struct dwc3_xlnx {
@@ -280,15 +284,18 @@ static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx *priv_data)
static const struct dwc3_xlnx_config zynqmp_config = {
.pltfm_init = dwc3_xlnx_init_zynqmp,
+ .tx_deemph = DWC3_LCSR_TX_DEEMPH_UNSPECIFIED,
};
static const struct dwc3_xlnx_config versal_config = {
.pltfm_init = dwc3_xlnx_init_versal,
+ .tx_deemph = DWC3_LCSR_TX_DEEMPH_UNSPECIFIED,
};
static const struct dwc3_xlnx_config versal2_config = {
.pltfm_init = dwc3_xlnx_init_versal2,
.no_mem_map = true,
+ .tx_deemph = XLNX_MMI_USB_TX_DEEMPH_DEF,
};
static const struct of_device_id dwc3_xlnx_of_match[] = {
@@ -308,10 +315,12 @@ static const struct of_device_id dwc3_xlnx_of_match[] = {
};
MODULE_DEVICE_TABLE(of, dwc3_xlnx_of_match);
-static int dwc3_set_swnode(struct device *dev)
+static int dwc3_set_swnode(struct dwc3_xlnx *priv_data)
{
+ struct device *dev = priv_data->dev;
+ const struct dwc3_xlnx_config *config = priv_data->dwc3_config;
struct device_node *np = dev->of_node, *dwc3_np;
- struct property_entry props[2];
+ struct property_entry props[3];
int prop_idx = 0, ret = 0;
dwc3_np = of_get_compatible_child(np, "snps,dwc3");
@@ -325,6 +334,11 @@ static int dwc3_set_swnode(struct device *dev)
if (of_dma_is_coherent(dwc3_np))
props[prop_idx++] = PROPERTY_ENTRY_U16("snps,gsbuscfg0-reqinfo",
0xffff);
+
+ if (config->tx_deemph != DWC3_LCSR_TX_DEEMPH_UNSPECIFIED)
+ props[prop_idx++] = PROPERTY_ENTRY_U32("snps,lcsr-tx-deemph",
+ config->tx_deemph);
+
of_node_put(dwc3_np);
if (prop_idx)
@@ -377,7 +391,7 @@ static int dwc3_xlnx_probe(struct platform_device *pdev)
if (ret)
goto err_clk_put;
- ret = dwc3_set_swnode(dev);
+ ret = dwc3_set_swnode(priv_data);
if (ret)
goto err_clk_put;
--
2.43.0
^ permalink raw reply related
* Re: [PATCH v5 0/8] unwind, arm64: add sframe unwinder for kernel
From: Mark Rutland @ 2026-04-29 17:18 UTC (permalink / raw)
To: Dylan Hatch
Cc: Roman Gushchin, Weinan Liu, Will Deacon, Josh Poimboeuf,
Indu Bhagat, Peter Zijlstra, Steven Rostedt, Catalin Marinas,
Jiri Kosina, Jens Remus, Prasanna Kumar T S M, Puranjay Mohan,
Song Liu, joe.lawrence, linux-toolchains, linux-kernel,
live-patching, linux-arm-kernel, Randy Dunlap
In-Reply-To: <20260428183643.3796063-1-dylanbhatch@google.com>
Hi Dylan,
On Tue, Apr 28, 2026 at 06:36:35PM +0000, Dylan Hatch wrote:
> Implement a generic kernel sframe-based [1] unwinder. The main goal is
> to improve reliable stacktrace on arm64 by unwinding across exception
> boundaries.
Thanks for this!
Just as a holding reply: I'm going over the series now, and I have some
partially-written comments that I'll try to finish up and get out
tomorrow.
Mark.
> On x86, the ORC unwinder provides reliable stacktrace through similar
> methodology, but arm64 lacks the necessary support from objtool to
> create ORC unwind tables.
>
> Currently, there's already a sframe unwinder proposed for userspace: [2].
> To maintain common definitions and algorithms for sframe lookup, a
> substantial portion of this patch series aims to refactor the sframe
> lookup code to support both kernel and userspace sframe sections.
>
> Currently, only GNU Binutils support sframe. This series relies on the
> Sframe V3 format, which is supported in binutils 2.46.
>
> These patches are based on Steven Rostedt's sframe/core branch [3],
> which is and aggregation of existing work done for x86 sframe userspace
> unwind, and contains [2]. This branch is, in turn, based on Linux
> v7.0-rc3. This full series (applied to the sframe/core branch) is
> available on github: [4].
>
> Ref:
> [1]: https://sourceware.org/binutils/docs/sframe-spec.html
> [2]: https://lore.kernel.org/lkml/20260127150554.2760964-1-jremus@linux.ibm.com/
> [3]: https://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-trace.git/log/?h=sframe/core
> [4]: https://github.com/dylanbhatch/linux/tree/sframe-v5
>
> Changes since v4:
> - (Jens) Fix some minor nits.
> - Handle .init.text and .exit.text in function address validation.
>
> Changes since v3:
>
> - (Jens) Clean up patch summaries.
> - (Jens) Rename SFRAME_LOOKUP -> UNWIND_SFRAME_LOOKUP to fit existing
> naming convention.
> - (Randy) Correct typo errors in new config options.
> - (Jens) Move unwind types to a new unwind_types.h to match their
> usage.
> - (Jens) Update KERNEL_[COPY|GET] to use label-based error handling
> like their userspace counterparts.
> - (Jens) Rename SFRAME_UNWINDER -> HAVE_UNWIND_KERNEL_SFRAME and
> ARCH_SUPPORTS_SFRAME_UNWINDER -> ARCH_SUPPORTS_UNWIND_KERNEL_SFRAME
> to match existing naming convention.
> - (Jens) Move HAVE_UNWIND_KERNEL_SFRAME config option to arch/Kconfig.
> - (Jens) Rename/move extern definitions of __[start|end]_sframe into
> include/asm-generic/sections.h.
> - (Jens) Fix up CFI annotations at kernel entry.
> - (Jens) Fix error path for unsorted FDE lookup.
> - (Jens) Zero-out module sframe_section before init.
> - (Jens) For SFRAME_VALIDATION, use an arch-specific function-address
> validation helper so that .rodata.text can be correctly handled on
> arm64 vmlinux.
> - (Jens) Fixup and better comment kernel stacktrace code.
>
> Changes since v2:
>
> The biggest change from v2 is the switch from adding a dedicated,
> in-kernel sframe-lookup library, to refactoring/using the existing
> library developed by Josh, Jens, and Steve. Consequently, this series
> now depends on Sframe V3, though this upgrade would likely have been
> necessary anyway. Below is a full accounting of the changes since v2.
>
> - (Josh) Add stricter reliability checks during unwind.
> - (Puranjay, Indu, Jens) Update to use a common sframe library with
> userpace unwind, thus resolving the need to support
> SFRAME_F_FDE_FUNC_START_PCREL, added in binutils 2.45.
> - (Jens) Add check for sframe V3, thus resolving the prior need for V2
> and SFRAME_F_FDE_FUNC_START_PCREL support.
> - (Will) Add ARCH_SUPPORTS_SFRAME_UNWINDER, remove SFRAME_UNWIND_TABLE
> - (Indu) add support for unsorted FDE tables, allowing for module
> sframe lookups.
> - (Mark) Prefer frame-pointer unwind when possible, for better
> performance.
> - Simplify compile-time logic, adding stubbs when necessary.
> - Add support for in-kernel SFRAME_VALIDATION.
> - Rebase onto core/sframe (with v7.0-rc3 base)
>
> Dylan Hatch (7):
> sframe: Allow kernelspace sframe sections
> arm64, unwind: build kernel with sframe V3 info
> sframe: Provide PC lookup for vmlinux .sframe section
> sframe: Allow unsorted FDEs
> arm64/module, sframe: Add sframe support for modules
> sframe: Introduce in-kernel SFRAME_VALIDATION
> unwind: arm64: Use sframe to unwind interrupt frames
>
> Weinan Liu (1):
> arm64: entry: add unwind info for various kernel entries
>
> MAINTAINERS | 3 +-
> Makefile | 8 +
> arch/Kconfig | 27 +-
> arch/arm64/Kconfig | 1 +
> arch/arm64/include/asm/module.h | 6 +
> arch/arm64/include/asm/sections.h | 1 +
> arch/arm64/include/asm/stacktrace/common.h | 6 +
> arch/arm64/include/asm/unwind_sframe.h | 55 +++
> arch/arm64/kernel/entry.S | 23 +
> arch/arm64/kernel/module.c | 8 +
> arch/arm64/kernel/setup.c | 2 +
> arch/arm64/kernel/stacktrace.c | 246 ++++++++++-
> arch/arm64/kernel/vdso/Makefile | 2 +-
> arch/arm64/kernel/vmlinux.lds.S | 2 +
> .../{unwind_user_sframe.h => unwind_sframe.h} | 6 +-
> arch/x86/include/asm/unwind_user.h | 12 +-
> include/asm-generic/sections.h | 4 +
> include/asm-generic/vmlinux.lds.h | 15 +
> include/linux/sframe.h | 67 ++-
> include/linux/unwind_types.h | 46 ++
> include/linux/unwind_user_types.h | 41 --
> kernel/unwind/Makefile | 2 +-
> kernel/unwind/sframe.c | 410 ++++++++++++++----
> kernel/unwind/user.c | 41 +-
> 24 files changed, 827 insertions(+), 207 deletions(-)
> create mode 100644 arch/arm64/include/asm/unwind_sframe.h
> rename arch/x86/include/asm/{unwind_user_sframe.h => unwind_sframe.h} (50%)
> create mode 100644 include/linux/unwind_types.h
>
> --
> 2.54.0.545.g6539524ca2-goog
>
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