* [PATCH v3 10/11] mtd: spinand: winbond: Create a helper to detect the need for the HS bit
From: Miquel Raynal @ 2026-04-29 17:56 UTC (permalink / raw)
To: Mark Brown, Richard Weinberger, Vignesh Raghavendra,
Michael Walle, Miquel Raynal, Takahiro Kuwano, Lorenzo Bianconi,
Ray Liu, Chin-Ting Kuo, Cédric Le Goater, Joel Stanley,
Andrew Jeffery, Avi Fishman, Tomer Maimon, Tali Perry,
Patrick Venture, Nancy Yuen, Benjamin Fair, Maxime Coquelin,
Alexandre Torgue, Jonathan Neuschäfer
Cc: Pratyush Yadav, Thomas Petazzoni, Steam Lin, Santhosh Kumar K,
linux-spi, linux-kernel, linux-mtd, linux-arm-kernel,
linux-aspeed, openbmc, linux-stm32
In-Reply-To: <20260429-winbond-v6-18-rc1-cont-read-v3-0-0f38b3c229ad@bootlin.com>
The logic is not complex but might be reused to cleanup a bit the
section by moving it to a dedicated helper.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
drivers/mtd/nand/spi/winbond.c | 31 +++++++++++++++++--------------
1 file changed, 17 insertions(+), 14 deletions(-)
diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c
index b30a343a6672..ffbcd25b0366 100644
--- a/drivers/mtd/nand/spi/winbond.c
+++ b/drivers/mtd/nand/spi/winbond.c
@@ -421,30 +421,33 @@ static int w25n0xjw_set_sr4_hs(struct spinand_device *spinand, bool enable)
return spinand_write_reg_op(spinand, W25N0XJW_SR4, sr4);
}
+/*
+ * SDR dual and quad I/O operations over 104MHz require the HS bit to
+ * enable a few more dummy cycles.
+ */
+static bool w25n0xjw_op_needs_hs(const struct spi_mem_op *op)
+{
+ if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr)
+ return false;
+ else if (op->cmd.buswidth != 1 || op->addr.buswidth == 1)
+ return false;
+ else if (op->max_freq && op->max_freq <= 104 * HZ_PER_MHZ)
+ return false;
+
+ return true;
+}
+
static int w25n0xjw_hs_cfg(struct spinand_device *spinand,
enum spinand_bus_interface iface)
{
const struct spi_mem_op *op;
- bool hs;
if (iface != SSDR)
return -EOPNOTSUPP;
- /*
- * SDR dual and quad I/O operations over 104MHz require the HS bit to
- * enable a few more dummy cycles.
- */
op = spinand->op_templates->read_cache;
- if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr)
- hs = false;
- else if (op->cmd.buswidth != 1 || op->addr.buswidth == 1)
- hs = false;
- else if (op->max_freq && op->max_freq <= 104 * HZ_PER_MHZ)
- hs = false;
- else
- hs = true;
- return w25n0xjw_set_sr4_hs(spinand, hs);
+ return w25n0xjw_set_sr4_hs(spinand, w25n0xjw_op_needs_hs(op));
}
static int w35n0xjw_write_vcr(struct spinand_device *spinand, u8 reg, u8 val)
--
2.53.0
^ permalink raw reply related
* [PATCH v3 11/11] mtd: spinand: winbond: Add support for continuous reads on W25NxxJW
From: Miquel Raynal @ 2026-04-29 17:56 UTC (permalink / raw)
To: Mark Brown, Richard Weinberger, Vignesh Raghavendra,
Michael Walle, Miquel Raynal, Takahiro Kuwano, Lorenzo Bianconi,
Ray Liu, Chin-Ting Kuo, Cédric Le Goater, Joel Stanley,
Andrew Jeffery, Avi Fishman, Tomer Maimon, Tali Perry,
Patrick Venture, Nancy Yuen, Benjamin Fair, Maxime Coquelin,
Alexandre Torgue, Jonathan Neuschäfer
Cc: Pratyush Yadav, Thomas Petazzoni, Steam Lin, Santhosh Kumar K,
linux-spi, linux-kernel, linux-mtd, linux-arm-kernel,
linux-aspeed, openbmc, linux-stm32
In-Reply-To: <20260429-winbond-v6-18-rc1-cont-read-v3-0-0f38b3c229ad@bootlin.com>
As for the W35NxxJW family, add support for W25N{01,02}JW continuous
read support. Similar operations require to be done, such as setting a
specific bit in a configuration register, and providing a set of read
variants without the address cycles.
As read from cache variants are badly supported by SPI memory
controllers, we create a new set of read from cache templates with a
fake address cycle and just enough dummy cycles. There are two
unsupported configurations (which would require 4.5 dummy bytes), so we
just do not provide them.
The same extra value in the ECC is possible as with the W35NxxJW family,
so we reference the same helper to retrieve the ECC status.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
---
All variants have been validated on a Nuvoton MA35D1 platform.
---
drivers/mtd/nand/spi/winbond.c | 108 +++++++++++++++++++++++++++++++++++++----
1 file changed, 98 insertions(+), 10 deletions(-)
diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c
index ffbcd25b0366..578f702528ee 100644
--- a/drivers/mtd/nand/spi/winbond.c
+++ b/drivers/mtd/nand/spi/winbond.c
@@ -46,6 +46,62 @@
SPI_MEM_OP_DATA_IN(len, buf, 1), \
SPI_MEM_OP_MAX_FREQ(freq))
+#define WINBOND_CONT_READ_FROM_CACHE_1S_1D_1D_OP(ndummy, buf, len, freq) \
+ SPI_MEM_OP(SPI_MEM_OP_CMD(0x0d, 1), \
+ SPI_MEM_DTR_OP_ADDR(2, 0, 1), \
+ SPI_MEM_DTR_OP_DUMMY(ndummy, 1), \
+ SPI_MEM_DTR_OP_DATA_IN(len, buf, 1), \
+ SPI_MEM_OP_MAX_FREQ(freq))
+
+#define WINBOND_CONT_READ_FROM_CACHE_1S_1S_2S_OP(ndummy, buf, len, freq) \
+ SPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1), \
+ SPI_MEM_OP_ADDR(1, 0, 1), \
+ SPI_MEM_OP_DUMMY(ndummy - 1, 1), \
+ SPI_MEM_OP_DATA_IN(len, buf, 2), \
+ SPI_MEM_OP_MAX_FREQ(freq))
+
+#define WINBOND_CONT_READ_FROM_CACHE_1S_2S_2S_OP(ndummy, buf, len, freq) \
+ SPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1), \
+ SPI_MEM_OP_ADDR(1, 0, 2), \
+ SPI_MEM_OP_DUMMY(ndummy - 1, 2), \
+ SPI_MEM_OP_DATA_IN(len, buf, 2), \
+ SPI_MEM_OP_MAX_FREQ(freq))
+
+#define WINBOND_CONT_READ_FROM_CACHE_1S_2D_2D_OP(ndummy, buf, len, freq) \
+ SPI_MEM_OP(SPI_MEM_OP_CMD(0xbd, 1), \
+ SPI_MEM_DTR_OP_ADDR(1, 0, 2), \
+ SPI_MEM_DTR_OP_DUMMY(ndummy - 1, 2), \
+ SPI_MEM_DTR_OP_DATA_IN(len, buf, 2), \
+ SPI_MEM_OP_MAX_FREQ(freq))
+
+#define WINBOND_CONT_READ_FROM_CACHE_1S_1S_4S_OP(ndummy, buf, len, freq) \
+ SPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1), \
+ SPI_MEM_OP_ADDR(1, 0, 1), \
+ SPI_MEM_OP_DUMMY(ndummy - 1, 1), \
+ SPI_MEM_OP_DATA_IN(len, buf, 4), \
+ SPI_MEM_OP_MAX_FREQ(freq))
+
+#define WINBOND_CONT_READ_FROM_CACHE_1S_1D_4D_OP(ndummy, buf, len, freq) \
+ SPI_MEM_OP(SPI_MEM_OP_CMD(0x6d, 1), \
+ SPI_MEM_DTR_OP_ADDR(1, 0, 1), \
+ SPI_MEM_DTR_OP_DUMMY(ndummy - 1, 1), \
+ SPI_MEM_DTR_OP_DATA_IN(len, buf, 4), \
+ SPI_MEM_OP_MAX_FREQ(freq))
+
+#define WINBOND_CONT_READ_FROM_CACHE_1S_4S_4S_OP(ndummy, buf, len, freq) \
+ SPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1), \
+ SPI_MEM_OP_ADDR(1, 0, 4), \
+ SPI_MEM_OP_DUMMY(ndummy - 1, 4), \
+ SPI_MEM_OP_DATA_IN(len, buf, 4), \
+ SPI_MEM_OP_MAX_FREQ(freq))
+
+#define WINBOND_CONT_READ_FROM_CACHE_1S_4D_4D_OP(ndummy, buf, len, freq) \
+ SPI_MEM_OP(SPI_MEM_OP_CMD(0xed, 1), \
+ SPI_MEM_DTR_OP_ADDR(1, 0, 4), \
+ SPI_MEM_DTR_OP_DUMMY(ndummy - 1, 4), \
+ SPI_MEM_DTR_OP_DATA_IN(len, buf, 4), \
+ SPI_MEM_OP_MAX_FREQ(freq))
+
#define WINBOND_CONT_READ_FROM_CACHE_1S_1S_8S_OP(ndummy, buf, len, freq) \
SPI_MEM_OP(SPI_MEM_OP_CMD(0x8b, 1), \
SPI_MEM_OP_ADDR(1, 0, 1), \
@@ -133,6 +189,20 @@ static SPINAND_OP_VARIANTS(read_cache_dual_quad_dtr_variants,
SPINAND_PAGE_READ_FROM_CACHE_FAST_1S_1S_1S_OP(0, 1, NULL, 0, 0),
SPINAND_PAGE_READ_FROM_CACHE_1S_1S_1S_OP(0, 1, NULL, 0, 54 * HZ_PER_MHZ));
+static SPINAND_OP_VARIANTS(cont_read_cache_dual_quad_dtr_variants,
+ WINBOND_CONT_READ_FROM_CACHE_1S_4D_4D_OP(11, NULL, 0, 80 * HZ_PER_MHZ),
+ WINBOND_CONT_READ_FROM_CACHE_1S_1D_4D_OP(5, NULL, 0, 80 * HZ_PER_MHZ),
+ WINBOND_CONT_READ_FROM_CACHE_1S_4S_4S_OP(7, NULL, 0, 0),
+ WINBOND_CONT_READ_FROM_CACHE_1S_4S_4S_OP(6, NULL, 0, 104 * HZ_PER_MHZ),
+ WINBOND_CONT_READ_FROM_CACHE_1S_1S_4S_OP(4, NULL, 0, 0),
+ WINBOND_CONT_READ_FROM_CACHE_1S_2D_2D_OP(6, NULL, 0, 80 * HZ_PER_MHZ),
+ /* The 1S_1D_2D variant would require 4.5 dummy bytes, this is not possible */
+ WINBOND_CONT_READ_FROM_CACHE_1S_2S_2S_OP(5, NULL, 0, 0),
+ WINBOND_CONT_READ_FROM_CACHE_1S_2S_2S_OP(4, NULL, 0, 104 * HZ_PER_MHZ),
+ WINBOND_CONT_READ_FROM_CACHE_1S_1S_2S_OP(4, NULL, 0, 0),
+ /* The 1S_1D_1D variant would require 4.5 dummy bytes, this is not possible */
+ WINBOND_CONT_READ_FROM_CACHE_FAST_1S_1S_1S_OP(4, NULL, 0, 0));
+
static SPINAND_OP_VARIANTS(read_cache_variants,
SPINAND_PAGE_READ_FROM_CACHE_1S_4S_4S_OP(0, 2, NULL, 0, 0),
SPINAND_PAGE_READ_FROM_CACHE_1S_1S_4S_OP(0, 1, NULL, 0, 0),
@@ -445,11 +515,25 @@ static int w25n0xjw_hs_cfg(struct spinand_device *spinand,
if (iface != SSDR)
return -EOPNOTSUPP;
+ /*
+ * At this stage, we do not yet know the continuous read template, nor
+ * if there is going to be one. Let's assume the continuous read
+ * template will be selected with the same heuristics as the buffered
+ * read variant, as there cannot be a HS configuration mismatch between
+ * them.
+ */
op = spinand->op_templates->read_cache;
return w25n0xjw_set_sr4_hs(spinand, w25n0xjw_op_needs_hs(op));
}
+static int w25n0xjw_set_cont_read(struct spinand_device *spinand, bool enable)
+{
+ u8 mask = enable ? 0 : WINBOND_CFG_BUF_READ;
+
+ return spinand_upd_cfg(spinand, WINBOND_CFG_BUF_READ, mask);
+}
+
static int w35n0xjw_write_vcr(struct spinand_device *spinand, u8 reg, u8 val)
{
struct spi_mem_op op = SPINAND_OP(spinand, winbond_write_vcr,
@@ -580,12 +664,14 @@ static const struct spinand_info winbond_spinand_table[] = {
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xbc, 0x21),
NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
NAND_ECCREQ(1, 512),
- SPINAND_INFO_OP_VARIANTS(&read_cache_dual_quad_dtr_variants,
- &write_cache_variants,
- &update_cache_variants),
+ SPINAND_INFO_OP_VARIANTS_WITH_CONT(&read_cache_dual_quad_dtr_variants,
+ &write_cache_variants,
+ &update_cache_variants,
+ &cont_read_cache_dual_quad_dtr_variants),
SPINAND_HAS_QE_BIT,
- SPINAND_ECCINFO(&w25n01jw_ooblayout, NULL),
- SPINAND_CONFIGURE_CHIP(w25n0xjw_hs_cfg)),
+ SPINAND_ECCINFO(&w25n01jw_ooblayout, w25w35nxxjw_ecc_get_status),
+ SPINAND_CONFIGURE_CHIP(w25n0xjw_hs_cfg),
+ SPINAND_CONT_READ(w25n0xjw_set_cont_read)),
SPINAND_INFO("W25N01KV", /* 3.3V */
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xae, 0x21),
NAND_MEMORG(1, 2048, 96, 64, 1024, 20, 1, 1, 1),
@@ -624,12 +710,14 @@ static const struct spinand_info winbond_spinand_table[] = {
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xbf, 0x22),
NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 2, 1),
NAND_ECCREQ(1, 512),
- SPINAND_INFO_OP_VARIANTS(&read_cache_dual_quad_dtr_variants,
- &write_cache_variants,
- &update_cache_variants),
+ SPINAND_INFO_OP_VARIANTS_WITH_CONT(&read_cache_dual_quad_dtr_variants,
+ &write_cache_variants,
+ &update_cache_variants,
+ &cont_read_cache_dual_quad_dtr_variants),
SPINAND_HAS_QE_BIT,
- SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL),
- SPINAND_CONFIGURE_CHIP(w25n0xjw_hs_cfg)),
+ SPINAND_ECCINFO(&w25m02gv_ooblayout, w25w35nxxjw_ecc_get_status),
+ SPINAND_CONFIGURE_CHIP(w25n0xjw_hs_cfg),
+ SPINAND_CONT_READ(w25n0xjw_set_cont_read)),
SPINAND_INFO("W25N02KV", /* 3.3V */
SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x22),
NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
--
2.53.0
^ permalink raw reply related
* Re: [PATCH v13 3/4] gpio: rpmsg: add generic rpmsg GPIO driver
From: Padhi, Beleswar @ 2026-04-29 18:06 UTC (permalink / raw)
To: Mathieu Poirier, Shenwei Wang
Cc: Andrew Lunn, Linus Walleij, Bartosz Golaszewski, Jonathan Corbet,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
Frank Li, Sascha Hauer, Shuah Khan, linux-gpio@vger.kernel.org,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
Pengutronix Kernel Team, Fabio Estevam, Peng Fan,
devicetree@vger.kernel.org, linux-remoteproc@vger.kernel.org,
imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
dl-linux-imx, Bartosz Golaszewski
In-Reply-To: <CANLsYkwvL0Z3+12MD=J+Dc2yAU2T8ypizyG=6AhYoWOh55odHA@mail.gmail.com>
Hi Mathieu,
On 4/29/2026 11:03 PM, Mathieu Poirier wrote:
> On Wed, 29 Apr 2026 at 10:53, Shenwei Wang <shenwei.wang@nxp.com> wrote:
>>
>>
>>> -----Original Message-----
>>> From: Mathieu Poirier <mathieu.poirier@linaro.org>
>>> Sent: Wednesday, April 29, 2026 10:42 AM
>>> To: Shenwei Wang <shenwei.wang@nxp.com>
>>> Cc: Andrew Lunn <andrew@lunn.ch>; Padhi, Beleswar <b-padhi@ti.com>; Linus
>>> Walleij <linusw@kernel.org>; Bartosz Golaszewski <brgl@kernel.org>; Jonathan
>>> Corbet <corbet@lwn.net>; Rob Herring <robh@kernel.org>; Krzysztof Kozlowski
>>> <krzk+dt@kernel.org>; Conor Dooley <conor+dt@kernel.org>; Bjorn Andersson
>>> <andersson@kernel.org>; Frank Li <frank.li@nxp.com>; Sascha Hauer
>>> <s.hauer@pengutronix.de>; Shuah Khan <skhan@linuxfoundation.org>; linux-
>>> gpio@vger.kernel.org; linux-doc@vger.kernel.org; linux-kernel@vger.kernel.org;
>>> Pengutronix Kernel Team <kernel@pengutronix.de>; Fabio Estevam
>>> <festevam@gmail.com>; Peng Fan <peng.fan@nxp.com>;
>>> devicetree@vger.kernel.org; linux-remoteproc@vger.kernel.org;
>>> imx@lists.linux.dev; linux-arm-kernel@lists.infradead.org; dl-linux-imx <linux-
>>> imx@nxp.com>; Bartosz Golaszewski <brgl@bgdev.pl>
>>> Subject: [EXT] Re: [PATCH v13 3/4] gpio: rpmsg: add generic rpmsg GPIO driver
>>> On Tue, Apr 28, 2026 at 03:24:59PM +0000, Shenwei Wang wrote:
>>>>
>>>>> -----Original Message-----
>>>>> From: Andrew Lunn <andrew@lunn.ch>
>>>>> Sent: Monday, April 27, 2026 3:49 PM
>>>>> To: Shenwei Wang <shenwei.wang@nxp.com>
>>>>> Cc: Padhi, Beleswar <b-padhi@ti.com>; Linus Walleij
>>>>> <linusw@kernel.org>; Bartosz Golaszewski <brgl@kernel.org>; Jonathan
>>>>> Corbet <corbet@lwn.net>; Rob Herring <robh@kernel.org>; Krzysztof
>>>>> Kozlowski <krzk+dt@kernel.org>; Conor Dooley <conor+dt@kernel.org>;
>>>>> Bjorn Andersson <andersson@kernel.org>; Mathieu Poirier
>>>>> <mathieu.poirier@linaro.org>; Frank Li <frank.li@nxp.com>; Sascha
>>>>> Hauer <s.hauer@pengutronix.de>; Shuah Khan
>>>>> <skhan@linuxfoundation.org>; linux-gpio@vger.kernel.org; linux-
>>>>> doc@vger.kernel.org; linux-kernel@vger.kernel.org; Pengutronix
>>>>> Kernel Team <kernel@pengutronix.de>; Fabio Estevam
>>>>> <festevam@gmail.com>; Peng Fan <peng.fan@nxp.com>;
>>>>> devicetree@vger.kernel.org; linux- remoteproc@vger.kernel.org;
>>>>> imx@lists.linux.dev; linux-arm- kernel@lists.infradead.org;
>>>>> dl-linux-imx <linux-imx@nxp.com>; Bartosz Golaszewski
>>>>> <brgl@bgdev.pl>
>>>>> Subject: [EXT] Re: [PATCH v13 3/4] gpio: rpmsg: add generic rpmsg
>>>>> GPIO driver
>>>>>>> struct virtio_gpio_response {
>>>>>>> __u8 status;
>>>>>>> __u8 value;
>>>>>>> };
>>>>>> It is the same message format. Please see the message definition
>>>>> (GET_DIRECTION) below:
>>>>>
>>>>>> + +-----+-----+-----+-----+-----+----+
>>>>>> + |0x00 |0x01 |0x02 |0x03 |0x04 |0x05|
>>>>>> + | 1 | 2 |port |line | err | dir|
>>>>>> + +-----+-----+-----+-----+-----+----+
>>>>> Sorry, but i don't see how two u8 vs six u8 are the same message format.
>>>>>
>>>> Some changes to the message format are necessary.
>>>>
>>>> Virtio uses two communication channels (virtqueues): one for requests and
>>> replies, and a second one for events.
>>>> In contrast, rpmsg provides only a single communication channel, so a
>>>> type field is required to distinguish between different kinds of messages.
>>>>
>>>> Since rpmsg replies and events share the same message format, an additional
>>> line is introduced to handle both cases.
>>>> Finally, rpmsg supports multiple GPIO controllers, so a port field is added to
>>> uniquely identify the target controller.
>>>
>>> I have commented on this before - RPMSG is already providing multiplexing
>>> capability by way of endpoints. There is no need for a port field. One endpoint,
>>> one GPIO controller.
>>>
>> You still need a way to let the remote side know which port the endpoint maps to, either
>> by embedding the port information in the message (the current way), or by sending it
>> separately.
>>
> An endpoint is created with every namespace request. There should be
> one namespace request for every GPIO controller, which yields a unique
> endpoint for each controller and eliminates the need for an extra
> field to identify them.
Right, but this can still be done by just having one namespace request.
We can create new endpoints bound to an existing namespace/channel by
invoking rpmsg_create_ept(). This is what I suggested here too:
https://lore.kernel.org/all/29485742-6e49-482e-b73d-228295daaeec@ti.com/
My mental model looks like this for the complete picture:
1. namespace/channel#1 = rpmsg-io
a. ept1 -> gpio-controller@1
b. ept2 -> gpio-controller@2
2. namespace/channel#2 = rpmsg-i2c
a. ept1 -> i2c@1
b. ept2 -> i2c@2
c. ept3 -> i2c@3
etc...
This way device groups are isolated with each channel/namespace, and
instances within each device groups are also respected with specific
endpoints.
Thanks,
Beleswar
^ permalink raw reply
* Re: [PATCH v3 1/2] media: verisilicon: Simplify motion vectors and rfc buffers allocation
From: Nicolas Dufresne @ 2026-04-29 18:11 UTC (permalink / raw)
To: Frank Li, Benjamin Gaignard
Cc: p.zabel, mchehab, s.hauer, kernel, festevam, heiko,
mcoquelin.stm32, alexandre.torgue, wens, jernej.skrabec, samuel,
linux-kernel, linux-media, linux-rockchip, imx, linux-arm-kernel,
linux-stm32, linux-sunxi, kernel
In-Reply-To: <aeIRWW937ev_F8zF@lizhi-Precision-Tower-5810>
[-- Attachment #1: Type: text/plain, Size: 1335 bytes --]
Hi Benjamin,
Le vendredi 17 avril 2026 à 06:54 -0400, Frank Li a écrit :
> On Wed, Apr 15, 2026 at 04:04:19PM +0200, Benjamin Gaignard wrote:
> > Until now we reserve the space needed for motion vectors and reference
> > frame compression at the end of the frame buffer.
> > Disentanglement mv and rfc from frame buffers by allocating
> > distinct buffers for each purpose.
> > That simplify the code by removing lot of offset computation.
>
> Can you try split to more small and straight forward patches, for example
>
> for example create patch just move hantro_h264_mv_size() to header file,
Marking this has Change Requested, as I completely agree with Frank that a split
of this giant will help proper review.
Nicolas
>
> ...
> > +++ b/drivers/media/platform/verisilicon/hantro_hevc.c
> > @@ -44,30 +44,49 @@ dma_addr_t hantro_hevc_get_ref_buf(struct hantro_ctx *ctx,
> > int i;
> >
> > /* Find the reference buffer in already known ones */
> > - for (i = 0; i < NUM_REF_PICTURES; i++) {
> > + for (i = 0; i < NUM_REF_PICTURES; i++) {
> > if (hevc_dec->ref_bufs_poc[i] == poc) {
> > hevc_dec->ref_bufs_used |= 1 << i;
> > return hevc_dec->ref_bufs[i].dma;
> > }
> > }
> > -
> > return 0;
>
> Move this code style change to new patches.
>
> Frank
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^ permalink raw reply
* Re: [PATCH] media: verisilicon: Stop allocate mv and rfc buffers inside frame buffers
From: Nicolas Dufresne @ 2026-04-29 18:13 UTC (permalink / raw)
To: Benjamin Gaignard, p.zabel, mchehab, heiko
Cc: linux-media, linux-rockchip, linux-kernel, linux-arm-kernel,
kernel
In-Reply-To: <b056e37f0cab9741f15612cc699720b414e05dbf.camel@collabora.com>
[-- Attachment #1: Type: text/plain, Size: 43385 bytes --]
Le lundi 16 mars 2026 à 11:37 -0400, Nicolas Dufresne a écrit :
> Hi,
>
> Le jeudi 12 mars 2026 à 18:35 +0100, Benjamin Gaignard a écrit :
> > Until now we reserve the space needed for motion vectors and reference
> > frame compression at the end of the frame buffer.
> > This method was convenient but won't fit when we will introduce secure
> > data path because we will want to protect YUV data but not motion vectors
> > or compression data.
> >
> > This patch disentanglement mv and rfc from frame buffers by allocating
> > distinct buffers for each purpose.
> >
> > Tested on imx8mq for VP8, VP9, H264 and H265 codecs.
>
> What did you test exactly ? When I check the RDC knobs on imx8mq, there is no
> subdivision of the domain. So when you run in policy 2 (using the RDC and set
> the VPU domain as secure read/write) these buffers effectively need to be inside
> the secure ranges, and this is what I have running downstream at the moment (not
> ready for upstreaming yet). To be more flexibly, and subdivides the rules within
> an IP, policy 1 is needed, meaning you need to protect the IP register range,
> and clearly we don't have that upstream since that imply passing the register
> data over to the TEE. So with that justification, this change seems like a bit
> early.
>
> The separation seems wanted in the more general case, but your implementation
> does not take advantage of it. Notably, this driver allocates the same number of
> reference as there is capture buffers. Both allocation pool endup too big due to
> V4L2 limitations, but if you look at MTK, you can see they made the effort to
> limit the number of auxiliary buffers. Perhaps leveraging the separation would
> make this patch a bit more acceptable to me.
I haven't received any feedback on this. Are we going to try and limit the
number of auxiliary buffer to the number of reference (or per codec maximum) ?
Nicolas
>
> regards,
> Nicolas
>
> > Tested on rk3588 for AV1.
> > All fluster scores are remain the sames.
> >
> > Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
> > ---
> > Note: This patch depends on "media: verisilicon: Create AV1 helper library"
> > version 2
> >
> > drivers/media/platform/verisilicon/hantro.h | 28 +-
> > .../media/platform/verisilicon/hantro_av1.c | 7 -
> > .../media/platform/verisilicon/hantro_av1.h | 1 -
> > .../media/platform/verisilicon/hantro_g2.c | 36 --
> > .../platform/verisilicon/hantro_g2_hevc_dec.c | 65 ++--
> > .../platform/verisilicon/hantro_g2_vp9_dec.c | 12 +-
> > .../media/platform/verisilicon/hantro_hevc.c | 38 ++-
> > .../media/platform/verisilicon/hantro_hw.h | 103 +-----
> > .../platform/verisilicon/hantro_postproc.c | 29 +-
> > .../media/platform/verisilicon/hantro_v4l2.c | 314 ++++++++++++++++--
> > .../verisilicon/rockchip_vpu981_hw_av1_dec.c | 16 +-
> > 11 files changed, 388 insertions(+), 261 deletions(-)
> >
> > diff --git a/drivers/media/platform/verisilicon/hantro.h
> > b/drivers/media/platform/verisilicon/hantro.h
> > index 0353de154a1e..daee5b95480c 100644
> > --- a/drivers/media/platform/verisilicon/hantro.h
> > +++ b/drivers/media/platform/verisilicon/hantro.h
> > @@ -31,6 +31,9 @@ struct hantro_ctx;
> > struct hantro_codec_ops;
> > struct hantro_postproc_ops;
> >
> > +#define MAX_MV_BUFFERS MAX_POSTPROC_BUFFERS
> > +#define MAX_RFC_BUFFERS MAX_POSTPROC_BUFFERS
> > +
> > #define HANTRO_JPEG_ENCODER BIT(0)
> > #define HANTRO_ENCODERS 0x0000ffff
> > #define HANTRO_MPEG2_DECODER BIT(16)
> > @@ -237,6 +240,9 @@ struct hantro_dev {
> > * @need_postproc: Set to true if the bitstream features require to
> > * use the post-processor.
> > *
> > + * @dec_mv: motion vectors buffers for the context.
> > + * @dec_rfc: reference frame compression buffers for the context.
> > + *
> > * @codec_ops: Set of operations related to codec mode.
> > * @postproc: Post-processing context.
> > * @h264_dec: H.264-decoding context.
> > @@ -264,6 +270,9 @@ struct hantro_ctx {
> > int jpeg_quality;
> > int bit_depth;
> >
> > + struct hantro_aux_buf dec_mv[MAX_MV_BUFFERS];
> > + struct hantro_aux_buf dec_rfc[MAX_RFC_BUFFERS];
> > +
> > const struct hantro_codec_ops *codec_ops;
> > struct hantro_postproc_ctx postproc;
> > bool need_postproc;
> > @@ -329,19 +338,29 @@ struct hantro_postproc_regs {
> > struct hantro_reg input_height_ext;
> > };
> >
> > +struct hantro_hevc_decoded_buffer_info {
> > + /* Info needed when the decoded frame serves as a reference frame. */
> > + s32 poc;
> > + dma_addr_t luma_addr;
> > + dma_addr_t chroma_addr;
> > + dma_addr_t mv_addr;
> > + dma_addr_t rfc_luma_addr;
> > + dma_addr_t rfc_chroma_addr;
> > +};
> > +
> > struct hantro_vp9_decoded_buffer_info {
> > /* Info needed when the decoded frame serves as a reference frame. */
> > unsigned short width;
> > unsigned short height;
> > size_t chroma_offset;
> > - size_t mv_offset;
> > + dma_addr_t mv_addr;
> > u32 bit_depth : 4;
> > };
> >
> > struct hantro_av1_decoded_buffer_info {
> > /* Info needed when the decoded frame serves as a reference frame. */
> > size_t chroma_offset;
> > - size_t mv_offset;
> > + dma_addr_t mv_addr;
> > };
> >
> > struct hantro_decoded_buffer {
> > @@ -351,6 +370,7 @@ struct hantro_decoded_buffer {
> > union {
> > struct hantro_vp9_decoded_buffer_info vp9;
> > struct hantro_av1_decoded_buffer_info av1;
> > + struct hantro_hevc_decoded_buffer_info hevc;
> > };
> > };
> >
> > @@ -507,4 +527,8 @@ void hantro_postproc_free(struct hantro_ctx *ctx);
> > int hanto_postproc_enum_framesizes(struct hantro_ctx *ctx,
> > struct v4l2_frmsizeenum *fsize);
> >
> > +dma_addr_t hantro_mv_get_buf_addr(struct hantro_ctx *ctx, int index);
> > +dma_addr_t hantro_rfc_get_luma_buf_addr(struct hantro_ctx *ctx, int index);
> > +dma_addr_t hantro_rfc_get_chroma_buf_addr(struct hantro_ctx *ctx, int index);
> > +
> > #endif /* HANTRO_H_ */
> > diff --git a/drivers/media/platform/verisilicon/hantro_av1.c
> > b/drivers/media/platform/verisilicon/hantro_av1.c
> > index 5a51ac877c9c..3a80a7994f67 100644
> > --- a/drivers/media/platform/verisilicon/hantro_av1.c
> > +++ b/drivers/media/platform/verisilicon/hantro_av1.c
> > @@ -222,13 +222,6 @@ size_t hantro_av1_luma_size(struct hantro_ctx *ctx)
> > return ctx->ref_fmt.plane_fmt[0].bytesperline * ctx->ref_fmt.height;
> > }
> >
> > -size_t hantro_av1_chroma_size(struct hantro_ctx *ctx)
> > -{
> > - size_t cr_offset = hantro_av1_luma_size(ctx);
> > -
> > - return ALIGN((cr_offset * 3) / 2, 64);
> > -}
> > -
> > static void hantro_av1_tiles_free(struct hantro_ctx *ctx)
> > {
> > struct hantro_dev *vpu = ctx->dev;
> > diff --git a/drivers/media/platform/verisilicon/hantro_av1.h
> > b/drivers/media/platform/verisilicon/hantro_av1.h
> > index 4e2122b95cdd..330f7938d097 100644
> > --- a/drivers/media/platform/verisilicon/hantro_av1.h
> > +++ b/drivers/media/platform/verisilicon/hantro_av1.h
> > @@ -41,7 +41,6 @@ int hantro_av1_get_order_hint(struct hantro_ctx *ctx, int
> > ref);
> > int hantro_av1_frame_ref(struct hantro_ctx *ctx, u64 timestamp);
> > void hantro_av1_clean_refs(struct hantro_ctx *ctx);
> > size_t hantro_av1_luma_size(struct hantro_ctx *ctx);
> > -size_t hantro_av1_chroma_size(struct hantro_ctx *ctx);
> > void hantro_av1_exit(struct hantro_ctx *ctx);
> > int hantro_av1_init(struct hantro_ctx *ctx);
> > int hantro_av1_prepare_run(struct hantro_ctx *ctx);
> > diff --git a/drivers/media/platform/verisilicon/hantro_g2.c
> > b/drivers/media/platform/verisilicon/hantro_g2.c
> > index 318673b66da8..4ae7df53dcb1 100644
> > --- a/drivers/media/platform/verisilicon/hantro_g2.c
> > +++ b/drivers/media/platform/verisilicon/hantro_g2.c
> > @@ -99,39 +99,3 @@ size_t hantro_g2_chroma_offset(struct hantro_ctx *ctx)
> > {
> > return ctx->ref_fmt.plane_fmt[0].bytesperline * ctx-
> > > ref_fmt.height;
> > }
> > -
> > -size_t hantro_g2_motion_vectors_offset(struct hantro_ctx *ctx)
> > -{
> > - size_t cr_offset = hantro_g2_chroma_offset(ctx);
> > -
> > - return ALIGN((cr_offset * 3) / 2, G2_ALIGN);
> > -}
> > -
> > -static size_t hantro_g2_mv_size(struct hantro_ctx *ctx)
> > -{
> > - const struct hantro_hevc_dec_ctrls *ctrls = &ctx->hevc_dec.ctrls;
> > - const struct v4l2_ctrl_hevc_sps *sps = ctrls->sps;
> > - unsigned int pic_width_in_ctbs, pic_height_in_ctbs;
> > - unsigned int max_log2_ctb_size;
> > -
> > - max_log2_ctb_size = sps->log2_min_luma_coding_block_size_minus3 + 3 +
> > - sps->log2_diff_max_min_luma_coding_block_size;
> > - pic_width_in_ctbs = (sps->pic_width_in_luma_samples +
> > - (1 << max_log2_ctb_size) - 1) >>
> > max_log2_ctb_size;
> > - pic_height_in_ctbs = (sps->pic_height_in_luma_samples + (1 <<
> > max_log2_ctb_size) - 1)
> > - >> max_log2_ctb_size;
> > -
> > - return pic_width_in_ctbs * pic_height_in_ctbs * (1 << (2 *
> > (max_log2_ctb_size - 4))) * 16;
> > -}
> > -
> > -size_t hantro_g2_luma_compress_offset(struct hantro_ctx *ctx)
> > -{
> > - return hantro_g2_motion_vectors_offset(ctx) +
> > - hantro_g2_mv_size(ctx);
> > -}
> > -
> > -size_t hantro_g2_chroma_compress_offset(struct hantro_ctx *ctx)
> > -{
> > - return hantro_g2_luma_compress_offset(ctx) +
> > - hantro_hevc_luma_compressed_size(ctx->dst_fmt.width, ctx-
> > > dst_fmt.height);
> > -}
> > diff --git a/drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c
> > b/drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c
> > index e8c2e83379de..5240cf9b5f58 100644
> > --- a/drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c
> > +++ b/drivers/media/platform/verisilicon/hantro_g2_hevc_dec.c
> > @@ -377,15 +377,9 @@ static int set_ref(struct hantro_ctx *ctx)
> > const struct v4l2_ctrl_hevc_pps *pps = ctrls->pps;
> > const struct v4l2_ctrl_hevc_decode_params *decode_params = ctrls-
> > > decode_params;
> > const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb;
> > - dma_addr_t luma_addr, chroma_addr, mv_addr = 0;
> > - dma_addr_t compress_luma_addr, compress_chroma_addr = 0;
> > struct hantro_dev *vpu = ctx->dev;
> > struct vb2_v4l2_buffer *vb2_dst;
> > - struct hantro_decoded_buffer *dst;
> > - size_t cr_offset = hantro_g2_chroma_offset(ctx);
> > - size_t mv_offset = hantro_g2_motion_vectors_offset(ctx);
> > - size_t compress_luma_offset = hantro_g2_luma_compress_offset(ctx);
> > - size_t compress_chroma_offset =
> > hantro_g2_chroma_compress_offset(ctx);
> > + struct hantro_decoded_buffer *ref;
> > u32 max_ref_frames;
> > u16 dpb_longterm_e;
> > static const struct hantro_reg cur_poc[] = {
> > @@ -453,50 +447,37 @@ static int set_ref(struct hantro_ctx *ctx)
> > dpb_longterm_e = 0;
> > for (i = 0; i < decode_params->num_active_dpb_entries &&
> > i < (V4L2_HEVC_DPB_ENTRIES_NUM_MAX - 1); i++) {
> > - luma_addr = hantro_hevc_get_ref_buf(ctx,
> > dpb[i].pic_order_cnt_val);
> > - if (!luma_addr)
> > + vb2_dst = hantro_hevc_get_ref_buf(ctx,
> > dpb[i].pic_order_cnt_val);
> > + if (!vb2_dst)
> > return -ENOMEM;
> >
> > - chroma_addr = luma_addr + cr_offset;
> > - mv_addr = luma_addr + mv_offset;
> > - compress_luma_addr = luma_addr + compress_luma_offset;
> > - compress_chroma_addr = luma_addr + compress_chroma_offset;
> > -
> > if (dpb[i].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE)
> > dpb_longterm_e |= BIT(V4L2_HEVC_DPB_ENTRIES_NUM_MAX -
> > 1 - i);
> >
> > - hantro_write_addr(vpu, G2_REF_LUMA_ADDR(i), luma_addr);
> > - hantro_write_addr(vpu, G2_REF_CHROMA_ADDR(i), chroma_addr);
> > - hantro_write_addr(vpu, G2_REF_MV_ADDR(i), mv_addr);
> > - hantro_write_addr(vpu, G2_REF_COMP_LUMA_ADDR(i),
> > compress_luma_addr);
> > - hantro_write_addr(vpu, G2_REF_COMP_CHROMA_ADDR(i),
> > compress_chroma_addr);
> > + ref = vb2_to_hantro_decoded_buf(&vb2_dst->vb2_buf);
> > + hantro_write_addr(vpu, G2_REF_LUMA_ADDR(i), ref-
> > > hevc.luma_addr);
> > + hantro_write_addr(vpu, G2_REF_CHROMA_ADDR(i), ref-
> > > hevc.chroma_addr);
> > + hantro_write_addr(vpu, G2_REF_MV_ADDR(i), ref->hevc.mv_addr);
> > + hantro_write_addr(vpu, G2_REF_COMP_LUMA_ADDR(i), ref-
> > > hevc.rfc_luma_addr);
> > + hantro_write_addr(vpu, G2_REF_COMP_CHROMA_ADDR(i), ref-
> > > hevc.rfc_chroma_addr);
> > }
> >
> > - vb2_dst = hantro_get_dst_buf(ctx);
> > - dst = vb2_to_hantro_decoded_buf(&vb2_dst->vb2_buf);
> > - luma_addr = hantro_get_dec_buf_addr(ctx, &dst->base.vb.vb2_buf);
> > - if (!luma_addr)
> > - return -ENOMEM;
> > -
> > - if (hantro_hevc_add_ref_buf(ctx, decode_params->pic_order_cnt_val,
> > luma_addr))
> > + vb2_dst = hantro_hevc_add_ref_buf(ctx, decode_params-
> > > pic_order_cnt_val);
> > + if (!vb2_dst)
> > return -EINVAL;
> >
> > - chroma_addr = luma_addr + cr_offset;
> > - mv_addr = luma_addr + mv_offset;
> > - compress_luma_addr = luma_addr + compress_luma_offset;
> > - compress_chroma_addr = luma_addr + compress_chroma_offset;
> > -
> > - hantro_write_addr(vpu, G2_REF_LUMA_ADDR(i), luma_addr);
> > - hantro_write_addr(vpu, G2_REF_CHROMA_ADDR(i), chroma_addr);
> > - hantro_write_addr(vpu, G2_REF_MV_ADDR(i), mv_addr);
> > - hantro_write_addr(vpu, G2_REF_COMP_LUMA_ADDR(i), compress_luma_addr);
> > - hantro_write_addr(vpu, G2_REF_COMP_CHROMA_ADDR(i++),
> > compress_chroma_addr);
> > -
> > - hantro_write_addr(vpu, G2_OUT_LUMA_ADDR, luma_addr);
> > - hantro_write_addr(vpu, G2_OUT_CHROMA_ADDR, chroma_addr);
> > - hantro_write_addr(vpu, G2_OUT_MV_ADDR, mv_addr);
> > - hantro_write_addr(vpu, G2_OUT_COMP_LUMA_ADDR, compress_luma_addr);
> > - hantro_write_addr(vpu, G2_OUT_COMP_CHROMA_ADDR,
> > compress_chroma_addr);
> > + ref = vb2_to_hantro_decoded_buf(&vb2_dst->vb2_buf);
> > + hantro_write_addr(vpu, G2_REF_LUMA_ADDR(i), ref->hevc.luma_addr);
> > + hantro_write_addr(vpu, G2_REF_CHROMA_ADDR(i), ref->hevc.chroma_addr);
> > + hantro_write_addr(vpu, G2_REF_MV_ADDR(i), ref->hevc.mv_addr);
> > + hantro_write_addr(vpu, G2_REF_COMP_LUMA_ADDR(i), ref-
> > > hevc.rfc_luma_addr);
> > + hantro_write_addr(vpu, G2_REF_COMP_CHROMA_ADDR(i++), ref-
> > > hevc.rfc_chroma_addr);
> > +
> > + hantro_write_addr(vpu, G2_OUT_LUMA_ADDR, ref->hevc.luma_addr);
> > + hantro_write_addr(vpu, G2_OUT_CHROMA_ADDR, ref->hevc.chroma_addr);
> > + hantro_write_addr(vpu, G2_OUT_MV_ADDR, ref->hevc.mv_addr);
> > + hantro_write_addr(vpu, G2_OUT_COMP_LUMA_ADDR, ref-
> > > hevc.rfc_luma_addr);
> > + hantro_write_addr(vpu, G2_OUT_COMP_CHROMA_ADDR, ref-
> > > hevc.rfc_chroma_addr);
> >
> > for (; i < V4L2_HEVC_DPB_ENTRIES_NUM_MAX; i++) {
> > hantro_write_addr(vpu, G2_REF_LUMA_ADDR(i), 0);
> > diff --git a/drivers/media/platform/verisilicon/hantro_g2_vp9_dec.c
> > b/drivers/media/platform/verisilicon/hantro_g2_vp9_dec.c
> > index 56c79e339030..1e96d0fce72a 100644
> > --- a/drivers/media/platform/verisilicon/hantro_g2_vp9_dec.c
> > +++ b/drivers/media/platform/verisilicon/hantro_g2_vp9_dec.c
> > @@ -129,7 +129,7 @@ static void config_output(struct hantro_ctx *ctx,
> > struct hantro_decoded_buffer *dst,
> > const struct v4l2_ctrl_vp9_frame *dec_params)
> > {
> > - dma_addr_t luma_addr, chroma_addr, mv_addr;
> > + dma_addr_t luma_addr, chroma_addr;
> >
> > hantro_reg_write(ctx->dev, &g2_out_dis, 0);
> > if (!ctx->dev->variant->legacy_regs)
> > @@ -142,9 +142,8 @@ static void config_output(struct hantro_ctx *ctx,
> > hantro_write_addr(ctx->dev, G2_OUT_CHROMA_ADDR, chroma_addr);
> > dst->vp9.chroma_offset = hantro_g2_chroma_offset(ctx);
> >
> > - mv_addr = luma_addr + hantro_g2_motion_vectors_offset(ctx);
> > - hantro_write_addr(ctx->dev, G2_OUT_MV_ADDR, mv_addr);
> > - dst->vp9.mv_offset = hantro_g2_motion_vectors_offset(ctx);
> > + dst->vp9.mv_addr = hantro_mv_get_buf_addr(ctx, dst-
> > > base.vb.vb2_buf.index);
> > + hantro_write_addr(ctx->dev, G2_OUT_MV_ADDR, dst->vp9.mv_addr);
> > }
> >
> > struct hantro_vp9_ref_reg {
> > @@ -215,15 +214,12 @@ static void config_ref_registers(struct hantro_ctx *ctx,
> > .c_base = G2_REF_CHROMA_ADDR(5),
> > },
> > };
> > - dma_addr_t mv_addr;
> >
> > config_ref(ctx, dst, &ref_regs[0], dec_params, dec_params-
> > > last_frame_ts);
> > config_ref(ctx, dst, &ref_regs[1], dec_params, dec_params-
> > > golden_frame_ts);
> > config_ref(ctx, dst, &ref_regs[2], dec_params, dec_params-
> > > alt_frame_ts);
> >
> > - mv_addr = hantro_get_dec_buf_addr(ctx, &mv_ref->base.vb.vb2_buf) +
> > - mv_ref->vp9.mv_offset;
> > - hantro_write_addr(ctx->dev, G2_REF_MV_ADDR(0), mv_addr);
> > + hantro_write_addr(ctx->dev, G2_REF_MV_ADDR(0), mv_ref->vp9.mv_addr);
> >
> > hantro_reg_write(ctx->dev, &vp9_last_sign_bias,
> > dec_params->ref_frame_sign_bias &
> > V4L2_VP9_SIGN_BIAS_LAST ? 1 : 0);
> > diff --git a/drivers/media/platform/verisilicon/hantro_hevc.c
> > b/drivers/media/platform/verisilicon/hantro_hevc.c
> > index 83cd12b0ddd6..7ea1dc57a639 100644
> > --- a/drivers/media/platform/verisilicon/hantro_hevc.c
> > +++ b/drivers/media/platform/verisilicon/hantro_hevc.c
> > @@ -37,39 +37,57 @@ void hantro_hevc_ref_init(struct hantro_ctx *ctx)
> > hevc_dec->ref_bufs_used = 0;
> > }
> >
> > -dma_addr_t hantro_hevc_get_ref_buf(struct hantro_ctx *ctx,
> > - s32 poc)
> > +struct vb2_v4l2_buffer *hantro_hevc_get_ref_buf(struct hantro_ctx *ctx, s32
> > poc)
> > {
> > struct hantro_hevc_dec_hw_ctx *hevc_dec = &ctx->hevc_dec;
> > + struct hantro_decoded_buffer *ref;
> > int i;
> >
> > /* Find the reference buffer in already known ones */
> > for (i = 0; i < NUM_REF_PICTURES; i++) {
> > - if (hevc_dec->ref_bufs_poc[i] == poc) {
> > + ref = vb2_to_hantro_decoded_buf(&hevc_dec->vb2_ref[i]-
> > > vb2_buf);
> > + if (ref->hevc.poc == poc) {
> > hevc_dec->ref_bufs_used |= 1 << i;
> > - return hevc_dec->ref_bufs[i].dma;
> > + return hevc_dec->vb2_ref[i];
> > }
> > }
> >
> > - return 0;
> > + return NULL;
> > }
> >
> > -int hantro_hevc_add_ref_buf(struct hantro_ctx *ctx, int poc, dma_addr_t addr)
> > +struct vb2_v4l2_buffer *hantro_hevc_add_ref_buf(struct hantro_ctx *ctx, int
> > poc)
> > {
> > struct hantro_hevc_dec_hw_ctx *hevc_dec = &ctx->hevc_dec;
> > + struct hantro_decoded_buffer *dst;
> > int i;
> >
> > /* Add a new reference buffer */
> > for (i = 0; i < NUM_REF_PICTURES; i++) {
> > if (!(hevc_dec->ref_bufs_used & 1 << i)) {
> > hevc_dec->ref_bufs_used |= 1 << i;
> > - hevc_dec->ref_bufs_poc[i] = poc;
> > - hevc_dec->ref_bufs[i].dma = addr;
> > - return 0;
> > + hevc_dec->vb2_ref[i] = hantro_get_dst_buf(ctx);
> > + dst = vb2_to_hantro_decoded_buf(&hevc_dec-
> > > vb2_ref[i]->vb2_buf);
> > + dst->hevc.poc = poc;
> > + dst->hevc.luma_addr = hantro_get_dec_buf_addr(ctx,
> > &dst->base.vb.vb2_buf);
> > + dst->hevc.chroma_addr = dst->hevc.luma_addr +
> > hantro_g2_chroma_offset(ctx);
> > + dst->hevc.mv_addr = hantro_mv_get_buf_addr(ctx, dst-
> > > base.vb.vb2_buf.index);
> > + if (ctx->hevc_dec.use_compression) {
> > + dst->hevc.rfc_luma_addr =
> > + hantro_rfc_get_luma_buf_addr(ctx,
> > + dst-
> > > base.vb.vb2_buf.index);
> > + dst->hevc.rfc_chroma_addr =
> > + hantro_rfc_get_chroma_buf_addr(ctx,
> > + dst-
> > > base.vb.vb2_buf.index);
> > + } else {
> > + dst->hevc.rfc_luma_addr = 0;
> > + dst->hevc.rfc_chroma_addr = 0;
> > + }
> > +
> > + return hevc_dec->vb2_ref[i];
> > }
> > }
> >
> > - return -EINVAL;
> > + return NULL;
> > }
> >
> > static int tile_buffer_reallocate(struct hantro_ctx *ctx)
> > diff --git a/drivers/media/platform/verisilicon/hantro_hw.h
> > b/drivers/media/platform/verisilicon/hantro_hw.h
> > index f0e4bca4b2b2..74e20fc82630 100644
> > --- a/drivers/media/platform/verisilicon/hantro_hw.h
> > +++ b/drivers/media/platform/verisilicon/hantro_hw.h
> > @@ -147,8 +147,8 @@ struct hantro_hevc_dec_ctrls {
> > * @tile_bsd: Tile BSD control buffer
> > * @ref_bufs: Internal reference buffers
> > * @scaling_lists: Scaling lists buffer
> > - * @ref_bufs_poc: Internal reference buffers picture order count
> > * @ref_bufs_used: Bitfield of used reference buffers
> > + * @vb2_ref: Reference buffers
> > * @ctrls: V4L2 controls attached to a run
> > * @num_tile_cols_allocated: number of allocated tiles
> > * @use_compression: use reference buffer compression
> > @@ -158,10 +158,9 @@ struct hantro_hevc_dec_hw_ctx {
> > struct hantro_aux_buf tile_filter;
> > struct hantro_aux_buf tile_sao;
> > struct hantro_aux_buf tile_bsd;
> > - struct hantro_aux_buf ref_bufs[NUM_REF_PICTURES];
> > struct hantro_aux_buf scaling_lists;
> > - s32 ref_bufs_poc[NUM_REF_PICTURES];
> > u32 ref_bufs_used;
> > + struct vb2_v4l2_buffer *vb2_ref[NUM_REF_PICTURES];
> > struct hantro_hevc_dec_ctrls ctrls;
> > unsigned int num_tile_cols_allocated;
> > bool use_compression;
> > @@ -456,8 +455,9 @@ void hantro_hevc_dec_exit(struct hantro_ctx *ctx);
> > int hantro_g2_hevc_dec_run(struct hantro_ctx *ctx);
> > int hantro_hevc_dec_prepare_run(struct hantro_ctx *ctx);
> > void hantro_hevc_ref_init(struct hantro_ctx *ctx);
> > -dma_addr_t hantro_hevc_get_ref_buf(struct hantro_ctx *ctx, s32 poc);
> > -int hantro_hevc_add_ref_buf(struct hantro_ctx *ctx, int poc, dma_addr_t
> > addr);
> > +struct vb2_v4l2_buffer *hantro_hevc_get_ref_buf(struct hantro_ctx *ctx, s32
> > poc);
> > +struct vb2_v4l2_buffer *hantro_hevc_add_ref_buf(struct hantro_ctx *ctx, int
> > poc);
> > +int hantro_hevc_get_ref_buf_index(struct hantro_ctx *ctx, s32 poc);
> >
> > int rockchip_vpu981_av1_dec_init(struct hantro_ctx *ctx);
> > void rockchip_vpu981_av1_dec_exit(struct hantro_ctx *ctx);
> > @@ -469,100 +469,7 @@ static inline unsigned short hantro_vp9_num_sbs(unsigned
> > short dimension)
> > return (dimension + 63) / 64;
> > }
> >
> > -static inline size_t
> > -hantro_vp9_mv_size(unsigned int width, unsigned int height)
> > -{
> > - int num_ctbs;
> > -
> > - /*
> > - * There can be up to (CTBs x 64) number of blocks,
> > - * and the motion vector for each block needs 16 bytes.
> > - */
> > - num_ctbs = hantro_vp9_num_sbs(width) * hantro_vp9_num_sbs(height);
> > - return (num_ctbs * 64) * 16;
> > -}
> > -
> > -static inline size_t
> > -hantro_h264_mv_size(unsigned int width, unsigned int height)
> > -{
> > - /*
> > - * A decoded 8-bit 4:2:0 NV12 frame may need memory for up to
> > - * 448 bytes per macroblock with additional 32 bytes on
> > - * multi-core variants.
> > - *
> > - * The H264 decoder needs extra space on the output buffers
> > - * to store motion vectors. This is needed for reference
> > - * frames and only if the format is non-post-processed NV12.
> > - *
> > - * Memory layout is as follow:
> > - *
> > - * +---------------------------+
> > - * | Y-plane 256 bytes x MBs |
> > - * +---------------------------+
> > - * | UV-plane 128 bytes x MBs |
> > - * +---------------------------+
> > - * | MV buffer 64 bytes x MBs |
> > - * +---------------------------+
> > - * | MC sync 32 bytes |
> > - * +---------------------------+
> > - */
> > - return 64 * MB_WIDTH(width) * MB_WIDTH(height) + 32;
> > -}
> > -
> > -static inline size_t
> > -hantro_hevc_mv_size(unsigned int width, unsigned int height)
> > -{
> > - /*
> > - * A CTB can be 64x64, 32x32 or 16x16.
> > - * Allocated memory for the "worse" case: 16x16
> > - */
> > - return width * height / 16;
> > -}
> > -
> > -static inline size_t
> > -hantro_hevc_luma_compressed_size(unsigned int width, unsigned int height)
> > -{
> > - u32 pic_width_in_cbsy =
> > - round_up((width + CBS_LUMA - 1) / CBS_LUMA, CBS_SIZE);
> > - u32 pic_height_in_cbsy = (height + CBS_LUMA - 1) / CBS_LUMA;
> > -
> > - return round_up(pic_width_in_cbsy * pic_height_in_cbsy, CBS_SIZE);
> > -}
> > -
> > -static inline size_t
> > -hantro_hevc_chroma_compressed_size(unsigned int width, unsigned int height)
> > -{
> > - u32 pic_width_in_cbsc =
> > - round_up((width + CBS_CHROMA_W - 1) / CBS_CHROMA_W,
> > CBS_SIZE);
> > - u32 pic_height_in_cbsc = (height / 2 + CBS_CHROMA_H - 1) /
> > CBS_CHROMA_H;
> > -
> > - return round_up(pic_width_in_cbsc * pic_height_in_cbsc, CBS_SIZE);
> > -}
> > -
> > -static inline size_t
> > -hantro_hevc_compressed_size(unsigned int width, unsigned int height)
> > -{
> > - return hantro_hevc_luma_compressed_size(width, height) +
> > - hantro_hevc_chroma_compressed_size(width, height);
> > -}
> > -
> > -static inline unsigned short hantro_av1_num_sbs(unsigned short dimension)
> > -{
> > - return DIV_ROUND_UP(dimension, 64);
> > -}
> > -
> > -static inline size_t
> > -hantro_av1_mv_size(unsigned int width, unsigned int height)
> > -{
> > - size_t num_sbs = hantro_av1_num_sbs(width) *
> > hantro_av1_num_sbs(height);
> > -
> > - return ALIGN(num_sbs * 384, 16) * 2 + 512;
> > -}
> > -
> > size_t hantro_g2_chroma_offset(struct hantro_ctx *ctx);
> > -size_t hantro_g2_motion_vectors_offset(struct hantro_ctx *ctx);
> > -size_t hantro_g2_luma_compress_offset(struct hantro_ctx *ctx);
> > -size_t hantro_g2_chroma_compress_offset(struct hantro_ctx *ctx);
> >
> > int hantro_g1_mpeg2_dec_run(struct hantro_ctx *ctx);
> > int rockchip_vpu2_mpeg2_dec_run(struct hantro_ctx *ctx);
> > diff --git a/drivers/media/platform/verisilicon/hantro_postproc.c
> > b/drivers/media/platform/verisilicon/hantro_postproc.c
> > index e94d1ba5ef10..2409353c16e4 100644
> > --- a/drivers/media/platform/verisilicon/hantro_postproc.c
> > +++ b/drivers/media/platform/verisilicon/hantro_postproc.c
> > @@ -196,36 +196,11 @@ void hantro_postproc_free(struct hantro_ctx *ctx)
> > }
> > }
> >
> > -static unsigned int hantro_postproc_buffer_size(struct hantro_ctx *ctx)
> > -{
> > - unsigned int buf_size;
> > -
> > - buf_size = ctx->ref_fmt.plane_fmt[0].sizeimage;
> > - if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_H264_SLICE)
> > - buf_size += hantro_h264_mv_size(ctx->ref_fmt.width,
> > - ctx->ref_fmt.height);
> > - else if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_VP9_FRAME)
> > - buf_size += hantro_vp9_mv_size(ctx->ref_fmt.width,
> > - ctx->ref_fmt.height);
> > - else if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_HEVC_SLICE) {
> > - buf_size += hantro_hevc_mv_size(ctx->ref_fmt.width,
> > - ctx->ref_fmt.height);
> > - if (ctx->hevc_dec.use_compression)
> > - buf_size += hantro_hevc_compressed_size(ctx-
> > > ref_fmt.width,
> > - ctx-
> > > ref_fmt.height);
> > - }
> > - else if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_AV1_FRAME)
> > - buf_size += hantro_av1_mv_size(ctx->ref_fmt.width,
> > - ctx->ref_fmt.height);
> > -
> > - return buf_size;
> > -}
> > -
> > static int hantro_postproc_alloc(struct hantro_ctx *ctx, int index)
> > {
> > struct hantro_dev *vpu = ctx->dev;
> > struct hantro_aux_buf *priv = &ctx->postproc.dec_q[index];
> > - unsigned int buf_size = hantro_postproc_buffer_size(ctx);
> > + unsigned int buf_size = ctx->ref_fmt.plane_fmt[0].sizeimage;
> >
> > if (!buf_size)
> > return -EINVAL;
> > @@ -267,7 +242,7 @@ dma_addr_t
> > hantro_postproc_get_dec_buf_addr(struct hantro_ctx *ctx, int index)
> > {
> > struct hantro_aux_buf *priv = &ctx->postproc.dec_q[index];
> > - unsigned int buf_size = hantro_postproc_buffer_size(ctx);
> > + unsigned int buf_size = ctx->ref_fmt.plane_fmt[0].sizeimage;
> > struct hantro_dev *vpu = ctx->dev;
> > int ret;
> >
> > diff --git a/drivers/media/platform/verisilicon/hantro_v4l2.c
> > b/drivers/media/platform/verisilicon/hantro_v4l2.c
> > index fcf3bd9bcda2..6a876142c224 100644
> > --- a/drivers/media/platform/verisilicon/hantro_v4l2.c
> > +++ b/drivers/media/platform/verisilicon/hantro_v4l2.c
> > @@ -36,6 +36,9 @@ static int hantro_set_fmt_out(struct hantro_ctx *ctx,
> > static int hantro_set_fmt_cap(struct hantro_ctx *ctx,
> > struct v4l2_pix_format_mplane *pix_mp);
> >
> > +static void hantro_mv_free(struct hantro_ctx *ctx);
> > +static void hantro_rfc_free(struct hantro_ctx *ctx);
> > +
> > static const struct hantro_fmt *
> > hantro_get_formats(const struct hantro_ctx *ctx, unsigned int *num_fmts, bool
> > need_postproc)
> > {
> > @@ -362,26 +365,6 @@ static int hantro_try_fmt(const struct hantro_ctx *ctx,
> > /* Fill remaining fields */
> > v4l2_fill_pixfmt_mp(pix_mp, fmt->fourcc, pix_mp->width,
> > pix_mp->height);
> > - if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_H264_SLICE &&
> > - !hantro_needs_postproc(ctx, fmt))
> > - pix_mp->plane_fmt[0].sizeimage +=
> > - hantro_h264_mv_size(pix_mp->width,
> > - pix_mp->height);
> > - else if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_VP9_FRAME
> > &&
> > - !hantro_needs_postproc(ctx, fmt))
> > - pix_mp->plane_fmt[0].sizeimage +=
> > - hantro_vp9_mv_size(pix_mp->width,
> > - pix_mp->height);
> > - else if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_HEVC_SLICE
> > &&
> > - !hantro_needs_postproc(ctx, fmt))
> > - pix_mp->plane_fmt[0].sizeimage +=
> > - hantro_hevc_mv_size(pix_mp->width,
> > - pix_mp->height);
> > - else if (ctx->vpu_src_fmt->fourcc == V4L2_PIX_FMT_AV1_FRAME
> > &&
> > - !hantro_needs_postproc(ctx, fmt))
> > - pix_mp->plane_fmt[0].sizeimage +=
> > - hantro_av1_mv_size(pix_mp->width,
> > - pix_mp->height);
> > } else if (!pix_mp->plane_fmt[0].sizeimage) {
> > /*
> > * For coded formats the application can specify
> > @@ -999,6 +982,9 @@ static void hantro_stop_streaming(struct vb2_queue *q)
> > if (V4L2_TYPE_IS_OUTPUT(q->type) &&
> > v4l2_m2m_has_stopped(ctx->fh.m2m_ctx))
> > v4l2_event_queue_fh(&ctx->fh, &hantro_eos_event);
> > +
> > + hantro_mv_free(ctx);
> > + hantro_rfc_free(ctx);
> > }
> >
> > static void hantro_buf_request_complete(struct vb2_buffer *vb)
> > @@ -1025,3 +1011,291 @@ const struct vb2_ops hantro_queue_ops = {
> > .start_streaming = hantro_start_streaming,
> > .stop_streaming = hantro_stop_streaming,
> > };
> > +
> > +static size_t
> > +hantro_vp9_mv_size(unsigned int width, unsigned int height)
> > +{
> > + int num_ctbs;
> > +
> > + /*
> > + * There can be up to (CTBs x 64) number of blocks,
> > + * and the motion vector for each block needs 16 bytes.
> > + */
> > + num_ctbs = hantro_vp9_num_sbs(width) * hantro_vp9_num_sbs(height);
> > + return (num_ctbs * 64) * 16;
> > +}
> > +
> > +static size_t
> > +hantro_h264_mv_size(unsigned int width, unsigned int height)
> > +{
> > + /*
> > + * A decoded 8-bit 4:2:0 NV12 frame may need memory for up to
> > + * 448 bytes per macroblock with additional 32 bytes on
> > + * multi-core variants.
> > + *
> > + * The H264 decoder needs extra space on the output buffers
> > + * to store motion vectors. This is needed for reference
> > + * frames and only if the format is non-post-processed NV12.
> > + *
> > + * Memory layout is as follow:
> > + *
> > + * +---------------------------+
> > + * | Y-plane 256 bytes x MBs |
> > + * +---------------------------+
> > + * | UV-plane 128 bytes x MBs |
> > + * +---------------------------+
> > + * | MV buffer 64 bytes x MBs |
> > + * +---------------------------+
> > + * | MC sync 32 bytes |
> > + * +---------------------------+
> > + */
> > + return 64 * MB_WIDTH(width) * MB_WIDTH(height) + 32;
> > +}
> > +
> > +static size_t
> > +hantro_hevc_mv_size(unsigned int width, unsigned int height, int depth)
> > +{
> > + /*
> > + * A CTB can be 64x64, 32x32 or 16x16.
> > + * Allocated memory for the "worse" case: 16x16
> > + */
> > + return DIV_ROUND_UP(width * height * depth / 8, 16);
> > +}
> > +
> > +static inline unsigned short hantro_av1_num_sbs(unsigned short dimension)
> > +{
> > + return DIV_ROUND_UP(dimension, 64);
> > +}
> > +
> > +static size_t
> > +hantro_av1_mv_size(unsigned int width, unsigned int height)
> > +{
> > + size_t num_sbs = hantro_av1_num_sbs(width) *
> > hantro_av1_num_sbs(height);
> > +
> > + return ALIGN(num_sbs * 384, 16) * 2 + 512;
> > +}
> > +
> > +static void hantro_mv_free(struct hantro_ctx *ctx)
> > +{
> > + struct hantro_dev *vpu = ctx->dev;
> > + int i;
> > +
> > + for (i = 0; i < MAX_MV_BUFFERS; i++) {
> > + struct hantro_aux_buf *mv = &ctx->dec_mv[i];
> > +
> > + if (!mv->cpu)
> > + continue;
> > +
> > + dma_free_attrs(vpu->dev, mv->size, mv->cpu,
> > + mv->dma, mv->attrs);
> > + mv->cpu = NULL;
> > + }
> > +}
> > +
> > +static unsigned int hantro_mv_buffer_size(struct hantro_ctx *ctx)
> > +{
> > + struct hantro_dev *vpu = ctx->dev;
> > + int fourcc = ctx->vpu_src_fmt->fourcc;
> > + int width = ctx->ref_fmt.width;
> > + int height = ctx->ref_fmt.height;
> > +
> > + switch (fourcc) {
> > + case V4L2_PIX_FMT_H264_SLICE:
> > + return hantro_h264_mv_size(width, height);
> > + case V4L2_PIX_FMT_VP9_FRAME:
> > + return hantro_vp9_mv_size(width, height);
> > + case V4L2_PIX_FMT_HEVC_SLICE:
> > + return hantro_hevc_mv_size(width, height, ctx->bit_depth);
> > + case V4L2_PIX_FMT_AV1_FRAME:
> > + return hantro_av1_mv_size(width, height);
> > + }
> > +
> > + /* Should not happen */
> > + dev_warn(vpu->dev, "Invalid motion vectors size\n");
> > + return 0;
> > +}
> > +
> > +static int hantro_mv_buffer_alloc(struct hantro_ctx *ctx, int index)
> > +{
> > + struct hantro_dev *vpu = ctx->dev;
> > + struct hantro_aux_buf *mv = &ctx->dec_mv[index];
> > + unsigned int buf_size = hantro_mv_buffer_size(ctx);
> > +
> > + if (!buf_size)
> > + return -EINVAL;
> > +
> > + /*
> > + * Motion vectors buffers are only read and write by the
> > + * hardware so no mapping is needed.
> > + */
> > + mv->attrs = DMA_ATTR_NO_KERNEL_MAPPING;
> > + mv->cpu = dma_alloc_attrs(vpu->dev, buf_size, &mv->dma,
> > + GFP_KERNEL, mv->attrs);
> > + if (!mv->cpu)
> > + return -ENOMEM;
> > + mv->size = buf_size;
> > +
> > + return 0;
> > +}
> > +
> > +dma_addr_t
> > +hantro_mv_get_buf_addr(struct hantro_ctx *ctx, int index)
> > +{
> > + struct hantro_aux_buf *mv = &ctx->dec_mv[index];
> > + unsigned int buf_size = hantro_mv_buffer_size(ctx);
> > + struct hantro_dev *vpu = ctx->dev;
> > + int ret;
> > +
> > + if (mv->size < buf_size && mv->cpu) {
> > + /* buffer is too small, release it */
> > + dma_free_attrs(vpu->dev, mv->size, mv->cpu,
> > + mv->dma, mv->attrs);
> > + mv->cpu = NULL;
> > + }
> > +
> > + if (!mv->cpu) {
> > + /* buffer not already allocated, try getting a new one */
> > + ret = hantro_mv_buffer_alloc(ctx, index);
> > + if (ret)
> > + return 0;
> > + }
> > +
> > + if (!mv->cpu)
> > + return 0;
> > +
> > + return mv->dma;
> > +}
> > +
> > +static inline size_t
> > +hantro_hevc_luma_compressed_size(unsigned int width, unsigned int height)
> > +{
> > + u32 pic_width_in_cbsy =
> > + round_up((width + CBS_LUMA - 1) / CBS_LUMA, CBS_SIZE);
> > + u32 pic_height_in_cbsy = (height + CBS_LUMA - 1) / CBS_LUMA;
> > +
> > + return round_up(pic_width_in_cbsy * pic_height_in_cbsy, CBS_SIZE);
> > +}
> > +
> > +static inline size_t
> > +hantro_hevc_chroma_compressed_size(unsigned int width, unsigned int height)
> > +{
> > + u32 pic_width_in_cbsc =
> > + round_up((width + CBS_CHROMA_W - 1) / CBS_CHROMA_W,
> > CBS_SIZE);
> > + u32 pic_height_in_cbsc = (height / 2 + CBS_CHROMA_H - 1) /
> > CBS_CHROMA_H;
> > +
> > + return round_up(pic_width_in_cbsc * pic_height_in_cbsc, CBS_SIZE);
> > +}
> > +
> > +static inline size_t
> > +hantro_hevc_compressed_size(unsigned int width, unsigned int height)
> > +{
> > + return hantro_hevc_luma_compressed_size(width, height) +
> > + hantro_hevc_chroma_compressed_size(width, height);
> > +}
> > +
> > +static void hantro_rfc_free(struct hantro_ctx *ctx)
> > +{
> > + struct hantro_dev *vpu = ctx->dev;
> > + int i;
> > +
> > + for (i = 0; i < MAX_MV_BUFFERS; i++) {
> > + struct hantro_aux_buf *rfc = &ctx->dec_rfc[i];
> > +
> > + if (!rfc->cpu)
> > + continue;
> > +
> > + dma_free_attrs(vpu->dev, rfc->size, rfc->cpu,
> > + rfc->dma, rfc->attrs);
> > + rfc->cpu = NULL;
> > + }
> > +}
> > +
> > +static unsigned int hantro_rfc_buffer_size(struct hantro_ctx *ctx)
> > +{
> > + struct hantro_dev *vpu = ctx->dev;
> > + int fourcc = ctx->vpu_src_fmt->fourcc;
> > + int width = ctx->ref_fmt.width;
> > + int height = ctx->ref_fmt.height;
> > +
> > + switch (fourcc) {
> > + case V4L2_PIX_FMT_HEVC_SLICE:
> > + return hantro_hevc_compressed_size(width, height);
> > + }
> > +
> > + /* Should not happen */
> > + dev_warn(vpu->dev, "Invalid rfc size\n");
> > + return 0;
> > +}
> > +
> > +static int hantro_rfc_buffer_alloc(struct hantro_ctx *ctx, int index)
> > +{
> > + struct hantro_dev *vpu = ctx->dev;
> > + struct hantro_aux_buf *rfc = &ctx->dec_rfc[index];
> > + unsigned int buf_size = hantro_rfc_buffer_size(ctx);
> > +
> > + if (!buf_size)
> > + return -EINVAL;
> > +
> > + /*
> > + * RFC buffers are only read and write by the
> > + * hardware so no mapping is needed.
> > + */
> > + rfc->attrs = DMA_ATTR_NO_KERNEL_MAPPING;
> > + rfc->cpu = dma_alloc_attrs(vpu->dev, buf_size, &rfc->dma,
> > + GFP_KERNEL, rfc->attrs);
> > + if (!rfc->cpu)
> > + return -ENOMEM;
> > + rfc->size = buf_size;
> > +
> > + return 0;
> > +}
> > +
> > +dma_addr_t
> > +hantro_rfc_get_luma_buf_addr(struct hantro_ctx *ctx, int index)
> > +{
> > + struct hantro_aux_buf *rfc = &ctx->dec_rfc[index];
> > + unsigned int buf_size = hantro_rfc_buffer_size(ctx);
> > + struct hantro_dev *vpu = ctx->dev;
> > + int ret;
> > +
> > + if (rfc->size < buf_size && rfc->cpu) {
> > + /* buffer is too small, release it */
> > + dma_free_attrs(vpu->dev, rfc->size, rfc->cpu,
> > + rfc->dma, rfc->attrs);
> > + rfc->cpu = NULL;
> > + }
> > +
> > + if (!rfc->cpu) {
> > + /* buffer not already allocated, try getting a new one */
> > + ret = hantro_rfc_buffer_alloc(ctx, index);
> > + if (ret)
> > + return 0;
> > + }
> > +
> > + if (!rfc->cpu)
> > + return 0;
> > +
> > + return rfc->dma;
> > +}
> > +
> > +dma_addr_t
> > +hantro_rfc_get_chroma_buf_addr(struct hantro_ctx *ctx, int index)
> > +{
> > + dma_addr_t luma_addr = hantro_rfc_get_luma_buf_addr(ctx, index);
> > + struct hantro_dev *vpu = ctx->dev;
> > + int fourcc = ctx->vpu_src_fmt->fourcc;
> > + int width = ctx->ref_fmt.width;
> > + int height = ctx->ref_fmt.height;
> > +
> > + if (!luma_addr)
> > + return -EINVAL;
> > +
> > + switch (fourcc) {
> > + case V4L2_PIX_FMT_HEVC_SLICE:
> > + return luma_addr + hantro_hevc_luma_compressed_size(width,
> > height);
> > + }
> > +
> > + /* Should not happen */
> > + dev_warn(vpu->dev, "Invalid rfc chroma address\n");
> > + return 0;
> > +}
> > diff --git a/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
> > b/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
> > index c1ada14df4c3..21da8ddfc4b3 100644
> > --- a/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
> > +++ b/drivers/media/platform/verisilicon/rockchip_vpu981_hw_av1_dec.c
> > @@ -62,7 +62,7 @@ rockchip_vpu981_av1_dec_set_ref(struct hantro_ctx *ctx, int
> > ref, int idx,
> > const struct v4l2_ctrl_av1_frame *frame = ctrls->frame;
> > struct hantro_dev *vpu = ctx->dev;
> > struct hantro_decoded_buffer *dst;
> > - dma_addr_t luma_addr, chroma_addr, mv_addr = 0;
> > + dma_addr_t luma_addr, chroma_addr = 0;
> > int cur_width = frame->frame_width_minus_1 + 1;
> > int cur_height = frame->frame_height_minus_1 + 1;
> > int scale_width =
> > @@ -120,11 +120,10 @@ rockchip_vpu981_av1_dec_set_ref(struct hantro_ctx *ctx,
> > int ref, int idx,
> > dst = vb2_to_hantro_decoded_buf(&av1_dec->frame_refs[idx].vb2_ref-
> > > vb2_buf);
> > luma_addr = hantro_get_dec_buf_addr(ctx, &dst->base.vb.vb2_buf);
> > chroma_addr = luma_addr + dst->av1.chroma_offset;
> > - mv_addr = luma_addr + dst->av1.mv_offset;
> >
> > hantro_write_addr(vpu, AV1_REFERENCE_Y(ref), luma_addr);
> > hantro_write_addr(vpu, AV1_REFERENCE_CB(ref), chroma_addr);
> > - hantro_write_addr(vpu, AV1_REFERENCE_MV(ref), mv_addr);
> > + hantro_write_addr(vpu, AV1_REFERENCE_MV(ref), dst->av1.mv_addr);
> >
> > return (scale_width != (1 << AV1_REF_SCALE_SHIFT)) ||
> > (scale_height != (1 << AV1_REF_SCALE_SHIFT));
> > @@ -180,11 +179,10 @@ static void
> > rockchip_vpu981_av1_dec_set_segmentation(struct hantro_ctx *ctx)
> > if (idx >= 0) {
> > dma_addr_t luma_addr, mv_addr = 0;
> > struct hantro_decoded_buffer *seg;
> > - size_t mv_offset = hantro_av1_chroma_size(ctx);
> >
> > seg = vb2_to_hantro_decoded_buf(&av1_dec-
> > > frame_refs[idx].vb2_ref->vb2_buf);
> > luma_addr = hantro_get_dec_buf_addr(ctx, &seg-
> > > base.vb.vb2_buf);
> > - mv_addr = luma_addr + mv_offset;
> > + mv_addr = hantro_mv_get_buf_addr(ctx, seg-
> > > base.vb.vb2_buf.index);
> >
> > hantro_write_addr(vpu, AV1_SEGMENTATION, mv_addr);
> > hantro_reg_write(vpu, &av1_use_temporal3_mvs, 1);
> > @@ -1350,22 +1348,20 @@ rockchip_vpu981_av1_dec_set_output_buffer(struct
> > hantro_ctx *ctx)
> > struct hantro_dev *vpu = ctx->dev;
> > struct hantro_decoded_buffer *dst;
> > struct vb2_v4l2_buffer *vb2_dst;
> > - dma_addr_t luma_addr, chroma_addr, mv_addr = 0;
> > + dma_addr_t luma_addr, chroma_addr = 0;
> > size_t cr_offset = hantro_av1_luma_size(ctx);
> > - size_t mv_offset = hantro_av1_chroma_size(ctx);
> >
> > vb2_dst = av1_dec->frame_refs[av1_dec->current_frame_index].vb2_ref;
> > dst = vb2_to_hantro_decoded_buf(&vb2_dst->vb2_buf);
> > luma_addr = hantro_get_dec_buf_addr(ctx, &dst->base.vb.vb2_buf);
> > chroma_addr = luma_addr + cr_offset;
> > - mv_addr = luma_addr + mv_offset;
> >
> > dst->av1.chroma_offset = cr_offset;
> > - dst->av1.mv_offset = mv_offset;
> > + dst->av1.mv_addr = hantro_mv_get_buf_addr(ctx, dst-
> > > base.vb.vb2_buf.index);
> >
> > hantro_write_addr(vpu, AV1_TILE_OUT_LU, luma_addr);
> > hantro_write_addr(vpu, AV1_TILE_OUT_CH, chroma_addr);
> > - hantro_write_addr(vpu, AV1_TILE_OUT_MV, mv_addr);
> > + hantro_write_addr(vpu, AV1_TILE_OUT_MV, dst->av1.mv_addr);
> > }
> >
> > int rockchip_vpu981_av1_dec_run(struct hantro_ctx *ctx)
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* Re: [PATCH v3 1/4] media: rkvdec: Introduce a global bitwriter helper
From: Nicolas Dufresne @ 2026-04-29 18:17 UTC (permalink / raw)
To: Detlev Casanova, Ezequiel Garcia, Mauro Carvalho Chehab,
Heiko Stuebner, Nathan Chancellor, Nick Desaulniers,
Bill Wendling, Justin Stitt, Jonas Karlman
Cc: linux-kernel, linux-media, linux-rockchip, linux-arm-kernel, llvm,
kernel
In-Reply-To: <20260402-rkvdec-use-bitwriter-v3-1-2072474ceaf4@collabora.com>
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Le jeudi 02 avril 2026 à 10:06 -0400, Detlev Casanova a écrit :
> The use of structures with bitfields is good when the values are
> somewhat aligned.
> More mis-alignement means that compilers need to do more gymanstics
gymnastics
> to edit the fields values.
>
> Some cases have been reported with CLang on specific architectures
> like armhf and hexagon, where the compiler would allocate a bigger
> local stack than needed or even completely freeze during compilation.
>
> Some fixes have been provided to ease the issues, but the real fix
> here is to use a bitwriter instead of heavily unaligned bitfields.
>
> This is a preparation commit to provide a global bitwriter interface
> for the whole driver.
>
> Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
> ---
> .../platform/rockchip/rkvdec/rkvdec-bitwriter.h | 39 ++++++++++++++++++++++
> 1 file changed, 39 insertions(+)
>
> diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-bitwriter.h b/drivers/media/platform/rockchip/rkvdec/rkvdec-bitwriter.h
> new file mode 100644
> index 000000000000..2a5c271ade91
> --- /dev/null
> +++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-bitwriter.h
> @@ -0,0 +1,39 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Rockchip Video Decoder bit writer
> + *
> + * Copyright (C) 2026 Collabora, Ltd.
> + * Detlev Casanova <detlev.casanova@collabora.com>
> + * Copyright (C) 2019 Collabora, Ltd.
> + * Boris Brezillon <boris.brezillon@collabora.com>
nit: indent it the same for for your name.
I will do the edits if I find now other issues in the series.
Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
> + */
> +
> +#ifndef RKVDEC_BIT_WRITER_H_
> +#define RKVDEC_BIT_WRITER_H_
> +
> +#include <linux/types.h>
> +#include <linux/bits.h>
> +
> +struct rkvdec_bw_field {
> + u16 offset;
> + u8 len;
> +};
> +
> +#define BW_FIELD(_offset, _len) ((struct rkvdec_bw_field){ _offset, _len })
> +
> +static inline void rkvdec_set_bw_field(u32 *buf, struct rkvdec_bw_field field, u32 value)
> +{
> + u8 bit = field.offset % 32;
> + u16 word = field.offset / 32;
> + u64 mask = GENMASK_ULL(bit + field.len - 1, bit);
> + u64 val = ((u64)value << bit) & mask;
> +
> + buf[word] &= ~mask;
> + buf[word] |= val;
> + if (bit + field.len > 32) {
> + buf[word + 1] &= ~(mask >> 32);
> + buf[word + 1] |= val >> 32;
> + }
> +}
> +
> +#endif /* RKVDEC_BIT_WRITER_H_ */
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^ permalink raw reply
* Re: [PATCH v7 2/3] dt-bindings: hwmon: emc2305: Add fan-shutdown-percent property
From: Conor Dooley @ 2026-04-29 18:18 UTC (permalink / raw)
To: florin.leotescu
Cc: Guenter Roeck, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Michael Shych, linux-hwmon, devicetree, linux-kernel,
daniel.baluta, viorel.suman, linux-arm-kernel, imx, festevam,
Florin Leotescu
In-Reply-To: <20260429065955.2113012-3-florin.leotescu@oss.nxp.com>
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On Wed, Apr 29, 2026 at 09:59:54AM +0300, florin.leotescu@oss.nxp.com wrote:
> From: Florin Leotescu <florin.leotescu@nxp.com>
>
> The EMC2305 fan controller supports multiple independent PWM fan
> outputs. Some systems require fans to enter a defined safe state
> during system shutdown or reboot handoff, until firmware or the next
> boot stage reconfigures the controller.
>
> Add an optional "fan-shutdown-percent" property to fan child nodes
> allowing the PWM duty cycle applied during shutdown to be configured
> per fan output.
>
> Signed-off-by: Florin Leotescu <florin.leotescu@nxp.com>
Why didn't you pick up my tag from here:
https://lore.kernel.org/all/20260407-slang-scoff-795164352c62@spud/
> ---
> .../devicetree/bindings/hwmon/microchip,emc2305.yaml | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/hwmon/microchip,emc2305.yaml b/Documentation/devicetree/bindings/hwmon/microchip,emc2305.yaml
> index d3f06ebc19fa..8c2548539d7f 100644
> --- a/Documentation/devicetree/bindings/hwmon/microchip,emc2305.yaml
> +++ b/Documentation/devicetree/bindings/hwmon/microchip,emc2305.yaml
> @@ -54,6 +54,12 @@ patternProperties:
> The fan number used to determine the associated PWM channel.
> maxItems: 1
>
> + fan-shutdown-percent:
> + description:
> + PWM duty cycle in percent applied to the fan during shutdown.
> + minimum: 0
> + maximum: 100
> +
> required:
> - reg
>
> @@ -80,12 +86,14 @@ examples:
> fan@0 {
> reg = <0x0>;
> pwms = <&fan_controller 26000 PWM_POLARITY_INVERTED 1>;
> + fan-shutdown-percent = <100>;
> #cooling-cells = <2>;
> };
>
> fan@1 {
> reg = <0x1>;
> pwms = <&fan_controller 26000 0 1>;
> + fan-shutdown-percent = <50>;
> #cooling-cells = <2>;
> };
>
> --
> 2.34.1
>
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^ permalink raw reply
* Re: [PATCH v3 2/4] media: rkvdec: Use the global bitwriter instead of local one
From: Nicolas Dufresne @ 2026-04-29 18:19 UTC (permalink / raw)
To: Detlev Casanova, Ezequiel Garcia, Mauro Carvalho Chehab,
Heiko Stuebner, Nathan Chancellor, Nick Desaulniers,
Bill Wendling, Justin Stitt, Jonas Karlman
Cc: linux-kernel, linux-media, linux-rockchip, linux-arm-kernel, llvm,
kernel
In-Reply-To: <20260402-rkvdec-use-bitwriter-v3-2-2072474ceaf4@collabora.com>
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Le jeudi 02 avril 2026 à 10:06 -0400, Detlev Casanova a écrit :
> Both rkvdec-h264.c and rkvdec-hevc.c use their own bitwriter
> function and macros.
>
> Move to using the global one introduced before.
>
> Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
> ---
> .../media/platform/rockchip/rkvdec/rkvdec-h264.c | 109 ++++++-------
> .../media/platform/rockchip/rkvdec/rkvdec-hevc.c | 171 +++++++++------------
> 2 files changed, 119 insertions(+), 161 deletions(-)
>
> diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c
> index d3202cecb988..ffa606038192 100644
> --- a/drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c
> +++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-h264.c
> @@ -16,6 +16,7 @@
> #include "rkvdec-regs.h"
> #include "rkvdec-cabac.h"
> #include "rkvdec-h264-common.h"
> +#include "rkvdec-bitwriter.h"
>
> /* Size with u32 units. */
> #define RKV_CABAC_INIT_BUFFER_SIZE (3680 + 128)
> @@ -25,56 +26,48 @@ struct rkvdec_sps_pps_packet {
> u32 info[8];
> };
>
> -struct rkvdec_ps_field {
> - u16 offset;
> - u8 len;
> -};
> -
> -#define PS_FIELD(_offset, _len) \
> - ((struct rkvdec_ps_field){ _offset, _len })
> -
> -#define SEQ_PARAMETER_SET_ID PS_FIELD(0, 4)
> -#define PROFILE_IDC PS_FIELD(4, 8)
> -#define CONSTRAINT_SET3_FLAG PS_FIELD(12, 1)
> -#define CHROMA_FORMAT_IDC PS_FIELD(13, 2)
> -#define BIT_DEPTH_LUMA PS_FIELD(15, 3)
> -#define BIT_DEPTH_CHROMA PS_FIELD(18, 3)
> -#define QPPRIME_Y_ZERO_TRANSFORM_BYPASS_FLAG PS_FIELD(21, 1)
> -#define LOG2_MAX_FRAME_NUM_MINUS4 PS_FIELD(22, 4)
> -#define MAX_NUM_REF_FRAMES PS_FIELD(26, 5)
> -#define PIC_ORDER_CNT_TYPE PS_FIELD(31, 2)
> -#define LOG2_MAX_PIC_ORDER_CNT_LSB_MINUS4 PS_FIELD(33, 4)
> -#define DELTA_PIC_ORDER_ALWAYS_ZERO_FLAG PS_FIELD(37, 1)
> -#define PIC_WIDTH_IN_MBS PS_FIELD(38, 9)
> -#define PIC_HEIGHT_IN_MBS PS_FIELD(47, 9)
> -#define FRAME_MBS_ONLY_FLAG PS_FIELD(56, 1)
> -#define MB_ADAPTIVE_FRAME_FIELD_FLAG PS_FIELD(57, 1)
> -#define DIRECT_8X8_INFERENCE_FLAG PS_FIELD(58, 1)
> -#define MVC_EXTENSION_ENABLE PS_FIELD(59, 1)
> -#define NUM_VIEWS PS_FIELD(60, 2)
> -#define VIEW_ID(i) PS_FIELD(62 + ((i) * 10), 10)
> -#define NUM_ANCHOR_REFS_L(i) PS_FIELD(82 + ((i) * 11), 1)
> -#define ANCHOR_REF_L(i) PS_FIELD(83 + ((i) * 11), 10)
> -#define NUM_NON_ANCHOR_REFS_L(i) PS_FIELD(104 + ((i) * 11), 1)
> -#define NON_ANCHOR_REFS_L(i) PS_FIELD(105 + ((i) * 11), 10)
> -#define PIC_PARAMETER_SET_ID PS_FIELD(128, 8)
> -#define PPS_SEQ_PARAMETER_SET_ID PS_FIELD(136, 5)
> -#define ENTROPY_CODING_MODE_FLAG PS_FIELD(141, 1)
> -#define BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT_FLAG PS_FIELD(142, 1)
> -#define NUM_REF_IDX_L_DEFAULT_ACTIVE_MINUS1(i) PS_FIELD(143 + ((i) * 5), 5)
> -#define WEIGHTED_PRED_FLAG PS_FIELD(153, 1)
> -#define WEIGHTED_BIPRED_IDC PS_FIELD(154, 2)
> -#define PIC_INIT_QP_MINUS26 PS_FIELD(156, 7)
> -#define PIC_INIT_QS_MINUS26 PS_FIELD(163, 6)
> -#define CHROMA_QP_INDEX_OFFSET PS_FIELD(169, 5)
> -#define DEBLOCKING_FILTER_CONTROL_PRESENT_FLAG PS_FIELD(174, 1)
> -#define CONSTRAINED_INTRA_PRED_FLAG PS_FIELD(175, 1)
> -#define REDUNDANT_PIC_CNT_PRESENT PS_FIELD(176, 1)
> -#define TRANSFORM_8X8_MODE_FLAG PS_FIELD(177, 1)
> -#define SECOND_CHROMA_QP_INDEX_OFFSET PS_FIELD(178, 5)
> -#define SCALING_LIST_ENABLE_FLAG PS_FIELD(183, 1)
> -#define SCALING_LIST_ADDRESS PS_FIELD(184, 32)
> -#define IS_LONG_TERM(i) PS_FIELD(216 + (i), 1)
> +#define SEQ_PARAMETER_SET_ID BW_FIELD(0, 4)
> +#define PROFILE_IDC BW_FIELD(4, 8)
> +#define CONSTRAINT_SET3_FLAG BW_FIELD(12, 1)
> +#define CHROMA_FORMAT_IDC BW_FIELD(13, 2)
> +#define BIT_DEPTH_LUMA BW_FIELD(15, 3)
> +#define BIT_DEPTH_CHROMA BW_FIELD(18, 3)
> +#define QPPRIME_Y_ZERO_TRANSFORM_BYPASS_FLAG BW_FIELD(21, 1)
> +#define LOG2_MAX_FRAME_NUM_MINUS4 BW_FIELD(22, 4)
> +#define MAX_NUM_REF_FRAMES BW_FIELD(26, 5)
> +#define PIC_ORDER_CNT_TYPE BW_FIELD(31, 2)
> +#define LOG2_MAX_PIC_ORDER_CNT_LSB_MINUS4 BW_FIELD(33, 4)
> +#define DELTA_PIC_ORDER_ALWAYS_ZERO_FLAG BW_FIELD(37, 1)
> +#define PIC_WIDTH_IN_MBS BW_FIELD(38, 9)
> +#define PIC_HEIGHT_IN_MBS BW_FIELD(47, 9)
> +#define FRAME_MBS_ONLY_FLAG BW_FIELD(56, 1)
> +#define MB_ADAPTIVE_FRAME_FIELD_FLAG BW_FIELD(57, 1)
> +#define DIRECT_8X8_INFERENCE_FLAG BW_FIELD(58, 1)
> +#define MVC_EXTENSION_ENABLE BW_FIELD(59, 1)
> +#define NUM_VIEWS BW_FIELD(60, 2)
> +#define VIEW_ID(i) BW_FIELD(62 + ((i) * 10), 10)
> +#define NUM_ANCHOR_REFS_L(i) BW_FIELD(82 + ((i) * 11), 1)
> +#define ANCHOR_REF_L(i) BW_FIELD(83 + ((i) * 11), 10)
> +#define NUM_NON_ANCHOR_REFS_L(i) BW_FIELD(104 + ((i) * 11), 1)
> +#define NON_ANCHOR_REFS_L(i) BW_FIELD(105 + ((i) * 11), 10)
> +#define PIC_PARAMETER_SET_ID BW_FIELD(128, 8)
> +#define PPS_SEQ_PARAMETER_SET_ID BW_FIELD(136, 5)
> +#define ENTROPY_CODING_MODE_FLAG BW_FIELD(141, 1)
> +#define BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT_FLAG BW_FIELD(142, 1)
> +#define NUM_REF_IDX_L_DEFAULT_ACTIVE_MINUS1(i) BW_FIELD(143 + ((i) * 5), 5)
> +#define WEIGHTED_PRED_FLAG BW_FIELD(153, 1)
> +#define WEIGHTED_BIPRED_IDC BW_FIELD(154, 2)
> +#define PIC_INIT_QP_MINUS26 BW_FIELD(156, 7)
> +#define PIC_INIT_QS_MINUS26 BW_FIELD(163, 6)
> +#define CHROMA_QP_INDEX_OFFSET BW_FIELD(169, 5)
> +#define DEBLOCKING_FILTER_CONTROL_PRESENT_FLAG BW_FIELD(174, 1)
> +#define CONSTRAINED_INTRA_PRED_FLAG BW_FIELD(175, 1)
> +#define REDUNDANT_PIC_CNT_PRESENT BW_FIELD(176, 1)
> +#define TRANSFORM_8X8_MODE_FLAG BW_FIELD(177, 1)
> +#define SECOND_CHROMA_QP_INDEX_OFFSET BW_FIELD(178, 5)
> +#define SCALING_LIST_ENABLE_FLAG BW_FIELD(183, 1)
> +#define SCALING_LIST_ADDRESS BW_FIELD(184, 32)
> +#define IS_LONG_TERM(i) BW_FIELD(216 + (i), 1)
>
> /* Data structure describing auxiliary buffer format. */
> struct rkvdec_h264_priv_tbl {
> @@ -91,20 +84,6 @@ struct rkvdec_h264_ctx {
> struct rkvdec_regs regs;
> };
>
> -static void set_ps_field(u32 *buf, struct rkvdec_ps_field field, u32 value)
> -{
> - u8 bit = field.offset % 32, word = field.offset / 32;
> - u64 mask = GENMASK_ULL(bit + field.len - 1, bit);
> - u64 val = ((u64)value << bit) & mask;
> -
> - buf[word] &= ~mask;
> - buf[word] |= val;
> - if (bit + field.len > 32) {
> - buf[word + 1] &= ~(mask >> 32);
> - buf[word + 1] |= val >> 32;
> - }
> -}
> -
> static void assemble_hw_pps(struct rkvdec_ctx *ctx,
> struct rkvdec_h264_run *run)
> {
> @@ -128,7 +107,7 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx,
> hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id];
> memset(hw_ps, 0, sizeof(*hw_ps));
>
> -#define WRITE_PPS(value, field) set_ps_field(hw_ps->info, field, value)
> +#define WRITE_PPS(value, field) rkvdec_set_bw_field(hw_ps->info, field, value)
> /* write sps */
> WRITE_PPS(sps->seq_parameter_set_id, SEQ_PARAMETER_SET_ID);
> WRITE_PPS(sps->profile_idc, PROFILE_IDC);
> diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c
> index ac8b825d080a..87abf93dfd5e 100644
> --- a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c
> +++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc.c
> @@ -18,6 +18,7 @@
> #include "rkvdec-regs.h"
> #include "rkvdec-cabac.h"
> #include "rkvdec-hevc-common.h"
> +#include "rkvdec-bitwriter.h"
>
> /* Size in u8/u32 units. */
> #define RKV_SCALING_LIST_SIZE 1360
> @@ -34,80 +35,72 @@ struct rkvdec_rps_packet {
> u32 info[RKV_RPS_SIZE];
> };
>
> -struct rkvdec_ps_field {
> - u16 offset;
> - u8 len;
> -};
> -
> -#define PS_FIELD(_offset, _len) \
> - ((struct rkvdec_ps_field){ _offset, _len })
> -
> /* SPS */
> -#define VIDEO_PARAMETER_SET_ID PS_FIELD(0, 4)
> -#define SEQ_PARAMETER_SET_ID PS_FIELD(4, 4)
> -#define CHROMA_FORMAT_IDC PS_FIELD(8, 2)
> -#define PIC_WIDTH_IN_LUMA_SAMPLES PS_FIELD(10, 13)
> -#define PIC_HEIGHT_IN_LUMA_SAMPLES PS_FIELD(23, 13)
> -#define BIT_DEPTH_LUMA PS_FIELD(36, 4)
> -#define BIT_DEPTH_CHROMA PS_FIELD(40, 4)
> -#define LOG2_MAX_PIC_ORDER_CNT_LSB PS_FIELD(44, 5)
> -#define LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE PS_FIELD(49, 2)
> -#define LOG2_MIN_LUMA_CODING_BLOCK_SIZE PS_FIELD(51, 3)
> -#define LOG2_MIN_TRANSFORM_BLOCK_SIZE PS_FIELD(54, 3)
> -#define LOG2_DIFF_MAX_MIN_LUMA_TRANSFORM_BLOCK_SIZE PS_FIELD(57, 2)
> -#define MAX_TRANSFORM_HIERARCHY_DEPTH_INTER PS_FIELD(59, 3)
> -#define MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA PS_FIELD(62, 3)
> -#define SCALING_LIST_ENABLED_FLAG PS_FIELD(65, 1)
> -#define AMP_ENABLED_FLAG PS_FIELD(66, 1)
> -#define SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG PS_FIELD(67, 1)
> -#define PCM_ENABLED_FLAG PS_FIELD(68, 1)
> -#define PCM_SAMPLE_BIT_DEPTH_LUMA PS_FIELD(69, 4)
> -#define PCM_SAMPLE_BIT_DEPTH_CHROMA PS_FIELD(73, 4)
> -#define PCM_LOOP_FILTER_DISABLED_FLAG PS_FIELD(77, 1)
> -#define LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE PS_FIELD(78, 3)
> -#define LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE PS_FIELD(81, 3)
> -#define NUM_SHORT_TERM_REF_PIC_SETS PS_FIELD(84, 7)
> -#define LONG_TERM_REF_PICS_PRESENT_FLAG PS_FIELD(91, 1)
> -#define NUM_LONG_TERM_REF_PICS_SPS PS_FIELD(92, 6)
> -#define SPS_TEMPORAL_MVP_ENABLED_FLAG PS_FIELD(98, 1)
> -#define STRONG_INTRA_SMOOTHING_ENABLED_FLAG PS_FIELD(99, 1)
> +#define VIDEO_PARAMETER_SET_ID BW_FIELD(0, 4)
> +#define SEQ_PARAMETER_SET_ID BW_FIELD(4, 4)
> +#define CHROMA_FORMAT_IDC BW_FIELD(8, 2)
> +#define PIC_WIDTH_IN_LUMA_SAMPLES BW_FIELD(10, 13)
> +#define PIC_HEIGHT_IN_LUMA_SAMPLES BW_FIELD(23, 13)
> +#define BIT_DEPTH_LUMA BW_FIELD(36, 4)
> +#define BIT_DEPTH_CHROMA BW_FIELD(40, 4)
> +#define LOG2_MAX_PIC_ORDER_CNT_LSB BW_FIELD(44, 5)
> +#define LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE BW_FIELD(49, 2)
> +#define LOG2_MIN_LUMA_CODING_BLOCK_SIZE BW_FIELD(51, 3)
> +#define LOG2_MIN_TRANSFORM_BLOCK_SIZE BW_FIELD(54, 3)
> +#define LOG2_DIFF_MAX_MIN_LUMA_TRANSFORM_BLOCK_SIZE BW_FIELD(57, 2)
> +#define MAX_TRANSFORM_HIERARCHY_DEPTH_INTER BW_FIELD(59, 3)
> +#define MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA BW_FIELD(62, 3)
> +#define SCALING_LIST_ENABLED_FLAG BW_FIELD(65, 1)
> +#define AMP_ENABLED_FLAG BW_FIELD(66, 1)
> +#define SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG BW_FIELD(67, 1)
> +#define PCM_ENABLED_FLAG BW_FIELD(68, 1)
> +#define PCM_SAMPLE_BIT_DEPTH_LUMA BW_FIELD(69, 4)
> +#define PCM_SAMPLE_BIT_DEPTH_CHROMA BW_FIELD(73, 4)
> +#define PCM_LOOP_FILTER_DISABLED_FLAG BW_FIELD(77, 1)
> +#define LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE BW_FIELD(78, 3)
> +#define LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE BW_FIELD(81, 3)
> +#define NUM_SHORT_TERM_REF_PIC_SETS BW_FIELD(84, 7)
> +#define LONG_TERM_REF_PICS_PRESENT_FLAG BW_FIELD(91, 1)
> +#define NUM_LONG_TERM_REF_PICS_SPS BW_FIELD(92, 6)
> +#define SPS_TEMPORAL_MVP_ENABLED_FLAG BW_FIELD(98, 1)
> +#define STRONG_INTRA_SMOOTHING_ENABLED_FLAG BW_FIELD(99, 1)
> /* PPS */
> -#define PIC_PARAMETER_SET_ID PS_FIELD(128, 6)
> -#define PPS_SEQ_PARAMETER_SET_ID PS_FIELD(134, 4)
> -#define DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG PS_FIELD(138, 1)
> -#define OUTPUT_FLAG_PRESENT_FLAG PS_FIELD(139, 1)
> -#define NUM_EXTRA_SLICE_HEADER_BITS PS_FIELD(140, 13)
> -#define SIGN_DATA_HIDING_ENABLED_FLAG PS_FIELD(153, 1)
> -#define CABAC_INIT_PRESENT_FLAG PS_FIELD(154, 1)
> -#define NUM_REF_IDX_L0_DEFAULT_ACTIVE PS_FIELD(155, 4)
> -#define NUM_REF_IDX_L1_DEFAULT_ACTIVE PS_FIELD(159, 4)
> -#define INIT_QP_MINUS26 PS_FIELD(163, 7)
> -#define CONSTRAINED_INTRA_PRED_FLAG PS_FIELD(170, 1)
> -#define TRANSFORM_SKIP_ENABLED_FLAG PS_FIELD(171, 1)
> -#define CU_QP_DELTA_ENABLED_FLAG PS_FIELD(172, 1)
> -#define LOG2_MIN_CU_QP_DELTA_SIZE PS_FIELD(173, 3)
> -#define PPS_CB_QP_OFFSET PS_FIELD(176, 5)
> -#define PPS_CR_QP_OFFSET PS_FIELD(181, 5)
> -#define PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT_FLAG PS_FIELD(186, 1)
> -#define WEIGHTED_PRED_FLAG PS_FIELD(187, 1)
> -#define WEIGHTED_BIPRED_FLAG PS_FIELD(188, 1)
> -#define TRANSQUANT_BYPASS_ENABLED_FLAG PS_FIELD(189, 1)
> -#define TILES_ENABLED_FLAG PS_FIELD(190, 1)
> -#define ENTROPY_CODING_SYNC_ENABLED_FLAG PS_FIELD(191, 1)
> -#define PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG PS_FIELD(192, 1)
> -#define LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG PS_FIELD(193, 1)
> -#define DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG PS_FIELD(194, 1)
> -#define PPS_DEBLOCKING_FILTER_DISABLED_FLAG PS_FIELD(195, 1)
> -#define PPS_BETA_OFFSET_DIV2 PS_FIELD(196, 4)
> -#define PPS_TC_OFFSET_DIV2 PS_FIELD(200, 4)
> -#define LISTS_MODIFICATION_PRESENT_FLAG PS_FIELD(204, 1)
> -#define LOG2_PARALLEL_MERGE_LEVEL PS_FIELD(205, 3)
> -#define SLICE_SEGMENT_HEADER_EXTENSION_PRESENT_FLAG PS_FIELD(208, 1)
> -#define NUM_TILE_COLUMNS PS_FIELD(212, 5)
> -#define NUM_TILE_ROWS PS_FIELD(217, 5)
> -#define COLUMN_WIDTH(i) PS_FIELD(256 + ((i) * 8), 8)
> -#define ROW_HEIGHT(i) PS_FIELD(416 + ((i) * 8), 8)
> -#define SCALING_LIST_ADDRESS PS_FIELD(592, 32)
> +#define PIC_PARAMETER_SET_ID BW_FIELD(128, 6)
> +#define PPS_SEQ_PARAMETER_SET_ID BW_FIELD(134, 4)
> +#define DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG BW_FIELD(138, 1)
> +#define OUTPUT_FLAG_PRESENT_FLAG BW_FIELD(139, 1)
> +#define NUM_EXTRA_SLICE_HEADER_BITS BW_FIELD(140, 13)
> +#define SIGN_DATA_HIDING_ENABLED_FLAG BW_FIELD(153, 1)
> +#define CABAC_INIT_PRESENT_FLAG BW_FIELD(154, 1)
> +#define NUM_REF_IDX_L0_DEFAULT_ACTIVE BW_FIELD(155, 4)
> +#define NUM_REF_IDX_L1_DEFAULT_ACTIVE BW_FIELD(159, 4)
> +#define INIT_QP_MINUS26 BW_FIELD(163, 7)
> +#define CONSTRAINED_INTRA_PRED_FLAG BW_FIELD(170, 1)
> +#define TRANSFORM_SKIP_ENABLED_FLAG BW_FIELD(171, 1)
> +#define CU_QP_DELTA_ENABLED_FLAG BW_FIELD(172, 1)
> +#define LOG2_MIN_CU_QP_DELTA_SIZE BW_FIELD(173, 3)
> +#define PPS_CB_QP_OFFSET BW_FIELD(176, 5)
> +#define PPS_CR_QP_OFFSET BW_FIELD(181, 5)
> +#define PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT_FLAG BW_FIELD(186, 1)
> +#define WEIGHTED_PRED_FLAG BW_FIELD(187, 1)
> +#define WEIGHTED_BIPRED_FLAG BW_FIELD(188, 1)
> +#define TRANSQUANT_BYPASS_ENABLED_FLAG BW_FIELD(189, 1)
> +#define TILES_ENABLED_FLAG BW_FIELD(190, 1)
> +#define ENTROPY_CODING_SYNC_ENABLED_FLAG BW_FIELD(191, 1)
> +#define PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG BW_FIELD(192, 1)
> +#define LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG BW_FIELD(193, 1)
> +#define DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG BW_FIELD(194, 1)
> +#define PPS_DEBLOCKING_FILTER_DISABLED_FLAG BW_FIELD(195, 1)
> +#define PPS_BETA_OFFSET_DIV2 BW_FIELD(196, 4)
> +#define PPS_TC_OFFSET_DIV2 BW_FIELD(200, 4)
> +#define LISTS_MODIFICATION_PRESENT_FLAG BW_FIELD(204, 1)
> +#define LOG2_PARALLEL_MERGE_LEVEL BW_FIELD(205, 3)
> +#define SLICE_SEGMENT_HEADER_EXTENSION_PRESENT_FLAG BW_FIELD(208, 1)
> +#define NUM_TILE_COLUMNS BW_FIELD(212, 5)
> +#define NUM_TILE_ROWS BW_FIELD(217, 5)
> +#define COLUMN_WIDTH(i) BW_FIELD(256 + ((i) * 8), 8)
> +#define ROW_HEIGHT(i) BW_FIELD(416 + ((i) * 8), 8)
> +#define SCALING_LIST_ADDRESS BW_FIELD(592, 32)
>
> /* Data structure describing auxiliary buffer format. */
> struct rkvdec_hevc_priv_tbl {
> @@ -123,20 +116,6 @@ struct rkvdec_hevc_ctx {
> struct rkvdec_regs regs;
> };
>
> -static void set_ps_field(u32 *buf, struct rkvdec_ps_field field, u32 value)
> -{
> - u8 bit = field.offset % 32, word = field.offset / 32;
> - u64 mask = GENMASK_ULL(bit + field.len - 1, bit);
> - u64 val = ((u64)value << bit) & mask;
> -
> - buf[word] &= ~mask;
> - buf[word] |= val;
> - if (bit + field.len > 32) {
> - buf[word + 1] &= ~(mask >> 32);
> - buf[word + 1] |= val >> 32;
> - }
> -}
> -
> static void assemble_hw_pps(struct rkvdec_ctx *ctx,
> struct rkvdec_hevc_run *run)
> {
> @@ -159,7 +138,7 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx,
> hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id];
> memset(hw_ps, 0, sizeof(*hw_ps));
>
> -#define WRITE_PPS(value, field) set_ps_field(hw_ps->info, field, value)
> +#define WRITE_PPS(value, field) rkvdec_set_bw_field(hw_ps->info, field, value)
> /* write sps */
> WRITE_PPS(sps->video_parameter_set_id, VIDEO_PARAMETER_SET_ID);
> WRITE_PPS(sps->seq_parameter_set_id, SEQ_PARAMETER_SET_ID);
> @@ -321,17 +300,17 @@ static void assemble_sw_rps(struct rkvdec_ctx *ctx,
> int i, j;
> unsigned int lowdelay;
>
> -#define WRITE_RPS(value, field) set_ps_field(hw_ps->info, field, value)
> +#define WRITE_RPS(value, field) rkvdec_set_bw_field(hw_ps->info, field, value)
>
> -#define REF_PIC_LONG_TERM_L0(i) PS_FIELD((i) * 5, 1)
> -#define REF_PIC_IDX_L0(i) PS_FIELD(1 + ((i) * 5), 4)
> -#define REF_PIC_LONG_TERM_L1(i) PS_FIELD(((i) < 5 ? 75 : 132) + ((i) * 5), 1)
> -#define REF_PIC_IDX_L1(i) PS_FIELD(((i) < 4 ? 76 : 128) + ((i) * 5), 4)
> +#define REF_PIC_LONG_TERM_L0(n) BW_FIELD((n) * 5, 1)
> +#define REF_PIC_IDX_L0(n) BW_FIELD(1 + ((n) * 5), 4)
> +#define REF_PIC_LONG_TERM_L1(n) BW_FIELD(((n) < 5 ? 75 : 132) + ((n) * 5), 1)
> +#define REF_PIC_IDX_L1(n) BW_FIELD(((n) < 4 ? 76 : 128) + ((n) * 5), 4)
>
> -#define LOWDELAY PS_FIELD(182, 1)
> -#define LONG_TERM_RPS_BIT_OFFSET PS_FIELD(183, 10)
> -#define SHORT_TERM_RPS_BIT_OFFSET PS_FIELD(193, 9)
> -#define NUM_RPS_POC PS_FIELD(202, 4)
> +#define LOWDELAY BW_FIELD(182, 1)
> +#define LONG_TERM_RPS_BIT_OFFSET BW_FIELD(183, 10)
> +#define SHORT_TERM_RPS_BIT_OFFSET BW_FIELD(193, 9)
> +#define NUM_RPS_POC BW_FIELD(202, 4)
>
> for (j = 0; j < run->num_slices; j++) {
> uint st_bit_offset = 0;
[-- Attachment #2: This is a digitally signed message part --]
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^ permalink raw reply
* Re: [PATCH v3 3/4] media: rkvdec: common: Drop bitfields for the bitwriter
From: Nicolas Dufresne @ 2026-04-29 18:20 UTC (permalink / raw)
To: Detlev Casanova, Ezequiel Garcia, Mauro Carvalho Chehab,
Heiko Stuebner, Nathan Chancellor, Nick Desaulniers,
Bill Wendling, Justin Stitt, Jonas Karlman
Cc: linux-kernel, linux-media, linux-rockchip, linux-arm-kernel, llvm,
kernel
In-Reply-To: <20260402-rkvdec-use-bitwriter-v3-3-2072474ceaf4@collabora.com>
[-- Attachment #1: Type: text/plain, Size: 12391 bytes --]
Le jeudi 02 avril 2026 à 10:06 -0400, Detlev Casanova a écrit :
> Currently, the common code files for hevc and h264 use structs with
> bitfields to represent the HW RPS buffer.
>
> Because the bitfields are mostly unaligned and numerous, it brings compiler
> issues, especially with clang.
>
> To prevent that, switch to using the global bitwriter previously
> introduced instead.
>
> Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
> ---
> .../platform/rockchip/rkvdec/rkvdec-h264-common.c | 51 +-----------
> .../platform/rockchip/rkvdec/rkvdec-h264-common.h | 40 +++-------
> .../platform/rockchip/rkvdec/rkvdec-hevc-common.c | 93 ++++------------------
> .../platform/rockchip/rkvdec/rkvdec-hevc-common.h | 57 ++++---------
> 4 files changed, 44 insertions(+), 197 deletions(-)
>
> diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-h264-common.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-h264-common.c
> index e28f06394470..54639512e456 100644
> --- a/drivers/media/platform/rockchip/rkvdec/rkvdec-h264-common.c
> +++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-h264-common.c
> @@ -21,51 +21,6 @@
>
> #define RKVDEC_NUM_REFLIST 3
>
> -static void set_dpb_info(struct rkvdec_rps_entry *entries,
> - u8 reflist,
> - u8 refnum,
> - u8 info,
> - bool bottom)
> -{
> - struct rkvdec_rps_entry *entry = &entries[(reflist * 4) + refnum / 8];
> - u8 idx = refnum % 8;
> -
> - switch (idx) {
> - case 0:
> - entry->dpb_info0 = info;
> - entry->bottom_flag0 = bottom;
> - break;
> - case 1:
> - entry->dpb_info1 = info;
> - entry->bottom_flag1 = bottom;
> - break;
> - case 2:
> - entry->dpb_info2 = info;
> - entry->bottom_flag2 = bottom;
> - break;
> - case 3:
> - entry->dpb_info3 = info;
> - entry->bottom_flag3 = bottom;
> - break;
> - case 4:
> - entry->dpb_info4 = info;
> - entry->bottom_flag4 = bottom;
> - break;
> - case 5:
> - entry->dpb_info5 = info;
> - entry->bottom_flag5 = bottom;
> - break;
> - case 6:
> - entry->dpb_info6 = info;
> - entry->bottom_flag6 = bottom;
> - break;
> - case 7:
> - entry->dpb_info7 = info;
> - entry->bottom_flag7 = bottom;
> - break;
> - }
> -}
> -
> void lookup_ref_buf_idx(struct rkvdec_ctx *ctx,
> struct rkvdec_h264_run *run)
> {
> @@ -111,7 +66,7 @@ void assemble_hw_rps(struct v4l2_h264_reflist_builder *builder,
> if (!(dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE))
> continue;
>
> - hw_rps->frame_num[i] = builder->refs[i].frame_num;
> + rkvdec_set_bw_field(hw_rps->info, RPS_FRAME_NUM(i), builder->refs[i].frame_num);
> }
>
> for (j = 0; j < RKVDEC_NUM_REFLIST; j++) {
> @@ -138,7 +93,9 @@ void assemble_hw_rps(struct v4l2_h264_reflist_builder *builder,
> dpb_valid = !!(run->ref_buf[ref->index]);
> bottom = ref->fields == V4L2_H264_BOTTOM_FIELD_REF;
>
> - set_dpb_info(hw_rps->entries, j, i, ref->index | (dpb_valid << 4), bottom);
> + rkvdec_set_bw_field(hw_rps->info, RPS_ENTRY_DPB_INFO(j, i),
> + ref->index | (dpb_valid << 4));
> + rkvdec_set_bw_field(hw_rps->info, RPS_ENTRY_BOTTOM_FLAG(j, i), bottom);
> }
> }
> }
> diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-h264-common.h b/drivers/media/platform/rockchip/rkvdec/rkvdec-h264-common.h
> index 5336370507d6..f04b700b863c 100644
> --- a/drivers/media/platform/rockchip/rkvdec/rkvdec-h264-common.h
> +++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-h264-common.h
> @@ -16,6 +16,7 @@
> #include <media/v4l2-mem2mem.h>
>
> #include "rkvdec.h"
> +#include "rkvdec-bitwriter.h"
>
> struct rkvdec_h264_scaling_list {
> u8 scaling_list_4x4[6][16];
> @@ -38,39 +39,16 @@ struct rkvdec_h264_run {
> struct vb2_buffer *ref_buf[V4L2_H264_NUM_DPB_ENTRIES];
> };
>
> -struct rkvdec_rps_entry {
> - u32 dpb_info0: 5;
> - u32 bottom_flag0: 1;
> - u32 view_index_off0: 1;
> - u32 dpb_info1: 5;
> - u32 bottom_flag1: 1;
> - u32 view_index_off1: 1;
> - u32 dpb_info2: 5;
> - u32 bottom_flag2: 1;
> - u32 view_index_off2: 1;
> - u32 dpb_info3: 5;
> - u32 bottom_flag3: 1;
> - u32 view_index_off3: 1;
> - u32 dpb_info4: 5;
> - u32 bottom_flag4: 1;
> - u32 view_index_off4: 1;
> - u32 dpb_info5: 5;
> - u32 bottom_flag5: 1;
> - u32 view_index_off5: 1;
> - u32 dpb_info6: 5;
> - u32 bottom_flag6: 1;
> - u32 view_index_off6: 1;
> - u32 dpb_info7: 5;
> - u32 bottom_flag7: 1;
> - u32 view_index_off7: 1;
> -} __packed;
> +#define RPS_FRAME_NUM(i) BW_FIELD((i) * 16, 16)
> +#define RPS_ENTRY_DPB_INFO(l, e) BW_FIELD(288 + (l) * 7 * 32 + (e) * 7, 5) //l: 0-2, e: 0-31
> +#define RPS_ENTRY_BOTTOM_FLAG(l, e) BW_FIELD(293 + (l) * 7 * 32 + (e) * 7, 1) //l: 0-2, e: 0-31
> +#define RPS_ENTRY_VIEW_INDEX_OFF(l, e) BW_FIELD(294 + (l) * 7 * 32 + (e) * 7, 1) //l: 0-2, e: 0-31
> +
> +#define RKVDEC_H264_RPS_SIZE ALIGN(288 + 3 * 7 * 32, 128)
>
> struct rkvdec_rps {
> - u16 frame_num[16];
> - u32 reserved0;
> - struct rkvdec_rps_entry entries[12];
> - u32 reserved1[66];
> -} __packed;
> + u32 info[RKVDEC_H264_RPS_SIZE / 8 / 4];
> +};
>
> void lookup_ref_buf_idx(struct rkvdec_ctx *ctx, struct rkvdec_h264_run *run);
> void assemble_hw_rps(struct v4l2_h264_reflist_builder *builder,
> diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c
> index 3119f3bc9f98..f89602075121 100644
> --- a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c
> +++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.c
> @@ -74,72 +74,6 @@ void compute_tiles_non_uniform(struct rkvdec_hevc_run *run, u16 log2_min_cb_size
> row_height[i] = pic_in_cts_height - sum;
> }
>
> -static void set_ref_poc(struct rkvdec_rps_short_term_ref_set *set, int poc, int value, int flag)
> -{
> - switch (poc) {
> - case 0:
> - set->delta_poc0 = value;
> - set->used_flag0 = flag;
> - break;
> - case 1:
> - set->delta_poc1 = value;
> - set->used_flag1 = flag;
> - break;
> - case 2:
> - set->delta_poc2 = value;
> - set->used_flag2 = flag;
> - break;
> - case 3:
> - set->delta_poc3 = value;
> - set->used_flag3 = flag;
> - break;
> - case 4:
> - set->delta_poc4 = value;
> - set->used_flag4 = flag;
> - break;
> - case 5:
> - set->delta_poc5 = value;
> - set->used_flag5 = flag;
> - break;
> - case 6:
> - set->delta_poc6 = value;
> - set->used_flag6 = flag;
> - break;
> - case 7:
> - set->delta_poc7 = value;
> - set->used_flag7 = flag;
> - break;
> - case 8:
> - set->delta_poc8 = value;
> - set->used_flag8 = flag;
> - break;
> - case 9:
> - set->delta_poc9 = value;
> - set->used_flag9 = flag;
> - break;
> - case 10:
> - set->delta_poc10 = value;
> - set->used_flag10 = flag;
> - break;
> - case 11:
> - set->delta_poc11 = value;
> - set->used_flag11 = flag;
> - break;
> - case 12:
> - set->delta_poc12 = value;
> - set->used_flag12 = flag;
> - break;
> - case 13:
> - set->delta_poc13 = value;
> - set->used_flag13 = flag;
> - break;
> - case 14:
> - set->delta_poc14 = value;
> - set->used_flag14 = flag;
> - break;
> - }
> -}
> -
> static void assemble_scalingfactor0(struct rkvdec_ctx *ctx, u8 *output,
> const struct v4l2_ctrl_hevc_scaling_matrix *input)
> {
> @@ -218,10 +152,11 @@ static void rkvdec_hevc_assemble_hw_lt_rps(struct rkvdec_hevc_run *run, struct r
> return;
>
> for (int i = 0; i < sps->num_long_term_ref_pics_sps; i++) {
> - rps->refs[i].lt_ref_pic_poc_lsb =
> - run->ext_sps_lt_rps[i].lt_ref_pic_poc_lsb_sps;
> - rps->refs[i].used_by_curr_pic_lt_flag =
> - !!(run->ext_sps_lt_rps[i].flags & V4L2_HEVC_EXT_SPS_LT_RPS_FLAG_USED_LT);
> + rkvdec_set_bw_field(rps->info, RPS_LT_REF_PIC_POC_LSB(i),
> + run->ext_sps_lt_rps[i].lt_ref_pic_poc_lsb_sps);
> + rkvdec_set_bw_field(rps->info, RPS_LT_REF_USED_BY_CURR_PIC(i),
> + !!(run->ext_sps_lt_rps[i].flags &
> + V4L2_HEVC_EXT_SPS_LT_RPS_FLAG_USED_LT));
> }
> }
>
> @@ -235,18 +170,24 @@ static void rkvdec_hevc_assemble_hw_st_rps(struct rkvdec_hevc_run *run, struct r
> int j = 0;
> const struct calculated_rps_st_set *set = &calculated_rps_st_sets[i];
>
> - rps->short_term_ref_sets[i].num_negative = set->num_negative_pics;
> - rps->short_term_ref_sets[i].num_positive = set->num_positive_pics;
> + rkvdec_set_bw_field(rps->info, RPS_ST_REF_SET_NUM_NEGATIVE(i),
> + set->num_negative_pics);
> + rkvdec_set_bw_field(rps->info, RPS_ST_REF_SET_NUM_POSITIVE(i),
> + set->num_positive_pics);
>
> for (; j < set->num_negative_pics; j++) {
> - set_ref_poc(&rps->short_term_ref_sets[i], j,
> - set->delta_poc_s0[j], set->used_by_curr_pic_s0[j]);
> + rkvdec_set_bw_field(rps->info, RPS_ST_REF_SET_DELTA_POC(i, j),
> + set->delta_poc_s0[j]);
> + rkvdec_set_bw_field(rps->info, RPS_ST_REF_SET_USED(i, j),
> + set->used_by_curr_pic_s0[j]);
> }
> poc = j;
>
> for (j = 0; j < set->num_positive_pics; j++) {
> - set_ref_poc(&rps->short_term_ref_sets[i], poc + j,
> - set->delta_poc_s1[j], set->used_by_curr_pic_s1[j]);
> + rkvdec_set_bw_field(rps->info, RPS_ST_REF_SET_DELTA_POC(i, poc + j),
> + set->delta_poc_s1[j]);
> + rkvdec_set_bw_field(rps->info, RPS_ST_REF_SET_USED(i, poc + j),
> + set->used_by_curr_pic_s1[j]);
> }
> }
> }
> diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.h b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.h
> index 6f4faca4c091..2a9b7719ab2d 100644
> --- a/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.h
> +++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-hevc-common.h
> @@ -19,53 +19,24 @@
> #include <linux/types.h>
>
> #include "rkvdec.h"
> +#include "rkvdec-bitwriter.h"
>
> -struct rkvdec_rps_refs {
> - u16 lt_ref_pic_poc_lsb;
> - u16 used_by_curr_pic_lt_flag : 1;
> - u16 reserved : 15;
> -} __packed;
> +#define RPS_LT_REF_PIC_POC_LSB(i) BW_FIELD(0 + (i) * 32, 16) // i: 0-31
> +#define RPS_LT_REF_USED_BY_CURR_PIC(i) BW_FIELD(16 + (i) * 32, 1) // i: 0-31
>
> -struct rkvdec_rps_short_term_ref_set {
> - u32 num_negative : 4;
> - u32 num_positive : 4;
> - u32 delta_poc0 : 16;
> - u32 used_flag0 : 1;
> - u32 delta_poc1 : 16;
> - u32 used_flag1 : 1;
> - u32 delta_poc2 : 16;
> - u32 used_flag2 : 1;
> - u32 delta_poc3 : 16;
> - u32 used_flag3 : 1;
> - u32 delta_poc4 : 16;
> - u32 used_flag4 : 1;
> - u32 delta_poc5 : 16;
> - u32 used_flag5 : 1;
> - u32 delta_poc6 : 16;
> - u32 used_flag6 : 1;
> - u32 delta_poc7 : 16;
> - u32 used_flag7 : 1;
> - u32 delta_poc8 : 16;
> - u32 used_flag8 : 1;
> - u32 delta_poc9 : 16;
> - u32 used_flag9 : 1;
> - u32 delta_poc10 : 16;
> - u32 used_flag10 : 1;
> - u32 delta_poc11 : 16;
> - u32 used_flag11 : 1;
> - u32 delta_poc12 : 16;
> - u32 used_flag12 : 1;
> - u32 delta_poc13 : 16;
> - u32 used_flag13 : 1;
> - u32 delta_poc14 : 16;
> - u32 used_flag14 : 1;
> - u32 reserved_bits : 25;
> - u32 reserved[3];
> -} __packed;
> +#define RPS_ST_REF_SET_NUM_NEGATIVE(i) BW_FIELD(1024 + ((i) * 384), 4) // i: 0-63
> +#define RPS_ST_REF_SET_NUM_POSITIVE(i) BW_FIELD(1028 + ((i) * 384), 4) // i: 0-63
> +
> +// i: 0-63, j: 0-14
> +#define RPS_ST_REF_SET_DELTA_POC(i, j) BW_FIELD(1032 + ((i) * 384) + ((j) * 17), 16)
> +
> +// i: 0-63, j: 0-14
> +#define RPS_ST_REF_SET_USED(i, j) BW_FIELD(1048 + ((i) * 384) + ((j) * 17), 1)
> +
> +#define RKVDEC_RPS_HEVC_SIZE ALIGN(1032 + 64 * 384, 128)
>
> struct rkvdec_rps {
> - struct rkvdec_rps_refs refs[32];
> - struct rkvdec_rps_short_term_ref_set short_term_ref_sets[64];
> + u32 info[RKVDEC_RPS_HEVC_SIZE / 8 / 4];
> } __packed;
>
> struct rkvdec_hevc_run {
[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply
* Re: [PATCH v3 4/4] media: rkvdec: vdpu383: Drop bitfields for the bitwriter
From: Nicolas Dufresne @ 2026-04-29 18:21 UTC (permalink / raw)
To: Detlev Casanova, Ezequiel Garcia, Mauro Carvalho Chehab,
Heiko Stuebner, Nathan Chancellor, Nick Desaulniers,
Bill Wendling, Justin Stitt, Jonas Karlman
Cc: linux-kernel, linux-media, linux-rockchip, linux-arm-kernel, llvm,
kernel
In-Reply-To: <20260402-rkvdec-use-bitwriter-v3-4-2072474ceaf4@collabora.com>
[-- Attachment #1: Type: text/plain, Size: 49111 bytes --]
Le jeudi 02 avril 2026 à 10:06 -0400, Detlev Casanova a écrit :
> The VDPU383 support for hevc and h264 use structs with bitfields to
> represent the SPS and PPS.
>
> Because the fields are mostly unaligned and numerous, it brings compiler
> issues, especially with clang.
>
> To prevent that, switch to using the global bitwriter previously
> introduced instead.
>
> Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
Ok good, I'll pick this series and apply the tiny edits on patch 1.
> ---
> .../platform/rockchip/rkvdec/rkvdec-vdpu383-h264.c | 351 ++++++--------
> .../platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c | 502 +++++++++------------
> 2 files changed, 360 insertions(+), 493 deletions(-)
>
> diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-h264.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-h264.c
> index fb4f849d7366..5ec755733916 100644
> --- a/drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-h264.c
> +++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-h264.c
> @@ -15,105 +15,64 @@
> #include "rkvdec-cabac.h"
> #include "rkvdec-vdpu383-regs.h"
> #include "rkvdec-h264-common.h"
> -
> -struct rkvdec_sps {
> - u16 seq_parameter_set_id: 4;
> - u16 profile_idc: 8;
> - u16 constraint_set3_flag: 1;
> - u16 chroma_format_idc: 2;
> - u16 bit_depth_luma: 3;
> - u16 bit_depth_chroma: 3;
> - u16 qpprime_y_zero_transform_bypass_flag: 1;
> - u16 log2_max_frame_num_minus4: 4;
> - u16 max_num_ref_frames: 5;
> - u16 pic_order_cnt_type: 2;
> - u16 log2_max_pic_order_cnt_lsb_minus4: 4;
> - u16 delta_pic_order_always_zero_flag: 1;
> -
> - u16 pic_width_in_mbs: 16;
> - u16 pic_height_in_mbs: 16;
> -
> - u16 frame_mbs_only_flag: 1;
> - u16 mb_adaptive_frame_field_flag: 1;
> - u16 direct_8x8_inference_flag: 1;
> - u16 mvc_extension_enable: 1;
> - u16 num_views: 2;
> - u16 view_id0: 10;
> - u16 view_id1: 10;
> -} __packed;
> -
> -struct rkvdec_pps {
> - u32 pic_parameter_set_id: 8;
> - u32 pps_seq_parameter_set_id: 5;
> - u32 entropy_coding_mode_flag: 1;
> - u32 bottom_field_pic_order_in_frame_present_flag: 1;
> - u32 num_ref_idx_l0_default_active_minus1: 5;
> - u32 num_ref_idx_l1_default_active_minus1: 5;
> - u32 weighted_pred_flag: 1;
> - u32 weighted_bipred_idc: 2;
> - u32 pic_init_qp_minus26: 7;
> - u32 pic_init_qs_minus26: 6;
> - u32 chroma_qp_index_offset: 5;
> - u32 deblocking_filter_control_present_flag: 1;
> - u32 constrained_intra_pred_flag: 1;
> - u32 redundant_pic_cnt_present: 1;
> - u32 transform_8x8_mode_flag: 1;
> - u32 second_chroma_qp_index_offset: 5;
> - u32 scaling_list_enable_flag: 1;
> - u32 is_longterm: 16;
> - u32 voidx: 16;
> -
> - // dpb
> - u32 pic_field_flag: 1;
> - u32 pic_associated_flag: 1;
> - u32 cur_top_field: 32;
> - u32 cur_bot_field: 32;
> -
> - u32 top_field_order_cnt0: 32;
> - u32 bot_field_order_cnt0: 32;
> - u32 top_field_order_cnt1: 32;
> - u32 bot_field_order_cnt1: 32;
> - u32 top_field_order_cnt2: 32;
> - u32 bot_field_order_cnt2: 32;
> - u32 top_field_order_cnt3: 32;
> - u32 bot_field_order_cnt3: 32;
> - u32 top_field_order_cnt4: 32;
> - u32 bot_field_order_cnt4: 32;
> - u32 top_field_order_cnt5: 32;
> - u32 bot_field_order_cnt5: 32;
> - u32 top_field_order_cnt6: 32;
> - u32 bot_field_order_cnt6: 32;
> - u32 top_field_order_cnt7: 32;
> - u32 bot_field_order_cnt7: 32;
> - u32 top_field_order_cnt8: 32;
> - u32 bot_field_order_cnt8: 32;
> - u32 top_field_order_cnt9: 32;
> - u32 bot_field_order_cnt9: 32;
> - u32 top_field_order_cnt10: 32;
> - u32 bot_field_order_cnt10: 32;
> - u32 top_field_order_cnt11: 32;
> - u32 bot_field_order_cnt11: 32;
> - u32 top_field_order_cnt12: 32;
> - u32 bot_field_order_cnt12: 32;
> - u32 top_field_order_cnt13: 32;
> - u32 bot_field_order_cnt13: 32;
> - u32 top_field_order_cnt14: 32;
> - u32 bot_field_order_cnt14: 32;
> - u32 top_field_order_cnt15: 32;
> - u32 bot_field_order_cnt15: 32;
> -
> - u32 ref_field_flags: 16;
> - u32 ref_topfield_used: 16;
> - u32 ref_botfield_used: 16;
> - u32 ref_colmv_use_flag: 16;
> -
> - u32 reserved0: 30;
> - u32 reserved[3];
> -} __packed;
> +#include "rkvdec-bitwriter.h"
> +
> +#define SEQ_PARAMETER_SET_ID BW_FIELD(0, 4)
> +#define PROFILE_IDC BW_FIELD(4, 8)
> +#define CONSTRAINT_SET3_FLAG BW_FIELD(12, 1)
> +#define CHROMA_FORMAT_IDC BW_FIELD(13, 2)
> +#define BIT_DEPTH_LUMA BW_FIELD(15, 3)
> +#define BIT_DEPTH_CHROMA BW_FIELD(18, 3)
> +#define QPPRIME_Y_ZERO_TRANSFORM_BYPASS_FLAG BW_FIELD(21, 1)
> +#define LOG2_MAX_FRAME_NUM_MINUS4 BW_FIELD(22, 4)
> +#define MAX_NUM_REF_FRAMES BW_FIELD(26, 5)
> +#define PIC_ORDER_CNT_TYPE BW_FIELD(31, 2)
> +#define LOG2_MAX_PIC_ORDER_CNT_LSB_MINUS4 BW_FIELD(33, 4)
> +#define DELTA_PIC_ORDER_ALWAYS_ZERO_FLAG BW_FIELD(37, 1)
> +#define PIC_WIDTH_IN_MBS BW_FIELD(38, 16)
> +#define PIC_HEIGHT_IN_MBS BW_FIELD(54, 16)
> +#define FRAME_MBS_ONLY_FLAG BW_FIELD(70, 1)
> +#define MB_ADAPTIVE_FRAME_FIELD_FLAG BW_FIELD(71, 1)
> +#define DIRECT_8X8_INFERENCE_FLAG BW_FIELD(72, 1)
> +#define MVC_EXTENSION_ENABLE BW_FIELD(73, 1)
> +#define NUM_VIEWS BW_FIELD(74, 2)
> +#define VIEW_ID(i) BW_FIELD(76 + ((i) * 10), 10) // i: 0-1
> +
> +#define PIC_PARAMETER_SET_ID BW_FIELD(96, 8)
> +#define PPS_SEQ_PARAMETER_SET_ID BW_FIELD(104, 5)
> +#define ENTROPY_CODING_MODE_FLAG BW_FIELD(109, 1)
> +#define BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT_FLAG BW_FIELD(110, 1)
> +#define NUM_REF_IDX_L_DEFAULT_ACTIVE_MINUS1(i) BW_FIELD(111 + ((i) * 5), 5) // i: 0-1
> +#define WEIGHTED_PRED_FLAG BW_FIELD(121, 1)
> +#define WEIGHTED_BIPRED_IDC BW_FIELD(122, 2)
> +#define PIC_INIT_QP_MINUS26 BW_FIELD(124, 7)
> +#define PIC_INIT_QS_MINUS26 BW_FIELD(131, 6)
> +#define CHROMA_QP_INDEX_OFFSET BW_FIELD(137, 5)
> +#define DEBLOCKING_FILTER_CONTROL_PRESENT_FLAG BW_FIELD(142, 1)
> +#define CONSTRAINED_INTRA_PRED_FLAG BW_FIELD(143, 1)
> +#define REDUNDANT_PIC_CNT_PRESENT BW_FIELD(144, 1)
> +#define TRANSFORM_8X8_MODE_FLAG BW_FIELD(145, 1)
> +#define SECOND_CHROMA_QP_INDEX_OFFSET BW_FIELD(146, 5)
> +#define SCALING_LIST_ENABLE_FLAG BW_FIELD(151, 1)
> +#define IS_LONG_TERM(i) BW_FIELD(152 + (i), 1) // i: 0-15
> +
> +#define PIC_FIELD_FLAG BW_FIELD(184, 1)
> +#define PIC_ASSOCIATED_FLAG BW_FIELD(185, 1)
> +#define CUR_TOP_FIELD BW_FIELD(186, 32)
> +#define CUR_BOT_FIELD BW_FIELD(218, 32)
> +
> +#define TOP_FIELD_ORDER_CNT(i) BW_FIELD(250 + (i) * 64, 32) // i: 0-15
> +#define BOT_FIELD_ORDER_CNT(i) BW_FIELD(282 + (i) * 64, 32) // i: 0-15
> +
> +#define REF_FIELD_FLAGS(i) BW_FIELD(1274 + (i), 1) // i: 0-15
> +#define REF_TOPFIELD_USED(i) BW_FIELD(1290 + (i), 1) // i: 0-15
> +#define REF_BOTFIELD_USED(i) BW_FIELD(1306 + (i), 1) // i: 0-15
> +#define REF_COLMV_USE_FLAG(i) BW_FIELD(1322 + (i), 1) // i: 0-15
> +
> +#define SPS_SIZE ALIGN(1322 + 16, 128)
>
> struct rkvdec_sps_pps {
> - struct rkvdec_sps sps;
> - struct rkvdec_pps pps;
> + u32 info[SPS_SIZE / 8 / 4];
> } __packed;
>
> /* Data structure describing auxiliary buffer format. */
> @@ -130,67 +89,6 @@ struct rkvdec_h264_ctx {
> struct vdpu383_regs_h26x regs;
> };
>
> -static noinline_for_stack void set_field_order_cnt(struct rkvdec_pps *pps, const struct v4l2_h264_dpb_entry *dpb)
> -{
> - pps->top_field_order_cnt0 = dpb[0].top_field_order_cnt;
> - pps->bot_field_order_cnt0 = dpb[0].bottom_field_order_cnt;
> - pps->top_field_order_cnt1 = dpb[1].top_field_order_cnt;
> - pps->bot_field_order_cnt1 = dpb[1].bottom_field_order_cnt;
> - pps->top_field_order_cnt2 = dpb[2].top_field_order_cnt;
> - pps->bot_field_order_cnt2 = dpb[2].bottom_field_order_cnt;
> - pps->top_field_order_cnt3 = dpb[3].top_field_order_cnt;
> - pps->bot_field_order_cnt3 = dpb[3].bottom_field_order_cnt;
> - pps->top_field_order_cnt4 = dpb[4].top_field_order_cnt;
> - pps->bot_field_order_cnt4 = dpb[4].bottom_field_order_cnt;
> - pps->top_field_order_cnt5 = dpb[5].top_field_order_cnt;
> - pps->bot_field_order_cnt5 = dpb[5].bottom_field_order_cnt;
> - pps->top_field_order_cnt6 = dpb[6].top_field_order_cnt;
> - pps->bot_field_order_cnt6 = dpb[6].bottom_field_order_cnt;
> - pps->top_field_order_cnt7 = dpb[7].top_field_order_cnt;
> - pps->bot_field_order_cnt7 = dpb[7].bottom_field_order_cnt;
> - pps->top_field_order_cnt8 = dpb[8].top_field_order_cnt;
> - pps->bot_field_order_cnt8 = dpb[8].bottom_field_order_cnt;
> - pps->top_field_order_cnt9 = dpb[9].top_field_order_cnt;
> - pps->bot_field_order_cnt9 = dpb[9].bottom_field_order_cnt;
> - pps->top_field_order_cnt10 = dpb[10].top_field_order_cnt;
> - pps->bot_field_order_cnt10 = dpb[10].bottom_field_order_cnt;
> - pps->top_field_order_cnt11 = dpb[11].top_field_order_cnt;
> - pps->bot_field_order_cnt11 = dpb[11].bottom_field_order_cnt;
> - pps->top_field_order_cnt12 = dpb[12].top_field_order_cnt;
> - pps->bot_field_order_cnt12 = dpb[12].bottom_field_order_cnt;
> - pps->top_field_order_cnt13 = dpb[13].top_field_order_cnt;
> - pps->bot_field_order_cnt13 = dpb[13].bottom_field_order_cnt;
> - pps->top_field_order_cnt14 = dpb[14].top_field_order_cnt;
> - pps->bot_field_order_cnt14 = dpb[14].bottom_field_order_cnt;
> - pps->top_field_order_cnt15 = dpb[15].top_field_order_cnt;
> - pps->bot_field_order_cnt15 = dpb[15].bottom_field_order_cnt;
> -}
> -
> -static noinline_for_stack void set_dec_params(struct rkvdec_pps *pps, const struct v4l2_ctrl_h264_decode_params *dec_params)
> -{
> - const struct v4l2_h264_dpb_entry *dpb = dec_params->dpb;
> -
> - for (int i = 0; i < ARRAY_SIZE(dec_params->dpb); i++) {
> - if (dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM)
> - pps->is_longterm |= (1 << i);
> - pps->ref_field_flags |=
> - (!!(dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_FIELD)) << i;
> - pps->ref_colmv_use_flag |=
> - (!!(dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE)) << i;
> - pps->ref_topfield_used |=
> - (!!(dpb[i].fields & V4L2_H264_TOP_FIELD_REF)) << i;
> - pps->ref_botfield_used |=
> - (!!(dpb[i].fields & V4L2_H264_BOTTOM_FIELD_REF)) << i;
> - }
> - pps->pic_field_flag =
> - !!(dec_params->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC);
> - pps->pic_associated_flag =
> - !!(dec_params->flags & V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD);
> -
> - pps->cur_top_field = dec_params->top_field_order_cnt;
> - pps->cur_bot_field = dec_params->bottom_field_order_cnt;
> -}
> -
> static void assemble_hw_pps(struct rkvdec_ctx *ctx,
> struct rkvdec_h264_run *run)
> {
> @@ -202,6 +100,7 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx,
> struct rkvdec_h264_priv_tbl *priv_tbl = h264_ctx->priv_tbl.cpu;
> struct rkvdec_sps_pps *hw_ps;
> u32 pic_width, pic_height;
> + int i;
>
> /*
> * HW read the SPS/PPS information from PPS packet index by PPS id.
> @@ -213,23 +112,25 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx,
> memset(hw_ps, 0, sizeof(*hw_ps));
>
> /* write sps */
> - hw_ps->sps.seq_parameter_set_id = sps->seq_parameter_set_id;
> - hw_ps->sps.profile_idc = sps->profile_idc;
> - hw_ps->sps.constraint_set3_flag = !!(sps->constraint_set_flags & (1 << 3));
> - hw_ps->sps.chroma_format_idc = sps->chroma_format_idc;
> - hw_ps->sps.bit_depth_luma = sps->bit_depth_luma_minus8;
> - hw_ps->sps.bit_depth_chroma = sps->bit_depth_chroma_minus8;
> - hw_ps->sps.qpprime_y_zero_transform_bypass_flag =
> - !!(sps->flags & V4L2_H264_SPS_FLAG_QPPRIME_Y_ZERO_TRANSFORM_BYPASS);
> - hw_ps->sps.log2_max_frame_num_minus4 = sps->log2_max_frame_num_minus4;
> - hw_ps->sps.max_num_ref_frames = sps->max_num_ref_frames;
> - hw_ps->sps.pic_order_cnt_type = sps->pic_order_cnt_type;
> - hw_ps->sps.log2_max_pic_order_cnt_lsb_minus4 =
> - sps->log2_max_pic_order_cnt_lsb_minus4;
> - hw_ps->sps.delta_pic_order_always_zero_flag =
> - !!(sps->flags & V4L2_H264_SPS_FLAG_DELTA_PIC_ORDER_ALWAYS_ZERO);
> - hw_ps->sps.mvc_extension_enable = 0;
> - hw_ps->sps.num_views = 0;
> + rkvdec_set_bw_field(hw_ps->info, SEQ_PARAMETER_SET_ID, sps->seq_parameter_set_id);
> + rkvdec_set_bw_field(hw_ps->info, PROFILE_IDC, sps->profile_idc);
> + rkvdec_set_bw_field(hw_ps->info, CONSTRAINT_SET3_FLAG,
> + !!(sps->constraint_set_flags & (1 << 3)));
> + rkvdec_set_bw_field(hw_ps->info, CHROMA_FORMAT_IDC, sps->chroma_format_idc);
> + rkvdec_set_bw_field(hw_ps->info, BIT_DEPTH_LUMA, sps->bit_depth_luma_minus8);
> + rkvdec_set_bw_field(hw_ps->info, BIT_DEPTH_CHROMA, sps->bit_depth_chroma_minus8);
> + rkvdec_set_bw_field(hw_ps->info, QPPRIME_Y_ZERO_TRANSFORM_BYPASS_FLAG,
> + !!(sps->flags & V4L2_H264_SPS_FLAG_QPPRIME_Y_ZERO_TRANSFORM_BYPASS));
> + rkvdec_set_bw_field(hw_ps->info, LOG2_MAX_FRAME_NUM_MINUS4,
> + sps->log2_max_frame_num_minus4);
> + rkvdec_set_bw_field(hw_ps->info, MAX_NUM_REF_FRAMES, sps->max_num_ref_frames);
> + rkvdec_set_bw_field(hw_ps->info, PIC_ORDER_CNT_TYPE, sps->pic_order_cnt_type);
> + rkvdec_set_bw_field(hw_ps->info, LOG2_MAX_PIC_ORDER_CNT_LSB_MINUS4,
> + sps->log2_max_pic_order_cnt_lsb_minus4);
> + rkvdec_set_bw_field(hw_ps->info, DELTA_PIC_ORDER_ALWAYS_ZERO_FLAG,
> + !!(sps->flags & V4L2_H264_SPS_FLAG_DELTA_PIC_ORDER_ALWAYS_ZERO));
> + rkvdec_set_bw_field(hw_ps->info, MVC_EXTENSION_ENABLE, 0);
> + rkvdec_set_bw_field(hw_ps->info, NUM_VIEWS, 0);
>
> /*
> * Use the SPS values since they are already in macroblocks
> @@ -245,48 +146,72 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx,
> if (!!(dec_params->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC))
> pic_height /= 2;
>
> - hw_ps->sps.pic_width_in_mbs = pic_width;
> - hw_ps->sps.pic_height_in_mbs = pic_height;
> + rkvdec_set_bw_field(hw_ps->info, PIC_WIDTH_IN_MBS, pic_width);
> + rkvdec_set_bw_field(hw_ps->info, PIC_HEIGHT_IN_MBS, pic_height);
>
> - hw_ps->sps.frame_mbs_only_flag =
> - !!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY);
> - hw_ps->sps.mb_adaptive_frame_field_flag =
> - !!(sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD);
> - hw_ps->sps.direct_8x8_inference_flag =
> - !!(sps->flags & V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE);
> + rkvdec_set_bw_field(hw_ps->info, FRAME_MBS_ONLY_FLAG,
> + !!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY));
> + rkvdec_set_bw_field(hw_ps->info, MB_ADAPTIVE_FRAME_FIELD_FLAG,
> + !!(sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD));
> + rkvdec_set_bw_field(hw_ps->info, DIRECT_8X8_INFERENCE_FLAG,
> + !!(sps->flags & V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE));
>
> /* write pps */
> - hw_ps->pps.pic_parameter_set_id = pps->pic_parameter_set_id;
> - hw_ps->pps.pps_seq_parameter_set_id = pps->seq_parameter_set_id;
> - hw_ps->pps.entropy_coding_mode_flag =
> - !!(pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE);
> - hw_ps->pps.bottom_field_pic_order_in_frame_present_flag =
> - !!(pps->flags & V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT);
> - hw_ps->pps.num_ref_idx_l0_default_active_minus1 =
> - pps->num_ref_idx_l0_default_active_minus1;
> - hw_ps->pps.num_ref_idx_l1_default_active_minus1 =
> - pps->num_ref_idx_l1_default_active_minus1;
> - hw_ps->pps.weighted_pred_flag =
> - !!(pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED);
> - hw_ps->pps.weighted_bipred_idc = pps->weighted_bipred_idc;
> - hw_ps->pps.pic_init_qp_minus26 = pps->pic_init_qp_minus26;
> - hw_ps->pps.pic_init_qs_minus26 = pps->pic_init_qs_minus26;
> - hw_ps->pps.chroma_qp_index_offset = pps->chroma_qp_index_offset;
> - hw_ps->pps.deblocking_filter_control_present_flag =
> - !!(pps->flags & V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT);
> - hw_ps->pps.constrained_intra_pred_flag =
> - !!(pps->flags & V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED);
> - hw_ps->pps.redundant_pic_cnt_present =
> - !!(pps->flags & V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT);
> - hw_ps->pps.transform_8x8_mode_flag =
> - !!(pps->flags & V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE);
> - hw_ps->pps.second_chroma_qp_index_offset = pps->second_chroma_qp_index_offset;
> - hw_ps->pps.scaling_list_enable_flag =
> - !!(pps->flags & V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT);
> -
> - set_field_order_cnt(&hw_ps->pps, dpb);
> - set_dec_params(&hw_ps->pps, dec_params);
> + rkvdec_set_bw_field(hw_ps->info, PIC_PARAMETER_SET_ID, pps->pic_parameter_set_id);
> + rkvdec_set_bw_field(hw_ps->info, PPS_SEQ_PARAMETER_SET_ID, pps->seq_parameter_set_id);
> + rkvdec_set_bw_field(hw_ps->info, ENTROPY_CODING_MODE_FLAG,
> + !!(pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE));
> + rkvdec_set_bw_field(hw_ps->info, BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT_FLAG,
> + !!(pps->flags &
> + V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT));
> + rkvdec_set_bw_field(hw_ps->info, NUM_REF_IDX_L_DEFAULT_ACTIVE_MINUS1(0),
> + pps->num_ref_idx_l0_default_active_minus1);
> + rkvdec_set_bw_field(hw_ps->info, NUM_REF_IDX_L_DEFAULT_ACTIVE_MINUS1(1),
> + pps->num_ref_idx_l1_default_active_minus1);
> + rkvdec_set_bw_field(hw_ps->info, WEIGHTED_PRED_FLAG,
> + !!(pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED));
> + rkvdec_set_bw_field(hw_ps->info, WEIGHTED_BIPRED_IDC, pps->weighted_bipred_idc);
> + rkvdec_set_bw_field(hw_ps->info, PIC_INIT_QP_MINUS26, pps->pic_init_qp_minus26);
> + rkvdec_set_bw_field(hw_ps->info, PIC_INIT_QS_MINUS26, pps->pic_init_qs_minus26);
> + rkvdec_set_bw_field(hw_ps->info, CHROMA_QP_INDEX_OFFSET, pps->chroma_qp_index_offset);
> + rkvdec_set_bw_field(hw_ps->info, DEBLOCKING_FILTER_CONTROL_PRESENT_FLAG,
> + !!(pps->flags & V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT));
> + rkvdec_set_bw_field(hw_ps->info, CONSTRAINED_INTRA_PRED_FLAG,
> + !!(pps->flags & V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED));
> + rkvdec_set_bw_field(hw_ps->info, REDUNDANT_PIC_CNT_PRESENT,
> + !!(pps->flags & V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT));
> + rkvdec_set_bw_field(hw_ps->info, TRANSFORM_8X8_MODE_FLAG,
> + !!(pps->flags & V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE));
> + rkvdec_set_bw_field(hw_ps->info, SECOND_CHROMA_QP_INDEX_OFFSET,
> + pps->second_chroma_qp_index_offset);
> + rkvdec_set_bw_field(hw_ps->info, SCALING_LIST_ENABLE_FLAG,
> + !!(pps->flags & V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT));
> +
> + for (i = 0; i < ARRAY_SIZE(dec_params->dpb); i++) {
> + rkvdec_set_bw_field(hw_ps->info, TOP_FIELD_ORDER_CNT(i),
> + dpb[i].top_field_order_cnt);
> + rkvdec_set_bw_field(hw_ps->info, BOT_FIELD_ORDER_CNT(i),
> + dpb[i].bottom_field_order_cnt);
> +
> + rkvdec_set_bw_field(hw_ps->info, IS_LONG_TERM(i),
> + !!(dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_LONG_TERM));
> + rkvdec_set_bw_field(hw_ps->info, REF_FIELD_FLAGS(i),
> + !!(dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_FIELD));
> + rkvdec_set_bw_field(hw_ps->info, REF_COLMV_USE_FLAG(i),
> + !!(dpb[i].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE));
> + rkvdec_set_bw_field(hw_ps->info, REF_TOPFIELD_USED(i),
> + !!(dpb[i].fields & V4L2_H264_TOP_FIELD_REF));
> + rkvdec_set_bw_field(hw_ps->info, REF_BOTFIELD_USED(i),
> + !!(dpb[i].fields & V4L2_H264_BOTTOM_FIELD_REF));
> + }
> +
> + rkvdec_set_bw_field(hw_ps->info, PIC_FIELD_FLAG,
> + !!(dec_params->flags & V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC));
> + rkvdec_set_bw_field(hw_ps->info, PIC_ASSOCIATED_FLAG,
> + !!(dec_params->flags & V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD));
>
> + rkvdec_set_bw_field(hw_ps->info, CUR_TOP_FIELD, dec_params->top_field_order_cnt);
> + rkvdec_set_bw_field(hw_ps->info, CUR_BOT_FIELD, dec_params->bottom_field_order_cnt);
> }
>
> static void rkvdec_write_regs(struct rkvdec_ctx *ctx)
> diff --git a/drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c b/drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c
> index 96d938ee70b0..3575338a531a 100644
> --- a/drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c
> +++ b/drivers/media/platform/rockchip/rkvdec/rkvdec-vdpu383-hevc.c
> @@ -13,149 +13,106 @@
> #include "rkvdec-rcb.h"
> #include "rkvdec-hevc-common.h"
> #include "rkvdec-vdpu383-regs.h"
> +#include "rkvdec-bitwriter.h"
> +
> +#define VIDEO_PARAMETER_SET_ID BW_FIELD(0, 4)
> +#define SEQ_PARAMETER_SET_ID BW_FIELD(4, 4)
> +#define CHROMA_FORMAT_IDC BW_FIELD(8, 2)
> +#define PIC_WIDTH_IN_LUMA_SAMPLES BW_FIELD(10, 16)
> +#define PIC_HEIGHT_IN_LUMA_SAMPLES BW_FIELD(26, 16)
> +#define BIT_DEPTH_LUMA BW_FIELD(42, 3)
> +#define BIT_DEPTH_CHROMA BW_FIELD(45, 3)
> +#define LOG2_MAX_PIC_ORDER_CNT_LSB BW_FIELD(48, 5)
> +#define LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE BW_FIELD(53, 2)
> +#define LOG2_MIN_LUMA_CODING_BLOCK_SIZE BW_FIELD(55, 3)
> +#define LOG2_MIN_TRANSFORM_BLOCK_SIZE BW_FIELD(58, 3)
> +#define LOG2_DIFF_MAX_MIN_LUMA_TRANSFORM_BLOCK_SIZE BW_FIELD(61, 2)
> +#define MAX_TRANSFORM_HIERARCHY_DEPTH_INTER BW_FIELD(63, 3)
> +#define MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA BW_FIELD(66, 3)
> +#define SCALING_LIST_ENABLED_FLAG BW_FIELD(69, 1)
> +#define AMP_ENABLED_FLAG BW_FIELD(70, 1)
> +#define SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG BW_FIELD(71, 1)
> +#define PCM_ENABLED_FLAG BW_FIELD(72, 1)
> +#define PCM_SAMPLE_BIT_DEPTH_LUMA BW_FIELD(73, 4)
> +#define PCM_SAMPLE_BIT_DEPTH_CHROMA BW_FIELD(77, 4)
> +#define PCM_LOOP_FILTER_DISABLED_FLAG BW_FIELD(81, 1)
> +#define LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE BW_FIELD(82, 3)
> +#define LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE BW_FIELD(85, 3)
> +#define NUM_SHORT_TERM_REF_PIC_SETS BW_FIELD(88, 7)
> +#define LONG_TERM_REF_PICS_PRESENT_FLAG BW_FIELD(95, 1)
> +#define NUM_LONG_TERM_REF_PICS_SPS BW_FIELD(96, 6)
> +#define SPS_TEMPORAL_MVP_ENABLED_FLAG BW_FIELD(102, 1)
> +#define STRONG_INTRA_SMOOTHING_ENABLED_FLAG BW_FIELD(103, 1)
> +#define SPS_MAX_DEC_PIC_BUFFERING_MINUS1 BW_FIELD(111, 4)
> +#define SEPARATE_COLOUR_PLANE_FLAG BW_FIELD(115, 1)
> +#define HIGH_PRECISION_OFFSETS_ENABLED_FLAG BW_FIELD(116, 1)
> +#define PERSISTENT_RICE_ADAPTATION_ENABLED_FLAG BW_FIELD(117, 1)
> +
> +/* PPS */
> +#define PIC_PARAMETER_SET_ID BW_FIELD(118, 6)
> +#define PPS_SEQ_PARAMETER_SET_ID BW_FIELD(124, 4)
> +#define DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG BW_FIELD(128, 1)
> +#define OUTPUT_FLAG_PRESENT_FLAG BW_FIELD(129, 1)
> +#define NUM_EXTRA_SLICE_HEADER_BITS BW_FIELD(130, 13)
> +#define SIGN_DATA_HIDING_ENABLED_FLAG BW_FIELD(143, 1)
> +#define CABAC_INIT_PRESENT_FLAG BW_FIELD(144, 1)
> +#define NUM_REF_IDX_L0_DEFAULT_ACTIVE BW_FIELD(145, 4)
> +#define NUM_REF_IDX_L1_DEFAULT_ACTIVE BW_FIELD(149, 4)
> +#define INIT_QP_MINUS26 BW_FIELD(153, 7)
> +#define CONSTRAINED_INTRA_PRED_FLAG BW_FIELD(160, 1)
> +#define TRANSFORM_SKIP_ENABLED_FLAG BW_FIELD(161, 1)
> +#define CU_QP_DELTA_ENABLED_FLAG BW_FIELD(162, 1)
> +#define LOG2_MIN_CU_QP_DELTA_SIZE BW_FIELD(163, 3)
> +#define PPS_CB_QP_OFFSET BW_FIELD(166, 5)
> +#define PPS_CR_QP_OFFSET BW_FIELD(171, 5)
> +#define PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT_FLAG BW_FIELD(176, 1)
> +#define WEIGHTED_PRED_FLAG BW_FIELD(177, 1)
> +#define WEIGHTED_BIPRED_FLAG BW_FIELD(178, 1)
> +#define TRANSQUANT_BYPASS_ENABLED_FLAG BW_FIELD(179, 1)
> +#define TILES_ENABLED_FLAG BW_FIELD(180, 1)
> +#define ENTROPY_CODING_SYNC_ENABLED_FLAG BW_FIELD(181, 1)
> +#define PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG BW_FIELD(182, 1)
> +#define LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG BW_FIELD(183, 1)
> +#define DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG BW_FIELD(184, 1)
> +#define PPS_DEBLOCKING_FILTER_DISABLED_FLAG BW_FIELD(185, 1)
> +#define PPS_BETA_OFFSET_DIV2 BW_FIELD(186, 4)
> +#define PPS_TC_OFFSET_DIV2 BW_FIELD(190, 4)
> +#define LISTS_MODIFICATION_PRESENT_FLAG BW_FIELD(194, 1)
> +#define LOG2_PARALLEL_MERGE_LEVEL BW_FIELD(195, 3)
> +#define SLICE_SEGMENT_HEADER_EXTENSION_PRESENT_FLAG BW_FIELD(198, 1)
> +
> +/* pps extensions */
> +#define LOG2_MAX_TRANSFORM_SKIP_BLOCK_SIZE BW_FIELD(202, 2)
> +#define CROSS_COMPONENT_PREDICTION_ENABLED_FLAG BW_FIELD(204, 1)
> +#define CHROMA_QP_OFFSET_LIST_ENABLED_FLAG BW_FIELD(205, 1)
> +#define LOG2_MIN_CU_CHROMA_QP_DELTA_SIZE BW_FIELD(206, 3)
> +#define CB_QP_OFFSET_LIST(i) BW_FIELD(209 + (i) * 5, 5) // i: 0-5
> +#define CB_CR_OFFSET_LIST(i) BW_FIELD(239 + (i) * 5, 5) // i: 0-5
> +#define CHROMA_QP_OFFSET_LIST_LEN_MINUS1 BW_FIELD(269, 3)
> +
> +/* mvc0 && mvc1 */
> +#define MVC_FF BW_FIELD(272, 16)
> +#define MVC_00 BW_FIELD(288, 9)
> +
> +/* poc info */
> +#define RESERVED2 BW_FIELD(297, 3)
> +#define CURRENT_POC BW_FIELD(300, 32)
> +#define REF_PIC_POC(i) BW_FIELD(332 + (i) * 32, 32) // i: 0-14
> +#define RESERVED3 BW_FIELD(812, 32)
> +#define REF_IS_VALID(i) BW_FIELD(844 + (i), 1) // i: 0-14
> +#define RESERVED4 BW_FIELD(859, 1)
> +
> +/* tile info*/
> +#define NUM_TILE_COLUMNS BW_FIELD(860, 5)
> +#define NUM_TILE_ROWS BW_FIELD(865, 5)
> +#define COLUMN_WIDTH(i) BW_FIELD(870 + (i) * 12, 12) // i: 0-19
> +#define ROW_HEIGHT(i) BW_FIELD(1110 + (i) * 12, 12) // i: 0-21
> +
> +#define HEVC_SPS_SIZE ALIGN(1110 + 22 * 12, 256)
>
> struct rkvdec_hevc_sps_pps {
> - // SPS
> - u16 video_parameters_set_id : 4;
> - u16 seq_parameters_set_id_sps : 4;
> - u16 chroma_format_idc : 2;
> - u16 width : 16;
> - u16 height : 16;
> - u16 bit_depth_luma : 3;
> - u16 bit_depth_chroma : 3;
> - u16 max_pic_order_count_lsb : 5;
> - u16 diff_max_min_luma_coding_block_size : 2;
> - u16 min_luma_coding_block_size : 3;
> - u16 min_transform_block_size : 3;
> - u16 diff_max_min_transform_block_size : 2;
> - u16 max_transform_hierarchy_depth_inter : 3;
> - u16 max_transform_hierarchy_depth_intra : 3;
> - u16 scaling_list_enabled_flag : 1;
> - u16 amp_enabled_flag : 1;
> - u16 sample_adaptive_offset_enabled_flag : 1;
> - u16 pcm_enabled_flag : 1;
> - u16 pcm_sample_bit_depth_luma : 4;
> - u16 pcm_sample_bit_depth_chroma : 4;
> - u16 pcm_loop_filter_disabled_flag : 1;
> - u16 diff_max_min_pcm_luma_coding_block_size : 3;
> - u16 min_pcm_luma_coding_block_size : 3;
> - u16 num_short_term_ref_pic_sets : 7;
> - u16 long_term_ref_pics_present_flag : 1;
> - u16 num_long_term_ref_pics_sps : 6;
> - u16 sps_temporal_mvp_enabled_flag : 1;
> - u16 strong_intra_smoothing_enabled_flag : 1;
> - u16 reserved0 : 7;
> - u16 sps_max_dec_pic_buffering_minus1 : 4;
> - u16 separate_colour_plane_flag : 1;
> - u16 high_precision_offsets_enabled_flag : 1;
> - u16 persistent_rice_adaptation_enabled_flag : 1;
> -
> - // PPS
> - u16 picture_parameters_set_id : 6;
> - u16 seq_parameters_set_id_pps : 4;
> - u16 dependent_slice_segments_enabled_flag : 1;
> - u16 output_flag_present_flag : 1;
> - u16 num_extra_slice_header_bits : 13;
> - u16 sign_data_hiding_enabled_flag : 1;
> - u16 cabac_init_present_flag : 1;
> - u16 num_ref_idx_l0_default_active : 4;
> - u16 num_ref_idx_l1_default_active : 4;
> - u16 init_qp_minus26 : 7;
> - u16 constrained_intra_pred_flag : 1;
> - u16 transform_skip_enabled_flag : 1;
> - u16 cu_qp_delta_enabled_flag : 1;
> - u16 log2_min_cb_size : 3;
> - u16 pps_cb_qp_offset : 5;
> - u16 pps_cr_qp_offset : 5;
> - u16 pps_slice_chroma_qp_offsets_present_flag : 1;
> - u16 weighted_pred_flag : 1;
> - u16 weighted_bipred_flag : 1;
> - u16 transquant_bypass_enabled_flag : 1;
> - u16 tiles_enabled_flag : 1;
> - u16 entropy_coding_sync_enabled_flag : 1;
> - u16 pps_loop_filter_across_slices_enabled_flag : 1;
> - u16 loop_filter_across_tiles_enabled_flag : 1;
> - u16 deblocking_filter_override_enabled_flag : 1;
> - u16 pps_deblocking_filter_disabled_flag : 1;
> - u16 pps_beta_offset_div2 : 4;
> - u16 pps_tc_offset_div2 : 4;
> - u16 lists_modification_present_flag : 1;
> - u16 log2_parallel_merge_level : 3;
> - u16 slice_segment_header_extension_present_flag : 1;
> - u16 reserved1 : 3;
> -
> - // pps extensions
> - u16 log2_max_transform_skip_block_size : 2;
> - u16 cross_component_prediction_enabled_flag : 1;
> - u16 chroma_qp_offset_list_enabled_flag : 1;
> - u16 log2_min_cu_chroma_qp_delta_size : 3;
> - u16 cb_qp_offset_list0 : 5;
> - u16 cb_qp_offset_list1 : 5;
> - u16 cb_qp_offset_list2 : 5;
> - u16 cb_qp_offset_list3 : 5;
> - u16 cb_qp_offset_list4 : 5;
> - u16 cb_qp_offset_list5 : 5;
> - u16 cb_cr_offset_list0 : 5;
> - u16 cb_cr_offset_list1 : 5;
> - u16 cb_cr_offset_list2 : 5;
> - u16 cb_cr_offset_list3 : 5;
> - u16 cb_cr_offset_list4 : 5;
> - u16 cb_cr_offset_list5 : 5;
> - u16 chroma_qp_offset_list_len_minus1 : 3;
> -
> - /* mvc0 && mvc1 */
> - u16 mvc_ff : 16;
> - u16 mvc_00 : 9;
> -
> - /* poc info */
> - u16 reserved2 : 3;
> - u32 current_poc : 32;
> - u32 ref_pic_poc0 : 32;
> - u32 ref_pic_poc1 : 32;
> - u32 ref_pic_poc2 : 32;
> - u32 ref_pic_poc3 : 32;
> - u32 ref_pic_poc4 : 32;
> - u32 ref_pic_poc5 : 32;
> - u32 ref_pic_poc6 : 32;
> - u32 ref_pic_poc7 : 32;
> - u32 ref_pic_poc8 : 32;
> - u32 ref_pic_poc9 : 32;
> - u32 ref_pic_poc10 : 32;
> - u32 ref_pic_poc11 : 32;
> - u32 ref_pic_poc12 : 32;
> - u32 ref_pic_poc13 : 32;
> - u32 ref_pic_poc14 : 32;
> - u32 reserved3 : 32;
> - u32 ref_is_valid : 15;
> - u32 reserved4 : 1;
> -
> - /* tile info*/
> - u16 num_tile_columns : 5;
> - u16 num_tile_rows : 5;
> - u32 column_width0 : 24;
> - u32 column_width1 : 24;
> - u32 column_width2 : 24;
> - u32 column_width3 : 24;
> - u32 column_width4 : 24;
> - u32 column_width5 : 24;
> - u32 column_width6 : 24;
> - u32 column_width7 : 24;
> - u32 column_width8 : 24;
> - u32 column_width9 : 24;
> - u32 row_height0 : 24;
> - u32 row_height1 : 24;
> - u32 row_height2 : 24;
> - u32 row_height3 : 24;
> - u32 row_height4 : 24;
> - u32 row_height5 : 24;
> - u32 row_height6 : 24;
> - u32 row_height7 : 24;
> - u32 row_height8 : 24;
> - u32 row_height9 : 24;
> - u32 row_height10 : 24;
> - u32 reserved5 : 2;
> - u32 padding;
> -} __packed;
> + u32 info[HEVC_SPS_SIZE / 8 / 4];
> +};
>
> struct rkvdec_hevc_priv_tbl {
> struct rkvdec_hevc_sps_pps param_set;
> @@ -171,51 +128,6 @@ struct rkvdec_hevc_ctx {
> struct vdpu383_regs_h26x regs;
> };
>
> -static void set_column_row(struct rkvdec_hevc_sps_pps *hw_ps, u16 *column, u16 *row)
> -{
> - hw_ps->column_width0 = column[0] | (column[1] << 12);
> - hw_ps->row_height0 = row[0] | (row[1] << 12);
> - hw_ps->column_width1 = column[2] | (column[3] << 12);
> - hw_ps->row_height1 = row[2] | (row[3] << 12);
> - hw_ps->column_width2 = column[4] | (column[5] << 12);
> - hw_ps->row_height2 = row[4] | (row[5] << 12);
> - hw_ps->column_width3 = column[6] | (column[7] << 12);
> - hw_ps->row_height3 = row[6] | (row[7] << 12);
> - hw_ps->column_width4 = column[8] | (column[9] << 12);
> - hw_ps->row_height4 = row[8] | (row[9] << 12);
> - hw_ps->column_width5 = column[10] | (column[11] << 12);
> - hw_ps->row_height5 = row[10] | (row[11] << 12);
> - hw_ps->column_width6 = column[12] | (column[13] << 12);
> - hw_ps->row_height6 = row[12] | (row[13] << 12);
> - hw_ps->column_width7 = column[14] | (column[15] << 12);
> - hw_ps->row_height7 = row[14] | (row[15] << 12);
> - hw_ps->column_width8 = column[16] | (column[17] << 12);
> - hw_ps->row_height8 = row[16] | (row[17] << 12);
> - hw_ps->column_width9 = column[18] | (column[19] << 12);
> - hw_ps->row_height9 = row[18] | (row[19] << 12);
> -
> - hw_ps->row_height10 = row[20] | (row[21] << 12);
> -}
> -
> -static void set_pps_ref_pic_poc(struct rkvdec_hevc_sps_pps *hw_ps, const struct v4l2_hevc_dpb_entry *dpb)
> -{
> - hw_ps->ref_pic_poc0 = dpb[0].pic_order_cnt_val;
> - hw_ps->ref_pic_poc1 = dpb[1].pic_order_cnt_val;
> - hw_ps->ref_pic_poc2 = dpb[2].pic_order_cnt_val;
> - hw_ps->ref_pic_poc3 = dpb[3].pic_order_cnt_val;
> - hw_ps->ref_pic_poc4 = dpb[4].pic_order_cnt_val;
> - hw_ps->ref_pic_poc5 = dpb[5].pic_order_cnt_val;
> - hw_ps->ref_pic_poc6 = dpb[6].pic_order_cnt_val;
> - hw_ps->ref_pic_poc7 = dpb[7].pic_order_cnt_val;
> - hw_ps->ref_pic_poc8 = dpb[8].pic_order_cnt_val;
> - hw_ps->ref_pic_poc9 = dpb[9].pic_order_cnt_val;
> - hw_ps->ref_pic_poc10 = dpb[10].pic_order_cnt_val;
> - hw_ps->ref_pic_poc11 = dpb[11].pic_order_cnt_val;
> - hw_ps->ref_pic_poc12 = dpb[12].pic_order_cnt_val;
> - hw_ps->ref_pic_poc13 = dpb[13].pic_order_cnt_val;
> - hw_ps->ref_pic_poc14 = dpb[14].pic_order_cnt_val;
> -}
> -
> static void assemble_hw_pps(struct rkvdec_ctx *ctx,
> struct rkvdec_hevc_run *run)
> {
> @@ -245,104 +157,130 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx,
> memset(hw_ps, 0, sizeof(*hw_ps));
>
> /* write sps */
> - hw_ps->video_parameters_set_id = sps->video_parameter_set_id;
> - hw_ps->seq_parameters_set_id_sps = sps->seq_parameter_set_id;
> - hw_ps->chroma_format_idc = sps->chroma_format_idc;
> + rkvdec_set_bw_field(hw_ps->info, VIDEO_PARAMETER_SET_ID, sps->video_parameter_set_id);
> + rkvdec_set_bw_field(hw_ps->info, SEQ_PARAMETER_SET_ID, sps->seq_parameter_set_id);
> + rkvdec_set_bw_field(hw_ps->info, CHROMA_FORMAT_IDC, sps->chroma_format_idc);
>
> log2_min_cb_size = sps->log2_min_luma_coding_block_size_minus3 + 3;
> width = sps->pic_width_in_luma_samples;
> height = sps->pic_height_in_luma_samples;
> - hw_ps->width = width;
> - hw_ps->height = height;
> - hw_ps->bit_depth_luma = sps->bit_depth_luma_minus8 + 8;
> - hw_ps->bit_depth_chroma = sps->bit_depth_chroma_minus8 + 8;
> - hw_ps->max_pic_order_count_lsb = sps->log2_max_pic_order_cnt_lsb_minus4 + 4;
> - hw_ps->diff_max_min_luma_coding_block_size = sps->log2_diff_max_min_luma_coding_block_size;
> - hw_ps->min_luma_coding_block_size = sps->log2_min_luma_coding_block_size_minus3 + 3;
> - hw_ps->min_transform_block_size = sps->log2_min_luma_transform_block_size_minus2 + 2;
> - hw_ps->diff_max_min_transform_block_size =
> - sps->log2_diff_max_min_luma_transform_block_size;
> - hw_ps->max_transform_hierarchy_depth_inter = sps->max_transform_hierarchy_depth_inter;
> - hw_ps->max_transform_hierarchy_depth_intra = sps->max_transform_hierarchy_depth_intra;
> - hw_ps->scaling_list_enabled_flag =
> - !!(sps->flags & V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED);
> - hw_ps->amp_enabled_flag = !!(sps->flags & V4L2_HEVC_SPS_FLAG_AMP_ENABLED);
> - hw_ps->sample_adaptive_offset_enabled_flag =
> - !!(sps->flags & V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET);
> +
> + rkvdec_set_bw_field(hw_ps->info, PIC_WIDTH_IN_LUMA_SAMPLES, width);
> + rkvdec_set_bw_field(hw_ps->info, PIC_HEIGHT_IN_LUMA_SAMPLES, height);
> + rkvdec_set_bw_field(hw_ps->info, BIT_DEPTH_LUMA, sps->bit_depth_luma_minus8 + 8);
> + rkvdec_set_bw_field(hw_ps->info, BIT_DEPTH_CHROMA, sps->bit_depth_chroma_minus8 + 8);
> + rkvdec_set_bw_field(hw_ps->info, LOG2_MAX_PIC_ORDER_CNT_LSB,
> + sps->log2_max_pic_order_cnt_lsb_minus4 + 4);
> + rkvdec_set_bw_field(hw_ps->info, LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE,
> + sps->log2_diff_max_min_luma_coding_block_size);
> + rkvdec_set_bw_field(hw_ps->info, LOG2_MIN_LUMA_CODING_BLOCK_SIZE,
> + sps->log2_min_luma_coding_block_size_minus3 + 3);
> + rkvdec_set_bw_field(hw_ps->info, LOG2_MIN_TRANSFORM_BLOCK_SIZE,
> + sps->log2_min_luma_transform_block_size_minus2 + 2);
> + rkvdec_set_bw_field(hw_ps->info, LOG2_DIFF_MAX_MIN_LUMA_TRANSFORM_BLOCK_SIZE,
> + sps->log2_diff_max_min_luma_transform_block_size);
> + rkvdec_set_bw_field(hw_ps->info, MAX_TRANSFORM_HIERARCHY_DEPTH_INTER,
> + sps->max_transform_hierarchy_depth_inter);
> + rkvdec_set_bw_field(hw_ps->info, MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA,
> + sps->max_transform_hierarchy_depth_intra);
> + rkvdec_set_bw_field(hw_ps->info, SCALING_LIST_ENABLED_FLAG,
> + !!(sps->flags & V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED));
> + rkvdec_set_bw_field(hw_ps->info, AMP_ENABLED_FLAG,
> + !!(sps->flags & V4L2_HEVC_SPS_FLAG_AMP_ENABLED));
> + rkvdec_set_bw_field(hw_ps->info, SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG,
> + !!(sps->flags & V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET));
>
> pcm_enabled = !!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_ENABLED);
> - hw_ps->pcm_enabled_flag = pcm_enabled;
> - hw_ps->pcm_sample_bit_depth_luma =
> - pcm_enabled ? sps->pcm_sample_bit_depth_luma_minus1 + 1 : 0;
> - hw_ps->pcm_sample_bit_depth_chroma =
> - pcm_enabled ? sps->pcm_sample_bit_depth_chroma_minus1 + 1 : 0;
> - hw_ps->pcm_loop_filter_disabled_flag =
> - !!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED);
> - hw_ps->diff_max_min_pcm_luma_coding_block_size =
> - sps->log2_diff_max_min_pcm_luma_coding_block_size;
> - hw_ps->min_pcm_luma_coding_block_size =
> - pcm_enabled ? sps->log2_min_pcm_luma_coding_block_size_minus3 + 3 : 0;
> - hw_ps->num_short_term_ref_pic_sets = sps->num_short_term_ref_pic_sets;
> - hw_ps->long_term_ref_pics_present_flag =
> - !!(sps->flags & V4L2_HEVC_SPS_FLAG_LONG_TERM_REF_PICS_PRESENT);
> - hw_ps->num_long_term_ref_pics_sps = sps->num_long_term_ref_pics_sps;
> - hw_ps->sps_temporal_mvp_enabled_flag =
> - !!(sps->flags & V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED);
> - hw_ps->strong_intra_smoothing_enabled_flag =
> - !!(sps->flags & V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED);
> - hw_ps->sps_max_dec_pic_buffering_minus1 = sps->sps_max_dec_pic_buffering_minus1;
> + rkvdec_set_bw_field(hw_ps->info, PCM_ENABLED_FLAG, pcm_enabled);
> + rkvdec_set_bw_field(hw_ps->info, PCM_SAMPLE_BIT_DEPTH_LUMA,
> + pcm_enabled ? sps->pcm_sample_bit_depth_luma_minus1 + 1 : 0);
> + rkvdec_set_bw_field(hw_ps->info, PCM_SAMPLE_BIT_DEPTH_CHROMA,
> + pcm_enabled ? sps->pcm_sample_bit_depth_chroma_minus1 + 1 : 0);
> + rkvdec_set_bw_field(hw_ps->info, PCM_LOOP_FILTER_DISABLED_FLAG,
> + !!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED));
> + rkvdec_set_bw_field(hw_ps->info, LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE,
> + sps->log2_diff_max_min_pcm_luma_coding_block_size);
> + rkvdec_set_bw_field(hw_ps->info, LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE,
> + pcm_enabled ? sps->log2_min_pcm_luma_coding_block_size_minus3 + 3 : 0);
> + rkvdec_set_bw_field(hw_ps->info, NUM_SHORT_TERM_REF_PIC_SETS,
> + sps->num_short_term_ref_pic_sets);
> + rkvdec_set_bw_field(hw_ps->info, LONG_TERM_REF_PICS_PRESENT_FLAG,
> + !!(sps->flags & V4L2_HEVC_SPS_FLAG_LONG_TERM_REF_PICS_PRESENT));
> + rkvdec_set_bw_field(hw_ps->info, NUM_LONG_TERM_REF_PICS_SPS,
> + sps->num_long_term_ref_pics_sps);
> + rkvdec_set_bw_field(hw_ps->info, SPS_TEMPORAL_MVP_ENABLED_FLAG,
> + !!(sps->flags & V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED));
> + rkvdec_set_bw_field(hw_ps->info, STRONG_INTRA_SMOOTHING_ENABLED_FLAG,
> + !!(sps->flags & V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED));
> + rkvdec_set_bw_field(hw_ps->info, SPS_MAX_DEC_PIC_BUFFERING_MINUS1,
> + sps->sps_max_dec_pic_buffering_minus1);
>
> /* write pps */
> - hw_ps->picture_parameters_set_id = pps->pic_parameter_set_id;
> - hw_ps->seq_parameters_set_id_pps = sps->seq_parameter_set_id;
> - hw_ps->dependent_slice_segments_enabled_flag =
> - !!(pps->flags & V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED);
> - hw_ps->output_flag_present_flag = !!(pps->flags & V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT);
> - hw_ps->num_extra_slice_header_bits = pps->num_extra_slice_header_bits;
> - hw_ps->sign_data_hiding_enabled_flag =
> - !!(pps->flags & V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED);
> - hw_ps->cabac_init_present_flag = !!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT);
> - hw_ps->num_ref_idx_l0_default_active = pps->num_ref_idx_l0_default_active_minus1 + 1;
> - hw_ps->num_ref_idx_l1_default_active = pps->num_ref_idx_l1_default_active_minus1 + 1;
> - hw_ps->init_qp_minus26 = pps->init_qp_minus26;
> - hw_ps->constrained_intra_pred_flag =
> - !!(pps->flags & V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED);
> - hw_ps->transform_skip_enabled_flag =
> - !!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED);
> - hw_ps->cu_qp_delta_enabled_flag = !!(pps->flags & V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED);
> - hw_ps->log2_min_cb_size = log2_min_cb_size +
> - sps->log2_diff_max_min_luma_coding_block_size -
> - pps->diff_cu_qp_delta_depth;
> - hw_ps->pps_cb_qp_offset = pps->pps_cb_qp_offset;
> - hw_ps->pps_cr_qp_offset = pps->pps_cr_qp_offset;
> - hw_ps->pps_slice_chroma_qp_offsets_present_flag =
> - !!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT);
> - hw_ps->weighted_pred_flag = !!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED);
> - hw_ps->weighted_bipred_flag = !!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED);
> - hw_ps->transquant_bypass_enabled_flag =
> - !!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED);
> + rkvdec_set_bw_field(hw_ps->info, PIC_PARAMETER_SET_ID, pps->pic_parameter_set_id);
> + rkvdec_set_bw_field(hw_ps->info, SEQ_PARAMETER_SET_ID, sps->seq_parameter_set_id);
> + rkvdec_set_bw_field(hw_ps->info, DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG,
> + !!(pps->flags & V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED));
> + rkvdec_set_bw_field(hw_ps->info, OUTPUT_FLAG_PRESENT_FLAG,
> + !!(pps->flags & V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT));
> + rkvdec_set_bw_field(hw_ps->info, NUM_EXTRA_SLICE_HEADER_BITS,
> + pps->num_extra_slice_header_bits);
> + rkvdec_set_bw_field(hw_ps->info, SIGN_DATA_HIDING_ENABLED_FLAG,
> + !!(pps->flags & V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED));
> + rkvdec_set_bw_field(hw_ps->info, CABAC_INIT_PRESENT_FLAG,
> + !!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT));
> + rkvdec_set_bw_field(hw_ps->info, NUM_REF_IDX_L0_DEFAULT_ACTIVE,
> + pps->num_ref_idx_l0_default_active_minus1 + 1);
> + rkvdec_set_bw_field(hw_ps->info, NUM_REF_IDX_L1_DEFAULT_ACTIVE,
> + pps->num_ref_idx_l1_default_active_minus1 + 1);
> + rkvdec_set_bw_field(hw_ps->info, INIT_QP_MINUS26, pps->init_qp_minus26);
> + rkvdec_set_bw_field(hw_ps->info, CONSTRAINED_INTRA_PRED_FLAG,
> + !!(pps->flags & V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED));
> + rkvdec_set_bw_field(hw_ps->info, TRANSFORM_SKIP_ENABLED_FLAG,
> + !!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED));
> + rkvdec_set_bw_field(hw_ps->info, CU_QP_DELTA_ENABLED_FLAG,
> + !!(pps->flags & V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED));
> + rkvdec_set_bw_field(hw_ps->info, LOG2_MIN_CU_QP_DELTA_SIZE, log2_min_cb_size +
> + sps->log2_diff_max_min_luma_coding_block_size -
> + pps->diff_cu_qp_delta_depth);
> + rkvdec_set_bw_field(hw_ps->info, PPS_CB_QP_OFFSET, pps->pps_cb_qp_offset);
> + rkvdec_set_bw_field(hw_ps->info, PPS_CR_QP_OFFSET, pps->pps_cr_qp_offset);
> + rkvdec_set_bw_field(hw_ps->info, PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT_FLAG,
> + !!(pps->flags &
> + V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT));
> + rkvdec_set_bw_field(hw_ps->info, WEIGHTED_PRED_FLAG,
> + !!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED));
> + rkvdec_set_bw_field(hw_ps->info, WEIGHTED_BIPRED_FLAG,
> + !!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED));
> + rkvdec_set_bw_field(hw_ps->info, TRANSQUANT_BYPASS_ENABLED_FLAG,
> + !!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED));
> tiles_enabled = !!(pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED);
> - hw_ps->tiles_enabled_flag = tiles_enabled;
> - hw_ps->entropy_coding_sync_enabled_flag =
> - !!(pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED);
> - hw_ps->pps_loop_filter_across_slices_enabled_flag =
> - !!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED);
> - hw_ps->loop_filter_across_tiles_enabled_flag =
> - !!(pps->flags & V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED);
> - hw_ps->deblocking_filter_override_enabled_flag =
> - !!(pps->flags & V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED);
> - hw_ps->pps_deblocking_filter_disabled_flag =
> - !!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER);
> - hw_ps->pps_beta_offset_div2 = pps->pps_beta_offset_div2;
> - hw_ps->pps_tc_offset_div2 = pps->pps_tc_offset_div2;
> - hw_ps->lists_modification_present_flag =
> - !!(pps->flags & V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT);
> - hw_ps->log2_parallel_merge_level = pps->log2_parallel_merge_level_minus2 + 2;
> - hw_ps->slice_segment_header_extension_present_flag =
> - !!(pps->flags & V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT);
> - hw_ps->num_tile_columns = tiles_enabled ? pps->num_tile_columns_minus1 + 1 : 1;
> - hw_ps->num_tile_rows = tiles_enabled ? pps->num_tile_rows_minus1 + 1 : 1;
> - hw_ps->mvc_ff = 0xffff;
> + rkvdec_set_bw_field(hw_ps->info, TILES_ENABLED_FLAG, tiles_enabled);
> + rkvdec_set_bw_field(hw_ps->info, ENTROPY_CODING_SYNC_ENABLED_FLAG,
> + !!(pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED));
> + rkvdec_set_bw_field(hw_ps->info, PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG,
> + !!(pps->flags &
> + V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED));
> + rkvdec_set_bw_field(hw_ps->info, LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG,
> + !!(pps->flags & V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED));
> + rkvdec_set_bw_field(hw_ps->info, DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG,
> + !!(pps->flags &
> + V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED));
> + rkvdec_set_bw_field(hw_ps->info, PPS_DEBLOCKING_FILTER_DISABLED_FLAG,
> + !!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER));
> + rkvdec_set_bw_field(hw_ps->info, PPS_BETA_OFFSET_DIV2, pps->pps_beta_offset_div2);
> + rkvdec_set_bw_field(hw_ps->info, PPS_TC_OFFSET_DIV2, pps->pps_tc_offset_div2);
> + rkvdec_set_bw_field(hw_ps->info, LISTS_MODIFICATION_PRESENT_FLAG,
> + !!(pps->flags & V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT));
> + rkvdec_set_bw_field(hw_ps->info, LOG2_PARALLEL_MERGE_LEVEL,
> + pps->log2_parallel_merge_level_minus2 + 2);
> + rkvdec_set_bw_field(hw_ps->info, SLICE_SEGMENT_HEADER_EXTENSION_PRESENT_FLAG,
> + !!(pps->flags &
> + V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT));
> + rkvdec_set_bw_field(hw_ps->info, NUM_TILE_COLUMNS,
> + tiles_enabled ? pps->num_tile_columns_minus1 + 1 : 1);
> + rkvdec_set_bw_field(hw_ps->info, NUM_TILE_ROWS,
> + tiles_enabled ? pps->num_tile_rows_minus1 + 1 : 1);
> + rkvdec_set_bw_field(hw_ps->info, MVC_FF, 0xffff);
>
> // Setup tiles information
> memset(column_width, 0, sizeof(column_width));
> @@ -367,15 +305,19 @@ static void assemble_hw_pps(struct rkvdec_ctx *ctx,
> row_height[0] = (height + max_cu_width - 1) / max_cu_width;
> }
>
> - set_column_row(hw_ps, column_width, row_height);
> + for (i = 0; i < 20; i++)
> + rkvdec_set_bw_field(hw_ps->info, COLUMN_WIDTH(i), column_width[i]);
> + for (i = 0; i < 22; i++)
> + rkvdec_set_bw_field(hw_ps->info, ROW_HEIGHT(i), row_height[i]);
>
> // Setup POC information
> - hw_ps->current_poc = dec_params->pic_order_cnt_val;
> + rkvdec_set_bw_field(hw_ps->info, CURRENT_POC, dec_params->pic_order_cnt_val);
>
> - set_pps_ref_pic_poc(hw_ps, dec_params->dpb);
> for (i = 0; i < ARRAY_SIZE(dec_params->dpb); i++) {
> - u32 valid = !!(dec_params->num_active_dpb_entries > i);
> - hw_ps->ref_is_valid |= valid << i;
> + rkvdec_set_bw_field(hw_ps->info, REF_IS_VALID(i),
> + !!(dec_params->num_active_dpb_entries > i));
> + rkvdec_set_bw_field(hw_ps->info, REF_PIC_POC(i),
> + dec_params->dpb[i].pic_order_cnt_val);
> }
> }
>
[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply
* Re: [PATCH v13 3/4] gpio: rpmsg: add generic rpmsg GPIO driver
From: Andrew Lunn @ 2026-04-29 18:21 UTC (permalink / raw)
To: Padhi, Beleswar
Cc: Shenwei Wang, Mathieu Poirier, Linus Walleij, Bartosz Golaszewski,
Jonathan Corbet, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson, Frank Li, Sascha Hauer, Shuah Khan,
linux-gpio@vger.kernel.org, linux-doc@vger.kernel.org,
linux-kernel@vger.kernel.org, Pengutronix Kernel Team,
Fabio Estevam, Peng Fan, devicetree@vger.kernel.org,
linux-remoteproc@vger.kernel.org, imx@lists.linux.dev,
linux-arm-kernel@lists.infradead.org, dl-linux-imx,
Bartosz Golaszewski
In-Reply-To: <b80e17fb-7986-4a95-a845-48a7d318ff33@ti.com>
> About this, we only need to do this because you are defining the gpio
> controller instances "statically" in the device tree. I understand gpio
> nodes can act as providers, but I do not see any device referencing the
> gpio nodes you are defining in the device tree.
They probably come later, and a board specific. The GPIO controllers
are probably SoC specific, so can be defined at the SoC .dtsi
level. The users are then in the board .dts files.
This is how GPIOs are typically used. Same will be true of I2C, the
SoC provides the I2C adaptor, the boards have devices on the bus,
again, described in DT.
Andrew
^ permalink raw reply
* Re: [GIT PULL 2/4] i.MX arm dts changes for v7.1
From: Krzysztof Kozlowski @ 2026-04-29 18:29 UTC (permalink / raw)
To: Sébastien Szymanski, Frank Li, soc, arm
Cc: Shawn Guo, Fabio Estevam, kernel, imx, linux-arm-kernel
In-Reply-To: <ab6b9b36-f08d-451a-9c2d-ef27b813d744@armadeus.com>
On 28/04/2026 16:03, Sébastien Szymanski wrote:
> Hello,
>
> On 3/30/26 4:14 PM, Frank Li wrote:
>> ARM: dts: imx: remove redundant intermediate node in pinmux hierarchy
>
> This commit breaks Linux 7.1-rc1 boot on my APF27Dev board. I see the
> following errors with earlyprintk enabled:
>
> [ 0.346162] imx27-pinctrl 10015000.pinmux: unable to find group for
> node i2c1grp
> [ 0.354438] imx27-pinctrl 10015000.pinmux: unable to find group for
> node i2c2grp
> ...
> [ 0.636217] imx27-pinctrl 10015000.pinmux: unable to find group for
> node pwmgrp
> [ 0.644346] imx27-pinctrl 10015000.pinmux: unable to find group for
> node gpioledsgrp
> [ 0.657247] imx27-pinctrl 10015000.pinmux: unable to find group for
> node uart1grp
> ...
> [ 0.868102] imx27-pinctrl 10015000.pinmux: unable to find group for
> node cspi1grp
> [ 0.876513] imx27-pinctrl 10015000.pinmux: unable to find group for
> node cspi2grp
> [ 0.888903] imx27-pinctrl 10015000.pinmux: unable to find group for
> node fec1grp
> ...
> [ 2.413181] imx27-pinctrl 10015000.pinmux: unable to find group for
> node gpiokeysgrp
>
> Reverting the commit makes the errors disappear and the board boot again.
>
> Should I send a patch reverting this commit ?
If you know how to fix it, then better fixing it instead of reverting,
but otherwise yes, revert is justified. Just give a few more days for
Frank or community to reply, because maybe there is a fix known.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v13 3/4] gpio: rpmsg: add generic rpmsg GPIO driver
From: Shenwei Wang @ 2026-04-29 18:35 UTC (permalink / raw)
To: Padhi, Beleswar, Mathieu Poirier
Cc: Andrew Lunn, Linus Walleij, Bartosz Golaszewski, Jonathan Corbet,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
Frank Li, Sascha Hauer, Shuah Khan, linux-gpio@vger.kernel.org,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
Pengutronix Kernel Team, Fabio Estevam, Peng Fan,
devicetree@vger.kernel.org, linux-remoteproc@vger.kernel.org,
imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
dl-linux-imx, Bartosz Golaszewski
In-Reply-To: <472f85bd-42c2-40c6-abfd-b76924797069@ti.com>
> -----Original Message-----
> From: Padhi, Beleswar <b-padhi@ti.com>
> Sent: Wednesday, April 29, 2026 1:07 PM
> To: Mathieu Poirier <mathieu.poirier@linaro.org>; Shenwei Wang
> <shenwei.wang@nxp.com>
> Cc: Andrew Lunn <andrew@lunn.ch>; Linus Walleij <linusw@kernel.org>; Bartosz
> Golaszewski <brgl@kernel.org>; Jonathan Corbet <corbet@lwn.net>; Rob Herring
> <robh@kernel.org>; Krzysztof Kozlowski <krzk+dt@kernel.org>; Conor Dooley
> <conor+dt@kernel.org>; Bjorn Andersson <andersson@kernel.org>; Frank Li
> <frank.li@nxp.com>; Sascha Hauer <s.hauer@pengutronix.de>; Shuah Khan
> <skhan@linuxfoundation.org>; linux-gpio@vger.kernel.org; linux-
> doc@vger.kernel.org; linux-kernel@vger.kernel.org; Pengutronix Kernel Team
> <kernel@pengutronix.de>; Fabio Estevam <festevam@gmail.com>; Peng Fan
> <peng.fan@nxp.com>; devicetree@vger.kernel.org; linux-
> remoteproc@vger.kernel.org; imx@lists.linux.dev; linux-arm-
> kernel@lists.infradead.org; dl-linux-imx <linux-imx@nxp.com>; Bartosz
> Golaszewski <brgl@bgdev.pl>
> Subject: [EXT] Re: [PATCH v13 3/4] gpio: rpmsg: add generic rpmsg GPIO driver
> Hi Mathieu,
>
> On 4/29/2026 11:03 PM, Mathieu Poirier wrote:
> > On Wed, 29 Apr 2026 at 10:53, Shenwei Wang <shenwei.wang@nxp.com>
> wrote:
> >>
> >>
> >>> -----Original Message-----
> >>> From: Mathieu Poirier <mathieu.poirier@linaro.org>
> >>> Sent: Wednesday, April 29, 2026 10:42 AM
> >>> To: Shenwei Wang <shenwei.wang@nxp.com>
> >>> Cc: Andrew Lunn <andrew@lunn.ch>; Padhi, Beleswar <b-padhi@ti.com>;
> >>> Linus Walleij <linusw@kernel.org>; Bartosz Golaszewski
> >>> <brgl@kernel.org>; Jonathan Corbet <corbet@lwn.net>; Rob Herring
> >>> <robh@kernel.org>; Krzysztof Kozlowski <krzk+dt@kernel.org>; Conor
> >>> Dooley <conor+dt@kernel.org>; Bjorn Andersson
> >>> <andersson@kernel.org>; Frank Li <frank.li@nxp.com>; Sascha Hauer
> >>> <s.hauer@pengutronix.de>; Shuah Khan <skhan@linuxfoundation.org>;
> >>> linux- gpio@vger.kernel.org; linux-doc@vger.kernel.org;
> >>> linux-kernel@vger.kernel.org; Pengutronix Kernel Team
> >>> <kernel@pengutronix.de>; Fabio Estevam <festevam@gmail.com>; Peng
> >>> Fan <peng.fan@nxp.com>; devicetree@vger.kernel.org;
> >>> linux-remoteproc@vger.kernel.org; imx@lists.linux.dev;
> >>> linux-arm-kernel@lists.infradead.org; dl-linux-imx <linux-
> >>> imx@nxp.com>; Bartosz Golaszewski <brgl@bgdev.pl>
> >>> Subject: [EXT] Re: [PATCH v13 3/4] gpio: rpmsg: add generic rpmsg
> >>> GPIO driver On Tue, Apr 28, 2026 at 03:24:59PM +0000, Shenwei Wang
> wrote:
> >>>>
> >>>>> -----Original Message-----
> >>>>> From: Andrew Lunn <andrew@lunn.ch>
> >>>>> Sent: Monday, April 27, 2026 3:49 PM
> >>>>> To: Shenwei Wang <shenwei.wang@nxp.com>
> >>>>> Cc: Padhi, Beleswar <b-padhi@ti.com>; Linus Walleij
> >>>>> <linusw@kernel.org>; Bartosz Golaszewski <brgl@kernel.org>;
> >>>>> Jonathan Corbet <corbet@lwn.net>; Rob Herring <robh@kernel.org>;
> >>>>> Krzysztof Kozlowski <krzk+dt@kernel.org>; Conor Dooley
> >>>>> <conor+dt@kernel.org>; Bjorn Andersson <andersson@kernel.org>;
> >>>>> Mathieu Poirier <mathieu.poirier@linaro.org>; Frank Li
> >>>>> <frank.li@nxp.com>; Sascha Hauer <s.hauer@pengutronix.de>; Shuah
> >>>>> Khan <skhan@linuxfoundation.org>; linux-gpio@vger.kernel.org;
> >>>>> linux- doc@vger.kernel.org; linux-kernel@vger.kernel.org;
> >>>>> Pengutronix Kernel Team <kernel@pengutronix.de>; Fabio Estevam
> >>>>> <festevam@gmail.com>; Peng Fan <peng.fan@nxp.com>;
> >>>>> devicetree@vger.kernel.org; linux- remoteproc@vger.kernel.org;
> >>>>> imx@lists.linux.dev; linux-arm- kernel@lists.infradead.org;
> >>>>> dl-linux-imx <linux-imx@nxp.com>; Bartosz Golaszewski
> >>>>> <brgl@bgdev.pl>
> >>>>> Subject: [EXT] Re: [PATCH v13 3/4] gpio: rpmsg: add generic rpmsg
> >>>>> GPIO driver
> >>>>>>> struct virtio_gpio_response {
> >>>>>>> __u8 status;
> >>>>>>> __u8 value;
> >>>>>>> };
> >>>>>> It is the same message format. Please see the message definition
> >>>>> (GET_DIRECTION) below:
> >>>>>
> >>>>>> + +-----+-----+-----+-----+-----+----+
> >>>>>> + |0x00 |0x01 |0x02 |0x03 |0x04 |0x05|
> >>>>>> + | 1 | 2 |port |line | err | dir|
> >>>>>> + +-----+-----+-----+-----+-----+----+
> >>>>> Sorry, but i don't see how two u8 vs six u8 are the same message format.
> >>>>>
> >>>> Some changes to the message format are necessary.
> >>>>
> >>>> Virtio uses two communication channels (virtqueues): one for
> >>>> requests and
> >>> replies, and a second one for events.
> >>>> In contrast, rpmsg provides only a single communication channel, so
> >>>> a type field is required to distinguish between different kinds of messages.
> >>>>
> >>>> Since rpmsg replies and events share the same message format, an
> >>>> additional
> >>> line is introduced to handle both cases.
> >>>> Finally, rpmsg supports multiple GPIO controllers, so a port field
> >>>> is added to
> >>> uniquely identify the target controller.
> >>>
> >>> I have commented on this before - RPMSG is already providing
> >>> multiplexing capability by way of endpoints. There is no need for a
> >>> port field. One endpoint, one GPIO controller.
> >>>
> >> You still need a way to let the remote side know which port the
> >> endpoint maps to, either by embedding the port information in the
> >> message (the current way), or by sending it separately.
> >>
> > An endpoint is created with every namespace request. There should be
> > one namespace request for every GPIO controller, which yields a unique
> > endpoint for each controller and eliminates the need for an extra
> > field to identify them.
>
>
> Right, but this can still be done by just having one namespace request.
> We can create new endpoints bound to an existing namespace/channel by
> invoking rpmsg_create_ept(). This is what I suggested here too:
> https://lore.kernel/
> .org%2Fall%2F29485742-6e49-482e-b73d-
> 228295daaeec%40ti.com%2F&data=05%7C02%7Cshenwei.wang%40nxp.com%7
> Caba62d7a899849fd57f708dea61a1d8b%7C686ea1d3bc2b4c6fa92cd99c5c3016
> 35%7C0%7C0%7C639130828278097401%7CUnknown%7CTWFpbGZsb3d8eyJFb
> XB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpb
> CIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=NLLYQ0NZCnYKLT%2F2OMDZE
> SKgC%2Fme3FoUNqqEGBOIY2k%3D&reserved=0
>
> My mental model looks like this for the complete picture:
>
> 1. namespace/channel#1 = rpmsg-io
> a. ept1 -> gpio-controller@1
> b. ept2 -> gpio-controller@2
>
> 2. namespace/channel#2 = rpmsg-i2c
> a. ept1 -> i2c@1
> b. ept2 -> i2c@2
> c. ept3 -> i2c@3
>
The GPIO nodes will act as providers.
Mapping the port index into the service name is a possible solution, but I don't believe it's better than
embedding that information in the message. A stateless approach feels simpler and cleaner overall.
Thanks,
Shenwei
> etc...
>
> This way device groups are isolated with each channel/namespace, and instances
> within each device groups are also respected with specific endpoints.
>
> Thanks,
> Beleswar
^ permalink raw reply
* Re: [DONOTAPPLY RFC PATCH v2 0/4] WiFi support for samsung,coreprimevelte
From: Karel Balej @ 2026-04-29 18:36 UTC (permalink / raw)
To: Brian Norris
Cc: Francesco Dolcini, Johannes Berg, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Duje Mihanović,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth, Ulf Hansson,
Frank Li, linux-wireless, devicetree, linux-kernel,
linux-arm-kernel, linux-mmc, ~postmarketos/upstreaming,
phone-devel, Jeff Chen, Peng Fan, david
In-Reply-To: <afI8y70U7wFT_07h@google.com>
Brian Norris, 2026-04-29T10:15:55-07:00:
>> and it would be great to not have to keep the
>> patches in a fork, especially when trying to build on top of them
>> further (such as to fix the driver-firmware incompatibilities discussed
>> in one of the patches of this series).
>
> Patch 3 is a different story. At the moment, it's definitely not
> acceptable. But I tried to provide hints about how you can write proper
> FW compatibility logic. I'm still not optimistic that'll be easy and
> maintainable, and we still reserve the right to reject patches if they
> make things unmaintainable.
I was referring to the original patches here, I would of course modify
the compability patch according to your feedback, I just didn't want to
invest the effort into that when it wasn't and still isn't clear if it
will ever be possible to upstream it.
I'm curious to hear from Johannes now then.
Thank you for the information,
Karel
^ permalink raw reply
* [PATCH v2 0/5] arm64: defconfig: Cleanup and change Ethernet drivers
From: Krzysztof Kozlowski @ 2026-04-29 18:50 UTC (permalink / raw)
To: linux-kernel, linux-arm-kernel, Catalin Marinas, Will Deacon,
Arnd Bergmann, Alexandre Belloni, Linus Walleij, Drew Fustini,
soc
Cc: Krzysztof Kozlowski
Changes in v2:
- Drop patch #5 "arm64: defconfig: Drop AMD XGBE Ethernet driver",
because the XGBE driver is used by enabled ARCH_SEATTLE
- Last patch (switch to modules): switch also IGB, because it can be a
module, since I2C will be built-in. Switch XGBE to module (it is not
removed now).
- Add tags.
- Link to v1: https://patch.msgid.link/20260412-defconfig-v1-0-a46918286451@oss.qualcomm.com
Several first commits have no functional impact. The last one has.
Best regards,
Krzysztof
---
Krzysztof Kozlowski (5):
arm64: defconfig: Move entries to match savedefconfig
arm64: defconfig: Drop unused legacy netfilter options
arm64: defconfig: Drop default or selected drivers
arm64: defconfig: Drop unused Ethernet vendors
arm64: defconfig: Switch Ethernet drivers to modules
arch/arm64/configs/defconfig | 374 +++++++++++++++++++++++--------------------
1 file changed, 197 insertions(+), 177 deletions(-)
---
base-commit: 9974969c14031a097d6b45bcb7a06bb4aa525c40
change-id: 20260412-defconfig-b57e7f9b5394
Best regards,
--
Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
^ permalink raw reply
* [PATCH v2 1/5] arm64: defconfig: Move entries to match savedefconfig
From: Krzysztof Kozlowski @ 2026-04-29 18:50 UTC (permalink / raw)
To: linux-kernel, linux-arm-kernel, Catalin Marinas, Will Deacon,
Arnd Bergmann, Alexandre Belloni, Linus Walleij, Drew Fustini,
soc
Cc: Krzysztof Kozlowski
In-Reply-To: <20260429-defconfig-v2-0-e4ed4186028b@oss.qualcomm.com>
Only re-shuffle entries to match savedefconfig, without removing any
symbols. This helps in reviewing defconfig when comparing with
savedefconfig and looking for obsolete symbols. No impact on
include/generated/autoconf.h.
Reviewed-by: Linus Walleij <linusw@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
arch/arm64/configs/defconfig | 218 +++++++++++++++++++++----------------------
1 file changed, 109 insertions(+), 109 deletions(-)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index dd1ac01ee29b..9c03ae2c767e 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -50,7 +50,6 @@ CONFIG_ARCH_BLAIZE=y
CONFIG_ARCH_BST=y
CONFIG_ARCH_CIX=y
CONFIG_ARCH_EXYNOS=y
-CONFIG_ARCH_SPARX5=y
CONFIG_ARCH_K3=y
CONFIG_ARCH_LG1K=y
CONFIG_ARCH_HISI=y
@@ -58,6 +57,7 @@ CONFIG_ARCH_KEEMBAY=y
CONFIG_ARCH_MEDIATEK=y
CONFIG_ARCH_MESON=y
CONFIG_ARCH_MICROCHIP=y
+CONFIG_ARCH_SPARX5=y
CONFIG_ARCH_MVEBU=y
CONFIG_ARCH_NXP=y
CONFIG_ARCH_LAYERSCAPE=y
@@ -99,7 +99,6 @@ CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
CONFIG_CPUFREQ_DT=y
-CONFIG_ACPI_CPPC_CPUFREQ=m
CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=m
CONFIG_ARM_APPLE_SOC_CPUFREQ=m
CONFIG_ARM_ARMADA_37XX_CPUFREQ=y
@@ -112,6 +111,7 @@ CONFIG_ARM_RASPBERRYPI_CPUFREQ=m
CONFIG_ARM_SCMI_CPUFREQ=y
CONFIG_ARM_TEGRA186_CPUFREQ=y
CONFIG_QORIQ_CPUFREQ=y
+CONFIG_ACPI_CPPC_CPUFREQ=m
CONFIG_ACPI=y
CONFIG_ACPI_HOTPLUG_MEMORY=y
CONFIG_ACPI_HMAT=y
@@ -126,6 +126,7 @@ CONFIG_JUMP_LABEL=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_IOSCHED_BFQ=y
+CONFIG_BLK_INLINE_ENCRYPTION=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
# CONFIG_COMPAT_BRK is not set
CONFIG_MEMORY_HOTPLUG=y
@@ -182,8 +183,8 @@ CONFIG_NET_CLS_FLOWER=m
CONFIG_NET_CLS_ACT=y
CONFIG_NET_ACT_GACT=m
CONFIG_NET_ACT_MIRRED=m
-CONFIG_HSR=m
CONFIG_NET_ACT_GATE=m
+CONFIG_HSR=m
CONFIG_QRTR_SMD=m
CONFIG_QRTR_TUN=m
CONFIG_CAN=m
@@ -241,8 +242,8 @@ CONFIG_PCIE_XILINX=y
CONFIG_PCIE_XILINX_DMA_PL=y
CONFIG_PCIE_XILINX_NWL=y
CONFIG_PCIE_XILINX_CPM=y
-CONFIG_PCI_J721E_HOST=m
CONFIG_PCI_SKY1_HOST=m
+CONFIG_PCI_J721E_HOST=m
CONFIG_PCI_IMX6_HOST=y
CONFIG_PCI_LAYERSCAPE=y
CONFIG_PCI_HISI=y
@@ -265,6 +266,7 @@ CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_FW_LOADER_USER_HELPER=y
CONFIG_HISILICON_LPC=y
+CONFIG_IMX_AIPSTZ=m
CONFIG_TEGRA_ACONNECT=m
CONFIG_MHI_BUS_PCI_GENERIC=m
CONFIG_ARM_SCMI_PROTOCOL=y
@@ -277,7 +279,6 @@ CONFIG_GOOGLE_FIRMWARE=y
CONFIG_GOOGLE_CBMEM=m
CONFIG_GOOGLE_COREBOOT_TABLE=m
CONFIG_EFI_CAPSULE_LOADER=y
-CONFIG_IMX_AIPSTZ=m
CONFIG_IMX_SCU=y
CONFIG_QCOM_TZMEM_MODE_SHMBRIDGE=y
CONFIG_QCOM_QSEECOM=y
@@ -304,11 +305,12 @@ CONFIG_MTD_NAND_MARVELL=y
CONFIG_MTD_NAND_BRCMNAND=m
CONFIG_MTD_NAND_FSL_IFC=y
CONFIG_MTD_NAND_QCOM=y
-CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPI_NAND=m
+CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_UBI=m
CONFIG_MTD_HYPERBUS=m
CONFIG_HBMC_AM654=m
+CONFIG_OF_OVERLAY=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_NBD=m
CONFIG_VIRTIO_BLK=y
@@ -322,6 +324,7 @@ CONFIG_XILINX_SDFEC=m
CONFIG_EEPROM_AT24=m
CONFIG_EEPROM_AT25=m
CONFIG_UACCE=m
+CONFIG_MISC_RP1=m
# CONFIG_SCSI_PROC_FS is not set
CONFIG_BLK_DEV_SD=y
CONFIG_SCSI_SAS_ATA=y
@@ -424,8 +427,8 @@ CONFIG_REALTEK_PHY=y
CONFIG_ROCKCHIP_PHY=y
CONFIG_DP83867_PHY=y
CONFIG_DP83869_PHY=m
-CONFIG_DP83TG720_PHY=m
CONFIG_DP83TD510_PHY=y
+CONFIG_DP83TG720_PHY=m
CONFIG_VITESSE_PHY=y
CONFIG_XILINX_GMII2RGMII=m
CONFIG_CAN_FLEXCAN=m
@@ -631,8 +634,6 @@ CONFIG_SPMI=y
CONFIG_SPMI_APPLE=m
CONFIG_SPMI_MTK_PMIF=m
CONFIG_PINCTRL_APPLE_GPIO=m
-CONFIG_PINCTRL_BRCMSTB=y
-CONFIG_PINCTRL_BCM2712=y
CONFIG_PINCTRL_DA9062=m
CONFIG_PINCTRL_MAX77620=y
CONFIG_PINCTRL_RK805=m
@@ -649,9 +650,12 @@ CONFIG_PINCTRL_IMX8QM=y
CONFIG_PINCTRL_IMX8QXP=y
CONFIG_PINCTRL_IMX8DXL=y
CONFIG_PINCTRL_IMX8ULP=y
-CONFIG_PINCTRL_IMX91=y
CONFIG_PINCTRL_IMX93=y
+CONFIG_PINCTRL_BRCMSTB=y
+CONFIG_PINCTRL_BCM2712=y
+CONFIG_PINCTRL_SKY1=y
CONFIG_PINCTRL_IMX_SCMI=y
+CONFIG_PINCTRL_IMX91=y
CONFIG_PINCTRL_MSM=y
CONFIG_PINCTRL_ELIZA=y
CONFIG_PINCTRL_GLYMUR=y
@@ -685,7 +689,6 @@ CONFIG_PINCTRL_SDM660=y
CONFIG_PINCTRL_SDM670=y
CONFIG_PINCTRL_SDM845=y
CONFIG_PINCTRL_SDX75=y
-CONFIG_PINCTRL_SKY1=y
CONFIG_PINCTRL_SM4450=y
CONFIG_PINCTRL_SM6115=y
CONFIG_PINCTRL_SM6125=y
@@ -722,9 +725,9 @@ CONFIG_GPIO_PL061=y
CONFIG_GPIO_RCAR=y
CONFIG_GPIO_SYSCON=y
CONFIG_GPIO_UNIPHIER=y
+CONFIG_GPIO_VF610=y
CONFIG_GPIO_VISCONTI=y
CONFIG_GPIO_WCD934X=m
-CONFIG_GPIO_VF610=y
CONFIG_GPIO_XGENE=y
CONFIG_GPIO_XGENE_SB=y
CONFIG_GPIO_XILINX=m
@@ -732,9 +735,9 @@ CONFIG_GPIO_ZYNQ=m
CONFIG_GPIO_MAX732X=y
CONFIG_GPIO_PCA953X=y
CONFIG_GPIO_PCA953X_IRQ=y
-CONFIG_GPIO_ADP5585=m
CONFIG_GPIO_PCF857X=m
CONFIG_GPIO_TPIC2810=m
+CONFIG_GPIO_ADP5585=m
CONFIG_GPIO_BD9571MWV=m
CONFIG_GPIO_MACSMC=m
CONFIG_GPIO_MAX77620=y
@@ -773,7 +776,6 @@ CONFIG_SENSORS_AMC6821=m
CONFIG_SENSORS_INA2XX=m
CONFIG_SENSORS_INA3221=m
CONFIG_SENSORS_TMP102=m
-CONFIG_MISC_RP1=m
CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
CONFIG_CPU_THERMAL=y
CONFIG_DEVFREQ_THERMAL=y
@@ -784,11 +786,6 @@ CONFIG_K3_THERMAL=m
CONFIG_QORIQ_THERMAL=m
CONFIG_SUN8I_THERMAL=y
CONFIG_ROCKCHIP_THERMAL=m
-CONFIG_RCAR_THERMAL=y
-CONFIG_RCAR_GEN3_THERMAL=y
-CONFIG_RZG2L_THERMAL=y
-CONFIG_RZG3E_THERMAL=y
-CONFIG_RZG3S_THERMAL=m
CONFIG_ARMADA_THERMAL=y
CONFIG_MTK_THERMAL=m
CONFIG_MTK_LVTS_THERMAL=m
@@ -796,6 +793,11 @@ CONFIG_BCM2711_THERMAL=m
CONFIG_BCM2835_THERMAL=m
CONFIG_BRCMSTB_THERMAL=m
CONFIG_EXYNOS_THERMAL=y
+CONFIG_RCAR_THERMAL=y
+CONFIG_RCAR_GEN3_THERMAL=y
+CONFIG_RZG2L_THERMAL=y
+CONFIG_RZG3E_THERMAL=y
+CONFIG_RZG3S_THERMAL=m
CONFIG_TEGRA_SOCTHERM=m
CONFIG_TEGRA_BPMP_THERMAL=m
CONFIG_GENERIC_ADC_THERMAL=m
@@ -921,10 +923,10 @@ CONFIG_SDR_PLATFORM_DRIVERS=y
CONFIG_V4L_MEM2MEM_DRIVERS=y
CONFIG_VIDEO_AMPHION_VPU=m
CONFIG_VIDEO_CADENCE_CSI2RX=m
-CONFIG_VIDEO_MEDIATEK_JPEG=m
-CONFIG_VIDEO_MEDIATEK_VCODEC=m
CONFIG_VIDEO_WAVE_VPU=m
CONFIG_VIDEO_E5010_JPEG_ENC=m
+CONFIG_VIDEO_MEDIATEK_JPEG=m
+CONFIG_VIDEO_MEDIATEK_VCODEC=m
CONFIG_VIDEO_MEDIATEK_MDP3=m
CONFIG_VIDEO_IMX7_CSI=m
CONFIG_VIDEO_IMX_MIPI_CSIS=m
@@ -934,8 +936,8 @@ CONFIG_VIDEO_IMX8_JPEG=m
CONFIG_VIDEO_QCOM_CAMSS=m
CONFIG_VIDEO_QCOM_IRIS=m
CONFIG_VIDEO_QCOM_VENUS=m
-CONFIG_VIDEO_RCAR_ISP=m
CONFIG_VIDEO_RCAR_CSI2=m
+CONFIG_VIDEO_RCAR_ISP=m
CONFIG_VIDEO_RCAR_VIN=m
CONFIG_VIDEO_RZG2L_CSI2=m
CONFIG_VIDEO_RZG2L_CRU=m
@@ -943,8 +945,8 @@ CONFIG_VIDEO_RENESAS_FCP=m
CONFIG_VIDEO_RENESAS_FDP1=m
CONFIG_VIDEO_RENESAS_VSP1=m
CONFIG_VIDEO_RCAR_DRIF=m
-CONFIG_VIDEO_ROCKCHIP_CIF=m
CONFIG_VIDEO_ROCKCHIP_RGA=m
+CONFIG_VIDEO_ROCKCHIP_CIF=m
CONFIG_VIDEO_SAMSUNG_EXYNOS_GSC=m
CONFIG_VIDEO_SAMSUNG_S5P_JPEG=m
CONFIG_VIDEO_SAMSUNG_S5P_MFC=m
@@ -959,64 +961,17 @@ CONFIG_VIDEO_OV5640=m
CONFIG_VIDEO_OV5645=m
CONFIG_VIDEO_S5KJN1=m
CONFIG_DRM=m
-CONFIG_DRM_I2C_NXP_TDA998X=m
CONFIG_DRM_HDLCD=m
CONFIG_DRM_MALI_DISPLAY=m
CONFIG_DRM_KOMEDA=m
-CONFIG_DRM_NOUVEAU=m
-CONFIG_DRM_EXYNOS=m
-CONFIG_DRM_EXYNOS5433_DECON=y
-CONFIG_DRM_EXYNOS7_DECON=y
-CONFIG_DRM_EXYNOS_DSI=y
-# CONFIG_DRM_EXYNOS_DP is not set
-CONFIG_DRM_EXYNOS_HDMI=y
-CONFIG_DRM_EXYNOS_MIC=y
-CONFIG_DRM_ROCKCHIP=m
-CONFIG_ROCKCHIP_VOP2=y
-CONFIG_ROCKCHIP_ANALOGIX_DP=y
-CONFIG_ROCKCHIP_CDN_DP=y
-CONFIG_ROCKCHIP_DW_DP=y
-CONFIG_ROCKCHIP_DW_HDMI=y
-CONFIG_ROCKCHIP_DW_HDMI_QP=y
-CONFIG_ROCKCHIP_DW_MIPI_DSI=y
-CONFIG_ROCKCHIP_INNO_HDMI=y
-CONFIG_ROCKCHIP_LVDS=y
-CONFIG_DRM_RCAR_DU=m
-CONFIG_DRM_RCAR_DW_HDMI=m
CONFIG_DRM_RCAR_MIPI_DSI=m
CONFIG_DRM_RZG2L_MIPI_DSI=m
-CONFIG_DRM_RZG2L_DU=m
-CONFIG_DRM_SUN4I=m
CONFIG_DRM_SUN6I_DSI=m
CONFIG_DRM_SUN8I_DW_HDMI=m
CONFIG_DRM_SUN8I_MIXER=m
-CONFIG_DRM_MSM=m
-CONFIG_DRM_TEGRA=m
-CONFIG_DRM_STM=m
-CONFIG_DRM_STM_LVDS=m
-CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m
-CONFIG_DRM_PANEL_LVDS=m
-CONFIG_DRM_PANEL_SIMPLE=m
-CONFIG_DRM_PANEL_SUMMIT=m
-CONFIG_DRM_PANEL_EDP=m
-CONFIG_DRM_PANEL_HIMAX_HX8279=m
-CONFIG_DRM_PANEL_HIMAX_HX83112A=m
-CONFIG_DRM_PANEL_HIMAX_HX83112B=m
-CONFIG_DRM_PANEL_ILITEK_ILI9882T=m
-CONFIG_DRM_PANEL_KHADAS_TS050=m
-CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m
-CONFIG_DRM_PANEL_NOVATEK_NT36672A=m
-CONFIG_DRM_PANEL_NOVATEK_NT36672E=m
-CONFIG_DRM_PANEL_NOVATEK_NT37801=m
-CONFIG_DRM_PANEL_RAYDIUM_RM67191=m
-CONFIG_DRM_PANEL_RAYDIUM_RM692E5=m
-CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m
-CONFIG_DRM_PANEL_SITRONIX_ST7703=m
-CONFIG_DRM_PANEL_STARTEK_KD070FHFID015=m
-CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
-CONFIG_DRM_PANEL_VISIONOX_VTDR6130=m
CONFIG_DRM_DISPLAY_CONNECTOR=m
CONFIG_DRM_FSL_LDB=m
+CONFIG_DRM_I2C_NXP_TDA998X=m
CONFIG_DRM_ITE_IT6263=m
CONFIG_DRM_LONTIUM_LT8912B=m
CONFIG_DRM_LONTIUM_LT9611=m
@@ -1043,27 +998,74 @@ CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE=m
CONFIG_DRM_DW_HDMI_AHB_AUDIO=m
CONFIG_DRM_DW_HDMI_CEC=m
CONFIG_DRM_DW_HDMI_QP_CEC=y
-CONFIG_DRM_IMX_DCSS=m
-CONFIG_DRM_V3D=m
-CONFIG_DRM_VC4=m
CONFIG_DRM_ETNAVIV=m
+CONFIG_DRM_EXYNOS=m
+CONFIG_DRM_EXYNOS5433_DECON=y
+CONFIG_DRM_EXYNOS7_DECON=y
+CONFIG_DRM_EXYNOS_DSI=y
+# CONFIG_DRM_EXYNOS_DP is not set
+CONFIG_DRM_EXYNOS_HDMI=y
+CONFIG_DRM_EXYNOS_MIC=y
CONFIG_DRM_HISI_HIBMC=m
CONFIG_DRM_HISI_KIRIN=m
+CONFIG_DRM_POWERVR=m
+CONFIG_DRM_IMX_DCSS=m
+CONFIG_DRM_LIMA=m
CONFIG_DRM_MEDIATEK=m
CONFIG_DRM_MEDIATEK_DP=m
CONFIG_DRM_MEDIATEK_HDMI=m
CONFIG_DRM_MEDIATEK_HDMI_V2=m
+CONFIG_DRM_MESON=m
+CONFIG_DRM_MSM=m
CONFIG_DRM_MXSFB=m
CONFIG_DRM_IMX_LCDIF=m
-CONFIG_DRM_MESON=m
-CONFIG_DRM_PL111=m
-CONFIG_DRM_LIMA=m
+CONFIG_DRM_NOUVEAU=m
+CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m
+CONFIG_DRM_PANEL_LVDS=m
+CONFIG_DRM_PANEL_HIMAX_HX8279=m
+CONFIG_DRM_PANEL_HIMAX_HX83112A=m
+CONFIG_DRM_PANEL_HIMAX_HX83112B=m
+CONFIG_DRM_PANEL_ILITEK_ILI9882T=m
+CONFIG_DRM_PANEL_KHADAS_TS050=m
+CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m
+CONFIG_DRM_PANEL_NOVATEK_NT36672A=m
+CONFIG_DRM_PANEL_NOVATEK_NT36672E=m
+CONFIG_DRM_PANEL_NOVATEK_NT37801=m
+CONFIG_DRM_PANEL_RAYDIUM_RM67191=m
+CONFIG_DRM_PANEL_RAYDIUM_RM692E5=m
+CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m
+CONFIG_DRM_PANEL_SITRONIX_ST7703=m
+CONFIG_DRM_PANEL_STARTEK_KD070FHFID015=m
+CONFIG_DRM_PANEL_EDP=m
+CONFIG_DRM_PANEL_SIMPLE=m
+CONFIG_DRM_PANEL_SUMMIT=m
+CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
+CONFIG_DRM_PANEL_VISIONOX_VTDR6130=m
CONFIG_DRM_PANFROST=m
CONFIG_DRM_PANTHOR=m
+CONFIG_DRM_PL111=m
+CONFIG_DRM_RCAR_DU=m
+CONFIG_DRM_RCAR_DW_HDMI=m
+CONFIG_DRM_RZG2L_DU=m
+CONFIG_DRM_ROCKCHIP=m
+CONFIG_ROCKCHIP_VOP2=y
+CONFIG_ROCKCHIP_ANALOGIX_DP=y
+CONFIG_ROCKCHIP_CDN_DP=y
+CONFIG_ROCKCHIP_DW_DP=y
+CONFIG_ROCKCHIP_DW_HDMI=y
+CONFIG_ROCKCHIP_DW_HDMI_QP=y
+CONFIG_ROCKCHIP_DW_MIPI_DSI=y
+CONFIG_ROCKCHIP_INNO_HDMI=y
+CONFIG_ROCKCHIP_LVDS=y
+CONFIG_DRM_STM=m
+CONFIG_DRM_STM_LVDS=m
+CONFIG_DRM_SUN4I=m
+CONFIG_DRM_TEGRA=m
CONFIG_DRM_TIDSS=m
+CONFIG_DRM_V3D=m
+CONFIG_DRM_VC4=m
CONFIG_DRM_ZYNQMP_DPSUB=m
CONFIG_DRM_ZYNQMP_DPSUB_AUDIO=y
-CONFIG_DRM_POWERVR=m
CONFIG_FB=y
CONFIG_FB_EFI=y
CONFIG_FB_MODE_HELPERS=y
@@ -1117,20 +1119,15 @@ CONFIG_SND_SOC_SC7180=m
CONFIG_SND_SOC_SC7280=m
CONFIG_SND_SOC_X1E80100=m
CONFIG_SND_SOC_ROCKCHIP=m
+CONFIG_SND_SOC_RCAR=m
+CONFIG_SND_SOC_MSIOF=m
+CONFIG_SND_SOC_RZ=m
CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=m
CONFIG_SND_SOC_ROCKCHIP_SAI=m
CONFIG_SND_SOC_ROCKCHIP_SPDIF=m
CONFIG_SND_SOC_ROCKCHIP_RT5645=m
CONFIG_SND_SOC_RK3399_GRU_SOUND=m
-CONFIG_SND_SOC_RCAR=m
-CONFIG_SND_SOC_MSIOF=m
-CONFIG_SND_SOC_RZ=m
CONFIG_SND_SOC_SAMSUNG=m
-CONFIG_SND_SOC_SOF_TOPLEVEL=y
-CONFIG_SND_SOC_SOF_OF=m
-CONFIG_SND_SOC_SOF_MTK_TOPLEVEL=y
-CONFIG_SND_SOC_SOF_MT8186=m
-CONFIG_SND_SOC_SOF_MT8195=m
CONFIG_SND_SUN8I_CODEC=m
CONFIG_SND_SUN8I_CODEC_ANALOG=m
CONFIG_SND_SUN50I_CODEC_ANALOG=m
@@ -1155,6 +1152,11 @@ CONFIG_SND_SOC_J721E_EVM=m
CONFIG_SND_SOC_XILINX_I2S=m
CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER=m
CONFIG_SND_SOC_XILINX_SPDIF=m
+CONFIG_SND_SOC_SOF_TOPLEVEL=y
+CONFIG_SND_SOC_SOF_OF=m
+CONFIG_SND_SOC_SOF_MTK_TOPLEVEL=y
+CONFIG_SND_SOC_SOF_MT8186=m
+CONFIG_SND_SOC_SOF_MT8195=m
CONFIG_SND_SOC_AK4613=m
CONFIG_SND_SOC_AK4619=m
CONFIG_SND_SOC_DA7213=m
@@ -1228,7 +1230,6 @@ CONFIG_USB_MTU3=y
CONFIG_USB_MUSB_HDRC=y
CONFIG_USB_MUSB_SUNXI=y
CONFIG_USB_DWC3=y
-CONFIG_OMAP_USB2=m
CONFIG_USB_DWC2=y
CONFIG_USB_CHIPIDEA=y
CONFIG_USB_CHIPIDEA_UDC=y
@@ -1314,6 +1315,7 @@ CONFIG_MMC_SDHCI_AM654=y
CONFIG_MMC_OWL=y
CONFIG_SCSI_UFSHCD=y
CONFIG_SCSI_UFS_BSG=y
+CONFIG_SCSI_UFS_CRYPTO=y
CONFIG_SCSI_UFSHCD_PLATFORM=y
CONFIG_SCSI_UFS_CDNS_PLATFORM=m
CONFIG_SCSI_UFS_QCOM=m
@@ -1323,8 +1325,6 @@ CONFIG_SCSI_UFS_RENESAS=m
CONFIG_SCSI_UFS_TI_J721E=m
CONFIG_SCSI_UFS_EXYNOS=y
CONFIG_SCSI_UFS_ROCKCHIP=y
-CONFIG_BLK_INLINE_ENCRYPTION=y
-CONFIG_SCSI_UFS_CRYPTO=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_CLASS_FLASH=m
@@ -1351,9 +1351,9 @@ CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_DS1307=m
CONFIG_RTC_DRV_HYM8563=m
CONFIG_RTC_DRV_MAX77686=y
+CONFIG_RTC_DRV_NVIDIA_VRS10=m
CONFIG_RTC_DRV_RK808=m
CONFIG_RTC_DRV_ISL1208=m
-CONFIG_RTC_DRV_PCF85063=m
CONFIG_RTC_DRV_PCF85363=m
CONFIG_RTC_DRV_PCF8563=m
CONFIG_RTC_DRV_M41T80=m
@@ -1361,10 +1361,10 @@ CONFIG_RTC_DRV_BQ32K=m
CONFIG_RTC_DRV_RX8581=m
CONFIG_RTC_DRV_RV3028=m
CONFIG_RTC_DRV_RV8803=m
-CONFIG_RTC_DRV_S32G=m
CONFIG_RTC_DRV_S5M=y
CONFIG_RTC_DRV_DS3232=y
CONFIG_RTC_DRV_PCF2127=m
+CONFIG_RTC_DRV_PCF85063=m
CONFIG_RTC_DRV_DA9063=m
CONFIG_RTC_DRV_EFI=y
CONFIG_RTC_DRV_ZYNQMP=m
@@ -1383,8 +1383,8 @@ CONFIG_RTC_DRV_MT6397=m
CONFIG_RTC_DRV_XGENE=y
CONFIG_RTC_DRV_TI_K3=m
CONFIG_RTC_DRV_RENESAS_RTCA3=m
-CONFIG_RTC_DRV_NVIDIA_VRS10=m
CONFIG_RTC_DRV_MACSMC=m
+CONFIG_RTC_DRV_S32G=m
CONFIG_DMADEVICES=y
CONFIG_APPLE_ADMAC=m
CONFIG_DMA_BCM2835=y
@@ -1435,11 +1435,11 @@ CONFIG_CROS_EC_RPMSG=m
CONFIG_CROS_EC_SPI=y
CONFIG_CROS_KBD_LED_BACKLIGHT=m
CONFIG_CROS_EC_CHARDEV=m
-CONFIG_COMMON_CLK_APPLE_NCO=m
CONFIG_EC_ACER_ASPIRE1=m
CONFIG_EC_HUAWEI_GAOKUN=m
CONFIG_EC_LENOVO_YOGA_C630=m
CONFIG_EC_LENOVO_THINKPAD_T14S=m
+CONFIG_COMMON_CLK_APPLE_NCO=m
CONFIG_COMMON_CLK_RK808=y
CONFIG_COMMON_CLK_SCMI=y
CONFIG_COMMON_CLK_SCPI=y
@@ -1524,17 +1524,16 @@ CONFIG_QCM_DISPCC_2290=m
CONFIG_QCS_DISPCC_615=m
CONFIG_QCS_CAMCC_615=m
CONFIG_QCS_GCC_404=y
-CONFIG_QCS_GCC_615=y
-CONFIG_QCS_GCC_8300=y
-CONFIG_SC_CAMCC_7280=m
CONFIG_SA_CAMCC_8775P=m
+CONFIG_QCS_GCC_8300=y
+CONFIG_QCS_GCC_615=y
CONFIG_QCS_GPUCC_615=m
CONFIG_QCS_VIDEOCC_615=m
-CONFIG_QDU_GCC_1000=y
+CONFIG_SC_CAMCC_7280=m
CONFIG_SC_CAMCC_8280XP=m
+CONFIG_SA_DISPCC_8775P=m
CONFIG_SC_DISPCC_7280=m
CONFIG_SC_DISPCC_8280XP=m
-CONFIG_SA_DISPCC_8775P=m
CONFIG_SA_GCC_8775P=y
CONFIG_SA_GPUCC_8775P=m
CONFIG_SC_GCC_7180=y
@@ -1547,6 +1546,7 @@ CONFIG_SC_LPASSCC_8280XP=m
CONFIG_SC_LPASS_CORECC_7280=m
CONFIG_SC_VIDEOCC_7280=m
CONFIG_SDM_CAMCC_845=m
+CONFIG_QDU_GCC_1000=y
CONFIG_SDM_GPUCC_845=y
CONFIG_SDM_VIDEOCC_845=y
CONFIG_SDM_DISPCC_845=y
@@ -1611,22 +1611,22 @@ CONFIG_RENESAS_OSTM=y
CONFIG_ARM_MHU=y
CONFIG_EXYNOS_MBOX=m
CONFIG_IMX_MBOX=y
-CONFIG_OMAP2PLUS_MBOX=m
CONFIG_PLATFORM_MHU=y
+CONFIG_OMAP2PLUS_MBOX=m
CONFIG_BCM2835_MBOX=y
CONFIG_QCOM_APCS_IPC=y
+CONFIG_TEGRA_HSP_MBOX=y
CONFIG_MTK_ADSP_MBOX=m
CONFIG_QCOM_CPUCP_MBOX=m
-CONFIG_TEGRA_HSP_MBOX=y
CONFIG_QCOM_IPCC=y
CONFIG_CIX_MBOX=y
-CONFIG_ROCKCHIP_IOMMU=y
-CONFIG_TEGRA_IOMMU_SMMU=y
CONFIG_ARM_SMMU=y
CONFIG_ARM_SMMU_V3=y
-CONFIG_MTK_IOMMU=y
CONFIG_QCOM_IOMMU=y
+CONFIG_ROCKCHIP_IOMMU=y
+CONFIG_TEGRA_IOMMU_SMMU=y
CONFIG_APPLE_DART=m
+CONFIG_MTK_IOMMU=y
CONFIG_REMOTEPROC=y
CONFIG_IMX_REMOTEPROC=y
CONFIG_MTK_SCP=m
@@ -1730,9 +1730,9 @@ CONFIG_PWM_BCM2835=m
CONFIG_PWM_BRCMSTB=m
CONFIG_PWM_CROS_EC=m
CONFIG_PWM_IMX27=m
+CONFIG_PWM_MEDIATEK=m
CONFIG_PWM_MESON=m
CONFIG_PWM_MTK_DISP=m
-CONFIG_PWM_MEDIATEK=m
CONFIG_PWM_RENESAS_RCAR=m
CONFIG_PWM_RENESAS_RZG2L_GPT=m
CONFIG_PWM_RENESAS_RZ_MTU3=m
@@ -1760,10 +1760,10 @@ CONFIG_RESET_QCOM_PDC=m
CONFIG_RESET_RZG2L_USBPHY_CTRL=y
CONFIG_RESET_RZV2H_USB2PHY=m
CONFIG_RESET_TI_SCI=y
-CONFIG_PHY_SNPS_EUSB2=m
-CONFIG_PHY_XGENE=y
CONFIG_PHY_CAN_TRANSCEIVER=m
CONFIG_PHY_NXP_PTN3222=m
+CONFIG_PHY_SNPS_EUSB2=m
+CONFIG_PHY_XGENE=y
CONFIG_PHY_SUN4I_USB=y
CONFIG_PHY_CADENCE_TORRENT=m
CONFIG_PHY_CADENCE_DPHY=m
@@ -1814,6 +1814,7 @@ CONFIG_PHY_UNIPHIER_USB3=y
CONFIG_PHY_TEGRA_XUSB=y
CONFIG_PHY_AM654_SERDES=m
CONFIG_PHY_J721E_WIZ=m
+CONFIG_OMAP_USB2=m
CONFIG_PHY_XILINX_ZYNQMP=m
CONFIG_ARM_CCI_PMU=m
CONFIG_ARM_CCN=m
@@ -1857,7 +1858,6 @@ CONFIG_ALTERA_FREEZE_BRIDGE=m
CONFIG_XILINX_PR_DECOUPLER=m
CONFIG_FPGA_REGION=m
CONFIG_OF_FPGA_REGION=m
-CONFIG_OF_OVERLAY=y
CONFIG_FPGA_MGR_ZYNQMP_FPGA=m
CONFIG_FPGA_MGR_VERSAL_FPGA=m
CONFIG_TEE=y
@@ -1906,9 +1906,9 @@ CONFIG_INTERCONNECT_QCOM_SM8650=y
CONFIG_INTERCONNECT_QCOM_SM8750=y
CONFIG_INTERCONNECT_QCOM_X1E80100=y
CONFIG_COUNTER=m
-CONFIG_TI_EQEP=m
CONFIG_RZ_MTU3_CNT=m
CONFIG_STM32_TIMER_CNT=m
+CONFIG_TI_EQEP=m
CONFIG_HTE=y
CONFIG_HTE_TEGRA194=y
CONFIG_HTE_TEGRA194_TEST=m
@@ -1942,8 +1942,8 @@ CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_SECURITY=y
CONFIG_CRYPTO_USER=y
-CONFIG_CRYPTO_CHACHA20=m
CONFIG_CRYPTO_BENCHMARK=m
+CONFIG_CRYPTO_CHACHA20=m
CONFIG_CRYPTO_ECHAINIV=y
CONFIG_CRYPTO_SHA3=m
CONFIG_CRYPTO_SM3=m
--
2.51.0
^ permalink raw reply related
* [PATCH v2 2/5] arm64: defconfig: Drop unused legacy netfilter options
From: Krzysztof Kozlowski @ 2026-04-29 18:50 UTC (permalink / raw)
To: linux-kernel, linux-arm-kernel, Catalin Marinas, Will Deacon,
Arnd Bergmann, Alexandre Belloni, Linus Walleij, Drew Fustini,
soc
Cc: Krzysztof Kozlowski
In-Reply-To: <20260429-defconfig-v2-0-e4ed4186028b@oss.qualcomm.com>
Drop all options which are ineffective now, because they depend on
disabled IP_NF_IPTABLES_LEGACY or IP6_NF_IPTABLES_LEGACY. No impact on
include/generated/autoconf.h.
Reviewed-by: Linus Walleij <linusw@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
arch/arm64/configs/defconfig | 10 ----------
1 file changed, 10 deletions(-)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 9c03ae2c767e..9a31b258a56e 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -155,17 +155,7 @@ CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
CONFIG_NETFILTER_XT_MATCH_IPVS=m
CONFIG_IP_VS=m
CONFIG_IP_NF_IPTABLES=m
-CONFIG_IP_NF_FILTER=m
-CONFIG_IP_NF_TARGET_REJECT=m
-CONFIG_IP_NF_NAT=m
-CONFIG_IP_NF_TARGET_MASQUERADE=m
-CONFIG_IP_NF_MANGLE=m
CONFIG_IP6_NF_IPTABLES=m
-CONFIG_IP6_NF_FILTER=m
-CONFIG_IP6_NF_TARGET_REJECT=m
-CONFIG_IP6_NF_MANGLE=m
-CONFIG_IP6_NF_NAT=m
-CONFIG_IP6_NF_TARGET_MASQUERADE=m
CONFIG_BRIDGE=m
CONFIG_BRIDGE_VLAN_FILTERING=y
CONFIG_NET_DSA=m
--
2.51.0
^ permalink raw reply related
* [PATCH v2 3/5] arm64: defconfig: Drop default or selected drivers
From: Krzysztof Kozlowski @ 2026-04-29 18:50 UTC (permalink / raw)
To: linux-kernel, linux-arm-kernel, Catalin Marinas, Will Deacon,
Arnd Bergmann, Alexandre Belloni, Linus Walleij, Drew Fustini,
soc
Cc: Krzysztof Kozlowski
In-Reply-To: <20260429-defconfig-v2-0-e4ed4186028b@oss.qualcomm.com>
Drop all options which are either defaults or selected by other drivers:
1. IMX Pinctrl drivers are defaults for this ARCH.
2. RP1 is selected by MISC_RP1.
3. I2C_DESIGNWARE_PLATFORM is default with I2C_DESIGNWARE_CORE.
4. DRM_SAMSUNG_DSIM is selected by DRM_EXYNOS_DSI.
5. SUN6I, SUN8I and Renesas DRM drivers have defaults.
6. SND_SOC_ROCKCHIP does not exist.
7. Several ASoC drivers are selected by other main sound switches.
8. USB_CDNS3_IMX is default with USB_CDNS3.
9. IPQ_APSS_5018 never existed.
No impact on include/generated/autoconf.h.
Reviewed-by: Linus Walleij <linusw@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
arch/arm64/configs/defconfig | 23 -----------------------
1 file changed, 23 deletions(-)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 9a31b258a56e..c9f6d5d6ef69 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -557,7 +557,6 @@ CONFIG_I2C_MUX_PINCTRL=m
CONFIG_I2C_BCM2835=m
CONFIG_I2C_CADENCE=m
CONFIG_I2C_DESIGNWARE_CORE=y
-CONFIG_I2C_DESIGNWARE_PLATFORM=y
CONFIG_I2C_GPIO=m
CONFIG_I2C_IMX=y
CONFIG_I2C_IMX_LPI2C=y
@@ -632,15 +631,6 @@ CONFIG_PINCTRL_SX150X=m
CONFIG_PINCTRL_OWL=y
CONFIG_PINCTRL_S700=y
CONFIG_PINCTRL_S900=y
-CONFIG_PINCTRL_IMX8MM=y
-CONFIG_PINCTRL_IMX8MN=y
-CONFIG_PINCTRL_IMX8MP=y
-CONFIG_PINCTRL_IMX8MQ=y
-CONFIG_PINCTRL_IMX8QM=y
-CONFIG_PINCTRL_IMX8QXP=y
-CONFIG_PINCTRL_IMX8DXL=y
-CONFIG_PINCTRL_IMX8ULP=y
-CONFIG_PINCTRL_IMX93=y
CONFIG_PINCTRL_BRCMSTB=y
CONFIG_PINCTRL_BCM2712=y
CONFIG_PINCTRL_SKY1=y
@@ -669,7 +659,6 @@ CONFIG_PINCTRL_QCS615=y
CONFIG_PINCTRL_QCS8300=y
CONFIG_PINCTRL_QDF2XXX=y
CONFIG_PINCTRL_QDU1000=y
-CONFIG_PINCTRL_RP1=m
CONFIG_PINCTRL_SA8775P=y
CONFIG_PINCTRL_SC7180=y
CONFIG_PINCTRL_SC7280=y
@@ -954,11 +943,6 @@ CONFIG_DRM=m
CONFIG_DRM_HDLCD=m
CONFIG_DRM_MALI_DISPLAY=m
CONFIG_DRM_KOMEDA=m
-CONFIG_DRM_RCAR_MIPI_DSI=m
-CONFIG_DRM_RZG2L_MIPI_DSI=m
-CONFIG_DRM_SUN6I_DSI=m
-CONFIG_DRM_SUN8I_DW_HDMI=m
-CONFIG_DRM_SUN8I_MIXER=m
CONFIG_DRM_DISPLAY_CONNECTOR=m
CONFIG_DRM_FSL_LDB=m
CONFIG_DRM_I2C_NXP_TDA998X=m
@@ -970,7 +954,6 @@ CONFIG_DRM_LONTIUM_LT8713SX=m
CONFIG_DRM_ITE_IT66121=m
CONFIG_DRM_NWL_MIPI_DSI=m
CONFIG_DRM_PARADE_PS8640=m
-CONFIG_DRM_SAMSUNG_DSIM=m
CONFIG_DRM_SII902X=m
CONFIG_DRM_SIMPLE_BRIDGE=m
CONFIG_DRM_THINE_THC63LVD1024=m
@@ -1108,7 +1091,6 @@ CONFIG_SND_SOC_SC8280XP=m
CONFIG_SND_SOC_SC7180=m
CONFIG_SND_SOC_SC7280=m
CONFIG_SND_SOC_X1E80100=m
-CONFIG_SND_SOC_ROCKCHIP=m
CONFIG_SND_SOC_RCAR=m
CONFIG_SND_SOC_MSIOF=m
CONFIG_SND_SOC_RZ=m
@@ -1137,7 +1119,6 @@ CONFIG_SND_SOC_TEGRA210_AMX=m
CONFIG_SND_SOC_TEGRA210_ADX=m
CONFIG_SND_SOC_TEGRA210_MIXER=m
CONFIG_SND_SOC_TEGRA_AUDIO_GRAPH_CARD=m
-CONFIG_SND_SOC_DAVINCI_MCASP=m
CONFIG_SND_SOC_J721E_EVM=m
CONFIG_SND_SOC_XILINX_I2S=m
CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER=m
@@ -1158,7 +1139,6 @@ CONFIG_SND_SOC_GTM601=m
CONFIG_SND_SOC_MAX98090=m
CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m
CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m
-CONFIG_SND_SOC_PCM3168A_I2C=m
CONFIG_SND_SOC_RK3308=m
CONFIG_SND_SOC_RK817=m
CONFIG_SND_SOC_RT5640=m
@@ -1215,7 +1195,6 @@ CONFIG_USB_CDNS_SUPPORT=m
CONFIG_USB_CDNS3=m
CONFIG_USB_CDNS3_GADGET=y
CONFIG_USB_CDNS3_HOST=y
-CONFIG_USB_CDNS3_IMX=m
CONFIG_USB_MTU3=y
CONFIG_USB_MUSB_HDRC=y
CONFIG_USB_MUSB_SUNXI=y
@@ -1437,7 +1416,6 @@ CONFIG_COMMON_CLK_CS2000_CP=y
CONFIG_COMMON_CLK_FSL_SAI=y
CONFIG_COMMON_CLK_S2MPS11=y
CONFIG_COMMON_CLK_PWM=y
-CONFIG_COMMON_CLK_RP1=m
CONFIG_COMMON_CLK_RS9_PCIE=y
CONFIG_COMMON_CLK_VC3=y
CONFIG_COMMON_CLK_VC5=y
@@ -1490,7 +1468,6 @@ CONFIG_QCOM_CLK_APCC_MSM8996=y
CONFIG_QCOM_CLK_SMD_RPM=y
CONFIG_QCOM_CLK_RPMH=y
CONFIG_IPQ_APSS_6018=y
-CONFIG_IPQ_APSS_5018=y
CONFIG_IPQ_CMN_PLL=m
CONFIG_IPQ_GCC_5018=y
CONFIG_IPQ_GCC_5210=y
--
2.51.0
^ permalink raw reply related
* [PATCH v2 4/5] arm64: defconfig: Drop unused Ethernet vendors
From: Krzysztof Kozlowski @ 2026-04-29 18:50 UTC (permalink / raw)
To: linux-kernel, linux-arm-kernel, Catalin Marinas, Will Deacon,
Arnd Bergmann, Alexandre Belloni, Linus Walleij, Drew Fustini,
soc
Cc: Krzysztof Kozlowski
In-Reply-To: <20260429-defconfig-v2-0-e4ed4186028b@oss.qualcomm.com>
Make going through `make menuconfig` easier by disabling the unused
Ethernet vendor menu options, where no actual driver for given vendor is
selected.
Impact checked with comparing old and new autoconf.h:
diff ... | grep '^-' | grep -v CONFIG_NET_VENDOR
Reviewed-by: Linus Walleij <linusw@kernel.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
arch/arm64/configs/defconfig | 51 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 51 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index c9f6d5d6ef69..79f6294fffdf 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -349,15 +349,33 @@ CONFIG_VIRTIO_NET=y
CONFIG_MHI_NET=m
CONFIG_NET_DSA_BCM_SF2=m
CONFIG_NET_DSA_MSCC_FELIX=m
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_ACTIONS is not set
+# CONFIG_NET_VENDOR_ADAPTEC is not set
+# CONFIG_NET_VENDOR_AGERE is not set
+# CONFIG_NET_VENDOR_ALACRITECH is not set
+# CONFIG_NET_VENDOR_ALLWINNER is not set
CONFIG_ENA_ETHERNET=m
CONFIG_AMD_XGBE=y
CONFIG_NET_XGENE=y
+# CONFIG_NET_VENDOR_AQUANTIA is not set
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_VENDOR_ASIX is not set
CONFIG_ATL1C=m
CONFIG_BCMGENET=m
CONFIG_BNX2X=m
CONFIG_SYSTEMPORT=m
CONFIG_MACB=y
CONFIG_THUNDER_NIC_PF=y
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_CISCO is not set
+# CONFIG_NET_VENDOR_CORTINA is not set
+# CONFIG_NET_VENDOR_DAVICOM is not set
+# CONFIG_NET_VENDOR_DEC is not set
+# CONFIG_NET_VENDOR_DLINK is not set
+# CONFIG_NET_VENDOR_EMULEX is not set
+# CONFIG_NET_VENDOR_ENGLEDER is not set
+# CONFIG_NET_VENDOR_EZCHIP is not set
CONFIG_FEC=y
CONFIG_FSL_FMAN=y
CONFIG_FSL_DPAA_ETH=y
@@ -367,16 +385,21 @@ CONFIG_NXP_ENETC4=m
CONFIG_FSL_ENETC_VF=y
CONFIG_FSL_ENETC_QOS=y
CONFIG_NXP_NETC_BLK_CTRL=m
+# CONFIG_NET_VENDOR_FUNGIBLE is not set
+# CONFIG_NET_VENDOR_GOOGLE is not set
CONFIG_HIX5HD2_GMAC=y
CONFIG_HNS_DSAF=y
CONFIG_HNS_ENET=y
CONFIG_HNS3=y
CONFIG_HNS3_HCLGE=y
CONFIG_HNS3_ENET=y
+# CONFIG_NET_VENDOR_HUAWEI is not set
CONFIG_E1000=y
CONFIG_E1000E=y
CONFIG_IGB=y
CONFIG_IGBVF=y
+# CONFIG_NET_VENDOR_ADI is not set
+# CONFIG_NET_VENDOR_LITEX is not set
CONFIG_MVNETA=y
CONFIG_MVPP2=y
CONFIG_SKY2=y
@@ -385,13 +408,34 @@ CONFIG_NET_MEDIATEK_STAR_EMAC=m
CONFIG_MLX4_EN=m
CONFIG_MLX5_CORE=m
CONFIG_MLX5_CORE_EN=y
+# CONFIG_NET_VENDOR_META is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_MICROSOFT is not set
+# CONFIG_NET_VENDOR_MUCSE is not set
+# CONFIG_NET_VENDOR_MYRI is not set
+# CONFIG_NET_VENDOR_NI is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_NETRONOME is not set
+# CONFIG_NET_VENDOR_NVIDIA is not set
+# CONFIG_NET_VENDOR_OKI is not set
+# CONFIG_NET_VENDOR_PACKET_ENGINES is not set
+# CONFIG_NET_VENDOR_QLOGIC is not set
+# CONFIG_NET_VENDOR_BROCADE is not set
CONFIG_QCOM_EMAC=m
CONFIG_RMNET=m
+# CONFIG_NET_VENDOR_RDC is not set
CONFIG_R8169=m
CONFIG_SH_ETH=y
CONFIG_RAVB=y
CONFIG_RENESAS_ETHER_SWITCH=y
CONFIG_RTSN=y
+# CONFIG_NET_VENDOR_ROCKER is not set
+# CONFIG_NET_VENDOR_SAMSUNG is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SILAN is not set
+# CONFIG_NET_VENDOR_SIS is not set
+# CONFIG_NET_VENDOR_SOLARFLARE is not set
CONFIG_SMC91X=y
CONFIG_SMSC911X=y
CONFIG_SNI_AVE=y
@@ -399,8 +443,15 @@ CONFIG_SNI_NETSEC=y
CONFIG_STMMAC_ETH=m
CONFIG_DWMAC_MEDIATEK=m
CONFIG_DWMAC_TEGRA=m
+# CONFIG_NET_VENDOR_SUN is not set
+# CONFIG_NET_VENDOR_SYNOPSYS is not set
+# CONFIG_NET_VENDOR_TEHUTI is not set
CONFIG_TI_K3_AM65_CPSW_NUSS=y
CONFIG_TI_ICSSG_PRUETH=m
+# CONFIG_NET_VENDOR_VERTEXCOM is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WANGXUN is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
CONFIG_XILINX_AXI_EMAC=m
CONFIG_QCOM_IPA=m
CONFIG_MESON_GXL_PHY=m
--
2.51.0
^ permalink raw reply related
* [PATCH v2 5/5] arm64: defconfig: Switch Ethernet drivers to modules
From: Krzysztof Kozlowski @ 2026-04-29 18:50 UTC (permalink / raw)
To: linux-kernel, linux-arm-kernel, Catalin Marinas, Will Deacon,
Arnd Bergmann, Alexandre Belloni, Linus Walleij, Drew Fustini,
soc
Cc: Krzysztof Kozlowski
In-Reply-To: <20260429-defconfig-v2-0-e4ed4186028b@oss.qualcomm.com>
Development of Linux kernel progressed over last 10 years and it is easy
to generate now initramfs for building own kernel, e.g. with Yocto or
mkosi. Therefore for a few years of reviews on mailing lists, all new
options enabled in arm64 defconfig were with assumption of having
initramfs which can load bare minimum of modules to mount filesystem
from network or disk. Basically network driver as built-in is not
anymore essential to boot the system, so switch almost all Ethernet
drivers to modules to save on kernel image size.
Similarly 9P network filesystem for QEMU, especially that testing kernel
unuder QEMU does not have any size or build process constraints and can
use initramfs with -initrd argument. Note that having network drivers
does not break NFS root, because whatever loading method, e.g. TFTP,
which brought the kernel image can bring also the initramfs with network
adapters (and I have been using such method for years for my Samsung
boards).
Notable exceptions / diff explanations:
1. Mark I2C as built-in, used by CONFIG_IGB as a module.
2. CONFIG_BCM4908_ENET and CONFIG_BCMASP appear in the diff, because
they were default=y (via ARCH_BCMBCA or ARCH_BCM_IPROC).
3. CONFIG_HNS3_HCLGE and CONFIG_HNS3_ENET are removed, because they are
default=m.
Moving code to modules has positive impact on kernel image size, thus
boot time of all users not using above drivers and ability to flash
fixed-size boot partitions.
Old Image size: 41.2 MiB (Image.gz: 14.8 MiB)
New Image size: 39.1 MiB (Image.gz: 13.8 MiB)
bloat-o-meter of vmlinux:
add/remove: 3/6972 grow/shrink: 6/45 up/down: 66659/-2333659 (-2267000)
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
arch/arm64/configs/defconfig | 72 +++++++++++++++++++++++---------------------
1 file changed, 37 insertions(+), 35 deletions(-)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 79f6294fffdf..f373549a7c12 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -199,8 +199,8 @@ CONFIG_MAC80211=m
CONFIG_MAC80211_LEDS=y
CONFIG_RFKILL=m
CONFIG_RFKILL_GPIO=m
-CONFIG_NET_9P=y
-CONFIG_NET_9P_VIRTIO=y
+CONFIG_NET_9P=m
+CONFIG_NET_9P_VIRTIO=m
CONFIG_NFC=m
CONFIG_NFC_NCI=m
CONFIG_NFC_NXP_NCI=m
@@ -356,17 +356,20 @@ CONFIG_NET_DSA_MSCC_FELIX=m
# CONFIG_NET_VENDOR_ALACRITECH is not set
# CONFIG_NET_VENDOR_ALLWINNER is not set
CONFIG_ENA_ETHERNET=m
-CONFIG_AMD_XGBE=y
+CONFIG_AMD_XGBE=m
CONFIG_NET_XGENE=y
# CONFIG_NET_VENDOR_AQUANTIA is not set
# CONFIG_NET_VENDOR_ARC is not set
# CONFIG_NET_VENDOR_ASIX is not set
CONFIG_ATL1C=m
+CONFIG_BCM4908_ENET=m
CONFIG_BCMGENET=m
CONFIG_BNX2X=m
+CONFIG_BGMAC_PLATFORM=m
CONFIG_SYSTEMPORT=m
-CONFIG_MACB=y
-CONFIG_THUNDER_NIC_PF=y
+CONFIG_BCMASP=m
+CONFIG_MACB=m
+CONFIG_THUNDER_NIC_PF=m
# CONFIG_NET_VENDOR_CHELSIO is not set
# CONFIG_NET_VENDOR_CISCO is not set
# CONFIG_NET_VENDOR_CORTINA is not set
@@ -376,33 +379,31 @@ CONFIG_THUNDER_NIC_PF=y
# CONFIG_NET_VENDOR_EMULEX is not set
# CONFIG_NET_VENDOR_ENGLEDER is not set
# CONFIG_NET_VENDOR_EZCHIP is not set
-CONFIG_FEC=y
-CONFIG_FSL_FMAN=y
-CONFIG_FSL_DPAA_ETH=y
-CONFIG_FSL_DPAA2_ETH=y
-CONFIG_FSL_ENETC=y
+CONFIG_FEC=m
+CONFIG_FSL_FMAN=m
+CONFIG_FSL_DPAA_ETH=m
+CONFIG_FSL_DPAA2_ETH=m
+CONFIG_FSL_ENETC=m
CONFIG_NXP_ENETC4=m
-CONFIG_FSL_ENETC_VF=y
+CONFIG_FSL_ENETC_VF=m
CONFIG_FSL_ENETC_QOS=y
CONFIG_NXP_NETC_BLK_CTRL=m
# CONFIG_NET_VENDOR_FUNGIBLE is not set
# CONFIG_NET_VENDOR_GOOGLE is not set
-CONFIG_HIX5HD2_GMAC=y
-CONFIG_HNS_DSAF=y
-CONFIG_HNS_ENET=y
-CONFIG_HNS3=y
-CONFIG_HNS3_HCLGE=y
-CONFIG_HNS3_ENET=y
+CONFIG_HIX5HD2_GMAC=m
+CONFIG_HNS_DSAF=m
+CONFIG_HNS_ENET=m
+CONFIG_HNS3=m
# CONFIG_NET_VENDOR_HUAWEI is not set
-CONFIG_E1000=y
-CONFIG_E1000E=y
-CONFIG_IGB=y
-CONFIG_IGBVF=y
+CONFIG_E1000=m
+CONFIG_E1000E=m
+CONFIG_IGB=m
+CONFIG_IGBVF=m
# CONFIG_NET_VENDOR_ADI is not set
# CONFIG_NET_VENDOR_LITEX is not set
-CONFIG_MVNETA=y
-CONFIG_MVPP2=y
-CONFIG_SKY2=y
+CONFIG_MVNETA=m
+CONFIG_MVPP2=m
+CONFIG_SKY2=m
CONFIG_NET_VENDOR_MEDIATEK=y
CONFIG_NET_MEDIATEK_STAR_EMAC=m
CONFIG_MLX4_EN=m
@@ -426,27 +427,27 @@ CONFIG_QCOM_EMAC=m
CONFIG_RMNET=m
# CONFIG_NET_VENDOR_RDC is not set
CONFIG_R8169=m
-CONFIG_SH_ETH=y
-CONFIG_RAVB=y
-CONFIG_RENESAS_ETHER_SWITCH=y
-CONFIG_RTSN=y
+CONFIG_SH_ETH=m
+CONFIG_RAVB=m
+CONFIG_RENESAS_ETHER_SWITCH=m
+CONFIG_RTSN=m
# CONFIG_NET_VENDOR_ROCKER is not set
# CONFIG_NET_VENDOR_SAMSUNG is not set
# CONFIG_NET_VENDOR_SEEQ is not set
# CONFIG_NET_VENDOR_SILAN is not set
# CONFIG_NET_VENDOR_SIS is not set
# CONFIG_NET_VENDOR_SOLARFLARE is not set
-CONFIG_SMC91X=y
-CONFIG_SMSC911X=y
-CONFIG_SNI_AVE=y
-CONFIG_SNI_NETSEC=y
+CONFIG_SMC91X=m
+CONFIG_SMSC911X=m
+CONFIG_SNI_AVE=m
+CONFIG_SNI_NETSEC=m
CONFIG_STMMAC_ETH=m
CONFIG_DWMAC_MEDIATEK=m
CONFIG_DWMAC_TEGRA=m
# CONFIG_NET_VENDOR_SUN is not set
# CONFIG_NET_VENDOR_SYNOPSYS is not set
# CONFIG_NET_VENDOR_TEHUTI is not set
-CONFIG_TI_K3_AM65_CPSW_NUSS=y
+CONFIG_TI_K3_AM65_CPSW_NUSS=m
CONFIG_TI_ICSSG_PRUETH=m
# CONFIG_NET_VENDOR_VERTEXCOM is not set
# CONFIG_NET_VENDOR_VIA is not set
@@ -479,7 +480,7 @@ CONFIG_CAN_M_CAN_PLATFORM=m
CONFIG_CAN_RCAR=m
CONFIG_CAN_RCAR_CANFD=m
CONFIG_CAN_MCP251XFD=m
-CONFIG_MDIO_GPIO=y
+CONFIG_MDIO_GPIO=m
CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y
CONFIG_MDIO_BUS_MUX_MMIOREG=y
CONFIG_USB_PEGASUS=m
@@ -601,6 +602,7 @@ CONFIG_TCG_TIS_SPI=m
CONFIG_TCG_TIS_SPI_CR50=y
CONFIG_TCG_TIS_I2C_CR50=m
CONFIG_TCG_TIS_I2C_INFINEON=y
+CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_MUX=y
CONFIG_I2C_MUX_PCA954x=y
@@ -1955,7 +1957,7 @@ CONFIG_NFS_V4=y
CONFIG_NFS_V4_1=y
CONFIG_NFS_V4_2=y
CONFIG_ROOT_NFS=y
-CONFIG_9P_FS=y
+CONFIG_9P_FS=m
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_SECURITY=y
--
2.51.0
^ permalink raw reply related
* Re: [PATCH v13 3/4] gpio: rpmsg: add generic rpmsg GPIO driver
From: Padhi, Beleswar @ 2026-04-29 18:57 UTC (permalink / raw)
To: Shenwei Wang, Mathieu Poirier
Cc: Andrew Lunn, Linus Walleij, Bartosz Golaszewski, Jonathan Corbet,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
Frank Li, Sascha Hauer, Shuah Khan, linux-gpio@vger.kernel.org,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
Pengutronix Kernel Team, Fabio Estevam, Peng Fan,
devicetree@vger.kernel.org, linux-remoteproc@vger.kernel.org,
imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
dl-linux-imx, Bartosz Golaszewski
In-Reply-To: <PAXPR04MB9185EB2DA65F8851CA16CE3489342@PAXPR04MB9185.eurprd04.prod.outlook.com>
On 4/30/2026 12:05 AM, Shenwei Wang wrote:
>
>> -----Original Message-----
>> From: Padhi, Beleswar <b-padhi@ti.com>
>> Sent: Wednesday, April 29, 2026 1:07 PM
>> To: Mathieu Poirier <mathieu.poirier@linaro.org>; Shenwei Wang
>> <shenwei.wang@nxp.com>
>> Cc: Andrew Lunn <andrew@lunn.ch>; Linus Walleij <linusw@kernel.org>; Bartosz
>> Golaszewski <brgl@kernel.org>; Jonathan Corbet <corbet@lwn.net>; Rob Herring
>> <robh@kernel.org>; Krzysztof Kozlowski <krzk+dt@kernel.org>; Conor Dooley
>> <conor+dt@kernel.org>; Bjorn Andersson <andersson@kernel.org>; Frank Li
>> <frank.li@nxp.com>; Sascha Hauer <s.hauer@pengutronix.de>; Shuah Khan
>> <skhan@linuxfoundation.org>; linux-gpio@vger.kernel.org; linux-
>> doc@vger.kernel.org; linux-kernel@vger.kernel.org; Pengutronix Kernel Team
>> <kernel@pengutronix.de>; Fabio Estevam <festevam@gmail.com>; Peng Fan
>> <peng.fan@nxp.com>; devicetree@vger.kernel.org; linux-
>> remoteproc@vger.kernel.org; imx@lists.linux.dev; linux-arm-
>> kernel@lists.infradead.org; dl-linux-imx <linux-imx@nxp.com>; Bartosz
>> Golaszewski <brgl@bgdev.pl>
>> Subject: [EXT] Re: [PATCH v13 3/4] gpio: rpmsg: add generic rpmsg GPIO driver
>> Hi Mathieu,
>>
>> On 4/29/2026 11:03 PM, Mathieu Poirier wrote:
>>> On Wed, 29 Apr 2026 at 10:53, Shenwei Wang <shenwei.wang@nxp.com>
>> wrote:
>>>>
>>>>> -----Original Message-----
>>>>> From: Mathieu Poirier <mathieu.poirier@linaro.org>
>>>>> Sent: Wednesday, April 29, 2026 10:42 AM
>>>>> To: Shenwei Wang <shenwei.wang@nxp.com>
>>>>> Cc: Andrew Lunn <andrew@lunn.ch>; Padhi, Beleswar <b-padhi@ti.com>;
>>>>> Linus Walleij <linusw@kernel.org>; Bartosz Golaszewski
>>>>> <brgl@kernel.org>; Jonathan Corbet <corbet@lwn.net>; Rob Herring
>>>>> <robh@kernel.org>; Krzysztof Kozlowski <krzk+dt@kernel.org>; Conor
>>>>> Dooley <conor+dt@kernel.org>; Bjorn Andersson
>>>>> <andersson@kernel.org>; Frank Li <frank.li@nxp.com>; Sascha Hauer
>>>>> <s.hauer@pengutronix.de>; Shuah Khan <skhan@linuxfoundation.org>;
>>>>> linux- gpio@vger.kernel.org; linux-doc@vger.kernel.org;
>>>>> linux-kernel@vger.kernel.org; Pengutronix Kernel Team
>>>>> <kernel@pengutronix.de>; Fabio Estevam <festevam@gmail.com>; Peng
>>>>> Fan <peng.fan@nxp.com>; devicetree@vger.kernel.org;
>>>>> linux-remoteproc@vger.kernel.org; imx@lists.linux.dev;
>>>>> linux-arm-kernel@lists.infradead.org; dl-linux-imx <linux-
>>>>> imx@nxp.com>; Bartosz Golaszewski <brgl@bgdev.pl>
>>>>> Subject: [EXT] Re: [PATCH v13 3/4] gpio: rpmsg: add generic rpmsg
>>>>> GPIO driver On Tue, Apr 28, 2026 at 03:24:59PM +0000, Shenwei Wang
>> wrote:
>>>>>>> -----Original Message-----
>>>>>>> From: Andrew Lunn <andrew@lunn.ch>
>>>>>>> Sent: Monday, April 27, 2026 3:49 PM
>>>>>>> To: Shenwei Wang <shenwei.wang@nxp.com>
>>>>>>> Cc: Padhi, Beleswar <b-padhi@ti.com>; Linus Walleij
>>>>>>> <linusw@kernel.org>; Bartosz Golaszewski <brgl@kernel.org>;
>>>>>>> Jonathan Corbet <corbet@lwn.net>; Rob Herring <robh@kernel.org>;
>>>>>>> Krzysztof Kozlowski <krzk+dt@kernel.org>; Conor Dooley
>>>>>>> <conor+dt@kernel.org>; Bjorn Andersson <andersson@kernel.org>;
>>>>>>> Mathieu Poirier <mathieu.poirier@linaro.org>; Frank Li
>>>>>>> <frank.li@nxp.com>; Sascha Hauer <s.hauer@pengutronix.de>; Shuah
>>>>>>> Khan <skhan@linuxfoundation.org>; linux-gpio@vger.kernel.org;
>>>>>>> linux- doc@vger.kernel.org; linux-kernel@vger.kernel.org;
>>>>>>> Pengutronix Kernel Team <kernel@pengutronix.de>; Fabio Estevam
>>>>>>> <festevam@gmail.com>; Peng Fan <peng.fan@nxp.com>;
>>>>>>> devicetree@vger.kernel.org; linux- remoteproc@vger.kernel.org;
>>>>>>> imx@lists.linux.dev; linux-arm- kernel@lists.infradead.org;
>>>>>>> dl-linux-imx <linux-imx@nxp.com>; Bartosz Golaszewski
>>>>>>> <brgl@bgdev.pl>
>>>>>>> Subject: [EXT] Re: [PATCH v13 3/4] gpio: rpmsg: add generic rpmsg
>>>>>>> GPIO driver
>>>>>>>>> struct virtio_gpio_response {
>>>>>>>>> __u8 status;
>>>>>>>>> __u8 value;
>>>>>>>>> };
>>>>>>>> It is the same message format. Please see the message definition
>>>>>>> (GET_DIRECTION) below:
>>>>>>>
>>>>>>>> + +-----+-----+-----+-----+-----+----+
>>>>>>>> + |0x00 |0x01 |0x02 |0x03 |0x04 |0x05|
>>>>>>>> + | 1 | 2 |port |line | err | dir|
>>>>>>>> + +-----+-----+-----+-----+-----+----+
>>>>>>> Sorry, but i don't see how two u8 vs six u8 are the same message format.
>>>>>>>
>>>>>> Some changes to the message format are necessary.
>>>>>>
>>>>>> Virtio uses two communication channels (virtqueues): one for
>>>>>> requests and
>>>>> replies, and a second one for events.
>>>>>> In contrast, rpmsg provides only a single communication channel, so
>>>>>> a type field is required to distinguish between different kinds of messages.
>>>>>>
>>>>>> Since rpmsg replies and events share the same message format, an
>>>>>> additional
>>>>> line is introduced to handle both cases.
>>>>>> Finally, rpmsg supports multiple GPIO controllers, so a port field
>>>>>> is added to
>>>>> uniquely identify the target controller.
>>>>>
>>>>> I have commented on this before - RPMSG is already providing
>>>>> multiplexing capability by way of endpoints. There is no need for a
>>>>> port field. One endpoint, one GPIO controller.
>>>>>
>>>> You still need a way to let the remote side know which port the
>>>> endpoint maps to, either by embedding the port information in the
>>>> message (the current way), or by sending it separately.
>>>>
>>> An endpoint is created with every namespace request. There should be
>>> one namespace request for every GPIO controller, which yields a unique
>>> endpoint for each controller and eliminates the need for an extra
>>> field to identify them.
>>
>> Right, but this can still be done by just having one namespace request.
>> We can create new endpoints bound to an existing namespace/channel by
>> invoking rpmsg_create_ept(). This is what I suggested here too:
>> https://lore.kernel/
>> .org%2Fall%2F29485742-6e49-482e-b73d-
>> 228295daaeec%40ti.com%2F&data=05%7C02%7Cshenwei.wang%40nxp.com%7
>> Caba62d7a899849fd57f708dea61a1d8b%7C686ea1d3bc2b4c6fa92cd99c5c3016
>> 35%7C0%7C0%7C639130828278097401%7CUnknown%7CTWFpbGZsb3d8eyJFb
>> XB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpb
>> CIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=NLLYQ0NZCnYKLT%2F2OMDZE
>> SKgC%2Fme3FoUNqqEGBOIY2k%3D&reserved=0
>>
>> My mental model looks like this for the complete picture:
>>
>> 1. namespace/channel#1 = rpmsg-io
>> a. ept1 -> gpio-controller@1
>> b. ept2 -> gpio-controller@2
>>
>> 2. namespace/channel#2 = rpmsg-i2c
>> a. ept1 -> i2c@1
>> b. ept2 -> i2c@2
>> c. ept3 -> i2c@3
>>
> The GPIO nodes will act as providers.
> Mapping the port index into the service name is a possible solution,
I am not suggesting this. Infact the opposite. Let there be a single
rpmsg service "rpmsg-io" for gpio. And multiple endpoints within
the service, each for one controller. Once you have relayed this info
(dynamic ept addr corresponding to each port) back to the
firmware, you no longer need the "port" field in the message
anymore.
Did you get a chance to analyze this?:
https://lore.kernel.org/all/a067452a-9a8d-45ea-8bef-b44f851da7b2@ti.com/
Thanks,
Beleswar
> but I don't believe it's better than
> embedding that information in the message. A stateless approach feels simpler and cleaner overall.
>
> Thanks,
> Shenwei
>
>
>> etc...
>>
>> This way device groups are isolated with each channel/namespace, and instances
>> within each device groups are also respected with specific endpoints.
>>
>> Thanks,
>> Beleswar
^ permalink raw reply
* [PATCH v3 1/2] dt-bindings: mailbox: google,gs101-mbox: Add samsung,exynos850-mbox
From: Alexey Klimov @ 2026-04-29 19:00 UTC (permalink / raw)
To: Krzysztof Kozlowski, Sam Protsenko, Rob Herring, Conor Dooley,
Tudor Ambarus, Jassi Brar, Alim Akhtar
Cc: Krzysztof Kozlowski, Peter Griffin, linux-samsung-soc,
linux-arm-kernel, devicetree, linux-kernel, Alexey Klimov,
Krzysztof Kozlowski
In-Reply-To: <20260429-exynos850-ap2apm-mailbox-v3-0-8e2719608c46@linaro.org>
Document support for a mailbox present on Exynos850-based platforms.
The registers offsets are different from gs101 mailbox, but the
workflow is similar, hence new compatible.
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org>
---
Documentation/devicetree/bindings/mailbox/google,gs101-mbox.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mailbox/google,gs101-mbox.yaml b/Documentation/devicetree/bindings/mailbox/google,gs101-mbox.yaml
index e249db4c1fbc..c109c1f7af24 100644
--- a/Documentation/devicetree/bindings/mailbox/google,gs101-mbox.yaml
+++ b/Documentation/devicetree/bindings/mailbox/google,gs101-mbox.yaml
@@ -20,7 +20,9 @@ description:
properties:
compatible:
- const: google,gs101-mbox
+ enum:
+ - google,gs101-mbox
+ - samsung,exynos850-mbox
reg:
maxItems: 1
--
2.51.0
^ permalink raw reply related
* [PATCH v3 0/2] Exynos850 AP-to-APM mailbox support
From: Alexey Klimov @ 2026-04-29 19:00 UTC (permalink / raw)
To: Krzysztof Kozlowski, Sam Protsenko, Rob Herring, Conor Dooley,
Tudor Ambarus, Jassi Brar, Alim Akhtar
Cc: Krzysztof Kozlowski, Peter Griffin, linux-samsung-soc,
linux-arm-kernel, devicetree, linux-kernel, Alexey Klimov,
Krzysztof Kozlowski
This patch series introduces support for the AP-to-APM mailbox on the
Exynos850 SoC. This mailbox is required for communicating with the APM
co-processor using ACPM.
The Exynos850 mailbox operates similarly to the existing gs101
implementation, but the register offsets and IRQ mask bits differ.
This series abstracts these differences into platform-specific data
structures matched via the device tree.
Also, it requires APM-to-AP mailbox clock in CMU_APM block (which was
already merged). I also dropped clk-list emails from this series.
Will be appreciated if it can be tested on gs101 to make sure that I
didn't break anything.
Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org>
---
Changes in v3:
- exynos850 dts change is split out to a separate patch;
- updated commit messages to a proper name AP-to-APM;
- added comment "ring the doorbell" right before generating an IRQ to APM;
- renamed regs callback names to intgr, intgr_shift, intmr, intmr_mask;
- Link to v2: https://lore.kernel.org/r/20260402-exynos850-ap2apm-mailbox-v2-0-ca5ffdff99d4@linaro.org
Changes in v2:
- dropped clock patches (they seem to be merged);
- patch 3: updated commit description mentioning that
exynos850 is not compatible to gs101 mbox (as suggested by Krzysztof);
- fixed comment description for struct exynos_mbox_driver_data
(reported by kernel test robot <lkp@intel.com>);
- Link to v1: https://lore.kernel.org/r/20260320-exynos850-ap2apm-mailbox-v1-0-983eb3f296fc@linaro.org
---
Alexey Klimov (2):
dt-bindings: mailbox: google,gs101-mbox: Add samsung,exynos850-mbox
mailbox: exynos: Add support for Exynos850 mailbox
.../bindings/mailbox/google,gs101-mbox.yaml | 4 +-
drivers/mailbox/exynos-mailbox.c | 59 ++++++++++++++++++++--
2 files changed, 59 insertions(+), 4 deletions(-)
---
base-commit: 0787c45ea08a13b5482e701fabc741877cf681f6
change-id: 20260320-exynos850-ap2apm-mailbox-cff0c8d69898
Best regards,
--
Alexey Klimov <alexey.klimov@linaro.org>
^ permalink raw reply
* [PATCH v3 2/2] mailbox: exynos: Add support for Exynos850 mailbox
From: Alexey Klimov @ 2026-04-29 19:00 UTC (permalink / raw)
To: Krzysztof Kozlowski, Sam Protsenko, Rob Herring, Conor Dooley,
Tudor Ambarus, Jassi Brar, Alim Akhtar
Cc: Krzysztof Kozlowski, Peter Griffin, linux-samsung-soc,
linux-arm-kernel, devicetree, linux-kernel, Alexey Klimov,
Krzysztof Kozlowski
In-Reply-To: <20260429-exynos850-ap2apm-mailbox-v3-0-8e2719608c46@linaro.org>
Exynos850-based platforms support ACPM and has similar workflow
of communicating with ACPM via mailbox, however mailbox controller
registers are located at different offsets and writes/reads could be
different. To distinguish between such different behaviours,
the registers offsets for Exynos850 and the platform-specific data
structs are introduced and configuration is described in such structs
for gs101 and exynos850 based SoCs. Probe routine now selects the
corresponding platform-specific data via device_get_match_data().
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org>
---
drivers/mailbox/exynos-mailbox.c | 59 ++++++++++++++++++++++++++++++++++++++--
1 file changed, 56 insertions(+), 3 deletions(-)
diff --git a/drivers/mailbox/exynos-mailbox.c b/drivers/mailbox/exynos-mailbox.c
index d2355b128ba4..11657dd475c0 100644
--- a/drivers/mailbox/exynos-mailbox.c
+++ b/drivers/mailbox/exynos-mailbox.c
@@ -31,14 +31,52 @@
#define EXYNOS_MBOX_CHAN_COUNT HWEIGHT32(EXYNOS_MBOX_INTGR1_MASK)
+#define EXYNOS850_MBOX_INTGR0 0x8 /* Interrupt Generation Register 0 */
+#define EXYNOS850_MBOX_INTMR1 0x24 /* Interrupt Mask Register 1 */
+
+#define EXYNOS850_MBOX_INTMR1_MASK GENMASK(15, 0)
+
+/**
+ * struct exynos_mbox_driver_data - platform-specific mailbox configuration.
+ * @intgr: offset to the IRQ generation register, doorbell
+ * to APM co-processor.
+ * @intgr_shift: shift to apply to the value written to IRQ generation
+ * register.
+ * @intmr: offset to the IRQ mask register.
+ * @intmr_mask: value to write to the mask register to mask out all
+ * interrupts.
+ */
+struct exynos_mbox_driver_data {
+ u16 intgr;
+ u16 intgr_shift;
+ u16 intmr;
+ u16 intmr_mask;
+};
+
/**
* struct exynos_mbox - driver's private data.
* @regs: mailbox registers base address.
* @mbox: pointer to the mailbox controller.
+ * @data: pointer to driver platform-specific data.
*/
struct exynos_mbox {
void __iomem *regs;
struct mbox_controller *mbox;
+ const struct exynos_mbox_driver_data *data;
+};
+
+static const struct exynos_mbox_driver_data exynos850_mbox_data = {
+ .intgr = EXYNOS850_MBOX_INTGR0,
+ .intgr_shift = 16,
+ .intmr = EXYNOS850_MBOX_INTMR1,
+ .intmr_mask = EXYNOS850_MBOX_INTMR1_MASK,
+};
+
+static const struct exynos_mbox_driver_data exynos_gs101_mbox_data = {
+ .intgr = EXYNOS_MBOX_INTGR1,
+ .intgr_shift = 0,
+ .intmr = EXYNOS_MBOX_INTMR0,
+ .intmr_mask = EXYNOS_MBOX_INTMR0_MASK,
};
static int exynos_mbox_send_data(struct mbox_chan *chan, void *data)
@@ -57,7 +95,9 @@ static int exynos_mbox_send_data(struct mbox_chan *chan, void *data)
return -EINVAL;
}
- writel(BIT(msg->chan_id), exynos_mbox->regs + EXYNOS_MBOX_INTGR1);
+ /* Ring the doorbell */
+ writel(BIT(msg->chan_id) << exynos_mbox->data->intgr_shift,
+ exynos_mbox->regs + exynos_mbox->data->intgr);
return 0;
}
@@ -87,13 +127,21 @@ static struct mbox_chan *exynos_mbox_of_xlate(struct mbox_controller *mbox,
}
static const struct of_device_id exynos_mbox_match[] = {
- { .compatible = "google,gs101-mbox" },
+ {
+ .compatible = "google,gs101-mbox",
+ .data = &exynos_gs101_mbox_data
+ },
+ {
+ .compatible = "samsung,exynos850-mbox",
+ .data = &exynos850_mbox_data
+ },
{},
};
MODULE_DEVICE_TABLE(of, exynos_mbox_match);
static int exynos_mbox_probe(struct platform_device *pdev)
{
+ const struct exynos_mbox_driver_data *data;
struct device *dev = &pdev->dev;
struct exynos_mbox *exynos_mbox;
struct mbox_controller *mbox;
@@ -122,6 +170,11 @@ static int exynos_mbox_probe(struct platform_device *pdev)
return dev_err_probe(dev, PTR_ERR(pclk),
"Failed to enable clock.\n");
+ data = device_get_match_data(&pdev->dev);
+ if (!data)
+ return -ENODEV;
+
+ exynos_mbox->data = data;
mbox->num_chans = EXYNOS_MBOX_CHAN_COUNT;
mbox->chans = chans;
mbox->dev = dev;
@@ -133,7 +186,7 @@ static int exynos_mbox_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, exynos_mbox);
/* Mask out all interrupts. We support just polling channels for now. */
- writel(EXYNOS_MBOX_INTMR0_MASK, exynos_mbox->regs + EXYNOS_MBOX_INTMR0);
+ writel(data->intmr_mask, exynos_mbox->regs + data->intmr);
return devm_mbox_controller_register(dev, mbox);
}
--
2.51.0
^ permalink raw reply related
* Re: [PATCH] media: cedrus: clean up media device on probe failure
From: Nicolas Dufresne @ 2026-04-29 19:08 UTC (permalink / raw)
To: 박명훈, Maxime Ripard, Paul Kocialkowski,
Mauro Carvalho Chehab, Greg Kroah-Hartman, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland
Cc: linux-media, linux-staging, linux-arm-kernel, linux-sunxi,
linux-kernel, stable, Ijae Kim
In-Reply-To: <20260427100049.29034-1-pakmyeonghun@bagmyeonghun-ui-MacBookPro.local>
[-- Attachment #1: Type: text/plain, Size: 1892 bytes --]
Le lundi 27 avril 2026 à 19:00 +0900, 박명훈 a écrit :
> From: Myeonghun Pak <mhun512@gmail.com>
>
> cedrus_probe() initializes the media device before registering the video
> device, the media controller, and the media device. If any of those later
> steps fails, probe returns without calling media_device_cleanup(), so the
> media device internals initialized by media_device_init() are left behind.
>
> Add a media-device cleanup label to the probe unwind path and route video
> registration failures through it as well.
>
> Fixes: 50e761516f2b8c ("media: platform: Add Cedrus VPU decoder driver")
> Cc: stable@vger.kernel.org
> Co-developed-by: Ijae Kim <ae878000@gmail.com>
> Signed-off-by: Ijae Kim <ae878000@gmail.com>
> Signed-off-by: Myeonghun Pak <mhun512@gmail.com>
> ---
> drivers/staging/media/sunxi/cedrus/cedrus.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c
> index 6600245dff..2c25654640 100644
> --- a/drivers/staging/media/sunxi/cedrus/cedrus.c
> +++ b/drivers/staging/media/sunxi/cedrus/cedrus.c
> @@ -507,7 +507,7 @@ static int cedrus_probe(struct platform_device *pdev)
> ret = video_register_device(vfd, VFL_TYPE_VIDEO, 0);
> if (ret) {
> v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
> - goto err_m2m;
> + goto err_media_cleanup;
> }
>
> v4l2_info(&dev->v4l2_dev,
> @@ -533,6 +533,8 @@ static int cedrus_probe(struct platform_device *pdev)
> v4l2_m2m_unregister_media_controller(dev->m2m_dev);
> err_video:
> video_unregister_device(&dev->vfd);
> +err_media_cleanup:
> + media_device_cleanup(&dev->mdev);
> err_m2m:
This label is left unused. Can you fix this warning please.
Nicolas
> v4l2_m2m_release(dev->m2m_dev);
> err_v4l2:
[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply
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