* Re: [PATCH v2 2/3] iio: adc: sun20i-gpadc: add A523 gpadc support
From: Andre Przywara @ 2026-05-13 11:53 UTC (permalink / raw)
To: Sanjay Chitroda, Michal Piekos, Jonathan Cameron, David Lechner,
Nuno Sá, Andy Shevchenko, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Chen-Yu Tsai, Jernej Skrabec, Samuel Holland,
Maksim Kiselev
Cc: linux-iio, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel
In-Reply-To: <A7772824-E704-4BFD-A796-BCD81197E5A2@gmail.com>
Hi Sanjay,
thanks for having a look!
On 5/13/26 13:44, Sanjay Chitroda wrote:
>
>
> On 13 May 2026 10:29:43 am IST, Michal Piekos <michal.piekos@mmpsystems.pl> wrote:
>> A523 differs from existing sun20i-gpadc-iio by having two clocks; bus
>> clock and module clock.
>>
>> Change driver to enable all clocks.
>>
>> Signed-off-by: Michal Piekos <michal.piekos@mmpsystems.pl>
>> ---
>> drivers/iio/adc/sun20i-gpadc-iio.c | 11 +++++++----
>> 1 file changed, 7 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/iio/adc/sun20i-gpadc-iio.c b/drivers/iio/adc/sun20i-gpadc-iio.c
>> index 861c14da75ad..3f1f07b3a385 100644
>> --- a/drivers/iio/adc/sun20i-gpadc-iio.c
>> +++ b/drivers/iio/adc/sun20i-gpadc-iio.c
>> @@ -180,7 +180,7 @@ static int sun20i_gpadc_probe(struct platform_device *pdev)
>> struct iio_dev *indio_dev;
>> struct sun20i_gpadc_iio *info;
>> struct reset_control *rst;
>> - struct clk *clk;
>> + struct clk_bulk_data *clks;
>> int irq;
>> int ret;
>>
>> @@ -205,9 +205,11 @@ static int sun20i_gpadc_probe(struct platform_device *pdev)
>> if (IS_ERR(info->regs))
>> return PTR_ERR(info->regs);
>>
>> - clk = devm_clk_get_enabled(dev, NULL);
>> - if (IS_ERR(clk))
>> - return dev_err_probe(dev, PTR_ERR(clk), "failed to enable bus clock\n");
>> + ret = devm_clk_bulk_get_all_enabled(dev, &clks);
>> + if (ret <= 0)
>
> Thank you Michal for the change.
>
> Have you validated the changes ?
> It looks while success ret would be 0 and it would give return error.
But devm_clk_bulk_get_all_enabled() returns the number of clocks found
and enabled. And since we need at least one, I think this is correct,
and the error message below reflects that.
To me that change looks good:
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Cheers,
Andre
>
> Thanks, Sanjay
>
>
>> + return dev_err_probe(
>> + dev, ret,
>> + "failed to enable clocks or no clocks defined\n");
>>
>> rst = devm_reset_control_get_exclusive(dev, NULL);
>> if (IS_ERR(rst))
>> @@ -243,6 +245,7 @@ static int sun20i_gpadc_probe(struct platform_device *pdev)
>>
>> static const struct of_device_id sun20i_gpadc_of_id[] = {
>> { .compatible = "allwinner,sun20i-d1-gpadc" },
>> + { .compatible = "allwinner,sun55i-a523-gpadc" },
>> { }
>> };
>> MODULE_DEVICE_TABLE(of, sun20i_gpadc_of_id);
>>
>
^ permalink raw reply
* Re: [PATCH v2 2/3] iio: adc: sun20i-gpadc: add A523 gpadc support
From: Sanjay Chitroda @ 2026-05-13 11:44 UTC (permalink / raw)
To: Michal Piekos, Jonathan Cameron, David Lechner, Nuno Sá,
Andy Shevchenko, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Maksim Kiselev
Cc: linux-iio, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel
In-Reply-To: <20260513-sunxi-a523-gpadc-v2-2-d5efde151dac@mmpsystems.pl>
On 13 May 2026 10:29:43 am IST, Michal Piekos <michal.piekos@mmpsystems.pl> wrote:
>A523 differs from existing sun20i-gpadc-iio by having two clocks; bus
>clock and module clock.
>
>Change driver to enable all clocks.
>
>Signed-off-by: Michal Piekos <michal.piekos@mmpsystems.pl>
>---
> drivers/iio/adc/sun20i-gpadc-iio.c | 11 +++++++----
> 1 file changed, 7 insertions(+), 4 deletions(-)
>
>diff --git a/drivers/iio/adc/sun20i-gpadc-iio.c b/drivers/iio/adc/sun20i-gpadc-iio.c
>index 861c14da75ad..3f1f07b3a385 100644
>--- a/drivers/iio/adc/sun20i-gpadc-iio.c
>+++ b/drivers/iio/adc/sun20i-gpadc-iio.c
>@@ -180,7 +180,7 @@ static int sun20i_gpadc_probe(struct platform_device *pdev)
> struct iio_dev *indio_dev;
> struct sun20i_gpadc_iio *info;
> struct reset_control *rst;
>- struct clk *clk;
>+ struct clk_bulk_data *clks;
> int irq;
> int ret;
>
>@@ -205,9 +205,11 @@ static int sun20i_gpadc_probe(struct platform_device *pdev)
> if (IS_ERR(info->regs))
> return PTR_ERR(info->regs);
>
>- clk = devm_clk_get_enabled(dev, NULL);
>- if (IS_ERR(clk))
>- return dev_err_probe(dev, PTR_ERR(clk), "failed to enable bus clock\n");
>+ ret = devm_clk_bulk_get_all_enabled(dev, &clks);
>+ if (ret <= 0)
Thank you Michal for the change.
Have you validated the changes ?
It looks while success ret would be 0 and it would give return error.
Thanks, Sanjay
>+ return dev_err_probe(
>+ dev, ret,
>+ "failed to enable clocks or no clocks defined\n");
>
> rst = devm_reset_control_get_exclusive(dev, NULL);
> if (IS_ERR(rst))
>@@ -243,6 +245,7 @@ static int sun20i_gpadc_probe(struct platform_device *pdev)
>
> static const struct of_device_id sun20i_gpadc_of_id[] = {
> { .compatible = "allwinner,sun20i-d1-gpadc" },
>+ { .compatible = "allwinner,sun55i-a523-gpadc" },
> { }
> };
> MODULE_DEVICE_TABLE(of, sun20i_gpadc_of_id);
>
^ permalink raw reply
* Re: [PATCH] iommu/arm-smmu-v3-sva: Enable Hardware Access and Hardware Dirty bits
From: Will Deacon @ 2026-05-13 11:42 UTC (permalink / raw)
To: Pranjal Shrivastava
Cc: Nicolin Chen, Robin Murphy, Jason Gunthorpe, Joerg Roedel,
Jean-Philippe Brucker, Catalin Marinas, Mikołaj Lenczewski,
linux-arm-kernel, iommu, linux-kernel
In-Reply-To: <agHYDxuYyqzmAfy5@google.com>
On Mon, May 11, 2026 at 01:22:23PM +0000, Pranjal Shrivastava wrote:
> On Sat, May 09, 2026 at 12:56:57AM -0700, Nicolin Chen wrote:
> > On Fri, May 08, 2026 at 03:24:32PM +0100, Robin Murphy wrote:
> > > On 2026-05-08 2:57 pm, Pranjal Shrivastava wrote:
> > > > I see, so IIUC, you mean if IS_ENABLED(CONFIG_ARM64_HW_AFDBM) but CPU
> > > > doesn't enable HTTU, it is perfectly safe to let the SMMU do HTT updates,
> > > > Since the fault handlers are already expecting HW-triggered updates?
> > > >
> > > > Which means our check would be something like:
> > > >
> > > > if (IS_ENABLED(CONFIG_ARM64_HW_AFDBM) {
> > > > if (smmu->features & FEAT_HA)
> > > > ...
> > > > }
> > > >
> > > > instead of cpu_has_hw_af()?
> > >
> > > Hmm, looking closer, cpu_has_hw_af() is the thing which actually influences
> > > mm behaviour (via arch_has_hw_pte_young and arch_wants_old_prefaulted_pte),
> > > and that can still be false at runtime if ARM64_HW_AFDBM is enabled but any
> > > CPU doesn't support HAFDBS, so perhaps you were right the first time :)
> >
> > IIUIC, v2 should be:
> >
> > + /*
> > + * Enable Hardware Access and Dirty updates (DBM) if supported by
> > + * both the SMMU and the CPU. It is unsafe to enable SMMU's HTTU,
> > + * if the CPU does not support it as it bypasses mm page aging.
> > + */
> > + if (cpu_has_hw_af()) {
>
> Ack, yes. IMO, this is the correct system-wide gate.
Hmm, I'm not so sure :/
cpu_has_hw_af() doesn't take into account CPUs with broken DBM and, in
fact, ID_AA64MMFR1_EL1.HAFDBS allows support for AF to be advertised
without support for DBM.
Having said that, I don't understand why we need to care about the CPU
support. The comment above states:
"It is unsafe to enable SMMU's HTTU, if the CPU does not support it as
it bypasses mm page aging."
but I don't understand what that "bypassing" means. vmscan should still
pick up the correct state from the page-table, so what's the problem?
Will
^ permalink raw reply
* Re: [PATCH net-next v6 08/12] net: airoha: Support multiple net_devices for a single FE GDM port
From: Lorenzo Bianconi @ 2026-05-13 9:26 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Christian Marangi, Benjamin Larsson, linux-arm-kernel,
linux-mediatek, netdev, devicetree, Xuegang Lu
In-Reply-To: <20260511-airoha-eth-multi-serdes-v6-8-c899462c4f75@kernel.org>
[-- Attachment #1: Type: text/plain, Size: 20393 bytes --]
On May 11, Lorenzo Bianconi wrote:
> EN7581 or AN7583 SoCs support connecting multiple external SerDes (e.g.
> Ethernet or USB SerDes) to GDM3 or GDM4 ports via a hw arbiter that
> manages the traffic in a TDM manner. As a result multiple net_devices can
> connect to the same GDM{3,4} port and there is a theoretical "1:n"
> relation between GDM ports and net_devices.
>
> ┌─────────────────────────────────┐
> │ │ ┌──────┐
> │ P1 GDM1 ├────►MT7530│
> │ │ └──────┘
> │ │ ETH0 (DSA conduit)
> │ │
> │ PSE/FE │
> │ │
> │ │
> │ │ ┌─────┐
> │ P0 CDM1 ├────►QDMA0│
> │ P4 P9 GDM4 │ └─────┘
> └──┬─────────────────────────┬────┘
> │ │
> ┌──▼──┐ ┌────▼────┐
> │ PPE │ │ ARB │
> └─────┘ └─┬─────┬─┘
> │ │
> ┌──▼──┐┌─▼───┐
> │ ETH ││ USB │
> └─────┘└─────┘
> ETH1 ETH2
>
> Introduce support for multiple net_devices connected to the same Frame
> Engine (FE) GDM port (GDM3 or GDM4) via an external hw arbiter.
> Please note GDM1 or GDM2 does not support the connection with the external
> arbiter.
> Add get_dev_from_sport callback since EN7581 and AN7583 have different
> logics for the net_device type connected to GDM3 or GDM4.
>
> Tested-by: Xuegang Lu <xuegang.lu@airoha.com>
> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> ---
> drivers/net/ethernet/airoha/airoha_eth.c | 271 ++++++++++++++++++++++++-------
> drivers/net/ethernet/airoha/airoha_eth.h | 10 +-
> drivers/net/ethernet/airoha/airoha_ppe.c | 13 +-
> 3 files changed, 228 insertions(+), 66 deletions(-)
>
> diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
> index f0d5f28dd731..4efd36779453 100644
> --- a/drivers/net/ethernet/airoha/airoha_eth.c
> +++ b/drivers/net/ethernet/airoha/airoha_eth.c
> @@ -106,7 +106,7 @@ static int airoha_set_vip_for_gdm_port(struct airoha_gdm_dev *dev, bool enable)
> struct airoha_eth *eth = dev->eth;
> u32 vip_port;
>
> - vip_port = eth->soc->ops.get_vip_port(port, port->nbq);
> + vip_port = eth->soc->ops.get_vip_port(port, dev->nbq);
> if (enable) {
> airoha_fe_set(eth, REG_FE_VIP_PORT_EN, vip_port);
> airoha_fe_set(eth, REG_FE_IFC_PORT_EN, vip_port);
> @@ -566,24 +566,26 @@ static int airoha_qdma_fill_rx_queue(struct airoha_queue *q)
> return nframes;
> }
>
> -static int airoha_qdma_get_gdm_port(struct airoha_eth *eth,
> - struct airoha_qdma_desc *desc)
> +static struct airoha_gdm_dev *
> +airoha_qdma_get_gdm_dev(struct airoha_eth *eth, struct airoha_qdma_desc *desc)
> {
> - u32 port, sport, msg1 = le32_to_cpu(READ_ONCE(desc->msg1));
> + struct airoha_gdm_port *port;
> + u16 p, d;
>
> - sport = FIELD_GET(QDMA_ETH_RXMSG_SPORT_MASK, msg1);
> - switch (sport) {
> - case 0x10 ... 0x14:
> - port = 0;
> - break;
> - case 0x2 ... 0x4:
> - port = sport - 1;
> - break;
> - default:
> - return -EINVAL;
> - }
> + if (eth->soc->ops.get_dev_from_sport(desc, &p, &d))
> + return ERR_PTR(-ENODEV);
>
> - return port >= ARRAY_SIZE(eth->ports) ? -EINVAL : port;
> + if (p >= ARRAY_SIZE(eth->ports))
> + return ERR_PTR(-ENODEV);
> +
> + port = eth->ports[p];
> + if (!port)
> + return ERR_PTR(-ENODEV);
> +
> + if (d >= ARRAY_SIZE(port->devs))
> + return ERR_PTR(-ENODEV);
> +
> + return port->devs[d] ? port->devs[d] : ERR_PTR(-ENODEV);
> }
>
> static int airoha_qdma_rx_process(struct airoha_queue *q, int budget)
> @@ -598,9 +600,8 @@ static int airoha_qdma_rx_process(struct airoha_queue *q, int budget)
> struct airoha_queue_entry *e = &q->entry[q->tail];
> struct airoha_qdma_desc *desc = &q->desc[q->tail];
> u32 hash, reason, msg1, desc_ctrl;
> - struct airoha_gdm_port *port;
> - struct net_device *netdev;
> - int data_len, len, p;
> + struct airoha_gdm_dev *dev;
> + int data_len, len;
> struct page *page;
>
> desc_ctrl = le32_to_cpu(READ_ONCE(desc->ctrl));
> @@ -623,12 +624,10 @@ static int airoha_qdma_rx_process(struct airoha_queue *q, int budget)
> if (!len || data_len < len)
> goto free_frag;
>
> - p = airoha_qdma_get_gdm_port(eth, desc);
> - if (p < 0 || !eth->ports[p])
> + dev = airoha_qdma_get_gdm_dev(eth, desc);
> + if (IS_ERR(dev))
> goto free_frag;
>
> - port = eth->ports[p];
> - netdev = port->dev->dev;
> if (!q->skb) { /* first buffer */
> q->skb = napi_build_skb(e->buf - AIROHA_RX_HEADROOM,
> q->buf_size);
> @@ -638,8 +637,8 @@ static int airoha_qdma_rx_process(struct airoha_queue *q, int budget)
> skb_reserve(q->skb, AIROHA_RX_HEADROOM);
> __skb_put(q->skb, len);
> skb_mark_for_recycle(q->skb);
> - q->skb->dev = netdev;
> - q->skb->protocol = eth_type_trans(q->skb, netdev);
> + q->skb->dev = dev->dev;
> + q->skb->protocol = eth_type_trans(q->skb, dev->dev);
> q->skb->ip_summed = CHECKSUM_UNNECESSARY;
> skb_record_rx_queue(q->skb, qid);
> } else { /* scattered frame */
> @@ -657,7 +656,9 @@ static int airoha_qdma_rx_process(struct airoha_queue *q, int budget)
> if (FIELD_GET(QDMA_DESC_MORE_MASK, desc_ctrl))
> continue;
>
> - if (netdev_uses_dsa(netdev)) {
> + if (netdev_uses_dsa(dev->dev)) {
> + struct airoha_gdm_port *port = dev->port;
> +
> /* PPE module requires untagged packets to work
> * properly and it provides DSA port index via the
> * DMA descriptor. Report DSA tag to the DSA stack
> @@ -851,24 +852,27 @@ static void airoha_qdma_wake_netdev_txqs(struct airoha_queue *q)
>
> for (i = 0; i < ARRAY_SIZE(eth->ports); i++) {
> struct airoha_gdm_port *port = eth->ports[i];
> - struct airoha_gdm_dev *dev;
> - int j;
> + int d;
>
> if (!port)
> continue;
>
> - dev = port->dev;
> - if (!dev)
> - continue;
> + for (d = 0; d < ARRAY_SIZE(port->devs); d++) {
> + struct airoha_gdm_dev *dev = port->devs[d];
> + int j;
>
> - if (dev->qdma != qdma)
> - continue;
> + if (!dev)
> + continue;
>
> - for (j = 0; j < dev->dev->num_tx_queues; j++) {
> - if (airoha_qdma_get_txq(qdma, j) != qid)
> + if (dev->qdma != qdma)
> continue;
>
> - netif_wake_subqueue(dev->dev, j);
> + for (j = 0; j < dev->dev->num_tx_queues; j++) {
> + if (airoha_qdma_get_txq(qdma, j) != qid)
> + continue;
> +
> + netif_wake_subqueue(dev->dev, j);
> + }
> }
> }
> q->txq_stopped = false;
> @@ -1829,7 +1833,7 @@ static int airoha_set_gdm2_loopback(struct airoha_gdm_dev *dev)
> airoha_fe_clear(eth, REG_FE_VIP_PORT_EN, BIT(AIROHA_GDM2_IDX));
> airoha_fe_clear(eth, REG_FE_IFC_PORT_EN, BIT(AIROHA_GDM2_IDX));
>
> - src_port = eth->soc->ops.get_sport(port, port->nbq);
> + src_port = eth->soc->ops.get_sport(port, dev->nbq);
> if (src_port < 0)
> return src_port;
>
> @@ -1846,7 +1850,7 @@ static int airoha_set_gdm2_loopback(struct airoha_gdm_dev *dev)
> airoha_ppe_set_cpu_port(dev, i, AIROHA_GDM2_IDX);
>
> if (port->id == AIROHA_GDM4_IDX && airoha_is_7581(eth)) {
> - u32 mask = FC_ID_OF_SRC_PORT_MASK(port->nbq);
> + u32 mask = FC_ID_OF_SRC_PORT_MASK(dev->nbq);
>
> airoha_fe_rmw(eth, REG_SRC_PORT_FC_MAP6, mask,
> __field_prep(mask, AIROHA_GDM2_IDX));
> @@ -2050,7 +2054,8 @@ static netdev_tx_t airoha_dev_xmit(struct sk_buff *skb,
> }
>
> fport = airoha_get_fe_port(dev);
> - msg1 = FIELD_PREP(QDMA_ETH_TXMSG_FPORT_MASK, fport) |
> + msg1 = FIELD_PREP(QDMA_ETH_TXMSG_NBOQ_MASK, dev->nbq) |
> + FIELD_PREP(QDMA_ETH_TXMSG_FPORT_MASK, fport) |
> FIELD_PREP(QDMA_ETH_TXMSG_METER_MASK, 0x7f);
>
> q = &qdma->q_tx[qid];
> @@ -2983,12 +2988,15 @@ bool airoha_is_valid_gdm_dev(struct airoha_eth *eth,
>
> for (i = 0; i < ARRAY_SIZE(eth->ports); i++) {
> struct airoha_gdm_port *port = eth->ports[i];
> + int j;
>
> if (!port)
> continue;
>
> - if (port->dev == dev)
> - return true;
> + for (j = 0; j < ARRAY_SIZE(port->devs); j++) {
> + if (port->devs[j] == dev)
> + return true;
> + }
> }
>
> return false;
> @@ -2996,10 +3004,11 @@ bool airoha_is_valid_gdm_dev(struct airoha_eth *eth,
>
> static int airoha_alloc_gdm_device(struct airoha_eth *eth,
> struct airoha_gdm_port *port,
> - struct device_node *np)
> + int nbq, struct device_node *np)
> {
> - struct airoha_gdm_dev *dev;
> struct net_device *netdev;
> + struct airoha_gdm_dev *dev;
> + u8 index;
> int err;
>
> netdev = devm_alloc_etherdev_mqs(eth->dev, sizeof(*dev),
> @@ -3019,7 +3028,6 @@ static int airoha_alloc_gdm_device(struct airoha_eth *eth,
> NETIF_F_HW_TC;
> netdev->features |= netdev->hw_features;
> netdev->vlan_features = netdev->hw_features;
> - netdev->dev.of_node = np;
> SET_NETDEV_DEV(netdev, eth->dev);
>
> /* reserve hw queues for HTB offloading */
> @@ -3037,11 +3045,25 @@ static int airoha_alloc_gdm_device(struct airoha_eth *eth,
> netdev->dev_addr);
> }
>
> + /* Allowed nbq for EN7581 on GDM3 port are 4 and 5 for PCIE0
> + * and PCIE1 respectively.
> + */
> + index = nbq;
> + if (index && airoha_is_7581(eth) && port->id == AIROHA_GDM3_IDX)
> + index -= 4;
> +
> + if (index >= ARRAY_SIZE(port->devs) || port->devs[index]) {
> + dev_err(eth->dev, "invalid nbq id: %d\n", nbq);
> + return -EINVAL;
> + }
> +
> + netdev->dev.of_node = of_node_get(np);
> dev = netdev_priv(netdev);
> dev->dev = netdev;
> dev->port = port;
> - port->dev = dev;
> dev->eth = eth;
> + dev->nbq = nbq;
> + port->devs[index] = dev;
>
> return 0;
> }
> @@ -3051,7 +3073,8 @@ static int airoha_alloc_gdm_port(struct airoha_eth *eth,
> {
> const __be32 *id_ptr = of_get_property(np, "reg", NULL);
> struct airoha_gdm_port *port;
> - int err, p;
> + struct device_node *node;
> + int err, nbq, p, d = 0;
> u32 id;
>
> if (!id_ptr) {
> @@ -3079,15 +3102,51 @@ static int airoha_alloc_gdm_port(struct airoha_eth *eth,
> u64_stats_init(&port->stats.syncp);
> spin_lock_init(&port->stats.lock);
> port->id = id;
> - /* XXX: Read nbq from DTS */
> - port->nbq = id == AIROHA_GDM3_IDX && airoha_is_7581(eth) ? 4 : 0;
> eth->ports[p] = port;
>
> err = airoha_metadata_dst_alloc(port);
> if (err)
> return err;
>
> - return airoha_alloc_gdm_device(eth, port, np);
> + /* Default nbq value to ensure backward compatibility */
> + nbq = id == AIROHA_GDM3_IDX && airoha_is_7581(eth) ? 4 : 0;
> +
> + for_each_child_of_node(np, node) {
> + /* Multiple external serdes connected to the FE GDM port via an
> + * external arbiter.
> + */
> + const __be32 *nbq_ptr;
> +
> + if (!of_device_is_compatible(node, "airoha,eth-port"))
> + continue;
> +
> + d++;
> + if (!of_device_is_available(node))
> + continue;
> +
> + nbq_ptr = of_get_property(node, "reg", NULL);
> + if (!nbq_ptr) {
> + dev_err(eth->dev, "missing nbq id\n");
> + of_node_put(node);
> + return -EINVAL;
> + }
> +
> + /* Verify the provided nbq parameter is valid */
> + nbq = be32_to_cpup(nbq_ptr);
> + err = eth->soc->ops.get_sport(port, nbq);
> + if (err < 0) {
> + of_node_put(node);
> + return err;
> + }
> +
> + err = airoha_alloc_gdm_device(eth, port, nbq, node);
> + if (err) {
> + of_node_put(node);
> + return err;
> + }
> + }
> +
> + return !d ? airoha_alloc_gdm_device(eth, port, nbq, np) : 0;
> }
>
> static int airoha_register_gdm_devices(struct airoha_eth *eth)
> @@ -3096,14 +3155,22 @@ static int airoha_register_gdm_devices(struct airoha_eth *eth)
>
> for (i = 0; i < ARRAY_SIZE(eth->ports); i++) {
> struct airoha_gdm_port *port = eth->ports[i];
> - int err;
> + int j;
>
> if (!port)
> continue;
>
> - err = register_netdev(port->dev->dev);
> - if (err)
> - return err;
> + for (j = 0; j < ARRAY_SIZE(port->devs); j++) {
> + struct airoha_gdm_dev *dev = port->devs[j];
> + int err;
> +
> + if (!dev)
> + continue;
> +
> + err = register_netdev(dev->dev);
> + if (err)
> + return err;
> + }
> }
>
> set_bit(DEV_STATE_REGISTERED, ð->state);
> @@ -3210,14 +3277,23 @@ static int airoha_probe(struct platform_device *pdev)
>
> for (i = 0; i < ARRAY_SIZE(eth->ports); i++) {
> struct airoha_gdm_port *port = eth->ports[i];
> - struct airoha_gdm_dev *dev;
> + int j;
>
> if (!port)
> continue;
>
> - dev = port->dev;
> - if (dev && dev->dev->reg_state == NETREG_REGISTERED)
> - unregister_netdev(dev->dev);
> + for (j = 0; j < ARRAY_SIZE(port->devs); j++) {
> + struct airoha_gdm_dev *dev = port->devs[j];
> + struct net_device *netdev;
> +
> + if (!dev)
> + continue;
> +
> + netdev = dev->dev;
> + if (netdev->reg_state == NETREG_REGISTERED)
> + unregister_netdev(netdev);
> + of_node_put(netdev->dev.of_node);
> + }
> airoha_metadata_dst_free(port);
> }
> airoha_hw_cleanup(eth);
> @@ -3238,14 +3314,22 @@ static void airoha_remove(struct platform_device *pdev)
>
> for (i = 0; i < ARRAY_SIZE(eth->ports); i++) {
> struct airoha_gdm_port *port = eth->ports[i];
> - struct airoha_gdm_dev *dev;
> + int j;
>
> if (!port)
> continue;
>
> - dev = port->dev;
> - if (dev)
> - unregister_netdev(dev->dev);
> + for (j = 0; j < ARRAY_SIZE(port->devs); j++) {
> + struct airoha_gdm_dev *dev = port->devs[j];
> + struct net_device *netdev;
> +
> + if (!dev)
> + continue;
> +
> + netdev = dev->dev;
> + unregister_netdev(netdev);
> + of_node_put(netdev->dev.of_node);
> + }
> airoha_metadata_dst_free(port);
> }
> airoha_hw_cleanup(eth);
> @@ -3308,6 +3392,39 @@ static u32 airoha_en7581_get_vip_port(struct airoha_gdm_port *port, int nbq)
> return 0;
> }
>
> +static int airoha_en7581_get_dev_from_sport(struct airoha_qdma_desc *desc,
> + u16 *port, u16 *dev)
> +{
> + u32 sport = FIELD_GET(QDMA_ETH_RXMSG_SPORT_MASK,
> + le32_to_cpu(READ_ONCE(desc->msg1)));
> +
> + *dev = 0;
> + switch (sport) {
> + case 0x10 ... 0x14:
> + *port = 0; /* GDM1 */
> + break;
> + case 0x2 ... 0x4:
> + *port = sport - 1;
> + break;
> + case HSGMII_LAN_7581_PCIE1_SRCPORT:
> + *dev = 1;
> + fallthrough;
> + case HSGMII_LAN_7581_PCIE0_SRCPORT:
> + *port = 2; /* GDM3 */
> + break;
> + case HSGMII_LAN_7581_USB_SRCPORT:
> + *dev = 1;
> + fallthrough;
> + case HSGMII_LAN_7581_ETH_SRCPORT:
> + *port = 3; /* GDM4 */
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> static const char * const an7583_xsi_rsts_names[] = {
> "xsi-mac",
> "hsi0-mac",
> @@ -3357,6 +3474,36 @@ static u32 airoha_an7583_get_vip_port(struct airoha_gdm_port *port, int nbq)
> return 0;
> }
>
> +static int airoha_an7583_get_dev_from_sport(struct airoha_qdma_desc *desc,
> + u16 *port, u16 *dev)
> +{
> + u32 sport = FIELD_GET(QDMA_ETH_RXMSG_SPORT_MASK,
> + le32_to_cpu(READ_ONCE(desc->msg1)));
> +
> + *dev = 0;
> + switch (sport) {
> + case 0x10 ... 0x14:
> + *port = 0; /* GDM1 */
> + break;
> + case 0x2 ... 0x4:
> + *port = sport - 1;
> + break;
> + case HSGMII_LAN_7583_ETH_SRCPORT:
> + *port = 2; /* GDM3 */
> + break;
> + case HSGMII_LAN_7583_USB_SRCPORT:
> + *dev = 1;
> + fallthrough;
> + case HSGMII_LAN_7583_PCIE_SRCPORT:
> + *port = 3; /* GDM4 */
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> static const struct airoha_eth_soc_data en7581_soc_data = {
> .version = 0x7581,
> .xsi_rsts_names = en7581_xsi_rsts_names,
> @@ -3365,6 +3512,7 @@ static const struct airoha_eth_soc_data en7581_soc_data = {
> .ops = {
> .get_sport = airoha_en7581_get_sport,
> .get_vip_port = airoha_en7581_get_vip_port,
> + .get_dev_from_sport = airoha_en7581_get_dev_from_sport,
> },
> };
>
> @@ -3376,6 +3524,7 @@ static const struct airoha_eth_soc_data an7583_soc_data = {
> .ops = {
> .get_sport = airoha_an7583_get_sport,
> .get_vip_port = airoha_an7583_get_vip_port,
> + .get_dev_from_sport = airoha_an7583_get_dev_from_sport,
> },
> };
>
> diff --git a/drivers/net/ethernet/airoha/airoha_eth.h b/drivers/net/ethernet/airoha/airoha_eth.h
> index fbb50dc73af8..fc49f0049983 100644
> --- a/drivers/net/ethernet/airoha/airoha_eth.h
> +++ b/drivers/net/ethernet/airoha/airoha_eth.h
> @@ -17,6 +17,7 @@
> #include <net/dsa.h>
>
> #define AIROHA_MAX_NUM_GDM_PORTS 4
> +#define AIROHA_MAX_NUM_GDM_DEVS 2
> #define AIROHA_MAX_NUM_QDMA 2
> #define AIROHA_MAX_NUM_IRQ_BANKS 4
> #define AIROHA_MAX_DSA_PORTS 7
> @@ -540,19 +541,20 @@ struct airoha_qdma {
> struct airoha_gdm_dev {
> struct airoha_gdm_port *port;
> struct airoha_qdma *qdma;
> - struct net_device *dev;
> struct airoha_eth *eth;
> + struct net_device *dev;
>
> DECLARE_BITMAP(qos_sq_bmap, AIROHA_NUM_QOS_CHANNELS);
> /* qos stats counters */
> u64 cpu_tx_packets;
> u64 fwd_tx_packets;
> +
> + int nbq;
> };
>
> struct airoha_gdm_port {
> - struct airoha_gdm_dev *dev;
> + struct airoha_gdm_dev *devs[AIROHA_MAX_NUM_GDM_DEVS];
> int id;
> - int nbq;
>
> struct airoha_hw_stats stats;
>
> @@ -588,6 +590,8 @@ struct airoha_eth_soc_data {
> struct {
> int (*get_sport)(struct airoha_gdm_port *port, int nbq);
> u32 (*get_vip_port)(struct airoha_gdm_port *port, int nbq);
> + int (*get_dev_from_sport)(struct airoha_qdma_desc *desc,
> + u16 *port, u16 *dev);
> } ops;
> };
>
> diff --git a/drivers/net/ethernet/airoha/airoha_ppe.c b/drivers/net/ethernet/airoha/airoha_ppe.c
> index 047141b2d6d8..c4086d29d984 100644
> --- a/drivers/net/ethernet/airoha/airoha_ppe.c
> +++ b/drivers/net/ethernet/airoha/airoha_ppe.c
> @@ -169,6 +169,7 @@ static void airoha_ppe_hw_init(struct airoha_ppe *ppe)
>
> for (p = 0; p < ARRAY_SIZE(eth->ports); p++) {
> struct airoha_gdm_port *port = eth->ports[p];
> + int j;
>
> airoha_fe_rmw(eth, REG_PPE_MTU(i, p),
> FP0_EGRESS_MTU_MASK |
> @@ -180,8 +181,16 @@ static void airoha_ppe_hw_init(struct airoha_ppe *ppe)
> if (!port)
> continue;
>
> - airoha_ppe_set_cpu_port(port->dev, i,
> - airoha_get_fe_port(port->dev));
> + for (j = 0; j < ARRAY_SIZE(port->devs); j++) {
> + struct airoha_gdm_dev *dev = port->devs[j];
> + u8 fport;
> +
> + if (!dev)
> + continue;
> +
> + fport = airoha_get_fe_port(dev);
> + airoha_ppe_set_cpu_port(dev, i, fport);
> + }
> }
> }
> }
>
> --
> 2.54.0
>
commenting on sashiko's report:
https://netdev-ai.bots.linux.dev/sashiko/#/patchset/20260511-airoha-eth-multi-serdes-v6-0-c899462c4f75%40kernel.org
- With multiple net_devices now sharing a single GDM3 or GDM4 port (for
example EN7581 GDM3 with PCIE0 nbq=4 and PCIE1 nbq=5), is
airoha_set_gdm2_loopback() still safe to call once per dev through .ndo_init?
- This is not a problem since airoha_set_gdm2_loopback() is run just for WAN
interfaces and we can have a single WAN device.
Regards,
Lorenzo
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^ permalink raw reply
* Re: [PATCH] arm64: dts: allwinner: Cubie A5E: enable SPI flash
From: M.samet Duman @ 2026-05-13 10:58 UTC (permalink / raw)
To: Andre Przywara
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, devicetree, linux-arm-kernel,
linux-sunxi
In-Reply-To: <20260511221741.25888-1-andre.przywara@arm.com>
Looks good.
--
Samet
> 2026. 5. 12. 오전 2:46, Andre Przywara <andre.przywara@arm.com> 작성:
>
> The Cubie A5E board comes with 16MiB of SPI NOR flash.
>
> Enable the SPI0 DT node and describe the configuration.
>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
> ---
> .../boot/dts/allwinner/sun55i-a527-cubie-a5e.dts | 15 +++++++++++++++
> 1 file changed, 15 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts
> index bfdf1728cd14b..7ad22fc85d1fd 100644
> --- a/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts
> +++ b/arch/arm64/boot/dts/allwinner/sun55i-a527-cubie-a5e.dts
> @@ -344,6 +344,21 @@ &r_pio {
> vcc-pm-supply = <®_aldo3>;
> };
>
> +&spi0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&spi0_pc_pins>, <&spi0_cs0_pc_pin>,
> + <&spi0_hold_pc_pin>, <&spi0_wp_pc_pin>;
> + status = "okay";
> +
> + flash@0 {
> + compatible = "winbond,w25q128", "jedec,spi-nor";
> + reg = <0>;
> + spi-max-frequency = <40000000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + };
> +};
> +
> &uart0 {
> pinctrl-names = "default";
> pinctrl-0 = <&uart0_pb_pins>;
> --
> 2.46.4
>
>
^ permalink raw reply
* Re: [PATCH] iio: adc: sun20i-gpadc: support non-contiguous channel lookups
From: Andy Shevchenko @ 2026-05-13 10:53 UTC (permalink / raw)
To: Michal Piekos
Cc: Jonathan Cameron, David Lechner, Nuno Sá, Andy Shevchenko,
Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, linux-iio,
linux-arm-kernel, linux-sunxi, linux-kernel
In-Reply-To: <20260513-fix-sunxi-gpadc-sparse-channels-v1-1-6c21e290bcee@mmpsystems.pl>
On Wed, May 13, 2026 at 11:51:31AM +0200, Michal Piekos wrote:
> Using consumer driver like iio-hwmon which resolve channels thorugh
> io-channels phandles will fail for sparse channels because IIO core
> threats phandle argument as index into channel array.
> eg. <&gpadc 1> will fail if there is only channel@1 specified
>
> Add fwnode_xlate which maps DT phandle to the registered channel whose
.fwnode_xlate()
> chan->channel matches the hardware channel number. It allows sparse
> channel maps to be consumed by drivers like iio-hwmon.
...
> +static int sun20i_gpadc_fwnode_xlate(struct iio_dev *indio_dev,
> + const struct fwnode_reference_args *iiospec)
Broken indentation (I understand the motivation to shift left, but I leave it
to Jonathan on how to proceed with this).
> +{
> + int i;
> +
> + for (i = 0; i < indio_dev->num_channels; i++)
for (unsigned int i = 0; i < indio_dev->num_channels; i++)
> + if (indio_dev->channels[i].channel == iiospec->args[0])
> + return i;
> +
> + return -EINVAL;
> +}
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* [PATCH] ASoC: sun4i-spdif: Use guard() for spin locks
From: phucduc.bui @ 2026-05-13 10:50 UTC (permalink / raw)
To: Mark Brown
Cc: Liam Girdwood, Jaroslav Kysela, Takashi Iwai, Chen-Yu Tsai,
Jernej Skrabec, Samuel Holland, Marcus Cooper, Chen Ni,
linux-sound, linux-sunxi, linux-arm-kernel, linux-kernel,
bui duc phuc
From: bui duc phuc <phucduc.bui@gmail.com>
Clean up the code using guard() for spin locks.
Merely code refactoring, and no behavior change.
Signed-off-by: bui duc phuc <phucduc.bui@gmail.com>
---
sound/soc/sunxi/sun4i-spdif.c | 10 ++--------
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/sound/soc/sunxi/sun4i-spdif.c b/sound/soc/sunxi/sun4i-spdif.c
index c2ec19437cd7..ec00779182db 100644
--- a/sound/soc/sunxi/sun4i-spdif.c
+++ b/sound/soc/sunxi/sun4i-spdif.c
@@ -427,10 +427,9 @@ static int sun4i_spdif_get_status(struct snd_kcontrol *kcontrol,
struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(cpu_dai);
u8 *status = ucontrol->value.iec958.status;
- unsigned long flags;
unsigned int reg;
- spin_lock_irqsave(&host->lock, flags);
+ guard(spinlock_irqsave)(&host->lock);
regmap_read(host->regmap, SUN4I_SPDIF_TXCHSTA0, ®);
@@ -444,8 +443,6 @@ static int sun4i_spdif_get_status(struct snd_kcontrol *kcontrol,
status[4] = reg & 0xff;
status[5] = (reg >> 8) & 0x3;
- spin_unlock_irqrestore(&host->lock, flags);
-
return 0;
}
@@ -455,11 +452,10 @@ static int sun4i_spdif_set_status(struct snd_kcontrol *kcontrol,
struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
struct sun4i_spdif_dev *host = snd_soc_dai_get_drvdata(cpu_dai);
u8 *status = ucontrol->value.iec958.status;
- unsigned long flags;
unsigned int reg;
bool chg0, chg1;
- spin_lock_irqsave(&host->lock, flags);
+ guard(spinlock_irqsave)(&host->lock);
reg = (u32)status[3] << 24;
reg |= (u32)status[2] << 16;
@@ -483,8 +479,6 @@ static int sun4i_spdif_set_status(struct snd_kcontrol *kcontrol,
SUN4I_SPDIF_TXCFG_CHSTMODE |
SUN4I_SPDIF_TXCFG_NONAUDIO, reg);
- spin_unlock_irqrestore(&host->lock, flags);
-
return chg0 || chg1;
}
--
2.43.0
^ permalink raw reply related
* Re: [PATCH v4 1/2] firmware: smccc: coco: Manage arm-smccc platform device and CCA auxiliary drivers
From: Catalin Marinas @ 2026-05-13 10:47 UTC (permalink / raw)
To: Aneesh Kumar K.V
Cc: linux-kernel, linux-arm-kernel, Greg KH, Jeremy Linton,
Jonathan Cameron, Lorenzo Pieralisi, Mark Rutland, Sudeep Holla,
Will Deacon, Suzuki K Poulose
In-Reply-To: <yq5aa4u3u7aq.fsf@kernel.org>
On Wed, May 13, 2026 at 12:26:13PM +0530, Aneesh Kumar K.V wrote:
> Catalin Marinas <catalin.marinas@arm.com> writes:
> > On Mon, Apr 27, 2026 at 11:46:14AM +0530, Aneesh Kumar K.V (Arm) wrote:
> >> diff --git a/arch/arm64/include/asm/rsi.h b/arch/arm64/include/asm/rsi.h
> >> index 88b50d660e85..2d2d363aaaee 100644
> >> --- a/arch/arm64/include/asm/rsi.h
> >> +++ b/arch/arm64/include/asm/rsi.h
> >> @@ -10,7 +10,7 @@
> >> #include <linux/jump_label.h>
> >> #include <asm/rsi_cmds.h>
> >>
> >> -#define RSI_PDEV_NAME "arm-cca-dev"
> >> +#define RSI_DEV_NAME "arm-rsi-dev"
> > [...]
> >> diff --git a/drivers/firmware/smccc/smccc.c b/drivers/firmware/smccc/smccc.c
> >> index bdee057db2fd..fc9b44b7c687 100644
> >> --- a/drivers/firmware/smccc/smccc.c
> >> +++ b/drivers/firmware/smccc/smccc.c
> >> @@ -12,6 +12,8 @@
> >> #include <linux/platform_device.h>
> >> #include <asm/archrandom.h>
> >>
> >> +#include "rmm.h"
> >> +
> >> static u32 smccc_version = ARM_SMCCC_VERSION_1_0;
> >> static enum arm_smccc_conduit smccc_conduit = SMCCC_CONDUIT_NONE;
> >>
> >> @@ -85,6 +87,18 @@ static int __init smccc_devices_init(void)
> >> {
> >> struct platform_device *pdev;
> >>
> >> + pdev = platform_device_register_simple("arm-smccc",
> >> + PLATFORM_DEVID_NONE, NULL, 0);
> >> + if (IS_ERR(pdev)) {
> >> + pr_err("arm-smccc: could not register device: %ld\n", PTR_ERR(pdev));
> >> + } else {
> >> + /*
> >> + * Register the RMI and RSI devices only when firmware exposes
> >> + * the required SMCCC function IDs at a supported revision.
> >> + */
> >> + register_rsi_device(pdev);
> >> + }
> >
> > So as per the cover letter, instead of "arm-cca-dev" as a platform
> > device, we get "arm-smccc" as a platform device with an auxiliary
> > "arm-rsi-dev" child device. This does not get rid of the platform
> > device, it just creates a synthetic platform device to represent the
> > SMCCC firmware interface.
> >
> > Looking at the earlier discussion, I think this is what Greg/Jason were
> > suggesting, except that we do not currently have an SMCCC platform
> > device:
> >
> > https://lore.kernel.org/all/2025101534-frosty-shank-00b1@gregkh/
> >
> > If we go this route, shouldn't the platform device above be created only
> > if !SMCCC_CONDUIT_NONE?
> >
>
> register_rsi_device() does check for
>
> if (arm_smccc_1_1_get_conduit() != SMCCC_CONDUIT_SMC)
> return;
Yes but I meant for the "arm-smccc" platform device, not the rsi one.
You don't want it create if SMCCC_CONDUIT_NONE.
--
Catalin
^ permalink raw reply
* Re: [PATCH] drivers: altera_edac: Guard SDRAM irq2 retrieval for Arria10 only
From: Dinh Nguyen @ 2026-05-13 10:45 UTC (permalink / raw)
To: Nazle Asmade, Muhammad Nazim Amirul, bp@alien8.de,
tony.luck@intel.com
Cc: linux-edac@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
In-Reply-To: <4f80ef77-a38b-4652-a1f1-1bea3e88de74@altera.com>
On 5/12/26 06:51, Nazle Asmade, Muhammad Nazim Amirul wrote:
> On 12/5/2026 7:25 pm, Dinh Nguyen wrote:
>>
>>
>> On 5/11/26 20:37, Nazle Asmade, Muhammad Nazim Amirul wrote:
>>> On 11/5/2026 7:54 pm, Dinh Nguyen wrote:
>>>>
>>>>
>>>> On 5/8/26 02:52, muhammad.nazim.amirul.nazle.asmade@altera.com wrote:
>>>>> From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
>>>>>
>>>>> Guard the irq2 retrieval with an of_machine_is_compatible() check so
>>>>> that platform_get_irq(pdev, 1) is only called on Arria10 platforms.
>>>>>
>>>>> Signed-off-by: Nazim Amirul
>>>>> <muhammad.nazim.amirul.nazle.asmade@altera.com>
>>>>> Signed-off-by: Niravkumar L Rabara <nirav.rabara@altera.com>
>>>>> ---
>>>>> drivers/edac/altera_edac.c | 3 ++-
>>>>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>>>>
>>>>> diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
>>>>> index 4edd2088c2db..b30302198cd4 100644
>>>>> --- a/drivers/edac/altera_edac.c
>>>>> +++ b/drivers/edac/altera_edac.c
>>>>> @@ -348,7 +348,8 @@ static int altr_sdram_probe(struct platform_device
>>>>> *pdev)
>>>>> }
>>>>> /* Arria10 has a 2nd IRQ */
>>>>> - irq2 = platform_get_irq(pdev, 1);
>>>>> + if (of_machine_is_compatible("altr,socfpga-arria10"))
>>>>> + irq2 = platform_get_irq(pdev, 1);
>>>>> layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
>>>>> layers[0].size = 1;
>>>>
>>>> Why? We already switch on arria10 later in the same function.
>>>>
>>>> Sorry, but NAK.
>>>>
>>>> Dinh
>>> This driver were used by cyclone5 and arria10. Cyclone5 only has one
>>> interrupt whereby arria10 has 2 interrupt. That is the reason why the
>>> interrupt was guard by (of_machine_is_compatible("altr,socfpga-arria10"))
>>>
>>
>> Yes, but look at line 397,
>>
>> /* Only the Arria10 has separate IRQs */
>> if (of_machine_is_compatible("altr,socfpga-arria10")) {
>> /* Arria10 specific initialization */
>>
>> Dinh
>>
>>
> Hi Dinh, That is true, but the one that we looking at now is at line 352
> which enabling the second interrupt and it is not required by cyclone5.
> Perhaps are you saying we should move the irq2 at line 352 under this
> line 397?
Yes, that would be fine.
Dinh
^ permalink raw reply
* [PATCH v2 3/3] arm64: dts: amlogic: t7: khadas-vim4: add PWM-driven status LED
From: Ronald Claveau via B4 Relay @ 2026-05-13 10:43 UTC (permalink / raw)
To: Neil Armstrong, Kevin Hilman, Jerome Brunet, Martin Blumenstingl,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-kernel, linux-amlogic, devicetree, linux-kernel,
Ronald Claveau
In-Reply-To: <20260513-add-kvim4-sysled-v2-0-3ec9779e8875@aliel.fr>
From: Ronald Claveau <linux-kernel-dev@aliel.fr>
The VIM4 board exposes a status LED wired to the PWM_AO_C_D output.
Enable the pwm_ao_cd controller with its pinmux, and declare a
pwm-leds node with a heartbeat trigger.
Signed-off-by: Ronald Claveau <linux-kernel-dev@aliel.fr>
---
.../boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts b/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts
index fd1b983354a01..c41525a34b721 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts
+++ b/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts
@@ -53,6 +53,16 @@ dc_in: regulator-dc-in {
regulator-always-on;
};
+ pwm-leds {
+ compatible = "pwm-leds";
+
+ status {
+ linux,default-trigger="heartbeat";
+ max-brightness = <255>;
+ pwms = <&pwm_ao_cd 0 30040 0>;
+ };
+ };
+
sd_3v3: regulator-sdcard-3v3 {
compatible = "regulator-fixed";
regulator-name = "SD_3V3";
@@ -163,6 +173,12 @@ &pwm_ab {
pinctrl-names = "default";
};
+&pwm_ao_cd {
+ status = "okay";
+ pinctrl-0 = <&pwm_ao_c_d_pins>;
+ pinctrl-names = "default";
+};
+
/* SDIO */
&sd_emmc_a {
status = "okay";
--
2.49.0
^ permalink raw reply related
* [PATCH v2 1/3] arm64: dts: amlogic: t7: Fix pwm_ao_c pinmux definitions
From: Ronald Claveau via B4 Relay @ 2026-05-13 10:43 UTC (permalink / raw)
To: Neil Armstrong, Kevin Hilman, Jerome Brunet, Martin Blumenstingl,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-kernel, linux-amlogic, devicetree, linux-kernel,
Ronald Claveau
In-Reply-To: <20260513-add-kvim4-sysled-v2-0-3ec9779e8875@aliel.fr>
From: Ronald Claveau <linux-kernel-dev@aliel.fr>
The pwm_ao_c pin node was incomplete: it was missing the group name
suffix, conflating two distinct pin groups (pwm_ao_c_d and pwm_ao_c_e)
into a single, ambiguous entry.
Split the node into two separate pinmux entries:
- pwm_ao_c_d_pins: uses group "pwm_ao_c_d"
- pwm_ao_c_e_pins: uses group "pwm_ao_c_e"
Both alternate pins are not yet referenced by any peripheral node,
so this has no functional impact on existing boards. No backport needed.
Fixes: ee6e05a49b93 ("arm64: dts: amlogic: t7: Add PWM pinctrl nodes")
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Ronald Claveau <linux-kernel-dev@aliel.fr>
---
arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
index 7fe72c94ed623..62f6b9baad28b 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
@@ -400,9 +400,17 @@ mux {
};
};
- pwm_ao_c_pins: pwm-ao-c {
+ pwm_ao_c_d_pins: pwm-ao-c-d {
mux {
- groups = "pwm_ao_c";
+ groups = "pwm_ao_c_d";
+ function = "pwm_ao_c";
+ bias-disable;
+ };
+ };
+
+ pwm_ao_c_e_pins: pwm-ao-c-e {
+ mux {
+ groups = "pwm_ao_c_e";
function = "pwm_ao_c";
bias-disable;
};
--
2.49.0
^ permalink raw reply related
* [PATCH v2 2/3] arm64: dts: amlogic: t7: khadas-vim4: reorder root node
From: Ronald Claveau via B4 Relay @ 2026-05-13 10:43 UTC (permalink / raw)
To: Neil Armstrong, Kevin Hilman, Jerome Brunet, Martin Blumenstingl,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-kernel, linux-amlogic, devicetree, linux-kernel,
Ronald Claveau
In-Reply-To: <20260513-add-kvim4-sysled-v2-0-3ec9779e8875@aliel.fr>
From: Ronald Claveau <linux-kernel-dev@aliel.fr>
Move the xtal-clk node to restore alphabetical ordering.
Signed-off-by: Ronald Claveau <linux-kernel-dev@aliel.fr>
---
.../boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts b/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts
index 69d6118ba57e7..fd1b983354a01 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts
+++ b/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts
@@ -45,13 +45,6 @@ secmon_reserved_bl32: secmon@5300000 {
};
};
- xtal: xtal-clk {
- compatible = "fixed-clock";
- clock-frequency = <24000000>;
- clock-output-names = "xtal";
- #clock-cells = <0>;
- };
-
dc_in: regulator-dc-in {
compatible = "regulator-fixed";
regulator-name = "DC_IN";
@@ -155,6 +148,13 @@ wifi32k: wifi32k {
clock-frequency = <32768>;
pwms = <&pwm_ab 0 30518 0>;
};
+
+ xtal: xtal-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "xtal";
+ #clock-cells = <0>;
+ };
};
&pwm_ab {
--
2.49.0
^ permalink raw reply related
* [PATCH v2 0/3] Khadas VIM4 PWM status LED support
From: Ronald Claveau via B4 Relay @ 2026-05-13 10:43 UTC (permalink / raw)
To: Neil Armstrong, Kevin Hilman, Jerome Brunet, Martin Blumenstingl,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-kernel, linux-amlogic, devicetree, linux-kernel,
Ronald Claveau
This series adds support for the PWM-driven status LED on the Khadas
VIM4 board (Amlogic T7).
The VIM4 exposes a heartbeat LED wired to the PWM_AO_C output, routed
through pin group pwm_ao_c_d. Before wiring it up in the board DTS,
the SoC pinmux definitions had to be corrected: the original
pwm_ao_c node was conflating two distinct pin groups (pwm_ao_c_d and
pwm_ao_c_e) into a single ambiguous entry.
Patch 1 fixes the pwm_ao_c pinmux entries in the T7 DTSI by splitting
them into two properly named nodes. Neither alternate is in use yet,
so there is no functional impact on existing boards.
Patch 2 moves the xtal-clk node to restore alphabetical ordering among
root node children.
Patch 3 enables the pwm_ao_cd controller on the VIM4 and adds a
pwm-leds node with a heartbeat trigger.
Signed-off-by: Ronald Claveau <linux-kernel-dev@aliel.fr>
---
Changes in v2:
- PATCH 2-3: Create a new patch specific to the reordering action.
According to Neil's review.
- Link to v1: https://lore.kernel.org/r/20260512-add-kvim4-sysled-v1-0-7178719a43e7@aliel.fr
---
Ronald Claveau (3):
arm64: dts: amlogic: t7: Fix pwm_ao_c pinmux definitions
arm64: dts: amlogic: t7: khadas-vim4: reorder root node
arm64: dts: amlogic: t7: khadas-vim4: add PWM-driven status LED
.../dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts | 30 +++++++++++++++++-----
arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi | 12 +++++++--
2 files changed, 33 insertions(+), 9 deletions(-)
---
base-commit: 31f32e8cdf59291e467250dfc57d1a8c718f63d2
change-id: 20260512-add-kvim4-sysled-8cc159524561
Best regards,
--
Ronald Claveau <linux-kernel-dev@aliel.fr>
^ permalink raw reply
* [PATCH 4/4] ASoC: stm: stm32_spdifrx: Use guard() for spin locks
From: phucduc.bui @ 2026-05-13 10:43 UTC (permalink / raw)
To: Olivier Moysan, Arnaud Pouliquen, Mark Brown
Cc: Liam Girdwood, Jaroslav Kysela, Takashi Iwai, Maxime Coquelin,
Alexandre Torgue, linux-sound, linux-stm32, linux-arm-kernel,
linux-kernel, bui duc phuc
In-Reply-To: <20260513104329.81592-1-phucduc.bui@gmail.com>
From: bui duc phuc <phucduc.bui@gmail.com>
Clean up the code using guard() for spin locks.
Merely code refactoring, and no behavior change.
Signed-off-by: bui duc phuc <phucduc.bui@gmail.com>
---
sound/soc/stm/stm32_spdifrx.c | 44 +++++++++++++----------------------
1 file changed, 16 insertions(+), 28 deletions(-)
diff --git a/sound/soc/stm/stm32_spdifrx.c b/sound/soc/stm/stm32_spdifrx.c
index 57b711c44278..2f83ca989e68 100644
--- a/sound/soc/stm/stm32_spdifrx.c
+++ b/sound/soc/stm/stm32_spdifrx.c
@@ -322,7 +322,6 @@ static void stm32_spdifrx_dma_ctrl_stop(struct stm32_spdifrx_data *spdifrx)
static int stm32_spdifrx_start_sync(struct stm32_spdifrx_data *spdifrx)
{
int cr, cr_mask, imr, ret;
- unsigned long flags;
/* Enable IRQs */
imr = SPDIFRX_IMR_IFEIE | SPDIFRX_IMR_SYNCDIE | SPDIFRX_IMR_PERRIE;
@@ -330,7 +329,7 @@ static int stm32_spdifrx_start_sync(struct stm32_spdifrx_data *spdifrx)
if (ret)
return ret;
- spin_lock_irqsave(&spdifrx->lock, flags);
+ guard(spinlock_irqsave)(&spdifrx->lock);
spdifrx->refcount++;
@@ -365,22 +364,17 @@ static int stm32_spdifrx_start_sync(struct stm32_spdifrx_data *spdifrx)
"Failed to start synchronization\n");
}
- spin_unlock_irqrestore(&spdifrx->lock, flags);
-
return ret;
}
static void stm32_spdifrx_stop(struct stm32_spdifrx_data *spdifrx)
{
int cr, cr_mask, reg;
- unsigned long flags;
- spin_lock_irqsave(&spdifrx->lock, flags);
+ guard(spinlock_irqsave)(&spdifrx->lock);
- if (--spdifrx->refcount) {
- spin_unlock_irqrestore(&spdifrx->lock, flags);
+ if (--spdifrx->refcount)
return;
- }
cr = SPDIFRX_CR_SPDIFENSET(SPDIFRX_SPDIFEN_DISABLE);
cr_mask = SPDIFRX_CR_SPDIFEN_MASK | SPDIFRX_CR_RXDMAEN;
@@ -396,8 +390,6 @@ static void stm32_spdifrx_stop(struct stm32_spdifrx_data *spdifrx)
/* dummy read to clear CSRNE and RXNE in status register */
regmap_read(spdifrx->regmap, STM32_SPDIFRX_DR, ®);
regmap_read(spdifrx->regmap, STM32_SPDIFRX_CSR, ®);
-
- spin_unlock_irqrestore(&spdifrx->lock, flags);
}
static int stm32_spdifrx_dma_ctrl_register(struct device *dev,
@@ -744,19 +736,19 @@ static irqreturn_t stm32_spdifrx_isr(int irq, void *devid)
return IRQ_HANDLED;
}
- spin_lock(&spdifrx->irq_lock);
- if (spdifrx->substream)
- snd_pcm_stop(spdifrx->substream,
- SNDRV_PCM_STATE_DISCONNECTED);
- spin_unlock(&spdifrx->irq_lock);
+ scoped_guard(spinlock, &spdifrx->irq_lock) {
+ if (spdifrx->substream)
+ snd_pcm_stop(spdifrx->substream,
+ SNDRV_PCM_STATE_DISCONNECTED);
+ }
return IRQ_HANDLED;
}
- spin_lock(&spdifrx->irq_lock);
- if (err_xrun && spdifrx->substream)
- snd_pcm_stop_xrun(spdifrx->substream);
- spin_unlock(&spdifrx->irq_lock);
+ scoped_guard(spinlock, &spdifrx->irq_lock) {
+ if (err_xrun && spdifrx->substream)
+ snd_pcm_stop_xrun(spdifrx->substream);
+ }
return IRQ_HANDLED;
}
@@ -765,12 +757,10 @@ static int stm32_spdifrx_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *cpu_dai)
{
struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
- unsigned long flags;
int ret;
- spin_lock_irqsave(&spdifrx->irq_lock, flags);
- spdifrx->substream = substream;
- spin_unlock_irqrestore(&spdifrx->irq_lock, flags);
+ scoped_guard(spinlock_irqsave, &spdifrx->irq_lock)
+ spdifrx->substream = substream;
ret = clk_prepare_enable(spdifrx->kclk);
if (ret)
@@ -846,11 +836,9 @@ static void stm32_spdifrx_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *cpu_dai)
{
struct stm32_spdifrx_data *spdifrx = snd_soc_dai_get_drvdata(cpu_dai);
- unsigned long flags;
- spin_lock_irqsave(&spdifrx->irq_lock, flags);
- spdifrx->substream = NULL;
- spin_unlock_irqrestore(&spdifrx->irq_lock, flags);
+ scoped_guard(spinlock_irqsave, &spdifrx->irq_lock)
+ spdifrx->substream = NULL;
clk_disable_unprepare(spdifrx->kclk);
}
--
2.43.0
^ permalink raw reply related
* [PATCH 3/4] ASoC: stm: stm32_sai_sub: Use guard() for mutex & spin locks
From: phucduc.bui @ 2026-05-13 10:43 UTC (permalink / raw)
To: Olivier Moysan, Arnaud Pouliquen, Mark Brown
Cc: Liam Girdwood, Jaroslav Kysela, Takashi Iwai, Maxime Coquelin,
Alexandre Torgue, linux-sound, linux-stm32, linux-arm-kernel,
linux-kernel, bui duc phuc
In-Reply-To: <20260513104329.81592-1-phucduc.bui@gmail.com>
From: bui duc phuc <phucduc.bui@gmail.com>
Clean up the code using guard() for mutex & spin locks.
Merely code refactoring, and no behavior change.
Signed-off-by: bui duc phuc <phucduc.bui@gmail.com>
---
sound/soc/stm/stm32_sai_sub.c | 29 +++++++++++------------------
1 file changed, 11 insertions(+), 18 deletions(-)
diff --git a/sound/soc/stm/stm32_sai_sub.c b/sound/soc/stm/stm32_sai_sub.c
index 3e82fa90e719..ea9e8bddd63f 100644
--- a/sound/soc/stm/stm32_sai_sub.c
+++ b/sound/soc/stm/stm32_sai_sub.c
@@ -280,9 +280,8 @@ static int snd_pcm_iec958_get(struct snd_kcontrol *kcontrol,
{
struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol);
- mutex_lock(&sai->ctrl_lock);
+ guard(mutex)(&sai->ctrl_lock);
memcpy(uctl->value.iec958.status, sai->iec958.status, 4);
- mutex_unlock(&sai->ctrl_lock);
return 0;
}
@@ -292,9 +291,8 @@ static int snd_pcm_iec958_put(struct snd_kcontrol *kcontrol,
{
struct stm32_sai_sub_data *sai = snd_kcontrol_chip(kcontrol);
- mutex_lock(&sai->ctrl_lock);
+ guard(mutex)(&sai->ctrl_lock);
memcpy(sai->iec958.status, uctl->value.iec958.status, 4);
- mutex_unlock(&sai->ctrl_lock);
return 0;
}
@@ -658,10 +656,10 @@ static irqreturn_t stm32_sai_isr(int irq, void *devid)
status = SNDRV_PCM_STATE_XRUN;
}
- spin_lock(&sai->irq_lock);
- if (status != SNDRV_PCM_STATE_RUNNING && sai->substream)
- snd_pcm_stop_xrun(sai->substream);
- spin_unlock(&sai->irq_lock);
+ scoped_guard(spinlock, &sai->irq_lock) {
+ if (status != SNDRV_PCM_STATE_RUNNING && sai->substream)
+ snd_pcm_stop_xrun(sai->substream);
+ }
return IRQ_HANDLED;
}
@@ -894,11 +892,9 @@ static int stm32_sai_startup(struct snd_pcm_substream *substream,
{
struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
int imr, cr2, ret;
- unsigned long flags;
- spin_lock_irqsave(&sai->irq_lock, flags);
- sai->substream = substream;
- spin_unlock_irqrestore(&sai->irq_lock, flags);
+ scoped_guard(spinlock_irqsave, &sai->irq_lock)
+ sai->substream = substream;
if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
snd_pcm_hw_constraint_mask64(substream->runtime,
@@ -1083,7 +1079,7 @@ static void stm32_sai_set_iec958_status(struct stm32_sai_sub_data *sai,
return;
/* Force the sample rate according to runtime rate */
- mutex_lock(&sai->ctrl_lock);
+ guard(mutex)(&sai->ctrl_lock);
switch (runtime->rate) {
case 22050:
sai->iec958.status[3] = IEC958_AES3_CON_FS_22050;
@@ -1116,7 +1112,6 @@ static void stm32_sai_set_iec958_status(struct stm32_sai_sub_data *sai,
sai->iec958.status[3] = IEC958_AES3_CON_FS_NOTID;
break;
}
- mutex_unlock(&sai->ctrl_lock);
}
static int stm32_sai_configure_clock(struct snd_soc_dai *cpu_dai,
@@ -1284,7 +1279,6 @@ static void stm32_sai_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *cpu_dai)
{
struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
- unsigned long flags;
stm32_sai_sub_reg_up(sai, STM_SAI_IMR_REGX, SAI_XIMR_MASK, 0);
@@ -1298,9 +1292,8 @@ static void stm32_sai_shutdown(struct snd_pcm_substream *substream,
if (!sai->sai_mclk && sai->put_sai_ck_rate)
sai->put_sai_ck_rate(sai);
- spin_lock_irqsave(&sai->irq_lock, flags);
- sai->substream = NULL;
- spin_unlock_irqrestore(&sai->irq_lock, flags);
+ scoped_guard(spinlock_irqsave, &sai->irq_lock)
+ sai->substream = NULL;
}
static int stm32_sai_pcm_new(struct snd_soc_pcm_runtime *rtd,
--
2.43.0
^ permalink raw reply related
* [PATCH 2/4] ASoC: stm: stm32_i2s: Use guard() for spin locks
From: phucduc.bui @ 2026-05-13 10:43 UTC (permalink / raw)
To: Olivier Moysan, Arnaud Pouliquen, Mark Brown
Cc: Liam Girdwood, Jaroslav Kysela, Takashi Iwai, Maxime Coquelin,
Alexandre Torgue, linux-sound, linux-stm32, linux-arm-kernel,
linux-kernel, bui duc phuc
In-Reply-To: <20260513104329.81592-1-phucduc.bui@gmail.com>
From: bui duc phuc <phucduc.bui@gmail.com>
Clean up the code using guard() for spin locks.
Merely code refactoring, and no behavior change.
Signed-off-by: bui duc phuc <phucduc.bui@gmail.com>
---
sound/soc/stm/stm32_i2s.c | 67 ++++++++++++++++++---------------------
1 file changed, 30 insertions(+), 37 deletions(-)
diff --git a/sound/soc/stm/stm32_i2s.c b/sound/soc/stm/stm32_i2s.c
index 6ca21780f21d..4fddb7ecd7fd 100644
--- a/sound/soc/stm/stm32_i2s.c
+++ b/sound/soc/stm/stm32_i2s.c
@@ -615,10 +615,10 @@ static irqreturn_t stm32_i2s_isr(int irq, void *devid)
if (flags & I2S_SR_TIFRE)
dev_dbg(&pdev->dev, "Frame error\n");
- spin_lock(&i2s->irq_lock);
- if (err && i2s->substream)
- snd_pcm_stop_xrun(i2s->substream);
- spin_unlock(&i2s->irq_lock);
+ scoped_guard(spinlock, &i2s->irq_lock) {
+ if (err && i2s->substream)
+ snd_pcm_stop_xrun(i2s->substream);
+ }
return IRQ_HANDLED;
}
@@ -905,12 +905,10 @@ static int stm32_i2s_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *cpu_dai)
{
struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
- unsigned long flags;
int ret;
- spin_lock_irqsave(&i2s->irq_lock, flags);
- i2s->substream = substream;
- spin_unlock_irqrestore(&i2s->irq_lock, flags);
+ scoped_guard(spinlock_irqsave, &i2s->irq_lock)
+ i2s->substream = substream;
if ((i2s->fmt & SND_SOC_DAIFMT_FORMAT_MASK) != SND_SOC_DAIFMT_DSP_A)
snd_pcm_hw_constraint_single(substream->runtime,
@@ -982,19 +980,19 @@ static int stm32_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
regmap_write_bits(i2s->regmap, STM32_I2S_IFCR_REG,
I2S_IFCR_MASK, I2S_IFCR_MASK);
- spin_lock(&i2s->lock_fd);
- i2s->refcount++;
- if (playback_flg) {
- ier = I2S_IER_UDRIE;
- } else {
- ier = I2S_IER_OVRIE;
-
- if (STM32_I2S_IS_MASTER(i2s) && i2s->refcount == 1)
- /* dummy write to gate bus clocks */
- regmap_write(i2s->regmap,
- STM32_I2S_TXDR_REG, 0);
+ scoped_guard(spinlock, &i2s->lock_fd) {
+ i2s->refcount++;
+ if (playback_flg) {
+ ier = I2S_IER_UDRIE;
+ } else {
+ ier = I2S_IER_OVRIE;
+
+ if (STM32_I2S_IS_MASTER(i2s) && i2s->refcount == 1)
+ /* dummy write to gate bus clocks */
+ regmap_write(i2s->regmap,
+ STM32_I2S_TXDR_REG, 0);
+ }
}
- spin_unlock(&i2s->lock_fd);
if (STM32_I2S_IS_SLAVE(i2s))
ier |= I2S_IER_TIFREIE;
@@ -1016,21 +1014,18 @@ static int stm32_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
I2S_IER_OVRIE,
(unsigned int)~I2S_IER_OVRIE);
- spin_lock(&i2s->lock_fd);
- i2s->refcount--;
- if (i2s->refcount) {
- spin_unlock(&i2s->lock_fd);
- break;
- }
+ scoped_guard(spinlock, &i2s->lock_fd) {
+ i2s->refcount--;
+ if (i2s->refcount)
+ break;
- ret = regmap_update_bits(i2s->regmap, STM32_I2S_CR1_REG,
- I2S_CR1_SPE, 0);
- if (ret < 0) {
- dev_err(cpu_dai->dev, "Error %d disabling I2S\n", ret);
- spin_unlock(&i2s->lock_fd);
- return ret;
+ ret = regmap_update_bits(i2s->regmap, STM32_I2S_CR1_REG,
+ I2S_CR1_SPE, 0);
+ if (ret < 0) {
+ dev_err(cpu_dai->dev, "Error %d disabling I2S\n", ret);
+ return ret;
+ }
}
- spin_unlock(&i2s->lock_fd);
cfg1_mask = I2S_CFG1_RXDMAEN | I2S_CFG1_TXDMAEN;
regmap_update_bits(i2s->regmap, STM32_I2S_CFG1_REG,
@@ -1047,7 +1042,6 @@ static void stm32_i2s_shutdown(struct snd_pcm_substream *substream,
struct snd_soc_dai *cpu_dai)
{
struct stm32_i2s_data *i2s = snd_soc_dai_get_drvdata(cpu_dai);
- unsigned long flags;
clk_disable_unprepare(i2s->i2sclk);
@@ -1059,9 +1053,8 @@ static void stm32_i2s_shutdown(struct snd_pcm_substream *substream,
if (!i2s->i2smclk && i2s->put_i2s_clk_rate)
i2s->put_i2s_clk_rate(i2s);
- spin_lock_irqsave(&i2s->irq_lock, flags);
- i2s->substream = NULL;
- spin_unlock_irqrestore(&i2s->irq_lock, flags);
+ scoped_guard(spinlock_irqsave, &i2s->irq_lock)
+ i2s->substream = NULL;
}
static int stm32_i2s_dai_probe(struct snd_soc_dai *cpu_dai)
--
2.43.0
^ permalink raw reply related
* [PATCH 1/4] ASoC: stm: stm32_adfsdm: Use guard() for mutex locks
From: phucduc.bui @ 2026-05-13 10:43 UTC (permalink / raw)
To: Olivier Moysan, Arnaud Pouliquen, Mark Brown
Cc: Liam Girdwood, Jaroslav Kysela, Takashi Iwai, Maxime Coquelin,
Alexandre Torgue, linux-sound, linux-stm32, linux-arm-kernel,
linux-kernel, bui duc phuc
In-Reply-To: <20260513104329.81592-1-phucduc.bui@gmail.com>
From: bui duc phuc <phucduc.bui@gmail.com>
Clean up the code using guard() for mutex locks.
Merely code refactoring, and no behavior change.
Signed-off-by: bui duc phuc <phucduc.bui@gmail.com>
---
sound/soc/stm/stm32_adfsdm.c | 10 +++-------
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/sound/soc/stm/stm32_adfsdm.c b/sound/soc/stm/stm32_adfsdm.c
index 0f6d32814c22..a585cb9fc011 100644
--- a/sound/soc/stm/stm32_adfsdm.c
+++ b/sound/soc/stm/stm32_adfsdm.c
@@ -62,12 +62,11 @@ static void stm32_adfsdm_shutdown(struct snd_pcm_substream *substream,
{
struct stm32_adfsdm_priv *priv = snd_soc_dai_get_drvdata(dai);
- mutex_lock(&priv->lock);
+ guard(mutex)(&priv->lock);
if (priv->iio_active) {
iio_channel_stop_all_cb(priv->iio_cb);
priv->iio_active = false;
}
- mutex_unlock(&priv->lock);
}
static int stm32_adfsdm_dai_prepare(struct snd_pcm_substream *substream,
@@ -76,7 +75,7 @@ static int stm32_adfsdm_dai_prepare(struct snd_pcm_substream *substream,
struct stm32_adfsdm_priv *priv = snd_soc_dai_get_drvdata(dai);
int ret;
- mutex_lock(&priv->lock);
+ guard(mutex)(&priv->lock);
if (priv->iio_active) {
iio_channel_stop_all_cb(priv->iio_cb);
priv->iio_active = false;
@@ -88,7 +87,7 @@ static int stm32_adfsdm_dai_prepare(struct snd_pcm_substream *substream,
if (ret < 0) {
dev_err(dai->dev, "%s: Failed to set %d sampling rate\n",
__func__, substream->runtime->rate);
- goto out;
+ return ret;
}
if (!priv->iio_active) {
@@ -100,9 +99,6 @@ static int stm32_adfsdm_dai_prepare(struct snd_pcm_substream *substream,
__func__, ret);
}
-out:
- mutex_unlock(&priv->lock);
-
return ret;
}
--
2.43.0
^ permalink raw reply related
* [PATCH 0/4] ASoC: stm: Use guard() for mutex & spin locks
From: phucduc.bui @ 2026-05-13 10:43 UTC (permalink / raw)
To: Olivier Moysan, Arnaud Pouliquen, Mark Brown
Cc: Liam Girdwood, Jaroslav Kysela, Takashi Iwai, Maxime Coquelin,
Alexandre Torgue, linux-sound, linux-stm32, linux-arm-kernel,
linux-kernel, bui duc phuc
From: bui duc phuc <phucduc.bui@gmail.com>
Hi all,
This series converts mutex and spinlock handling in the STM drivers
to use guard() helpers.
The changes are code cleanup only and should have no functional impact.
Best regards,
Phuc
bui duc phuc (4):
ASoC: stm: stm32_adfsdm: Use guard() for mutex locks
ASoC: stm: stm32_i2s: Use guard() for spin locks
ASoC: stm: stm32_sai_sub: Use guard() for mutex & spin locks
ASoC: stm: stm32_spdifrx: Use guard() for spin locks
sound/soc/stm/stm32_adfsdm.c | 10 ++----
sound/soc/stm/stm32_i2s.c | 67 ++++++++++++++++-------------------
sound/soc/stm/stm32_sai_sub.c | 29 ++++++---------
sound/soc/stm/stm32_spdifrx.c | 44 +++++++++--------------
4 files changed, 60 insertions(+), 90 deletions(-)
--
2.43.0
^ permalink raw reply
* Re: [PATCH] clk: rockchip: allow COMPILE_TEST builds
From: Heiko Stuebner @ 2026-05-13 10:37 UTC (permalink / raw)
To: linux-rockchip, Rosen Penev
Cc: Heiko Stuebner, Michael Turquette, Stephen Boyd, Brian Masney,
Nathan Chancellor, Nick Desaulniers, Bill Wendling, Justin Stitt,
linux-clk, linux-kernel, linux-arm-kernel, llvm
In-Reply-To: <20260509003602.956186-1-rosenp@gmail.com>
On Fri, 08 May 2026 17:36:02 -0700, Rosen Penev wrote:
> COMMON_CLK_ROCKCHIP already gates the Rockchip clock objects inside the
> Rockchip clock Makefile. Allow selecting it for COMPILE_TEST and use it
> for the parent Makefile descent instead of ARCH_ROCKCHIP.
>
> The per-SoC Rockchip clock symbols already have COMPILE_TEST dependencies,
> so this exposes the existing build coverage to other architectures without
> selecting the Rockchip platform.
>
> [...]
Applied, thanks!
[1/1] clk: rockchip: allow COMPILE_TEST builds
commit: 7edfb7fb58ee058298e18fde76a6077ef17d19d8
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
^ permalink raw reply
* Re: [PATCH v4 2/2] coco: guest: arm64: Drop dummy RSI platform device stub
From: Greg KH @ 2026-05-13 9:59 UTC (permalink / raw)
To: Aneesh Kumar K.V
Cc: Catalin Marinas, linux-kernel, linux-arm-kernel, Jeremy Linton,
Jonathan Cameron, Lorenzo Pieralisi, Mark Rutland, Sudeep Holla,
Will Deacon, Jonathan Cameron, Suzuki K Poulose
In-Reply-To: <yq5a4ikbu1w2.fsf@kernel.org>
On Wed, May 13, 2026 at 02:23:01PM +0530, Aneesh Kumar K.V wrote:
> Greg KH <gregkh@linuxfoundation.org> writes:
>
> > On Wed, May 13, 2026 at 12:28:12PM +0530, Aneesh Kumar K.V wrote:
> >> Catalin Marinas <catalin.marinas@arm.com> writes:
> >>
> >> > + Suzuki again
> >> >
> >> > On Mon, Apr 27, 2026 at 11:46:15AM +0530, Aneesh Kumar K.V (Arm) wrote:
> >> >> The SMCCC firmware driver now creates the `arm-smccc` platform device
> >> >> and also creates the CCA auxiliary devices once the RSI ABI is
> >> >> discovered. This makes the arch-specific arm64_create_dummy_rsi_dev()
> >> >> helper redundant. Remove the arm-cca-dev platform device registration
> >> >> and let the SMCCC probe manage the RSI device.
> >> >>
> >> >> systemd match on platform:arm-cca-dev for confidential vm detection [1].
> >> >> Losing the platform device registration can break that. Keeping this
> >> >> removal in its own change makes it easy to revert if that regression
> >> >> blocks the rollout.
> >> >>
> >> >> [1] https://lore.kernel.org/all/4a7d84b2-2ec4-4773-a2d5-7b63d5c683cf@arm.com
> >> >
> >> > I wouldn't merge this now given that systemd checks this file. Could we
> >> > have a symbolic link instead for some time until systemd eventually gets
> >> > updated (years?).
> >> >
> >>
> >> I’ll add this in the next revision.
> >>
> >> static int create_rsi_compat_link(struct device *target_dev)
> >> {
> >> struct kobject *platform_kobj;
> >> /*
> >> * target_dev is:
> >> * /sys/devices/platform/arm-smccc/arm_cca_guest.arm-rsi-dev.0
> >> * Create compat link /sys/devices/platform/arm-cca-dev
> >> */
> >> platform_kobj = target_dev->kobj.parent->parent;
> >
> > What? That is crazy, you don't know that is always going to be ok.
> >
> >> return sysfs_create_link(platform_kobj,
> >> &target_dev->kobj,
> >> "arm-cca-dev");
> >
> > No, don't do that, if a driver calls a sysfs* function, something is
> > almost always wrong. Don't be making random sysfs symlinks please.
> >
>
> Sure, but could you explain why this is wrong? Below is the full version
> of the updated patch.
>
> coco: guest: arm64 Replace RSI platform device with compat symlink
>
> The SMCCC firmware driver now creates the arm-smccc platform device and
> registers the RSI device as an auxiliary device once the RSI ABI has been
> discovered. This makes the arch-specific arm64 arm-cca-dev platform device
> redundant.
>
> Remove the arm64 platform device stub and let the SMCCC core manage RSI
> device creation.
>
> This changes the real device location from the old platform device path to:
>
> /sys/devices/platform/arm-smccc/arm_cca_guest.arm-rsi-dev.0
>
> Keep userspace compatibility by creating a sysfs symlink at the old path:
>
> /sys/devices/platform/arm-cca-dev
>
> A Debian Code Search check found systemd matching on the old
> platform:arm-cca-dev device path for confidential VM detection. No other
> userspace dependency on the old platform device path was found, but keeping
> the compatibility symlink avoids breaking existing systemd-based detection
> [1].
>
> [1] https://lore.kernel.org/all/4a7d84b2-2ec4-4773-a2d5-7b63d5c683cf@arm.com
Don't attempt to put symlinks between random devices in sysfs, that way
lies madness and you will never get anything fixed.
Just fix userspace, it shouldn't have hard-coded a device path in the
first place, and you are thinking it would now use a different
hard-coded device path? Please do this properly.
Again, there should never be any hard-coded device paths, they are free
to move around and be renamed at any time. Use the correct apis instead
(walking all bus devices, looking at userspace attributes of classes,
etc.)
So your patch is ok, if you remove the symlink stuff.
thanks,
greg k-h
^ permalink raw reply
* [PATCH v5 0/2] arm64: dts: imx8dxl: Add SolidRun SoM and HummingBoard
From: Josua Mayer @ 2026-05-13 10:32 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Andrew Lunn, Vladimir Oltean, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni
Cc: Yazan Shhady, Mikhail Anikin, Alexander Dahl, devicetree,
linux-kernel, imx, linux-arm-kernel, Vladimir Oltean,
Conor Dooley, Krzysztof Kozlowski, netdev, Josua Mayer,
Krzysztof Kozlowski
Add bindings and description for SolidRUn i.MX8DXL based SoM and
HummingBoard Telematics.
Modify SJA1110 Ethernet Switch bindings to allow SPI Mode 0.
This patch-set is based on v7.0-rc2, because rc1 was experiencing
deadlocks with imx8qxp clock driver.
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
Changes in v5:
- Change cpu port phy-mode to rgmii-id, and set zero delays. Delays are
added by connected ethernet switch port.
- Added ethernet aliases for all switch ports.
- Removed undocumented reset-duration-us property from usb modem node.
- Fix T1 interface count in commit message.
- Change USB-A Port dr_mode to host.
- Add cap-sdio-irq for wifi.
- Link to v4: https://lore.kernel.org/r/20260511-imx8dxl-sr-som-v4-0-64381b3bf80d@solid-run.com
Changes in v4:
- picked up acked-by adnrew lunn
- Link to v3: https://lore.kernel.org/r/20260430-imx8dxl-sr-som-v3-0-ce2b86cf75bc@solid-run.com
Changes in v3:
- rebased on v7.1-rc1.
- dropped dsa swtch port labels, should be handled by udev rules if
required.
- Fixed spelling error in alias comment.
- Dropped superfluous status okay properties from switch sub-nodes.
- Link to v2: https://lore.kernel.org/r/20260409-imx8dxl-sr-som-v2-0-83ff20629ba0@solid-run.com
Changes in v2:
- Dropped accidental change to unrelated imx8mp-sr-som.dtsi file.
- Fixed phy-mode on fixed link between cpu and ethernet switch.
(Reported-by: Andrew Lunn <andrew@lunn.ch>)
- Removed spi-cpol property from ethernet-switch on spi bus, fixing
sja1110a driver probe.
- Changed SJA1110 bindings to allow removing spi-cpol property.
- Aligned comments on all ethernet switch port nodes to be consistent.
- Dropped regulator-always-on from dsrc radio power-supplies.
- Link to v1: https://lore.kernel.org/r/20260408-imx8dxl-sr-som-v1-0-ce5a39acd713@solid-run.com
---
Josua Mayer (2):
dt-bindings: arm: fsl: Add SolidRun i.MX8DXL SoM and HummingBoard
arm64: dts: imx8dxl: Add SolidRun SoM and HummingBoard
Documentation/devicetree/bindings/arm/fsl.yaml | 7 +
arch/arm64/boot/dts/freescale/Makefile | 2 +
.../freescale/imx8dxl-hummingboard-telematics.dts | 536 +++++++++++++++++++++
arch/arm64/boot/dts/freescale/imx8dxl-sr-som.dtsi | 458 ++++++++++++++++++
4 files changed, 1003 insertions(+)
---
base-commit: 254f49634ee16a731174d2ae34bc50bd5f45e731
change-id: 20260408-imx8dxl-sr-som-f141ec343173
Best regards,
--
Josua Mayer <josua@solid-run.com>
^ permalink raw reply
* [PATCH v5 2/2] arm64: dts: imx8dxl: Add SolidRun SoM and HummingBoard
From: Josua Mayer @ 2026-05-13 10:32 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Andrew Lunn, Vladimir Oltean, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni
Cc: Yazan Shhady, Mikhail Anikin, Alexander Dahl, devicetree,
linux-kernel, imx, linux-arm-kernel, Vladimir Oltean,
Conor Dooley, Krzysztof Kozlowski, netdev, Josua Mayer
In-Reply-To: <20260513-imx8dxl-sr-som-v5-0-d0899b371c38@solid-run.com>
Add support for the SolidRun i.MX8DXL System-on-Module (revision 2.1)
and its corresponding evaluation carrier board, the HummingBoard
Telematics (revision 2.0).
The SoM features:
- eMMC
- GNSS with 1PPS
- V2X DSRC Radio
- Secure Element for V2X Applications
- Inertial Sensor
- Pressure Sensor
- Compass
The HummingBoard Telematics carrier board features:
- Cellular Modem
- WiFi & Bluetooth
- RTC with backup battery
- CAN
- 100Base-TX Ethernet
- 100Base-T1 Ethernet
- Multi-interface I/O connector
- Multi-interface add-on board connector
The multi-interface I/O connector supplies power and provides basic I/O
(Console UART, 100Base-TX, 100Base-T1, CAN, and power-supply logic level
GPIOs). The SolidRun Evaluation Kit includes a suitable cable and
adapter board that breaks these out into RJ45, USB Type-A, microUSB
Console, and Terminal Block connectors.
The multi-interface add-on board connector provides additional
interfaces (5x 100Base-T1, 2x SGMII, USB 2.0 shared with the cellular
modem, CAN, MDIO, SPI, UART, PCIe, I2C, and GPIO). These add-on
interfaces are disabled by default in the base device tree and are
intended to be enabled and extended via device tree overlays.
Note that a few components physically present on the SoM were omitted
from this description due to a lack of upstream bindings and drivers:
- Pressure Sensor
- V2X DSRC Radio
- Secure Element
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
arch/arm64/boot/dts/freescale/Makefile | 2 +
.../freescale/imx8dxl-hummingboard-telematics.dts | 536 +++++++++++++++++++++
arch/arm64/boot/dts/freescale/imx8dxl-sr-som.dtsi | 458 ++++++++++++++++++
3 files changed, 996 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 711e36cc2c990..7db459f666610 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -111,6 +111,8 @@ dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk.dtb
imx8dxl-evk-pcie-ep-dtbs += imx8dxl-evk.dtb imx-pcie0-ep.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk-pcie-ep.dtb
+DTC_FLAGS_imx8dxl-hummingboard-telematics := -@
+dtb-$(CONFIG_ARCH_MXC) += imx8dxl-hummingboard-telematics.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8dxp-tqma8xdp-mba8xx.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8dxp-tqma8xdps-mb-smarc-2.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-hummingboard-telematics.dts b/arch/arm64/boot/dts/freescale/imx8dxl-hummingboard-telematics.dts
new file mode 100644
index 0000000000000..5f42c4f2e3be9
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-hummingboard-telematics.dts
@@ -0,0 +1,536 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022-2026 Josua Mayer <josua@solid-run.com>
+ */
+
+/dts-v1/;
+
+#include "imx8dxl-sr-som.dtsi"
+
+/ {
+ compatible = "solidrun,imx8dxl-hummingboard-telematics",
+ "solidrun,imx8dxl-sr-som", "fsl,imx8dxl";
+ model = "SolidRun i.MX8DXL HummingBoard Telematics";
+
+ aliases {
+ /* override ethernet aliases from imx8dxl.dtsi */
+ ethernet0 = &eqos;
+ ethernet1 = &switch_port1;
+ ethernet2 = &switch_port2;
+ ethernet3 = &switch_port3;
+ ethernet4 = &switch_port4;
+ ethernet5 = &switch_port5;
+ ethernet6 = &switch_port6;
+ ethernet7 = &switch_port7;
+ ethernet8 = &switch_port8;
+ ethernet9 = &switch_port9;
+ ethernet10 = &switch_port10;
+ /delete-property/ ethernet1;
+ gpio8 = &tca6408_u2;
+ mmc2 = &usdhc3;
+ rtc0 = &carrier_rtc;
+ rtc1 = &rtc;
+ serial1 = &lpuart1;
+ };
+
+ v_1_1: regulator-1-1 {
+ compatible = "regulator-fixed";
+ regulator-name = "1v1";
+ pinctrl-0 = <®ulator_1v1_pins>;
+ pinctrl-names = "default";
+ regulator-always-on;
+ regulator-max-microvolt = <1100000>;
+ regulator-min-microvolt = <1100000>;
+ vin-supply = <&v_5_0>;
+ gpio = <&lsio_gpio4 5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ v_5_0: regulator-5-0 {
+ compatible = "regulator-fixed";
+ regulator-name = "5v0";
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <5000000>;
+ };
+
+ /* can transceiver builtin regulator (STBN1 pin) */
+ reg_flexcan1_stby: regulator-flexcan1-standby {
+ compatible = "regulator-fixed";
+ regulator-name = "flexcan1-standby";
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ gpio = <&tca6408_u2 2 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ /* can transceiver builtin regulator (STBN2 pin) */
+ reg_flexcan2_stby: regulator-flexcan2-standby {
+ compatible = "regulator-fixed";
+ regulator-name = "flexcan2-standby";
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ gpio = <&tca6408_u2 3 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ modem_vbat: regulator-modem-vbat {
+ compatible = "regulator-fixed";
+ regulator-name = "vbat";
+ pinctrl-0 = <®ulator_modem_vbat_pins>;
+ pinctrl-names = "default";
+ regulator-max-microvolt = <3600000>;
+ regulator-min-microvolt = <3600000>;
+ vin-supply = <&v_5_0>;
+ gpio = <&lsio_gpio0 14 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vbus1: regulator-vbus-1 {
+ compatible = "regulator-fixed";
+ regulator-name = "vbus1";
+ pinctrl-0 = <®ulator_usb1_vbus_pins>;
+ pinctrl-names = "default";
+ regulator-max-microvolt = <5000000>;
+ regulator-min-microvolt = <5000000>;
+ gpio = <&lsio_gpio0 16 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ usdhc3_pwrseq: usdhc3-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&lsio_gpio0 15 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&dma_apbh {
+ status = "disabled";
+};
+
+&eqos {
+ /* delays are added by connected ethernet-switch cpu port */
+ phy-mode = "rgmii-id";
+ rx-internal-delay-ps = <0>;
+ tx-internal-delay-ps = <0>;
+ pinctrl-0 = <&eqos_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ fixed-link {
+ full-duplex;
+ speed = <1000>;
+ };
+};
+
+&flexcan1 {
+ pinctrl-0 = <&flexcan1_pins>;
+ pinctrl-names = "default";
+ xceiver-supply = <®_flexcan1_stby>;
+ status = "okay";
+
+ can-transceiver {
+ max-bitrate = <5000000>;
+ };
+};
+
+&flexcan2 {
+ pinctrl-0 = <&flexcan2_pins>;
+ pinctrl-names = "default";
+ xceiver-supply = <®_flexcan2_stby>;
+ status = "okay";
+
+ can-transceiver {
+ max-bitrate = <5000000>;
+ };
+};
+
+&i2c2 {
+ /* routed to J14: SDA(51), SCL(53) */
+
+ /* regulator@18 */
+
+ tca6408_u2: gpio@20 {
+ compatible = "ti,tca6408";
+ reg = <0x20>;
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-line-names = "DIG_IN1", "DIG_IN2", "CAN_STNB1", "CAN_STNB2",
+ "DIG_OUT1", "DIG_OUT2", "", "";
+ interrupts-extended = <&lsio_gpio0 20 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-0 = <&tca6408_u2_int_pins>;
+ pinctrl-names = "default";
+ };
+
+ carrier_rtc: rtc@32 {
+ compatible = "epson,rx8111";
+ reg = <0x32>;
+ };
+};
+
+&iomuxc {
+ bluetooth_pins: pinctrl-bluetooth-grp {
+ fsl,pins = <
+ /* BT_REG_ON: io without pull (module integrates pd) */
+ IMX8DXL_SPI3_SCK_LSIO_GPIO0_IO13 0x0000061
+ >;
+ };
+
+ eqos_pins: pinctrl-eqos-grp {
+ fsl,pins = <
+ /* MDIO to Switch */
+ /* enet0 mdio pads supplied with 3.3v */
+ /* IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIOCT */
+ IMX8DXL_ENET0_MDC_CONN_EQOS_MDC 0x06000020
+ IMX8DXL_ENET0_MDIO_CONN_EQOS_MDIO 0x06000020
+ /* RGMII to Switch */
+ IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL 0x06000020
+ IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC 0x06000020
+ IMX8DXL_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0 0x06000020
+ IMX8DXL_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1 0x06000020
+ IMX8DXL_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2 0x06000020
+ IMX8DXL_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3 0x06000020
+ IMX8DXL_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC 0x06000020
+ IMX8DXL_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL 0x06000020
+ IMX8DXL_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0 0x06000020
+ IMX8DXL_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1 0x06000020
+ IMX8DXL_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2 0x06000020
+ IMX8DXL_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3 0x06000020
+ >;
+ };
+
+ flexcan1_pins: pinctrl-flexcan1-grp {
+ fsl,pins = <
+ IMX8DXL_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x00000021
+ IMX8DXL_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x00000021
+ >;
+ };
+
+ flexcan2_pins: pinctrl-flexcan2-grp {
+ fsl,pins = <
+ IMX8DXL_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x00000021
+ IMX8DXL_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x00000021
+ >;
+ };
+
+ lpspi0_pins: pinctrl-lpspi0-grp {
+ fsl,pins = <
+ IMX8DXL_SPI0_SCK_ADMA_SPI0_SCK 0x600004c
+ IMX8DXL_SPI0_SDO_ADMA_SPI0_SDO 0x600004c
+ IMX8DXL_SPI0_SDI_ADMA_SPI0_SDI 0x600004c
+ IMX8DXL_SPI0_CS0_LSIO_GPIO1_IO08 0x0000021
+ IMX8DXL_SPI0_CS1_LSIO_GPIO1_IO07 0x0000021
+ >;
+ };
+
+ lpuart1_pins: pinctrl-lpuart1-grp {
+ fsl,pins = <
+ IMX8DXL_UART1_RX_ADMA_UART1_RX 0x06000020
+ IMX8DXL_UART1_TX_ADMA_UART1_TX 0x06000020
+ IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B 0x06000020
+ IMX8DXL_UART1_RTS_B_ADMA_UART1_RTS_B 0x06000020
+ >;
+ };
+
+ modem_pins: pinctrl-lte-grp {
+ fsl,pins = <
+ /* modem RESET_N: io open drain drive 2mA */
+ IMX8DXL_ADC_IN3_LSIO_GPIO1_IO11 0x2000061
+
+ /* modem PWRKEY: io open drain with pull-up, drive 2mA */
+ IMX8DXL_ADC_IN2_LSIO_GPIO1_IO12 0x2000021
+ >;
+ };
+
+ regulator_1v1_pins: pinctrl-regulator-1-1-grp {
+ fsl,pins = <
+ /* SW_PE: io without pull-up */
+ IMX8DXL_USB_SS3_TC2_LSIO_GPIO4_IO05 0x0000061
+ >;
+ };
+
+ regulator_modem_vbat_pins: pinctrl-regulator-modem-vbat-grp {
+ fsl,pins = <
+ /*
+ * RF_PWR: io without pull-up,
+ * has either external pull-up (R1117) or pull-down (R1118).
+ * With pull-up Modem will boot at system power-up,
+ * with pull-down modem will enter power-down mode once
+ * vbat is enabled -> toggle pwrkey to boot modem.
+ * Hence pull-up (R1117) is preferred.
+ */
+ IMX8DXL_SPI3_SDO_LSIO_GPIO0_IO14 0x0000061
+ >;
+ };
+
+ regulator_usb1_vbus_pins: pinctrl-regulator-usb1-vbus-grp {
+ fsl,pins = <
+ /* regulator enable: open-drain with pull-up & low drive strength */
+ IMX8DXL_SPI3_CS0_LSIO_GPIO0_IO16 0x2000021
+ >;
+ };
+
+ switch_pins: pinctrl-switch-grp {
+ fsl,pins = <
+ /* SW_RSTn: io without pull-up */
+ IMX8DXL_USB_SS3_TC0_LSIO_GPIO4_IO03 0x0000021
+
+ /* SW_CORE_RSTn: io without pull-up */
+ IMX8DXL_USB_SS3_TC1_LSIO_GPIO4_IO04 0x0000021
+
+ /* INT_N: io without pull-up */
+ IMX8DXL_USB_SS3_TC3_LSIO_GPIO4_IO06 0x0000021
+ >;
+ };
+
+ tca6408_u2_int_pins: pinctrl-tca6408-u2-int-grp {
+ fsl,pins = <
+ /* gpio-expander interrupt: io with pull-up */
+ IMX8DXL_MCLK_OUT0_LSIO_GPIO0_IO20 0x0000021
+ >;
+ };
+
+ usdhc3_pins: pinctrl-usdhc3-grp {
+ fsl,pins = <
+ IMX8DXL_ENET0_RGMII_TXC_CONN_USDHC2_CLK 0x06000040
+ IMX8DXL_ENET0_RGMII_TX_CTL_CONN_USDHC2_CMD 0x00000021
+ IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC2_DATA0 0x00000021
+ IMX8DXL_ENET0_RGMII_TXD1_CONN_USDHC2_DATA1 0x00000021
+ IMX8DXL_ENET0_RGMII_TXD2_CONN_USDHC2_DATA2 0x00000021
+ IMX8DXL_ENET0_RGMII_TXD3_CONN_USDHC2_DATA3 0x00000021
+ >;
+ };
+
+ wifi_pins: pinctrl-wifi-grp {
+ fsl,pins = <
+ /* WL_REG_ON: io without pull (module integrates pd) */
+ IMX8DXL_SPI3_SDI_LSIO_GPIO0_IO15 0x0000061
+ >;
+ };
+};
+
+&lpspi0 {
+ cs-gpios = <&lsio_gpio1 8 GPIO_ACTIVE_LOW>, <&lsio_gpio1 7 GPIO_ACTIVE_LOW>;
+ pinctrl-0 = <&lpspi0_pins>, <&switch_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ ethernet-switch@0 {
+ compatible = "nxp,sja1110a";
+ reg = <0>;
+ reset-gpios = <&lsio_gpio4 3 GPIO_ACTIVE_LOW>;
+ spi-max-frequency = <4000000>;
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* 100Base-TX on connector J26 */
+ switch_port1: port@1 {
+ reg = <0x1>;
+ phy-handle = <&switch_port1_base_tx_phy>;
+ phy-mode = "internal";
+ };
+
+ /* CPU */
+ switch_port2: port@2 {
+ reg = <0x2>;
+ ethernet = <&eqos>;
+ phy-mode = "rgmii-id";
+ rx-internal-delay-ps = <2000>;
+ tx-internal-delay-ps = <2000>;
+
+ fixed-link {
+ full-duplex;
+ speed = <1000>;
+ };
+ };
+
+ /* sgmii on addon board connector J21 */
+ switch_port3: port@3 {
+ reg = <0x3>;
+ status = "disabled";
+ };
+
+ /* sgmii on addon board connector J21 */
+ switch_port4: port@4 {
+ reg = <0x4>;
+ status = "disabled";
+ };
+
+ /* 100base-t1 on addon board connector J21 */
+ switch_port5: port@5 {
+ reg = <0x5>;
+ phy-handle = <&switch_port5_base_t1_phy>;
+ phy-mode = "internal";
+ status = "disabled";
+ };
+
+ /* 100base-t1 on addon board connector J21 */
+ switch_port6: port@6 {
+ reg = <0x6>;
+ phy-handle = <&switch_port6_base_t1_phy>;
+ phy-mode = "internal";
+ status = "disabled";
+ };
+
+ /* 100base-t1 on addon board connector J21 */
+ switch_port7: port@7 {
+ reg = <0x7>;
+ phy-handle = <&switch_port7_base_t1_phy>;
+ phy-mode = "internal";
+ status = "disabled";
+ };
+
+ /* 100base-t1 on addon board connector J21 */
+ switch_port8: port@8 {
+ reg = <0x8>;
+ phy-handle = <&switch_port8_base_t1_phy>;
+ phy-mode = "internal";
+ status = "disabled";
+ };
+
+ /* 100base-t1 on addon board connector J21 */
+ switch_port9: port@9 {
+ reg = <0x9>;
+ phy-handle = <&switch_port9_base_t1_phy>;
+ phy-mode = "internal";
+ status = "disabled";
+ };
+
+ /* 100Base-T1 on connector J26 */
+ switch_port10: port@a {
+ reg = <0xa>;
+ phy-handle = <&switch_port10_base_t1_phy>;
+ phy-mode = "internal";
+ };
+ };
+
+ mdios {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mdio@0 {
+ compatible = "nxp,sja1110-base-t1-mdio";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* 100base-t1 on addon board connector J21 */
+ switch_port5_base_t1_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x1>;
+ status = "disabled";
+ };
+
+ /* 100base-t1 on addon board connector J21 */
+ switch_port6_base_t1_phy: ethernet-phy@2 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x2>;
+ status = "disabled";
+ };
+
+ /* 100base-t1 on addon board connector J21 */
+ switch_port7_base_t1_phy: ethernet-phy@3 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x3>;
+ status = "disabled";
+ };
+
+ /* 100base-t1 on addon board connector J21 */
+ switch_port8_base_t1_phy: ethernet-phy@4 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x4>;
+ status = "disabled";
+ };
+
+ /* 100base-t1 on addon board connector J21 */
+ switch_port9_base_t1_phy: ethernet-phy@5 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x5>;
+ status = "disabled";
+ };
+
+ /* 100Base-T1 on connector J26 */
+ switch_port10_base_t1_phy: ethernet-phy@6 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <0x6>;
+ };
+ };
+
+ mdio@1 {
+ compatible = "nxp,sja1110-base-tx-mdio";
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* 100Base-TX on connector J26 */
+ switch_port1_base_tx_phy: ethernet-phy@1 {
+ reg = <0x1>;
+ };
+ };
+ };
+ };
+};
+
+/* bluetooth */
+&lpuart1 {
+ pinctrl-0 = <&lpuart1_pins>, <&bluetooth_pins>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm4345c5";
+ /* Murata 1MW module supports max. 3M baud */
+ max-speed = <3000000>;
+ shutdown-gpios = <&lsio_gpio0 13 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&usbotg1 {
+ dr_mode = "host";
+ vbus-supply = <&vbus1>;
+};
+
+/* cellular modem */
+&usbotg2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ adp-disable;
+ disable-over-current;
+ dr_mode = "host";
+ hnp-disable;
+ pinctrl-0 = <&modem_pins>;
+ pinctrl-names = "default";
+ power-active-high;
+ srp-disable;
+ vbus-supply = <&v_5_0>;
+ status = "okay";
+
+ usb-device@1 {
+ compatible = "usb2c7c,125";
+ reg = <1>;
+ reset-gpios = <&lsio_gpio1 11 GPIO_ACTIVE_LOW>;
+ vbus-supply = <&v_3_3>;
+ vdd-supply = <&modem_vbat>;
+ };
+};
+
+&usbphy2 {
+ status = "okay";
+};
+
+/* WiFi */
+&usdhc3 {
+ bus-width = <4>;
+ cap-sdio-irq;
+ mmc-pwrseq = <&usdhc3_pwrseq>;
+ non-removable;
+ no-sd;
+ pinctrl-0 = <&usdhc3_pins>, <&wifi_pins>;
+ pinctrl-names = "default";
+ vmmc-supply = <&v_3_3>;
+ vqmmc-supply = <&v_1_8>;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-sr-som.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-sr-som.dtsi
new file mode 100644
index 0000000000000..93a0eb4d7f770
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8dxl-sr-som.dtsi
@@ -0,0 +1,458 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022-2026 Josua Mayer <josua@solid-run.com>
+ */
+
+#include "imx8dxl.dtsi"
+/ {
+ compatible = "solidrun,imx8dxl-sr-som", "fsl,imx8dxl";
+ model = "SolidRun i.MX8DXL SoM";
+
+ aliases {
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ mmc0 = &usdhc1;
+ mmc1 = &usdhc2;
+ serial0 = &lpuart0;
+ serial2 = &lpuart2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ imx8dxl-cm4 {
+ compatible = "fsl,imx8qxp-cm4";
+ clocks = <&clk_dummy>;
+ mboxes = <&lsio_mu5 0 1 &lsio_mu5 1 1 &lsio_mu5 3 1>;
+ mbox-names = "tx", "rx", "rxdb";
+ memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
+ <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>;
+ power-domains = <&pd IMX_SC_R_M4_0_PID0>, <&pd IMX_SC_R_M4_0_MU_1A>;
+ fsl,entry-address = <0x34fe0000>;
+ fsl,resource-id = <IMX_SC_R_M4_0_PID0>;
+ };
+
+ pps {
+ compatible = "pps-gpio";
+ gpios = <&lsio_gpio2 6 GPIO_ACTIVE_HIGH>;
+ pinctrl-0 = <&gnss_pps_pins>;
+ pinctrl-names = "default";
+ };
+
+ v_1_2: regulator-1-2 {
+ compatible = "regulator-fixed";
+ regulator-name = "1v2";
+ pinctrl-0 = <®ulator_1_2_pins>;
+ pinctrl-names = "default";
+ regulator-max-microvolt = <1200000>;
+ regulator-min-microvolt = <1200000>;
+ gpio = <&lsio_gpio1 13 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ v_1_6: regulator-1-6 {
+ compatible = "regulator-fixed";
+ regulator-name = "1v6";
+ pinctrl-0 = <®ulator_1_6_pins>;
+ pinctrl-names = "default";
+ regulator-max-microvolt = <1600000>;
+ regulator-min-microvolt = <1600000>;
+ vin-supply = <&v_1_8>;
+ gpio = <&lsio_gpio1 14 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ v_1_8: regulator-1-8 {
+ compatible = "regulator-fixed";
+ regulator-name = "1v8";
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ };
+
+ v_1_8_se: regulator-1-8-secure-element {
+ compatible = "regulator-fixed";
+ regulator-name = "1v8-se";
+ pinctrl-0 = <®ulator_1_8_se_pins>;
+ pinctrl-names = "default";
+ regulator-max-microvolt = <1800000>;
+ regulator-min-microvolt = <1800000>;
+ vin-supply = <&v_1_8>;
+ gpio = <&lsio_gpio3 18 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ v_3_3: regulator-3-3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3v3";
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ };
+
+ reserved-memory {
+ ranges;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ /* global autoconfigured region for contiguous allocations */
+ linux,cma {
+ compatible = "shared-dma-pool";
+ alloc-ranges = <0 0x98000000 0 0x14000000>;
+ reusable;
+ size = <0 0x14000000>;
+ linux,cma-default;
+ };
+
+ vdev0vring0: memory0@90000000 {
+ reg = <0 0x90000000 0 0x8000>;
+ no-map;
+ };
+
+ vdev0vring1: memory@90008000 {
+ reg = <0 0x90008000 0 0x8000>;
+ no-map;
+ };
+
+ vdev1vring0: memory@90010000 {
+ reg = <0 0x90010000 0 0x8000>;
+ no-map;
+ };
+
+ vdev1vring1: memory@90018000 {
+ reg = <0 0x90018000 0 0x8000>;
+ no-map;
+ };
+
+ rsc_table: memory-rsc-table@900ff000 {
+ reg = <0 0x900ff000 0 0x1000>;
+ no-map;
+ };
+
+ vdevbuffer: memory-vdevbuffer@90400000 {
+ compatible = "shared-dma-pool";
+ reg = <0 0x90400000 0 0x100000>;
+ no-map;
+ };
+
+ /*
+ * Memory reserved for optee usage. Please do not use.
+ * This will be automatically added to dtb if OP-TEE is installed.
+ * optee@96000000 {
+ * reg = <0 0x96000000 0 0x2000000>;
+ * no-map;
+ * };
+ */
+ };
+
+ memory@80000000 {
+ reg = <0x00000000 0x80000000 0 0x40000000>;
+ device_type = "memory";
+ };
+};
+
+&i2c2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <100000>;
+ pinctrl-0 = <&i2c2_pins>;
+ pinctrl-1 = <&i2c2_gpio_pins>;
+ pinctrl-names = "default", "gpio";
+ scl-gpios = <&lsio_gpio3 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&lsio_gpio3 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+};
+
+&i2c3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <100000>;
+ pinctrl-0 = <&i2c3_pins>;
+ pinctrl-1 = <&i2c3_gpio_pins>;
+ pinctrl-names = "default", "gpio";
+ scl-gpios = <&lsio_gpio3 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ sda-gpios = <&lsio_gpio3 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+ status = "okay";
+
+ magnetometer@1e {
+ compatible = "st,iis2mdc";
+ reg = <0x1e>;
+ interrupt-parent = <&lsio_gpio2>;
+ interrupts = <10 IRQ_TYPE_EDGE_RISING>;
+ pinctrl-0 = <&magnetometer_pins>;
+ pinctrl-names = "default";
+ st,drdy-int-pin = <1>;
+ };
+
+ /* pressure-sensor@5c */
+
+ inertial-sensor@6b {
+ compatible = "st,ism330dhcx";
+ reg = <0x6b>;
+ interrupt-parent = <&lsio_gpio2>;
+ interrupts = <11 IRQ_TYPE_EDGE_RISING>;
+ pinctrl-0 = <&imu_pins>;
+ pinctrl-names = "default";
+ st,drdy-int-pin = <1>;
+ };
+};
+
+&iomuxc {
+ pinctrl-0 = <&pinctrl_hog>;
+ pinctrl-names = "default";
+
+ pinctrl_hog: hoggrp {
+ fsl,pins = <
+ IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0
+ IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD 0x000014a0
+ >;
+ };
+
+ dsrc_pins: pinctrl-dsrc-grp {
+ fsl,pins = <
+ /* reset: io without pull */
+ IMX8DXL_ADC_IN0_LSIO_GPIO1_IO10 0x0000060
+
+ /*
+ * boot0: io without pull
+ * After reset, this pin selects radio boot media:
+ * - 0: flash spi
+ * - 1: slave sdio
+ * Once the firmware boots however, the radio controls
+ * this pin for flow-control to signal readiness.
+ */
+ IMX8DXL_ADC_IN1_LSIO_GPIO1_IO09 0x0000060
+ >;
+ };
+
+ gnss_pins: pinctrl-gnss-grp {
+ fsl,pins = <
+ /* gps reset: input with pull-up */
+ IMX8DXL_SNVS_TAMPER_OUT4_LSIO_GPIO2_IO08_IN 0x0000021
+ /* gps interrupt: io without pull-up */
+ IMX8DXL_SNVS_TAMPER_IN0_LSIO_GPIO2_IO09_IN 0x0000061
+ >;
+ };
+
+ gnss_pps_pins: pinctrl-gnss-pps-grp {
+ fsl,pins = <
+ /* gps timepulse: input without pull-up */
+ IMX8DXL_SNVS_TAMPER_OUT2_LSIO_GPIO2_IO06_IN 0x0000061
+ >;
+ };
+
+ i2c2_gpio_pins: pinctrl-i2c2-gpio-grp {
+ fsl,pins = <
+ /* io with pull-up and weak drive */
+ IMX8DXL_SPI1_SCK_LSIO_GPIO3_IO00 0x00000021
+ /* io with pull-up, weak drive, open-drain */
+ IMX8DXL_SPI1_SDO_LSIO_GPIO3_IO01 0x02000021
+ >;
+ };
+
+ i2c2_pins: pinctrl-i2c2-grp {
+ fsl,pins = <
+ /* io with pull-up and weak drive */
+ IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA 0x06000021
+ IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL 0x06000021
+ >;
+ };
+
+ i2c3_gpio_pins: pinctrl-i2c3-gpio-grp {
+ fsl,pins = <
+ /* io with pull-up and weak drive */
+ IMX8DXL_SPI1_CS0_LSIO_GPIO3_IO03 0x00000021
+ /* io with pull-up, weak drive, open-drain */
+ IMX8DXL_SPI1_SDI_LSIO_GPIO3_IO02 0x02000021
+ >;
+ };
+
+ i2c3_pins: pinctrl-i2c3-grp {
+ fsl,pins = <
+ /* io with pull-up and weak drive */
+ IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA 0x06000021
+ IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL 0x06000021
+ >;
+ };
+
+ imu_pins: pinctrl-imu-grp {
+ fsl,pins = <
+ /* interrupt: io with pull-down */
+ IMX8DXL_SNVS_TAMPER_IN2_LSIO_GPIO2_IO11_IN 0x0000041
+ >;
+ };
+
+ lpspi2_pins: pinctrl-lpspi2-grp {
+ fsl,pins = <
+ IMX8DXL_USDHC1_RESET_B_ADMA_SPI2_SCK 0x600004c
+ IMX8DXL_USDHC1_VSELECT_ADMA_SPI2_SDO 0x600004c
+ IMX8DXL_USDHC1_WP_ADMA_SPI2_SDI 0x600004c
+ IMX8DXL_USDHC1_CD_B_LSIO_GPIO4_IO22 0x6000021
+ >;
+ };
+
+ lpuart0_pins: pinctrl-lpuart0-grp {
+ fsl,pins = <
+ IMX8DXL_UART0_RX_ADMA_UART0_RX 0x06000020
+ IMX8DXL_UART0_TX_ADMA_UART0_TX 0x06000020
+ >;
+ };
+
+ lpuart2_pins: pinctrl-lpuart2-grp {
+ fsl,pins = <
+ IMX8DXL_UART2_TX_ADMA_UART2_TX 0x06000020
+ IMX8DXL_UART2_RX_ADMA_UART2_RX 0x06000020
+ >;
+ };
+
+ magnetometer_pins: pinctrl-magnetometer-grp {
+ fsl,pins = <
+ /* interrupt: io with pull-down */
+ IMX8DXL_SNVS_TAMPER_IN1_LSIO_GPIO2_IO10_IN 0x0000041
+ >;
+ };
+
+ regulator_1_2_pins: pinctrl-regulator-1-2-grp {
+ fsl,pins = <
+ /* io without pull-up */
+ /* has etxernal pull-down */
+ IMX8DXL_ADC_IN5_LSIO_GPIO1_IO13 0x0000061
+ >;
+ };
+
+ regulator_1_6_pins: pinctrl-regulator-1-6-grp {
+ fsl,pins = <
+ /* io without pull-up */
+ /* has etxernal pull-down */
+ IMX8DXL_ADC_IN4_LSIO_GPIO1_IO14 0x0000061
+ >;
+ };
+
+ regulator_1_8_se_pins: pinctrl-regulator-1-8-secure-element-grp {
+ fsl,pins = <
+ /* v2x-secure-element power switch: io with pull-down */
+ IMX8DXL_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x0000041
+ >;
+ };
+
+ se_pins: pinctrl-secure-element-grp {
+ fsl,pins = <
+ /* v2x-secure-element reset: io with pull-up */
+ IMX8DXL_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x0000021
+
+ /*
+ * v2x-secure-element gpio0: io with pull-up
+ * pulled low by sxf after boot indicating ready for commands
+ */
+ IMX8DXL_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x0000021
+
+ /* v2x-secure-element gpio1: io with pull-up */
+ IMX8DXL_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x0000021
+ >;
+ };
+
+ usdhc1_pins: pinctrl-usdhc1-grp {
+ fsl,pins = <
+ IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
+ IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
+ IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
+ IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
+ IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
+ IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
+ IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
+ IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
+ IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
+ IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
+ IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
+ IMX8DXL_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000061
+ >;
+ };
+
+ usdhc2_pins: pinctrl-usdhc2-grp {
+ fsl,pins = <
+ IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000040
+ IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021
+ IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021
+ IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021
+ IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021
+ IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021
+ >;
+ };
+};
+
+&lpspi2 {
+ cs-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
+ num-cs = <1>;
+ pinctrl-0 = <&lpspi2_pins>, <&se_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+/* console */
+&lpuart0 {
+ pinctrl-0 = <&lpuart0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+/* gnss */
+&lpuart2 {
+ pinctrl-0 = <&lpuart2_pins>, <&gnss_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&lsio_gpio3 {
+ gpio-line-names = "", "", "", "", "", "", "", "",
+ "", "", "", "", "", "", "", "",
+ "", "", "", "SXF_RST", "SXF_GPIO0", "SXF_GPIO1", "", "",
+ "", "", "", "", "", "", "", "";
+};
+
+&lsio_mu5 {
+ status = "okay";
+};
+
+/* OTG port for boot */
+&usbotg1 {
+ adp-disable;
+ disable-over-current;
+ dr_mode = "peripheral";
+ hnp-disable;
+ power-active-high;
+ srp-disable;
+ status = "okay";
+};
+
+&usbphy1 {
+ status = "okay";
+};
+
+/* eMMC */
+&usdhc1 {
+ bus-width = <8>;
+ cap-mmc-hw-reset;
+ non-removable;
+ no-sd;
+ no-sdio;
+ pinctrl-0 = <&usdhc1_pins>;
+ pinctrl-1 = <&usdhc1_pins>;
+ pinctrl-2 = <&usdhc1_pins>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ vmmc-supply = <&v_3_3>;
+ vqmmc-supply = <&v_1_8>;
+ status = "okay";
+};
+
+/* DSRC Radio */
+&usdhc2 {
+ bus-width = <4>;
+ keep-power-in-suspend;
+ max-frequency = <40000000>;
+ non-removable;
+ no-sd;
+ pinctrl-0 = <&usdhc2_pins>, <&dsrc_pins>;
+ pinctrl-names = "default";
+ vmmc-supply = <&v_3_3>;
+ vqmmc-supply = <&v_1_8>;
+ status = "okay";
+};
--
2.51.0
^ permalink raw reply related
* [PATCH v5 1/2] dt-bindings: arm: fsl: Add SolidRun i.MX8DXL SoM and HummingBoard
From: Josua Mayer @ 2026-05-13 10:32 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Andrew Lunn, Vladimir Oltean, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni
Cc: Yazan Shhady, Mikhail Anikin, Alexander Dahl, devicetree,
linux-kernel, imx, linux-arm-kernel, Vladimir Oltean,
Conor Dooley, Krzysztof Kozlowski, netdev, Josua Mayer,
Krzysztof Kozlowski
In-Reply-To: <20260513-imx8dxl-sr-som-v5-0-d0899b371c38@solid-run.com>
Add binding for the SolidRun i.MX8DXL based System on Module, and the
reference HummingBoard Telematics.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Josua Mayer <josua@solid-run.com>
---
Documentation/devicetree/bindings/arm/fsl.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index 0023cd1268075..17cd47e8efce8 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -1394,6 +1394,13 @@ properties:
- fsl,imx8dxl-evk # i.MX8DXL EVK Board
- const: fsl,imx8dxl
+ - description: SolidRun i.MX8DXL SoM based boards
+ items:
+ - enum:
+ - solidrun,imx8dxl-hummingboard-telematics # SolidRun i.MX8DXL SoM EVK Board
+ - const: solidrun,imx8dxl-sr-som
+ - const: fsl,imx8dxl
+
- description: i.MX8QXP/i.MX8DX Boards with Toradex Colibri iMX8X Modules
items:
- enum:
--
2.51.0
^ permalink raw reply related
* Re: [PATCH 1/3] dt-bindings: soc: imx: fsl,imx93-media-blk-ctrl: Allow LVDS Display Bridge child node
From: Marco Felsch @ 2026-05-13 10:29 UTC (permalink / raw)
To: Liu Ying
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, Peng Fan,
devicetree, linux-kernel, linux-arm-kernel, imx
In-Reply-To: <20260513-imx93-ldb-v1-1-d11c5c3cc197@nxp.com>
Hi Liu,
can we please wait for the outcome of this dicussion:
https://lore.kernel.org/all/uyh5s6g7bvuufnhfjrmungp5dbyllxfrgfzaxno22knpxxojmj@qqvh75ezblpp/
before we're going further?
Regards,
Marco
On 26-05-13, Liu Ying wrote:
> i.MX93 SoC mediamix blk-ctrl contains one LDB_CTRL register and one LVDS
> register which control video output through a LVDS interface. Allow the
> LVDS Display Bridge(LDB) child node and add the child node to example.
>
> Signed-off-by: Liu Ying <victor.liu@nxp.com>
> ---
> .../bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml | 38 ++++++++++++++++++++++
> 1 file changed, 38 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml
> index d828c2e82965..ab563b457e07 100644
> --- a/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml
> +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml
> @@ -26,6 +26,12 @@ properties:
> reg:
> maxItems: 1
>
> + '#address-cells':
> + const: 1
> +
> + '#size-cells':
> + const: 1
> +
> '#power-domain-cells':
> const: 1
>
> @@ -92,6 +98,11 @@ properties:
> - compatible
> - ports
>
> + bridge@20:
> + type: object
> + $ref: /schemas/display/bridge/fsl,ldb.yaml#
> + unevaluatedProperties: false
> +
> allOf:
> - if:
> properties:
> @@ -163,6 +174,8 @@ examples:
> <&clk IMX93_CLK_MIPI_DSI_GATE>;
> clock-names = "apb", "axi", "nic", "disp", "cam",
> "pxp", "lcdif", "isi", "csi", "dsi";
> + #address-cells = <1>;
> + #size-cells = <1>;
> #power-domain-cells = <1>;
>
> dpi-bridge {
> @@ -190,4 +203,29 @@ examples:
> };
> };
> };
> +
> + bridge@20 {
> + compatible = "fsl,imx93-ldb";
> + reg = <0x20 0x4>, <0x24 0x4>;
> + reg-names = "ldb", "lvds";
> + clocks = <&clk IMX93_CLK_LVDS_GATE>;
> + clock-names = "ldb";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + endpoint {
> + remote-endpoint = <&lcdif_to_ldb>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + };
> + };
> + };
> };
>
> --
> 2.43.0
>
>
>
--
#gernperDu
#CallMeByMyFirstName
Pengutronix e.K. | |
Steuerwalder Str. 21 | https://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-9 |
^ permalink raw reply
* Re: [PATCH v4 02/15] mm: Make empty_zero_page __ro_after_init
From: Mike Rapoport @ 2026-05-13 10:28 UTC (permalink / raw)
To: Ard Biesheuvel
Cc: Jann Horn, Ard Biesheuvel, linux-arm-kernel, linux-kernel,
Will Deacon, Catalin Marinas, Mark Rutland, Ryan Roberts,
Anshuman Khandual, Liz Prucka, Seth Jenkins, Kees Cook,
David Hildenbrand, Andrew Morton, linux-mm, linux-hardening
In-Reply-To: <49d30ffe-b7e1-4b05-89e0-c3fe01348bb6@app.fastmail.com>
On Wed, May 13, 2026 at 10:53:08AM +0200, Ard Biesheuvel wrote:
>
> On Wed, 13 May 2026, at 10:50, Mike Rapoport wrote:
> > On Tue, May 12, 2026 at 02:56:16PM +0200, Ard Biesheuvel wrote:
> >> On Mon, 11 May 2026, at 16:40, Jann Horn wrote:
> >> > On Mon, May 11, 2026 at 10:59 AM Ard Biesheuvel <ardb@kernel.org> wrote:
> >> >> I think we should simply do something along the lines of the below,
> >> >> considering that the size of a data object tends to correlate with
> >> >> its minimum alignment.
> >> >>
> >> >> I do find it rather puzzling that the compiler emits empty_zero_page
> >> >> *after* zero_page_pfn - ideally, we'd combine the below with
> >> >> -fdata-sections so that the linker sees all individual objects, but
> >> >> I suspect that would create some problems elsewhere.
> >> >>
> >> >>
> >> >> --- a/include/asm-generic/vmlinux.lds.h
> >> >> +++ b/include/asm-generic/vmlinux.lds.h
> >> >> @@ -452,7 +452,7 @@
> >> >> #define RO_AFTER_INIT_DATA \
> >> >> . = ALIGN(8); \
> >> >> __start_ro_after_init = .; \
> >> >> - *(.data..ro_after_init) \
> >> >> + *(SORT_BY_ALIGNMENT(.data..ro_after_init)) \
> >> >
> >> > Oh, neat, I didn't realize that's possible. That seems like a nicer
> >> > approach...
> >>
> >> Neat but rather ineffective, unfortunately. (I don't see a size
> >> difference with the arm64 defconfig kernel)
> >>
> >> Given that empty_zero_page only ever gets its address taken, we
> >> might just move it into the linker script if that requires tweaking
> >> anyway. We can just place it at the start of .rodata, which is
> >> already page aligned on most architectures (and will become page
> >> aligned unless EMPTY_ZERO_PAGE is #define'd by the arch linker
> >> script to something else)
> >>
> >>
> >> --- a/include/asm-generic/vmlinux.lds.h
> >> +++ b/include/asm-generic/vmlinux.lds.h
> >> @@ -472,6 +472,17 @@
> >> #endif
> >> #endif
> >>
> >> +#ifndef EMPTY_ZERO_PAGE
> >> +#ifndef __HAVE_COLOR_ZERO_PAGE
> >
> > I don't think we want let architectures that don't use colored zero pages
> > redefine it.
> > If it will be really required we can add the ability to redefine
> > EMPTY_ZERO_PAGE later.
> >
>
> I was actually intending to add use this for arm64 in the next patch. It
> already has a reserved_pg_dir in .rodata which is page-sized (i.e., up
> to 64k in size) and guaranteed to remain all zeroes, so empty_zero_page
> could actually be an alias for that. This is what I had in a previous
> revision, before you turned the empty_zero_page definition into common
> code:
Works for me if from arm64 perspective that's ok :)
> https://lore.kernel.org/all/20260320145934.2349881-16-ardb+git@google.com/
--
Sincerely yours,
Mike.
^ permalink raw reply
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