* Re: [PATCH 05/16] media: v4l2-common: Fix NV15_4L4 format info block height
From: Nicolas Dufresne @ 2026-05-19 15:16 UTC (permalink / raw)
To: Paul Kocialkowski, linux-media, linux-arm-kernel, linux-sunxi,
linux-kernel, linux-staging
Cc: Mauro Carvalho Chehab, Chen-Yu Tsai, Jernej Skrabec,
Samuel Holland, Greg Kroah-Hartman, Arash Golgol,
Laurent Pinchart
In-Reply-To: <20260518102451.417971-6-paulk@sys-base.io>
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Le lundi 18 mai 2026 à 12:24 +0200, Paul Kocialkowski a écrit :
> The NV15_4L4 format is specified as a 4x4 format, not 4x1.
> In addition the block size should not take subsampling in account,
> so specify it as 4x4 for both luma and chroma.
>
> Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
> ---
> drivers/media/v4l2-core/v4l2-common.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c
> index 554c591e1113..77a0daa92c2b 100644
> --- a/drivers/media/v4l2-core/v4l2-common.c
> +++ b/drivers/media/v4l2-core/v4l2-common.c
> @@ -309,7 +309,7 @@ const struct v4l2_format_info *v4l2_format_info(u32 format)
> /* Tiled YUV formats */
> { .format = V4L2_PIX_FMT_NV12_4L4, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 2, .vdiv = 2 },
> { .format = V4L2_PIX_FMT_NV15_4L4, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 5, 10, 0, 0 }, .bpp_div = { 4, 4, 1, 1 }, .hdiv = 2, .vdiv = 2,
> - .block_w = { 4, 2, 0, 0 }, .block_h = { 1, 1, 0, 0 }},
> + .block_w = { 4, 4, 0, 0 }, .block_h = { 4, 4, 0, 0 }},
Only the block_h is broken. The block_w is in "pixels" which for the UV plane is
component pairs. So both set of tiles have 5bytes stride. But since the second
set, the UV tiles, are interleaved, they only have 2 pairs of UV per row. So to
me the correct fix is:
+ .block_w = { 4, 2, 0, 0 }, .block_h = { 4, 4, 0, 0 }},
If its not the case for the camera pipeline, then a new format is needed, since
this format should perfectly match NV15 + VIVANTE_TILED in the DRM world.
regards,
Nicolas
> { .format = V4L2_PIX_FMT_P010_4L4, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 2, 4, 0, 0 }, .bpp_div = { 1, 1, 1, 1 }, .hdiv = 2, .vdiv = 2 },
>
> /* YUV planar formats, non contiguous variant */
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^ permalink raw reply
* Re: [PATCH 31/37] drm/bridge: panel: implement .is_tail
From: Neil Armstrong @ 2026-05-19 15:12 UTC (permalink / raw)
To: Luca Ceresoli, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Andrzej Hajda,
Robert Foss, Laurent Pinchart, Jonas Karlman, Jernej Skrabec,
Inki Dae, Jagan Teki, Marek Szyprowski, Marek Vasut, Stefan Agner,
Frank Li, Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: Hui Pu, Ian Ray, Thomas Petazzoni, dri-devel, linux-kernel, imx,
linux-arm-kernel
In-Reply-To: <20260519-drm-bridge-hotplug-v1-31-45e2bdb3dfb4@bootlin.com>
On 5/19/26 12:37, Luca Ceresoli wrote:
> This bridge is always a tail bridge, i.e. it never needs a following bridge
> to complete the pipeline. Add a is_tail func to expose this.
>
> Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
> ---
> drivers/gpu/drm/bridge/panel.c | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/bridge/panel.c b/drivers/gpu/drm/bridge/panel.c
> index 4978ec98a082..102f987b1235 100644
> --- a/drivers/gpu/drm/bridge/panel.c
> +++ b/drivers/gpu/drm/bridge/panel.c
> @@ -58,6 +58,11 @@ static const struct drm_connector_funcs panel_bridge_connector_funcs = {
> .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
> };
>
> +static bool panel_bridge_is_tail(struct drm_bridge *bridge)
> +{
> + return true;
> +}
> +
> static int panel_bridge_attach(struct drm_bridge *bridge,
> struct drm_encoder *encoder,
> enum drm_bridge_attach_flags flags)
> @@ -206,6 +211,7 @@ static void panel_bridge_debugfs_init(struct drm_bridge *bridge,
> }
>
> static const struct drm_bridge_funcs panel_bridge_bridge_funcs = {
> + .is_tail = panel_bridge_is_tail,
> .attach = panel_bridge_attach,
> .detach = panel_bridge_detach,
> .atomic_pre_enable = panel_bridge_atomic_pre_enable,
> @@ -297,7 +303,7 @@ struct drm_bridge *drm_panel_bridge_add_typed(struct drm_panel *panel,
> panel_bridge->panel = panel;
>
> panel_bridge->bridge.of_node = panel->dev->of_node;
> - panel_bridge->bridge.ops = DRM_BRIDGE_OP_MODES;
> + panel_bridge->bridge.ops = DRM_BRIDGE_OP_MODES | DRM_BRIDGE_OP_IS_TAIL;
> panel_bridge->bridge.type = connector_type;
> panel_bridge->bridge.pre_enable_prev_first = panel->prepare_prev_first;
>
>
This looks reasonable
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Thanks,
Neil
^ permalink raw reply
* Re: (subset) [PATCH v3 1/3] dt-bindings: nvmem: lan9662-otpc: Add LAN969x series
From: Srinivas Kandagatla @ 2026-05-19 15:11 UTC (permalink / raw)
To: robh, krzk+dt, conor+dt, nicolas.ferre, claudiu.beznea,
horatiu.vultur, daniel.machon, devicetree, linux-kernel,
linux-arm-kernel, Robert Marko
Cc: luka.perkov, Conor Dooley
In-Reply-To: <20260515115954.701155-1-robimarko@gmail.com>
On Fri, 15 May 2026 13:59:07 +0200, Robert Marko wrote:
> Unlike LAN966x series which has 8K of OTP space, LAN969x series has 16K of
> OTP space, so document the compatible.
>
>
Applied, thanks!
[1/3] dt-bindings: nvmem: lan9662-otpc: Add LAN969x series
commit: dbb14a8de386286bd986513c89eefedd8471aa45
[2/3] nvmem: lan9662-otp: add support for LAN969x
commit: e5b013d742acf9894c9ec534bbc8ebf1a3dd3c64
Best regards,
--
Srinivas Kandagatla <srini@kernel.org>
^ permalink raw reply
* [PATCH v17 00/14] crypto/dmaengine: qce: introduce BAM locking and use DMA for register I/O
From: Bartosz Golaszewski @ 2026-05-19 13:17 UTC (permalink / raw)
To: Vinod Koul, Jonathan Corbet, Thara Gopinath, Herbert Xu,
David S. Miller, Udit Tiwari, Md Sadre Alam, Dmitry Baryshkov,
Manivannan Sadhasivam, Stephan Gerhold, Bjorn Andersson,
Peter Ujfalusi, Michal Simek, Frank Li, Andy Gross,
Neil Armstrong
Cc: dmaengine, linux-doc, linux-kernel, linux-arm-msm, linux-crypto,
linux-arm-kernel, brgl, Bartosz Golaszewski, Bartosz Golaszewski,
Dmitry Baryshkov, Konrad Dybcio
This revision addresses some issues pointed out by sashiko.
Merging strategy: there are build-time dependencies between the crypto
and DMA patches so the best approach is for Vinod to create an immutable
branch with the DMA part pulled in by the crypto tree.
This iteration continues to build on top of v12 but uses the BAM's NWD
bit on data descriptors as suggested by Stephan. To that end, there are
some more changes like reversing the order of command and data
descriptors queuedy by the QCE driver.
Currently the QCE crypto driver accesses the crypto engine registers
directly via CPU. Trust Zone may perform crypto operations simultaneously
resulting in a race condition. To remedy that, let's introduce support
for BAM locking/unlocking to the driver. The BAM driver will now wrap
any existing issued descriptor chains with additional descriptors
performing the locking when the client starts the transaction
(dmaengine_issue_pending()). The client wanting to profit from locking
needs to switch to performing register I/O over DMA and communicate the
address to which to perform the dummy writes via a call to
dmaengine_desc_attach_metadata().
In the specific case of the BAM DMA this translates to sending command
descriptors performing dummy writes with the relevant flags set. The BAM
will then lock all other pipes not related to the current pipe group, and
keep handling the current pipe only until it sees the the unlock bit.
In order for the locking to work correctly, we also need to switch to
using DMA for all register I/O.
On top of this, the series contains some additional tweaks and
refactoring.
The goal of this is not to improve the performance but to prepare the
driver for supporting decryption into secure buffers in the future.
Tested with tcrypt.ko, kcapi and cryptsetup.
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
---
Changes in v17:
- New patch: free the interrupt before disabling the clock in error path
in probe()
- New patch: cancel the QCE work on device detach
- Hold the channel lock when attaching the metadata
- Reorder the operations in devm_qce_dma_request() to avoid freeing
memory that may still be used by the DMA channel
- Register algorithms as the last step in QCE's probe() to avoid making
the resources available to the system before the DMA is fully set up
- Fix error paths in algo request handlers
- Don't pass dmaengine attributes to map_sg_attrs() as it expects
dma-mapping attribute flags
- Fix a dma mapping leak for command descriptors
- Rebase on top of v7.1-rc4
- Link to v16: https://patch.msgid.link/20260427-qcom-qce-cmd-descr-v16-0-945fd1cafbbc@oss.qualcomm.com
Changes in v16:
- Fix a reported race between dma_map_sg() called with spinlock taken
and the corresponding dma_unmap_sg() called without it by moving the
descriptor locking data into the descriptor struct
- Also queue the TX data descriptors before the command descriptors to
match what downstream is doing
- Tweak commit messages
- Rebase on top of v7.1-rc1
- Link to v15: https://patch.msgid.link/20260402-qcom-qce-cmd-descr-v15-0-98b5361f7ed7@oss.qualcomm.com
Changes in v15:
- Extend the descriptor metadata struct to also carry the channel's
transfer direction and stop using dmaengine_slave_config() for that
- Link to v14: https://patch.msgid.link/20260323-qcom-qce-cmd-descr-v14-0-f323af411274@oss.qualcomm.com
Changes in v14:
- Don't return an error to a client which wants to use locking on BAM
that doesn't support it
- Add a comment describing the DMA descriptor metadata structure
- Fix memory leaks
- Remove leftovers from previous iterations
- Propagate errors from dma_cookie_assign() when setting up lock
descriptors
- Link to v13: https://patch.msgid.link/20260317-qcom-qce-cmd-descr-v13-0-0968eb4f8c40@oss.qualcomm.com
Changes in v13:
- As part of the DMA changes in the QCE driver: reverse the order of
queueing the descriptors in the QCE driver: queue command descriptors
with all the register writes first, followed by all the data descriptors,
this is in line with the recommandations from the BAM HPG
- Set the NWD (notify-when-done) bit (DMA_PREP_FENCE in dmaengine
parlance) on the data descriptors to ensure that the UNLOCK descriptor
will not be processed until after they have been processed by the
engine. While technically the NWD bit is only needed on the final data
descriptor, it's hard to tell which one *will* be the last from the
driver's point-of-view and both the downstream driver as well as
the Qualcomm TZ against which we want to synchronize sets NWD on every
data descriptor,
- Revert to creating the LOCK/UNLOCK command descriptor pair in one
place now that the NWD bit is in place,
- Link to v12: https://patch.msgid.link/20260310-qcom-qce-cmd-descr-v12-0-398f37f26ef0@oss.qualcomm.com
Changes in v12:
- Wait until the transaction is done before queueing the UNLOCK command
descriptor
- Use descriptor metadata for communicating the scratchpad address to
the BAM driver
- To that end: reverse the order of the series (first BAM, then QCE) to
maintain bisectability
- Unmap buffers used for dummy writes after the transaction
- Link to v11: https://patch.msgid.link/20260302-qcom-qce-cmd-descr-v11-0-4bf1f5db4802@oss.qualcomm.com
Changes in v11:
- Use new approach, not requiring the client to be involved in locking.
- Add a patch constifying dma_descriptor_metadata_ops
- Rebase on top of v7.0-rc1
- Link to v10: https://lore.kernel.org/r/20251219-qcom-qce-cmd-descr-v10-0-ff7e4bf7dad4@oss.qualcomm.com
Changes in v10:
- Move DESC_FLAG_(UN)LOCK BIT definitions from patch 2 to 3
- Add a patch constifying the dma engine metadata as the first in the
series
- Use the VERSION register for dummy lock/unlock writes
- Link to v9: https://lore.kernel.org/r/20251128-qcom-qce-cmd-descr-v9-0-9a5f72b89722@linaro.org
Changes in v9:
- Drop the global, generic LOCK/UNLOCK flags and instead use DMA
descriptor metadata ops to pass BAM-specific information from the QCE
to the DMA engine
- Link to v8: https://lore.kernel.org/r/20251106-qcom-qce-cmd-descr-v8-0-ecddca23ca26@linaro.org
Changes in v8:
- Rework the command descriptor logic and drop a lot of unneeded code
- Use the physical address for BAM command descriptor access, not the
mapped DMA address
- Fix the problems with iommu faults on newer platforms
- Generalize the LOCK/UNLOCK flags in dmaengine and reword the docs and
commit messages
- Make the BAM locking logic stricter in the DMA engine driver
- Add some additional minor QCE driver refactoring changes to the series
- Lots of small reworks and tweaks to rebase on current mainline and fix
previous issues
- Link to v7: https://lore.kernel.org/all/20250311-qce-cmd-descr-v7-0-db613f5d9c9f@linaro.org/
Changes in v7:
- remove unused code: writing to multiple registers was not used in v6,
neither were the functions for reading registers over BAM DMA-
- remove
- don't read the SW_VERSION register needlessly in the BAM driver,
instead: encode the information on whether the IP supports BAM locking
in device match data
- shrink code where possible with logic modifications (for instance:
change the implementation of qce_write() instead of replacing it
everywhere with a new symbol)
- remove duplicated error messages
- rework commit messages
- a lot of shuffling code around for easier review and a more
streamlined series
- Link to v6: https://lore.kernel.org/all/20250115103004.3350561-1-quic_mdalam@quicinc.com/
Changes in v6:
- change "BAM" to "DMA"
- Ensured this series is compilable with the current Linux-next tip of
the tree (TOT).
Changes in v5:
- Added DMA_PREP_LOCK and DMA_PREP_UNLOCK flag support in separate patch
- Removed DMA_PREP_LOCK & DMA_PREP_UNLOCK flag
- Added FIELD_GET and GENMASK macro to extract major and minor version
Changes in v4:
- Added feature description and test hardware
with test command
- Fixed patch version numbering
- Dropped dt-binding patch
- Dropped device tree changes
- Added BAM_SW_VERSION register read
- Handled the error path for the api dma_map_resource()
in probe
- updated the commit messages for batter redability
- Squash the change where qce_bam_acquire_lock() and
qce_bam_release_lock() api got introduce to the change where
the lock/unlock flag get introced
- changed cover letter subject heading to
"dmaengine: qcom: bam_dma: add cmd descriptor support"
- Added the very initial post for BAM lock/unlock patch link
as v1 to track this feature
Changes in v3:
- https://lore.kernel.org/lkml/183d4f5e-e00a-8ef6-a589-f5704bc83d4a@quicinc.com/
- Addressed all the comments from v2
- Added the dt-binding
- Fix alignment issue
- Removed type casting from qce_write_reg_dma()
and qce_read_reg_dma()
- Removed qce_bam_txn = dma->qce_bam_txn; line from
qce_alloc_bam_txn() api and directly returning
dma->qce_bam_txn
Changes in v2:
- https://lore.kernel.org/lkml/20231214114239.2635325-1-quic_mdalam@quicinc.com/
- Initial set of patches for cmd descriptor support
- Add client driver to use BAM lock/unlock feature
- Added register read/write via BAM in QCE Crypto driver
to use BAM lock/unlock feature
---
Bartosz Golaszewski (14):
dmaengine: constify struct dma_descriptor_metadata_ops
dmaengine: qcom: bam_dma: free interrupt before the clock in error path
dmaengine: qcom: bam_dma: convert tasklet to a BH workqueue
dmaengine: qcom: bam_dma: Extend the driver's device match data
dmaengine: qcom: bam_dma: Add pipe_lock_supported flag support
dmaengine: qcom: bam_dma: add support for BAM locking
crypto: qce - Cancel work on device detach
crypto: qce - Include algapi.h in the core.h header
crypto: qce - Remove unused ignore_buf
crypto: qce - Simplify arguments of devm_qce_dma_request()
crypto: qce - Use existing devres APIs in devm_qce_dma_request()
crypto: qce - Map crypto memory for DMA
crypto: qce - Add BAM DMA support for crypto register I/O
crypto: qce - Communicate the base physical address to the dmaengine
drivers/crypto/qce/aead.c | 10 +-
drivers/crypto/qce/common.c | 20 ++--
drivers/crypto/qce/core.c | 38 ++++++-
drivers/crypto/qce/core.h | 11 ++
drivers/crypto/qce/dma.c | 168 +++++++++++++++++++++++------
drivers/crypto/qce/dma.h | 11 +-
drivers/crypto/qce/sha.c | 10 +-
drivers/crypto/qce/skcipher.c | 10 +-
drivers/dma/qcom/bam_dma.c | 228 +++++++++++++++++++++++++++++++++------
drivers/dma/ti/k3-udma.c | 2 +-
drivers/dma/xilinx/xilinx_dma.c | 2 +-
include/linux/dma/qcom_bam_dma.h | 14 +++
include/linux/dmaengine.h | 2 +-
13 files changed, 430 insertions(+), 96 deletions(-)
---
base-commit: b4a253871ac29e454a62b6746b0385d52cfe7b24
change-id: 20251103-qcom-qce-cmd-descr-c5e9b11fe609
Best regards,
--
Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
^ permalink raw reply
* Re: [PATCH v1] crypto: Use named initializers for struct i2c_device_id
From: Thorsten Blum @ 2026-05-19 15:08 UTC (permalink / raw)
To: Uwe Kleine-König (The Capable Hub)
Cc: Herbert Xu, David S. Miller, Nicolas Ferre, Alexandre Belloni,
Claudiu Beznea, linux-crypto, linux-arm-kernel, linux-kernel
In-Reply-To: <20260519141033.1586036-2-u.kleine-koenig@baylibre.com>
Hi Uwe,
On Tue, May 19, 2026 at 04:10:33PM +0200, Uwe Kleine-König (The Capable Hub) wrote:
> While being less compact, using named initializers allows to more easily
> see which members of the structs are assigned which value without having
> to lookup the declaration of the struct. And it's also more robust
> against changes to the struct definition.
>
> This patch doesn't modify the compiled arrays, only their representation
> in source form benefits. The former was confirmed with x86 and arm64
> builds.
>
> Signed-off-by: Uwe Kleine-König (The Capable Hub) <u.kleine-koenig@baylibre.com>
This part has changed recently, and your patch no longer applies. Please
see linux-next or Herbert's tree for the latest version.
atmel_sha204a_id[] now uses .driver_data, and atmel_ecc_id[] has been
extended by another entry.
Thanks,
Thorsten
^ permalink raw reply
* Re: [PATCH] arm64: futex: Consolidate 'old == new' check in __lsui_cmpxchg32()
From: Catalin Marinas @ 2026-05-19 15:09 UTC (permalink / raw)
To: Will Deacon; +Cc: linux-arm-kernel, Yeoreum Yun
In-Reply-To: <20260519090823.7216-1-will@kernel.org>
On Tue, May 19, 2026 at 10:08:22AM +0100, Will Deacon wrote:
> The LSUI futex implementation relies on a cmpxchg() loop to implement
> FUTEX_OP_XOR, as the architecture doesn't provide unprivileged *EOR
> atomics. Since the unprivileged 'CAST' instructions used to implement
> the cmpxchg() can only operate on 64-bit memory locations, the
> __lsui_cmpxchg32() helper function performs a song and dance to marshall
> the 32-bit futex value into the correct part of a 64-bit register and
> fill the remaining bytes with the neighbouring data.
IIRC, the reason for the current __lsui_cmpxchg32() was not EOR but the
expected futex_atomic_cmpxchg_inatomic() semantics. Looking at it again,
we have wake_futex_pi() that does something else if the ret is 0 but the
value differs. Looking at it again, the caller of wake_futex_pi()
retries on -EAGAIN anyway, so I don't see a correctness issue, it will
eventually hit the condition.
(Sashiko complains about the change but I think we can ignore it)
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
^ permalink raw reply
* Re: [PATCH v4 04/13] dma: swiotlb: track pool encryption state and honor DMA_ATTR_CC_SHARED
From: Aneesh Kumar K.V @ 2026-05-19 15:07 UTC (permalink / raw)
To: Mostafa Saleh
Cc: iommu, linux-arm-kernel, linux-kernel, linux-coco, Robin Murphy,
Marek Szyprowski, Will Deacon, Marc Zyngier, Steven Price,
Suzuki K Poulose, Catalin Marinas, Jiri Pirko, Jason Gunthorpe,
Petr Tesarik, Alexey Kardashevskiy, Dan Williams, Xu Yilun,
linuxppc-dev, linux-s390, Madhavan Srinivasan, Michael Ellerman,
Nicholas Piggin, Christophe Leroy (CS GROUP), Alexander Gordeev,
Gerald Schaefer, Heiko Carstens, Vasily Gorbik,
Christian Borntraeger, Sven Schnelle, x86
In-Reply-To: <yq5amrxvshxg.fsf@kernel.org>
Aneesh Kumar K.V <aneesh.kumar@kernel.org> writes:
> Mostafa Saleh <smostafa@google.com> writes:
>
>> On Thu, May 14, 2026 at 08:13:25PM +0530, Aneesh Kumar K.V wrote:
>>> >>
>>> >> What I meant was that we need a generic way to identify a pKVM guest, so
>>> >> that we can use it in the conditional above.
>>> >
>>> > I have this patch, with that I can boot with your series unmodified,
>>> > but I will need to do more testing.
>>> >
>>>
>>> Thanks, I can add this to the series once you complete the required testing.
>>>
>>
>> I am still running more tests, but looking more into it. Setting
>> force_dma_unencrypted() to true for pKVM guests is wrong, as the
>> guest shouldn’t try to decrypt arbitrary memory as it can include
>> sensitive information (for example in case of virtio sub-page
>> allocation) and should strictly rely on the restricted-dma-pool
>> for that.
>>
>> However, with my patch and setting force_dma_unencrypted() to false
>> on top of this series, it fails on pKVM due to a missing shared
>> attribute as Alexey mentioned, as now SWIOTLB rejects non shared
>> attrs, so, the DMA-API has to pass it. With that, I can boot again:
>>
>> diff --git a/kernel/dma/direct.c b/kernel/dma/direct.c
>> index 5103a04df99f..b19aeec03f27 100644
>> --- a/kernel/dma/direct.c
>> +++ b/kernel/dma/direct.c
>> @@ -286,6 +286,8 @@ void *dma_direct_alloc(struct device *dev, size_t size,
>> }
>>
>> if (is_swiotlb_for_alloc(dev)) {
>> + attrs |= DMA_ATTR_CC_SHARED;
>> +
>> page = dma_direct_alloc_swiotlb(dev, size, attrs);
>> if (page) {
>> /*
>> @@ -449,6 +451,8 @@ struct page *dma_direct_alloc_pages(struct device *dev, size_t size,
>> &cpu_addr, gfp, attrs);
>>
>> if (is_swiotlb_for_alloc(dev)) {
>> + attrs |= DMA_ATTR_CC_SHARED;
>> +
>> page = dma_direct_alloc_swiotlb(dev, size, attrs);
>> if (!page)
>> return NULL;
>> diff --git a/kernel/dma/direct.h b/kernel/dma/direct.h
>> index 4e35264ab6f8..8ee5bbf78cfb 100644
>> --- a/kernel/dma/direct.h
>> +++ b/kernel/dma/direct.h
>> @@ -92,6 +92,7 @@ static inline dma_addr_t dma_direct_map_phys(struct device *dev,
>> if (attrs & (DMA_ATTR_MMIO | DMA_ATTR_REQUIRE_COHERENT))
>> return DMA_MAPPING_ERROR;
>>
>> + attrs |= DMA_ATTR_CC_SHARED;
>> return swiotlb_map(dev, phys, size, dir, attrs);
>> }
>>
>> --
>>
>
> How about the below?
>
> modified kernel/dma/direct.c
> @@ -278,6 +278,10 @@ void *dma_direct_alloc(struct device *dev, size_t size,
> }
>
> if (is_swiotlb_for_alloc(dev)) {
> +
> + if (dev->dma_io_tlb_mem->unencrypted)
> + attrs |= DMA_ATTR_CC_SHARED;
> +
> page = dma_direct_alloc_swiotlb(dev, size, attrs);
> if (page) {
> /*
> @@ -451,6 +455,10 @@ struct page *dma_direct_alloc_pages(struct device *dev, size_t size,
> &cpu_addr, gfp, attrs);
>
> if (is_swiotlb_for_alloc(dev)) {
> +
> + if (dev->dma_io_tlb_mem->unencrypted)
> + attrs |= DMA_ATTR_CC_SHARED;
> +
> page = dma_direct_alloc_swiotlb(dev, size, attrs);
> if (!page)
> return NULL;
> modified kernel/dma/direct.h
> @@ -92,6 +92,9 @@ static inline dma_addr_t dma_direct_map_phys(struct device *dev,
> if (attrs & (DMA_ATTR_MMIO | DMA_ATTR_REQUIRE_COHERENT))
> return DMA_MAPPING_ERROR;
>
> + if (dev->dma_io_tlb_mem->unencrypted)
> + attrs |= DMA_ATTR_CC_SHARED;
> +
> return swiotlb_map(dev, phys, size, dir, attrs);
> }
>
>
>
if we get force_dma_unencrypted(dev) correct, we won't need the above.
for dma_direct_alloc and dma_direct_alloc_pages() we have
if (force_dma_unencrypted(dev))
attrs |= DMA_ATTR_CC_SHARED;
for dma_direct_map_phys(), if we have swiotlb bouncing forced,
swiotlb_tbl_map_single():
if ((attrs & DMA_ATTR_CC_SHARED) || force_dma_unencrypted(dev))
require_decrypted = true;
-aneesh
^ permalink raw reply
* [PATCH v9 2/4] firmware: ti_sci: add support for restoring IRQs during resume
From: Thomas Richard (TI) @ 2026-05-19 15:06 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Santosh Shilimkar, Michael Turquette,
Stephen Boyd, Brian Masney
Cc: Gregory CLEMENT, richard.genoud, Udit Kumar, Abhash Kumar,
Thomas Petazzoni, linux-arm-kernel, linux-kernel, linux-clk,
Thomas Richard (TI), Dhruva Gole, Kendall Willis
In-Reply-To: <20260519-ti-sci-jacinto-s2r-restore-irq-v9-0-c550a8ae0f31@bootlin.com>
Some DM-Firmware are not able to restore the IRQ context after a
suspend-resume. The IRQ_CONTEXT_LOST firmware capability has been
introduced to identify this characteristic. In this case the
responsibility is delegated to the ti_sci driver, which maintains an
internal list of all requested IRQs. This list is updated on each
set()/free() operation, and all IRQs are restored during the resume_noirq()
phase.
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Kendall Willis <k-willis@ti.com>
Signed-off-by: Thomas Richard (TI) <thomas.richard@bootlin.com>
---
drivers/firmware/ti_sci.c | 190 +++++++++++++++++++++++++++++++++++++++++++---
drivers/firmware/ti_sci.h | 3 +
2 files changed, 181 insertions(+), 12 deletions(-)
diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
index eaeaaae94142..e42cce4298a8 100644
--- a/drivers/firmware/ti_sci.c
+++ b/drivers/firmware/ti_sci.c
@@ -12,11 +12,13 @@
#include <linux/cpu.h>
#include <linux/debugfs.h>
#include <linux/export.h>
+#include <linux/hashtable.h>
#include <linux/io.h>
#include <linux/iopoll.h>
#include <linux/kernel.h>
#include <linux/mailbox_client.h>
#include <linux/module.h>
+#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
@@ -87,6 +89,16 @@ struct ti_sci_desc {
int max_msg_size;
};
+/**
+ * struct ti_sci_irq - Description of allocated irqs
+ * @node: Link to hash table
+ * @desc: Description of the irq
+ */
+struct ti_sci_irq {
+ struct hlist_node node;
+ struct ti_sci_msg_req_manage_irq desc;
+};
+
/**
* struct ti_sci_info - Structure representing a TI SCI instance
* @dev: Device pointer
@@ -101,6 +113,8 @@ struct ti_sci_desc {
* @chan_rx: Receive mailbox channel
* @minfo: Message info
* @node: list head
+ * @irqs: List of allocated irqs
+ * @irq_lock: Protection for irq hash list
* @host_id: Host ID
* @fw_caps: FW/SoC low power capabilities
* @users: Number of users of this instance
@@ -118,6 +132,8 @@ struct ti_sci_info {
struct mbox_chan *chan_rx;
struct ti_sci_xfers_info minfo;
struct list_head node;
+ DECLARE_HASHTABLE(irqs, 8);
+ struct mutex irq_lock;
u8 host_id;
u64 fw_caps;
/* protected by ti_sci_list_mutex */
@@ -2301,6 +2317,32 @@ static int ti_sci_manage_irq(const struct ti_sci_handle *handle,
return ret;
}
+/**
+ * ti_sci_irq_hash() - Helper API to compute irq hash for the hash table.
+ * @irq: irq to hash
+ *
+ * Return: the computed hash value.
+ */
+static int ti_sci_irq_hash(struct ti_sci_msg_req_manage_irq *irq)
+{
+ return irq->src_id ^ irq->src_index;
+}
+
+/**
+ * ti_sci_irq_equal() - Helper API to compare two irqs (generic headers are not
+ * compared)
+ * @irq_a: irq_a to compare
+ * @irq_b: irq_b to compare
+ *
+ * Return: true if the two irqs are equal, else false.
+ */
+static bool ti_sci_irq_equal(struct ti_sci_msg_req_manage_irq *irq_a,
+ struct ti_sci_msg_req_manage_irq *irq_b)
+{
+ return !memcmp(&irq_a->valid_params, &irq_b->valid_params,
+ sizeof(*irq_a) - sizeof(irq_a->hdr));
+}
+
/**
* ti_sci_set_irq() - Helper api to configure the irq route between the
* requested source and destination
@@ -2324,15 +2366,53 @@ static int ti_sci_set_irq(const struct ti_sci_handle *handle, u32 valid_params,
u16 dst_host_irq, u16 ia_id, u16 vint,
u16 global_event, u8 vint_status_bit, u8 s_host)
{
+ struct ti_sci_info *info = handle_to_ti_sci_info(handle);
+ struct ti_sci_msg_req_manage_irq *desc;
+ struct ti_sci_irq *irq;
+ int ret;
+
+ /* Lock for set_irq() and free_irq() to keep the IRQ hash list consistent */
+ guard(mutex)(&info->irq_lock);
+
pr_debug("%s: IRQ set with valid_params = 0x%x from src = %d, index = %d, to dst = %d, irq = %d,via ia_id = %d, vint = %d, global event = %d,status_bit = %d\n",
__func__, valid_params, src_id, src_index,
dst_id, dst_host_irq, ia_id, vint, global_event,
vint_status_bit);
- return ti_sci_manage_irq(handle, valid_params, src_id, src_index,
- dst_id, dst_host_irq, ia_id, vint,
- global_event, vint_status_bit, s_host,
- TI_SCI_MSG_SET_IRQ);
+ ret = ti_sci_manage_irq(handle, valid_params, src_id, src_index,
+ dst_id, dst_host_irq, ia_id, vint,
+ global_event, vint_status_bit, s_host,
+ TI_SCI_MSG_SET_IRQ);
+
+ if (ret || !(info->fw_caps & MSG_FLAG_CAPS_LPM_IRQ_CONTEXT_LOST))
+ goto end;
+
+ irq = kzalloc_obj(*irq, GFP_KERNEL);
+ if (!irq) {
+ ti_sci_manage_irq(handle, valid_params, src_id, src_index,
+ dst_id, dst_host_irq, ia_id, vint,
+ global_event, vint_status_bit, s_host,
+ TI_SCI_MSG_FREE_IRQ);
+ ret = -ENOMEM;
+ goto end;
+ }
+
+ desc = &irq->desc;
+ desc->valid_params = valid_params;
+ desc->src_id = src_id;
+ desc->src_index = src_index;
+ desc->dst_id = dst_id;
+ desc->dst_host_irq = dst_host_irq;
+ desc->ia_id = ia_id;
+ desc->vint = vint;
+ desc->global_event = global_event;
+ desc->vint_status_bit = vint_status_bit;
+ desc->secondary_host = s_host;
+
+ hash_add(info->irqs, &irq->node, ti_sci_irq_hash(desc));
+
+end:
+ return ret;
}
/**
@@ -2358,15 +2438,53 @@ static int ti_sci_free_irq(const struct ti_sci_handle *handle, u32 valid_params,
u16 dst_host_irq, u16 ia_id, u16 vint,
u16 global_event, u8 vint_status_bit, u8 s_host)
{
+ struct ti_sci_info *info = handle_to_ti_sci_info(handle);
+ struct ti_sci_msg_req_manage_irq irq_desc;
+ struct device *dev = info->dev;
+ struct ti_sci_irq *this_irq;
+ struct hlist_node *tmp_node;
+ int ret;
+
+ guard(mutex)(&info->irq_lock);
+
pr_debug("%s: IRQ release with valid_params = 0x%x from src = %d, index = %d, to dst = %d, irq = %d,via ia_id = %d, vint = %d, global event = %d,status_bit = %d\n",
__func__, valid_params, src_id, src_index,
dst_id, dst_host_irq, ia_id, vint, global_event,
vint_status_bit);
- return ti_sci_manage_irq(handle, valid_params, src_id, src_index,
- dst_id, dst_host_irq, ia_id, vint,
- global_event, vint_status_bit, s_host,
- TI_SCI_MSG_FREE_IRQ);
+ ret = ti_sci_manage_irq(handle, valid_params, src_id, src_index,
+ dst_id, dst_host_irq, ia_id, vint,
+ global_event, vint_status_bit, s_host,
+ TI_SCI_MSG_FREE_IRQ);
+
+ if (ret || !(info->fw_caps & MSG_FLAG_CAPS_LPM_IRQ_CONTEXT_LOST))
+ goto end;
+
+ irq_desc.valid_params = valid_params;
+ irq_desc.src_id = src_id;
+ irq_desc.src_index = src_index;
+ irq_desc.dst_id = dst_id;
+ irq_desc.dst_host_irq = dst_host_irq;
+ irq_desc.ia_id = ia_id;
+ irq_desc.vint = vint;
+ irq_desc.global_event = global_event;
+ irq_desc.vint_status_bit = vint_status_bit;
+ irq_desc.secondary_host = s_host;
+
+ hash_for_each_possible_safe(info->irqs, this_irq, tmp_node, node,
+ ti_sci_irq_hash(&irq_desc)) {
+ if (ti_sci_irq_equal(&irq_desc, &this_irq->desc)) {
+ hlist_del(&this_irq->node);
+ kfree(this_irq);
+ goto end;
+ }
+ }
+
+ dev_warn(dev, "%s: should not be here, IRQ was not found in hash list\n",
+ __func__);
+
+end:
+ return ret;
}
/**
@@ -3847,7 +3965,10 @@ static int ti_sci_suspend_noirq(struct device *dev)
static int ti_sci_resume_noirq(struct device *dev)
{
struct ti_sci_info *info = dev_get_drvdata(dev);
- int ret = 0;
+ struct ti_sci_msg_req_manage_irq *irq_desc;
+ struct ti_sci_irq *irq;
+ struct hlist_node *tmp_node;
+ int ret = 0, err = 0, i;
u32 source;
u64 time;
u8 pin;
@@ -3859,13 +3980,50 @@ static int ti_sci_resume_noirq(struct device *dev)
return ret;
}
+ switch (pm_suspend_target_state) {
+ case PM_SUSPEND_MEM:
+ if (info->fw_caps & MSG_FLAG_CAPS_LPM_IRQ_CONTEXT_LOST) {
+ hash_for_each_safe(info->irqs, i, tmp_node, irq, node) {
+ irq_desc = &irq->desc;
+ ret = ti_sci_manage_irq(&info->handle,
+ irq_desc->valid_params,
+ irq_desc->src_id,
+ irq_desc->src_index,
+ irq_desc->dst_id,
+ irq_desc->dst_host_irq,
+ irq_desc->ia_id,
+ irq_desc->vint,
+ irq_desc->global_event,
+ irq_desc->vint_status_bit,
+ irq_desc->secondary_host,
+ TI_SCI_MSG_SET_IRQ);
+ if (ret) {
+ dev_err(dev, "failed to restore IRQ with valid_params = 0x%x from src = %d, index = %d, to dst = %d, irq = %d, via ia_id = %d, vint = %d, global event = %d,status_bit = %d\n",
+ irq_desc->valid_params,
+ irq_desc->src_id,
+ irq_desc->src_index,
+ irq_desc->dst_id,
+ irq_desc->dst_host_irq,
+ irq_desc->ia_id,
+ irq_desc->vint,
+ irq_desc->global_event,
+ irq_desc->vint_status_bit);
+ err = ret;
+ }
+ }
+ }
+ break;
+ default:
+ break;
+ }
+
ret = ti_sci_msg_cmd_lpm_wake_reason(&info->handle, &source, &time, &pin, &mode);
/* Do not fail to resume on error as the wake reason is not critical */
if (!ret)
dev_info(dev, "ti_sci: wakeup source:0x%x, pin:0x%x, mode:0x%x\n",
source, pin, mode);
- return 0;
+ return err;
}
static void ti_sci_pm_complete(struct device *dev)
@@ -4014,13 +4172,14 @@ static int ti_sci_probe(struct platform_device *pdev)
}
ti_sci_msg_cmd_query_fw_caps(&info->handle, &info->fw_caps);
- dev_dbg(dev, "Detected firmware capabilities: %s%s%s%s%s%s\n",
+ dev_dbg(dev, "Detected firmware capabilities: %s%s%s%s%s%s%s\n",
info->fw_caps & MSG_FLAG_CAPS_GENERIC ? "Generic" : "",
info->fw_caps & MSG_FLAG_CAPS_LPM_PARTIAL_IO ? " Partial-IO" : "",
info->fw_caps & MSG_FLAG_CAPS_LPM_DM_MANAGED ? " DM-Managed" : "",
info->fw_caps & MSG_FLAG_CAPS_LPM_ABORT ? " LPM-Abort" : "",
info->fw_caps & MSG_FLAG_CAPS_IO_ISOLATION ? " IO-Isolation" : "",
- info->fw_caps & MSG_FLAG_CAPS_LPM_BOARDCFG_MANAGED ? " BoardConfig-Managed" : ""
+ info->fw_caps & MSG_FLAG_CAPS_LPM_BOARDCFG_MANAGED ? " BoardConfig-Managed" : "",
+ info->fw_caps & MSG_FLAG_CAPS_LPM_IRQ_CONTEXT_LOST ? " IRQ-Context-Lost" : ""
);
ti_sci_setup_ops(info);
@@ -4053,6 +4212,13 @@ static int ti_sci_probe(struct platform_device *pdev)
list_add_tail(&info->node, &ti_sci_list);
mutex_unlock(&ti_sci_list_mutex);
+ ret = devm_mutex_init(dev, &info->irq_lock);
+ if (ret)
+ goto out;
+
+ if (info->fw_caps & MSG_FLAG_CAPS_LPM_IRQ_CONTEXT_LOST)
+ hash_init(info->irqs);
+
ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
if (ret) {
dev_err(dev, "platform_populate failed %pe\n", ERR_PTR(ret));
diff --git a/drivers/firmware/ti_sci.h b/drivers/firmware/ti_sci.h
index d5e06769b01c..ad69c765d614 100644
--- a/drivers/firmware/ti_sci.h
+++ b/drivers/firmware/ti_sci.h
@@ -152,6 +152,8 @@ struct ti_sci_msg_req_reboot {
* MSG_FLAG_CAPS_IO_ISOLATION: IO Isolation support
* MSG_FLAG_CAPS_LPM_BOARDCFG_MANAGED: LPM config done statically
* for the DM via boardcfg
+ * MSG_FLAG_CAPS_LPM_IRQ_CONTEXT_LOST: DM is not able to restore IRQ
+ * context
*
* Response to a generic message with message type TI_SCI_MSG_QUERY_FW_CAPS
* providing currently available SOC/firmware capabilities. SoC that don't
@@ -165,6 +167,7 @@ struct ti_sci_msg_resp_query_fw_caps {
#define MSG_FLAG_CAPS_LPM_ABORT TI_SCI_MSG_FLAG(9)
#define MSG_FLAG_CAPS_IO_ISOLATION TI_SCI_MSG_FLAG(7)
#define MSG_FLAG_CAPS_LPM_BOARDCFG_MANAGED TI_SCI_MSG_FLAG(12)
+#define MSG_FLAG_CAPS_LPM_IRQ_CONTEXT_LOST TI_SCI_MSG_FLAG(14)
#define MSG_MASK_CAPS_LPM GENMASK_ULL(4, 1)
u64 fw_caps;
} __packed;
--
2.53.0
^ permalink raw reply related
* [PATCH v9 1/4] firmware: ti_sci: add BOARDCFG_MANAGED mode support
From: Thomas Richard (TI) @ 2026-05-19 15:06 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Santosh Shilimkar, Michael Turquette,
Stephen Boyd, Brian Masney
Cc: Gregory CLEMENT, richard.genoud, Udit Kumar, Abhash Kumar,
Thomas Petazzoni, linux-arm-kernel, linux-kernel, linux-clk,
Thomas Richard (TI), Dhruva Gole, Kendall Willis
In-Reply-To: <20260519-ti-sci-jacinto-s2r-restore-irq-v9-0-c550a8ae0f31@bootlin.com>
In BOARDCFG_MANAGED mode, the low power mode configuration is done
statically for the DM via the boardcfg. Constraints are not supported, and
prepare_sleep() is not needed.
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Kendall Willis <k-willis@ti.com>
Signed-off-by: Thomas Richard (TI) <thomas.richard@bootlin.com>
---
drivers/firmware/ti_sci.c | 10 +++++++---
drivers/firmware/ti_sci.h | 3 +++
2 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
index dd9911b1cc11..eaeaaae94142 100644
--- a/drivers/firmware/ti_sci.c
+++ b/drivers/firmware/ti_sci.c
@@ -3772,8 +3772,11 @@ static int ti_sci_prepare_system_suspend(struct ti_sci_info *info)
return ti_sci_cmd_prepare_sleep(&info->handle,
TISCI_MSG_VALUE_SLEEP_MODE_DM_MANAGED,
0, 0, 0);
+ } else if (info->fw_caps & MSG_FLAG_CAPS_LPM_BOARDCFG_MANAGED) {
+ /* Nothing to do in the BOARDCFG_MANAGED mode */
+ return 0;
} else {
- /* DM Managed is not supported by the firmware. */
+ /* DM Managed and BoardCfg Managed are not supported by the firmware. */
dev_err(info->dev, "Suspend to memory is not supported by the firmware\n");
return -EOPNOTSUPP;
}
@@ -4011,12 +4014,13 @@ static int ti_sci_probe(struct platform_device *pdev)
}
ti_sci_msg_cmd_query_fw_caps(&info->handle, &info->fw_caps);
- dev_dbg(dev, "Detected firmware capabilities: %s%s%s%s%s\n",
+ dev_dbg(dev, "Detected firmware capabilities: %s%s%s%s%s%s\n",
info->fw_caps & MSG_FLAG_CAPS_GENERIC ? "Generic" : "",
info->fw_caps & MSG_FLAG_CAPS_LPM_PARTIAL_IO ? " Partial-IO" : "",
info->fw_caps & MSG_FLAG_CAPS_LPM_DM_MANAGED ? " DM-Managed" : "",
info->fw_caps & MSG_FLAG_CAPS_LPM_ABORT ? " LPM-Abort" : "",
- info->fw_caps & MSG_FLAG_CAPS_IO_ISOLATION ? " IO-Isolation" : ""
+ info->fw_caps & MSG_FLAG_CAPS_IO_ISOLATION ? " IO-Isolation" : "",
+ info->fw_caps & MSG_FLAG_CAPS_LPM_BOARDCFG_MANAGED ? " BoardConfig-Managed" : ""
);
ti_sci_setup_ops(info);
diff --git a/drivers/firmware/ti_sci.h b/drivers/firmware/ti_sci.h
index 4616127e33ff..d5e06769b01c 100644
--- a/drivers/firmware/ti_sci.h
+++ b/drivers/firmware/ti_sci.h
@@ -150,6 +150,8 @@ struct ti_sci_msg_req_reboot {
* MSG_FLAG_CAPS_LPM_DM_MANAGED: LPM can be managed by DM
* MSG_FLAG_CAPS_LPM_ABORT: Abort entry to LPM
* MSG_FLAG_CAPS_IO_ISOLATION: IO Isolation support
+ * MSG_FLAG_CAPS_LPM_BOARDCFG_MANAGED: LPM config done statically
+ * for the DM via boardcfg
*
* Response to a generic message with message type TI_SCI_MSG_QUERY_FW_CAPS
* providing currently available SOC/firmware capabilities. SoC that don't
@@ -162,6 +164,7 @@ struct ti_sci_msg_resp_query_fw_caps {
#define MSG_FLAG_CAPS_LPM_DM_MANAGED TI_SCI_MSG_FLAG(5)
#define MSG_FLAG_CAPS_LPM_ABORT TI_SCI_MSG_FLAG(9)
#define MSG_FLAG_CAPS_IO_ISOLATION TI_SCI_MSG_FLAG(7)
+#define MSG_FLAG_CAPS_LPM_BOARDCFG_MANAGED TI_SCI_MSG_FLAG(12)
#define MSG_MASK_CAPS_LPM GENMASK_ULL(4, 1)
u64 fw_caps;
} __packed;
--
2.53.0
^ permalink raw reply related
* [PATCH v9 3/4] clk: keystone: sci-clk: add restore_context() operation
From: Thomas Richard (TI) @ 2026-05-19 15:06 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Santosh Shilimkar, Michael Turquette,
Stephen Boyd, Brian Masney
Cc: Gregory CLEMENT, richard.genoud, Udit Kumar, Abhash Kumar,
Thomas Petazzoni, linux-arm-kernel, linux-kernel, linux-clk,
Thomas Richard (TI), Dhruva Gole, Kendall Willis
In-Reply-To: <20260519-ti-sci-jacinto-s2r-restore-irq-v9-0-c550a8ae0f31@bootlin.com>
Implement the restore_context() operation to restore the clock rate and the
clock parent state. The clock rate is saved in sci_clk struct during
set_rate() and recalc_rate() operations. The parent index is saved in
sci_clk struct during set_parent() operation. During clock registration,
the core retrieves each clock’s parent using get_parent() operation to
ensure the internal clock tree reflects the actual hardware state,
including any configurations made by the bootloader. So we also save the
parent index in get_parent().
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Kendall Willis <k-willis@ti.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Brian Masney <bmasney@redhat.com>
Signed-off-by: Thomas Richard (TI) <thomas.richard@bootlin.com>
---
drivers/clk/keystone/sci-clk.c | 45 ++++++++++++++++++++++++++++++++++--------
1 file changed, 37 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/keystone/sci-clk.c b/drivers/clk/keystone/sci-clk.c
index 9d5071223f4c..7c0f7b3e89e0 100644
--- a/drivers/clk/keystone/sci-clk.c
+++ b/drivers/clk/keystone/sci-clk.c
@@ -47,6 +47,8 @@ struct sci_clk_provider {
* @node: Link for handling clocks probed via DT
* @cached_req: Cached requested freq for determine rate calls
* @cached_res: Cached result freq for determine rate calls
+ * @parent_id: Parent index for this clock
+ * @rate: Clock rate
*/
struct sci_clk {
struct clk_hw hw;
@@ -58,6 +60,8 @@ struct sci_clk {
struct list_head node;
unsigned long cached_req;
unsigned long cached_res;
+ int parent_id;
+ unsigned long rate;
};
#define to_sci_clk(_hw) container_of(_hw, struct sci_clk, hw)
@@ -150,6 +154,8 @@ static unsigned long sci_clk_recalc_rate(struct clk_hw *hw,
return 0;
}
+ clk->rate = freq;
+
return freq;
}
@@ -210,10 +216,15 @@ static int sci_clk_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct sci_clk *clk = to_sci_clk(hw);
+ int ret;
- return clk->provider->ops->set_freq(clk->provider->sci, clk->dev_id,
- clk->clk_id, rate / 10 * 9, rate,
- rate / 10 * 11);
+ ret = clk->provider->ops->set_freq(clk->provider->sci, clk->dev_id,
+ clk->clk_id, rate / 10 * 9, rate,
+ rate / 10 * 11);
+ if (!ret)
+ clk->rate = rate;
+
+ return ret;
}
/**
@@ -234,12 +245,13 @@ static u8 sci_clk_get_parent(struct clk_hw *hw)
dev_err(clk->provider->dev,
"get-parent failed for dev=%d, clk=%d, ret=%d\n",
clk->dev_id, clk->clk_id, ret);
+ clk->parent_id = ret;
return 0;
}
- parent_id = parent_id - clk->clk_id - 1;
+ clk->parent_id = parent_id - clk->clk_id - 1;
- return (u8)parent_id;
+ return (u8)clk->parent_id;
}
/**
@@ -252,12 +264,28 @@ static u8 sci_clk_get_parent(struct clk_hw *hw)
static int sci_clk_set_parent(struct clk_hw *hw, u8 index)
{
struct sci_clk *clk = to_sci_clk(hw);
+ int ret;
clk->cached_req = 0;
- return clk->provider->ops->set_parent(clk->provider->sci, clk->dev_id,
- clk->clk_id,
- index + 1 + clk->clk_id);
+ ret = clk->provider->ops->set_parent(clk->provider->sci, clk->dev_id,
+ clk->clk_id,
+ index + 1 + clk->clk_id);
+ if (!ret)
+ clk->parent_id = index;
+
+ return ret;
+}
+
+static void sci_clk_restore_context(struct clk_hw *hw)
+{
+ struct sci_clk *clk = to_sci_clk(hw);
+
+ if (clk->num_parents > 1 && clk->parent_id >= 0)
+ sci_clk_set_parent(hw, (u8)clk->parent_id);
+
+ if (clk->rate)
+ sci_clk_set_rate(hw, clk->rate, 0);
}
static const struct clk_ops sci_clk_ops = {
@@ -269,6 +297,7 @@ static const struct clk_ops sci_clk_ops = {
.set_rate = sci_clk_set_rate,
.get_parent = sci_clk_get_parent,
.set_parent = sci_clk_set_parent,
+ .restore_context = sci_clk_restore_context,
};
/**
--
2.53.0
^ permalink raw reply related
* [PATCH v9 4/4] firmware: ti_sci: add support for restoring clock context during resume
From: Thomas Richard (TI) @ 2026-05-19 15:06 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Santosh Shilimkar, Michael Turquette,
Stephen Boyd, Brian Masney
Cc: Gregory CLEMENT, richard.genoud, Udit Kumar, Abhash Kumar,
Thomas Petazzoni, linux-arm-kernel, linux-kernel, linux-clk,
Thomas Richard (TI), Dhruva Gole, Kendall Willis
In-Reply-To: <20260519-ti-sci-jacinto-s2r-restore-irq-v9-0-c550a8ae0f31@bootlin.com>
Some DM-Firmware are not able to restore the clock rates and the clock
parents after a suspend-resume. The CLK_CONTEXT_LOST firmware capability
has been introduced to identify this characteristic. In this case the
responsibility is therefore delegated to the ti_sci driver, which uses
clk_restore_context() to trigger the context_restore() operation for all
registered clocks, including those managed by the sci-clk. The sci-clk
driver implements the context_restore() operation to ensure rates and clock
parents are correctly restored.
Reviewed-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Kendall Willis <k-willis@ti.com>
Signed-off-by: Thomas Richard (TI) <thomas.richard@bootlin.com>
---
drivers/firmware/ti_sci.c | 9 +++++++--
drivers/firmware/ti_sci.h | 3 +++
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c
index e42cce4298a8..29caa33dbc4d 100644
--- a/drivers/firmware/ti_sci.c
+++ b/drivers/firmware/ti_sci.c
@@ -9,6 +9,7 @@
#define pr_fmt(fmt) "%s: " fmt, __func__
#include <linux/bitmap.h>
+#include <linux/clk.h>
#include <linux/cpu.h>
#include <linux/debugfs.h>
#include <linux/export.h>
@@ -4012,6 +4013,9 @@ static int ti_sci_resume_noirq(struct device *dev)
}
}
}
+
+ if (info->fw_caps & MSG_FLAG_CAPS_LPM_CLK_CONTEXT_LOST)
+ clk_restore_context();
break;
default:
break;
@@ -4172,14 +4176,15 @@ static int ti_sci_probe(struct platform_device *pdev)
}
ti_sci_msg_cmd_query_fw_caps(&info->handle, &info->fw_caps);
- dev_dbg(dev, "Detected firmware capabilities: %s%s%s%s%s%s%s\n",
+ dev_dbg(dev, "Detected firmware capabilities: %s%s%s%s%s%s%s%s\n",
info->fw_caps & MSG_FLAG_CAPS_GENERIC ? "Generic" : "",
info->fw_caps & MSG_FLAG_CAPS_LPM_PARTIAL_IO ? " Partial-IO" : "",
info->fw_caps & MSG_FLAG_CAPS_LPM_DM_MANAGED ? " DM-Managed" : "",
info->fw_caps & MSG_FLAG_CAPS_LPM_ABORT ? " LPM-Abort" : "",
info->fw_caps & MSG_FLAG_CAPS_IO_ISOLATION ? " IO-Isolation" : "",
info->fw_caps & MSG_FLAG_CAPS_LPM_BOARDCFG_MANAGED ? " BoardConfig-Managed" : "",
- info->fw_caps & MSG_FLAG_CAPS_LPM_IRQ_CONTEXT_LOST ? " IRQ-Context-Lost" : ""
+ info->fw_caps & MSG_FLAG_CAPS_LPM_IRQ_CONTEXT_LOST ? " IRQ-Context-Lost" : "",
+ info->fw_caps & MSG_FLAG_CAPS_LPM_CLK_CONTEXT_LOST ? " Clk-Context-Lost" : ""
);
ti_sci_setup_ops(info);
diff --git a/drivers/firmware/ti_sci.h b/drivers/firmware/ti_sci.h
index ad69c765d614..8fccbcd1c9a2 100644
--- a/drivers/firmware/ti_sci.h
+++ b/drivers/firmware/ti_sci.h
@@ -154,6 +154,8 @@ struct ti_sci_msg_req_reboot {
* for the DM via boardcfg
* MSG_FLAG_CAPS_LPM_IRQ_CONTEXT_LOST: DM is not able to restore IRQ
* context
+ * MSG_FLAG_CAPS_LPM_CLK_CONTEXT_LOST: DM is not able to restore
+ * Clock context
*
* Response to a generic message with message type TI_SCI_MSG_QUERY_FW_CAPS
* providing currently available SOC/firmware capabilities. SoC that don't
@@ -168,6 +170,7 @@ struct ti_sci_msg_resp_query_fw_caps {
#define MSG_FLAG_CAPS_IO_ISOLATION TI_SCI_MSG_FLAG(7)
#define MSG_FLAG_CAPS_LPM_BOARDCFG_MANAGED TI_SCI_MSG_FLAG(12)
#define MSG_FLAG_CAPS_LPM_IRQ_CONTEXT_LOST TI_SCI_MSG_FLAG(14)
+#define MSG_FLAG_CAPS_LPM_CLK_CONTEXT_LOST TI_SCI_MSG_FLAG(15)
#define MSG_MASK_CAPS_LPM GENMASK_ULL(4, 1)
u64 fw_caps;
} __packed;
--
2.53.0
^ permalink raw reply related
* [PATCH v9 0/4] firmware: ti_sci: Introduce BOARDCFG_MANAGED mode for Jacinto family
From: Thomas Richard (TI) @ 2026-05-19 15:06 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Santosh Shilimkar, Michael Turquette,
Stephen Boyd, Brian Masney
Cc: Gregory CLEMENT, richard.genoud, Udit Kumar, Abhash Kumar,
Thomas Petazzoni, linux-arm-kernel, linux-kernel, linux-clk,
Thomas Richard (TI), Dhruva Gole, Kendall Willis
This is the 9th iteration of this series. The only change is that now the
irq_lock mutex is used unconditionally in set_irq() and free_irq(). It
makes the code easier, and prevents coccinelle warnings.
Best Regards,
Thomas
Signed-off-by: Thomas Richard (TI) <thomas.richard@bootlin.com>
---
Changes in v9:
- ti_sci: use irq_lock mutex unconditionally (previously used only with IRQ-Context-Lost capability).
- Link to v8: https://lore.kernel.org/r/20260513-ti-sci-jacinto-s2r-restore-irq-v8-0-195b27f91519@bootlin.com
Changes in v8:
- ti_sci: fix error path if devm_mutex_init() fails.
- ti_sci: fix error message in ti_sci_resume_noirq().
- ti_sci: keep some lines under 100 chars in ti_sci header file.
- Link to v7: https://lore.kernel.org/r/20260506-ti-sci-jacinto-s2r-restore-irq-v7-0-037098a35215@bootlin.com
Changes in v7:
- ti_sci: add a lock around set_irq() and free_irq() to keep hash list
consistent.
- ti_sci: in free_irq() add warning in case we are in a path that shall not
be run.
- ti_sci: free an IRQ if we failed to add it in the hash list.
- ti_sci: during resume in case of error, try to restore remaining IRQs and
logs all errors, then return the latest one.
- sci-clk: add Stephen's AB tag and Brian's RB tag.
- sci-clk: handle get_parent() error, in restore_context() do not call
set_parent() with parent_id=0 if get_parent() failed.
- Link to v6: https://lore.kernel.org/r/20260427-ti-sci-jacinto-s2r-restore-irq-v6-0-72c6468cb2ab@bootlin.com
Changes in v6:
- rebase on v7.1-rc1.
- add Kendall's RB tag.
- sci-clk: call set_parent() during restore_context() only for clocks which
have more than one parent.
- sci-clk: save also rate returned by recalc_rate().
- Link to v5: https://lore.kernel.org/r/20260407-ti-sci-jacinto-s2r-restore-irq-v5-0-97b28f2d93f9@bootlin.com
Changes in v5:
- rebase on v7.0-rc7.
- add Dhruva's RB tag.
- use kzalloc_obj() in ti_sci driver.
- Link to v4: https://lore.kernel.org/r/20260204-ti-sci-jacinto-s2r-restore-irq-v4-0-67820af39eac@bootlin.com
Changes in v4:
- rebase on linux-next next-20260202.
- fix BOARDCFG_MANAGED value.
- add MSG_FLAG_CAPS_LPM_IRQ_CONTEXT_LOST firmware capability.
- add MSG_FLAG_CAPS_LPM_CLK_CONTEXT_LOST firmware capability.
- Link to v3: https://lore.kernel.org/r/20251205-ti-sci-jacinto-s2r-restore-irq-v3-0-d06963974ad4@bootlin.com
Changes in v3:
- rebased on linux-next
- sci-clk: context_restore() operation restores also rate.
- Link to v2: https://lore.kernel.org/r/20251127-ti-sci-jacinto-s2r-restore-irq-v2-0-a487fa3ff221@bootlin.com
Changes in v2:
- ti_sci: use hlist to store IRQs.
- sci-clk: add context_restore operation
- ti_sci: restore clock parents during resume
- Link to v1: https://lore.kernel.org/r/20251017-ti-sci-jacinto-s2r-restore-irq-v1-0-34d4339d247a@bootlin.com
---
Thomas Richard (TI) (4):
firmware: ti_sci: add BOARDCFG_MANAGED mode support
firmware: ti_sci: add support for restoring IRQs during resume
clk: keystone: sci-clk: add restore_context() operation
firmware: ti_sci: add support for restoring clock context during resume
drivers/clk/keystone/sci-clk.c | 45 +++++++--
drivers/firmware/ti_sci.c | 201 ++++++++++++++++++++++++++++++++++++++---
drivers/firmware/ti_sci.h | 9 ++
3 files changed, 234 insertions(+), 21 deletions(-)
---
base-commit: 5d4a179f6bf3628fd28a4d90fe26f387f8001b02
change-id: 20251010-ti-sci-jacinto-s2r-restore-irq-428e008fd10c
Best regards,
--
Thomas Richard (TI) <thomas.richard@bootlin.com>
^ permalink raw reply
* Re: [PATCH 6/8] drm/sun4i: hdmi: Use the common TMDS char rate constant
From: Chen-Yu Tsai @ 2026-05-19 14:57 UTC (permalink / raw)
To: Javier Martinez Canillas
Cc: linux-kernel, Maxime Ripard, David Airlie, Jernej Skrabec,
Maarten Lankhorst, Samuel Holland, Simona Vetter,
Thomas Zimmermann, dri-devel, linux-arm-kernel, linux-sunxi
In-Reply-To: <20260519144712.1418302-7-javierm@redhat.com>
On Tue, May 19, 2026 at 10:47 PM Javier Martinez Canillas
<javierm@redhat.com> wrote:
>
> Replace the 165000000 magic number with the shared constant defined
> in the <drm/display/drm_hdmi_helper.h> header.
>
> The old comment referenced "HDMI <= 1.2" but 165 MHz is actually
> the maximum TMDS character rate defined by the HDMI 1.0 spec.
>
> Suggested-by: Maxime Ripard <mripard@kernel.org>
> Signed-off-by: Javier Martinez Canillas <javierm@redhat.com>
Reviewed-by: Chen-Yu Tsai <wens@kernel.org>
^ permalink raw reply
* Re: [PATCH v4 0/5] nvmem: Add Raspberry Pi OTP nvmem driver
From: Stefan Wahren @ 2026-05-19 14:55 UTC (permalink / raw)
To: Gregor Herburger, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Florian Fainelli, Ray Jui, Scott Branden,
Broadcom internal kernel review list, Eric Anholt,
Srinivas Kandagatla, Kees Cook, Gustavo A. R. Silva
Cc: devicetree, linux-rpi-kernel, linux-arm-kernel, linux-kernel,
linux-hardening
In-Reply-To: <20260508-rpi-otp-driver-v4-0-cf8d725d8821@linutronix.de>
Hi Gregor,
Am 08.05.26 um 16:42 schrieb Gregor Herburger:
> Hi,
>
> This series adds support for the Raspberry Pis OTP registers. The
> Raspberry Pi has one or more OTP regions. These registers are accessible
> through the firmware. Add a driver for it and add updates the devicetree
> for the Raspberry Pi 5.
>
> ---
> Changes in v4:
> - Additional patch to drop unnecessary select schema
> - fix dt-bindings
> - use __counted_by_le
> - additional alignment check in read/write callbacks
> - Link to v3: https://patch.msgid.link/20260506-rpi-otp-driver-v3-0-294602663695@linutronix.de
>
> Changes in v3:
> - dts: add "raspberrypi,bcm2835-firmware" as fallback and fix dt-bindings
> - Fix Kconfig depends
> - Changed firmware data fields to __le32
> - Add MODULE_ALIAS
> - Link to v2: https://patch.msgid.link/20260505-rpi-otp-driver-v2-0-e9176ec72837@linutronix.de
>
> Changes in v2:
> - register nvmem driver from firmware driver and drop firmware sub nodes
> - Use struct_size and __counted_by for dynamic array
> - Drop unneeded comment in Kconfig
> - Use NVMEM_DEVID_NONE
> - Use kzalloc
> - Update module description
> - Link to v1: https://patch.msgid.link/20260408-rpi-otp-driver-v1-0-e02d1dbe6008@linutronix.de
>
> ---
> Gregor Herburger (5):
> dt-bindings: raspberrypi,bcm2835-firmware: Add bcm2712-firmware compatible
> nvmem: Add the Raspberry Pi OTP driver
> firmware: raspberrypi: register nvmem driver
> arm64: dts: broadcom: bcm2712: add raspberrypi,bcm2712-firmware compatible
> dt-bindings: raspberrypi,bcm2835-firmware: Drop unnecessary select
>
> .../arm/bcm/raspberrypi,bcm2835-firmware.yaml | 20 ++--
> .../boot/dts/broadcom/bcm2712-rpi-5-b-base.dtsi | 4 +-
> drivers/firmware/raspberrypi.c | 59 +++++++++-
> drivers/nvmem/Kconfig | 10 ++
> drivers/nvmem/Makefile | 1 +
> drivers/nvmem/raspberrypi-otp.c | 130 +++++++++++++++++++++
> include/soc/bcm2835/raspberrypi-firmware.h | 14 +++
> 7 files changed, 224 insertions(+), 14 deletions(-)
since you plan to submit a V5 of this series, could you please append
another patch to enable the driver as module for arm64/defconfig?
Thanks
^ permalink raw reply
* Re: [PATCH v2 2/3] clk: nuvoton: ma35d1: fix PLL_CTL1_FRAC bit field width and fractional calc
From: Brian Masney @ 2026-05-19 14:53 UTC (permalink / raw)
To: Joey Lu
Cc: mturquette, sboyd, ychuang3, schung, yclu4, linux-arm-kernel,
linux-clk, linux-kernel
In-Reply-To: <20260513055626.1070533-3-a0987203069@gmail.com>
Hi Joey,
On Wed, May 13, 2026 at 01:56:25PM +0800, Joey Lu wrote:
> PLL_CTL1_FRAC was defined as GENMASK(31, 24), covering only 8 bits.
> The hardware fractional field occupies bits [31:8] (24 bits), so the
> mask must be GENMASK(31, 8).
>
> The previous fractional-mode calculation used FIELD_MAX(PLL_CTL1_FRAC)
> as the denominator to obtain 2 decimal places. With the corrected 24-bit
> mask the old divisor is wrong; replace the arithmetic with a proper
> 24-bit fixed-point rounding to 3 decimal places:
>
> n_frac = n * 1000 + (x * 1000 + 500) >> 24
>
> The +500 term provides round-to-nearest before the right shift.
>
> Fixes: 691521a367cf ("clk: nuvoton: Add clock driver for ma35d1 clock controller")
> Signed-off-by: Joey Lu <a0987203069@gmail.com>
> ---
> drivers/clk/nuvoton/clk-ma35d1-pll.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/clk/nuvoton/clk-ma35d1-pll.c b/drivers/clk/nuvoton/clk-ma35d1-pll.c
> index bfedd45bd04b..7e6b30d20c01 100644
> --- a/drivers/clk/nuvoton/clk-ma35d1-pll.c
> +++ b/drivers/clk/nuvoton/clk-ma35d1-pll.c
> @@ -48,7 +48,7 @@
> #define PLL_CTL1_PD BIT(0)
> #define PLL_CTL1_BP BIT(1)
> #define PLL_CTL1_OUTDIV GENMASK(6, 4)
> -#define PLL_CTL1_FRAC GENMASK(31, 24)
> +#define PLL_CTL1_FRAC GENMASK(31, 8)
> #define PLL_CTL2_SLOPE GENMASK(23, 0)
>
> #define INDIV_MIN 1
> @@ -113,9 +113,9 @@ static unsigned long ma35d1_calc_pll_freq(u8 mode, u32 *reg_ctl, unsigned long p
> pll_freq = div_u64(pll_freq, m * p);
> } else {
> x = FIELD_GET(PLL_CTL1_FRAC, reg_ctl[1]);
> - /* 2 decimal places floating to integer (ex. 1.23 to 123) */
> - n = n * 100 + ((x * 100) / FIELD_MAX(PLL_CTL1_FRAC));
> - pll_freq = div_u64(parent_rate * n, 100 * m * p);
> + /* x is 24-bit fractional part, convert to 3 decimal digits */
> + n = n * 1000 + (u32)(((u64)x * 1000 + 500) >> 24);
^^^^^^^^^^^^^^^^^^^^^
You should be able to use DIV_ROUND_CLOSEST_ULL() here.
Brian
> + pll_freq = div_u64((u64)parent_rate * n, 1000 * m * p);
> }
> return pll_freq;
> }
> --
> 2.43.0
>
^ permalink raw reply
* Re: [PATCH v2 1/3] clk: nuvoton: ma35d1: fix ignored div_u64 return values in PLL freq calculation
From: Brian Masney @ 2026-05-19 14:51 UTC (permalink / raw)
To: Joey Lu
Cc: mturquette, sboyd, ychuang3, schung, yclu4, linux-arm-kernel,
linux-clk, linux-kernel
In-Reply-To: <20260513055626.1070533-2-a0987203069@gmail.com>
On Wed, May 13, 2026 at 01:56:24PM +0800, Joey Lu wrote:
> div_u64() does not modify its argument in place; the return value must
> be assigned. Both ma35d1_calc_smic_pll_freq() and ma35d1_calc_pll_freq()
> called div_u64() and discarded the result, leaving pll_freq holding the
> undivided product and thus returning a frequency orders of magnitude too
> high.
>
> Fixes: 691521a367cf ("clk: nuvoton: Add clock driver for ma35d1 clock controller")
> Signed-off-by: Joey Lu <a0987203069@gmail.com>
Reviewed-by: Brian Masney <bmasney@redhat.com>
^ permalink raw reply
* Re: [PATCH v4 04/13] dma: swiotlb: track pool encryption state and honor DMA_ATTR_CC_SHARED
From: Jason Gunthorpe @ 2026-05-19 14:49 UTC (permalink / raw)
To: Mostafa Saleh
Cc: Aneesh Kumar K.V, iommu, linux-arm-kernel, linux-kernel,
linux-coco, Robin Murphy, Marek Szyprowski, Will Deacon,
Marc Zyngier, Steven Price, Suzuki K Poulose, Catalin Marinas,
Jiri Pirko, Petr Tesarik, Alexey Kardashevskiy, Dan Williams,
Xu Yilun, linuxppc-dev, linux-s390, Madhavan Srinivasan,
Michael Ellerman, Nicholas Piggin, Christophe Leroy (CS GROUP),
Alexander Gordeev, Gerald Schaefer, Heiko Carstens, Vasily Gorbik,
Christian Borntraeger, Sven Schnelle, x86
In-Reply-To: <agx3j6Oc8QivZ3RG@google.com>
On Tue, May 19, 2026 at 02:45:35PM +0000, Mostafa Saleh wrote:
> However, it should not alway use SWIOTLB? It can trigger decryption for
> any memory returned from __dma_direct_alloc_pages() which can come
> from alloc_pages_node().
The alloc coherent flow is seperate and different, these are not pages
'passed into the DMA API' but pages fully allocated internally and
owned by it.
Yes, it should cause decrypted *allocation*.
Jason
^ permalink raw reply
* [PATCH 6/8] drm/sun4i: hdmi: Use the common TMDS char rate constant
From: Javier Martinez Canillas @ 2026-05-19 14:47 UTC (permalink / raw)
To: linux-kernel
Cc: Javier Martinez Canillas, Maxime Ripard, Chen-Yu Tsai,
David Airlie, Jernej Skrabec, Maarten Lankhorst, Samuel Holland,
Simona Vetter, Thomas Zimmermann, dri-devel, linux-arm-kernel,
linux-sunxi
In-Reply-To: <20260519144712.1418302-1-javierm@redhat.com>
Replace the 165000000 magic number with the shared constant defined
in the <drm/display/drm_hdmi_helper.h> header.
The old comment referenced "HDMI <= 1.2" but 165 MHz is actually
the maximum TMDS character rate defined by the HDMI 1.0 spec.
Suggested-by: Maxime Ripard <mripard@kernel.org>
Signed-off-by: Javier Martinez Canillas <javierm@redhat.com>
---
drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
index 07e2afcb4f95..723a6a11c94e 100644
--- a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
+++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
@@ -189,8 +189,8 @@ sun4i_hdmi_connector_clock_valid(const struct drm_connector *connector,
if (mode->flags & DRM_MODE_FLAG_DBLCLK)
return MODE_BAD;
- /* 165 MHz is the typical max pixelclock frequency for HDMI <= 1.2 */
- if (clock > 165000000)
+ /* HDMI 1.0 max TMDS character rate */
+ if (clock > DRM_HDMI_TMDS_CHAR_RATE_MAX_1_0)
return MODE_CLOCK_HIGH;
rounded_rate = clk_round_rate(hdmi->tmds_clk, clock);
--
2.54.0
^ permalink raw reply related
* [PATCH 0/8] drm/display: hdmi: Add common TMDS character rate constants
From: Javier Martinez Canillas @ 2026-05-19 14:46 UTC (permalink / raw)
To: linux-kernel
Cc: Javier Martinez Canillas, Abhinav Kumar, Alain Volmat,
Andrzej Hajda, Andy Yan, Brian Masney, Chen-Yu Tsai, Chris Morgan,
Cristian Ciocaltea, Daniel Stone, David Airlie, Dmitry Baryshkov,
Dmitry Baryshkov, Heiko Stuebner, Jani Nikula, Jernej Skrabec,
Jessica Zhang, Jonas Karlman, Konrad Dybcio, Laurent Pinchart,
Liu Ying, Luca Ceresoli, Maarten Lankhorst, Marijn Suijten,
Maxime Ripard, Neil Armstrong, Nicolas Frattaroli,
Raphael Gallais-Pou, Rob Clark, Robert Foss, Samuel Holland,
Sean Paul, Sebastian Reichel, Shengjiu Wang, Simona Vetter,
Thomas Zimmermann, dri-devel, freedreno, linux-arm-kernel,
linux-arm-msm, linux-sunxi
Several DRM drivers define their own local macros or use magic numbers for
the standard HDMI TMDS character rate limits. Maxime Ripard suggested that
instead these common rate constants could be included to a shared header.
This series introduces these constants to the <drm/display/drm_hdmi_helper.h>
header and replaces the local defined constants or magic numbers in drivers.
I split the changes as one patch per driver, so that these can be reviewed
individually and merged at their own pace.
Javier Martinez Canillas (8):
drm/display: hdmi: Add common TMDS character rate constants
drm/bridge: dw-hdmi: Use the common TMDS char rate constant
drm/bridge: dw-hdmi-qp: Use the common TMDS char rate constant
drm/bridge: inno-hdmi: Use the common TMDS char rate constant
drm/sti: hdmi: Use the common TMDS char rate constants
drm/sun4i: hdmi: Use the common TMDS char rate constant
drm/msm/hdmi: Use the common TMDS char rate constants in 8996 PHY
drm/msm/hdmi: Use the common TMDS char rate constants in 8998 PHY
drivers/gpu/drm/bridge/inno-hdmi.c | 4 +---
drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c | 6 ++----
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 10 ++++------
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c | 9 +++++----
drivers/gpu/drm/msm/hdmi/hdmi_phy_8998.c | 9 +++++----
drivers/gpu/drm/sti/sti_hdmi_tx3g4c28phy.c | 5 +++--
drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c | 4 ++--
include/drm/display/drm_hdmi_helper.h | 6 ++++++
8 files changed, 28 insertions(+), 25 deletions(-)
--
2.54.0
base-commit: fa81649af168a4d6d5260ed0fa9bbb5f6db3f11c
branch: add-common-tmds-rates
^ permalink raw reply
* Re: [PATCH v4 04/13] dma: swiotlb: track pool encryption state and honor DMA_ATTR_CC_SHARED
From: Mostafa Saleh @ 2026-05-19 14:45 UTC (permalink / raw)
To: Jason Gunthorpe
Cc: Aneesh Kumar K.V, iommu, linux-arm-kernel, linux-kernel,
linux-coco, Robin Murphy, Marek Szyprowski, Will Deacon,
Marc Zyngier, Steven Price, Suzuki K Poulose, Catalin Marinas,
Jiri Pirko, Petr Tesarik, Alexey Kardashevskiy, Dan Williams,
Xu Yilun, linuxppc-dev, linux-s390, Madhavan Srinivasan,
Michael Ellerman, Nicholas Piggin, Christophe Leroy (CS GROUP),
Alexander Gordeev, Gerald Schaefer, Heiko Carstens, Vasily Gorbik,
Christian Borntraeger, Sven Schnelle, x86
In-Reply-To: <20260519143529.GD7702@ziepe.ca>
On Tue, May 19, 2026 at 11:35:29AM -0300, Jason Gunthorpe wrote:
> On Tue, May 19, 2026 at 01:41:42PM +0000, Mostafa Saleh wrote:
> > On Tue, May 19, 2026 at 10:29:11AM -0300, Jason Gunthorpe wrote:
> > > On Tue, May 19, 2026 at 11:04:37AM +0000, Mostafa Saleh wrote:
> > > > On Thu, May 14, 2026 at 08:13:25PM +0530, Aneesh Kumar K.V wrote:
> > > > > >>
> > > > > >> What I meant was that we need a generic way to identify a pKVM guest, so
> > > > > >> that we can use it in the conditional above.
> > > > > >
> > > > > > I have this patch, with that I can boot with your series unmodified,
> > > > > > but I will need to do more testing.
> > > > > >
> > > > >
> > > > > Thanks, I can add this to the series once you complete the required testing.
> > > > >
> > > >
> > > > I am still running more tests, but looking more into it. Setting
> > > > force_dma_unencrypted() to true for pKVM guests is wrong, as the
> > > > guest shouldn’t try to decrypt arbitrary memory as it can include
> > > > sensitive information (for example in case of virtio sub-page
> > > > allocation) and should strictly rely on the restricted-dma-pool
> > > > for that.
> > >
> > > ??
> > >
> > > Where does force_dma_unencrypted() cause arbitary memory passed into
> > > the DMA API to be decrypted? That should never happen???
> >
> > Sorry, maybe arbitrary is not the right expression again :)
> > I mean that, with emulated devices that use the DMA-API under pKVM,
> > they will map memory coming from other layers (VFS, net) through
> > vitrio-block, virtio-net... These can be smaller than a page, and
> > using force_dma_unencrypted() will share the whole page.
>
> force_dma_unencrypted() should only trigger swiotlb and that never
> memcpy's more than necessary?
>
> Where does it do otherwise? That sounds like a bug?
Agh, I got confused and thought that it can be triggered from dma_map()
too. I need to figure out why that made pKVM guests boot with broken
restricted-dma-pool then.
However, it should not alway use SWIOTLB? It can trigger decryption for
any memory returned from __dma_direct_alloc_pages() which can come
from alloc_pages_node().
Thanks,
Mostafa
>
> Jason
^ permalink raw reply
* Re: [PATCH 2/2] arm64: dts: freescale: add initial device tree for TQMa8MPQS with i.MX8MP
From: Andrew Lunn @ 2026-05-19 14:44 UTC (permalink / raw)
To: Alexander Stein
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Geert Uytterhoeven, Magnus Damm, Shawn Guo, Paul Gerber,
devicetree, linux-kernel, imx, linux-arm-kernel, linux,
linux-renesas-soc
In-Reply-To: <5102480.31r3eYUQgx@steina-w>
On Tue, May 19, 2026 at 04:11:05PM +0200, Alexander Stein wrote:
> Am Dienstag, 5. Mai 2026, 17:02:12 CEST schrieb Andrew Lunn:
> > > +/* GBE1 */
> > > +&fec {
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&pinctrl_fec>;
> > > + phy-mode = "rgmii-id";
> > > + phy-handle = <ðphy3>;
> > > + fsl,magic-packet;
> >
> > One of my FAQs: Has WoL been tested?
>
> Well, I can "wake" the system per WoL. But resume stucks after CPUs are up
So probably not a networking problem, somebody elses problem, so this
is O.K. for me :-)
Thanks
Andrew
^ permalink raw reply
* [PATCH v23 8/8] arm64: dts: imx8mq: tqma8mq-mba8mx: Enable HDMI support
From: Laurentiu Palcu @ 2026-05-19 14:42 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: Laurentiu Palcu, dri-devel, devicetree, linux-kernel, linux-phy,
imx, linux-arm-kernel, linux, Alexander Stein, Ying Liu
In-Reply-To: <20260519-dcss-hdmi-upstreaming-v23-0-5615524a9c63@oss.nxp.com>
From: Alexander Stein <alexander.stein@ew.tq-group.com>
Add HDMI connector and connect it to MHDP output. Enable peripherals
for HDMI output.
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
---
.../boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts | 28 ++++++++++++++++++++++
arch/arm64/boot/dts/freescale/mba8mx.dtsi | 7 ++++++
2 files changed, 35 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts
index 0165f3a259853..4ea1c790bae46 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts
@@ -53,6 +53,10 @@ &btn2 {
gpios = <&gpio3 17 GPIO_ACTIVE_LOW>;
};
+&dcss {
+ status = "okay";
+};
+
&gpio_leds {
led3 {
label = "led3";
@@ -60,6 +64,16 @@ led3 {
};
};
+&hdmi_connector {
+ status = "okay";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&mhdp_out>;
+ };
+ };
+};
+
&i2c1 {
expander2: gpio@25 {
compatible = "nxp,pca9555";
@@ -91,6 +105,20 @@ &led2 {
gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
};
+&mhdp {
+ status = "okay";
+ ports {
+ port@1 {
+ reg = <1>;
+
+ mhdp_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ data-lanes = <0 1 2 3>;
+ };
+ };
+ };
+};
+
/* PCIe slot on X36 */
&pcie0 {
reset-gpio = <&expander0 14 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm64/boot/dts/freescale/mba8mx.dtsi b/arch/arm64/boot/dts/freescale/mba8mx.dtsi
index c24ae953cbc25..a723547dd71d1 100644
--- a/arch/arm64/boot/dts/freescale/mba8mx.dtsi
+++ b/arch/arm64/boot/dts/freescale/mba8mx.dtsi
@@ -89,6 +89,13 @@ gpio_delays: gpio-delays {
gpio-line-names = "LVDS_BRIDGE_EN_1V8";
};
+ hdmi_connector: connector {
+ compatible = "hdmi-connector";
+ label = "X11";
+ type = "a";
+ status = "disabled";
+ };
+
panel: panel-lvds {
/*
* Display is not fixed, so compatible has to be added from
--
2.51.0
^ permalink raw reply related
* [PATCH v23 6/8] drm: bridge: Cadence: Add MHDP8501 DP/HDMI driver
From: Laurentiu Palcu @ 2026-05-19 14:42 UTC (permalink / raw)
To: Parshuram Thombare, Swapnil Jakhade, Dmitry Baryshkov,
Nikhil Devshatwar, Jayesh Choudhary, Andrzej Hajda,
Neil Armstrong, Robert Foss, Laurent Pinchart, Jonas Karlman,
Jernej Skrabec, Luca Ceresoli, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter
Cc: Laurentiu Palcu, dri-devel, devicetree, linux-kernel, linux-phy,
imx, linux-arm-kernel, linux, Alexander Stein, Ying Liu
In-Reply-To: <20260519-dcss-hdmi-upstreaming-v23-0-5615524a9c63@oss.nxp.com>
From: Sandor Yu <Sandor.yu@nxp.com>
Add a new DRM DisplayPort and HDMI bridge driver for Candence MHDP8501
used in i.MX8MQ SOC. MHDP8501 could support HDMI or DisplayPort
standards according embedded Firmware running in the uCPU.
For iMX8MQ SOC, the DisplayPort/HDMI FW was loaded and activated by
SOC's ROM code. Bootload binary included respective specific firmware
is required.
Driver will check display connector type and
then load the corresponding driver.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Co-developed-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
---
To: Parshuram Thombare <pthombar@cadence.com>
To: Swapnil Jakhade <sjakhade@cadence.com>
To: Dmitry Baryshkov <lumag@kernel.org>
To: Nikhil Devshatwar <nikhil.nd@ti.com>
To: Jayesh Choudhary <j-choudhary@ti.com>
---
drivers/gpu/drm/bridge/cadence/Kconfig | 16 +
drivers/gpu/drm/bridge/cadence/Makefile | 2 +
.../gpu/drm/bridge/cadence/cdns-mhdp8501-core.c | 447 ++++++++++++
.../gpu/drm/bridge/cadence/cdns-mhdp8501-core.h | 391 ++++++++++
drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-dp.c | 725 +++++++++++++++++++
.../gpu/drm/bridge/cadence/cdns-mhdp8501-hdmi.c | 805 +++++++++++++++++++++
6 files changed, 2386 insertions(+)
diff --git a/drivers/gpu/drm/bridge/cadence/Kconfig b/drivers/gpu/drm/bridge/cadence/Kconfig
index 2ff261e18bf1c..233a220d5368a 100644
--- a/drivers/gpu/drm/bridge/cadence/Kconfig
+++ b/drivers/gpu/drm/bridge/cadence/Kconfig
@@ -49,3 +49,19 @@ config DRM_CDNS_MHDP8546_J721E
initializes the J721E Display Port and sets up the
clock and data muxes.
endif
+
+config DRM_CDNS_MHDP8501
+ tristate "Cadence MHDP8501 DP/HDMI bridge"
+ select DRM_KMS_HELPER
+ select DRM_PANEL_BRIDGE
+ select DRM_DISPLAY_DP_HELPER
+ select DRM_DISPLAY_HELPER
+ select DRM_DISPLAY_HDMI_STATE_HELPER
+ select CDNS_MHDP_HELPER
+ depends on OF
+ help
+ Support Cadence MHDP8501 DisplayPort/HDMI bridge.
+ Cadence MHDP8501 support one or more protocols,
+ including DisplayPort and HDMI.
+ To use the DP and HDMI drivers, their respective
+ specific firmware is required.
diff --git a/drivers/gpu/drm/bridge/cadence/Makefile b/drivers/gpu/drm/bridge/cadence/Makefile
index c95fd5b81d137..ea327287d1c14 100644
--- a/drivers/gpu/drm/bridge/cadence/Makefile
+++ b/drivers/gpu/drm/bridge/cadence/Makefile
@@ -5,3 +5,5 @@ cdns-dsi-$(CONFIG_DRM_CDNS_DSI_J721E) += cdns-dsi-j721e.o
obj-$(CONFIG_DRM_CDNS_MHDP8546) += cdns-mhdp8546.o
cdns-mhdp8546-y := cdns-mhdp8546-core.o cdns-mhdp8546-hdcp.o
cdns-mhdp8546-$(CONFIG_DRM_CDNS_MHDP8546_J721E) += cdns-mhdp8546-j721e.o
+obj-$(CONFIG_DRM_CDNS_MHDP8501) += cdns-mhdp8501.o
+cdns-mhdp8501-y := cdns-mhdp8501-core.o cdns-mhdp8501-dp.o cdns-mhdp8501-hdmi.o
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-core.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-core.c
new file mode 100644
index 0000000000000..6e05e96ad322e
--- /dev/null
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-core.c
@@ -0,0 +1,447 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Cadence Display Port Interface (DP) driver
+ *
+ * Copyright (C) 2023-2026 NXP Semiconductor, Inc.
+ *
+ */
+#include <drm/drm_of.h>
+#include <drm/drm_print.h>
+#include <linux/clk.h>
+#include <linux/debugfs.h>
+#include <linux/irq.h>
+#include <linux/mutex.h>
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/phy/phy.h>
+
+#include "cdns-mhdp8501-core.h"
+
+static int firmware_version_show(struct seq_file *s, void *data)
+{
+ struct cdns_mhdp8501_device *mhdp = s->private;
+
+ u32 version = readl(mhdp->base.regs + VER_L) | readl(mhdp->base.regs + VER_H) << 8;
+ u32 lib_version = readl(mhdp->base.regs + VER_LIB_L_ADDR) |
+ readl(mhdp->base.regs + VER_LIB_H_ADDR) << 8;
+
+ seq_printf(s, "FW version %d, Lib version %d\n", version, lib_version);
+
+ return 0;
+}
+DEFINE_SHOW_ATTRIBUTE(firmware_version);
+
+static void cdns_mhdp8501_debugfs_init(struct cdns_mhdp8501_device *mhdp)
+{
+ mhdp->debugfs = debugfs_create_dir(dev_name(mhdp->dev), NULL);
+
+ debugfs_create_file("firmware_version", 0444, mhdp->debugfs,
+ mhdp, &firmware_version_fops);
+}
+
+static void cdns_mhdp8501_debugfs_cleanup(struct cdns_mhdp8501_device *mhdp)
+{
+ debugfs_remove_recursive(mhdp->debugfs);
+}
+
+static int cdns_mhdp8501_read_hpd(struct cdns_mhdp8501_device *mhdp)
+{
+ u8 status = 0xff;
+ int ret;
+
+ ret = cdns_mhdp_mailbox_send_recv(&mhdp->base, MB_MODULE_ID_GENERAL,
+ GENERAL_GET_HPD_STATE,
+ 0, NULL, sizeof(status), &status);
+ if (ret) {
+ dev_err(mhdp->dev, "read hpd failed: %d\n", ret);
+ return ret;
+ }
+
+ return status;
+}
+
+enum drm_connector_status cdns_mhdp8501_detect(struct drm_bridge *bridge,
+ struct drm_connector *connector)
+{
+ struct cdns_mhdp8501_device *mhdp = bridge_to_mhdp(bridge);
+ int hpd;
+
+ hpd = cdns_mhdp8501_read_hpd(mhdp);
+
+ if (hpd == 1)
+ return connector_status_connected;
+ else if (hpd == 0)
+ return connector_status_disconnected;
+
+ return connector_status_unknown;
+}
+
+enum drm_mode_status
+cdns_mhdp8501_mode_valid(struct drm_bridge *bridge,
+ const struct drm_display_info *info,
+ const struct drm_display_mode *mode)
+{
+ /* We don't support double-clocked */
+ if (mode->flags & DRM_MODE_FLAG_DBLCLK)
+ return MODE_BAD;
+
+ /* MAX support pixel clock rate 594MHz */
+ if (mode->clock > 594000)
+ return MODE_CLOCK_HIGH;
+
+ if (mode->hdisplay > 3840)
+ return MODE_BAD_HVALUE;
+
+ if (mode->vdisplay > 2160)
+ return MODE_BAD_VVALUE;
+
+ return MODE_OK;
+}
+
+static void hotplug_work_func(struct work_struct *work)
+{
+ struct cdns_mhdp8501_device *mhdp = container_of(work,
+ struct cdns_mhdp8501_device,
+ hotplug_work.work);
+ enum drm_connector_status status = cdns_mhdp8501_detect(&mhdp->bridge,
+ NULL);
+
+ /*
+ * iMX8MQ has two HPD interrupts: one for plugout and one for plugin.
+ * These interrupts cannot be masked and cleaned, so we must enable one
+ * and disable the other to avoid continuous interrupt generation.
+ */
+ if (status == connector_status_connected) {
+ /* Cable connected */
+ dev_dbg(mhdp->dev, "HDMI/DP Cable Plug In\n");
+ drm_bridge_hpd_notify(&mhdp->bridge, status);
+ if (!READ_ONCE(mhdp->removing))
+ enable_irq(mhdp->irq[IRQ_OUT]);
+
+ /* Reset HDMI/DP link with sink */
+ if (mhdp->bridge_type == DRM_MODE_CONNECTOR_HDMIA)
+ cdns_hdmi_handle_hotplug(mhdp);
+ else
+ cdns_dp_check_link_state(mhdp);
+ } else if (status == connector_status_disconnected) {
+ /* Cable Disconnected */
+ dev_dbg(mhdp->dev, "HDMI/DP Cable Plug Out\n");
+ drm_bridge_hpd_notify(&mhdp->bridge, status);
+ if (!READ_ONCE(mhdp->removing))
+ enable_irq(mhdp->irq[IRQ_IN]);
+ } else {
+ /* HPD state read failed, retry to avoid losing HPD */
+ dev_warn(mhdp->dev, "failed to read HPD state, retrying\n");
+ mod_delayed_work(system_wq, &mhdp->hotplug_work,
+ msecs_to_jiffies(HOTPLUG_DEBOUNCE_MS));
+ }
+}
+
+static irqreturn_t cdns_mhdp8501_irq_thread(int irq, void *data)
+{
+ struct cdns_mhdp8501_device *mhdp = data;
+
+ disable_irq_nosync(irq);
+
+ mod_delayed_work(system_wq, &mhdp->hotplug_work,
+ msecs_to_jiffies(HOTPLUG_DEBOUNCE_MS));
+
+ return IRQ_HANDLED;
+}
+
+#define DATA_LANES_COUNT 4
+static int cdns_mhdp8501_dt_parse(struct platform_device *pdev,
+ u32 *lane_mapping)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ u32 data_lanes[DATA_LANES_COUNT];
+ struct device_node *endpoint;
+ int ret, i;
+
+ endpoint = of_graph_get_endpoint_by_regs(np, 1, -1);
+ if (!endpoint) {
+ dev_err(dev, "missing port@1 endpoint\n");
+ return -ENODEV;
+ }
+
+ ret = drm_of_get_data_lanes_count(endpoint, DATA_LANES_COUNT,
+ DATA_LANES_COUNT);
+ if (ret < 0) {
+ dev_err(dev, "expected 4 data lanes\n");
+ of_node_put(endpoint);
+ return ret;
+ }
+
+ ret = of_property_read_u32_array(endpoint, "data-lanes",
+ data_lanes, DATA_LANES_COUNT);
+ of_node_put(endpoint);
+ if (ret)
+ return ret;
+
+ *lane_mapping = 0;
+ for (i = 0; i < DATA_LANES_COUNT; i++) {
+ if (data_lanes[i] > 3) {
+ dev_err(dev, "invalid lane index %u at position %d\n",
+ data_lanes[i], i);
+ return -EINVAL;
+ }
+ *lane_mapping |= data_lanes[i] << (i * 2);
+ }
+
+ return 0;
+}
+
+static int cdns_mhdp8501_add_bridge(struct cdns_mhdp8501_device *mhdp)
+{
+ mhdp->bridge.type = mhdp->bridge_type;
+ mhdp->bridge.of_node = mhdp->dev->of_node;
+ mhdp->bridge.vendor = "NXP";
+ mhdp->bridge.product = "i.MX8";
+ mhdp->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID |
+ DRM_BRIDGE_OP_HPD;
+
+ if (mhdp->bridge_type == DRM_MODE_CONNECTOR_HDMIA) {
+ mhdp->bridge.ops |= DRM_BRIDGE_OP_HDMI;
+ mhdp->bridge.ddc = cdns_hdmi_i2c_adapter(mhdp);
+ if (IS_ERR(mhdp->bridge.ddc))
+ return PTR_ERR(mhdp->bridge.ddc);
+ }
+
+ drm_bridge_add(&mhdp->bridge);
+
+ return 0;
+}
+
+static int cdns_mhdp8501_probe(struct platform_device *pdev)
+{
+ const struct drm_bridge_funcs *bridge_funcs;
+ struct cdns_mhdp8501_device *mhdp;
+ struct device *dev = &pdev->dev;
+ struct device_node *remote;
+ enum phy_mode phy_mode;
+ struct resource *res;
+ u32 lane_mapping;
+ int bridge_type;
+ u32 reg;
+ int ret;
+
+ bridge_type = (int)(uintptr_t)of_device_get_match_data(dev);
+
+ ret = cdns_mhdp8501_dt_parse(pdev, &lane_mapping);
+ if (ret < 0)
+ return ret;
+
+ ret = devm_of_platform_populate(dev);
+ if (ret)
+ return ret;
+
+ bridge_funcs = (bridge_type == DRM_MODE_CONNECTOR_HDMIA) ?
+ &cdns_hdmi_bridge_funcs : &cdns_dp_bridge_funcs;
+
+ mhdp = devm_drm_bridge_alloc(dev, struct cdns_mhdp8501_device,
+ bridge, bridge_funcs);
+ if (!mhdp)
+ return -ENOMEM;
+
+ mhdp->dev = dev;
+ mhdp->bridge_type = bridge_type;
+ mhdp->lane_mapping = lane_mapping;
+
+ remote = of_graph_get_remote_node(dev->of_node, 1, 0);
+ if (!remote)
+ return dev_err_probe(dev, -ENODEV,
+ "failed to find remote bridge node\n");
+
+ mhdp->bridge.next_bridge = of_drm_find_and_get_bridge(remote);
+ of_node_put(remote);
+ if (!mhdp->bridge.next_bridge)
+ return dev_err_probe(dev, -EPROBE_DEFER,
+ "failed to get next bridge\n");
+
+ INIT_DELAYED_WORK(&mhdp->hotplug_work, hotplug_work_func);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res)
+ return -ENODEV;
+
+ mhdp->regs = devm_ioremap(dev, res->start, resource_size(res));
+ if (!mhdp->regs)
+ return -ENOMEM;
+
+ /* init base struct for access mhdp mailbox */
+ mhdp->base.dev = mhdp->dev;
+ mhdp->base.regs = mhdp->regs;
+ mutex_init(&mhdp->base.mailbox_mutex);
+ mutex_init(&mhdp->link_mutex);
+
+ /*
+ * Store &mhdp->base as drvdata so child devices (e.g. the PHY) can
+ * retrieve the shared cdns_mhdp_base, including the mailbox_mutex.
+ */
+ dev_set_drvdata(dev, &mhdp->base);
+
+ mhdp->phy = devm_of_phy_get_by_index(dev, pdev->dev.of_node, 0);
+ if (IS_ERR(mhdp->phy)) {
+ ret = dev_err_probe(dev, PTR_ERR(mhdp->phy), "no PHY configured\n");
+ goto err_mutex;
+ }
+
+ mhdp->irq[IRQ_IN] = platform_get_irq_byname(pdev, "plug_in");
+ if (mhdp->irq[IRQ_IN] < 0) {
+ ret = dev_err_probe(dev, mhdp->irq[IRQ_IN], "No plug_in irq number\n");
+ goto err_mutex;
+ }
+
+ mhdp->irq[IRQ_OUT] = platform_get_irq_byname(pdev, "plug_out");
+ if (mhdp->irq[IRQ_OUT] < 0) {
+ ret = dev_err_probe(dev, mhdp->irq[IRQ_OUT], "No plug_out irq number\n");
+ goto err_mutex;
+ }
+
+ irq_set_status_flags(mhdp->irq[IRQ_IN], IRQ_NOAUTOEN);
+ ret = devm_request_threaded_irq(dev, mhdp->irq[IRQ_IN],
+ NULL, cdns_mhdp8501_irq_thread,
+ IRQF_ONESHOT, dev_name(dev), mhdp);
+ if (ret < 0) {
+ dev_err(dev, "can't claim irq %d\n", mhdp->irq[IRQ_IN]);
+ ret = -EINVAL;
+ goto err_mutex;
+ }
+
+ irq_set_status_flags(mhdp->irq[IRQ_OUT], IRQ_NOAUTOEN);
+ ret = devm_request_threaded_irq(dev, mhdp->irq[IRQ_OUT],
+ NULL, cdns_mhdp8501_irq_thread,
+ IRQF_ONESHOT, dev_name(dev), mhdp);
+ if (ret < 0) {
+ dev_err(dev, "can't claim irq %d\n", mhdp->irq[IRQ_OUT]);
+ ret = -EINVAL;
+ goto err_mutex;
+ }
+
+ if (mhdp->bridge_type == DRM_MODE_CONNECTOR_DisplayPort)
+ phy_mode = PHY_MODE_DP;
+ else if (mhdp->bridge_type == DRM_MODE_CONNECTOR_HDMIA)
+ phy_mode = PHY_MODE_HDMI;
+
+ if (mhdp->bridge_type == DRM_MODE_CONNECTOR_DisplayPort) {
+ drm_dp_aux_init(&mhdp->dp.aux);
+ mhdp->dp.aux.name = "mhdp8501_dp_aux";
+ mhdp->dp.aux.dev = dev;
+ mhdp->dp.aux.transfer = cdns_dp_aux_transfer;
+ }
+
+ /* Enable APB clock */
+ mhdp->apb_clk = devm_clk_get_enabled(dev, NULL);
+ if (IS_ERR(mhdp->apb_clk)) {
+ ret = dev_err_probe(dev, PTR_ERR(mhdp->apb_clk),
+ "couldn't get apb clk\n");
+ goto err_mutex;
+ }
+
+ /*
+ * Wait for the KEEP_ALIVE "message" on the first 8 bits.
+ * Updated each sched "tick" (~2ms)
+ */
+ ret = readl_poll_timeout(mhdp->regs + KEEP_ALIVE, reg,
+ reg & CDNS_KEEP_ALIVE_MASK, 500,
+ CDNS_KEEP_ALIVE_TIMEOUT);
+ if (ret) {
+ dev_err(dev, "device didn't give any life sign: reg %d\n", reg);
+ goto err_mutex;
+ }
+
+ /*
+ * Create debugfs only after the APB clock is on and the firmware is
+ * confirmed running. A concurrent read of firmware_version before
+ * this point would access clock-gated registers and cause a bus fault.
+ */
+ cdns_mhdp8501_debugfs_init(mhdp);
+
+ ret = phy_init(mhdp->phy);
+ if (ret) {
+ dev_err(dev, "Failed to initialize PHY: %d\n", ret);
+ goto err_debugfs;
+ }
+
+ ret = phy_set_mode(mhdp->phy, phy_mode);
+ if (ret) {
+ dev_err(dev, "Failed to configure PHY: %d\n", ret);
+ goto err_phy;
+ }
+
+ ret = cdns_mhdp8501_add_bridge(mhdp);
+ if (ret)
+ goto err_phy;
+
+ /* Enable cable hotplug detect */
+ ret = cdns_mhdp8501_read_hpd(mhdp);
+ if (ret < 0)
+ goto err_bridge;
+
+ if (ret == 1)
+ enable_irq(mhdp->irq[IRQ_OUT]);
+ else
+ enable_irq(mhdp->irq[IRQ_IN]);
+
+ return 0;
+
+err_bridge:
+ drm_bridge_remove(&mhdp->bridge);
+err_phy:
+ phy_exit(mhdp->phy);
+err_debugfs:
+ cdns_mhdp8501_debugfs_cleanup(mhdp);
+err_mutex:
+ mutex_destroy(&mhdp->link_mutex);
+ mutex_destroy(&mhdp->base.mailbox_mutex);
+ return ret;
+}
+
+static void cdns_mhdp8501_remove(struct platform_device *pdev)
+{
+ struct cdns_mhdp_base *base = platform_get_drvdata(pdev);
+ struct cdns_mhdp8501_device *mhdp =
+ container_of(base, struct cdns_mhdp8501_device, base);
+
+ WRITE_ONCE(mhdp->removing, true);
+
+ disable_irq(mhdp->irq[IRQ_IN]);
+ disable_irq(mhdp->irq[IRQ_OUT]);
+
+ cancel_delayed_work_sync(&mhdp->hotplug_work);
+
+ drm_bridge_remove(&mhdp->bridge);
+
+ phy_exit(mhdp->phy);
+
+ mutex_destroy(&mhdp->link_mutex);
+ mutex_destroy(&mhdp->base.mailbox_mutex);
+
+ cdns_mhdp8501_debugfs_cleanup(mhdp);
+}
+
+static const struct of_device_id cdns_mhdp8501_dt_ids[] = {
+ { .compatible = "fsl,imx8mq-mhdp8501-hdmi",
+ .data = (void *)DRM_MODE_CONNECTOR_HDMIA },
+ { .compatible = "fsl,imx8mq-mhdp8501-dp",
+ .data = (void *)DRM_MODE_CONNECTOR_DisplayPort },
+ { },
+};
+MODULE_DEVICE_TABLE(of, cdns_mhdp8501_dt_ids);
+
+static struct platform_driver cdns_mhdp8501_driver = {
+ .probe = cdns_mhdp8501_probe,
+ .remove = cdns_mhdp8501_remove,
+ .driver = {
+ .name = "cdns-mhdp8501",
+ .of_match_table = cdns_mhdp8501_dt_ids,
+ },
+};
+
+module_platform_driver(cdns_mhdp8501_driver);
+
+MODULE_AUTHOR("Sandor Yu <sandor.yu@nxp.com>");
+MODULE_DESCRIPTION("Cadence MHDP8501 bridge driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-core.h b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-core.h
new file mode 100644
index 0000000000000..f74e7b4ccf77d
--- /dev/null
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-core.h
@@ -0,0 +1,391 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Cadence MHDP 8501 Common head file
+ *
+ * Copyright (C) 2019-2024 NXP Semiconductor, Inc.
+ *
+ */
+
+#ifndef _CDNS_MHDP8501_CORE_H_
+#define _CDNS_MHDP8501_CORE_H_
+
+#include <drm/drm_bridge.h>
+#include <drm/drm_connector.h>
+#include <drm/display/drm_dp_helper.h>
+#include <linux/bitops.h>
+#include <linux/i2c.h>
+#include <soc/cadence/cdns-mhdp-helper.h>
+
+#define ADDR_IMEM 0x10000
+#define ADDR_DMEM 0x20000
+
+/* APB CFG addr */
+#define APB_CTRL 0
+#define XT_INT_CTRL 0x04
+#define MAILBOX_FULL_ADDR 0x08
+#define MAILBOX_EMPTY_ADDR 0x0c
+#define MAILBOX0_WR_DATA 0x10
+#define MAILBOX0_RD_DATA 0x14
+#define KEEP_ALIVE 0x18
+#define VER_L 0x1c
+#define VER_H 0x20
+#define VER_LIB_L_ADDR 0x24
+#define VER_LIB_H_ADDR 0x28
+#define SW_DEBUG_L 0x2c
+#define SW_DEBUG_H 0x30
+#define MAILBOX_INT_MASK 0x34
+#define MAILBOX_INT_STATUS 0x38
+#define SW_CLK_L 0x3c
+#define SW_CLK_H 0x40
+#define SW_EVENTS0 0x44
+#define SW_EVENTS1 0x48
+#define SW_EVENTS2 0x4c
+#define SW_EVENTS3 0x50
+#define XT_OCD_CTRL 0x60
+#define APB_INT_MASK 0x6c
+#define APB_STATUS_MASK 0x70
+
+/* Source phy comp */
+#define PHY_DATA_SEL 0x0818
+#define LANES_CONFIG 0x0814
+
+/* Source CAR Addr */
+#define SOURCE_HDTX_CAR 0x0900
+#define SOURCE_DPTX_CAR 0x0904
+#define SOURCE_PHY_CAR 0x0908
+#define SOURCE_CEC_CAR 0x090c
+#define SOURCE_CBUS_CAR 0x0910
+#define SOURCE_PKT_CAR 0x0918
+#define SOURCE_AIF_CAR 0x091c
+#define SOURCE_CIPHER_CAR 0x0920
+#define SOURCE_CRYPTO_CAR 0x0924
+
+/* clock meters addr */
+#define CM_CTRL 0x0a00
+#define CM_I2S_CTRL 0x0a04
+#define CM_SPDIF_CTRL 0x0a08
+#define CM_VID_CTRL 0x0a0c
+#define CM_LANE_CTRL 0x0a10
+#define I2S_NM_STABLE 0x0a14
+#define I2S_NCTS_STABLE 0x0a18
+#define SPDIF_NM_STABLE 0x0a1c
+#define SPDIF_NCTS_STABLE 0x0a20
+#define NMVID_MEAS_STABLE 0x0a24
+#define I2S_MEAS 0x0a40
+#define SPDIF_MEAS 0x0a80
+#define NMVID_MEAS 0x0ac0
+
+/* source vif addr */
+#define BND_HSYNC2VSYNC 0x0b00
+#define HSYNC2VSYNC_F1_L1 0x0b04
+#define HSYNC2VSYNC_STATUS 0x0b0c
+#define HSYNC2VSYNC_POL_CTRL 0x0b10
+
+/* MHDP TX_top_comp */
+#define SCHEDULER_H_SIZE 0x1000
+#define SCHEDULER_V_SIZE 0x1004
+#define HDTX_SIGNAL_FRONT_WIDTH 0x100c
+#define HDTX_SIGNAL_SYNC_WIDTH 0x1010
+#define HDTX_SIGNAL_BACK_WIDTH 0x1014
+#define HDTX_CONTROLLER 0x1018
+#define HDTX_HPD 0x1020
+#define HDTX_CLOCK_REG_0 0x1024
+#define HDTX_CLOCK_REG_1 0x1028
+
+/* DPTX hpd addr */
+#define HPD_IRQ_DET_MIN_TIMER 0x2100
+#define HPD_IRQ_DET_MAX_TIMER 0x2104
+#define HPD_UNPLGED_DET_MIN_TIMER 0x2108
+#define HPD_STABLE_TIMER 0x210c
+#define HPD_FILTER_TIMER 0x2110
+#define HPD_EVENT_MASK 0x211c
+#define HPD_EVENT_DET 0x2120
+
+/* DPTX framer addr */
+#define DP_FRAMER_GLOBAL_CONFIG 0x2200
+#define DP_SW_RESET 0x2204
+#define DP_FRAMER_TU 0x2208
+#define DP_FRAMER_PXL_REPR 0x220c
+#define DP_FRAMER_SP 0x2210
+#define AUDIO_PACK_CONTROL 0x2214
+#define DP_VC_TABLE(x) (0x2218 + ((x) << 2))
+#define DP_VB_ID 0x2258
+#define DP_MTPH_LVP_CONTROL 0x225c
+#define DP_MTPH_SYMBOL_VALUES 0x2260
+#define DP_MTPH_ECF_CONTROL 0x2264
+#define DP_MTPH_ACT_CONTROL 0x2268
+#define DP_MTPH_STATUS 0x226c
+#define DP_INTERRUPT_SOURCE 0x2270
+#define DP_INTERRUPT_MASK 0x2274
+#define DP_FRONT_BACK_PORCH 0x2278
+#define DP_BYTE_COUNT 0x227c
+
+/* DPTX stream addr */
+#define MSA_HORIZONTAL_0 0x2280
+#define MSA_HORIZONTAL_1 0x2284
+#define MSA_VERTICAL_0 0x2288
+#define MSA_VERTICAL_1 0x228c
+#define MSA_MISC 0x2290
+#define STREAM_CONFIG 0x2294
+#define AUDIO_PACK_STATUS 0x2298
+#define VIF_STATUS 0x229c
+#define PCK_STUFF_STATUS_0 0x22a0
+#define PCK_STUFF_STATUS_1 0x22a4
+#define INFO_PACK_STATUS 0x22a8
+#define RATE_GOVERNOR_STATUS 0x22ac
+#define DP_HORIZONTAL 0x22b0
+#define DP_VERTICAL_0 0x22b4
+#define DP_VERTICAL_1 0x22b8
+#define DP_BLOCK_SDP 0x22bc
+
+/* DPTX glbl addr */
+#define DPTX_LANE_EN 0x2300
+#define DPTX_ENHNCD 0x2304
+#define DPTX_INT_MASK 0x2308
+#define DPTX_INT_STATUS 0x230c
+
+/* DP AUX Addr */
+#define DP_AUX_HOST_CONTROL 0x2800
+#define DP_AUX_INTERRUPT_SOURCE 0x2804
+#define DP_AUX_INTERRUPT_MASK 0x2808
+#define DP_AUX_SWAP_INVERSION_CONTROL 0x280c
+#define DP_AUX_SEND_NACK_TRANSACTION 0x2810
+#define DP_AUX_CLEAR_RX 0x2814
+#define DP_AUX_CLEAR_TX 0x2818
+#define DP_AUX_TIMER_STOP 0x281c
+#define DP_AUX_TIMER_CLEAR 0x2820
+#define DP_AUX_RESET_SW 0x2824
+#define DP_AUX_DIVIDE_2M 0x2828
+#define DP_AUX_TX_PREACHARGE_LENGTH 0x282c
+#define DP_AUX_FREQUENCY_1M_MAX 0x2830
+#define DP_AUX_FREQUENCY_1M_MIN 0x2834
+#define DP_AUX_RX_PRE_MIN 0x2838
+#define DP_AUX_RX_PRE_MAX 0x283c
+#define DP_AUX_TIMER_PRESET 0x2840
+#define DP_AUX_NACK_FORMAT 0x2844
+#define DP_AUX_TX_DATA 0x2848
+#define DP_AUX_RX_DATA 0x284c
+#define DP_AUX_TX_STATUS 0x2850
+#define DP_AUX_RX_STATUS 0x2854
+#define DP_AUX_RX_CYCLE_COUNTER 0x2858
+#define DP_AUX_MAIN_STATES 0x285c
+#define DP_AUX_MAIN_TIMER 0x2860
+#define DP_AUX_AFE_OUT 0x2864
+
+/* source pif addr */
+#define SOURCE_PIF_WR_ADDR 0x30800
+#define SOURCE_PIF_WR_REQ 0x30804
+#define SOURCE_PIF_RD_ADDR 0x30808
+#define SOURCE_PIF_RD_REQ 0x3080c
+#define SOURCE_PIF_DATA_WR 0x30810
+#define SOURCE_PIF_DATA_RD 0x30814
+#define SOURCE_PIF_FIFO1_FLUSH 0x30818
+#define SOURCE_PIF_FIFO2_FLUSH 0x3081c
+#define SOURCE_PIF_STATUS 0x30820
+#define SOURCE_PIF_INTERRUPT_SOURCE 0x30824
+#define SOURCE_PIF_INTERRUPT_MASK 0x30828
+#define SOURCE_PIF_PKT_ALLOC_REG 0x3082c
+#define SOURCE_PIF_PKT_ALLOC_WR_EN 0x30830
+#define SOURCE_PIF_SW_RESET 0x30834
+
+#define LINK_TRAINING_NOT_ACTIV 0
+#define LINK_TRAINING_RUN 1
+#define LINK_TRAINING_RESTART 2
+
+#define CONTROL_VIDEO_IDLE 0
+#define CONTROL_VIDEO_VALID 1
+
+#define INTERLACE_FMT_DET BIT(12)
+#define VIF_BYPASS_INTERLACE BIT(13)
+#define TU_CNT_RST_EN BIT(15)
+#define INTERLACE_DTCT_WIN 0x20
+
+#define DP_FRAMER_SP_INTERLACE_EN BIT(2)
+#define DP_FRAMER_SP_HSP BIT(1)
+#define DP_FRAMER_SP_VSP BIT(0)
+
+/* Capability */
+#define AUX_HOST_INVERT 3
+#define FAST_LT_SUPPORT 1
+#define FAST_LT_NOT_SUPPORT 0
+#define LANE_MAPPING_FLIPPED 0xe4
+#define ENHANCED 1
+#define SCRAMBLER_EN BIT(4)
+
+#define FULL_LT_STARTED BIT(0)
+#define FASE_LT_STARTED BIT(1)
+#define CLK_RECOVERY_FINISHED BIT(2)
+#define EQ_PHASE_FINISHED BIT(3)
+#define FASE_LT_START_FINISHED BIT(4)
+#define CLK_RECOVERY_FAILED BIT(5)
+#define EQ_PHASE_FAILED BIT(6)
+#define FASE_LT_FAILED BIT(7)
+
+#define TU_SIZE 30
+#define CDNS_DP_MAX_LINK_RATE 540000
+
+#define F_HDMI2_CTRL_IL_MODE(x) (((x) & ((1 << 1) - 1)) << 19)
+#define F_HDMI2_PREAMBLE_EN(x) (((x) & ((1 << 1) - 1)) << 18)
+#define F_HDMI_ENCODING(x) (((x) & ((1 << 2) - 1)) << 16)
+#define F_DATA_EN(x) (((x) & ((1 << 1) - 1)) << 15)
+#define F_CLEAR_AVMUTE(x) (((x) & ((1 << 1) - 1)) << 14)
+#define F_SET_AVMUTE(x) (((x) & ((1 << 1) - 1)) << 13)
+#define F_GCP_EN(x) (((x) & ((1 << 1) - 1)) << 12)
+#define F_BCH_EN(x) (((x) & ((1 << 1) - 1)) << 11)
+#define F_PIC_3D(x) (((x) & ((1 << 4) - 1)) << 7)
+#define F_VIF_DATA_WIDTH(x) (((x) & ((1 << 2) - 1)) << 2)
+#define F_HDMI_MODE(x) (((x) & ((1 << 2) - 1)) << 0)
+
+#define F_SOURCE_PHY_MHDP_SEL(x) (((x) & ((1 << 2) - 1)) << 3)
+
+#define F_HPD_GLITCH_WIDTH(x) (((x) & ((1 << 8) - 1)) << 12)
+#define F_PACKET_TYPE(x) (((x) & ((1 << 8) - 1)) << 8)
+#define F_HPD_VALID_WIDTH(x) (((x) & ((1 << 12) - 1)) << 0)
+
+#define F_SOURCE_PHY_LANE3_SWAP(x) (((x) & ((1 << 2) - 1)) << 6)
+#define F_SOURCE_PHY_LANE2_SWAP(x) (((x) & ((1 << 2) - 1)) << 4)
+#define F_SOURCE_PHY_LANE1_SWAP(x) (((x) & ((1 << 2) - 1)) << 2)
+#define F_SOURCE_PHY_LANE0_SWAP(x) (((x) & ((1 << 2) - 1)) << 0)
+
+#define F_ACTIVE_IDLE_TYPE(x) (((x) & ((1 << 1) - 1)) << 17)
+#define F_TYPE_VALID(x) (((x) & ((1 << 1) - 1)) << 16)
+#define F_PKT_ALLOC_ADDRESS(x) (((x) & ((1 << 4) - 1)) << 0)
+
+#define F_FIFO1_FLUSH(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_PKT_ALLOC_WR_EN(x) (((x) & ((1 << 1) - 1)) << 0)
+#define F_DATA_WR(x) (x)
+#define F_WR_ADDR(x) (((x) & ((1 << 4) - 1)) << 0)
+#define F_HOST_WR(x) (((x) & ((1 << 1) - 1)) << 0)
+
+/* Reference cycles when using lane clock as reference */
+#define LANE_REF_CYC 0x8000
+
+/* HPD Debounce */
+#define HOTPLUG_DEBOUNCE_MS 200
+
+/* HPD IRQ Index */
+#define IRQ_IN 0
+#define IRQ_OUT 1
+#define IRQ_NUM 2
+
+/* FW check alive timeout */
+#define CDNS_KEEP_ALIVE_TIMEOUT 2000
+#define CDNS_KEEP_ALIVE_MASK GENMASK(7, 0)
+
+enum voltage_swing_level {
+ VOLTAGE_LEVEL_0,
+ VOLTAGE_LEVEL_1,
+ VOLTAGE_LEVEL_2,
+ VOLTAGE_LEVEL_3,
+};
+
+enum pre_emphasis_level {
+ PRE_EMPHASIS_LEVEL_0,
+ PRE_EMPHASIS_LEVEL_1,
+ PRE_EMPHASIS_LEVEL_2,
+ PRE_EMPHASIS_LEVEL_3,
+};
+
+enum pattern_set {
+ PTS1 = BIT(0),
+ PTS2 = BIT(1),
+ PTS3 = BIT(2),
+ PTS4 = BIT(3),
+ DP_NONE = BIT(4)
+};
+
+enum vic_color_depth {
+ BCS_6 = 0x1,
+ BCS_8 = 0x2,
+ BCS_10 = 0x4,
+ BCS_12 = 0x8,
+ BCS_16 = 0x10,
+};
+
+enum vic_bt_type {
+ BT_601 = 0x0,
+ BT_709 = 0x1,
+};
+
+enum {
+ MODE_DVI,
+ MODE_HDMI_1_4,
+ MODE_HDMI_2_0,
+};
+
+struct video_info {
+ int bpc;
+ int color_fmt;
+};
+
+struct cdns_hdmi_i2c {
+ struct i2c_adapter adap;
+
+ struct mutex lock; /* used to serialize data transfers */
+ struct completion cmp;
+ u8 stat;
+
+ u8 slave_reg;
+ bool is_regaddr;
+ bool is_segment;
+};
+
+struct cdns_mhdp8501_device {
+ struct cdns_mhdp_base base;
+
+ struct device *dev;
+ void __iomem *regs;
+ struct drm_crtc *curr_crtc;
+ struct drm_bridge bridge;
+ struct clk *apb_clk;
+ struct phy *phy;
+ bool phy_powered;
+
+ struct video_info video_info;
+
+ struct mutex link_mutex; /* serialises PHY/FW ops vs. hotplug retrain */
+
+ int irq[IRQ_NUM];
+ struct delayed_work hotplug_work;
+ bool removing;
+ int bridge_type;
+ u32 lane_mapping;
+
+ union {
+ struct _dp_data {
+ u32 rate;
+ u8 num_lanes;
+ struct drm_dp_aux aux;
+ u8 dpcd[DP_RECEIVER_CAP_SIZE];
+ } dp;
+ struct _hdmi_data {
+ u32 hdmi_type;
+ struct cdns_hdmi_i2c *i2c;
+ } hdmi;
+ };
+
+ struct dentry *debugfs;
+};
+
+static inline struct cdns_mhdp8501_device *
+bridge_to_mhdp(const struct drm_bridge *bridge)
+{
+ return container_of(bridge, struct cdns_mhdp8501_device, bridge);
+}
+
+extern const struct drm_bridge_funcs cdns_dp_bridge_funcs;
+extern const struct drm_bridge_funcs cdns_hdmi_bridge_funcs;
+
+enum drm_connector_status
+cdns_mhdp8501_detect(struct drm_bridge *bridge, struct drm_connector *connector);
+enum drm_mode_status
+cdns_mhdp8501_mode_valid(struct drm_bridge *bridge,
+ const struct drm_display_info *info,
+ const struct drm_display_mode *mode);
+
+ssize_t cdns_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg);
+void cdns_dp_check_link_state(struct cdns_mhdp8501_device *mhdp);
+
+void cdns_hdmi_handle_hotplug(struct cdns_mhdp8501_device *mhdp);
+struct i2c_adapter *cdns_hdmi_i2c_adapter(struct cdns_mhdp8501_device *mhdp);
+#endif
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-dp.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-dp.c
new file mode 100644
index 0000000000000..f1e48e631c63e
--- /dev/null
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-dp.c
@@ -0,0 +1,725 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Cadence MHDP8501 DisplayPort(DP) bridge driver
+ *
+ * Copyright (C) 2019-2026 NXP Semiconductor, Inc.
+ *
+ */
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_drv.h>
+#include <drm/drm_edid.h>
+#include <drm/drm_print.h>
+#include <linux/media-bus-format.h>
+#include <linux/phy/phy.h>
+#include <linux/phy/phy-dp.h>
+
+#include "cdns-mhdp8501-core.h"
+
+#define LINK_TRAINING_TIMEOUT_MS 500
+#define LINK_TRAINING_RETRY_MS 20
+
+ssize_t cdns_dp_aux_transfer(struct drm_dp_aux *aux,
+ struct drm_dp_aux_msg *msg)
+{
+ struct cdns_mhdp8501_device *mhdp = dev_get_drvdata(aux->dev);
+ bool native = msg->request == DP_AUX_NATIVE_WRITE ||
+ msg->request == DP_AUX_NATIVE_READ;
+ int ret;
+
+ /* Ignore address only message */
+ if (!msg->size || !msg->buffer) {
+ msg->reply = native ?
+ DP_AUX_NATIVE_REPLY_ACK : DP_AUX_I2C_REPLY_ACK;
+ return msg->size;
+ }
+
+ if (!native) {
+ dev_err(mhdp->dev, "%s: only native messages supported\n", __func__);
+ return -EINVAL;
+ }
+
+ /* msg sanity check */
+ if (msg->size > DP_AUX_MAX_PAYLOAD_BYTES) {
+ dev_err(mhdp->dev, "%s: invalid msg: size(%zu), request(%x)\n",
+ __func__, msg->size, (unsigned int)msg->request);
+ return -EINVAL;
+ }
+
+ if (msg->request == DP_AUX_NATIVE_WRITE) {
+ const u8 *buf = msg->buffer;
+ int i;
+
+ for (i = 0; i < msg->size; ++i) {
+ ret = cdns_mhdp_dpcd_write(&mhdp->base,
+ msg->address + i, buf[i]);
+ if (ret < 0) {
+ dev_err(mhdp->dev, "Failed to write DPCD\n");
+ return ret;
+ }
+ }
+ msg->reply = DP_AUX_NATIVE_REPLY_ACK;
+ return msg->size;
+ }
+
+ if (msg->request == DP_AUX_NATIVE_READ) {
+ ret = cdns_mhdp_dpcd_read(&mhdp->base, msg->address,
+ msg->buffer, msg->size);
+ if (ret < 0)
+ return ret;
+ msg->reply = DP_AUX_NATIVE_REPLY_ACK;
+ return msg->size;
+ }
+ return 0;
+}
+
+static int cdns_dp_get_msa_misc(struct video_info *video)
+{
+ u32 msa_misc;
+ u8 color_space = 0;
+ u8 bpc = 0;
+
+ switch (video->color_fmt) {
+ /* set YUV default color space conversion to BT601 */
+ case BIT(DRM_OUTPUT_COLOR_FORMAT_YCBCR444):
+ color_space = 6 + BT_601 * 8;
+ break;
+ case BIT(DRM_OUTPUT_COLOR_FORMAT_YCBCR422):
+ color_space = 5 + BT_601 * 8;
+ break;
+ case BIT(DRM_OUTPUT_COLOR_FORMAT_YCBCR420):
+ color_space = 5;
+ break;
+ case BIT(DRM_OUTPUT_COLOR_FORMAT_RGB444):
+ default:
+ color_space = 0;
+ break;
+ }
+
+ switch (video->bpc) {
+ case 6:
+ bpc = 0;
+ break;
+ case 10:
+ bpc = 2;
+ break;
+ case 12:
+ bpc = 3;
+ break;
+ case 16:
+ bpc = 4;
+ break;
+ case 8:
+ default:
+ bpc = 1;
+ break;
+ }
+
+ msa_misc = (bpc << 5) | (color_space << 1);
+
+ return msa_misc;
+}
+
+static int cdns_dp_config_video(struct cdns_mhdp8501_device *mhdp,
+ const struct drm_display_mode *mode)
+{
+ struct video_info *video = &mhdp->video_info;
+ bool h_sync_polarity, v_sync_polarity;
+ u64 symbol;
+ u32 val, link_rate, rem;
+ u8 bit_per_pix, tu_size_reg = TU_SIZE;
+ int ret;
+
+ bit_per_pix = (video->color_fmt == BIT(DRM_OUTPUT_COLOR_FORMAT_YCBCR422)) ?
+ (video->bpc * 2) : (video->bpc * 3);
+
+ link_rate = mhdp->dp.rate / 1000;
+
+ ret = cdns_mhdp_reg_write(&mhdp->base, BND_HSYNC2VSYNC, VIF_BYPASS_INTERLACE);
+ if (ret)
+ goto err_config_video;
+
+ ret = cdns_mhdp_reg_write(&mhdp->base, HSYNC2VSYNC_POL_CTRL, 0);
+ if (ret)
+ goto err_config_video;
+
+ /*
+ * get a best tu_size and valid symbol:
+ * 1. chose Lclk freq(162Mhz, 270Mhz, 540Mhz), set TU to 32
+ * 2. calculate VS(valid symbol) = TU * Pclk * Bpp / (Lclk * Lanes)
+ * 3. if VS > *.85 or VS < *.1 or VS < 2 or TU < VS + 4, then set
+ * TU += 2 and repeat 2nd step.
+ */
+ do {
+ tu_size_reg += 2;
+ symbol = (u64)tu_size_reg * mode->clock * bit_per_pix;
+ do_div(symbol, mhdp->dp.num_lanes * link_rate * 8);
+ rem = do_div(symbol, 1000);
+ if (tu_size_reg > 64) {
+ ret = -EINVAL;
+ dev_err(mhdp->dev, "tu error, clk:%d, lanes:%d, rate:%d\n",
+ mode->clock, mhdp->dp.num_lanes, link_rate);
+ goto err_config_video;
+ }
+ } while ((symbol <= 1) || (tu_size_reg - symbol < 4) ||
+ (rem > 850) || (rem < 100));
+
+ val = symbol + (tu_size_reg << 8);
+ val |= TU_CNT_RST_EN;
+ ret = cdns_mhdp_reg_write(&mhdp->base, DP_FRAMER_TU, val);
+ if (ret)
+ goto err_config_video;
+
+ /* set the FIFO Buffer size */
+ val = div_u64(mode->clock * (symbol + 1), 1000) + link_rate;
+ val /= (mhdp->dp.num_lanes * link_rate);
+ val = div_u64(8 * (symbol + 1), bit_per_pix) - val;
+ val += 2;
+ ret = cdns_mhdp_reg_write(&mhdp->base, DP_VC_TABLE(15), val);
+ if (ret)
+ goto err_config_video;
+
+ switch (video->bpc) {
+ case 6:
+ val = BCS_6;
+ break;
+ case 10:
+ val = BCS_10;
+ break;
+ case 12:
+ val = BCS_12;
+ break;
+ case 16:
+ val = BCS_16;
+ break;
+ case 8:
+ default:
+ val = BCS_8;
+ break;
+ }
+
+ val += video->color_fmt << 8;
+ ret = cdns_mhdp_reg_write(&mhdp->base, DP_FRAMER_PXL_REPR, val);
+ if (ret)
+ goto err_config_video;
+
+ v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
+ h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
+
+ val = h_sync_polarity ? DP_FRAMER_SP_HSP : 0;
+ val |= v_sync_polarity ? DP_FRAMER_SP_VSP : 0;
+ ret = cdns_mhdp_reg_write(&mhdp->base, DP_FRAMER_SP, val);
+ if (ret)
+ goto err_config_video;
+
+ val = (mode->hsync_start - mode->hdisplay) << 16;
+ val |= mode->htotal - mode->hsync_end;
+ ret = cdns_mhdp_reg_write(&mhdp->base, DP_FRONT_BACK_PORCH, val);
+ if (ret)
+ goto err_config_video;
+
+ val = mode->hdisplay * bit_per_pix / 8;
+ ret = cdns_mhdp_reg_write(&mhdp->base, DP_BYTE_COUNT, val);
+ if (ret)
+ goto err_config_video;
+
+ val = mode->htotal | ((mode->htotal - mode->hsync_start) << 16);
+ ret = cdns_mhdp_reg_write(&mhdp->base, MSA_HORIZONTAL_0, val);
+ if (ret)
+ goto err_config_video;
+
+ val = mode->hsync_end - mode->hsync_start;
+ val |= (mode->hdisplay << 16) | (h_sync_polarity << 15);
+ ret = cdns_mhdp_reg_write(&mhdp->base, MSA_HORIZONTAL_1, val);
+ if (ret)
+ goto err_config_video;
+
+ val = mode->vtotal;
+ val |= (mode->vtotal - mode->vsync_start) << 16;
+ ret = cdns_mhdp_reg_write(&mhdp->base, MSA_VERTICAL_0, val);
+ if (ret)
+ goto err_config_video;
+
+ val = mode->vsync_end - mode->vsync_start;
+ val |= (mode->vdisplay << 16) | (v_sync_polarity << 15);
+ ret = cdns_mhdp_reg_write(&mhdp->base, MSA_VERTICAL_1, val);
+ if (ret)
+ goto err_config_video;
+
+ val = cdns_dp_get_msa_misc(video);
+ ret = cdns_mhdp_reg_write(&mhdp->base, MSA_MISC, val);
+ if (ret)
+ goto err_config_video;
+
+ ret = cdns_mhdp_reg_write(&mhdp->base, STREAM_CONFIG, 1);
+ if (ret)
+ goto err_config_video;
+
+ val = mode->hsync_end - mode->hsync_start;
+ val |= mode->hdisplay << 16;
+ ret = cdns_mhdp_reg_write(&mhdp->base, DP_HORIZONTAL, val);
+ if (ret)
+ goto err_config_video;
+
+ val = mode->vdisplay;
+ val |= (mode->vtotal - mode->vsync_start) << 16;
+ ret = cdns_mhdp_reg_write(&mhdp->base, DP_VERTICAL_0, val);
+ if (ret)
+ goto err_config_video;
+
+ val = mode->vtotal;
+ ret = cdns_mhdp_reg_write(&mhdp->base, DP_VERTICAL_1, val);
+ if (ret)
+ goto err_config_video;
+
+ ret = cdns_mhdp_dp_reg_write_bit(&mhdp->base, DP_VB_ID, 2, 1, 0);
+
+err_config_video:
+ if (ret)
+ dev_err(mhdp->dev, "config video failed: %d\n", ret);
+ return ret;
+}
+
+static int cdns_dp_pixel_clk_reset(struct cdns_mhdp8501_device *mhdp)
+{
+ u32 val;
+ int ret;
+
+ /* reset pixel clk */
+ ret = cdns_mhdp_reg_read(&mhdp->base, SOURCE_HDTX_CAR, &val);
+ if (ret)
+ return ret;
+
+ ret = cdns_mhdp_reg_write(&mhdp->base, SOURCE_HDTX_CAR, val & 0xFD);
+ if (ret)
+ return ret;
+
+ return cdns_mhdp_reg_write(&mhdp->base, SOURCE_HDTX_CAR, val);
+}
+
+static int cdns_dp_set_video_status(struct cdns_mhdp8501_device *mhdp, int active)
+{
+ u8 msg;
+ int ret;
+
+ msg = !!active;
+
+ ret = cdns_mhdp_mailbox_send(&mhdp->base, MB_MODULE_ID_DP_TX,
+ DPTX_SET_VIDEO, sizeof(msg), &msg);
+ if (ret)
+ dev_err(mhdp->dev, "set video status failed: %d\n", ret);
+
+ return ret;
+}
+
+static int cdns_dp_training_start(struct cdns_mhdp8501_device *mhdp)
+{
+ unsigned long timeout;
+ u8 msg, event[2];
+ int ret;
+
+ msg = LINK_TRAINING_RUN;
+
+ /* start training */
+ ret = cdns_mhdp_mailbox_send(&mhdp->base, MB_MODULE_ID_DP_TX,
+ DPTX_TRAINING_CONTROL, sizeof(msg), &msg);
+ if (ret)
+ return ret;
+
+ timeout = jiffies + msecs_to_jiffies(LINK_TRAINING_TIMEOUT_MS);
+ while (time_before(jiffies, timeout)) {
+ msleep(LINK_TRAINING_RETRY_MS);
+ ret = cdns_mhdp_mailbox_send_recv(&mhdp->base, MB_MODULE_ID_DP_TX,
+ DPTX_READ_EVENT,
+ 0, NULL, sizeof(event), event);
+ if (ret)
+ return ret;
+
+ if (event[1] & CLK_RECOVERY_FAILED)
+ dev_err(mhdp->dev, "clock recovery failed\n");
+ else if (event[1] & EQ_PHASE_FINISHED)
+ return 0;
+ }
+
+ return -ETIMEDOUT;
+}
+
+static int cdns_dp_get_training_status(struct cdns_mhdp8501_device *mhdp)
+{
+ u8 status[13];
+ int ret;
+
+ ret = cdns_mhdp_mailbox_send_recv(&mhdp->base, MB_MODULE_ID_DP_TX,
+ DPTX_READ_LINK_STAT,
+ 0, NULL, sizeof(status), status);
+ if (ret)
+ return ret;
+
+ mhdp->dp.rate = drm_dp_bw_code_to_link_rate(status[0]);
+ mhdp->dp.num_lanes = status[1];
+
+ if (!mhdp->dp.rate || !mhdp->dp.num_lanes) {
+ dev_err(mhdp->dev, "invalid link params from FW: rate=%d lanes=%d\n",
+ mhdp->dp.rate, mhdp->dp.num_lanes);
+ return -EINVAL;
+ }
+
+ return ret;
+}
+
+static int cdns_dp_train_link(struct cdns_mhdp8501_device *mhdp)
+{
+ int ret;
+
+ ret = cdns_dp_training_start(mhdp);
+ if (ret) {
+ dev_err(mhdp->dev, "Failed to start training %d\n", ret);
+ return ret;
+ }
+
+ ret = cdns_dp_get_training_status(mhdp);
+ if (ret) {
+ dev_err(mhdp->dev, "Failed to get training stat %d\n", ret);
+ return ret;
+ }
+
+ dev_dbg(mhdp->dev, "rate:0x%x, lanes:%d\n", mhdp->dp.rate,
+ mhdp->dp.num_lanes);
+ return ret;
+}
+
+static int cdns_dp_set_host_cap(struct cdns_mhdp8501_device *mhdp)
+{
+ u8 msg[8];
+ int ret;
+
+ msg[0] = drm_dp_link_rate_to_bw_code(mhdp->dp.rate);
+ msg[1] = mhdp->dp.num_lanes | SCRAMBLER_EN;
+ msg[2] = VOLTAGE_LEVEL_2;
+ msg[3] = PRE_EMPHASIS_LEVEL_3;
+ msg[4] = PTS1 | PTS2 | PTS3 | PTS4;
+ msg[5] = FAST_LT_NOT_SUPPORT;
+ msg[6] = mhdp->lane_mapping;
+ msg[7] = ENHANCED;
+
+ ret = cdns_mhdp_mailbox_send(&mhdp->base, MB_MODULE_ID_DP_TX,
+ DPTX_SET_HOST_CAPABILITIES,
+ sizeof(msg), msg);
+ if (ret)
+ dev_err(mhdp->dev, "set host cap failed: %d\n", ret);
+
+ return ret;
+}
+
+static int cdns_dp_get_edid_block(void *data, u8 *edid,
+ unsigned int block, size_t length)
+{
+ struct cdns_mhdp8501_device *mhdp = data;
+ u8 msg[2], reg[2], i;
+ int ret;
+
+ for (i = 0; i < 4; i++) {
+ msg[0] = block / 2;
+ msg[1] = block % 2;
+
+ ret = cdns_mhdp_mailbox_send_recv_multi(&mhdp->base,
+ MB_MODULE_ID_DP_TX,
+ DPTX_GET_EDID,
+ sizeof(msg), msg,
+ DPTX_GET_EDID,
+ sizeof(reg), reg,
+ length, edid);
+ if (ret) {
+ drm_dbg_dp(mhdp->bridge.dev,
+ "edid block read failed: %d. Retrying...\n",
+ ret);
+ continue;
+ }
+
+ if (reg[0] == length && reg[1] == block / 2) {
+ ret = 0;
+ break;
+ }
+
+ ret = -EINVAL;
+ drm_dbg_dp(mhdp->bridge.dev,
+ "edid block validation failed (len=%u/%zu, blk=%u/%u). Retrying...\n",
+ reg[0], length, reg[1], block / 2);
+ }
+
+ if (ret)
+ dev_err(mhdp->dev, "get block[%d] edid failed: %d\n",
+ block, ret);
+
+ return ret;
+}
+
+static int cdns_dp_mode_set(struct cdns_mhdp8501_device *mhdp,
+ const struct drm_display_mode *mode)
+{
+ union phy_configure_opts phy_cfg = {};
+ int ret;
+
+ ret = cdns_dp_pixel_clk_reset(mhdp);
+ if (ret)
+ return ret;
+
+ /* delay for DP FW stable after pixel clock relock */
+ fsleep(20000);
+
+ /* Get DP Caps */
+ ret = drm_dp_dpcd_read(&mhdp->dp.aux, DP_DPCD_REV, mhdp->dp.dpcd,
+ DP_RECEIVER_CAP_SIZE);
+ if (ret < 0) {
+ dev_err(mhdp->dev, "Failed to get caps %d\n", ret);
+ return ret;
+ }
+
+ mhdp->dp.rate = drm_dp_max_link_rate(mhdp->dp.dpcd);
+ mhdp->dp.num_lanes = drm_dp_max_lane_count(mhdp->dp.dpcd);
+
+ if (!mhdp->dp.rate || !mhdp->dp.num_lanes) {
+ dev_err(mhdp->dev, "invalid link params from DPCD: rate=%d lanes=%d\n",
+ mhdp->dp.rate, mhdp->dp.num_lanes);
+ return -EINVAL;
+ }
+
+ /* check the max link rate */
+ if (mhdp->dp.rate > CDNS_DP_MAX_LINK_RATE)
+ mhdp->dp.rate = CDNS_DP_MAX_LINK_RATE;
+
+ phy_cfg.dp.lanes = mhdp->dp.num_lanes;
+ phy_cfg.dp.link_rate = mhdp->dp.rate;
+ phy_cfg.dp.set_lanes = false;
+ phy_cfg.dp.set_rate = false;
+ phy_cfg.dp.set_voltages = false;
+
+ ret = phy_configure(mhdp->phy, &phy_cfg);
+ if (ret) {
+ dev_err(mhdp->dev, "%s: phy_configure() failed: %d\n",
+ __func__, ret);
+ return ret;
+ }
+
+ /* Video off */
+ ret = cdns_dp_set_video_status(mhdp, CONTROL_VIDEO_IDLE);
+ if (ret) {
+ dev_err(mhdp->dev, "Failed to valid video %d\n", ret);
+ return ret;
+ }
+
+ /* Line swapping */
+ cdns_mhdp_reg_write(&mhdp->base, LANES_CONFIG, 0x00400000 | mhdp->lane_mapping);
+
+ /* Set DP host capability */
+ ret = cdns_dp_set_host_cap(mhdp);
+ if (ret) {
+ dev_err(mhdp->dev, "Failed to set host cap %d\n", ret);
+ return ret;
+ }
+
+ ret = cdns_mhdp_reg_write(&mhdp->base, DP_AUX_SWAP_INVERSION_CONTROL,
+ AUX_HOST_INVERT);
+ if (ret) {
+ dev_err(mhdp->dev, "Failed to set host invert %d\n", ret);
+ return ret;
+ }
+
+ ret = cdns_dp_config_video(mhdp, mode);
+ if (ret)
+ dev_err(mhdp->dev, "Failed to config video %d\n", ret);
+
+ return ret;
+}
+
+static bool
+cdns_dp_needs_link_retrain(struct cdns_mhdp8501_device *mhdp)
+{
+ u8 link_status[DP_LINK_STATUS_SIZE];
+
+ /*
+ * Treat an AUX read failure as needing retrain: the link may be down,
+ * which is exactly the condition that requires retraining.
+ */
+ if (drm_dp_dpcd_read_phy_link_status(&mhdp->dp.aux, DP_PHY_DPRX,
+ link_status) < 0)
+ return true;
+
+ /* Retrain if link not ok */
+ return !drm_dp_channel_eq_ok(link_status, mhdp->dp.num_lanes);
+}
+
+void cdns_dp_check_link_state(struct cdns_mhdp8501_device *mhdp)
+{
+ int ret;
+
+ scoped_guard(mutex, &mhdp->link_mutex) {
+ if (!mhdp->phy_powered)
+ return;
+
+ if (!cdns_dp_needs_link_retrain(mhdp))
+ return;
+
+ /* DP link retrain */
+ ret = cdns_dp_train_link(mhdp);
+ if (ret)
+ dev_err(mhdp->dev, "Failed link train\n");
+ }
+}
+
+static int cdns_dp_bridge_attach(struct drm_bridge *bridge,
+ struct drm_encoder *encoder,
+ enum drm_bridge_attach_flags flags)
+{
+ struct cdns_mhdp8501_device *mhdp = bridge_to_mhdp(bridge);
+ int ret;
+
+ if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
+ dev_err(mhdp->dev, "do not support creating a drm_connector\n");
+ return -EINVAL;
+ }
+
+ ret = drm_bridge_attach(encoder, bridge->next_bridge, bridge,
+ flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR);
+ if (ret < 0)
+ return ret;
+
+ mhdp->dp.aux.drm_dev = bridge->dev;
+
+ return drm_dp_aux_register(&mhdp->dp.aux);
+}
+
+static void cdns_dp_bridge_detach(struct drm_bridge *bridge)
+{
+ struct cdns_mhdp8501_device *mhdp = bridge_to_mhdp(bridge);
+
+ drm_dp_aux_unregister(&mhdp->dp.aux);
+}
+
+static const struct drm_edid
+*cdns_dp_bridge_edid_read(struct drm_bridge *bridge,
+ struct drm_connector *connector)
+{
+ struct cdns_mhdp8501_device *mhdp = bridge_to_mhdp(bridge);
+
+ return drm_edid_read_custom(connector, cdns_dp_get_edid_block, mhdp);
+}
+
+static u32 *cdns_dp_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state,
+ u32 output_fmt,
+ unsigned int *num_input_fmts)
+{
+ u32 *input_fmts;
+
+ input_fmts = kmalloc_obj(*input_fmts);
+ if (!input_fmts) {
+ *num_input_fmts = 0;
+ return NULL;
+ }
+
+ *num_input_fmts = 1;
+ input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24;
+
+ return input_fmts;
+}
+
+static int cdns_dp_bridge_atomic_check(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state)
+{
+ if (bridge_state->input_bus_cfg.format != MEDIA_BUS_FMT_RGB888_1X24)
+ return -EINVAL;
+
+ return 0;
+}
+
+static void cdns_dp_bridge_atomic_disable(struct drm_bridge *bridge,
+ struct drm_atomic_commit *state)
+{
+ struct cdns_mhdp8501_device *mhdp = bridge_to_mhdp(bridge);
+
+ scoped_guard(mutex, &mhdp->link_mutex) {
+ cdns_dp_set_video_status(mhdp, CONTROL_VIDEO_IDLE);
+ if (mhdp->phy_powered) {
+ phy_power_off(mhdp->phy);
+ mhdp->phy_powered = false;
+ }
+ }
+}
+
+static void cdns_dp_bridge_atomic_enable(struct drm_bridge *bridge,
+ struct drm_atomic_commit *state)
+{
+ struct cdns_mhdp8501_device *mhdp = bridge_to_mhdp(bridge);
+ struct drm_bridge_state *bridge_state;
+ struct drm_connector *connector;
+ struct drm_crtc_state *crtc_state;
+ struct drm_connector_state *conn_state;
+ int ret;
+
+ bridge_state = drm_atomic_get_new_bridge_state(state, bridge);
+ if (WARN_ON(!bridge_state))
+ return;
+
+ connector = drm_atomic_get_new_connector_for_encoder(state,
+ bridge->encoder);
+ if (WARN_ON(!connector))
+ return;
+
+ conn_state = drm_atomic_get_new_connector_state(state, connector);
+ if (WARN_ON(!conn_state))
+ return;
+
+ crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
+ if (WARN_ON(!crtc_state))
+ return;
+
+ switch (bridge_state->input_bus_cfg.format) {
+ case MEDIA_BUS_FMT_RGB888_1X24:
+ default:
+ mhdp->video_info.bpc = 8;
+ mhdp->video_info.color_fmt = BIT(DRM_OUTPUT_COLOR_FORMAT_RGB444);
+ break;
+ }
+
+ ret = cdns_dp_mode_set(mhdp, &crtc_state->adjusted_mode);
+ if (ret)
+ return;
+
+ scoped_guard(mutex, &mhdp->link_mutex) {
+ /* Power up PHY before link training */
+ phy_power_on(mhdp->phy);
+ mhdp->phy_powered = true;
+
+ /* Link training */
+ ret = cdns_dp_train_link(mhdp);
+ if (ret) {
+ dev_err(mhdp->dev, "Failed link train %d\n", ret);
+ phy_power_off(mhdp->phy);
+ mhdp->phy_powered = false;
+ return;
+ }
+
+ ret = cdns_dp_set_video_status(mhdp, CONTROL_VIDEO_VALID);
+ if (ret)
+ dev_err(mhdp->dev, "Failed to valid video %d\n", ret);
+ }
+}
+
+const struct drm_bridge_funcs cdns_dp_bridge_funcs = {
+ .attach = cdns_dp_bridge_attach,
+ .detach = cdns_dp_bridge_detach,
+ .detect = cdns_mhdp8501_detect,
+ .edid_read = cdns_dp_bridge_edid_read,
+ .mode_valid = cdns_mhdp8501_mode_valid,
+ .atomic_enable = cdns_dp_bridge_atomic_enable,
+ .atomic_disable = cdns_dp_bridge_atomic_disable,
+ .atomic_get_input_bus_fmts = cdns_dp_bridge_atomic_get_input_bus_fmts,
+ .atomic_check = cdns_dp_bridge_atomic_check,
+ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
+ .atomic_reset = drm_atomic_helper_bridge_reset,
+};
diff --git a/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-hdmi.c b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-hdmi.c
new file mode 100644
index 0000000000000..4172d5ff6cd59
--- /dev/null
+++ b/drivers/gpu/drm/bridge/cadence/cdns-mhdp8501-hdmi.c
@@ -0,0 +1,805 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Cadence MHDP8501 HDMI bridge driver
+ *
+ * Copyright (C) 2019-2026 NXP Semiconductor, Inc.
+ *
+ */
+#include <drm/drm_drv.h>
+#include <drm/display/drm_hdmi_helper.h>
+#include <drm/display/drm_hdmi_state_helper.h>
+#include <drm/display/drm_scdc_helper.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_edid.h>
+#include <drm/drm_print.h>
+#include <linux/phy/phy.h>
+#include <linux/phy/phy-hdmi.h>
+
+#include "cdns-mhdp8501-core.h"
+
+/**
+ * cdns_hdmi_config_infoframe() - fill the HDMI infoframe
+ * @mhdp: phandle to mhdp device.
+ * @entry_id: The packet memory address in which the data is written.
+ * @len: length of infoframe.
+ * @buf: point to InfoFrame Packet.
+ * @type: Packet Type of InfoFrame in HDMI Specification.
+ *
+ */
+
+static void cdns_hdmi_clear_infoframe(struct cdns_mhdp8501_device *mhdp,
+ u8 entry_id, u8 type)
+{
+ u32 val;
+
+ /* invalidate entry */
+ val = F_ACTIVE_IDLE_TYPE(1) | F_PKT_ALLOC_ADDRESS(entry_id) |
+ F_PACKET_TYPE(type);
+ writel(val, mhdp->regs + SOURCE_PIF_PKT_ALLOC_REG);
+ writel(F_PKT_ALLOC_WR_EN(1), mhdp->regs + SOURCE_PIF_PKT_ALLOC_WR_EN);
+}
+
+static void cdns_hdmi_config_infoframe(struct cdns_mhdp8501_device *mhdp,
+ u8 entry_id, u8 len,
+ const u8 *buf, u8 type)
+{
+ u8 packet[32] = { 0 }, packet_len = 32;
+ u32 packet32, len32;
+ u32 val, i;
+
+ /*
+ * only support 32 bytes now
+ * packet[0] = 0
+ * packet[1-3] = HB[0-2] InfoFrame Packet Header
+ * packet[4-31] = PB[0-27] InfoFrame Packet Contents
+ */
+ if (len > (packet_len - 1))
+ return;
+
+ memcpy(packet + 1, buf, len);
+
+ cdns_hdmi_clear_infoframe(mhdp, entry_id, type);
+
+ /* flush fifo 1 */
+ writel(F_FIFO1_FLUSH(1), mhdp->regs + SOURCE_PIF_FIFO1_FLUSH);
+
+ /* write packet into memory */
+ len32 = packet_len / 4;
+ for (i = 0; i < len32; i++) {
+ packet32 = get_unaligned_le32(packet + 4 * i);
+ writel(F_DATA_WR(packet32), mhdp->regs + SOURCE_PIF_DATA_WR);
+ }
+
+ /* write entry id */
+ writel(F_WR_ADDR(entry_id), mhdp->regs + SOURCE_PIF_WR_ADDR);
+
+ /* write request */
+ writel(F_HOST_WR(1), mhdp->regs + SOURCE_PIF_WR_REQ);
+
+ /* update entry */
+ val = F_ACTIVE_IDLE_TYPE(1) | F_TYPE_VALID(1) |
+ F_PACKET_TYPE(type) | F_PKT_ALLOC_ADDRESS(entry_id);
+ writel(val, mhdp->regs + SOURCE_PIF_PKT_ALLOC_REG);
+
+ writel(F_PKT_ALLOC_WR_EN(1), mhdp->regs + SOURCE_PIF_PKT_ALLOC_WR_EN);
+}
+
+static int cdns_hdmi_get_edid_block(void *data, u8 *edid,
+ u32 block, size_t length)
+{
+ struct cdns_mhdp8501_device *mhdp = data;
+ u8 msg[2], reg[5], i;
+ int ret;
+
+ for (i = 0; i < 4; i++) {
+ msg[0] = block / 2;
+ msg[1] = block % 2;
+
+ ret = cdns_mhdp_mailbox_send_recv_multi(&mhdp->base,
+ MB_MODULE_ID_HDMI_TX,
+ HDMI_TX_EDID,
+ sizeof(msg), msg,
+ HDMI_TX_EDID,
+ sizeof(reg), reg,
+ length, edid);
+ if (ret) {
+ drm_dbg(mhdp->bridge.dev,
+ "edid block read failed: %d. Retrying...\n",
+ ret);
+ continue;
+ }
+
+ if ((reg[3] << 8 | reg[4]) == length) {
+ ret = 0;
+ break;
+ }
+
+ ret = -EINVAL;
+ drm_dbg(mhdp->bridge.dev,
+ "edid block validation failed (len=%u/%zu). Retrying...\n",
+ reg[3] << 8 | reg[4], length);
+ }
+
+ if (ret)
+ dev_err(mhdp->dev, "get block[%d] edid failed: %d\n", block, ret);
+
+ return ret;
+}
+
+static int cdns_hdmi_set_hdmi_mode_type(struct cdns_mhdp8501_device *mhdp,
+ unsigned long long tmds_char_rate)
+{
+ u32 protocol = mhdp->hdmi.hdmi_type;
+ u32 val;
+ int ret;
+
+ if (protocol == MODE_HDMI_2_0 &&
+ tmds_char_rate >= 340000000) {
+ ret = cdns_mhdp_reg_write(&mhdp->base, HDTX_CLOCK_REG_0, 0);
+ if (ret)
+ return ret;
+ ret = cdns_mhdp_reg_write(&mhdp->base, HDTX_CLOCK_REG_1, 0xFFFFF);
+ if (ret)
+ return ret;
+ }
+
+ ret = cdns_mhdp_reg_read(&mhdp->base, HDTX_CONTROLLER, &val);
+ if (ret)
+ return ret;
+
+ /* set HDMI mode and preemble mode data enable */
+ val |= F_HDMI_MODE(protocol) | F_HDMI2_PREAMBLE_EN(1) |
+ F_HDMI2_CTRL_IL_MODE(1);
+ return cdns_mhdp_reg_write(&mhdp->base, HDTX_CONTROLLER, val);
+}
+
+static int cdns_hdmi_ctrl_init(struct cdns_mhdp8501_device *mhdp,
+ unsigned long long tmds_char_rate)
+{
+ u32 val;
+ int ret;
+
+ /* Set PHY to HDMI data */
+ ret = cdns_mhdp_reg_write(&mhdp->base, PHY_DATA_SEL, F_SOURCE_PHY_MHDP_SEL(1));
+ if (ret < 0)
+ return ret;
+
+ ret = cdns_mhdp_reg_write(&mhdp->base, HDTX_HPD,
+ F_HPD_VALID_WIDTH(4) | F_HPD_GLITCH_WIDTH(0));
+ if (ret < 0)
+ return ret;
+
+ /* open CARS */
+ ret = cdns_mhdp_reg_write(&mhdp->base, SOURCE_PHY_CAR, 0xF);
+ if (ret < 0)
+ return ret;
+ ret = cdns_mhdp_reg_write(&mhdp->base, SOURCE_HDTX_CAR, 0xFF);
+ if (ret < 0)
+ return ret;
+ ret = cdns_mhdp_reg_write(&mhdp->base, SOURCE_PKT_CAR, 0xF);
+ if (ret < 0)
+ return ret;
+ ret = cdns_mhdp_reg_write(&mhdp->base, SOURCE_AIF_CAR, 0xF);
+ if (ret < 0)
+ return ret;
+ ret = cdns_mhdp_reg_write(&mhdp->base, SOURCE_CIPHER_CAR, 0xF);
+ if (ret < 0)
+ return ret;
+ ret = cdns_mhdp_reg_write(&mhdp->base, SOURCE_CRYPTO_CAR, 0xF);
+ if (ret < 0)
+ return ret;
+ ret = cdns_mhdp_reg_write(&mhdp->base, SOURCE_CEC_CAR, 3);
+ if (ret < 0)
+ return ret;
+
+ ret = cdns_mhdp_reg_write(&mhdp->base, HDTX_CLOCK_REG_0, 0x7c1f);
+ if (ret < 0)
+ return ret;
+ ret = cdns_mhdp_reg_write(&mhdp->base, HDTX_CLOCK_REG_1, 0x7c1f);
+ if (ret < 0)
+ return ret;
+
+ /* init HDMI Controller */
+ val = F_BCH_EN(1) | F_PIC_3D(0xF) | F_CLEAR_AVMUTE(1);
+ ret = cdns_mhdp_reg_write(&mhdp->base, HDTX_CONTROLLER, val);
+ if (ret < 0)
+ return ret;
+
+ return cdns_hdmi_set_hdmi_mode_type(mhdp, tmds_char_rate);
+}
+
+static int cdns_hdmi_mode_config(struct cdns_mhdp8501_device *mhdp,
+ struct drm_display_mode *mode,
+ struct drm_connector_hdmi_state *hdmi)
+{
+ u32 vsync_lines = mode->vsync_end - mode->vsync_start;
+ u32 eof_lines = mode->vsync_start - mode->vdisplay;
+ u32 sof_lines = mode->vtotal - mode->vsync_end;
+ u32 hblank = mode->htotal - mode->hdisplay;
+ u32 hactive = mode->hdisplay;
+ u32 vblank = mode->vtotal - mode->vdisplay;
+ u32 vactive = mode->vdisplay;
+ u32 hfront = mode->hsync_start - mode->hdisplay;
+ u32 hback = mode->htotal - mode->hsync_end;
+ u32 vfront = eof_lines;
+ u32 hsync = hblank - hfront - hback;
+ u32 vsync = vsync_lines;
+ u32 vback = sof_lines;
+ u32 v_h_polarity = ((mode->flags & DRM_MODE_FLAG_NHSYNC) ? 0 : 1) +
+ ((mode->flags & DRM_MODE_FLAG_NVSYNC) ? 0 : 2);
+ int ret;
+ u32 val;
+
+ ret = cdns_mhdp_reg_write(&mhdp->base, SCHEDULER_H_SIZE, (hactive << 16) + hblank);
+ if (ret < 0)
+ return ret;
+
+ ret = cdns_mhdp_reg_write(&mhdp->base, SCHEDULER_V_SIZE, (vactive << 16) + vblank);
+ if (ret < 0)
+ return ret;
+
+ ret = cdns_mhdp_reg_write(&mhdp->base, HDTX_SIGNAL_FRONT_WIDTH, (vfront << 16) + hfront);
+ if (ret < 0)
+ return ret;
+
+ ret = cdns_mhdp_reg_write(&mhdp->base, HDTX_SIGNAL_SYNC_WIDTH, (vsync << 16) + hsync);
+ if (ret < 0)
+ return ret;
+
+ ret = cdns_mhdp_reg_write(&mhdp->base, HDTX_SIGNAL_BACK_WIDTH, (vback << 16) + hback);
+ if (ret < 0)
+ return ret;
+
+ ret = cdns_mhdp_reg_write(&mhdp->base, HSYNC2VSYNC_POL_CTRL, v_h_polarity);
+ if (ret < 0)
+ return ret;
+
+ /* Reset Data Enable */
+ ret = cdns_mhdp_reg_read(&mhdp->base, HDTX_CONTROLLER, &val);
+ if (ret < 0)
+ return ret;
+
+ val &= ~F_DATA_EN(1);
+ ret = cdns_mhdp_reg_write(&mhdp->base, HDTX_CONTROLLER, val);
+ if (ret < 0)
+ return ret;
+
+ /* Set bpc */
+ val &= ~F_VIF_DATA_WIDTH(3);
+ switch (hdmi->output_bpc) {
+ case 10:
+ val |= F_VIF_DATA_WIDTH(1);
+ break;
+ case 12:
+ val |= F_VIF_DATA_WIDTH(2);
+ break;
+ case 16:
+ val |= F_VIF_DATA_WIDTH(3);
+ break;
+ case 8:
+ default:
+ val |= F_VIF_DATA_WIDTH(0);
+ break;
+ }
+
+ /* select color encoding */
+ val &= ~F_HDMI_ENCODING(3);
+ switch (hdmi->output_format) {
+ case HDMI_COLORSPACE_YUV444:
+ val |= F_HDMI_ENCODING(2);
+ break;
+ case HDMI_COLORSPACE_YUV422:
+ val |= F_HDMI_ENCODING(1);
+ break;
+ case HDMI_COLORSPACE_YUV420:
+ val |= F_HDMI_ENCODING(3);
+ break;
+ case HDMI_COLORSPACE_RGB:
+ default:
+ val |= F_HDMI_ENCODING(0);
+ break;
+ }
+
+ ret = cdns_mhdp_reg_write(&mhdp->base, HDTX_CONTROLLER, val);
+ if (ret < 0)
+ return ret;
+
+ /* set data enable */
+ val |= F_DATA_EN(1);
+ return cdns_mhdp_reg_write(&mhdp->base, HDTX_CONTROLLER, val);
+}
+
+static int cdns_hdmi_disable_gcp(struct cdns_mhdp8501_device *mhdp)
+{
+ u32 val;
+ int ret;
+
+ ret = cdns_mhdp_reg_read(&mhdp->base, HDTX_CONTROLLER, &val);
+ if (ret)
+ return ret;
+
+ val &= ~F_GCP_EN(1);
+
+ return cdns_mhdp_reg_write(&mhdp->base, HDTX_CONTROLLER, val);
+}
+
+static int cdns_hdmi_enable_gcp(struct cdns_mhdp8501_device *mhdp)
+{
+ u32 val;
+ int ret;
+
+ ret = cdns_mhdp_reg_read(&mhdp->base, HDTX_CONTROLLER, &val);
+ if (ret)
+ return ret;
+
+ val |= F_GCP_EN(1);
+
+ return cdns_mhdp_reg_write(&mhdp->base, HDTX_CONTROLLER, val);
+}
+
+#define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000)
+static void cdns_hdmi_sink_config(struct cdns_mhdp8501_device *mhdp,
+ struct drm_connector *connector,
+ unsigned long long tmds_char_rate)
+{
+ struct drm_display_info *display = &connector->display_info;
+ struct drm_scdc *scdc = &display->hdmi.scdc;
+ bool hdmi_scrambling = false;
+ bool hdmi_high_tmds_clock_ratio = false;
+
+ /* check sink type (HDMI or DVI) */
+ if (!display->is_hdmi) {
+ mhdp->hdmi.hdmi_type = MODE_DVI;
+ return;
+ }
+
+ /* Default work in HDMI1.4 */
+ mhdp->hdmi.hdmi_type = MODE_HDMI_1_4;
+
+ /* check sink support SCDC or not */
+ if (!scdc->supported) {
+ dev_dbg(mhdp->dev, "Sink Not Support SCDC\n");
+ return;
+ }
+
+ if (tmds_char_rate > HDMI_14_MAX_TMDS_CLK) {
+ hdmi_scrambling = true;
+ hdmi_high_tmds_clock_ratio = true;
+ mhdp->hdmi.hdmi_type = MODE_HDMI_2_0;
+ } else if (scdc->scrambling.low_rates) {
+ hdmi_scrambling = true;
+ mhdp->hdmi.hdmi_type = MODE_HDMI_2_0;
+ }
+
+ /* Set TMDS bit clock ratio to 1/40 or 1/10, and enable/disable scrambling */
+ drm_scdc_set_high_tmds_clock_ratio(connector, hdmi_high_tmds_clock_ratio);
+ drm_scdc_set_scrambling(connector, hdmi_scrambling);
+}
+
+static int cdns_hdmi_bridge_attach(struct drm_bridge *bridge,
+ struct drm_encoder *encoder,
+ enum drm_bridge_attach_flags flags)
+{
+ struct cdns_mhdp8501_device *mhdp = bridge_to_mhdp(bridge);
+
+ if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
+ dev_err(mhdp->dev, "do not support creating a drm_connector\n");
+ return -EINVAL;
+ }
+
+ return drm_bridge_attach(encoder, bridge->next_bridge, bridge,
+ flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR);
+}
+
+static int reset_pipe(struct drm_crtc *crtc)
+{
+ struct drm_atomic_commit *state;
+ struct drm_crtc_state *crtc_state;
+ struct drm_modeset_acquire_ctx ctx;
+ int ret;
+
+ state = drm_atomic_commit_alloc(crtc->dev);
+ if (!state)
+ return -ENOMEM;
+
+ drm_modeset_acquire_init(&ctx, 0);
+
+ state->acquire_ctx = &ctx;
+
+retry:
+ crtc_state = drm_atomic_get_crtc_state(state, crtc);
+ if (IS_ERR(crtc_state)) {
+ ret = PTR_ERR(crtc_state);
+ goto out;
+ }
+
+ crtc_state->connectors_changed = true;
+
+ ret = drm_atomic_commit(state);
+
+out:
+ if (ret == -EDEADLK) {
+ drm_atomic_commit_clear(state);
+ drm_modeset_backoff(&ctx);
+ goto retry;
+ }
+
+ drm_atomic_commit_put(state);
+ drm_modeset_drop_locks(&ctx);
+ drm_modeset_acquire_fini(&ctx);
+
+ return ret;
+}
+
+void cdns_hdmi_handle_hotplug(struct cdns_mhdp8501_device *mhdp)
+{
+ struct drm_crtc *crtc = NULL;
+
+ scoped_guard(mutex, &mhdp->link_mutex) {
+ if (!mhdp->phy_powered)
+ return;
+ crtc = mhdp->curr_crtc;
+ }
+
+ if (!crtc)
+ return;
+
+ /*
+ * HDMI 2.0 says that one should not send scrambled data
+ * prior to configuring the sink scrambling, and that
+ * TMDS clock/data transmission should be suspended when
+ * changing the TMDS clock rate in the sink. So let's
+ * just do a full modeset here, even though some sinks
+ * would be perfectly happy if were to just reconfigure
+ * the SCDC settings on the fly.
+ */
+ reset_pipe(crtc);
+}
+
+static int cdns_hdmi_i2c_write(struct cdns_mhdp8501_device *mhdp,
+ struct i2c_msg *msgs)
+{
+ u8 msg[5], reg[5];
+ int ret;
+
+ if (msgs->len != 2)
+ return -EINVAL;
+
+ msg[0] = msgs->addr;
+ msg[1] = msgs->buf[0];
+ msg[2] = 0;
+ msg[3] = 1;
+ msg[4] = msgs->buf[1];
+
+ ret = cdns_mhdp_mailbox_send_recv(&mhdp->base,
+ MB_MODULE_ID_HDMI_TX, HDMI_TX_WRITE,
+ sizeof(msg), msg, sizeof(reg), reg);
+ if (ret) {
+ dev_err(mhdp->dev, "I2C write failed: %d\n", ret);
+ return ret;
+ }
+
+ if (reg[0] != 0)
+ return -EINVAL;
+
+ return 0;
+}
+
+static int cdns_hdmi_i2c_read(struct cdns_mhdp8501_device *mhdp,
+ struct i2c_msg *msgs, int num)
+{
+ u8 msg[4], reg[5];
+ int ret;
+
+ /* SCDC read is a fixed 2-message transaction: [write offset][read data] */
+ if (num != 2 || (msgs[0].flags & I2C_M_RD) || !(msgs[1].flags & I2C_M_RD))
+ return -EINVAL;
+
+ if (msgs[0].len < 1)
+ return -EINVAL;
+
+ msg[0] = msgs[1].addr;
+ msg[1] = msgs[0].buf[0];
+ put_unaligned_be16(msgs[1].len, msg + 2);
+
+ ret = cdns_mhdp_mailbox_send_recv_multi(&mhdp->base,
+ MB_MODULE_ID_HDMI_TX, HDMI_TX_READ,
+ sizeof(msg), msg,
+ HDMI_TX_READ,
+ sizeof(reg), reg,
+ msgs[1].len, msgs[1].buf);
+ if (ret) {
+ dev_err(mhdp->dev, "I2c Read failed: %d\n", ret);
+ return ret;
+ }
+
+ if (reg[0] != 0)
+ return -EINVAL;
+
+ return 0;
+}
+
+#define SCDC_I2C_SLAVE_ADDRESS 0x54
+static int cdns_hdmi_i2c_xfer(struct i2c_adapter *adap,
+ struct i2c_msg *msgs, int num)
+{
+ struct cdns_mhdp8501_device *mhdp = i2c_get_adapdata(adap);
+ struct cdns_hdmi_i2c *i2c = mhdp->hdmi.i2c;
+ int i, ret = 0;
+
+ /*
+ * MHDP FW provides mailbox APIs for SCDC registers access, but lacks direct I2C APIs.
+ * While individual I2C registers can be read/written using HDMI general register APIs,
+ * block reads (e.g., EDID) are not supported, making it a limited I2C interface.
+ */
+ for (i = 0; i < num; i++) {
+ if (msgs[i].addr != SCDC_I2C_SLAVE_ADDRESS) {
+ dev_err(mhdp->dev, "ADDR=%02x is not supported\n", msgs[i].addr);
+ return -EINVAL;
+ }
+ }
+
+ mutex_lock(&i2c->lock);
+
+ if (num == 1 && !(msgs[0].flags & I2C_M_RD))
+ ret = cdns_hdmi_i2c_write(mhdp, msgs);
+ else
+ ret = cdns_hdmi_i2c_read(mhdp, msgs, num);
+
+ if (!ret)
+ ret = num;
+
+ mutex_unlock(&i2c->lock);
+
+ return ret;
+}
+
+static u32 cdns_hdmi_i2c_func(struct i2c_adapter *adapter)
+{
+ return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
+}
+
+static const struct i2c_algorithm cdns_hdmi_algorithm = {
+ .master_xfer = cdns_hdmi_i2c_xfer,
+ .functionality = cdns_hdmi_i2c_func,
+};
+
+struct i2c_adapter *cdns_hdmi_i2c_adapter(struct cdns_mhdp8501_device *mhdp)
+{
+ struct i2c_adapter *adap;
+ struct cdns_hdmi_i2c *i2c;
+ int ret;
+
+ i2c = devm_kzalloc(mhdp->dev, sizeof(*i2c), GFP_KERNEL);
+ if (!i2c)
+ return ERR_PTR(-ENOMEM);
+
+ mutex_init(&i2c->lock);
+
+ adap = &i2c->adap;
+ adap->owner = THIS_MODULE;
+ adap->dev.parent = mhdp->dev;
+ adap->algo = &cdns_hdmi_algorithm;
+ strscpy(adap->name, "MHDP HDMI", sizeof(adap->name));
+ i2c_set_adapdata(adap, mhdp);
+ mhdp->hdmi.i2c = i2c;
+
+ ret = devm_i2c_add_adapter(mhdp->dev, adap);
+ if (ret) {
+ dev_warn(mhdp->dev, "cannot add %s I2C adapter\n", adap->name);
+ mutex_destroy(&i2c->lock);
+ return ERR_PTR(ret);
+ }
+
+ return adap;
+}
+
+static enum drm_mode_status
+cdns_hdmi_tmds_char_rate_valid(const struct drm_bridge *bridge,
+ const struct drm_display_mode *mode,
+ unsigned long long tmds_rate)
+{
+ struct cdns_mhdp8501_device *mhdp = bridge_to_mhdp(bridge);
+ union phy_configure_opts phy_cfg = {};
+ int ret;
+
+ phy_cfg.hdmi.tmds_char_rate = tmds_rate;
+
+ ret = phy_validate(mhdp->phy, PHY_MODE_HDMI, 0, &phy_cfg);
+ if (ret < 0)
+ return MODE_CLOCK_RANGE;
+
+ return MODE_OK;
+}
+
+static const struct drm_edid
+*cdns_hdmi_bridge_edid_read(struct drm_bridge *bridge,
+ struct drm_connector *connector)
+{
+ struct cdns_mhdp8501_device *mhdp = bridge_to_mhdp(bridge);
+
+ return drm_edid_read_custom(connector, cdns_hdmi_get_edid_block, mhdp);
+}
+
+static void cdns_hdmi_bridge_atomic_disable(struct drm_bridge *bridge,
+ struct drm_atomic_commit *state)
+{
+ struct cdns_mhdp8501_device *mhdp = bridge_to_mhdp(bridge);
+
+ scoped_guard(mutex, &mhdp->link_mutex) {
+ mhdp->curr_crtc = NULL;
+ if (mhdp->phy_powered) {
+ phy_power_off(mhdp->phy);
+ mhdp->phy_powered = false;
+ }
+ }
+}
+
+static void cdns_hdmi_bridge_atomic_enable(struct drm_bridge *bridge,
+ struct drm_atomic_commit *state)
+{
+ struct cdns_mhdp8501_device *mhdp = bridge_to_mhdp(bridge);
+ struct drm_connector *connector;
+ struct drm_crtc_state *crtc_state;
+ struct drm_connector_state *conn_state;
+ struct drm_connector_hdmi_state *hdmi;
+ union phy_configure_opts phy_cfg = {};
+ int ret;
+
+ connector = drm_atomic_get_new_connector_for_encoder(state,
+ bridge->encoder);
+ if (WARN_ON(!connector))
+ return;
+
+ conn_state = drm_atomic_get_new_connector_state(state, connector);
+ if (WARN_ON(!conn_state))
+ return;
+
+ crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
+ if (WARN_ON(!crtc_state))
+ return;
+
+ /* Line swapping */
+ ret = cdns_mhdp_reg_write(&mhdp->base, LANES_CONFIG, 0x00400000 | mhdp->lane_mapping);
+ if (ret) {
+ dev_err(mhdp->dev, "Failed to configure lane mapping: %d\n", ret);
+ return;
+ }
+
+ hdmi = &conn_state->hdmi;
+
+ phy_cfg.hdmi.tmds_char_rate = hdmi->tmds_char_rate;
+ ret = phy_configure(mhdp->phy, &phy_cfg);
+ if (ret) {
+ dev_err(mhdp->dev, "%s: phy_configure() failed: %d\n",
+ __func__, ret);
+ return;
+ }
+
+ scoped_guard(mutex, &mhdp->link_mutex) {
+ mhdp->curr_crtc = conn_state->crtc;
+
+ phy_power_on(mhdp->phy);
+ mhdp->phy_powered = true;
+
+ cdns_hdmi_sink_config(mhdp, connector, hdmi->tmds_char_rate);
+
+ ret = cdns_hdmi_ctrl_init(mhdp, hdmi->tmds_char_rate);
+ if (ret < 0) {
+ dev_err(mhdp->dev, "hdmi ctrl init failed = %d\n", ret);
+ phy_power_off(mhdp->phy);
+ mhdp->phy_powered = false;
+ mhdp->curr_crtc = NULL;
+ return;
+ }
+
+ /* Config GCP */
+ if (hdmi->output_bpc == 8)
+ ret = cdns_hdmi_disable_gcp(mhdp);
+ else
+ ret = cdns_hdmi_enable_gcp(mhdp);
+ if (ret < 0) {
+ dev_err(mhdp->dev, "Failed to configure GCP: %d\n", ret);
+ phy_power_off(mhdp->phy);
+ mhdp->phy_powered = false;
+ mhdp->curr_crtc = NULL;
+ return;
+ }
+
+ ret = cdns_hdmi_mode_config(mhdp, &crtc_state->adjusted_mode, hdmi);
+ if (ret < 0) {
+ dev_err(mhdp->dev, "CDN_API_HDMITX_SetVic_blocking ret = %d\n", ret);
+ phy_power_off(mhdp->phy);
+ mhdp->phy_powered = false;
+ mhdp->curr_crtc = NULL;
+ return;
+ }
+
+ drm_atomic_helper_connector_hdmi_update_infoframes(connector, state);
+ }
+}
+
+static int cdns_hdmi_bridge_clear_avi_infoframe(struct drm_bridge *bridge)
+{
+ struct cdns_mhdp8501_device *mhdp = bridge_to_mhdp(bridge);
+
+ cdns_hdmi_clear_infoframe(mhdp, 0, HDMI_INFOFRAME_TYPE_AVI);
+
+ return 0;
+}
+
+static int cdns_hdmi_bridge_write_avi_infoframe(struct drm_bridge *bridge,
+ const u8 *buffer, size_t len)
+{
+ struct cdns_mhdp8501_device *mhdp = bridge_to_mhdp(bridge);
+
+ cdns_hdmi_config_infoframe(mhdp, 0, len, buffer, HDMI_INFOFRAME_TYPE_AVI);
+
+ return 0;
+}
+
+static int cdns_hdmi_bridge_clear_spd_infoframe(struct drm_bridge *bridge)
+{
+ struct cdns_mhdp8501_device *mhdp = bridge_to_mhdp(bridge);
+
+ cdns_hdmi_clear_infoframe(mhdp, 1, HDMI_INFOFRAME_TYPE_SPD);
+
+ return 0;
+}
+
+static int cdns_hdmi_bridge_write_spd_infoframe(struct drm_bridge *bridge,
+ const u8 *buffer, size_t len)
+{
+ struct cdns_mhdp8501_device *mhdp = bridge_to_mhdp(bridge);
+
+ cdns_hdmi_config_infoframe(mhdp, 1, len, buffer, HDMI_INFOFRAME_TYPE_SPD);
+
+ return 0;
+}
+
+static int cdns_hdmi_bridge_clear_hdmi_infoframe(struct drm_bridge *bridge)
+{
+ struct cdns_mhdp8501_device *mhdp = bridge_to_mhdp(bridge);
+
+ cdns_hdmi_clear_infoframe(mhdp, 2, HDMI_INFOFRAME_TYPE_VENDOR);
+
+ return 0;
+}
+
+static int cdns_hdmi_bridge_write_hdmi_infoframe(struct drm_bridge *bridge,
+ const u8 *buffer, size_t len)
+{
+ struct cdns_mhdp8501_device *mhdp = bridge_to_mhdp(bridge);
+
+ cdns_hdmi_config_infoframe(mhdp, 2, len, buffer, HDMI_INFOFRAME_TYPE_VENDOR);
+
+ return 0;
+}
+
+static int cdns_hdmi_bridge_atomic_check(struct drm_bridge *bridge,
+ struct drm_bridge_state *bridge_state,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state)
+{
+ return drm_atomic_helper_connector_hdmi_check(conn_state->connector, conn_state->state);
+}
+
+const struct drm_bridge_funcs cdns_hdmi_bridge_funcs = {
+ .attach = cdns_hdmi_bridge_attach,
+ .detect = cdns_mhdp8501_detect,
+ .edid_read = cdns_hdmi_bridge_edid_read,
+ .mode_valid = cdns_mhdp8501_mode_valid,
+ .atomic_enable = cdns_hdmi_bridge_atomic_enable,
+ .atomic_disable = cdns_hdmi_bridge_atomic_disable,
+ .atomic_check = cdns_hdmi_bridge_atomic_check,
+ .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
+ .atomic_reset = drm_atomic_helper_bridge_reset,
+ .hdmi_clear_hdmi_infoframe = cdns_hdmi_bridge_clear_hdmi_infoframe,
+ .hdmi_write_hdmi_infoframe = cdns_hdmi_bridge_write_hdmi_infoframe,
+ .hdmi_clear_avi_infoframe = cdns_hdmi_bridge_clear_avi_infoframe,
+ .hdmi_write_avi_infoframe = cdns_hdmi_bridge_write_avi_infoframe,
+ .hdmi_clear_spd_infoframe = cdns_hdmi_bridge_clear_spd_infoframe,
+ .hdmi_write_spd_infoframe = cdns_hdmi_bridge_write_spd_infoframe,
+ .hdmi_tmds_char_rate_valid = cdns_hdmi_tmds_char_rate_valid,
+};
--
2.51.0
^ permalink raw reply related
* [PATCH v23 7/8] arm64: dts: imx8mq: Add DCSS + HDMI/DP display pipeline
From: Laurentiu Palcu @ 2026-05-19 14:42 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: Laurentiu Palcu, dri-devel, devicetree, linux-kernel, linux-phy,
imx, linux-arm-kernel, linux, Alexander Stein, Ying Liu
In-Reply-To: <20260519-dcss-hdmi-upstreaming-v23-0-5615524a9c63@oss.nxp.com>
From: Alexander Stein <alexander.stein@ew.tq-group.com>
This adds DCSS + MHDP + MHDP PHY nodes. PHY mode (DP/HDMI) is selected
by the connector type connected to mhdp port@1 endpoint.
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 60 +++++++++++++++++++++++++++++++
1 file changed, 60 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 6a25e219832ce..82dc75a787499 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -1598,6 +1598,66 @@ aips4: bus@32c00000 { /* AIPS4 */
#size-cells = <1>;
ranges = <0x32c00000 0x32c00000 0x400000>;
+ mhdp: bridge@32c00000 {
+ compatible = "fsl,imx8mq-mhdp8501-hdmi";
+ reg = <0x32c00000 0x100000>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "plug_in", "plug_out";
+ clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
+ phys = <&mhdp_phy>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mhdp_in: endpoint {
+ remote-endpoint = <&dcss_out>;
+ };
+ };
+ };
+
+ mhdp_phy: phy {
+ compatible = "fsl,imx8mq-hdptx-phy";
+ #phy-cells = <0>;
+ clocks = <&hdmi_phy_27m>, <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
+ clock-names = "ref", "apb";
+ };
+ };
+
+ dcss: display-controller@32e00000 {
+ compatible = "nxp,imx8mq-dcss";
+ reg = <0x32e00000 0x2d000>, <0x32e2f000 0x1000>;
+ interrupt-parent = <&irqsteer>;
+ interrupts = <6>, <8>, <9>;
+ interrupt-names = "ctxld", "ctxld_kick", "vblank";
+ clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>,
+ <&clk IMX8MQ_CLK_DISP_AXI_ROOT>,
+ <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>,
+ <&clk IMX8MQ_VIDEO2_PLL_OUT>,
+ <&clk IMX8MQ_CLK_DISP_DTRC>;
+ clock-names = "apb", "axi", "rtrm", "pix", "dtrc";
+ assigned-clocks = <&clk IMX8MQ_CLK_DISP_AXI>,
+ <&clk IMX8MQ_CLK_DISP_RTRM>,
+ <&clk IMX8MQ_VIDEO2_PLL1_REF_SEL>;
+ assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>,
+ <&clk IMX8MQ_SYS1_PLL_800M>,
+ <&clk IMX8MQ_CLK_27M>;
+ assigned-clock-rates = <800000000>,
+ <400000000>;
+ status = "disabled";
+
+ port {
+ dcss_out: endpoint {
+ remote-endpoint = <&mhdp_in>;
+ };
+ };
+ };
+
irqsteer: interrupt-controller@32e2d000 {
compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer";
reg = <0x32e2d000 0x1000>;
--
2.51.0
^ permalink raw reply related
* [PATCH v23 5/8] dt-bindings: display: bridge: Add Cadence MHDP8501
From: Laurentiu Palcu @ 2026-05-19 14:42 UTC (permalink / raw)
To: Andrzej Hajda, Neil Armstrong, Robert Foss, Laurent Pinchart,
Jonas Karlman, Jernej Skrabec, Luca Ceresoli, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, David Airlie, Simona Vetter,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Laurentiu Palcu, dri-devel, devicetree, linux-kernel, linux-phy,
imx, linux-arm-kernel, linux, Alexander Stein, Ying Liu
In-Reply-To: <20260519-dcss-hdmi-upstreaming-v23-0-5615524a9c63@oss.nxp.com>
From: Sandor Yu <Sandor.yu@nxp.com>
Add bindings for Cadence MHDP8501 DisplayPort/HDMI bridge.
Signed-off-by: Sandor Yu <Sandor.yu@nxp.com>
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
---
.../bindings/display/bridge/cdns,mhdp8501.yaml | 136 +++++++++++++++++++++
1 file changed, 136 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml
new file mode 100644
index 0000000000000..57e7e95199777
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8501.yaml
@@ -0,0 +1,136 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/cdns,mhdp8501.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Cadence MHDP8501 DP/HDMI bridge
+
+maintainers:
+ - Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
+
+description:
+ Cadence MHDP8501 DisplayPort/HDMI interface.
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx8mq-mhdp8501-hdmi
+ - fsl,imx8mq-mhdp8501-dp
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+ description: MHDP8501 DP/HDMI APB clock.
+
+ phys:
+ maxItems: 1
+ description:
+ phandle to the DP/HDMI PHY
+
+ interrupts:
+ items:
+ - description: Hotplug cable plugin.
+ - description: Hotplug cable plugout.
+
+ interrupt-names:
+ items:
+ - const: plug_in
+ - const: plug_out
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ Input port from display controller output.
+
+ port@1:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description:
+ Output port to DisplayPort or HDMI connector.
+
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ description: Lane reordering for HDMI or DisplayPort interface.
+ minItems: 4
+ maxItems: 4
+
+ required:
+ - data-lanes
+
+ required:
+ - port@0
+ - port@1
+
+ phy:
+ description:
+ Child node describing the Cadence HDP-TX DP/HDMI PHY, which shares
+ the same MMIO region as the bridge.
+ $ref: /schemas/phy/fsl,imx8mq-hdptx-phy.yaml#
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - interrupts
+ - interrupt-names
+ - phys
+ - ports
+ - phy
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx8mq-clock.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ display-bridge@32c00000 {
+ compatible = "fsl,imx8mq-mhdp8501-dp";
+ reg = <0x32c00000 0x100000>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "plug_in", "plug_out";
+ clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
+ phys = <&mhdp_phy>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mhdp_in: endpoint {
+ remote-endpoint = <&dcss_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mhdp_out: endpoint {
+ remote-endpoint = <&dp_connector>;
+ data-lanes = <2 1 0 3>;
+ };
+ };
+ };
+
+ mhdp_phy: phy {
+ compatible = "fsl,imx8mq-hdptx-phy";
+ #phy-cells = <0>;
+ clocks = <&hdmi_phy_27m>, <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
+ clock-names = "ref", "apb";
+ };
+ };
--
2.51.0
^ permalink raw reply related
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