* [PATCH v1 0/6] perf vendor events intel: update
From: Chun-Tse Shao @ 2026-06-09 21:50 UTC (permalink / raw)
To: peterz, mingo, acme, namhyung
Cc: alexander.shishkin, jolsa, irogers, adrian.hunter, james.clark,
afaerber, mani, dapeng1.mi, linux-perf-users, linux-kernel,
linux-arm-kernel, linux-actions, Chun-Tse Shao
Sync with the latest perfmon events from:
https://github.com/intel/perfmon
by running the script:
https://github.com/intel/perfmon/blob/main/scripts/create_perf_json.py
and copying the resulting json and mapfile.csv changes into the perf
tree.
Chun-Tse Shao (6):
perf vendor events intel: Update arrowlake events from 1.17 to 1.19
perf vendor events intel: Update emeraldrapids events from 1.23 to
1.24
perf vendor events intel: Update graniterapids events from 1.18 to
1.19
perf vendor events intel: Update lunarlake events from 1.22 to 1.25
perf vendor events intel: Update pantherlake events from 1.05 to 1.06
perf vendor events intel: Update tigerlake events from 1.18 to 1.19
.../pmu-events/arch/x86/arrowlake/cache.json | 30 ++-
.../arch/x86/arrowlake/floating-point.json | 45 ++++
.../pmu-events/arch/x86/arrowlake/memory.json | 18 ++
.../arch/x86/arrowlake/pipeline.json | 129 +++++++++-
.../arch/x86/emeraldrapids/cache.json | 9 +
.../graniterapids/uncore-interconnect.json | 10 +
.../arch/x86/graniterapids/uncore-memory.json | 2 +-
.../pmu-events/arch/x86/lunarlake/cache.json | 2 +-
.../arch/x86/lunarlake/pipeline.json | 27 ++-
.../arch/x86/lunarlake/uncore-memory.json | 208 ++++++++++++++++-
tools/perf/pmu-events/arch/x86/mapfile.csv | 12 +-
.../arch/x86/pantherlake/counter.json | 5 +
.../arch/x86/pantherlake/pipeline.json | 29 ++-
.../x86/pantherlake/uncore-interconnect.json | 10 +
.../arch/x86/pantherlake/uncore-memory.json | 221 +++++++++++++++++-
15 files changed, 728 insertions(+), 29 deletions(-)
create mode 100644 tools/perf/pmu-events/arch/x86/pantherlake/uncore-interconnect.json
--
2.54.0.1099.g489fc7bff1-goog
^ permalink raw reply
* [PATCH v1 1/6] perf vendor events intel: Update arrowlake events from 1.17 to 1.19
From: Chun-Tse Shao @ 2026-06-09 21:50 UTC (permalink / raw)
To: peterz, mingo, acme, namhyung
Cc: alexander.shishkin, jolsa, irogers, adrian.hunter, james.clark,
afaerber, mani, dapeng1.mi, linux-perf-users, linux-kernel,
linux-arm-kernel, linux-actions, Chun-Tse Shao
In-Reply-To: <20260609215046.2391903-1-ctshao@google.com>
The updated events were published in:
https://github.com/intel/perfmon/commit/b84e75626ae78558b8f526a276e4597c5ca6c429
Signed-off-by: Chun-Tse Shao <ctshao@google.com>
---
.../pmu-events/arch/x86/arrowlake/cache.json | 30 +++-
.../arch/x86/arrowlake/floating-point.json | 45 ++++++
.../pmu-events/arch/x86/arrowlake/memory.json | 18 +++
.../arch/x86/arrowlake/pipeline.json | 129 +++++++++++++++++-
tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +-
5 files changed, 217 insertions(+), 7 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/arrowlake/cache.json b/tools/perf/pmu-events/arch/x86/arrowlake/cache.json
index fe6b9ad68f87..142f62c59531 100644
--- a/tools/perf/pmu-events/arch/x86/arrowlake/cache.json
+++ b/tools/perf/pmu-events/arch/x86/arrowlake/cache.json
@@ -1,6 +1,6 @@
[
{
- "BriefDescription": "Counts the number of request that were not accepted into the L2Q because the L2Q is FULL.",
+ "BriefDescription": "Counts the number of requests that were not accepted into the L2Q because the L2Q is FULL.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x31",
"EventName": "CORE_REJECT_L2Q.ANY",
@@ -8,6 +8,15 @@
"SampleAfterValue": "1000003",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the number of requests that were not accepted into the L2Q because the L2Q is FULL.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x31",
+ "EventName": "CORE_REJECT_L2Q.ANY",
+ "PublicDescription": "Counts the number of (demand and L1 prefetchers) core requests rejected by the L2Q due to a full or nearly full w condition which likely indicates back pressure from L2Q. It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link. The L2Q may also reject transactions from a core to insure fairness between cores, or to delay a cores dirty eviction when the address conflicts incoming external snoops. (Note that L2 prefetcher requests that are dropped are not counted by this event.) Counts on a per core basis.",
+ "SampleAfterValue": "200003",
+ "Unit": "cpu_lowpower"
+ },
{
"BriefDescription": "Counts the number of L1D cacheline (dirty) evictions caused by load misses, stores, and prefetches.",
"Counter": "0,1,2,3,4,5,6,7",
@@ -310,6 +319,15 @@
"SampleAfterValue": "1000003",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x30",
+ "EventName": "L2_REJECT_XQ.ANY",
+ "PublicDescription": "Counts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition which likely indicates back pressure from the IDI link. The XQ may reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses) and WOB (L2 write-back victims).",
+ "SampleAfterValue": "200003",
+ "Unit": "cpu_lowpower"
+ },
{
"BriefDescription": "Counts the number of L2 Cache Accesses Counts the total number of L2 Cache Accesses - sum of hits, misses, rejects front door requests for CRd/DRd/RFO/ItoM/L2 Prefetches only, per core event",
"Counter": "0,1,2,3,4,5,6,7",
@@ -1382,6 +1400,16 @@
"UMask": "0x83",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the number of memory uops retired. A single uop that performs both a load AND a store will be counted as 1, not 2 (e.g. ADD [mem], CONST)",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "Data_LA": "1",
+ "EventCode": "0xd0",
+ "EventName": "MEM_UOPS_RETIRED.ALL",
+ "SampleAfterValue": "200003",
+ "UMask": "0x83",
+ "Unit": "cpu_lowpower"
+ },
{
"BriefDescription": "Counts the number of load uops retired.",
"Counter": "0,1,2,3,4,5,6,7",
diff --git a/tools/perf/pmu-events/arch/x86/arrowlake/floating-point.json b/tools/perf/pmu-events/arch/x86/arrowlake/floating-point.json
index c54fc201a6ca..8dc3a11350c5 100644
--- a/tools/perf/pmu-events/arch/x86/arrowlake/floating-point.json
+++ b/tools/perf/pmu-events/arch/x86/arrowlake/floating-point.json
@@ -510,6 +510,15 @@
"UMask": "0x1f",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the number of uops executed on all floating point ports.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xb2",
+ "EventName": "FP_VINT_UOPS_EXECUTED.ALL",
+ "SampleAfterValue": "1000003",
+ "UMask": "0xf",
+ "Unit": "cpu_lowpower"
+ },
{
"BriefDescription": "Counts the number of uops executed on floating point and vector integer port 0.",
"Counter": "0,1,2,3,4,5,6,7",
@@ -519,6 +528,15 @@
"UMask": "0x2",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the number of uops executed on floating point and vector integer port 0.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xb2",
+ "EventName": "FP_VINT_UOPS_EXECUTED.P0",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x2",
+ "Unit": "cpu_lowpower"
+ },
{
"BriefDescription": "Counts the number of uops executed on floating point and vector integer port 1.",
"Counter": "0,1,2,3,4,5,6,7",
@@ -528,6 +546,15 @@
"UMask": "0x4",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the number of uops executed on floating point and vector integer port 1.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xb2",
+ "EventName": "FP_VINT_UOPS_EXECUTED.P1",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x4",
+ "Unit": "cpu_lowpower"
+ },
{
"BriefDescription": "Counts the number of uops executed on floating point and vector integer port 2.",
"Counter": "0,1,2,3,4,5,6,7",
@@ -537,6 +564,15 @@
"UMask": "0x8",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the number of uops executed on floating point and vector integer port 2.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xb2",
+ "EventName": "FP_VINT_UOPS_EXECUTED.P2",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x8",
+ "Unit": "cpu_lowpower"
+ },
{
"BriefDescription": "Counts the number of uops executed on floating point and vector integer port 3.",
"Counter": "0,1,2,3,4,5,6,7",
@@ -555,6 +591,15 @@
"UMask": "0x1e",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the number of uops executed on floating point and vector integer port 0, 1, 2.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xb2",
+ "EventName": "FP_VINT_UOPS_EXECUTED.PRIMARY",
+ "SampleAfterValue": "1000003",
+ "UMask": "0xe",
+ "Unit": "cpu_lowpower"
+ },
{
"BriefDescription": "Counts the number of uops executed on floating point and vector integer store data port.",
"Counter": "0,1,2,3,4,5,6,7",
diff --git a/tools/perf/pmu-events/arch/x86/arrowlake/memory.json b/tools/perf/pmu-events/arch/x86/arrowlake/memory.json
index 05cc46518232..44922186c2b0 100644
--- a/tools/perf/pmu-events/arch/x86/arrowlake/memory.json
+++ b/tools/perf/pmu-events/arch/x86/arrowlake/memory.json
@@ -173,6 +173,15 @@
"UMask": "0x2",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to request buffers full or lock in progress.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x05",
+ "EventName": "LD_HEAD.WCB_FULL",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x2",
+ "Unit": "cpu_lowpower"
+ },
{
"BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to request buffers full or lock in progress.",
"Counter": "0,1,2,3,4,5,6,7",
@@ -182,6 +191,15 @@
"UMask": "0x82",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to request buffers full or lock in progress.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x05",
+ "EventName": "LD_HEAD.WCB_FULL_AT_RET",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x82",
+ "Unit": "cpu_lowpower"
+ },
{
"BriefDescription": "Counts the number of memory ordering machine clears triggered due to a snoop from an external agent. Does not count internally generated machine clears such as those due to disambiguations.",
"Counter": "0,1,2,3,4,5,6,7",
diff --git a/tools/perf/pmu-events/arch/x86/arrowlake/pipeline.json b/tools/perf/pmu-events/arch/x86/arrowlake/pipeline.json
index a0fd63cace22..bdfee0347cc5 100644
--- a/tools/perf/pmu-events/arch/x86/arrowlake/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/arrowlake/pipeline.json
@@ -209,7 +209,6 @@
"EventName": "BR_INST_RETIRED.COND_TAKEN_FWD",
"PublicDescription": "Counts taken forward conditional branch instructions retired. Available PDIST counters: 0,1",
"SampleAfterValue": "400009",
- "UMask": "0x102",
"Unit": "cpu_core"
},
{
@@ -608,7 +607,7 @@
"EventName": "BR_MISP_RETIRED.COND_TAKEN_BWD_COST",
"PublicDescription": "number of branch instructions retired that were mispredicted and taken backward. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. Available PDIST counters: 0,1",
"SampleAfterValue": "400009",
- "UMask": "0x8001",
+ "UMask": "0x41",
"Unit": "cpu_core"
},
{
@@ -637,7 +636,7 @@
"EventName": "BR_MISP_RETIRED.COND_TAKEN_FWD_COST",
"PublicDescription": "number of branch instructions retired that were mispredicted and taken forward. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. Available PDIST counters: 0,1",
"SampleAfterValue": "400009",
- "UMask": "0x8002",
+ "UMask": "0x140",
"Unit": "cpu_core"
},
{
@@ -773,11 +772,11 @@
"Unit": "cpu_core"
},
{
- "BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS",
+ "BriefDescription": "This event counts the number of mispredicted ret instructions retired.",
"Counter": "0,1,2,3,4,5,6,7,8,9",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.RET",
- "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired. Available PDIST counters: 0,1",
+ "PublicDescription": "This event counts the number of mispredicted ret instructions retired. Available PDIST counters: 0,1",
"SampleAfterValue": "100007",
"UMask": "0x8",
"Unit": "cpu_core"
@@ -1326,6 +1325,15 @@
"UMask": "0xff",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the number of uops executed on all Integer ports.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xb3",
+ "EventName": "INT_UOPS_EXECUTED.ALL",
+ "SampleAfterValue": "1000003",
+ "UMask": "0xff",
+ "Unit": "cpu_lowpower"
+ },
{
"BriefDescription": "Counts the number of uops executed on a load port.",
"Counter": "0,1,2,3,4,5,6,7",
@@ -1336,6 +1344,16 @@
"UMask": "0x1",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the number of uops executed on a load port.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xb3",
+ "EventName": "INT_UOPS_EXECUTED.LD",
+ "PublicDescription": "Counts the number of uops executed on a load port. This event counts for integer uops even if the destination is FP/vector",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x1",
+ "Unit": "cpu_lowpower"
+ },
{
"BriefDescription": "Counts the number of uops executed on integer port 0.",
"Counter": "0,1,2,3,4,5,6,7",
@@ -1345,6 +1363,15 @@
"UMask": "0x8",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the number of uops executed on integer port 0.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xb3",
+ "EventName": "INT_UOPS_EXECUTED.P0",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x8",
+ "Unit": "cpu_lowpower"
+ },
{
"BriefDescription": "Counts the number of uops executed on integer port 1.",
"Counter": "0,1,2,3,4,5,6,7",
@@ -1354,6 +1381,15 @@
"UMask": "0x10",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the number of uops executed on integer port 1.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xb3",
+ "EventName": "INT_UOPS_EXECUTED.P1",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x10",
+ "Unit": "cpu_lowpower"
+ },
{
"BriefDescription": "Counts the number of uops executed on integer port 2.",
"Counter": "0,1,2,3,4,5,6,7",
@@ -1363,6 +1399,15 @@
"UMask": "0x20",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the number of uops executed on integer port 2.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xb3",
+ "EventName": "INT_UOPS_EXECUTED.P2",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x20",
+ "Unit": "cpu_lowpower"
+ },
{
"BriefDescription": "Counts the number of uops executed on integer port 3.",
"Counter": "0,1,2,3,4,5,6,7",
@@ -1372,6 +1417,15 @@
"UMask": "0x40",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the number of uops executed on integer port 3.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xb3",
+ "EventName": "INT_UOPS_EXECUTED.P3",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x40",
+ "Unit": "cpu_lowpower"
+ },
{
"BriefDescription": "Counts the number of uops executed on integer port 0,1, 2, 3.",
"Counter": "0,1,2,3,4,5,6,7",
@@ -1381,6 +1435,15 @@
"UMask": "0x78",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the number of uops executed on integer port 0,1, 2, 3.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xb3",
+ "EventName": "INT_UOPS_EXECUTED.PRIMARY",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x78",
+ "Unit": "cpu_lowpower"
+ },
{
"BriefDescription": "Counts the number of uops executed on a Store address port.",
"Counter": "0,1,2,3,4,5,6,7",
@@ -1391,6 +1454,16 @@
"UMask": "0x2",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the number of uops executed on a Store address port.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xb3",
+ "EventName": "INT_UOPS_EXECUTED.STA",
+ "PublicDescription": "Counts the number of uops executed on a Store address port. This event counts integer uops even if the data source is FP/vector",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x2",
+ "Unit": "cpu_lowpower"
+ },
{
"BriefDescription": "Counts the number of uops executed on an integer store data and jump port.",
"Counter": "0,1,2,3,4,5,6,7",
@@ -1400,6 +1473,15 @@
"UMask": "0x4",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the number of uops executed on an integer store data and jump port.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xb3",
+ "EventName": "INT_UOPS_EXECUTED.STD_JMP",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x4",
+ "Unit": "cpu_lowpower"
+ },
{
"BriefDescription": "Number of vector integer instructions retired of 128-bit vector-width.",
"Counter": "0,1,2,3,4,5,6,7,8,9",
@@ -1691,6 +1773,15 @@
"UMask": "0x88",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the number of machine clears that flush the pipeline and restart the machine without the use of microcode.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xc3",
+ "EventName": "MACHINE_CLEARS.FAST",
+ "SampleAfterValue": "20003",
+ "UMask": "0x10",
+ "Unit": "cpu_lowpower"
+ },
{
"BriefDescription": "Counts number of virtual trap actually taken (e.g. highest priority event during retirement). It can count virtual trap from FPC port 0 or port 1 (x87/SSE) equally in a single counter.",
"Counter": "0,1,2,3,4,5,6,7",
@@ -1700,6 +1791,15 @@
"UMask": "0x40",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the number of virtual traps taken.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xc3",
+ "EventName": "MACHINE_CLEARS.FPC_VIRTUAL_TRAP",
+ "SampleAfterValue": "20003",
+ "UMask": "0x40",
+ "Unit": "cpu_lowpower"
+ },
{
"BriefDescription": "Counts the number of nukes due to memory renaming",
"Counter": "0,1,2,3,4,5,6,7",
@@ -2015,6 +2115,15 @@
"UMask": "0x8",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the number of issue slots not consumed due to a color request for an FCW or MXCSR control register when all 4 colors (copies) are already in use.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x75",
+ "EventName": "SERIALIZATION.COLOR_STALLS",
+ "SampleAfterValue": "200003",
+ "UMask": "0x8",
+ "Unit": "cpu_lowpower"
+ },
{
"BriefDescription": "Counts the number of issue slots where no uop could issue due to an IQ scoreboard that stalls allocation until a specified older uop retires or (in the case of jump scoreboard) executes. Commonly executed instructions with IQ scoreboards include LFENCE and MFENCE.",
"Counter": "0,1,2,3,4,5,6,7",
@@ -2034,6 +2143,16 @@
"UMask": "0x2",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the number of issue slots not consumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the front-end from issuing from the UROM until a specified older uop retires.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0x75",
+ "EventName": "SERIALIZATION.NON_C01_MS_SCB",
+ "PublicDescription": "Counts the number of issue slots not consumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the front-end from issuing from the UROM until a specified older uop retires. The most commonly executed instruction with an MS scoreboard is PAUSE.",
+ "SampleAfterValue": "200003",
+ "UMask": "0x2",
+ "Unit": "cpu_lowpower"
+ },
{
"BriefDescription": "This event counts a subset of the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution units limitations, or other conditions.",
"Counter": "0,1,2,3,4,5,6,7,8,9",
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index 50a403b429b1..613881d04a9a 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -1,7 +1,7 @@
Family-model,Version,Filename,EventType
GenuineIntel-6-(97|9A|B7|BA|BF),v1.39,alderlake,core
GenuineIntel-6-BE,v1.39,alderlaken,core
-GenuineIntel-6-C[56],v1.17,arrowlake,core
+GenuineIntel-6-C[56],v1.19,arrowlake,core
GenuineIntel-6-(1C|26|27|35|36),v5,bonnell,core
GenuineIntel-6-(3D|47),v30,broadwell,core
GenuineIntel-6-56,v12,broadwellde,core
--
2.54.0.1099.g489fc7bff1-goog
^ permalink raw reply related
* [PATCH v1 2/6] perf vendor events intel: Update emeraldrapids events from 1.23 to 1.24
From: Chun-Tse Shao @ 2026-06-09 21:50 UTC (permalink / raw)
To: peterz, mingo, acme, namhyung
Cc: alexander.shishkin, jolsa, irogers, adrian.hunter, james.clark,
afaerber, mani, dapeng1.mi, linux-perf-users, linux-kernel,
linux-arm-kernel, linux-actions, Chun-Tse Shao
In-Reply-To: <20260609215046.2391903-1-ctshao@google.com>
The updated events were published in:
https://github.com/intel/perfmon/commit/3f1d40d1953193e75c6b5a559638cf1f67bacaed
Signed-off-by: Chun-Tse Shao <ctshao@google.com>
---
tools/perf/pmu-events/arch/x86/emeraldrapids/cache.json | 9 +++++++++
tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +-
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/tools/perf/pmu-events/arch/x86/emeraldrapids/cache.json b/tools/perf/pmu-events/arch/x86/emeraldrapids/cache.json
index ff6071d7728e..a44e1f027c1d 100644
--- a/tools/perf/pmu-events/arch/x86/emeraldrapids/cache.json
+++ b/tools/perf/pmu-events/arch/x86/emeraldrapids/cache.json
@@ -368,6 +368,15 @@
"SampleAfterValue": "200003",
"UMask": "0x40"
},
+ {
+ "BriefDescription": "Cycles when L1D is locked",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x42",
+ "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
+ "PublicDescription": "This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION).",
+ "SampleAfterValue": "2000003",
+ "UMask": "0x2"
+ },
{
"BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)",
"Counter": "0,1,2,3,4,5,6,7",
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index 613881d04a9a..0f39073805ba 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -9,7 +9,7 @@ GenuineIntel-6-4F,v23,broadwellx,core
GenuineIntel-6-55-[56789ABCDEF],v1.25,cascadelakex,core
GenuineIntel-6-DD,v1.02,clearwaterforest,core
GenuineIntel-6-9[6C],v1.05,elkhartlake,core
-GenuineIntel-6-CF,v1.23,emeraldrapids,core
+GenuineIntel-6-CF,v1.24,emeraldrapids,core
GenuineIntel-6-5[CF],v13,goldmont,core
GenuineIntel-6-7A,v1.01,goldmontplus,core
GenuineIntel-6-B6,v1.12,grandridge,core
--
2.54.0.1099.g489fc7bff1-goog
^ permalink raw reply related
* [PATCH v1 4/6] perf vendor events intel: Update lunarlake events from 1.22 to 1.25
From: Chun-Tse Shao @ 2026-06-09 21:50 UTC (permalink / raw)
To: peterz, mingo, acme, namhyung
Cc: alexander.shishkin, jolsa, irogers, adrian.hunter, james.clark,
afaerber, mani, dapeng1.mi, linux-perf-users, linux-kernel,
linux-arm-kernel, linux-actions, Chun-Tse Shao
In-Reply-To: <20260609215046.2391903-1-ctshao@google.com>
The updated events were published in:
https://github.com/intel/perfmon/commit/5535a3e8cc14ae8ef58013cf3d8e9480018b911a
Signed-off-by: Chun-Tse Shao <ctshao@google.com>
---
.../pmu-events/arch/x86/lunarlake/cache.json | 2 +-
.../arch/x86/lunarlake/pipeline.json | 27 ++-
.../arch/x86/lunarlake/uncore-memory.json | 208 +++++++++++++++++-
tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +-
4 files changed, 228 insertions(+), 11 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/lunarlake/cache.json b/tools/perf/pmu-events/arch/x86/lunarlake/cache.json
index 92a3667b4520..5b350233a5e1 100644
--- a/tools/perf/pmu-events/arch/x86/lunarlake/cache.json
+++ b/tools/perf/pmu-events/arch/x86/lunarlake/cache.json
@@ -1,6 +1,6 @@
[
{
- "BriefDescription": "Counts the number of request that were not accepted into the L2Q because the L2Q is FULL.",
+ "BriefDescription": "Counts the number of requests that were not accepted into the L2Q because the L2Q is FULL.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x31",
"EventName": "CORE_REJECT_L2Q.ANY",
diff --git a/tools/perf/pmu-events/arch/x86/lunarlake/pipeline.json b/tools/perf/pmu-events/arch/x86/lunarlake/pipeline.json
index d66eafccebbb..a7467b2f291d 100644
--- a/tools/perf/pmu-events/arch/x86/lunarlake/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/lunarlake/pipeline.json
@@ -190,7 +190,6 @@
"EventName": "BR_INST_RETIRED.COND_TAKEN_FWD",
"PublicDescription": "Counts taken forward conditional branch instructions retired. Available PDIST counters: 0,1",
"SampleAfterValue": "400009",
- "UMask": "0x102",
"Unit": "cpu_core"
},
{
@@ -324,6 +323,15 @@
"UMask": "0xdf",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts the number of taken branch instructions retired",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xc4",
+ "EventName": "BR_INST_RETIRED.TAKEN",
+ "SampleAfterValue": "200003",
+ "UMask": "0x80",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Counts the total number of mispredicted branch instructions retired for all branch types.",
"Counter": "0,1,2,3,4,5,6,7",
@@ -446,7 +454,7 @@
"EventName": "BR_MISP_RETIRED.COND_TAKEN_BWD_COST",
"PublicDescription": "number of branch instructions retired that were mispredicted and taken backward. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. Available PDIST counters: 0,1",
"SampleAfterValue": "400009",
- "UMask": "0x8001",
+ "UMask": "0x41",
"Unit": "cpu_core"
},
{
@@ -475,7 +483,7 @@
"EventName": "BR_MISP_RETIRED.COND_TAKEN_FWD_COST",
"PublicDescription": "number of branch instructions retired that were mispredicted and taken forward. This precise event may be used to get the misprediction cost via the Retire_Latency field of PEBS. It fires on the instruction that immediately follows the mispredicted branch. Available PDIST counters: 0,1",
"SampleAfterValue": "400009",
- "UMask": "0x8002",
+ "UMask": "0x140",
"Unit": "cpu_core"
},
{
@@ -575,11 +583,11 @@
"Unit": "cpu_core"
},
{
- "BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS",
+ "BriefDescription": "This event counts the number of mispredicted ret instructions retired.",
"Counter": "0,1,2,3,4,5,6,7,8,9",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.RET",
- "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired. Available PDIST counters: 0,1",
+ "PublicDescription": "This event counts the number of mispredicted ret instructions retired. Available PDIST counters: 0,1",
"SampleAfterValue": "100007",
"UMask": "0x8",
"Unit": "cpu_core"
@@ -1373,6 +1381,15 @@
"UMask": "0x88",
"Unit": "cpu_atom"
},
+ {
+ "BriefDescription": "Counts number of virtual trap actually taken (e.g. highest priority event during retirement). It can count virtual trap from FPC port 0 or port 1 (x87/SSE) equally in a single counter.",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xc3",
+ "EventName": "MACHINE_CLEARS.FPC_VIRTUAL_TRAP",
+ "SampleAfterValue": "20003",
+ "UMask": "0x40",
+ "Unit": "cpu_atom"
+ },
{
"BriefDescription": "Counts the number of nukes due to memory renaming",
"Counter": "0,1,2,3,4,5,6,7",
diff --git a/tools/perf/pmu-events/arch/x86/lunarlake/uncore-memory.json b/tools/perf/pmu-events/arch/x86/lunarlake/uncore-memory.json
index 63c4aa2791e4..a1e79f06645a 100644
--- a/tools/perf/pmu-events/arch/x86/lunarlake/uncore-memory.json
+++ b/tools/perf/pmu-events/arch/x86/lunarlake/uncore-memory.json
@@ -1,6 +1,30 @@
[
{
- "BriefDescription": "Read CAS command sent to DRAM",
+ "BriefDescription": "ACT command for a read request sent to DRAM.",
+ "Counter": "0,1,2,3,4",
+ "EventCode": "0x24",
+ "EventName": "UNC_M_ACT_COUNT_RD",
+ "PerPkg": "1",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "ACT command sent to DRAM.",
+ "Counter": "0,1,2,3,4",
+ "EventCode": "0x26",
+ "EventName": "UNC_M_ACT_COUNT_TOTAL",
+ "PerPkg": "1",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "ACT command for a write request sent to DRAM.",
+ "Counter": "0,1,2,3,4",
+ "EventCode": "0x25",
+ "EventName": "UNC_M_ACT_COUNT_WR",
+ "PerPkg": "1",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Read CAS command sent to DRAM.",
"Counter": "0,1,2,3,4",
"EventCode": "0x22",
"EventName": "UNC_M_CAS_COUNT_RD",
@@ -8,7 +32,7 @@
"Unit": "iMC"
},
{
- "BriefDescription": "Write CAS command sent to DRAM",
+ "BriefDescription": "Write CAS command sent to DRAM.",
"Counter": "0,1,2,3,4",
"EventCode": "0x23",
"EventName": "UNC_M_CAS_COUNT_WR",
@@ -16,7 +40,94 @@
"Unit": "iMC"
},
{
- "BriefDescription": "Any Rank at Hot state",
+ "BriefDescription": "Counting the number of clocks.",
+ "Counter": "0,1,2,3,4",
+ "EventCode": "0x01",
+ "EventName": "UNC_M_CLOCKTICKS",
+ "Experimental": "1",
+ "PerPkg": "1",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "CKE in DRAM is low.",
+ "Counter": "0,1,2,3,4",
+ "EventCode": "0x29",
+ "EventName": "UNC_M_DRAM_CKE_OFF_CYCLES",
+ "Experimental": "1",
+ "PerPkg": "1",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Incoming read request page status is Page Empty.",
+ "Counter": "0,1,2,3,4",
+ "EventCode": "0x1D",
+ "EventName": "UNC_M_DRAM_PAGE_EMPTY_RD",
+ "Experimental": "1",
+ "PerPkg": "1",
+ "PublicDescription": "incoming read request page status is Page Empty",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Incoming write request page status is Page Empty.",
+ "Counter": "0,1,2,3,4",
+ "EventCode": "0x20",
+ "EventName": "UNC_M_DRAM_PAGE_EMPTY_WR",
+ "Experimental": "1",
+ "PerPkg": "1",
+ "PublicDescription": "incoming write request page status is Page Empty",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Incoming read request page status is Page Hit.",
+ "Counter": "0,1,2,3,4",
+ "EventCode": "0x1C",
+ "EventName": "UNC_M_DRAM_PAGE_HIT_RD",
+ "Experimental": "1",
+ "PerPkg": "1",
+ "PublicDescription": "incoming read request page status is Page Hit",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Incoming write request page status is Page Hit.",
+ "Counter": "0,1,2,3,4",
+ "EventCode": "0x1F",
+ "EventName": "UNC_M_DRAM_PAGE_HIT_WR",
+ "Experimental": "1",
+ "PerPkg": "1",
+ "PublicDescription": "incoming write request page status is Page Hit",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Incoming read request page status is Page Miss.",
+ "Counter": "0,1,2,3,4",
+ "EventCode": "0x1E",
+ "EventName": "UNC_M_DRAM_PAGE_MISS_RD",
+ "Experimental": "1",
+ "PerPkg": "1",
+ "PublicDescription": "incoming read request page status is Page Miss",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Incoming write request page status is Page Miss.",
+ "Counter": "0,1,2,3,4",
+ "EventCode": "0x21",
+ "EventName": "UNC_M_DRAM_PAGE_MISS_WR",
+ "Experimental": "1",
+ "PerPkg": "1",
+ "PublicDescription": "incoming write request page status is Page Miss",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "DRAM in Self-refresh (all channels).",
+ "Counter": "0,1,2,3,4",
+ "EventCode": "0x12",
+ "EventName": "UNC_M_DRAM_SELF_REFRESH",
+ "Experimental": "1",
+ "PerPkg": "1",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Any Rank at Hot state.",
"Counter": "0,1,2,3,4",
"EventCode": "0x19",
"EventName": "UNC_M_DRAM_THERMAL_HOT",
@@ -25,7 +136,7 @@
"Unit": "iMC"
},
{
- "BriefDescription": "Any Rank at Warm state",
+ "BriefDescription": "Any Rank at Warm state.",
"Counter": "0,1,2,3,4",
"EventCode": "0x1A",
"EventName": "UNC_M_DRAM_THERMAL_WARM",
@@ -33,6 +144,42 @@
"PerPkg": "1",
"Unit": "iMC"
},
+ {
+ "BriefDescription": "PRE command sent to DRAM for a read/write request.",
+ "Counter": "0,1,2,3,4",
+ "EventCode": "0x27",
+ "EventName": "UNC_M_PRE_COUNT_PAGE_MISS",
+ "PerPkg": "1",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Counts number of bytes read, in 32B chunk, per DDR channel. Counter increments by 1 after receiving 32B chunk data.",
+ "Counter": "0,1,2,3,4",
+ "EventCode": "0x3A",
+ "EventName": "UNC_M_RD_DATA",
+ "PerPkg": "1",
+ "PublicDescription": "This counter counts number of bytes read, in 32B chunk, per DDR channel. Counter increments by 1 after receiving 32B chunk data.",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Number of VC0 read in channel0 - this event can increment by more than 1 (per channel/sub-ch).",
+ "Counter": "0,1,2,3,4",
+ "EventCode": "0x13",
+ "EventName": "UNC_M_RD_OCCUPANCY_CH0",
+ "Experimental": "1",
+ "PerPkg": "1",
+ "PublicDescription": "Number of VC0 read in channel0 - this event can increment by more than 1 (per channel/sub-ch)",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Number of VC0 read in channel1 - this event can increment by more than 1 (per channel/sub-ch).",
+ "Counter": "0,1,2,3,4",
+ "EventCode": "0x14",
+ "EventName": "UNC_M_RD_OCCUPANCY_CH1",
+ "Experimental": "1",
+ "PerPkg": "1",
+ "Unit": "iMC"
+ },
{
"BriefDescription": "Total number of read and write byte transfers to/from DRAM, in 32B chunk, per DDR channel. Counter increments by 1 after sending or receiving 32B chunk data.",
"Counter": "0,1,2,3,4",
@@ -40,5 +187,58 @@
"EventName": "UNC_M_TOTAL_DATA",
"PerPkg": "1",
"Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Total number of requests entering MC, this is the sum of all RD + WR requests for all VCs.",
+ "Counter": "0,1,2,3,4",
+ "EventCode": "0x39",
+ "EventName": "UNC_M_TOTAL_REQUESTS",
+ "Experimental": "1",
+ "PerPkg": "1",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Incoming VC0 read request.",
+ "Counter": "0,1,2,3,4",
+ "EventCode": "0x02",
+ "EventName": "UNC_M_VC0_REQUESTS_RD",
+ "Experimental": "1",
+ "PerPkg": "1",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Incoming VC0 write request.",
+ "Counter": "0,1,2,3,4",
+ "EventCode": "0x03",
+ "EventName": "UNC_M_VC0_REQUESTS_WR",
+ "Experimental": "1",
+ "PerPkg": "1",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Incoming VC1 read request.",
+ "Counter": "0,1,2,3,4",
+ "EventCode": "0x04",
+ "EventName": "UNC_M_VC1_REQUESTS_RD",
+ "Experimental": "1",
+ "PerPkg": "1",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Incoming VC1 write request.",
+ "Counter": "0,1,2,3,4",
+ "EventCode": "0x05",
+ "EventName": "UNC_M_VC1_REQUESTS_WR",
+ "Experimental": "1",
+ "PerPkg": "1",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Counts number of bytes written, in 32B chunk, per DDR channel. Counter increments by 1 after sending 32B chunk data.",
+ "Counter": "0,1,2,3,4",
+ "EventCode": "0x3B",
+ "EventName": "UNC_M_WR_DATA",
+ "PerPkg": "1",
+ "Unit": "iMC"
}
]
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index b8ea72b99c52..7d19f8fa335a 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -22,7 +22,7 @@ GenuineIntel-6-3A,v24,ivybridge,core
GenuineIntel-6-3E,v24,ivytown,core
GenuineIntel-6-2D,v24,jaketown,core
GenuineIntel-6-(57|85),v16,knightslanding,core
-GenuineIntel-6-BD,v1.22,lunarlake,core
+GenuineIntel-6-BD,v1.25,lunarlake,core
GenuineIntel-6-(AA|AC|B5),v1.21,meteorlake,core
GenuineIntel-6-1[AEF],v4,nehalemep,core
GenuineIntel-6-2E,v4,nehalemex,core
--
2.54.0.1099.g489fc7bff1-goog
^ permalink raw reply related
* [PATCH v1 5/6] perf vendor events intel: Update pantherlake events from 1.05 to 1.06
From: Chun-Tse Shao @ 2026-06-09 21:50 UTC (permalink / raw)
To: peterz, mingo, acme, namhyung
Cc: alexander.shishkin, jolsa, irogers, adrian.hunter, james.clark,
afaerber, mani, dapeng1.mi, linux-perf-users, linux-kernel,
linux-arm-kernel, linux-actions, Chun-Tse Shao
In-Reply-To: <20260609215046.2391903-1-ctshao@google.com>
The updated events were published in:
https://github.com/intel/perfmon/commit/ffc03fc3b414127c5a36bbb648e500c4afeff134
Signed-off-by: Chun-Tse Shao <ctshao@google.com>
---
tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +-
.../arch/x86/pantherlake/counter.json | 5 +
.../arch/x86/pantherlake/pipeline.json | 29 ++-
.../x86/pantherlake/uncore-interconnect.json | 10 +
.../arch/x86/pantherlake/uncore-memory.json | 221 +++++++++++++++++-
5 files changed, 260 insertions(+), 7 deletions(-)
create mode 100644 tools/perf/pmu-events/arch/x86/pantherlake/uncore-interconnect.json
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index 7d19f8fa335a..6af3cee12c8a 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -26,7 +26,7 @@ GenuineIntel-6-BD,v1.25,lunarlake,core
GenuineIntel-6-(AA|AC|B5),v1.21,meteorlake,core
GenuineIntel-6-1[AEF],v4,nehalemep,core
GenuineIntel-6-2E,v4,nehalemex,core
-GenuineIntel-6-(CC|D5),v1.05,pantherlake,core
+GenuineIntel-6-(CC|D5),v1.06,pantherlake,core
GenuineIntel-6-A7,v1.04,rocketlake,core
GenuineIntel-6-2A,v19,sandybridge,core
GenuineIntel-6-8F,v1.39,sapphirerapids,core
diff --git a/tools/perf/pmu-events/arch/x86/pantherlake/counter.json b/tools/perf/pmu-events/arch/x86/pantherlake/counter.json
index 432b6946ccbc..9794b435f650 100644
--- a/tools/perf/pmu-events/arch/x86/pantherlake/counter.json
+++ b/tools/perf/pmu-events/arch/x86/pantherlake/counter.json
@@ -13,5 +13,10 @@
"Unit": "iMC",
"CountersNumFixed": "0",
"CountersNumGeneric": "5"
+ },
+ {
+ "Unit": "SANTA",
+ "CountersNumFixed": 1,
+ "CountersNumGeneric": "0"
}
]
\ No newline at end of file
diff --git a/tools/perf/pmu-events/arch/x86/pantherlake/pipeline.json b/tools/perf/pmu-events/arch/x86/pantherlake/pipeline.json
index d476bad5e2a7..5d5303c02954 100644
--- a/tools/perf/pmu-events/arch/x86/pantherlake/pipeline.json
+++ b/tools/perf/pmu-events/arch/x86/pantherlake/pipeline.json
@@ -887,11 +887,32 @@
"Unit": "cpu_core"
},
{
- "BriefDescription": "This event counts the number of mispredicted ret instructions retired. Non PEBS [This event is alias to BR_MISP_RETIRED.RET]",
+ "BriefDescription": "This event is deprecated. [This event is alias to BR_MISP_RETIRED.NEAR_RETURN]",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "Deprecated": "1",
+ "EventCode": "0xc5",
+ "EventName": "BR_MISP_RETIRED.NEAR_RET",
+ "PublicDescription": "This event is deprecated. [This event is alias to BR_MISP_RETIRED.NEAR_RETURN] Available PDIST counters: 0,1",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x8",
+ "Unit": "cpu_atom"
+ },
+ {
+ "BriefDescription": "Counts the number of mispredicted near RET branch instructions retired. [This event is alias to BR_MISP_RETIRED.NEAR_RET]",
+ "Counter": "0,1,2,3,4,5,6,7",
+ "EventCode": "0xc5",
+ "EventName": "BR_MISP_RETIRED.NEAR_RETURN",
+ "PublicDescription": "Counts the number of mispredicted near RET branch instructions retired. [This event is alias to BR_MISP_RETIRED.NEAR_RET] Available PDIST counters: 0,1",
+ "SampleAfterValue": "1000003",
+ "UMask": "0x8",
+ "Unit": "cpu_atom"
+ },
+ {
+ "BriefDescription": "This event counts the number of mispredicted ret instructions retired [This event is alias to BR_MISP_RETIRED.RET]",
"Counter": "0,1,2,3,4,5,6,7,8,9",
"EventCode": "0xc5",
"EventName": "BR_MISP_RETIRED.NEAR_RETURN",
- "PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that counts mispredicted return instructions retired. [This event is alias to BR_MISP_RETIRED.RET] Available PDIST counters: 0,1",
+ "PublicDescription": "This event counts the number of mispredicted ret instructions retired [This event is alias to BR_MISP_RETIRED.RET] Available PDIST counters: 0,1",
"SampleAfterValue": "100007",
"UMask": "0x8",
"Unit": "cpu_core"
@@ -1726,7 +1747,7 @@
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number of machines clears due to memory renaming.",
+ "BriefDescription": "Counts the number of machine clears due to memory renaming.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0xc3",
"EventName": "MACHINE_CLEARS.MRN_NUKE",
@@ -1930,7 +1951,7 @@
"Unit": "cpu_atom"
},
{
- "BriefDescription": "Counts the number issue slots not consumed due to a color request for an FCW or MXCSR control register when all 4 colors (copies) are already in use.",
+ "BriefDescription": "Counts the number of issue slots not consumed due to a color request for an FCW or MXCSR control register when all 4 colors (copies) are already in use.",
"Counter": "0,1,2,3,4,5,6,7",
"EventCode": "0x75",
"EventName": "SERIALIZATION.COLOR_STALLS",
diff --git a/tools/perf/pmu-events/arch/x86/pantherlake/uncore-interconnect.json b/tools/perf/pmu-events/arch/x86/pantherlake/uncore-interconnect.json
new file mode 100644
index 000000000000..69ef928d57f6
--- /dev/null
+++ b/tools/perf/pmu-events/arch/x86/pantherlake/uncore-interconnect.json
@@ -0,0 +1,10 @@
+[
+ {
+ "BriefDescription": "This 48-bit fixed counter counts the UCLK cycles.",
+ "Counter": "FIXED",
+ "EventCode": "0xff",
+ "EventName": "UNC_CLOCK.SOCKET",
+ "PerPkg": "1",
+ "Unit": "SANTA"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/x86/pantherlake/uncore-memory.json b/tools/perf/pmu-events/arch/x86/pantherlake/uncore-memory.json
index a881b99be5f3..8faa03e1c6d0 100644
--- a/tools/perf/pmu-events/arch/x86/pantherlake/uncore-memory.json
+++ b/tools/perf/pmu-events/arch/x86/pantherlake/uncore-memory.json
@@ -1,6 +1,30 @@
[
{
- "BriefDescription": "Read CAS command sent to DRAM",
+ "BriefDescription": "ACT command for a read request sent to DRAM.",
+ "Counter": "0,1,2,3,4",
+ "EventCode": "0x24",
+ "EventName": "UNC_M_ACT_COUNT_RD",
+ "PerPkg": "1",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "ACT command sent to DRAM.",
+ "Counter": "0,1,2,3,4",
+ "EventCode": "0x26",
+ "EventName": "UNC_M_ACT_COUNT_TOTAL",
+ "PerPkg": "1",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "ACT command for a write request sent to DRAM.",
+ "Counter": "0,1,2,3,4",
+ "EventCode": "0x25",
+ "EventName": "UNC_M_ACT_COUNT_WR",
+ "PerPkg": "1",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Read CAS command sent to DRAM.",
"Counter": "0,1,2,3,4",
"EventCode": "0x22",
"EventName": "UNC_M_CAS_COUNT_RD",
@@ -8,13 +32,153 @@
"Unit": "iMC"
},
{
- "BriefDescription": "Write CAS command sent to DRAM",
+ "BriefDescription": "Write CAS command sent to DRAM.",
"Counter": "0,1,2,3,4",
"EventCode": "0x23",
"EventName": "UNC_M_CAS_COUNT_WR",
"PerPkg": "1",
"Unit": "iMC"
},
+ {
+ "BriefDescription": "Counting the number of clocks.",
+ "Counter": "0,1,2,3,4",
+ "EventCode": "0x01",
+ "EventName": "UNC_M_CLOCKTICKS",
+ "Experimental": "1",
+ "PerPkg": "1",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "CKE in DRAM is low.",
+ "Counter": "0,1,2,3,4",
+ "EventCode": "0x29",
+ "EventName": "UNC_M_DRAM_CKE_OFF_CYCLES",
+ "Experimental": "1",
+ "PerPkg": "1",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Incoming read request page status is Page Empty.",
+ "Counter": "0,1,2,3,4",
+ "EventCode": "0x1D",
+ "EventName": "UNC_M_DRAM_PAGE_EMPTY_RD",
+ "Experimental": "1",
+ "PerPkg": "1",
+ "PublicDescription": "incoming read request page status is Page Empty",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Incoming write request page status is Page Empty.",
+ "Counter": "0,1,2,3,4",
+ "EventCode": "0x20",
+ "EventName": "UNC_M_DRAM_PAGE_EMPTY_WR",
+ "Experimental": "1",
+ "PerPkg": "1",
+ "PublicDescription": "incoming write request page status is Page Empty",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Incoming read request page status is Page Hit.",
+ "Counter": "0,1,2,3,4",
+ "EventCode": "0x1C",
+ "EventName": "UNC_M_DRAM_PAGE_HIT_RD",
+ "Experimental": "1",
+ "PerPkg": "1",
+ "PublicDescription": "incoming read request page status is Page Hit",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Incoming write request page status is Page Hit.",
+ "Counter": "0,1,2,3,4",
+ "EventCode": "0x1F",
+ "EventName": "UNC_M_DRAM_PAGE_HIT_WR",
+ "Experimental": "1",
+ "PerPkg": "1",
+ "PublicDescription": "incoming write request page status is Page Hit",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Incoming read request page status is Page Miss.",
+ "Counter": "0,1,2,3,4",
+ "EventCode": "0x1E",
+ "EventName": "UNC_M_DRAM_PAGE_MISS_RD",
+ "Experimental": "1",
+ "PerPkg": "1",
+ "PublicDescription": "incoming read request page status is Page Miss",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Incoming write request page status is Page Miss.",
+ "Counter": "0,1,2,3,4",
+ "EventCode": "0x21",
+ "EventName": "UNC_M_DRAM_PAGE_MISS_WR",
+ "Experimental": "1",
+ "PerPkg": "1",
+ "PublicDescription": "incoming write request page status is Page Miss",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "DRAM in Self-refresh (all channels).",
+ "Counter": "0,1,2,3,4",
+ "EventCode": "0x12",
+ "EventName": "UNC_M_DRAM_SELF_REFRESH",
+ "Experimental": "1",
+ "PerPkg": "1",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Any Rank at Hot state.",
+ "Counter": "0,1,2,3,4",
+ "EventCode": "0x19",
+ "EventName": "UNC_M_DRAM_THERMAL_HOT",
+ "Experimental": "1",
+ "PerPkg": "1",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Any Rank at Warm state.",
+ "Counter": "0,1,2,3,4",
+ "EventCode": "0x1A",
+ "EventName": "UNC_M_DRAM_THERMAL_WARM",
+ "Experimental": "1",
+ "PerPkg": "1",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "PRE command sent to DRAM for a read/write request.",
+ "Counter": "0,1,2,3,4",
+ "EventCode": "0x27",
+ "EventName": "UNC_M_PRE_COUNT_PAGE_MISS",
+ "PerPkg": "1",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Counts number of bytes read, in 32B chunk, per DDR channel. Counter increments by 1 after receiving 32B chunk data.",
+ "Counter": "0,1,2,3,4",
+ "EventCode": "0x3A",
+ "EventName": "UNC_M_RD_DATA",
+ "PerPkg": "1",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Number of VC0 read in channel0 - this event can increment by more than 1 (per channel/sub-ch).",
+ "Counter": "0,1,2,3,4",
+ "EventCode": "0x13",
+ "EventName": "UNC_M_RD_OCCUPANCY_CH0",
+ "Experimental": "1",
+ "PerPkg": "1",
+ "PublicDescription": "Number of VC0 read in channel0 - this event can increment by more than 1 (per channel/sub-ch)",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Number of VC0 read in channel1 - this event can increment by more than 1 (per channel/sub-ch).",
+ "Counter": "0,1,2,3,4",
+ "EventCode": "0x14",
+ "EventName": "UNC_M_RD_OCCUPANCY_CH1",
+ "Experimental": "1",
+ "PerPkg": "1",
+ "Unit": "iMC"
+ },
{
"BriefDescription": "Total number of read and write byte transfers to/from DRAM, in 32B chunk, per DDR channel. Counter increments by 1 after sending or receiving 32B chunk data.",
"Counter": "0,1,2,3,4",
@@ -22,5 +186,58 @@
"EventName": "UNC_M_TOTAL_DATA",
"PerPkg": "1",
"Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Total number of requests entering MC, this is the sum of all RD + WR requests for all VCs.",
+ "Counter": "0,1,2,3,4",
+ "EventCode": "0x39",
+ "EventName": "UNC_M_TOTAL_REQUESTS",
+ "Experimental": "1",
+ "PerPkg": "1",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Incoming VC0 read request.",
+ "Counter": "0,1,2,3,4",
+ "EventCode": "0x02",
+ "EventName": "UNC_M_VC0_REQUESTS_RD",
+ "Experimental": "1",
+ "PerPkg": "1",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Incoming VC0 write request.",
+ "Counter": "0,1,2,3,4",
+ "EventCode": "0x03",
+ "EventName": "UNC_M_VC0_REQUESTS_WR",
+ "Experimental": "1",
+ "PerPkg": "1",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Incoming VC1 read request.",
+ "Counter": "0,1,2,3,4",
+ "EventCode": "0x04",
+ "EventName": "UNC_M_VC1_REQUESTS_RD",
+ "Experimental": "1",
+ "PerPkg": "1",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Incoming VC1 write request.",
+ "Counter": "0,1,2,3,4",
+ "EventCode": "0x05",
+ "EventName": "UNC_M_VC1_REQUESTS_WR",
+ "Experimental": "1",
+ "PerPkg": "1",
+ "Unit": "iMC"
+ },
+ {
+ "BriefDescription": "Counts number of bytes written, in 32B chunk, per DDR channel. Counter increments by 1 after sending 32B chunk data.",
+ "Counter": "0,1,2,3,4",
+ "EventCode": "0x3B",
+ "EventName": "UNC_M_WR_DATA",
+ "PerPkg": "1",
+ "Unit": "iMC"
}
]
--
2.54.0.1099.g489fc7bff1-goog
^ permalink raw reply related
* [PATCH v1 6/6] perf vendor events intel: Update tigerlake events from 1.18 to 1.19
From: Chun-Tse Shao @ 2026-06-09 21:50 UTC (permalink / raw)
To: peterz, mingo, acme, namhyung
Cc: alexander.shishkin, jolsa, irogers, adrian.hunter, james.clark,
afaerber, mani, dapeng1.mi, linux-perf-users, linux-kernel,
linux-arm-kernel, linux-actions, Chun-Tse Shao
In-Reply-To: <20260609215046.2391903-1-ctshao@google.com>
The updated events were published in:
https://github.com/intel/perfmon/commit/8353ffb63efcad6b6fac1a8c05d76e2d6317ae23
Signed-off-by: Chun-Tse Shao <ctshao@google.com>
---
tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index 6af3cee12c8a..a7f870669827 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -35,7 +35,7 @@ GenuineIntel-6-(37|4A|4C|4D|5A),v15,silvermont,core
GenuineIntel-6-(4E|5E|8E|9E|A5|A6),v59,skylake,core
GenuineIntel-6-55-[01234],v1.37,skylakex,core
GenuineIntel-6-86,v1.23,snowridgex,core
-GenuineIntel-6-8[CD],v1.18,tigerlake,core
+GenuineIntel-6-8[CD],v1.19,tigerlake,core
GenuineIntel-6-2C,v5,westmereep-dp,core
GenuineIntel-6-25,v4,westmereep-sp,core
GenuineIntel-6-2F,v4,westmereex,core
--
2.54.0.1099.g489fc7bff1-goog
^ permalink raw reply related
* [PATCH v1 3/6] perf vendor events intel: Update graniterapids events from 1.18 to 1.19
From: Chun-Tse Shao @ 2026-06-09 21:50 UTC (permalink / raw)
To: peterz, mingo, acme, namhyung
Cc: alexander.shishkin, jolsa, irogers, adrian.hunter, james.clark,
afaerber, mani, dapeng1.mi, linux-perf-users, linux-kernel,
linux-arm-kernel, linux-actions, Chun-Tse Shao
In-Reply-To: <20260609215046.2391903-1-ctshao@google.com>
The updated events were published in:
https://github.com/intel/perfmon/commit/875354c88686ef50387d9601f52354a6da8f24cc
Signed-off-by: Chun-Tse Shao <ctshao@google.com>
---
.../arch/x86/graniterapids/uncore-interconnect.json | 10 ++++++++++
.../arch/x86/graniterapids/uncore-memory.json | 2 +-
tools/perf/pmu-events/arch/x86/mapfile.csv | 2 +-
3 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/tools/perf/pmu-events/arch/x86/graniterapids/uncore-interconnect.json b/tools/perf/pmu-events/arch/x86/graniterapids/uncore-interconnect.json
index 5eb1145f204f..9f0c4c7198b0 100644
--- a/tools/perf/pmu-events/arch/x86/graniterapids/uncore-interconnect.json
+++ b/tools/perf/pmu-events/arch/x86/graniterapids/uncore-interconnect.json
@@ -808,6 +808,16 @@
"PerPkg": "1",
"Unit": "IRP"
},
+ {
+ "BriefDescription": "Counts Timeouts - Set 0 : Cache Inserts of Write Transactions as Secondary",
+ "Counter": "0,1,2,3",
+ "EventCode": "0x1E",
+ "EventName": "UNC_I_MISC0.2ND_WR_INSERT",
+ "Experimental": "1",
+ "PerPkg": "1",
+ "UMask": "0x8",
+ "Unit": "IRP"
+ },
{
"BriefDescription": "Counts Timeouts - Set 0 : Fastpath Rejects",
"Counter": "0,1,2,3",
diff --git a/tools/perf/pmu-events/arch/x86/graniterapids/uncore-memory.json b/tools/perf/pmu-events/arch/x86/graniterapids/uncore-memory.json
index f559e27e2815..9cd2905726fd 100644
--- a/tools/perf/pmu-events/arch/x86/graniterapids/uncore-memory.json
+++ b/tools/perf/pmu-events/arch/x86/graniterapids/uncore-memory.json
@@ -539,7 +539,7 @@
"Unit": "IMC"
},
{
- "BriefDescription": "DRAM Precharge commands. : Precharge due to (?) : Counts the number of DRAM Precharge commands sent on this channel.",
+ "BriefDescription": "DRAM Precharge commands. : Precharge due to page table : Counts the number of DRAM Precharge commands sent on this channel.",
"Counter": "0,1,2,3",
"EventCode": "0x03",
"EventName": "UNC_M_PRE_COUNT.PGT",
diff --git a/tools/perf/pmu-events/arch/x86/mapfile.csv b/tools/perf/pmu-events/arch/x86/mapfile.csv
index 0f39073805ba..b8ea72b99c52 100644
--- a/tools/perf/pmu-events/arch/x86/mapfile.csv
+++ b/tools/perf/pmu-events/arch/x86/mapfile.csv
@@ -13,7 +13,7 @@ GenuineIntel-6-CF,v1.24,emeraldrapids,core
GenuineIntel-6-5[CF],v13,goldmont,core
GenuineIntel-6-7A,v1.01,goldmontplus,core
GenuineIntel-6-B6,v1.12,grandridge,core
-GenuineIntel-6-A[DE],v1.18,graniterapids,core
+GenuineIntel-6-A[DE],v1.19,graniterapids,core
GenuineIntel-6-(3C|45|46),v36,haswell,core
GenuineIntel-6-3F,v29,haswellx,core
GenuineIntel-6-7[DE],v1.24,icelake,core
--
2.54.0.1099.g489fc7bff1-goog
^ permalink raw reply related
* [PATCH 2/2] arm64: tlbflush: Reset active_cpu on ASID rollover
From: sk @ 2026-06-09 21:34 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux-kernel, Catalin Marinas, Will Deacon, Ryan Roberts,
Andrew Morton, David Hildenbrand, Anshuman Khandual,
Mike Rapoport, Dev Jain, Kevin Brodsky, Marc Zyngier,
Oliver Upton, cl, Sayali Kulkarni
In-Reply-To: <20260609213615.2788698-1-sk@gentwo.org>
From: Sayali Kulkarni <sskulkarni@amperecomputing.com>
Once active_cpu flips to ACTIVE_CPU_MULTIPLE, it never resets, even if the process settles back to one CPU. Reset it to ACTIVE_CPU_NONE when a new ASID is assigned after rollover, since flush_context() already issued a global TLB flush at that point meaning no stale TLB entries exist on any CPU.
This gives processes a fresh chance at the local-only flush fast path after each ASID generation rollover.
Signed-off-by: Sayali Kulkarni <sskulkarni@amperecomputing.com>
---
arch/arm64/mm/context.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c
index f34ed78393e0..0c92cc8fb4cd 100644
--- a/arch/arm64/mm/context.c
+++ b/arch/arm64/mm/context.c
@@ -250,6 +250,7 @@ void check_and_switch_context(struct mm_struct *mm)
if (!asid_gen_match(asid)) {
asid = new_context(mm);
atomic64_set(&mm->context.id, asid);
+ WRITE_ONCE(mm->context.active_cpu, ACTIVE_CPU_NONE);
}
if (cpumask_test_and_clear_cpu(cpu, &tlb_flush_pending))
@@ -321,6 +322,7 @@ unsigned long arm64_mm_context_get(struct mm_struct *mm)
*/
asid = new_context(mm);
atomic64_set(&mm->context.id, asid);
+ WRITE_ONCE(mm->context.active_cpu, ACTIVE_CPU_NONE);
}
nr_pinned_asids++;
--
2.47.3
^ permalink raw reply related
* Re: (subset) [PATCH v2 00/10] gpiolib: fence off legacy interfaces
From: Kevin Hilman @ 2026-06-09 22:25 UTC (permalink / raw)
To: linux-gpio, Arnd Bergmann
Cc: linux-kernel, Arnd Bergmann, Christian Lamparter, Johannes Berg,
Aaro Koskinen, Andreas Kemnade, Roger Quadros, Tony Lindgren,
Thomas Bogendoerfer, John Paul Adrian Glaubitz, Thomas Gleixner,
Ingo Molnar, Borislav Petkov, Dave Hansen, x86, H. Peter Anvin,
Linus Walleij, Bartosz Golaszewski, Dmitry Torokhov, Lee Jones,
Pavel Machek, Matti Vaittinen, Florian Fainelli, Jonas Gorski,
Andrew Lunn, Vladimir Oltean, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, linux-wireless, linux-omap,
linux-arm-kernel, linux-mips, linux-sh, linux-input, linux-leds,
netdev
In-Reply-To: <20260520183815.2510387-1-arnd@kernel.org>
On Wed, 20 May 2026 20:38:05 +0200, Arnd Bergmann wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> This is an update of all the patches that are still required before
> we can actually turn off CONFIG_GPIOLIB_LEGACY for most platforms
> in the final patch of this series.
>
> I originally posted this as a series in
> https://lore.kernel.org/all/20250808151822.536879-1-arnd@kernel.org/
>
> [...]
Applied, thanks!
[09/10] ARM: dts: omap2: add stlc4560 spi-wireless node
commit: c5a0ac76b364bbd1d4fb7e440edabcd2a369343c
Best regards,
--
Kevin Hilman (TI) <khilman@baylibre.com>
^ permalink raw reply
* Re: [PATCH v4] arm: multi_v7_defconfig: Enable BRIDGE and DP83848_PHY for TI AM57xx, AM437x and AM335x
From: Kevin Hilman @ 2026-06-09 22:26 UTC (permalink / raw)
To: nm, vigneshr, linux, ardb, ebiggers, krzysztof.kozlowski, arnd,
geert+renesas, tiwai, kory.maincent, andreas, dmitry.baryshkov,
prabhakar.mahadev-lad.rj, twoerner, Parvathi Pudi
Cc: linux-arm-kernel, linux-kernel, pratheesh, j-rameshbabu, praneeth,
srk, rogerq, danishanwar, m-malladi, krishna, mohan, pmohan,
basharath
In-Reply-To: <20260428085003.3023464-1-parvathi@couthit.com>
On Tue, 28 Apr 2026 14:17:31 +0530, Parvathi Pudi wrote:
> This patch enables BRIDGE and DP83848_PHY as kernel modules for AM57xx,
> AM437x and AM335x SoCs. BRIDGE is to support STP/RSTP Switch mode using
> PRU-ICSS which got recently merged and DP83848 PHY driver to support
> TI TLK10X PHY.
Applied, thanks!
[1/1] arm: multi_v7_defconfig: Enable BRIDGE and DP83848_PHY for TI AM57xx, AM437x and AM335x
commit: 7ec7f27d5d078e5786274a669feda967efef674e
Best regards,
--
Kevin Hilman (TI) <khilman@baylibre.com>
^ permalink raw reply
* Re: [PATCH v1] ARM: OMAP2+: Fix OF node reference leaks in omap_hwmod
From: Kevin Hilman @ 2026-06-09 22:25 UTC (permalink / raw)
To: Paul Walmsley, Aaro Koskinen, Andreas Kemnade, Roger Quadros,
Tony Lindgren, Russell King, Yuho Choi
Cc: linux-omap, linux-arm-kernel, linux-kernel
In-Reply-To: <20260504164711.2854116-1-dbgh9129@gmail.com>
On Mon, 04 May 2026 12:47:11 -0400, Yuho Choi wrote:
> The OF helpers that return device nodes acquire references that must be
> released by the caller.
>
> _init() leaks the "ocp" bus node returned by of_find_node_by_name() on
> all paths after lookup, and also leaks the child returned by
> of_get_next_child() when parsing module flags. Route the post-lookup
> returns through a common cleanup path and release the child after use.
>
> [...]
Applied, thanks!
[1/1] ARM: OMAP2+: Fix OF node reference leaks in omap_hwmod
commit: f7ab9e7070b8dd77d6f8f7bd1162b7190af8694d
Best regards,
--
Kevin Hilman (TI) <khilman@baylibre.com>
^ permalink raw reply
* Re: [PATCH v3] ARM: OMAP2+: Add CFI type for omap4_finish_suspend
From: Kevin Hilman @ 2026-06-09 22:25 UTC (permalink / raw)
To: Aaro Koskinen, Andreas Kemnade, Roger Quadros, Tony Lindgren,
Russell King, Mithil Bavishi
Cc: Sami Tolvanen, Kees Cook, Nathan Chancellor, linux-arm-kernel,
linux-omap, llvm, linux-kernel
In-Reply-To: <20260604054048.18980-1-bavishimithil@gmail.com>
On Wed, 03 Jun 2026 22:40:48 -0700, Mithil Bavishi wrote:
> With CONFIG_CFI enabled, OMAP4 can trap in omap4_enter_lowpower()
> because omap_pm_ops.finish_suspend points directly to the assembly
> routine omap4_finish_suspend, which lacks the expected KCFI type
> metadata.
>
> Annotate omap4_finish_suspend with SYM_TYPED_FUNC_START so the assembly
> routine carries the KCFI type metadata.
>
> [...]
Applied, thanks!
[1/1] ARM: OMAP2+: Add CFI type for omap4_finish_suspend
commit: d58849ac304472fdc75f44c468743d75ca75c2ce
Best regards,
--
Kevin Hilman (TI) <khilman@baylibre.com>
^ permalink raw reply
* [PATCHv2 0/4] serial: mxs-auart: devm conversion, clock rework, and IRQ ordering fixes
From: Rosen Penev @ 2026-06-09 22:37 UTC (permalink / raw)
To: linux-serial
Cc: Greg Kroah-Hartman, Jiri Slaby, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam,
open list:TTY LAYER AND SERIAL DRIVERS,
open list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
This series cleans up the mxs-auart driver by converting to devm-managed
resources, fixing clock prepare/enable ordering, and addressing IRQ
registration races.
Patch 1 fixes compilation on 64-bit build with W=1
Patch 2 reworks the clock handling to use devm_clk_get_enabled and
reorders clk_prepare_enable after clk_set_rate to avoid
CLK_SET_RATE_GATE failures.
Patch 3 converts iomem mapping and GPIO IRQ requests to devm,
removing the manual cleanup paths.
Patch 4 moves the main UART IRQ registration after uart_add_one_port
so the port state is initialized before the handler can run, and
manages the module clock for console vs non-console ports correctly.
v2: split off of_device_get_match_data change.
Rosen Penev (4):
serial: mxs-auart: fix cast type for of_device_get_match_data
serial: mxs-auart: rework clock handling in mxs_get_clks and probe
serial: mxs-auart: use devm resources for iomem and GPIO IRQs
serial: mxs-auart: fix IRQ registration ordering and manage console
clock
drivers/tty/serial/mxs-auart.c | 141 +++++++++++++++------------------
1 file changed, 63 insertions(+), 78 deletions(-)
--
2.54.0
^ permalink raw reply
* [PATCHv2 2/4] serial: mxs-auart: rework clock handling in mxs_get_clks and probe
From: Rosen Penev @ 2026-06-09 22:37 UTC (permalink / raw)
To: linux-serial
Cc: Greg Kroah-Hartman, Jiri Slaby, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam,
open list:TTY LAYER AND SERIAL DRIVERS,
open list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
In-Reply-To: <20260609223717.41670-1-rosenp@gmail.com>
Use devm_clk_get_enabled for the AHB clock so its enable/disable
lifetime is managed by the driver model. Move the mod clock
(clk) prepare_enable out of mxs_get_clks and into probe so that
clk_set_rate is called while the clock is still disabled, avoiding
CLK_SET_RATE_GATE failures. Clean up the error labels accordingly.
Assisted-by: opencode:big-pickle
Signed-off-by: Rosen Penev <rosenp@gmail.com>
---
drivers/tty/serial/mxs-auart.c | 47 ++++++++++++----------------------
1 file changed, 17 insertions(+), 30 deletions(-)
diff --git a/drivers/tty/serial/mxs-auart.c b/drivers/tty/serial/mxs-auart.c
index de97c0f74e7d..aa59a48bfad7 100644
--- a/drivers/tty/serial/mxs-auart.c
+++ b/drivers/tty/serial/mxs-auart.c
@@ -1470,34 +1470,22 @@ static int mxs_get_clks(struct mxs_auart_port *s,
return PTR_ERR(s->clk);
}
- s->clk_ahb = devm_clk_get(s->dev, "ahb");
+ s->clk_ahb = devm_clk_get_enabled(s->dev, "ahb");
if (IS_ERR(s->clk_ahb)) {
dev_err(s->dev, "Failed to get \"ahb\" clk\n");
return PTR_ERR(s->clk_ahb);
}
- err = clk_prepare_enable(s->clk_ahb);
- if (err) {
- dev_err(s->dev, "Failed to enable ahb_clk!\n");
- return err;
- }
-
+ /*
+ * Set mod clock rate while it is still disabled so
+ * CLK_SET_RATE_GATE does not cause clk_set_rate to fail.
+ * The mod clock will be enabled in mxs_auart_startup()
+ * and in probe after mxs_get_clks returns.
+ */
err = clk_set_rate(s->clk, clk_get_rate(s->clk_ahb));
- if (err) {
+ if (err)
dev_err(s->dev, "Failed to set rate!\n");
- goto disable_clk_ahb;
- }
- err = clk_prepare_enable(s->clk);
- if (err) {
- dev_err(s->dev, "Failed to enable clk!\n");
- goto disable_clk_ahb;
- }
-
- return 0;
-
-disable_clk_ahb:
- clk_disable_unprepare(s->clk_ahb);
return err;
}
@@ -1604,17 +1592,21 @@ static int mxs_auart_probe(struct platform_device *pdev)
if (ret)
return ret;
+ ret = clk_prepare_enable(s->clk);
+ if (ret)
+ return ret;
+
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!r) {
ret = -ENXIO;
- goto out_disable_clks;
+ goto out_disable_clk;
}
s->port.mapbase = r->start;
s->port.membase = ioremap(r->start, resource_size(r));
if (!s->port.membase) {
ret = -ENOMEM;
- goto out_disable_clks;
+ goto out_disable_clk;
}
s->port.ops = &mxs_auart_ops;
s->port.iotype = UPIO_MEM;
@@ -1681,11 +1673,8 @@ static int mxs_auart_probe(struct platform_device *pdev)
out_iounmap:
iounmap(s->port.membase);
-out_disable_clks:
- if (is_asm9260_auart(s)) {
- clk_disable_unprepare(s->clk);
- clk_disable_unprepare(s->clk_ahb);
- }
+out_disable_clk:
+ clk_disable_unprepare(s->clk);
return ret;
}
@@ -1697,10 +1686,8 @@ static void mxs_auart_remove(struct platform_device *pdev)
auart_port[pdev->id] = NULL;
mxs_auart_free_gpio_irq(s);
iounmap(s->port.membase);
- if (is_asm9260_auart(s)) {
+ if (is_asm9260_auart(s))
clk_disable_unprepare(s->clk);
- clk_disable_unprepare(s->clk_ahb);
- }
}
static struct platform_driver mxs_auart_driver = {
--
2.54.0
^ permalink raw reply related
* [PATCHv2 1/4] serial: mxs-auart: fix cast type for of_device_get_match_data
From: Rosen Penev @ 2026-06-09 22:37 UTC (permalink / raw)
To: linux-serial
Cc: Greg Kroah-Hartman, Jiri Slaby, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam,
open list:TTY LAYER AND SERIAL DRIVERS,
open list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
In-Reply-To: <20260609223717.41670-1-rosenp@gmail.com>
of_device_get_match_data returns const void*. Cast to unsigned long to
avoid implicit integer truncation warnings. All the data parameters are
correct anyway.
Assisted-by: opencode:big-pickle
Signed-off-by: Rosen Penev <rosenp@gmail.com>
---
drivers/tty/serial/mxs-auart.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/tty/serial/mxs-auart.c b/drivers/tty/serial/mxs-auart.c
index 697318dbb146..de97c0f74e7d 100644
--- a/drivers/tty/serial/mxs-auart.c
+++ b/drivers/tty/serial/mxs-auart.c
@@ -1598,7 +1598,7 @@ static int mxs_auart_probe(struct platform_device *pdev)
return -EINVAL;
}
- s->devtype = (enum mxs_auart_type)of_device_get_match_data(&pdev->dev);
+ s->devtype = (unsigned long)of_device_get_match_data(&pdev->dev);
ret = mxs_get_clks(s, pdev);
if (ret)
--
2.54.0
^ permalink raw reply related
* [PATCHv2 4/4] serial: mxs-auart: fix IRQ registration ordering and manage console clock
From: Rosen Penev @ 2026-06-09 22:37 UTC (permalink / raw)
To: linux-serial
Cc: Greg Kroah-Hartman, Jiri Slaby, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam,
open list:TTY LAYER AND SERIAL DRIVERS,
open list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
In-Reply-To: <20260609223717.41670-1-rosenp@gmail.com>
Move the main UART IRQ registration after uart_add_one_port so that
s->port.state and s->port.lock are initialized before the interrupt
handler can run. Mask all UART interrupts before adding the port to
prevent spurious IRQs left by the bootloader.
After probe succeeds, disable the module clock for non-console ports
since startup will re-enable it on port open. For console ports, keep
the clock prepared so auart_console_write() can safely call
clk_enable() from atomic context.
Guard the IRQ handler and get_mctrl with clk_enable/clk_disable since
GPIO IRQs and serial-core status queries can fire while the clock is
disabled for non-console ports.
In remove, disable the clock for console ports to balance the enable
done in probe, preventing a clock leak on unbind.
Assisted-by: opencode:big-pickle
---
drivers/tty/serial/mxs-auart.c | 49 +++++++++++++++++++++++++++-------
1 file changed, 39 insertions(+), 10 deletions(-)
diff --git a/drivers/tty/serial/mxs-auart.c b/drivers/tty/serial/mxs-auart.c
index 4499e3206e85..e2b656638ab3 100644
--- a/drivers/tty/serial/mxs-auart.c
+++ b/drivers/tty/serial/mxs-auart.c
@@ -738,9 +738,13 @@ static u32 mxs_auart_modem_status(struct mxs_auart_port *s, u32 mctrl)
static u32 mxs_auart_get_mctrl(struct uart_port *u)
{
struct mxs_auart_port *s = to_auart_port(u);
- u32 stat = mxs_read(s, REG_STAT);
+ u32 stat;
u32 mctrl = 0;
+ clk_enable(s->clk);
+ stat = mxs_read(s, REG_STAT);
+ clk_disable(s->clk);
+
if (stat & AUART_STAT_CTS)
mctrl |= TIOCM_CTS;
@@ -1079,6 +1083,7 @@ static irqreturn_t mxs_auart_irq_handle(int irq, void *context)
struct mxs_auart_port *s = context;
u32 mctrl_temp = s->mctrl_prev;
+ clk_enable(s->clk);
uart_port_lock(&s->port);
stat = mxs_read(s, REG_STAT);
@@ -1118,6 +1123,7 @@ static irqreturn_t mxs_auart_irq_handle(int irq, void *context)
}
uart_port_unlock(&s->port);
+ clk_disable(s->clk);
return IRQ_HANDLED;
}
@@ -1603,10 +1609,6 @@ static int mxs_auart_probe(struct platform_device *pdev)
}
s->port.irq = irq;
- ret = devm_request_irq(&pdev->dev, irq, mxs_auart_irq_handle, 0,
- dev_name(&pdev->dev), s);
- if (ret)
- goto out_disable_clk;
platform_set_drvdata(pdev, s);
@@ -1627,9 +1629,28 @@ static int mxs_auart_probe(struct platform_device *pdev)
mxs_auart_reset_deassert(s);
+ /* Mask all UART interrupts to prevent spurious IRQs from bootloader */
+ mxs_write(0, s, REG_INTR);
+
ret = uart_add_one_port(&auart_driver, &s->port);
- if (ret)
- goto out_free_qpio_irq;
+ if (ret) {
+ auart_port[s->port.line] = NULL;
+ goto out_disable_clk;
+ }
+
+ /*
+ * Request the main IRQ after uart_add_one_port so that
+ * s->port.state and s->port.lock are initialized before
+ * the handler can run in response to a bootloader-left
+ * interrupt.
+ */
+ ret = devm_request_irq(&pdev->dev, irq, mxs_auart_irq_handle, 0,
+ dev_name(&pdev->dev), s);
+ if (ret) {
+ uart_remove_one_port(&auart_driver, &s->port);
+ auart_port[s->port.line] = NULL;
+ goto out_disable_clk;
+ }
/* ASM9260 don't have version reg */
if (is_asm9260_auart(s)) {
@@ -1641,10 +1662,16 @@ static int mxs_auart_probe(struct platform_device *pdev)
(version >> 16) & 0xff, version & 0xffff);
}
- return 0;
+ /*
+ * Disable clock -- startup will re-enable when the port is opened.
+ * For the console port the clock must stay prepared so that
+ * auart_console_write() can safely call clk_enable() from
+ * atomic context.
+ */
+ if (!uart_console(&s->port))
+ clk_disable_unprepare(s->clk);
-out_free_qpio_irq:
- auart_port[s->port.line] = NULL;
+ return 0;
out_disable_clk:
clk_disable_unprepare(s->clk);
@@ -1657,6 +1684,8 @@ static void mxs_auart_remove(struct platform_device *pdev)
uart_remove_one_port(&auart_driver, &s->port);
auart_port[s->port.line] = NULL;
+ if (uart_console(&s->port))
+ clk_disable_unprepare(s->clk);
}
static struct platform_driver mxs_auart_driver = {
--
2.54.0
^ permalink raw reply related
* [PATCHv2 3/4] serial: mxs-auart: use devm resources for iomem and GPIO IRQs
From: Rosen Penev @ 2026-06-09 22:37 UTC (permalink / raw)
To: linux-serial
Cc: Greg Kroah-Hartman, Jiri Slaby, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam,
open list:TTY LAYER AND SERIAL DRIVERS,
open list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
In-Reply-To: <20260609223717.41670-1-rosenp@gmail.com>
Replace platform_get_resource + ioremap with
devm_platform_get_and_ioremap_resource and convert GPIO IRQ
request_irq/free_irq to devm_request_irq. This eliminates the
mxs_auart_free_gpio_irq function and its call sites, and the
out_iounmap error label. Simplify the remove function accordingly.
Assisted-by: opencode:big-pickle
Signed-off-by: Rosen Penev <rosenp@gmail.com>
---
drivers/tty/serial/mxs-auart.c | 53 +++++++---------------------------
1 file changed, 11 insertions(+), 42 deletions(-)
diff --git a/drivers/tty/serial/mxs-auart.c b/drivers/tty/serial/mxs-auart.c
index aa59a48bfad7..4499e3206e85 100644
--- a/drivers/tty/serial/mxs-auart.c
+++ b/drivers/tty/serial/mxs-auart.c
@@ -1517,15 +1517,6 @@ static int mxs_auart_init_gpios(struct mxs_auart_port *s, struct device *dev)
return 0;
}
-static void mxs_auart_free_gpio_irq(struct mxs_auart_port *s)
-{
- enum mctrl_gpio_idx i;
-
- for (i = 0; i < UART_GPIO_MAX; i++)
- if (s->gpio_irq[i] >= 0)
- free_irq(s->gpio_irq[i], s);
-}
-
static int mxs_auart_request_gpio_irq(struct mxs_auart_port *s)
{
int *irq = s->gpio_irq;
@@ -1537,21 +1528,13 @@ static int mxs_auart_request_gpio_irq(struct mxs_auart_port *s)
continue;
irq_set_status_flags(irq[i], IRQ_NOAUTOEN);
- err = request_irq(irq[i], mxs_auart_irq_handle,
- IRQ_TYPE_EDGE_BOTH, dev_name(s->dev), s);
+ err = devm_request_irq(s->dev, irq[i], mxs_auart_irq_handle,
+ IRQ_TYPE_EDGE_BOTH, dev_name(s->dev), s);
if (err)
dev_err(s->dev, "%s - Can't get %d irq\n",
__func__, irq[i]);
}
- /*
- * If something went wrong, rollback.
- * Be careful: i may be unsigned.
- */
- while (err && (i-- > 0))
- if (irq[i] >= 0)
- free_irq(irq[i], s);
-
return err;
}
@@ -1596,18 +1579,12 @@ static int mxs_auart_probe(struct platform_device *pdev)
if (ret)
return ret;
- r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!r) {
- ret = -ENXIO;
+ s->port.membase = devm_platform_get_and_ioremap_resource(pdev, 0, &r);
+ if (IS_ERR(s->port.membase)) {
+ ret = PTR_ERR(s->port.membase);
goto out_disable_clk;
}
-
s->port.mapbase = r->start;
- s->port.membase = ioremap(r->start, resource_size(r));
- if (!s->port.membase) {
- ret = -ENOMEM;
- goto out_disable_clk;
- }
s->port.ops = &mxs_auart_ops;
s->port.iotype = UPIO_MEM;
s->port.fifosize = MXS_AUART_FIFO_SIZE;
@@ -1622,21 +1599,21 @@ static int mxs_auart_probe(struct platform_device *pdev)
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
ret = irq;
- goto out_iounmap;
+ goto out_disable_clk;
}
s->port.irq = irq;
ret = devm_request_irq(&pdev->dev, irq, mxs_auart_irq_handle, 0,
dev_name(&pdev->dev), s);
if (ret)
- goto out_iounmap;
+ goto out_disable_clk;
platform_set_drvdata(pdev, s);
ret = mxs_auart_init_gpios(s, &pdev->dev);
if (ret) {
dev_err(&pdev->dev, "Failed to initialize GPIOs.\n");
- goto out_iounmap;
+ goto out_disable_clk;
}
/*
@@ -1644,7 +1621,7 @@ static int mxs_auart_probe(struct platform_device *pdev)
*/
ret = mxs_auart_request_gpio_irq(s);
if (ret)
- goto out_iounmap;
+ goto out_disable_clk;
auart_port[s->port.line] = s;
@@ -1667,11 +1644,7 @@ static int mxs_auart_probe(struct platform_device *pdev)
return 0;
out_free_qpio_irq:
- mxs_auart_free_gpio_irq(s);
- auart_port[pdev->id] = NULL;
-
-out_iounmap:
- iounmap(s->port.membase);
+ auart_port[s->port.line] = NULL;
out_disable_clk:
clk_disable_unprepare(s->clk);
@@ -1683,11 +1656,7 @@ static void mxs_auart_remove(struct platform_device *pdev)
struct mxs_auart_port *s = platform_get_drvdata(pdev);
uart_remove_one_port(&auart_driver, &s->port);
- auart_port[pdev->id] = NULL;
- mxs_auart_free_gpio_irq(s);
- iounmap(s->port.membase);
- if (is_asm9260_auart(s))
- clk_disable_unprepare(s->clk);
+ auart_port[s->port.line] = NULL;
}
static struct platform_driver mxs_auart_driver = {
--
2.54.0
^ permalink raw reply related
* [PATCH 1/2] arm64: tlbflush: Don't broadcast if mm was only active on local cpu
From: sk @ 2026-06-09 21:34 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux-kernel, Catalin Marinas, Will Deacon, Ryan Roberts,
Andrew Morton, David Hildenbrand, Anshuman Khandual,
Mike Rapoport, Dev Jain, Kevin Brodsky, Marc Zyngier,
Oliver Upton, cl, Huang Ying, Linu Cherian
In-Reply-To: <20260609213615.2788698-1-sk@gentwo.org>
From: Ryan Roberts <ryan.roberts@arm.com>
There are 3 variants of tlb flush that invalidate user mappings:
flush_tlb_mm(), flush_tlb_page() and __flush_tlb_range(). All of these
would previously unconditionally broadcast their tlbis to all cpus in
the inner shareable domain.
But this is a waste of effort if we can prove that the mm for which we
are flushing the mappings has only ever been active on the local cpu. In
that case, it is safe to avoid the broadcast and simply invalidate the
current cpu.
So let's track in mm_context_t::active_cpu either the mm has never been
active on any cpu, has been active on more than 1 cpu, or has been
active on precisely 1 cpu - and in that case, which one. We update this
when switching context, being careful to ensure that it gets updated
*before* installing the mm's pgtables. On the reader side, we ensure we
read *after* the previous write(s) to the pgtable(s) that necessitated
the tlb flush have completed. This guarrantees that if a cpu that is
doing a tlb flush sees it's own id in active_cpu, then the old pgtable
entry cannot have been seen by any other cpu and we can flush only the
local cpu.
Signed-off-by: Ryan Roberts <ryan.roberts@arm.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Huang Ying <ying.huang@linux.alibaba.com>
[linu.cherian@arm.com: Adapted for v7.1 flush tlb API changes]
Signed-off-by: Linu Cherian <linu.cherian@arm.com>
---
arch/arm64/include/asm/mmu.h | 12 +++
arch/arm64/include/asm/mmu_context.h | 2 +
arch/arm64/include/asm/tlbflush.h | 127 +++++++++++++++++++++------
arch/arm64/mm/context.c | 30 ++++++-
4 files changed, 141 insertions(+), 30 deletions(-)
diff --git a/arch/arm64/include/asm/mmu.h b/arch/arm64/include/asm/mmu.h
index 5e1211c540ab..0002101c1f21 100644
--- a/arch/arm64/include/asm/mmu.h
+++ b/arch/arm64/include/asm/mmu.h
@@ -16,6 +16,17 @@
#include <linux/refcount.h>
#include <asm/cpufeature.h>
+/*
+ * Sentinal values for mm_context_t::active_cpu. ACTIVE_CPU_NONE indicates the
+ * mm has never been active on any CPU. ACTIVE_CPU_MULTIPLE indicates the mm
+ * has been active on multiple CPUs. Any other value is the ID of the single
+ * CPU that the mm has been active on.
+ */
+enum active_cpu {
+ ACTIVE_CPU_NONE = UINT_MAX,
+ ACTIVE_CPU_MULTIPLE = UINT_MAX - 1,
+};
+
typedef struct {
atomic64_t id;
#ifdef CONFIG_COMPAT
@@ -25,6 +36,7 @@ typedef struct {
void *vdso;
unsigned long flags;
u8 pkey_allocation_map;
+ unsigned int active_cpu;
} mm_context_t;
/*
diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/mmu_context.h
index 803b68758152..101cae0c7262 100644
--- a/arch/arm64/include/asm/mmu_context.h
+++ b/arch/arm64/include/asm/mmu_context.h
@@ -172,6 +172,8 @@ init_new_context(struct task_struct *tsk, struct mm_struct *mm)
/* pkey 0 is the default, so always reserve it. */
mm->context.pkey_allocation_map = BIT(0);
+ WRITE_ONCE(mm->context.active_cpu, ACTIVE_CPU_NONE);
+
return 0;
}
diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
index c0bf5b398041..1f75bce4fa0d 100644
--- a/arch/arm64/include/asm/tlbflush.h
+++ b/arch/arm64/include/asm/tlbflush.h
@@ -164,6 +164,12 @@ static inline void sme_dvmsync_batch(struct arch_tlbflush_unmap_batch *batch)
typedef void (*tlbi_op)(u64 arg);
+static __always_inline void vae1(u64 arg)
+{
+ __tlbi(vae1, arg);
+ __tlbi_user(vae1, arg);
+}
+
static __always_inline void vae1is(u64 arg)
{
__tlbi(vae1is, arg);
@@ -308,6 +314,74 @@ static inline void __tlbi_sync_s1ish_hyp(void)
__repeat_tlbi_sync(vale2is, 0);
}
+typedef unsigned __bitwise tlbf_t;
+
+/* No special behaviour. */
+#define TLBF_NONE ((__force tlbf_t)0)
+
+/* Invalidate tlb entries only, leaving the page table walk cache intact. */
+#define TLBF_NOWALKCACHE ((__force tlbf_t)BIT(0))
+
+/* Skip the trailing dsb after issuing tlbi. */
+#define TLBF_NOSYNC ((__force tlbf_t)BIT(1))
+
+/* Suppress tlb notifier callbacks for this flush operation. */
+#define TLBF_NONOTIFY ((__force tlbf_t)BIT(2))
+
+/* Perform the tlbi locally without broadcasting to other CPUs. */
+#define TLBF_NOBROADCAST ((__force tlbf_t)BIT(3))
+
+/*
+ * Determines whether the user tlbi invalidation can be performed only on the
+ * local CPU or whether it needs to be broadcast. (Returns true for local).
+ * Additionally issues appropriate barrier to ensure prior pgtable updates are
+ * visible to the table walker. Must be paired with flush_tlb_user_post().
+ */
+static inline bool flush_tlb_user_pre(struct mm_struct *mm, tlbf_t flags)
+{
+ unsigned int self, active;
+ bool local;
+
+ migrate_disable();
+
+ if (flags & TLBF_NOBROADCAST) {
+ dsb(nshst);
+ return true;
+ }
+
+ self = smp_processor_id();
+
+ /*
+ * The load of mm->context.active_cpu must not be reordered before the
+ * store to the pgtable that necessitated this flush. This ensures that
+ * if the value read is our cpu id, then no other cpu can have seen the
+ * old pgtable value and therefore does not need this old value to be
+ * flushed from its tlb. But we don't want to upgrade the dsb(ishst),
+ * needed to make the pgtable updates visible to the walker, to a
+ * dsb(ish) by default. So speculatively load without a barrier and if
+ * it indicates our cpu id, then upgrade the barrier and re-load.
+ */
+ active = READ_ONCE(mm->context.active_cpu);
+ if (active == self) {
+ dsb(ish);
+ active = READ_ONCE(mm->context.active_cpu);
+ } else {
+ dsb(ishst);
+ }
+
+ local = active == self;
+ if (!local)
+ migrate_enable();
+
+ return local;
+}
+
+static inline void flush_tlb_user_post(bool local)
+{
+ if (local)
+ migrate_enable();
+}
+
/*
* TLB Invalidation
* ================
@@ -408,12 +482,20 @@ static inline void flush_tlb_all(void)
static inline void flush_tlb_mm(struct mm_struct *mm)
{
unsigned long asid;
+ bool local;
- dsb(ishst);
+ local = flush_tlb_user_pre(mm, TLBF_NONE);
asid = __TLBI_VADDR(0, ASID(mm));
- __tlbi(aside1is, asid);
- __tlbi_user(aside1is, asid);
- __tlbi_sync_s1ish(mm);
+ if (local) {
+ __tlbi(aside1, asid);
+ __tlbi_user(aside1, asid);
+ dsb(nsh);
+ } else {
+ __tlbi(aside1is, asid);
+ __tlbi_user(aside1is, asid);
+ __tlbi_sync_s1ish(mm);
+ }
+ flush_tlb_user_post(local);
mmu_notifier_arch_invalidate_secondary_tlbs(mm, 0, -1UL);
}
@@ -475,6 +557,12 @@ static inline void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch)
* operations can only span an even number of pages. We save this for last to
* ensure 64KB start alignment is maintained for the LPA2 case.
*/
+static __always_inline void rvae1(u64 arg)
+{
+ __tlbi(rvae1, arg);
+ __tlbi_user(rvae1, arg);
+}
+
static __always_inline void rvae1is(u64 arg)
{
__tlbi(rvae1is, arg);
@@ -573,23 +661,6 @@ static inline bool __flush_tlb_range_limit_excess(unsigned long pages,
return pages >= (MAX_DVM_OPS * stride) >> PAGE_SHIFT;
}
-typedef unsigned __bitwise tlbf_t;
-
-/* No special behaviour. */
-#define TLBF_NONE ((__force tlbf_t)0)
-
-/* Invalidate tlb entries only, leaving the page table walk cache intact. */
-#define TLBF_NOWALKCACHE ((__force tlbf_t)BIT(0))
-
-/* Skip the trailing dsb after issuing tlbi. */
-#define TLBF_NOSYNC ((__force tlbf_t)BIT(1))
-
-/* Suppress tlb notifier callbacks for this flush operation. */
-#define TLBF_NONOTIFY ((__force tlbf_t)BIT(2))
-
-/* Perform the tlbi locally without broadcasting to other CPUs. */
-#define TLBF_NOBROADCAST ((__force tlbf_t)BIT(3))
-
static __always_inline void __do_flush_tlb_range(struct vm_area_struct *vma,
unsigned long start, unsigned long end,
unsigned long stride, int tlb_level,
@@ -597,6 +668,7 @@ static __always_inline void __do_flush_tlb_range(struct vm_area_struct *vma,
{
struct mm_struct *mm = vma->vm_mm;
unsigned long asid, pages;
+ bool local;
pages = (end - start) >> PAGE_SHIFT;
@@ -605,10 +677,9 @@ static __always_inline void __do_flush_tlb_range(struct vm_area_struct *vma,
return;
}
- if (!(flags & TLBF_NOBROADCAST))
- dsb(ishst);
- else
- dsb(nshst);
+ local = flush_tlb_user_pre(mm, flags);
+ if (local && !(flags & TLBF_NOBROADCAST))
+ flags |= TLBF_NOBROADCAST;
asid = ASID(mm);
@@ -622,8 +693,8 @@ static __always_inline void __do_flush_tlb_range(struct vm_area_struct *vma,
asid, tlb_level);
break;
case TLBF_NOBROADCAST:
- /* Combination unused */
- BUG();
+ __flush_s1_tlb_range_op(vae1, start, pages, stride,
+ asid, tlb_level);
break;
case TLBF_NOWALKCACHE | TLBF_NOBROADCAST:
__flush_s1_tlb_range_op(vale1, start, pages, stride,
@@ -640,6 +711,8 @@ static __always_inline void __do_flush_tlb_range(struct vm_area_struct *vma,
else
dsb(nsh);
}
+
+ flush_tlb_user_post(local);
}
static inline void __flush_tlb_range(struct vm_area_struct *vma,
diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c
index 0f4a28b87469..f34ed78393e0 100644
--- a/arch/arm64/mm/context.c
+++ b/arch/arm64/mm/context.c
@@ -214,9 +214,10 @@ static u64 new_context(struct mm_struct *mm)
void check_and_switch_context(struct mm_struct *mm)
{
- unsigned long flags;
- unsigned int cpu;
+ unsigned int cpu = smp_processor_id();
u64 asid, old_active_asid;
+ unsigned int active;
+ unsigned long flags;
if (system_supports_cnp())
cpu_set_reserved_ttbr0();
@@ -251,7 +252,6 @@ void check_and_switch_context(struct mm_struct *mm)
atomic64_set(&mm->context.id, asid);
}
- cpu = smp_processor_id();
if (cpumask_test_and_clear_cpu(cpu, &tlb_flush_pending))
local_flush_tlb_all();
@@ -262,6 +262,30 @@ void check_and_switch_context(struct mm_struct *mm)
arm64_apply_bp_hardening();
+ /*
+ * Update mm->context.active_cpu in such a manner that we avoid cmpxchg
+ * and dsb unless we definitely need it. If initially ACTIVE_CPU_NONE
+ * then we are the first cpu to run so set it to our id. If initially
+ * any id other than ours, we are the second cpu to run so set it to
+ * ACTIVE_CPU_MULTIPLE. If we update the value then we must issue
+ * dsb(ishst) to ensure stores to mm->context.active_cpu are ordered
+ * against the TTBR0 write in cpu_switch_mm()/uaccess_enable(); the
+ * store must be visible to another cpu before this cpu could have
+ * populated any TLB entries based on the pgtables that will be
+ * installed.
+ */
+ active = READ_ONCE(mm->context.active_cpu);
+ if (active != cpu && active != ACTIVE_CPU_MULTIPLE) {
+ if (active == ACTIVE_CPU_NONE)
+ active = cmpxchg_relaxed(&mm->context.active_cpu,
+ ACTIVE_CPU_NONE, cpu);
+
+ if (active != ACTIVE_CPU_NONE)
+ WRITE_ONCE(mm->context.active_cpu, ACTIVE_CPU_MULTIPLE);
+
+ dsb(ishst);
+ }
+
/*
* Defer TTBR0_EL1 setting for user threads to uaccess_enable() when
* emulating PAN.
--
2.47.3
^ permalink raw reply related
* Re: [PATCH v2 2/7] clk: qcom: Restrict A7PLL and IPQ4019 GCC to ARM
From: Dmitry Baryshkov @ 2026-06-09 22:44 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Bjorn Andersson, Michael Turquette, Stephen Boyd, Brian Masney,
Konrad Dybcio, linux-arm-msm, linux-clk, linux-kernel,
linux-arm-kernel
In-Reply-To: <20260609-clk-qcom-defaults-v2-2-0c67c06dca11@oss.qualcomm.com>
On Tue, Jun 09, 2026 at 05:32:36PM +0200, Krzysztof Kozlowski wrote:
> IPQ4019 is ARM 32-bit only SoC and QCOM_A7PLL is used only on SDX55 and
> SDX65, which are 32-bit as well.
>
> Do not allow building them for ARM64 to make built kernels smaller and
> user choices easier.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply
* [soc:imx/dt] BUILD SUCCESS 8772e1f64c7d69986821d71d8e58fd10594c9aa1
From: kernel test robot @ 2026-06-09 22:52 UTC (permalink / raw)
To: Frank Li; +Cc: linux-arm-kernel, arm
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git imx/dt
branch HEAD: 8772e1f64c7d69986821d71d8e58fd10594c9aa1 dt-bindings: soc: imx: Add fsl,aipi-bus and fsl,emi-bus
elapsed time: 7286m
configs tested: 184
configs skipped: 9
The following configs have been built successfully.
More configs may be tested in the coming days.
tested configs:
alpha allnoconfig gcc-16.1.0
alpha allyesconfig gcc-16.1.0
alpha defconfig gcc-16.1.0
arc allmodconfig clang-23
arc allmodconfig gcc-16.1.0
arc allnoconfig gcc-16.1.0
arc allyesconfig clang-23
arc allyesconfig gcc-16.1.0
arc axs101_defconfig gcc-16.1.0
arc defconfig gcc-16.1.0
arc randconfig-001-20260610 gcc-8.5.0
arc randconfig-002-20260610 gcc-8.5.0
arm allnoconfig clang-23
arm allnoconfig gcc-16.1.0
arm allyesconfig clang-23
arm allyesconfig gcc-16.1.0
arm defconfig gcc-16.1.0
arm randconfig-001-20260610 gcc-8.5.0
arm randconfig-002-20260610 gcc-8.5.0
arm randconfig-003-20260610 gcc-8.5.0
arm randconfig-004-20260610 gcc-8.5.0
arm64 allmodconfig clang-23
arm64 allnoconfig gcc-16.1.0
arm64 defconfig gcc-16.1.0
arm64 randconfig-001-20260610 gcc-11.5.0
arm64 randconfig-002-20260610 gcc-11.5.0
arm64 randconfig-003-20260610 gcc-11.5.0
arm64 randconfig-004-20260610 gcc-11.5.0
csky allmodconfig gcc-16.1.0
csky allnoconfig gcc-16.1.0
csky defconfig gcc-16.1.0
csky randconfig-001-20260610 gcc-11.5.0
csky randconfig-002-20260610 gcc-11.5.0
hexagon allmodconfig clang-23
hexagon allmodconfig gcc-16.1.0
hexagon allnoconfig clang-23
hexagon allnoconfig gcc-16.1.0
hexagon defconfig gcc-16.1.0
hexagon randconfig-001-20260610 clang-22
hexagon randconfig-002-20260610 clang-22
i386 allmodconfig clang-22
i386 allnoconfig gcc-14
i386 allnoconfig gcc-16.1.0
i386 allyesconfig clang-22
i386 buildonly-randconfig-001-20260610 gcc-14
i386 buildonly-randconfig-002-20260610 gcc-14
i386 buildonly-randconfig-003-20260610 gcc-14
i386 buildonly-randconfig-004-20260610 gcc-14
i386 buildonly-randconfig-005-20260610 gcc-14
i386 buildonly-randconfig-006-20260610 gcc-14
i386 defconfig gcc-16.1.0
i386 randconfig-011-20260610 gcc-14
i386 randconfig-012-20260610 gcc-14
i386 randconfig-013-20260610 gcc-14
i386 randconfig-014-20260610 gcc-14
i386 randconfig-015-20260610 gcc-14
i386 randconfig-016-20260610 gcc-14
i386 randconfig-017-20260610 gcc-14
loongarch allmodconfig clang-19
loongarch allmodconfig clang-23
loongarch allnoconfig clang-20
loongarch allnoconfig gcc-16.1.0
loongarch defconfig clang-23
loongarch randconfig-001-20260610 clang-22
loongarch randconfig-002-20260610 clang-22
m68k allmodconfig gcc-16.1.0
m68k allnoconfig gcc-16.1.0
m68k allyesconfig clang-23
m68k allyesconfig gcc-16.1.0
m68k defconfig clang-23
microblaze allnoconfig gcc-16.1.0
microblaze allyesconfig gcc-16.1.0
microblaze defconfig clang-23
mips allmodconfig gcc-16.1.0
mips allnoconfig gcc-16.1.0
mips allyesconfig gcc-16.1.0
nios2 allmodconfig clang-20
nios2 allmodconfig gcc-11.5.0
nios2 allnoconfig clang-23
nios2 allnoconfig gcc-11.5.0
nios2 defconfig clang-23
nios2 randconfig-001-20260610 clang-22
nios2 randconfig-002-20260610 clang-22
openrisc allmodconfig clang-20
openrisc allmodconfig gcc-16.1.0
openrisc allnoconfig clang-23
openrisc allnoconfig gcc-16.1.0
openrisc defconfig gcc-16.1.0
parisc allmodconfig gcc-16.1.0
parisc allnoconfig clang-23
parisc allnoconfig gcc-16.1.0
parisc allyesconfig clang-23
parisc allyesconfig gcc-16.1.0
parisc defconfig gcc-16.1.0
parisc randconfig-001-20260610 gcc-8.5.0
parisc randconfig-002-20260610 gcc-8.5.0
parisc64 defconfig clang-23
powerpc allmodconfig gcc-16.1.0
powerpc allnoconfig clang-23
powerpc allnoconfig gcc-16.1.0
powerpc microwatt_defconfig gcc-16.1.0
powerpc pasemi_defconfig clang-23
powerpc randconfig-001-20260610 gcc-8.5.0
powerpc randconfig-002-20260610 gcc-8.5.0
powerpc tqm8548_defconfig clang-23
powerpc64 randconfig-001-20260610 gcc-8.5.0
powerpc64 randconfig-002-20260610 gcc-8.5.0
riscv allmodconfig clang-23
riscv allnoconfig clang-23
riscv allnoconfig gcc-16.1.0
riscv allyesconfig clang-23
riscv defconfig gcc-16.1.0
riscv randconfig-001-20260610 gcc-16.1.0
riscv randconfig-002-20260610 gcc-16.1.0
s390 allmodconfig clang-23
s390 allnoconfig clang-23
s390 allyesconfig gcc-16.1.0
s390 defconfig gcc-16.1.0
s390 randconfig-001-20260610 gcc-16.1.0
s390 randconfig-002-20260610 gcc-16.1.0
sh allmodconfig gcc-16.1.0
sh allnoconfig clang-23
sh allnoconfig gcc-16.1.0
sh allyesconfig clang-23
sh allyesconfig gcc-16.1.0
sh defconfig gcc-14
sh randconfig-001-20260610 gcc-16.1.0
sh randconfig-002-20260610 gcc-16.1.0
sparc allnoconfig clang-23
sparc allnoconfig gcc-16.1.0
sparc defconfig gcc-16.1.0
sparc randconfig-001-20260610 gcc-14.3.0
sparc randconfig-002-20260610 gcc-14.3.0
sparc64 allmodconfig clang-20
sparc64 defconfig gcc-14
sparc64 randconfig-001-20260610 gcc-14.3.0
sparc64 randconfig-002-20260610 gcc-14.3.0
um allmodconfig clang-23
um allnoconfig clang-16
um allnoconfig clang-23
um allyesconfig gcc-14
um allyesconfig gcc-16.1.0
um defconfig gcc-14
um i386_defconfig gcc-14
um randconfig-001-20260610 gcc-14.3.0
um randconfig-002-20260610 gcc-14.3.0
um x86_64_defconfig gcc-14
x86_64 allmodconfig clang-22
x86_64 allnoconfig clang-22
x86_64 allnoconfig clang-23
x86_64 allyesconfig clang-22
x86_64 buildonly-randconfig-001-20260610 gcc-14
x86_64 buildonly-randconfig-002-20260610 gcc-14
x86_64 buildonly-randconfig-003-20260610 gcc-14
x86_64 buildonly-randconfig-004-20260610 gcc-14
x86_64 buildonly-randconfig-005-20260610 gcc-14
x86_64 buildonly-randconfig-006-20260610 gcc-14
x86_64 defconfig gcc-14
x86_64 kexec clang-22
x86_64 randconfig-011-20260610 gcc-14
x86_64 randconfig-012-20260610 gcc-14
x86_64 randconfig-013-20260610 gcc-14
x86_64 randconfig-014-20260610 gcc-14
x86_64 randconfig-015-20260610 gcc-14
x86_64 randconfig-016-20260610 gcc-14
x86_64 randconfig-071-20260610 gcc-14
x86_64 randconfig-072-20260610 gcc-14
x86_64 randconfig-073-20260610 gcc-14
x86_64 randconfig-074-20260610 gcc-14
x86_64 randconfig-075-20260610 gcc-14
x86_64 randconfig-076-20260610 gcc-14
x86_64 rhel-9.4 clang-22
x86_64 rhel-9.4-bpf gcc-14
x86_64 rhel-9.4-func clang-22
x86_64 rhel-9.4-kselftests clang-22
x86_64 rhel-9.4-kunit gcc-14
x86_64 rhel-9.4-ltp gcc-14
x86_64 rhel-9.4-rust clang-22
xtensa allnoconfig clang-23
xtensa allnoconfig gcc-16.1.0
xtensa allyesconfig clang-20
xtensa allyesconfig gcc-16.1.0
xtensa randconfig-001-20260610 gcc-14.3.0
xtensa randconfig-002-20260610 gcc-14.3.0
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply
* Re: [PATCH v2] regulator: dt-bindings: mt6311: Convert to DT schema
From: Mark Brown @ 2026-06-09 21:46 UTC (permalink / raw)
To: lgirdwood, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, Ninad Naik
Cc: devicetree, linux-kernel, linux-arm-kernel, linux-mediatek, me,
linux-kernel-mentees, skhan
In-Reply-To: <20260604162624.644241-1-ninadnaik07@gmail.com>
On Thu, 04 Jun 2026 21:56:24 +0530, Ninad Naik wrote:
> regulator: dt-bindings: mt6311: Convert to DT schema
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator.git for-7.2
Thanks!
[1/1] regulator: dt-bindings: mt6311: Convert to DT schema
https://git.kernel.org/broonie/regulator/c/fd964ee0ac9e
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
^ permalink raw reply
* Re: [PATCH v1] spi: Use named initializers for platform_device_id arrays
From: Mark Brown @ 2026-06-09 21:44 UTC (permalink / raw)
To: Uwe Kleine-König (The Capable Hub)
Cc: Jonas Gorski, David Rhodes, Richard Fitzgerald, Andi Shyti,
Tudor Ambarus, Krzysztof Kozlowski, Peter Griffin, Alim Akhtar,
linux-spi, linux-kernel, patches, linux-samsung-soc,
linux-arm-kernel
In-Reply-To: <3fcd432a505bb1bb7f8ef0fba9162243200b3347.1780606153.git.u.kleine-koenig@baylibre.com>
On Thu, 04 Jun 2026 22:55:26 +0200, Uwe Kleine-König (The Capable Hub) wrote:
> spi: Use named initializers for platform_device_id arrays
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-7.2
Thanks!
[1/1] spi: Use named initializers for platform_device_id arrays
https://git.kernel.org/broonie/spi/c/fc82dda1dcc6
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
^ permalink raw reply
* Re: [PATCH] regulator: mt6359: Fix vbbck default internal supply name
From: Mark Brown @ 2026-06-09 18:01 UTC (permalink / raw)
To: Liam Girdwood, Matthias Brugger, AngeloGioacchino Del Regno,
Chen-Yu Tsai
Cc: linux-arm-kernel, linux-mediatek, linux-kernel
In-Reply-To: <20260609083630.1600070-1-wenst@chromium.org>
On Tue, 09 Jun 2026 16:36:27 +0800, Chen-Yu Tsai wrote:
> regulator: mt6359: Fix vbbck default internal supply name
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator.git for-7.2
Thanks!
[1/1] regulator: mt6359: Fix vbbck default internal supply name
https://git.kernel.org/broonie/regulator/c/9aeba1351a22
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
^ permalink raw reply
* [soc:imx/soc] BUILD SUCCESS ccb4b54b8ecf1ebafef96d538cd6c5c8455bb390
From: kernel test robot @ 2026-06-09 23:28 UTC (permalink / raw)
To: Frank Li; +Cc: linux-arm-kernel, arm
tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git imx/soc
branch HEAD: ccb4b54b8ecf1ebafef96d538cd6c5c8455bb390 ARM: imx31: Fix IIM mapping leak in revision check
elapsed time: 11559m
configs tested: 266
configs skipped: 8
The following configs have been built successfully.
More configs may be tested in the coming days.
tested configs:
alpha allnoconfig gcc-16.1.0
alpha allyesconfig gcc-16.1.0
alpha defconfig gcc-16.1.0
arc allmodconfig gcc-16.1.0
arc allnoconfig gcc-16.1.0
arc allyesconfig clang-23
arc allyesconfig gcc-16.1.0
arc axs101_defconfig gcc-16.1.0
arc defconfig gcc-16.1.0
arc randconfig-001-20260609 gcc-15.2.0
arc randconfig-001-20260610 gcc-8.5.0
arc randconfig-002-20260609 gcc-13.4.0
arc randconfig-002-20260610 gcc-8.5.0
arm allnoconfig clang-23
arm allnoconfig gcc-16.1.0
arm allyesconfig gcc-16.1.0
arm defconfig clang-23
arm defconfig gcc-16.1.0
arm randconfig-001-20260609 gcc-13.4.0
arm randconfig-001-20260610 gcc-8.5.0
arm randconfig-002-20260609 clang-23
arm randconfig-002-20260610 gcc-8.5.0
arm randconfig-003-20260609 clang-23
arm randconfig-003-20260610 gcc-8.5.0
arm randconfig-004-20260609 clang-23
arm randconfig-004-20260610 gcc-8.5.0
arm64 allmodconfig clang-23
arm64 allnoconfig gcc-16.1.0
arm64 defconfig gcc-16.1.0
arm64 randconfig-001-20260609 clang-23
arm64 randconfig-001-20260610 gcc-11.5.0
arm64 randconfig-002-20260609 gcc-13.4.0
arm64 randconfig-002-20260610 gcc-11.5.0
arm64 randconfig-003-20260609 gcc-15.2.0
arm64 randconfig-003-20260610 gcc-11.5.0
arm64 randconfig-004-20260609 clang-23
arm64 randconfig-004-20260610 gcc-11.5.0
csky allmodconfig gcc-16.1.0
csky allnoconfig gcc-16.1.0
csky defconfig gcc-16.1.0
csky randconfig-001-20260609 gcc-9.5.0
csky randconfig-001-20260610 gcc-11.5.0
csky randconfig-002-20260609 gcc-11.5.0
csky randconfig-002-20260610 gcc-11.5.0
hexagon allmodconfig clang-23
hexagon allnoconfig clang-23
hexagon allnoconfig gcc-16.1.0
hexagon defconfig clang-23
hexagon defconfig gcc-16.1.0
hexagon randconfig-001-20260609 clang-18
hexagon randconfig-002-20260609 clang-23
i386 allmodconfig clang-22
i386 allmodconfig gcc-14
i386 allnoconfig gcc-14
i386 allnoconfig gcc-16.1.0
i386 allyesconfig clang-22
i386 allyesconfig gcc-14
i386 buildonly-randconfig-001-20260609 gcc-14
i386 buildonly-randconfig-001-20260610 gcc-14
i386 buildonly-randconfig-002-20260609 gcc-14
i386 buildonly-randconfig-002-20260610 gcc-14
i386 buildonly-randconfig-003-20260609 clang-22
i386 buildonly-randconfig-003-20260610 gcc-14
i386 buildonly-randconfig-004-20260609 clang-22
i386 buildonly-randconfig-004-20260610 gcc-14
i386 buildonly-randconfig-005-20260609 gcc-14
i386 buildonly-randconfig-005-20260610 gcc-14
i386 buildonly-randconfig-006-20260609 clang-22
i386 buildonly-randconfig-006-20260610 gcc-14
i386 defconfig clang-22
i386 defconfig gcc-16.1.0
i386 randconfig-001 clang-22
i386 randconfig-001-20260609 gcc-14
i386 randconfig-002 gcc-14
i386 randconfig-002-20260609 gcc-14
i386 randconfig-003 gcc-14
i386 randconfig-003-20260609 gcc-14
i386 randconfig-004 clang-22
i386 randconfig-004-20260609 clang-22
i386 randconfig-005 gcc-14
i386 randconfig-005-20260609 clang-22
i386 randconfig-006 gcc-14
i386 randconfig-006-20260609 clang-22
i386 randconfig-007 gcc-14
i386 randconfig-007-20260609 gcc-14
i386 randconfig-011 clang-22
i386 randconfig-011-20260609 clang-22
i386 randconfig-011-20260610 gcc-14
i386 randconfig-012 clang-22
i386 randconfig-012-20260609 clang-22
i386 randconfig-012-20260610 gcc-14
i386 randconfig-013 gcc-14
i386 randconfig-013-20260609 clang-22
i386 randconfig-013-20260610 gcc-14
i386 randconfig-014 clang-22
i386 randconfig-014-20260609 gcc-14
i386 randconfig-014-20260610 gcc-14
i386 randconfig-015 gcc-14
i386 randconfig-015-20260609 clang-22
i386 randconfig-015-20260610 gcc-14
i386 randconfig-016 gcc-14
i386 randconfig-016-20260609 clang-22
i386 randconfig-016-20260610 gcc-14
i386 randconfig-017 gcc-14
i386 randconfig-017-20260609 gcc-14
i386 randconfig-017-20260610 gcc-14
loongarch allmodconfig clang-19
loongarch allmodconfig clang-23
loongarch allnoconfig clang-20
loongarch allnoconfig gcc-16.1.0
loongarch defconfig clang-23
loongarch randconfig-001-20260609 clang-23
loongarch randconfig-002-20260609 clang-23
m68k allmodconfig gcc-16.1.0
m68k allnoconfig gcc-16.1.0
m68k allyesconfig gcc-16.1.0
m68k defconfig gcc-16.1.0
microblaze allnoconfig gcc-16.1.0
microblaze allyesconfig gcc-16.1.0
microblaze defconfig gcc-16.1.0
mips allmodconfig gcc-16.1.0
mips allnoconfig gcc-16.1.0
mips allyesconfig gcc-16.1.0
nios2 allmodconfig clang-20
nios2 allmodconfig gcc-11.5.0
nios2 allnoconfig clang-23
nios2 allnoconfig gcc-11.5.0
nios2 defconfig gcc-11.5.0
nios2 randconfig-001-20260609 gcc-11.5.0
nios2 randconfig-002-20260609 gcc-11.5.0
openrisc allmodconfig clang-20
openrisc allmodconfig gcc-16.1.0
openrisc allnoconfig clang-23
openrisc allnoconfig gcc-16.1.0
openrisc defconfig gcc-16.1.0
parisc allmodconfig gcc-16.1.0
parisc allnoconfig clang-23
parisc allnoconfig gcc-16.1.0
parisc allyesconfig clang-23
parisc allyesconfig gcc-16.1.0
parisc defconfig gcc-16.1.0
parisc randconfig-001-20260609 gcc-14.3.0
parisc randconfig-001-20260610 gcc-8.5.0
parisc randconfig-002-20260609 gcc-16.1.0
parisc randconfig-002-20260610 gcc-8.5.0
parisc64 defconfig gcc-16.1.0
powerpc allmodconfig gcc-16.1.0
powerpc allnoconfig clang-23
powerpc allnoconfig gcc-16.1.0
powerpc randconfig-001-20260609 clang-23
powerpc randconfig-001-20260610 gcc-8.5.0
powerpc randconfig-002-20260609 clang-23
powerpc randconfig-002-20260610 gcc-8.5.0
powerpc64 randconfig-001-20260609 gcc-8.5.0
powerpc64 randconfig-001-20260610 gcc-8.5.0
powerpc64 randconfig-002-20260609 gcc-13.4.0
powerpc64 randconfig-002-20260610 gcc-8.5.0
riscv allmodconfig clang-23
riscv allnoconfig clang-23
riscv allnoconfig gcc-16.1.0
riscv allyesconfig clang-23
riscv defconfig clang-23
riscv defconfig gcc-16.1.0
riscv randconfig-001-20260609 clang-23
riscv randconfig-001-20260610 gcc-16.1.0
riscv randconfig-002-20260609 clang-23
riscv randconfig-002-20260610 gcc-16.1.0
s390 allmodconfig clang-23
s390 allnoconfig clang-23
s390 allyesconfig gcc-16.1.0
s390 defconfig clang-18
s390 defconfig gcc-16.1.0
s390 randconfig-001-20260609 clang-23
s390 randconfig-001-20260610 gcc-16.1.0
s390 randconfig-002-20260609 gcc-16.1.0
s390 randconfig-002-20260610 gcc-16.1.0
sh allmodconfig gcc-16.1.0
sh allnoconfig clang-23
sh allnoconfig gcc-16.1.0
sh allyesconfig clang-23
sh allyesconfig gcc-16.1.0
sh defconfig gcc-14
sh defconfig gcc-16.1.0
sh kfr2r09-romimage_defconfig gcc-16.1.0
sh randconfig-001-20260609 gcc-13.4.0
sh randconfig-001-20260610 gcc-16.1.0
sh randconfig-002-20260609 gcc-11.5.0
sh randconfig-002-20260610 gcc-16.1.0
sparc allnoconfig clang-23
sparc allnoconfig gcc-16.1.0
sparc defconfig gcc-16.1.0
sparc randconfig-001-20260609 gcc-16.1.0
sparc randconfig-001-20260610 gcc-14.3.0
sparc randconfig-002-20260609 gcc-16.1.0
sparc randconfig-002-20260610 gcc-14.3.0
sparc64 allmodconfig clang-20
sparc64 defconfig clang-23
sparc64 defconfig gcc-14
sparc64 randconfig-001-20260609 clang-23
sparc64 randconfig-001-20260610 gcc-14.3.0
sparc64 randconfig-002-20260609 gcc-10.5.0
sparc64 randconfig-002-20260610 gcc-14.3.0
um allmodconfig clang-23
um allnoconfig clang-16
um allnoconfig clang-23
um allyesconfig gcc-14
um defconfig clang-23
um defconfig gcc-14
um i386_defconfig gcc-14
um randconfig-001-20260609 gcc-14
um randconfig-001-20260610 gcc-14.3.0
um randconfig-002-20260609 gcc-12
um randconfig-002-20260610 gcc-14.3.0
um x86_64_defconfig clang-23
um x86_64_defconfig gcc-14
x86_64 allmodconfig clang-22
x86_64 allnoconfig clang-22
x86_64 allnoconfig clang-23
x86_64 allyesconfig clang-22
x86_64 buildonly-randconfig-001-20260610 gcc-14
x86_64 buildonly-randconfig-002-20260610 gcc-14
x86_64 buildonly-randconfig-003-20260610 gcc-14
x86_64 buildonly-randconfig-004-20260610 gcc-14
x86_64 buildonly-randconfig-005-20260610 gcc-14
x86_64 buildonly-randconfig-006-20260610 gcc-14
x86_64 defconfig gcc-14
x86_64 kexec clang-22
x86_64 randconfig-001-20260609 gcc-14
x86_64 randconfig-002-20260609 clang-22
x86_64 randconfig-003-20260609 gcc-14
x86_64 randconfig-004-20260609 clang-22
x86_64 randconfig-005-20260609 clang-22
x86_64 randconfig-006-20260609 clang-22
x86_64 randconfig-011-20260609 gcc-14
x86_64 randconfig-011-20260610 gcc-14
x86_64 randconfig-012-20260609 clang-22
x86_64 randconfig-012-20260610 gcc-14
x86_64 randconfig-013-20260609 gcc-14
x86_64 randconfig-013-20260610 gcc-14
x86_64 randconfig-014-20260609 gcc-14
x86_64 randconfig-014-20260610 gcc-14
x86_64 randconfig-015-20260609 clang-22
x86_64 randconfig-015-20260610 gcc-14
x86_64 randconfig-016-20260609 gcc-14
x86_64 randconfig-016-20260610 gcc-14
x86_64 randconfig-071-20260609 clang-22
x86_64 randconfig-072-20260609 clang-22
x86_64 randconfig-073-20260609 clang-22
x86_64 randconfig-074-20260609 gcc-14
x86_64 randconfig-075-20260609 gcc-14
x86_64 randconfig-076-20260609 clang-22
x86_64 rhel-9.4 clang-22
x86_64 rhel-9.4-bpf gcc-14
x86_64 rhel-9.4-func clang-22
x86_64 rhel-9.4-kselftests clang-22
x86_64 rhel-9.4-kunit gcc-14
x86_64 rhel-9.4-ltp gcc-14
x86_64 rhel-9.4-rust clang-22
xtensa allnoconfig clang-23
xtensa allnoconfig gcc-16.1.0
xtensa allyesconfig clang-20
xtensa allyesconfig gcc-16.1.0
xtensa randconfig-001-20260609 gcc-16.1.0
xtensa randconfig-001-20260610 gcc-14.3.0
xtensa randconfig-002-20260609 gcc-8.5.0
xtensa randconfig-002-20260610 gcc-14.3.0
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply
* Re: [PATCH v2 00/16] Bump minimum version of LLVM for building the kernel to 17.0.1
From: Nathan Chancellor @ 2026-06-09 23:28 UTC (permalink / raw)
To: Nicolas Schier, Bill Wendling, Justin Stitt, Nick Desaulniers,
Nathan Chancellor
Cc: linux-kernel, llvm, linux-kbuild, Jonathan Corbet, Shuah Khan,
linux-doc, Kees Cook, Gustavo A. R. Silva, linux-hardening,
linux-security-module, Rong Xu, Han Shen, Russell King,
Arnd Bergmann, linux-arm-kernel, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Alexandre Ghiti, linux-riscv, Thomas Gleixner,
Ingo Molnar, Borislav Petkov, Dave Hansen, x86, H. Peter Anvin,
Ard Biesheuvel, Peter Zijlstra
In-Reply-To: <20260517-bump-minimum-supported-llvm-version-to-17-v2-0-b3b8cda46bdd@kernel.org>
On Sun, 17 May 2026 13:05:03 -1000, Nathan Chancellor wrote:
> Bump minimum version of LLVM for building the kernel to 17.0.1
>
> The current minimum version of LLVM for building the kernel is 15.0.0.
> However, there are two deficiencies compared to GCC that were fixed in
> LLVM 17 that are starting to become more noticeable.
>
> The first was a bug in LLVM's scope checker [1], where all labels in a
> function were validated as potential targets of an asm goto statement,
> even if they were not listed in the asm goto statement as targets. This
> becomes particularly problematic when the cleanup attribute is used, as
>
> [...]
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/kbuild/linux.git kbuild-next
Thanks!
[01/16] kbuild: Bump minimum version of LLVM for building the kernel to 17.0.1
https://git.kernel.org/kbuild/c/ce3267a39a92b
[02/16] security/Kconfig.hardening: Remove tautological condition from CC_HAS_ZERO_CALL_USED_REGS
https://git.kernel.org/kbuild/c/813fe686e90b4
[03/16] security/Kconfig.hardening: Remove tautological condition from FORTIFY_SOURCE
https://git.kernel.org/kbuild/c/8ad2017578c99
[04/16] security/Kconfig.hardening: Remove tautological condition from CC_HAS_RANDSTRUCT
https://git.kernel.org/kbuild/c/9331258bc129a
[05/16] arch/Kconfig: Remove tautological conditions from HAS_LTO_CLANG
https://git.kernel.org/kbuild/c/2189cb1a80f06
[06/16] arch/Kconfig: Remove tautological condition from AUTOFDO_CLANG
https://git.kernel.org/kbuild/c/de0bf1e138fcd
[07/16] ARM: Drop tautological ld.lld conditions from ARCH_MULTI_V4{,T}
https://git.kernel.org/kbuild/c/48d229b6a48ae
[08/16] riscv: Remove tautological condition from selection of ARCH_SUPPORTS_CFI
https://git.kernel.org/kbuild/c/62c4af8689511
[09/16] riscv: Drop tautological condition from TOOLCHAIN_NEEDS_OLD_ISA_SPEC
https://git.kernel.org/kbuild/c/7e279976cf2a2
[10/16] scripts/Makefile.warn: Drop -Wformat handling for clang < 16
https://git.kernel.org/kbuild/c/2a35c63c6bc42
[11/16] x86/build: Drop unnecessary '-ffreestanding' addition to KBUILD_CFLAGS
https://git.kernel.org/kbuild/c/7b3281fcb43c5
[12/16] x86/module: Revert "Deal with GOT based stack cookie load on Clang < 17"
https://git.kernel.org/kbuild/c/12b7bf92bddd4
[13/16] x86/entry/vdso32: Remove conditional omission of '.cfi_offset eflags'
https://git.kernel.org/kbuild/c/4e7af20d0d104
[14/16] kbuild: Remove check for broken scoping with clang < 17 in CC_HAS_ASM_GOTO_OUTPUT
https://git.kernel.org/kbuild/c/f3de78cb19d12
[15/16] compiler-clang.h: Remove __cleanup -Wunused-variable workaround
https://git.kernel.org/kbuild/c/c69eaa687667e
[16/16] compiler-clang.h: Drop explicit version number from "all" diagnostic macro
https://git.kernel.org/kbuild/c/c919893eabb43
Please look out for regression or issue reports or other follow up
comments, as they may result in the patch/series getting dropped or
reverted. Patches applied to an "unstable" branch are accepted pending
wider testing in -next and any post-commit review; they will generally
be moved to the main branch in a week if no issues are found.
Best regards,
--
Cheers,
Nathan
^ permalink raw reply
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