* [PATCH 1/2] clocksource/drivers/arm_arch_timer_mmio: Refactor for early init
From: Stephan Gerhold @ 2026-06-10 17:53 UTC (permalink / raw)
To: Mark Rutland, Marc Zyngier, Daniel Lezcano, Thomas Gleixner,
Sudeep Holla
Cc: linux-arm-kernel, linux-kernel, linux-arm-msm, Jack Matthews
In-Reply-To: <20260610-arm-arch-timer-mmio-early-v1-0-ac17218ec8b4@linaro.org>
In preparation of restoring support for using arm,armv7-timer-mem as an
early timer, refactor the driver to allow early initialization without
a device pointer. Replace uses of dev_() logging with pr_(), replace devm
helpers with manual cleanup or scope-based cleanup helpers where possible.
Create a new arch_timer_mmio_init() function that performs the
initialization and registration without a device pointer.
This is not very pretty, although given that the driver cannot be removed
at runtime due to .suppress_bind_attrs = true, at least the overhead for
the manual resource management is limited.
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
---
drivers/clocksource/arm_arch_timer_mmio.c | 139 +++++++++++++++++-------------
1 file changed, 79 insertions(+), 60 deletions(-)
diff --git a/drivers/clocksource/arm_arch_timer_mmio.c b/drivers/clocksource/arm_arch_timer_mmio.c
index d10362692fdd..5cb94051c4be 100644
--- a/drivers/clocksource/arm_arch_timer_mmio.c
+++ b/drivers/clocksource/arm_arch_timer_mmio.c
@@ -10,7 +10,9 @@
#define pr_fmt(fmt) "arch_timer_mmio: " fmt
+#include <linux/cleanup.h>
#include <linux/clockchips.h>
+#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/io-64-nonatomic-lo-hi.h>
#include <linux/of_irq.h>
@@ -191,17 +193,16 @@ static irqreturn_t arch_timer_mmio_handler(int irq, void *dev_id)
return IRQ_NONE;
}
-static struct arch_timer_mem_frame *find_best_frame(struct platform_device *pdev)
+static struct arch_timer_mem_frame *find_best_frame(struct arch_timer *at)
{
struct arch_timer_mem_frame *frame, *best_frame = NULL;
- struct arch_timer *at = platform_get_drvdata(pdev);
void __iomem *cntctlbase;
u32 cnttidr;
cntctlbase = ioremap(at->gt_block->cntctlbase, at->gt_block->size);
if (!cntctlbase) {
- dev_err(&pdev->dev, "Can't map CNTCTLBase @ %pa\n",
- &at->gt_block->cntctlbase);
+ pr_err("Can't map CNTCTLBase @ %pa\n",
+ &at->gt_block->cntctlbase);
return NULL;
}
@@ -277,22 +278,21 @@ static void arch_timer_mmio_setup(struct arch_timer *at, int irq)
clocksource_register_hz(&at->cs, at->rate);
}
-static int arch_timer_mmio_frame_register(struct platform_device *pdev,
- struct arch_timer_mem_frame *frame)
+static int arch_timer_mmio_frame_register(struct arch_timer *at,
+ struct arch_timer_mem_frame *frame,
+ struct device_node *np)
{
- struct arch_timer *at = platform_get_drvdata(pdev);
- struct device_node *np = pdev->dev.of_node;
int ret, irq;
u32 rate;
- if (!devm_request_mem_region(&pdev->dev, frame->cntbase, frame->size,
- "arch_mem_timer"))
+ if (!request_mem_region(frame->cntbase, frame->size, "arch_mem_timer"))
return -EBUSY;
- at->base = devm_ioremap(&pdev->dev, frame->cntbase, frame->size);
+ at->base = ioremap(frame->cntbase, frame->size);
if (!at->base) {
- dev_err(&pdev->dev, "Can't map frame's registers\n");
- return -ENXIO;
+ pr_err("Can't map frame's registers @ %pa\n", &frame->cntbase);
+ ret = -ENXIO;
+ goto err_release_region;
}
/*
@@ -310,49 +310,56 @@ static int arch_timer_mmio_frame_register(struct platform_device *pdev,
at->rate = arch_timer_get_rate();
irq = at->access == VIRT_ACCESS ? frame->virt_irq : frame->phys_irq;
- ret = devm_request_irq(&pdev->dev, irq, arch_timer_mmio_handler,
- IRQF_TIMER | IRQF_NO_AUTOEN, "arch_mem_timer",
- &at->evt);
+ ret = request_irq(irq, arch_timer_mmio_handler,
+ IRQF_TIMER | IRQF_NO_AUTOEN, "arch_mem_timer",
+ &at->evt);
if (ret) {
- dev_err(&pdev->dev, "Failed to request mem timer irq\n");
- return ret;
+ pr_err("Failed to request mem timer irq for frame @ %pa\n",
+ &frame->cntbase);
+ goto err_iounmap;
}
/* Afer this point, we're not allowed to fail anymore */
arch_timer_mmio_setup(at, irq);
return 0;
+
+err_iounmap:
+ iounmap(at->base);
+err_release_region:
+ release_mem_region(frame->cntbase, frame->size);
+ return ret;
}
-static int of_populate_gt_block(struct platform_device *pdev,
- struct arch_timer *at)
+static int of_populate_gt_block(struct device_node *np, struct arch_timer_mem *gt_block)
{
struct resource res;
- if (of_address_to_resource(pdev->dev.of_node, 0, &res))
+ if (of_address_to_resource(np, 0, &res))
return -EINVAL;
- at->gt_block->cntctlbase = res.start;
- at->gt_block->size = resource_size(&res);
+ gt_block->cntctlbase = res.start;
+ gt_block->size = resource_size(&res);
- for_each_available_child_of_node_scoped(pdev->dev.of_node, frame_node) {
+ for_each_available_child_of_node_scoped(np, frame_node) {
struct arch_timer_mem_frame *frame;
u32 n;
if (of_property_read_u32(frame_node, "frame-number", &n)) {
- dev_err(&pdev->dev, FW_BUG "Missing frame-number\n");
+ pr_err(FW_BUG "Missing frame-number for %pOF\n",
+ frame_node);
return -EINVAL;
}
if (n >= ARCH_TIMER_MEM_MAX_FRAMES) {
- dev_err(&pdev->dev,
- FW_BUG "Wrong frame-number, only 0-%u are permitted\n",
- ARCH_TIMER_MEM_MAX_FRAMES - 1);
+ pr_err(FW_BUG "Wrong frame-number %u for %pOF, only 0-%u are permitted\n",
+ n, frame_node, ARCH_TIMER_MEM_MAX_FRAMES - 1);
return -EINVAL;
}
- frame = &at->gt_block->frame[n];
+ frame = >_block->frame[n];
if (frame->valid) {
- dev_err(&pdev->dev, FW_BUG "Duplicated frame-number\n");
+ pr_err(FW_BUG "Duplicated frame-number %u for %pOF\n",
+ n, frame_node);
return -EINVAL;
}
@@ -371,50 +378,62 @@ static int of_populate_gt_block(struct platform_device *pdev,
return 0;
}
-static int arch_timer_mmio_probe(struct platform_device *pdev)
+static struct arch_timer *arch_timer_mmio_init(struct arch_timer_mem *gt_block,
+ struct device_node *np)
{
+ struct arch_timer *at __free(kfree) = kzalloc_obj(*at);
struct arch_timer_mem_frame *frame;
- struct arch_timer *at;
- struct device_node *np;
int ret;
- np = pdev->dev.of_node;
-
- at = devm_kmalloc(&pdev->dev, sizeof(*at), GFP_KERNEL | __GFP_ZERO);
if (!at)
- return -ENOMEM;
+ return ERR_PTR(-ENOMEM);
+
+ at->gt_block = gt_block;
+
+ frame = find_best_frame(at);
+ if (!frame) {
+ pr_err("Unable to find a suitable frame in timer @ %pa\n",
+ &at->gt_block->cntctlbase);
+ return ERR_PTR(-EINVAL);
+ }
+
+ ret = arch_timer_mmio_frame_register(at, frame, np);
+ if (ret)
+ return ERR_PTR(ret);
+
+ pr_info("mmio timer running at %lu.%02luMHz (%s)\n",
+ (unsigned long)at->rate / 1000000,
+ (unsigned long)(at->rate / 10000) % 100,
+ at->access == VIRT_ACCESS ? "virt" : "phys");
+
+ return_ptr(at);
+}
+
+static int arch_timer_mmio_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct arch_timer_mem *gt_block;
+ struct arch_timer *at;
+ int ret;
if (np) {
- at->gt_block = devm_kmalloc(&pdev->dev, sizeof(*at->gt_block),
- GFP_KERNEL | __GFP_ZERO);
- if (!at->gt_block)
+ gt_block = devm_kzalloc(&pdev->dev, sizeof(*gt_block),
+ GFP_KERNEL);
+ if (!gt_block)
return -ENOMEM;
- ret = of_populate_gt_block(pdev, at);
+ ret = of_populate_gt_block(np, gt_block);
if (ret)
return ret;
} else {
- at->gt_block = dev_get_platdata(&pdev->dev);
- }
-
- platform_set_drvdata(pdev, at);
-
- frame = find_best_frame(pdev);
- if (!frame) {
- dev_err(&pdev->dev,
- "Unable to find a suitable frame in timer @ %pa\n",
- &at->gt_block->cntctlbase);
- return -EINVAL;
+ gt_block = dev_get_platdata(&pdev->dev);
}
- ret = arch_timer_mmio_frame_register(pdev, frame);
- if (!ret)
- dev_info(&pdev->dev,
- "mmio timer running at %lu.%02luMHz (%s)\n",
- (unsigned long)at->rate / 1000000,
- (unsigned long)(at->rate / 10000) % 100,
- at->access == VIRT_ACCESS ? "virt" : "phys");
+ at = arch_timer_mmio_init(gt_block, np);
+ if (IS_ERR(at))
+ return PTR_ERR(at);
- return ret;
+ platform_set_drvdata(pdev, at);
+ return 0;
}
static const struct of_device_id arch_timer_mmio_of_table[] = {
--
2.54.0
^ permalink raw reply related
* [PATCH 0/2] clocksource/drivers/arm_arch_timer_mmio: Restore support for early init
From: Stephan Gerhold @ 2026-06-10 17:53 UTC (permalink / raw)
To: Mark Rutland, Marc Zyngier, Daniel Lezcano, Thomas Gleixner,
Sudeep Holla
Cc: linux-arm-kernel, linux-kernel, linux-arm-msm, Jack Matthews
Jack reported a regression for some single-core Qualcomm platforms (e.g.
MDM9625, MDM9607) that no longer boot because no timers can be found during
early boot [1]. These platforms rely on an obscure timer setup where the
global Arm MMIO timer (arm,armv7-timer-mem) is used as the only available
timer for the CPU. This setup used to work fine until commit 0f67b56d84b4
("clocksource/drivers/arm_arch_timer_mmio: Switch over to standalone
driver") when the early timer initialization using TIMER_OF_DECLARE() was
removed when moving to the standalone MMIO driver.
There doesn't seem to be any other usable CPU timer on those platforms, so
this series restores the early timer support using TIMER_OF_DECLARE()
inside the new standalone arm_arch_timer_mmio driver. This is pretty ugly,
but I could not think of a better solution so far. I tried to keep the
ugliness for the two probe paths as limited as possible. :-)
If someone has a better idea how to solve this, I would be happy to try it.
[1]: https://lore.kernel.org/r/46A20F89-E208-4091-8B6E-B5C38BF82B42@jackmatthe.ws/
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
---
Stephan Gerhold (2):
clocksource/drivers/arm_arch_timer_mmio: Refactor for early init
clocksource/drivers/arm_arch_timer_mmio: Restore support for early init
drivers/clocksource/arm_arch_timer_mmio.c | 180 ++++++++++++++++++++----------
1 file changed, 123 insertions(+), 57 deletions(-)
---
base-commit: 49e02880ec0a8c378e811bc9d85da188d7c6204c
change-id: 20260609-arm-arch-timer-mmio-early-de97155938e4
Best regards,
--
Stephan Gerhold <stephan.gerhold@linaro.org>
^ permalink raw reply
* Re: [PATCH v8 11/12] iommu/arm-smmu-v3: Invoke pm_runtime before hw access
From: Daniel Mentz @ 2026-06-10 17:13 UTC (permalink / raw)
To: Pranjal Shrivastava
Cc: iommu, Will Deacon, Joerg Roedel, Robin Murphy, Jason Gunthorpe,
Mostafa Saleh, Nicolin Chen, Ashish Mhetre, linux-arm-kernel
In-Reply-To: <aihzgtczL99fM-1c@google.com>
On Tue, Jun 9, 2026 at 1:11 PM Pranjal Shrivastava <praan@google.com> wrote:
>
> On Tue, Jun 09, 2026 at 11:34:42AM -0700, Daniel Mentz wrote:
> > On Tue, Jun 9, 2026 at 3:34 AM Pranjal Shrivastava <praan@google.com> wrote:
> > > > I'm not sure if I have a good suggestion here. Have you considered the
> > > > following: Do not call arm_smmu_handle_gerror() from
> > > > arm_smmu_runtime_suspend(). Instead, call disable_irq() at the end of
> > > > the suspend handler (and enable_irq() at the beginning of the resume
> > > > handler)?
> > >
> > > I thought about using disable_irq(), but I think doing it at the
> > > hardware level (IRQ_CTRL) is better.
> > >
> > > By disabling in IRQ_CTRL and keeping the manual arm_smmu_handle_gerror()
> > > call at the end of suspend, we ensure that we don't lose any gerror info
> > > We catch and handle any errors that occurred during the drain/quiesce
> > > phase right before the power-down.
> >
> > I think the beauty of disable_irq() is that it synchronizes any
> > potentially running hard IRQ handler, which helps avoid races.
>
> Alright, I guess we could:
>
> 1. SMMUEN=0
> 2. IRQ_CTRL.gerror=0
Should we call arm_smmu_disable_irqs() here?
> 3. disable_irq();
> 4. handle_gerror(); at the end of suspend
^ permalink raw reply
* Re: [PATCH v8 07/12] iommu/arm-smmu-v3: Add CMDQ_PROD_STOP_FLAG to gate CMDQ submissions
From: Daniel Mentz @ 2026-06-10 17:37 UTC (permalink / raw)
To: Pranjal Shrivastava
Cc: iommu, Will Deacon, Joerg Roedel, Robin Murphy, Jason Gunthorpe,
Mostafa Saleh, Nicolin Chen, Ashish Mhetre, linux-arm-kernel
In-Reply-To: <aihiPQ2mdqMm13Cd@google.com>
On Tue, Jun 9, 2026 at 11:58 AM Pranjal Shrivastava <praan@google.com> wrote:
>
> On Tue, Jun 09, 2026 at 11:20:52AM -0700, Daniel Mentz wrote:
> > On Tue, Jun 9, 2026 at 3:05 AM Pranjal Shrivastava <praan@google.com> wrote:
> > > >
> > > > > Even if the worker CPU reorders the PTE write after the STOP_FLAG check,
> > > > > it is benign because the SMMU is incapable of fetching that (or any) PTE
> > > > > while the gate is closed. Because GATE_CLOSED == SMMUEN = 0, implying no
> > > > > access to any HW structures whatsoever.
> > > > >
> > > > > The real synchronization happens in the Resume Path:
> > > > >
> > > > > 1. arm_smmu_device_reset() clears all caches / TLBs.
> > > > > (None of these can have entries before SMMUEN=1)
> > > > >
> > > > > 2. We execute a full smp_mb() before setting SMMUEN=1. (that's why we
> > > > > need smp_mb before SMMUEN=1). This barrier ensures that any PTE
> > > > > writes made by any thread—including those that were elided while the
> > > > > gate was closed, are globally visible before the SMMU hardware starts
> > > > > fetching into TLBs again. (This is why Jason suggested this in v6 [1])
> > > >
> > > > A barrier on one CPU has no bearing on whether writes by any other CPU
> > > > can be observed by any particular agent in the system.
> > > >
> > > > Let's compare this with the long comment in
> > > > arm_smmu_domain_inv_range() which is what I believe Jason was
> > > > referring to. In that example, you see smp_mb() in the code path on
> > > > CPU0 and dma_wmb() in the code path on CPU1. Hence, barriers exist on
> > > > both sides. If you compare the runtime PM design with
> > > > arm_smmu_domain_inv_range(), then smp_mb() belongs in the CPU thread
> > > > that performs the translation table updates not the one that performs
> > > > the suspend/resume operation.
> > > >
> > >
> > > I might be missing something here, so please bear with me. My
> > > understanding it that's needed because the IOMMU is live & actively
> > > caching, which is not true for our case.
> >
> > I think the "invs" design (Per-domain invalidation array) is more
> > similar than you think! An SMMU being absent from invs is equivalent
> > to the STOP flag, and the STE pointing to TTB0 is roughly the
> > equivalent of SMMEN=1 i.e. the IOMMU is not actively caching a
> > particular translation domain until an STE (or CD) points to it.
> >
> > > [Assuming we use non-relaxed semantics & ordering for the STOP flag,
> > > i.e. set STOP_FLAG + barrier & clear STOP_FLAG (implicit dma_wmb())]
> > >
> > > In our case, during the resume op, we first clear the STOP_FLAG before
> > > setting SMMUEN=1 in program order. Thus, any PTE invalidations occurring
> > > before SMMUEN=1 are executed, i.e. EVEN when the SMMU is guaranteed not
> > > to access any structures, we've resumed invalidations.
> >
> > "[...] we first clear the STOP_FLAG before setting SMMUEN=1 in program
> > order." I think this should be modified to "we first clear the
> > STOP_FLAG and ensure that the cleared STOP_FLAG is observable by all
> > other CPUs before setting SMMUEN=1"
> >
>
> Ack. The goal was to explain the algorithm for this thread, I won't be
> commenting it in code. Are you suggesting I should convert my
> explaination of the algorithm above into in-line comments and make sure
> to include the STOP_FLAG observability part?
I believe there would be a benefit to having a comment in the code
that states the requirements for the STOP_FLAG observability.
Something along the lines of either of the following:
* SMMU must be disabled any time another CPU can observe the STOP_FLAG
* Other CPUs must (a) observe the STOP flag only after the SMMU is
disabled, and (b) observe the cleared STOP flag before the SMMU is
re-enabled.
> >
> > I would define a set of invariants:
> >
> > * If an agent observes the STOP flag, it is guaranteed that SMMUEN=0
> > (with ABORT set) at the time of observation.
> > * Any transition from a set STOP flag to SMMUEN=1 involves an
> > invalidate-all operation prior to setting SMMUEN=1
> >
> > Hence, if a CPU observes the STOP flag, it is assured that (a)
> > transactions are blocked and (b) if the SMMU is ever re-enabled, an
> > invalidate-all is performed prior to it being enabled.
> >
> > I would then argue that all operations support these invariants. For
> > example, we need proper barriers in the iommu_unmap path to ensure
> > that the STOP flag is only checked *after* the translation table
> > update is made. Hence, we need a memory barrier.
> >
> > I look at it this way: Every elided invalidation creates an
> > "invalidation deficit", and this deficit is tolerable for two reasons:
> > (a) SMMU blocks all transactions while there is a deficit. (b) An
> > invalidate-all eliminates any deficit accrued while the STOP flag was
> > set.
>
> Ack, which means you agree with the design proposed in my last reply.
> I'll document these invariants in line if that's what you're suggesting
> here?
Yes, I believe we are in agreement, and yes, I think documenting these
invariants would be beneficial.
[...]
> >
> >
> > > HW structures not accessed means no TLB / CFG
> > > cache accesses as well according to the spec.
> > >
> > > [CPU1] ==> PTE update => Invalidate => Succeeds (although SMMUEN = 0)
> > >
> > > [CPU0] GBPA.Abort set ==> Txns are blocked
> > >
> > > [CPU2] => PTE update => Invalidate => Succeeds [Txns blocked + SMMUEN=0]
> > >
> > > [CPU0] ==> SET STOP_FLAG ==> Elision begins
> > >
> > > [CPU3] ==> PTE update ==> Invalidation ==> Elided [Txns blocked + SMMUEN=0]
> > >
> > > Hence, the races in the suspend sequence are handled correctly.
> >
> > I'm not sure if this description demonstrates that every possible race
> > is handled correctly. If I compare this with Nicolin's presentation in
> > arm_smmu_domain_inv_range, I like that presentation, as it explicitly
> > mentions loads and barriers. For example, it has an smp_mb() followed
> > by "// load the updated invs". I think you should make have something
> > like "smp_mb() ; CHECK STOP_FLAG" in your presentation. Currently, the
> > STOP_FLAG checking is somehow implicit in "Invalidation".
>
> Ack. The goal of this diagram was to explain the working of the design,
> this is NOT the comment/document I plan to include in code.
>
> I'll add this as an in-line comment if that's what you're suggesting? OR
> are you also suggesting I should have this in my cover letter?
In arm_smmu_domain_inv_range(), there's Nicolin's sequence diagram
that describes how installing a new domain is synchronized with PTE
updates and subsequent TLBIs. I would recommend adding a similar
diagram that shows how suspend and resume are synchronized with PTE
updates and TLBIs.
Thanks
Daniel
^ permalink raw reply
* Re: [PATCH v2] EDAC/synopsys: Fix cleanup on injection sysfs failure
From: Borislav Petkov @ 2026-06-10 17:27 UTC (permalink / raw)
To: Yuho Choi
Cc: Tony Luck, Michal Simek, linux-edac, linux-arm-kernel,
linux-kernel
In-Reply-To: <20260605125417.2348115-1-dbgh9129@gmail.com>
On Fri, Jun 05, 2026 at 08:54:17AM -0400, Yuho Choi wrote:
> edac_create_sysfs_attributes() creates inject_data_error before
> inject_data_poison. If the second file creation fails, the first file is
> left behind.
>
> The same failure path runs after edac_mc_add_mc() has registered the
> memory controller with the EDAC core. Jumping directly to edac_mc_free()
> skips edac_mc_del_mc() and leaves the registered controller state
> unwound incorrectly.
>
> Remove inject_data_error when inject_data_poison creation fails, and
> route the probe failure through edac_mc_del_mc() before freeing mci.
>
> Fixes: 1a81361f75d8 ("EDAC, synopsys: Add Error Injection support for ZynqMP DDR controller")
> Signed-off-by: Yuho Choi <dbgh9129@gmail.com>
> ---
> Changes in v2:
> - Remove the CONFIG_EDAC_DEBUG-guarded del_mc label.
> - Call edac_mc_del_mc() inline before jumping to free_edac_mc when
> edac_create_sysfs_attributes() fails.
>
> drivers/edac/synopsys_edac.c | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
https://sashiko.dev/#/patchset/20260605125417.2348115-1-dbgh9129%40gmail.com
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
^ permalink raw reply
* [PATCH v5] soc: aspeed: lpc-snoop: Fix usercopy overflow in snoop_file_read
From: Karthikeyan KS @ 2026-06-10 17:23 UTC (permalink / raw)
To: andrew
Cc: joel, andrew, Kees Cook, linux-arm-kernel, linux-aspeed,
linux-kernel, linux-hardening, Karthikeyan KS, stable
In-Reply-To: <033f2657ae6a94ad13d22f717a2900afb75d892d.camel@codeconstruct.com.au>
put_fifo_with_discard() acts as both producer and consumer on the kfifo:
it calls kfifo_skip() (advances out) and kfifo_put() (advances in) from
the IRQ handler without synchronizing with snoop_file_read(), which also
consumes via kfifo_to_user(). On SMP systems this concurrent access can
leave (in - out) larger than the ring buffer, so __kfifo_to_user()'s clamp
to (in - out) is ineffective and kfifo_copy_to_user() can attempt a
copy_to_user() past the kmalloc-2k backing store:
usercopy: Kernel memory exposure attempt detected from SLUB object
'kmalloc-2k' (offset 0, size 2049)!
kernel BUG at mm/usercopy.c!
Call trace:
usercopy_abort
__check_heap_object
__check_object_size
kfifo_copy_to_user
__kfifo_to_user
snoop_file_read
vfs_read
Serialize kfifo access with a per-channel spinlock. The reader drains
into a bounce buffer under the lock with kfifo_out_spinlocked() and then
copies to userspace after dropping it, since copy_to_user() may sleep on
a page fault.
Fixes: 3772e5da4454 ("drivers/misc: Aspeed LPC snoop output using misc chardev")
Cc: stable@vger.kernel.org
Signed-off-by: Karthikeyan KS <karthiproffesional@gmail.com>
---
Andrew,
Thanks for the review.
Changes since v4:
- Use __free(kfree) for automatic cleanup
- Allocate clamped count instead of full SNOOP_FIFO_SIZE
- Use kfifo_out_spinlocked() in snoop_file_read
- Use scoped_guard(spinlock) in put_fifo_with_discard
drivers/soc/aspeed/aspeed-lpc-snoop.c | 25 +++++++++++++++++++------
1 file changed, 19 insertions(+), 6 deletions(-)
diff --git a/drivers/soc/aspeed/aspeed-lpc-snoop.c b/drivers/soc/aspeed/aspeed-lpc-snoop.c
index b03310c0830d..c9c87a794228 100644
--- a/drivers/soc/aspeed/aspeed-lpc-snoop.c
+++ b/drivers/soc/aspeed/aspeed-lpc-snoop.c
@@ -11,6 +11,7 @@
*/
#include <linux/bitops.h>
+#include <linux/cleanup.h>
#include <linux/clk.h>
#include <linux/dev_printk.h>
#include <linux/interrupt.h>
@@ -74,6 +75,7 @@ struct aspeed_lpc_snoop_channel_cfg {
struct aspeed_lpc_snoop_channel {
const struct aspeed_lpc_snoop_channel_cfg *cfg;
bool enabled;
+ spinlock_t lock; /* serialises @fifo: irq producer vs reader */
struct kfifo fifo;
wait_queue_head_t wq;
struct miscdevice miscdev;
@@ -114,6 +116,7 @@ static ssize_t snoop_file_read(struct file *file, char __user *buffer,
size_t count, loff_t *ppos)
{
struct aspeed_lpc_snoop_channel *chan = snoop_file_to_chan(file);
+ u8 *buf __free(kfree) = NULL;
unsigned int copied;
int ret = 0;
@@ -125,9 +128,16 @@ static ssize_t snoop_file_read(struct file *file, char __user *buffer,
if (ret == -ERESTARTSYS)
return -EINTR;
}
- ret = kfifo_to_user(&chan->fifo, buffer, count, &copied);
- if (ret)
- return ret;
+
+ count = min_t(size_t, count, SNOOP_FIFO_SIZE);
+
+ buf = kmalloc(count, GFP_KERNEL);
+ if (!buf)
+ return -ENOMEM;
+
+ copied = kfifo_out_spinlocked(&chan->fifo, buf, count, &chan->lock);
+ if (copied && copy_to_user(buffer, buf, copied))
+ return -EFAULT;
return copied;
}
@@ -153,9 +163,11 @@ static void put_fifo_with_discard(struct aspeed_lpc_snoop_channel *chan, u8 val)
{
if (!kfifo_initialized(&chan->fifo))
return;
- if (kfifo_is_full(&chan->fifo))
- kfifo_skip(&chan->fifo);
- kfifo_put(&chan->fifo, val);
+ scoped_guard(spinlock, &chan->lock) {
+ if (kfifo_is_full(&chan->fifo))
+ kfifo_skip(&chan->fifo);
+ kfifo_put(&chan->fifo, val);
+ }
wake_up_interruptible(&chan->wq);
}
@@ -228,6 +240,7 @@ static int aspeed_lpc_enable_snoop(struct device *dev,
return -EBUSY;
init_waitqueue_head(&channel->wq);
+ spin_lock_init(&channel->lock);
channel->cfg = cfg;
channel->miscdev.minor = MISC_DYNAMIC_MINOR;
--
2.43.0
^ permalink raw reply related
* Re: [PATCH] Bluetooth: hci_bcm4377: Use named initializers for pci_device_id array
From: Luiz Augusto von Dentz @ 2026-06-10 17:13 UTC (permalink / raw)
To: Uwe Kleine-König (The Capable Hub)
Cc: Sven Peter, Janne Grunau, Neal Gompa, Marcel Holtmann,
Markus Schneider-Pargmann, asahi, linux-arm-kernel,
linux-bluetooth, linux-kernel
In-Reply-To: <aimXkX4FC4JVxt6q@monoceros>
Hi Uwe,
On Wed, Jun 10, 2026 at 12:59 PM Uwe Kleine-König (The Capable Hub)
<u.kleine-koenig@baylibre.com> wrote:
>
> On Mon, May 04, 2026 at 06:09:40PM +0200, Uwe Kleine-König (The Capable Hub) wrote:
> > Initializing a struct using list initializers is hard to read, compared
> > to that using named initializers is more ideomatic. Convert the macro
> > used to assign values in the driver's pci_device_id array accordingly.
> >
> > This change doesn't introduce any changes to the compiled array on an
> > x86 and an arm64 build.
> >
> > Signed-off-by: Uwe Kleine-König (The Capable Hub) <u.kleine-koenig@baylibre.com>
> > ---
> > Hello,
> >
> > this is a preparing change for making struct pci_device_id::driver_data an
> > anonymous union (similar to
> > https://lore.kernel.org/all/cover.1776579304.git.u.kleine-koenig@baylibre.com/).
> > This requires named initializers for .driver_data. But even without that
> > this is a nice cleanup making the macro better readable.
> >
> > Gcc is happy with simplifying the assignment further using
> > PCI_VDEVICE(BROADCOM, BCM ## id ## _DEVICE_ID), but this is a bit fishy
> > because PCI_VDEVICE also assigns .class and .class_mask (using list
> > initializers), so I didn't convert that.
>
> In the meantime I learned that doing that would break W=1 builds, so it
> was a good choice to not go that path.
>
> > Once all pci_device_id use
> > named initializers, the two zeros can be dropped from PCI_VDEVICE and
> > this entry simplified accordingly.
>
> Is this patch still on someone's radar? Ideally for application in time
> for 7.2-rc1?
It is no longer in patchwork so if you really want to get in please resend.
> Best regards
> Uwe
--
Luiz Augusto von Dentz
^ permalink raw reply
* Re: [PATCH] ARM: footbridge: convert to sparse IRQs
From: Dmitry Torokhov @ 2026-06-10 17:03 UTC (permalink / raw)
To: Ethan Nelson-Moore
Cc: Arnd Bergmann, linux-arm-kernel, linux-input, linux-serial,
Russell King, Greg Kroah-Hartman, Jiri Slaby, Russell King,
Linus Walleij, Kees Cook, Nathan Chancellor,
Sebastian Andrzej Siewior, Steven Rostedt, Thomas Weißschuh,
Peter Zijlstra
In-Reply-To: <CADkSEUhh1NdOMTHVsErhqzyCpDGFA-FkNFaWp94e9LnB3njxqw@mail.gmail.com>
On Mon, Jun 08, 2026 at 10:13:50AM -0700, Ethan Nelson-Moore wrote:
> Hi, Arnd,
>
> On Mon, Jun 8, 2026 at 10:11 AM Arnd Bergmann <arnd@arndb.de> wrote:
> > I think this is correct, as footbridge is the only one that selects
> > CONFIG_ARCH_MIGHT_HAVE_PC_SERIO and defines I8042_KBD_IRQ on arm.
>
> I came to the same conclusion.
I see. In this case:
Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> # for input
Thanks.
--
Dmitry
^ permalink raw reply
* Re: [PATCH] Bluetooth: hci_bcm4377: Use named initializers for pci_device_id array
From: Uwe Kleine-König (The Capable Hub) @ 2026-06-10 16:59 UTC (permalink / raw)
To: Sven Peter, Janne Grunau, Neal Gompa, Marcel Holtmann,
Luiz Augusto von Dentz
Cc: Markus Schneider-Pargmann, asahi, linux-arm-kernel,
linux-bluetooth, linux-kernel
In-Reply-To: <20260504160940.2168650-2-u.kleine-koenig@baylibre.com>
[-- Attachment #1: Type: text/plain, Size: 1473 bytes --]
On Mon, May 04, 2026 at 06:09:40PM +0200, Uwe Kleine-König (The Capable Hub) wrote:
> Initializing a struct using list initializers is hard to read, compared
> to that using named initializers is more ideomatic. Convert the macro
> used to assign values in the driver's pci_device_id array accordingly.
>
> This change doesn't introduce any changes to the compiled array on an
> x86 and an arm64 build.
>
> Signed-off-by: Uwe Kleine-König (The Capable Hub) <u.kleine-koenig@baylibre.com>
> ---
> Hello,
>
> this is a preparing change for making struct pci_device_id::driver_data an
> anonymous union (similar to
> https://lore.kernel.org/all/cover.1776579304.git.u.kleine-koenig@baylibre.com/).
> This requires named initializers for .driver_data. But even without that
> this is a nice cleanup making the macro better readable.
>
> Gcc is happy with simplifying the assignment further using
> PCI_VDEVICE(BROADCOM, BCM ## id ## _DEVICE_ID), but this is a bit fishy
> because PCI_VDEVICE also assigns .class and .class_mask (using list
> initializers), so I didn't convert that.
In the meantime I learned that doing that would break W=1 builds, so it
was a good choice to not go that path.
> Once all pci_device_id use
> named initializers, the two zeros can be dropped from PCI_VDEVICE and
> this entry simplified accordingly.
Is this patch still on someone's radar? Ideally for application in time
for 7.2-rc1?
Best regards
Uwe
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply
* [PATCH v3] arm64: errata: Workaround NVIDIA Olympus device store/load ordering erratum
From: Shanker Donthineni @ 2026-06-10 16:48 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Vladimir Murzin
Cc: Jason Gunthorpe, linux-arm-kernel, Mark Rutland, linux-kernel,
linux-doc, Shanker Donthineni, Vikram Sethi, Jason Sequeira
On systems with NVIDIA Olympus cores, a Device-nGnR* load can be
observed by a peripheral before an older, non-overlapping Device-nGnR*
store to the same peripheral. This breaks the program-order guarantee
that software expects for Device-nGnR* accesses and can leave a
peripheral in an incorrect state, as a load is observed before an
earlier store takes effect.
The erratum can occur only when all of the following apply:
- A PE executes a Device-nGnR* store followed by a younger
Device-nGnR* load.
- The store is not a store-release.
- The accesses target the same peripheral and do not overlap in bytes.
- There is at most one intervening Device-nGnR* store in program
order, and there are no intervening Device-nGnR* loads.
- There is no DSB, and no DMB that orders loads, between the store and
the load.
- Specific micro-architectural and timing conditions occur.
Promote the raw MMIO store helpers (__raw_writeb/w/l/q) from plain str*
to stlr* (Store-Release), which removes the "store is not a
store-release" condition for every device write the kernel issues.
Because writel() and writel_relaxed() are both built on __raw_writel()
in asm-generic/io.h, patching the raw variants covers both the
non-relaxed and relaxed APIs without touching the higher layers. Note
that writel()'s own barrier sits before the store, so it does not order
the store against a subsequent readl(); the store-release promotion is
what provides that ordering.
Like ARM64_ERRATUM_832075 on the load side, the change is gated on a new
ARM64_WORKAROUND_DEVICE_STORE_RELEASE capability and only activated on
parts that match MIDR_NVIDIA_OLYMPUS, so unaffected CPUs continue to use
the plain str* sequence.
Note: stlr* only supports base-register addressing, so affected CPUs use
a base-register stlr* path. Unaffected CPUs keep the original
offset-addressed str* sequence introduced by commit d044d6ba6f02
("arm64: io: permit offset addressing").
The __const_memcpy_toio_aligned32() and __const_memcpy_toio_aligned64()
helpers are left unchanged. These helpers are intended for
write-combining mappings, which are Normal-NC on arm64. Replacing their
contiguous str* groups would defeat the write-combining behavior used to
improve store performance.
Co-developed-by: Vikram Sethi <vsethi@nvidia.com>
Signed-off-by: Vikram Sethi <vsethi@nvidia.com>
Signed-off-by: Shanker Donthineni <sdonthineni@nvidia.com>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
---
Changes since v2:
- Reworked the raw MMIO write helpers so unaffected CPUs keep the
existing offset-addressed STR sequence, while affected CPUs use the
base-register STLR path.
- Updated the commit message to match the code changes.
- Rebased on top of the arm64 for-next/errata branch:
https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux.git/log/?h=for-next/errata
Changes since v1:
- Updated the commit message based on feedback from Vladimir Murzin.
Documentation/arch/arm64/silicon-errata.rst | 2 ++
arch/arm64/Kconfig | 23 ++++++++++++++++
arch/arm64/include/asm/io.h | 30 +++++++++++++++++++++
arch/arm64/kernel/cpu_errata.c | 8 ++++++
arch/arm64/tools/cpucaps | 1 +
5 files changed, 64 insertions(+)
diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst
index ad09bbb10da80..fc45125dc2f80 100644
--- a/Documentation/arch/arm64/silicon-errata.rst
+++ b/Documentation/arch/arm64/silicon-errata.rst
@@ -298,6 +298,8 @@ stable kernels.
+----------------+-----------------+-----------------+-----------------------------+
| NVIDIA | Carmel Core | N/A | NVIDIA_CARMEL_CNP_ERRATUM |
+----------------+-----------------+-----------------+-----------------------------+
+| NVIDIA | Olympus core | T410-OLY-1027 | NVIDIA_OLYMPUS_1027_ERRATUM |
++----------------+-----------------+-----------------+-----------------------------+
| NVIDIA | Olympus core | T410-OLY-1029 | ARM64_ERRATUM_4118414 |
+----------------+-----------------+-----------------+-----------------------------+
| NVIDIA | T241 GICv3/4.x | T241-FABRIC-4 | N/A |
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index c65cef81be86a..d633eb70de1ac 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -564,6 +564,29 @@ config ARM64_ERRATUM_832075
If unsure, say Y.
+config NVIDIA_OLYMPUS_1027_ERRATUM
+ bool "NVIDIA Olympus: device store/load ordering erratum"
+ default y
+ help
+ This option adds an alternative code sequence to work around an
+ NVIDIA Olympus core erratum where a Device-nGnR* store can be
+ observed by a peripheral after a younger Device-nGnR* load to the
+ same peripheral. This breaks the program order that drivers rely
+ on for MMIO and can leave a device in an incorrect state.
+
+ The workaround promotes the raw MMIO store helpers
+ (__raw_writeb/w/l/q) to Store-Release (STLR), which restores the
+ required ordering. Because writel() and writel_relaxed() are built
+ on __raw_writel(), both are covered without changes to the higher
+ layers.
+
+ The fix is applied through the alternatives framework, so enabling
+ this option does not by itself activate the workaround: it is
+ patched in only when an affected CPU is detected, and is a no-op on
+ unaffected CPUs.
+
+ If unsure, say Y.
+
config ARM64_ERRATUM_834220
bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault (rare)"
depends on KVM
diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h
index 8cbd1e96fd50b..801223e754c90 100644
--- a/arch/arm64/include/asm/io.h
+++ b/arch/arm64/include/asm/io.h
@@ -22,10 +22,22 @@
/*
* Generic IO read/write. These perform native-endian accesses.
*/
+static __always_inline bool arm64_needs_device_store_release(void)
+{
+ return alternative_has_cap_unlikely(
+ ARM64_WORKAROUND_DEVICE_STORE_RELEASE);
+}
+
#define __raw_writeb __raw_writeb
static __always_inline void __raw_writeb(u8 val, volatile void __iomem *addr)
{
volatile u8 __iomem *ptr = addr;
+
+ if (arm64_needs_device_store_release()) {
+ asm volatile("stlrb %w0, [%1]" : : "rZ" (val), "r" (addr));
+ return;
+ }
+
asm volatile("strb %w0, %1" : : "rZ" (val), "Qo" (*ptr));
}
@@ -33,6 +45,12 @@ static __always_inline void __raw_writeb(u8 val, volatile void __iomem *addr)
static __always_inline void __raw_writew(u16 val, volatile void __iomem *addr)
{
volatile u16 __iomem *ptr = addr;
+
+ if (arm64_needs_device_store_release()) {
+ asm volatile("stlrh %w0, [%1]" : : "rZ" (val), "r" (addr));
+ return;
+ }
+
asm volatile("strh %w0, %1" : : "rZ" (val), "Qo" (*ptr));
}
@@ -40,6 +58,12 @@ static __always_inline void __raw_writew(u16 val, volatile void __iomem *addr)
static __always_inline void __raw_writel(u32 val, volatile void __iomem *addr)
{
volatile u32 __iomem *ptr = addr;
+
+ if (arm64_needs_device_store_release()) {
+ asm volatile("stlr %w0, [%1]" : : "rZ" (val), "r" (addr));
+ return;
+ }
+
asm volatile("str %w0, %1" : : "rZ" (val), "Qo" (*ptr));
}
@@ -47,6 +71,12 @@ static __always_inline void __raw_writel(u32 val, volatile void __iomem *addr)
static __always_inline void __raw_writeq(u64 val, volatile void __iomem *addr)
{
volatile u64 __iomem *ptr = addr;
+
+ if (arm64_needs_device_store_release()) {
+ asm volatile("stlr %x0, [%1]" : : "rZ" (val), "r" (addr));
+ return;
+ }
+
asm volatile("str %x0, %1" : : "rZ" (val), "Qo" (*ptr));
}
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index d597896b0f7f3..b096d9acca578 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -838,6 +838,14 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
ERRATA_MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL),
},
#endif
+#ifdef CONFIG_NVIDIA_OLYMPUS_1027_ERRATUM
+ {
+ /* NVIDIA Olympus core */
+ .desc = "NVIDIA Olympus device load/store ordering erratum",
+ .capability = ARM64_WORKAROUND_DEVICE_STORE_RELEASE,
+ ERRATA_MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS),
+ },
+#endif
#ifdef CONFIG_ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
{
/*
diff --git a/arch/arm64/tools/cpucaps b/arch/arm64/tools/cpucaps
index 811c2479e82d6..d367257bf7703 100644
--- a/arch/arm64/tools/cpucaps
+++ b/arch/arm64/tools/cpucaps
@@ -120,6 +120,7 @@ WORKAROUND_CAVIUM_TX2_219_PRFM
WORKAROUND_CAVIUM_TX2_219_TVM
WORKAROUND_CLEAN_CACHE
WORKAROUND_DEVICE_LOAD_ACQUIRE
+WORKAROUND_DEVICE_STORE_RELEASE
WORKAROUND_NVIDIA_CARMEL_CNP
WORKAROUND_PMUV3_IMPDEF_TRAPS
WORKAROUND_QCOM_FALKOR_E1003
--
2.43.0
^ permalink raw reply related
* Re: [PATCH 2/2] ufs: mediatek: Implement get_hba_nortt callback for RTT capability
From: Bart Van Assche @ 2026-06-10 16:46 UTC (permalink / raw)
To: ed.tsai, alim.akhtar, avri.altman, James.Bottomley,
martin.petersen, linux-scsi
Cc: linux-kernel, linux-arm-kernel, linux-mediatek, wsd_upstream,
peter.wang, alice.chao, naomi.chu, chun-hung.wu
In-Reply-To: <20260609103856.676222-3-ed.tsai@mediatek.com>
On 6/9/26 3:38 AM, ed.tsai@mediatek.com wrote:
> Implement the get_hba_nortt callback to handle platform-specific RTT
> capability differences:
Reviewed-by: Bart Van Assche <bvanassche@acm.org>
^ permalink raw reply
* Re: [PATCH 1/2] ufs: core: Add get_hba_nortt callback for vendor-specific RTT capability
From: Bart Van Assche @ 2026-06-10 16:46 UTC (permalink / raw)
To: ed.tsai, alim.akhtar, avri.altman, James.Bottomley,
martin.petersen, linux-scsi
Cc: linux-kernel, linux-arm-kernel, linux-mediatek, wsd_upstream,
peter.wang, alice.chao, naomi.chu, chun-hung.wu
In-Reply-To: <20260609103856.676222-2-ed.tsai@mediatek.com>
On 6/9/26 3:38 AM, ed.tsai@mediatek.com wrote:
> diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h
> index cfbc75d8df83..13d0d7798294 100644
> --- a/include/ufs/ufshcd.h
> +++ b/include/ufs/ufshcd.h
> @@ -370,7 +370,6 @@ struct ufshcd_tx_eq_params {
> /**
> * struct ufs_hba_variant_ops - variant specific callbacks
> * @name: variant name
> - * @max_num_rtt: maximum RTT supported by the host
> * @init: called when the driver is initialized
> * @exit: called to cleanup everything done in init
> * @set_dma_mask: For setting another DMA mask than indicated by the 64AS
> @@ -415,10 +414,11 @@ struct ufshcd_tx_eq_params {
> * @get_rx_fom: called to get Figure of Merit (FOM) value.
> * @tx_eqtr_notify: called before and after TX Equalization Training procedure
> * to allow platform vendor specific configs to take place.
> + * @get_hba_nortt: called to get maximum number of outstanding RTTs supported by
> + * the controller.
> */
> struct ufs_hba_variant_ops {
> const char *name;
> - int max_num_rtt;
> int (*init)(struct ufs_hba *);
> void (*exit)(struct ufs_hba *);
> u32 (*get_ufs_hci_version)(struct ufs_hba *);
> @@ -477,6 +477,7 @@ struct ufs_hba_variant_ops {
> int (*tx_eqtr_notify)(struct ufs_hba *hba,
> enum ufs_notify_change_status status,
> struct ufs_pa_layer_attr *pwr_mode);
> + int (*get_hba_nortt)(struct ufs_hba *hba);
> };
A patch series should be bisectable. Removing max_num_rtt from struct
ufs_hba_variant_ops before the code is removed from the MediaTek driver
that sets that variable introduces a build break. Please keep
'max_num_rtt' in this patch and add a third patch to this series that
removes 'max_num_rtt'.
Thanks,
Bart.
^ permalink raw reply
* Re: [PATCH v2 1/2] dt-bindings: arm: rockchip: Add HINLINK H28K
From: Conor Dooley @ 2026-06-10 16:43 UTC (permalink / raw)
To: Chukun Pan
Cc: Heiko Stuebner, Rob Herring, Conor Dooley, Krzysztof Kozlowski,
linux-arm-kernel, linux-rockchip, linux-kernel, devicetree
In-Reply-To: <20260610100006.366963-2-amadeus@jmu.edu.cn>
[-- Attachment #1: Type: text/plain, Size: 75 bytes --]
Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply
* Re: [PATCH v6 04/20] dma-pool: track decrypted atomic pools and select them via attrs
From: Jason Gunthorpe @ 2026-06-10 16:41 UTC (permalink / raw)
To: Aneesh Kumar K.V
Cc: iommu, linux-arm-kernel, linux-kernel, linux-coco, Robin Murphy,
Marek Szyprowski, Will Deacon, Marc Zyngier, Steven Price,
Suzuki K Poulose, Catalin Marinas, Jiri Pirko, Mostafa Saleh,
Petr Tesarik, Alexey Kardashevskiy, Dan Williams, Xu Yilun,
linuxppc-dev, linux-s390, Madhavan Srinivasan, Michael Ellerman,
Nicholas Piggin, Christophe Leroy (CS GROUP), Alexander Gordeev,
Gerald Schaefer, Heiko Carstens, Vasily Gorbik,
Christian Borntraeger, Sven Schnelle, x86, Jiri Pirko,
Michael Kelley
In-Reply-To: <yq5afr2uzum9.fsf@kernel.org>
On Wed, Jun 10, 2026 at 01:37:26PM +0530, Aneesh Kumar K.V wrote:
> Jason Gunthorpe <jgg@ziepe.ca> writes:
>
> > On Thu, Jun 04, 2026 at 02:09:43PM +0530, Aneesh Kumar K.V (Arm) wrote:
> >> struct page *dma_alloc_from_pool(struct device *dev, size_t size,
> >> - void **cpu_addr, gfp_t gfp,
> >> + void **cpu_addr, gfp_t gfp, unsigned long attrs,
> >> bool (*phys_addr_ok)(struct device *, phys_addr_t, size_t))
> >> {
> >> - struct gen_pool *pool = NULL;
> >> + struct dma_gen_pool *dma_pool = NULL;
> >> struct page *page;
> >> bool pool_found = false;
> >>
> >> - while ((pool = dma_guess_pool(pool, gfp))) {
> >> + while ((dma_pool = dma_guess_pool(dma_pool, gfp))) {
> >> +
> >> + if (dma_pool->unencrypted != !!(attrs & DMA_ATTR_CC_SHARED))
> >> + continue;
> >
> > I don't think you should be overloading DMA_ATTR_CC_SHARED like this.
> >
> > /*
> > * DMA_ATTR_CC_SHARED is not a caller-visible dma_alloc_*()
> > * attribute. The direct allocator uses it internally after it has
> > * decided that the backing pages must be shared/decrypted, so the
> > * rest of the allocation path can consistently select DMA addresses,
> > * choose compatible pools and restore encryption on free.
> > */
> > if (attrs & DMA_ATTR_CC_SHARED)
> > return NULL;
> >
> > if (force_dma_unencrypted(dev)) {
> > attrs |= DMA_ATTR_CC_SHARED;
> > mark_mem_decrypt = true;
> > }
> >
> > It is fine to have a bit inside the attrs that is only used by the
> > internal logic, but it needs to have a clearer name
> > __DMA_ATTR_REQUIRE_CC_SHARED perhaps.
> >
>
> Are you suggesting adding another attribute in addition to
> DMA_ATTR_CC_SHARED?
>
> Is the idea that __DMA_ATTR_REQUIRE_CC_SHARED would be used in the
> allocation path to request a CC_SHARED allocation, while
> DMA_ATTR_CC_SHARED would be used in the mapping path to describe the
> attribute of the address?
Yeah, it is a thought at least
Maybe a comment is good enough.
I just find it hard to follow when we have this dual usage. Like the
code above for dma_pool->unencrypted is completely wrong if it is an
"attribute of an address". Easy to cut & paste that into the wrong
context.
Especially if you move things up higher.. having the alloc set both
CC_SHARED and REQUIRE_CC_SHARED or maybe ALLOC_CC_SHARED would make it
clearer that the alloc code lives under that callchain
Jason
^ permalink raw reply
* Re: [PATCH] KVM: arm64: Hold kvm->mmu_lock while initialising vcpu->arch.vncr_tlb
From: Yosry Ahmed @ 2026-06-10 16:39 UTC (permalink / raw)
To: Marc Zyngier
Cc: kvmarm, kvm, linux-arm-kernel, Steffen Eiden, Joey Gouly,
Suzuki K Poulose, Oliver Upton, Zenghui Yu
In-Reply-To: <868q8mu0hr.wl-maz@kernel.org>
On Wed, Jun 10, 2026 at 3:57 AM Marc Zyngier <maz@kernel.org> wrote:
>
> On Tue, 09 Jun 2026 18:57:26 +0100,
> Yosry Ahmed <yosry@kernel.org> wrote:
> >
> > > > If yes, I think the code looks confusing, at least to a layman like
> > > > myself. It initially seems like the lock protects against concurrent
> > > > initializations, but then the NULL check is not done again under the
> > > > lock. The goal of the lock is not clear without the original report.
> > > >
> > > > Mayeb it's clearer to explicitly use barriers if the goal is preventing
> > > > reordering?
> > >
> > > This would require both the initialisation of vncr_tlb to use a store
> > > release, *and* all the other call sites to use a load acquire.
> > >
> > > I really don't think it is worth the churn, nor the (very small)
> > > burden on the readers.
> >
> > That's fair. I was mainly just pointing out my initial confusion and
> > that others may share it. Avoiding the churn on the readers' side is
> > understandable. Maybe a comment here would help explain why the lock
> > needs to be held?
>
> I have added this:
>
> /*
> * Taking the lock on assignment ensures that the TLB is
> * seen as initialised when following the pointer (release
> * semantics of the unlock), and avoids having acquires on
> * each user which already take the lock.
> */
Looks good, thank you!
^ permalink raw reply
* Re: [PATCH 2/3] dt-bindings: arm: rockchip: Add Youyeetoo YY3588
From: Conor Dooley @ 2026-06-10 16:33 UTC (permalink / raw)
To: Daniele Briguglio
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner,
devicetree, linux-kernel, linux-arm-kernel, linux-rockchip
In-Reply-To: <20260610-yy3588-board-v1-2-4bb7176b6826@superkali.me>
[-- Attachment #1: Type: text/plain, Size: 75 bytes --]
Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply
* Re: [PATCH 1/3] dt-bindings: vendor-prefixes: Add youyeetoo
From: Conor Dooley @ 2026-06-10 16:33 UTC (permalink / raw)
To: Daniele Briguglio
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner,
devicetree, linux-kernel, linux-arm-kernel, linux-rockchip
In-Reply-To: <20260610-yy3588-board-v1-1-4bb7176b6826@superkali.me>
[-- Attachment #1: Type: text/plain, Size: 75 bytes --]
Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply
* Re: [PATCH] ASoC: meson: axg-tdm-formatter: Use guard() for mutex locks
From: Bui Duc Phuc @ 2026-06-10 16:27 UTC (permalink / raw)
To: Jerome Brunet
Cc: Mark Brown, Liam Girdwood, Neil Armstrong, Kevin Hilman,
Martin Blumenstingl, Jaroslav Kysela, Takashi Iwai, linux-sound,
linux-arm-kernel, linux-amlogic, linux-kernel
In-Reply-To: <1j8q8mfte7.fsf@starbuckisacylon.baylibre.com>
Hi Jerome,
Thank you for your feedback,
>
> I suppose it is OK but it does not seem to really clean anything and
> make the code easier to follow in that instance, from my perspective at
> least.
>
> If there is policy to systematically use guard() whenever
> possible then OK, otherwise it seems unnecessary.
>
I have noticed that guard() has been adopted in several subsystems.
Since this appears to be the only place in the Meson ASoC code currently using
mutex_lock()/mutex_unlock(), I converted it for consistency with the
newer style.
Going forward, should new Meson ASoC code use guard(), or should it continue
using the traditional mutex_lock()/mutex_unlock() pattern?
Best regards,
Phuc
^ permalink raw reply
* [PATCH 5.10] spi: meson-spicc: Fix double-put in remove path
From: Alexey Panov @ 2026-06-10 16:11 UTC (permalink / raw)
To: stable, Greg Kroah-Hartman
Cc: Alexey Panov, Mark Brown, Kevin Hilman, Neil Armstrong,
Jerome Brunet, Martin Blumenstingl, Dongliang Mu, linux-spi,
linux-arm-kernel, linux-amlogic, linux-kernel, Neil Armstrong,
lvc-project, Felix Gu, Johan Hovold
From: Felix Gu <ustc.gu@gmail.com>
commit 63542bb402b7013171c9f621c28b609eda4dbf1f upstream.
meson_spicc_probe() registers the controller with
devm_spi_register_controller(), so teardown already drops the
controller reference via devm cleanup.
Calling spi_controller_put() again in meson_spicc_remove()
causes a double-put.
Fixes: 8311ee2164c5 ("spi: meson-spicc: fix memory leak in meson_spicc_remove")
Signed-off-by: Felix Gu <ustc.gu@gmail.com>
Reviewed-by: Johan Hovold <johan@kernel.org>
Link: https://patch.msgid.link/20260322-rockchip-v1-1-fac3f0c6dad8@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
[ Alexey: Remove the equivalent legacy spi_master_put() call used in
linux-5.10.y. ]
Signed-off-by: Alexey Panov <apanov@astralinux.ru>
---
Backport fix for CVE-2026-31489
drivers/spi/spi-meson-spicc.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/spi/spi-meson-spicc.c b/drivers/spi/spi-meson-spicc.c
index 6974a1c947aa..ae818e7df791 100644
--- a/drivers/spi/spi-meson-spicc.c
+++ b/drivers/spi/spi-meson-spicc.c
@@ -863,8 +863,6 @@ static int meson_spicc_remove(struct platform_device *pdev)
clk_disable_unprepare(spicc->core);
clk_disable_unprepare(spicc->pclk);
- spi_master_put(spicc->master);
-
return 0;
}
--
2.47.3
^ permalink raw reply related
* Re: [PATCH v2] arm64: errata: Workaround NVIDIA Olympus device store/load ordering erratum
From: Jason Gunthorpe @ 2026-06-10 16:11 UTC (permalink / raw)
To: Shanker Donthineni
Cc: Will Deacon, Catalin Marinas, linux-arm-kernel, Vladimir Murzin,
Mark Rutland, linux-kernel, linux-doc, Vikram Sethi,
Jason Sequeira
In-Reply-To: <223c49ee-528c-4750-9885-fd8e0247151e@nvidia.com>
On Wed, Jun 10, 2026 at 08:20:28AM -0500, Shanker Donthineni wrote:
> Based on the existing code comments and after reviewing this path again,
> __const_memcpy_toio_aligned32() and __const_memcpy_toio_aligned64()
> appear to be intended for WC regions. Since the erratum is scoped to
> Device-nGnR* accesses, and WC mappings are Normal-NC on arm64, I don’t
> think the STLR workaround should apply to these helpers by default.
Hmm, unfortunately I think the APIs mix together IO and WC both as
__iomem things. However I recall when I was looking a this everyone
was using it for WC.
Jason
^ permalink raw reply
* Re: [PATCH] KVM: arm64: vgic: Check the interrupt is still ours before migrating it
From: Marc Zyngier @ 2026-06-10 16:00 UTC (permalink / raw)
To: Hyunwoo Kim
Cc: Oliver Upton, joey.gouly, seiden, suzuki.poulose, yuzenghui,
catalin.marinas, will, Sascha.Bischoff, jic23, timothy.hayes,
andre.przywara, linux-arm-kernel, kvmarm
In-Reply-To: <ailsCnyoS82r_QRz@v4bel>
On Wed, 10 Jun 2026 14:52:10 +0100,
Hyunwoo Kim <imv4bel@gmail.com> wrote:
>
> On Fri, Jun 05, 2026 at 01:43:32AM -0700, Oliver Upton wrote:
> > On Fri, Jun 05, 2026 at 08:42:52AM +0100, Marc Zyngier wrote:
> > > On Fri, 05 Jun 2026 07:00:37 +0100,
> > > Oliver Upton <oupton@kernel.org> wrote:
> > > >
> > > > On Fri, Jun 05, 2026 at 05:59:15AM +0900, Hyunwoo Kim wrote:
> > > > > vgic_prune_ap_list() drops both ap_list_lock and irq_lock while migrating
> > > > > an interrupt to another vCPU. After reacquiring the locks it only checks
> > > > > that the affinity is unchanged (target_vcpu == vgic_target_oracle(irq))
> > > > > before moving the interrupt, which assumes that an interrupt whose affinity
> > > > > is preserved is still queued on this vCPU's ap_list.
> > > > >
> > > > > That assumption no longer holds if the interrupt is taken off the ap_list
> > > > > while the locks are dropped. vgic_flush_pending_lpis() removes the
> > > > > interrupt from the list and sets irq->vcpu to NULL, but leaves
> > > > > enabled/pending/target_vcpu untouched. As the interrupt is still enabled
> > > > > and pending, vgic_target_oracle() returns the same target_vcpu, so the
> > > > > affinity check passes and list_del() is run a second time on an entry that
> > > > > has already been removed.
> > > > >
> > > > > Also check that the interrupt is still assigned to this vCPU
> > > > > (irq->vcpu == vcpu) before moving it.
> > > > >
> > > > > Fixes: 0919e84c0fc1 ("KVM: arm/arm64: vgic-new: Add IRQ sync/flush framework")
> > > > > Signed-off-by: Hyunwoo Kim <imv4bel@gmail.com>
> > > >
> > > > Looking at this and the other VGIC patch you sent (which should've been
> > > > a combined series), are you trying to deal with a vCPU writing to
> > > > another vCPU's redistributor? I.e. vCPU B setting GICR_CTLR.EnableLPIs=0
> > > > behind the back of vCPU A?
> > > >
> > > > That is extremely relevant information as the off-the-cuff reaction is
> > > > that no race exists. But since the GIC architecture is awesome and
> > > > allows for this sort of insanity, it obviously does....
> > > >
> > > > Anyway, for LPIs resident on a particular RD, there's zero expectation
> > > > that the pending state is preserved when EnableLPIs=0. So I'd rather
> > > > vgic_flush_pending_lpis() just invalidate the pending state.
> > >
> > > Just clearing the pending state introduces a potential problem as we
> > > now have an interrupt that is neither active nor pending on the AP
> > > list. It is not impossible to solve (we now have similar behaviours
> > > with SPI deactivation from another vcpu), but that requires posting a
> > > KVM_REQ_VGIC_PROCESS_UPDATE to the target vcpu.
> >
> > Right, I was suggesting that in addition to deleting the LPI from the AP
> > list we actually invalidate the pending state so that someone sitting on
> > a pointer to a to-be-freed LPI sees vgic_target_oracle() returning
> > NULL
> >
> > > > Beyond that, I see two other fixes for lifetime issues around the
> > > > vgic_irq in the middle of migration. I'd like to see explicit RCU
> > > > protection around the release && reacquire of the ap_list_lock rather
> > > > than depending on the precondition that IRQs are disabled.
> > >
> > > I'm not sure I follow. Are you suggesting turning the AP list into an
> > > RCU protected list?
> >
> > No, sorry, I should expand a little.
> >
> > We store a reference on the vgic_irq struct in the AP list, which is
> > stable so long as the ap_list_lock is held. It should be possible for
> > the refcount to drop to 0 between releasing the ap_list_lock and
> > reacquiring it.
> >
> > So either vgic_prune_ap_list() takes an additional reference on the
> > vgic_irq before dropping the ap_list_lock or rely on RCU to protect
> > vgic_irq structs observed with a non-zero refcount.
>
> What are your thoughts on this approach?
>
>
> Best regards,
> Hyunwoo Kim
>
> ---
>
> diff --git a/arch/arm64/kvm/vgic/vgic-init.c b/arch/arm64/kvm/vgic/vgic-init.c
> index 933983bb2005..7fb871c3ccd8 100644
> --- a/arch/arm64/kvm/vgic/vgic-init.c
> +++ b/arch/arm64/kvm/vgic/vgic-init.c
> @@ -523,7 +523,7 @@ static void __kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu)
> * Retire all pending LPIs on this vcpu anyway as we're
> * going to destroy it.
> */
> - vgic_flush_pending_lpis(vcpu);
> + vgic_flush_pending_lpis(vcpu, true);
>
> INIT_LIST_HEAD(&vgic_cpu->ap_list_head);
> kfree(vgic_cpu->private_irqs);
> diff --git a/arch/arm64/kvm/vgic/vgic-mmio-v3.c b/arch/arm64/kvm/vgic/vgic-mmio-v3.c
> index 5913a20d8301..f85d63f17af0 100644
> --- a/arch/arm64/kvm/vgic/vgic-mmio-v3.c
> +++ b/arch/arm64/kvm/vgic/vgic-mmio-v3.c
> @@ -303,7 +303,7 @@ static void vgic_mmio_write_v3r_ctlr(struct kvm_vcpu *vcpu,
> if (ctlr != GICR_CTLR_ENABLE_LPIS)
> return;
>
> - vgic_flush_pending_lpis(vcpu);
> + vgic_flush_pending_lpis(vcpu, false);
> vgic_its_invalidate_all_caches(vcpu->kvm);
> atomic_set_release(&vgic_cpu->ctlr, 0);
> } else {
> diff --git a/arch/arm64/kvm/vgic/vgic.c b/arch/arm64/kvm/vgic/vgic.c
> index 1e9fe8764584..09629a38fc0a 100644
> --- a/arch/arm64/kvm/vgic/vgic.c
> +++ b/arch/arm64/kvm/vgic/vgic.c
> @@ -192,7 +192,7 @@ static void vgic_release_deleted_lpis(struct kvm *kvm)
> xa_unlock_irqrestore(&dist->lpi_xa, flags);
> }
>
> -void vgic_flush_pending_lpis(struct kvm_vcpu *vcpu)
> +void vgic_flush_pending_lpis(struct kvm_vcpu *vcpu, bool destroy)
> {
> struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu;
> struct vgic_irq *irq, *tmp;
> @@ -204,6 +204,13 @@ void vgic_flush_pending_lpis(struct kvm_vcpu *vcpu)
> list_for_each_entry_safe(irq, tmp, &vgic_cpu->ap_list_head, ap_list) {
> if (irq_is_lpi(vcpu->kvm, irq->intid)) {
> raw_spin_lock(&irq->irq_lock);
> + /* Leave interrupts pending a migration for prune. */
> + if (!destroy && irq->vcpu != vgic_target_oracle(irq)) {
> + raw_spin_unlock(&irq->irq_lock);
> + continue;
> + }
It's rather unclear to me what the semantics of this are.
If vcpu-a decides to nuke the LPIs of vcpu-b and the LPI had in the
meantime been migrated to vcpu-c, but obviously not observed by vcpu-c
yet as the LPI is still on vcpu-b's AP-list, then I don't see the
point in keeping this state.
Am I missing something obvious?
> + /* Pending state is not preserved across EnableLPIs=0. */
> + irq->pending_latch = false;
That part I agree with.
> list_del(&irq->ap_list);
> irq->vcpu = NULL;
> raw_spin_unlock(&irq->irq_lock);
> @@ -797,6 +804,9 @@ static void vgic_prune_ap_list(struct kvm_vcpu *vcpu)
>
> /* This interrupt looks like it has to be migrated. */
>
> + /* Keep the interrupt alive while the locks are dropped. */
> + vgic_get_irq_ref(irq);
> +
> raw_spin_unlock(&irq->irq_lock);
> raw_spin_unlock(&vgic_cpu->ap_list_lock);
>
> @@ -839,6 +849,8 @@ static void vgic_prune_ap_list(struct kvm_vcpu *vcpu)
> raw_spin_unlock(&vcpuB->arch.vgic_cpu.ap_list_lock);
> raw_spin_unlock(&vcpuA->arch.vgic_cpu.ap_list_lock);
>
> + deleted_lpis |= vgic_put_irq_norelease(vcpu->kvm, irq);
> +
> if (target_vcpu_needs_kick) {
> kvm_make_request(KVM_REQ_IRQ_PENDING, target_vcpu);
> kvm_vcpu_kick(target_vcpu);
> diff --git a/arch/arm64/kvm/vgic/vgic.h b/arch/arm64/kvm/vgic/vgic.h
> index 9d941241c8a2..c1ac24ede899 100644
> --- a/arch/arm64/kvm/vgic/vgic.h
> +++ b/arch/arm64/kvm/vgic/vgic.h
> @@ -341,7 +341,7 @@ void vgic_v3_put(struct kvm_vcpu *vcpu);
> bool vgic_has_its(struct kvm *kvm);
> int kvm_vgic_register_its_device(void);
> void vgic_enable_lpis(struct kvm_vcpu *vcpu);
> -void vgic_flush_pending_lpis(struct kvm_vcpu *vcpu);
> +void vgic_flush_pending_lpis(struct kvm_vcpu *vcpu, bool destroy);
> int vgic_its_inject_msi(struct kvm *kvm, struct kvm_msi *msi);
> int vgic_v3_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr);
> int vgic_v3_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
>
I reckon this would work just as well with just the pending state
being removed in vgic_flush_pending_lpis(), and the reference holding
hack in gvgic_prune_ap_list().
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
^ permalink raw reply
* ❌ FAIL: Test report for for-kernelci (7.1.0-rc7, upstream-arm-next, 596d152b)
From: cki-project @ 2026-06-10 15:52 UTC (permalink / raw)
To: catalin.marinas, will, yoyang, linux-arm-kernel
Hi, we tested your kernel and here are the results:
Overall result: FAILED
Merge: OK
Compile: OK
Test: FAILED
Kernel information:
Commit message: Merge branch 'for-next/core' into for-kernelci
You can find all the details about the test run at
https://datawarehouse.cki-project.org/kcidb/checkouts/redhat:2591239284
One or more kernel tests failed:
Unrecognized or new issues:
xfstests - btrfs
aarch64
Logs: https://datawarehouse.cki-project.org/kcidb/tests/redhat:2591239284_aarch64_kernel_kcidb_tool_21441185_9
Non-passing ran subtests:
❌ FAIL generic/301
We also see the following known issues which are not related to your changes:
Issue: [upstream] Hardware - Firmware test suite - auto-waive failures
URL: https://gitlab.com/cki-project/infrastructure/-/issues/779
Affected tests:
Hardware - Firmware test suite [aarch64]
If you find a failure unrelated to your changes, please ask the test maintainer to review it.
This will prevent the failures from being incorrectly reported in the future.
Please reply to this email if you have any questions about the tests that we
ran or if you have any suggestions on how to make future tests more effective.
,-. ,-.
( C ) ( K ) Continuous
`-',-.`-' Kernel
( I ) Integration
`-'
______________________________________________________________________________
^ permalink raw reply
* [PATCH v2 4/9] media: Add tgid and fd to the v4l2-requests trace fields
From: Detlev Casanova @ 2026-06-10 14:33 UTC (permalink / raw)
To: Daniel Almeida, Mauro Carvalho Chehab, Steven Rostedt,
Masami Hiramatsu, Mathieu Desnoyers, Nicolas Dufresne,
Benjamin Gaignard, Philipp Zabel, Heiko Stuebner
Cc: linux-kernel, linux-media, linux-trace-kernel, linux-rockchip,
linux-arm-kernel, kernel, Detlev Casanova
In-Reply-To: <20260610-v4l2-add-ftrace-v2-0-9756edf72ac1@collabora.com>
With these fields, userspace can better track which trace event matches
with a given stream.
Even though the trace shows the PID (based on current->tgid), trace
functions could be called from other contexts, therefore showing the wrong
PID, or none at all.
These will ensure that the trace event can be matched with the PID/FD that
opened and configured the video device file.
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
Reviewed-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
---
drivers/media/test-drivers/visl/visl-dec.c | 68 ++--
include/trace/events/v4l2_controls.h | 628 +++++++++++++++++++----------
2 files changed, 445 insertions(+), 251 deletions(-)
diff --git a/drivers/media/test-drivers/visl/visl-dec.c b/drivers/media/test-drivers/visl/visl-dec.c
index 1c66a1b8d78f..2a065a6249ad 100644
--- a/drivers/media/test-drivers/visl/visl-dec.c
+++ b/drivers/media/test-drivers/visl/visl-dec.c
@@ -489,67 +489,71 @@ static void visl_tpg_fill(struct visl_ctx *ctx, struct visl_run *run)
static void visl_trace_ctrls(struct visl_ctx *ctx, struct visl_run *run)
{
int i;
+ struct v4l2_fh *fh = &ctx->fh;
switch (ctx->current_codec) {
default:
case VISL_CODEC_NONE:
break;
case VISL_CODEC_FWHT:
- trace_v4l2_ctrl_fwht_params(run->fwht.params);
+ trace_v4l2_ctrl_fwht_params(fh->tgid, fh->fd, run->fwht.params);
break;
case VISL_CODEC_MPEG2:
- trace_v4l2_ctrl_mpeg2_sequence(run->mpeg2.seq);
- trace_v4l2_ctrl_mpeg2_picture(run->mpeg2.pic);
- trace_v4l2_ctrl_mpeg2_quantisation(run->mpeg2.quant);
+ trace_v4l2_ctrl_mpeg2_sequence(fh->tgid, fh->fd, run->mpeg2.seq);
+ trace_v4l2_ctrl_mpeg2_picture(fh->tgid, fh->fd, run->mpeg2.pic);
+ trace_v4l2_ctrl_mpeg2_quantisation(fh->tgid, fh->fd, run->mpeg2.quant);
break;
case VISL_CODEC_VP8:
- trace_v4l2_ctrl_vp8_frame(run->vp8.frame);
- trace_v4l2_ctrl_vp8_entropy(run->vp8.frame);
+ trace_v4l2_ctrl_vp8_frame(fh->tgid, fh->fd, run->vp8.frame);
+ trace_v4l2_ctrl_vp8_entropy(fh->tgid, fh->fd, run->vp8.frame);
break;
case VISL_CODEC_VP9:
- trace_v4l2_ctrl_vp9_frame(run->vp9.frame);
- trace_v4l2_ctrl_vp9_compressed_hdr(run->vp9.probs);
- trace_v4l2_ctrl_vp9_compressed_coeff(run->vp9.probs);
- trace_v4l2_vp9_mv_probs(&run->vp9.probs->mv);
+ trace_v4l2_ctrl_vp9_frame(fh->tgid, fh->fd, run->vp9.frame);
+ trace_v4l2_ctrl_vp9_compressed_hdr(fh->tgid, fh->fd, run->vp9.probs);
+ trace_v4l2_ctrl_vp9_compressed_coeff(fh->tgid, fh->fd, run->vp9.probs);
+ trace_v4l2_vp9_mv_probs(fh->tgid, fh->fd, &run->vp9.probs->mv);
break;
case VISL_CODEC_H264:
- trace_v4l2_ctrl_h264_sps(run->h264.sps);
- trace_v4l2_ctrl_h264_pps(run->h264.pps);
- trace_v4l2_ctrl_h264_scaling_matrix(run->h264.sm);
- trace_v4l2_ctrl_h264_slice_params(run->h264.spram);
+ trace_v4l2_ctrl_h264_sps(fh->tgid, fh->fd, run->h264.sps);
+ trace_v4l2_ctrl_h264_pps(fh->tgid, fh->fd, run->h264.pps);
+ trace_v4l2_ctrl_h264_scaling_matrix(fh->tgid, fh->fd, run->h264.sm);
+ trace_v4l2_ctrl_h264_slice_params(fh->tgid, fh->fd, run->h264.spram);
for (i = 0; i < ARRAY_SIZE(run->h264.spram->ref_pic_list0); i++)
- trace_v4l2_h264_ref_pic_list0(&run->h264.spram->ref_pic_list0[i], i);
+ trace_v4l2_h264_ref_pic_list0(fh->tgid, fh->fd,
+ &run->h264.spram->ref_pic_list0[i], i);
for (i = 0; i < ARRAY_SIZE(run->h264.spram->ref_pic_list0); i++)
- trace_v4l2_h264_ref_pic_list1(&run->h264.spram->ref_pic_list1[i], i);
+ trace_v4l2_h264_ref_pic_list1(fh->tgid, fh->fd,
+ &run->h264.spram->ref_pic_list1[i], i);
- trace_v4l2_ctrl_h264_decode_params(run->h264.dpram);
+ trace_v4l2_ctrl_h264_decode_params(fh->tgid, fh->fd, run->h264.dpram);
for (i = 0; i < ARRAY_SIZE(run->h264.dpram->dpb); i++)
- trace_v4l2_h264_dpb_entry(&run->h264.dpram->dpb[i], i);
+ trace_v4l2_h264_dpb_entry(fh->tgid, fh->fd, &run->h264.dpram->dpb[i], i);
- trace_v4l2_ctrl_h264_pred_weights(run->h264.pwht);
+ trace_v4l2_ctrl_h264_pred_weights(fh->tgid, fh->fd, run->h264.pwht);
break;
case VISL_CODEC_HEVC:
- trace_v4l2_ctrl_hevc_sps(run->hevc.sps);
- trace_v4l2_ctrl_hevc_pps(run->hevc.pps);
- trace_v4l2_ctrl_hevc_slice_params(run->hevc.spram);
- trace_v4l2_ctrl_hevc_scaling_matrix(run->hevc.sm);
- trace_v4l2_ctrl_hevc_decode_params(run->hevc.dpram);
+ trace_v4l2_ctrl_hevc_sps(fh->tgid, fh->fd, run->hevc.sps);
+ trace_v4l2_ctrl_hevc_pps(fh->tgid, fh->fd, run->hevc.pps);
+ trace_v4l2_ctrl_hevc_slice_params(fh->tgid, fh->fd, run->hevc.spram);
+ trace_v4l2_ctrl_hevc_scaling_matrix(fh->tgid, fh->fd, run->hevc.sm);
+ trace_v4l2_ctrl_hevc_decode_params(fh->tgid, fh->fd, run->hevc.dpram);
for (i = 0; i < ARRAY_SIZE(run->hevc.dpram->dpb); i++)
- trace_v4l2_hevc_dpb_entry(&run->hevc.dpram->dpb[i]);
+ trace_v4l2_hevc_dpb_entry(fh->tgid, fh->fd, &run->hevc.dpram->dpb[i]);
- trace_v4l2_hevc_pred_weight_table(&run->hevc.spram->pred_weight_table);
- trace_v4l2_ctrl_hevc_ext_sps_lt_rps(run->hevc.rps_lt);
- trace_v4l2_ctrl_hevc_ext_sps_st_rps(run->hevc.rps_st);
+ trace_v4l2_hevc_pred_weight_table(fh->tgid, fh->fd,
+ &run->hevc.spram->pred_weight_table);
+ trace_v4l2_ctrl_hevc_ext_sps_lt_rps(fh->tgid, fh->fd, run->hevc.rps_lt);
+ trace_v4l2_ctrl_hevc_ext_sps_st_rps(fh->tgid, fh->fd, run->hevc.rps_st);
break;
case VISL_CODEC_AV1:
- trace_v4l2_ctrl_av1_sequence(run->av1.seq);
- trace_v4l2_ctrl_av1_frame(run->av1.frame);
- trace_v4l2_ctrl_av1_film_grain(run->av1.grain);
- trace_v4l2_ctrl_av1_tile_group_entry(run->av1.tge);
+ trace_v4l2_ctrl_av1_sequence(fh->tgid, fh->fd, run->av1.seq);
+ trace_v4l2_ctrl_av1_frame(fh->tgid, fh->fd, run->av1.frame);
+ trace_v4l2_ctrl_av1_film_grain(fh->tgid, fh->fd, run->av1.grain);
+ trace_v4l2_ctrl_av1_tile_group_entry(fh->tgid, fh->fd, run->av1.tge);
break;
}
}
diff --git a/include/trace/events/v4l2_controls.h b/include/trace/events/v4l2_controls.h
index 3a9bc75752bf..a7c61c36a025 100644
--- a/include/trace/events/v4l2_controls.h
+++ b/include/trace/events/v4l2_controls.h
@@ -14,27 +14,39 @@
* They can be identified by the name of the event. All control fields are copied in a TP_STRUCT
* field so that they can be filtered separately in userspace.
*
+ * In addition to the controls fields, tgid and fd are also added in each trace events.
+ * This allows to identify controls set by a specific process and to match them with other events
+ * from the same process.
+ * tgid contains the process id that opened the video device.
+ * fd is the file descriptor in the tgid, used in case a process opens multiple video devices.
+ *
* Currently only the codec controls are supported.
*/
/* AV1 controls */
DECLARE_EVENT_CLASS(v4l2_ctrl_av1_seq_tmpl,
- TP_PROTO(const struct v4l2_ctrl_av1_sequence *s),
- TP_ARGS(s),
- TP_STRUCT__entry(__field(__u32, flags)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_av1_sequence *s),
+ TP_ARGS(tgid, fd, s),
+ TP_STRUCT__entry(__field(u32, tgid)
+ __field(u32, fd)
+ __field(__u32, flags)
__field(__u8, seq_profile)
__field(__u8, order_hint_bits)
__field(__u8, bit_depth)
__field(__u16, max_frame_width_minus_1)
__field(__u16, max_frame_height_minus_1)),
- TP_fast_assign(__entry->flags = s->flags;
+ TP_fast_assign(__entry->tgid = tgid;
+ __entry->fd = fd;
+ __entry->flags = s->flags;
__entry->seq_profile = s->seq_profile;
__entry->order_hint_bits = s->order_hint_bits;
__entry->bit_depth = s->bit_depth;
__entry->max_frame_width_minus_1 = s->max_frame_width_minus_1;
__entry->max_frame_height_minus_1 = s->max_frame_height_minus_1;),
- TP_printk("\nflags %s\nseq_profile: %u\norder_hint_bits: %u\nbit_depth: %u\n"
+ TP_printk("tgid = %u, fd = %u, "
+ "\nflags %s\nseq_profile: %u\norder_hint_bits: %u\nbit_depth: %u\n"
"max_frame_width_minus_1: %u\nmax_frame_height_minus_1: %u\n",
+ __entry->tgid, __entry->fd,
__print_flags(__entry->flags, "|",
{V4L2_AV1_SEQUENCE_FLAG_STILL_PICTURE, "STILL_PICTURE"},
{V4L2_AV1_SEQUENCE_FLAG_USE_128X128_SUPERBLOCK, "USE_128X128_SUPERBLOCK"},
@@ -65,17 +77,23 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_av1_seq_tmpl,
);
DECLARE_EVENT_CLASS(v4l2_ctrl_av1_tge_tmpl,
- TP_PROTO(const struct v4l2_ctrl_av1_tile_group_entry *t),
- TP_ARGS(t),
- TP_STRUCT__entry(__field(__u32, tile_offset)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_av1_tile_group_entry *t),
+ TP_ARGS(tgid, fd, t),
+ TP_STRUCT__entry(__field(u32, tgid)
+ __field(u32, fd)
+ __field(__u32, tile_offset)
__field(__u32, tile_size)
__field(__u32, tile_row)
__field(__u32, tile_col)),
- TP_fast_assign(__entry->tile_offset = t->tile_offset;
+ TP_fast_assign(__entry->tgid = tgid;
+ __entry->fd = fd;
+ __entry->tile_offset = t->tile_offset;
__entry->tile_size = t->tile_size;
__entry->tile_row = t->tile_row;
__entry->tile_col = t->tile_col;),
- TP_printk("\ntile_offset: %u\n tile_size: %u\n tile_row: %u\ntile_col: %u\n",
+ TP_printk("tgid = %u, fd = %u, "
+ "\ntile_offset: %u\n tile_size: %u\n tile_row: %u\ntile_col: %u\n",
+ __entry->tgid, __entry->fd,
__entry->tile_offset,
__entry->tile_size,
__entry->tile_row,
@@ -84,9 +102,11 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_av1_tge_tmpl,
);
DECLARE_EVENT_CLASS(v4l2_ctrl_av1_frame_tmpl,
- TP_PROTO(const struct v4l2_ctrl_av1_frame *f),
- TP_ARGS(f),
- TP_STRUCT__entry(__field(u8, tile_info_flags)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_av1_frame *f),
+ TP_ARGS(tgid, fd, f),
+ TP_STRUCT__entry(__field(u32, tgid)
+ __field(u32, fd)
+ __field(u8, tile_info_flags)
__field(u8, tile_info_context_update_tile_id)
__field(u8, tile_info_tile_cols)
__field(u8, tile_info_tile_rows)
@@ -144,7 +164,9 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_av1_frame_tmpl,
__array(u64, reference_frame_ts, V4L2_AV1_TOTAL_REFS_PER_FRAME)
__array(s8, ref_frame_idx, V4L2_AV1_REFS_PER_FRAME)
__field(u8, refresh_frame_flags)),
- TP_fast_assign(__entry->tile_info_flags = f->tile_info.flags;
+ TP_fast_assign(__entry->tgid = tgid;
+ __entry->fd = fd;
+ __entry->tile_info_flags = f->tile_info.flags;
__entry->tile_info_context_update_tile_id =
f->tile_info.context_update_tile_id;
__entry->tile_info_tile_cols = f->tile_info.tile_cols;
@@ -226,7 +248,8 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_av1_frame_tmpl,
memcpy(__entry->ref_frame_idx, f->ref_frame_idx,
sizeof(__entry->ref_frame_idx));
__entry->refresh_frame_flags = f->refresh_frame_flags;),
- TP_printk("\ntile_info.flags: %s\ntile_info.context_update_tile_id: %u\n"
+ TP_printk("tgid = %u, fd = %u, "
+ "\ntile_info.flags: %s\ntile_info.context_update_tile_id: %u\n"
"tile_info.tile_cols: %u\ntile_info.tile_rows: %u\n"
"tile_info.mi_col_starts: %s\ntile_info.mi_row_starts: %s\n"
"tile_info.width_in_sbs_minus_1: %s\ntile_info.height_in_sbs_minus_1: %s\n"
@@ -250,6 +273,7 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_av1_frame_tmpl,
"render_width_minus_1: %u\nrender_height_minus_1: %u\ncurrent_frame_id: %u\n"
"buffer_removal_time: %s\norder_hints: %s\nreference_frame_ts: %s\n"
"ref_frame_idx: %s\nrefresh_frame_flags: %u\n",
+ __entry->tgid, __entry->fd,
__print_flags(__entry->tile_info_flags, "|",
{V4L2_AV1_TILE_INFO_FLAG_UNIFORM_TILE_SPACING, "UNIFORM_TILE_SPACING"}),
__entry->tile_info_context_update_tile_id,
@@ -385,9 +409,11 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_av1_frame_tmpl,
DECLARE_EVENT_CLASS(v4l2_ctrl_av1_film_grain_tmpl,
- TP_PROTO(const struct v4l2_ctrl_av1_film_grain *f),
- TP_ARGS(f),
- TP_STRUCT__entry(__field(__u8, flags)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_av1_film_grain *f),
+ TP_ARGS(tgid, fd, f),
+ TP_STRUCT__entry(__field(u32, tgid)
+ __field(u32, fd)
+ __field(__u8, flags)
__field(__u8, cr_mult)
__field(__u16, grain_seed)
__field(__u8, film_grain_params_ref_idx)
@@ -412,7 +438,9 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_av1_film_grain_tmpl,
__field(__u8, cr_luma_mult)
__field(__u16, cb_offset)
__field(__u16, cr_offset)),
- TP_fast_assign(__entry->flags = f->flags;
+ TP_fast_assign(__entry->tgid = tgid;
+ __entry->fd = fd;
+ __entry->flags = f->flags;
__entry->cr_mult = f->cr_mult;
__entry->grain_seed = f->grain_seed;
__entry->film_grain_params_ref_idx = f->film_grain_params_ref_idx;
@@ -446,7 +474,8 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_av1_film_grain_tmpl,
__entry->cr_luma_mult = f->cr_luma_mult;
__entry->cb_offset = f->cb_offset;
__entry->cr_offset = f->cr_offset;),
- TP_printk("\nflags %s\ncr_mult: %u\ngrain_seed: %u\n"
+ TP_printk("tgid = %u, fd = %u, "
+ "\nflags %s\ncr_mult: %u\ngrain_seed: %u\n"
"film_grain_params_ref_idx: %u\nnum_y_points: %u\npoint_y_value: %s\n"
"point_y_scaling: %s\nnum_cb_points: %u\npoint_cb_value: %s\n"
"point_cb_scaling: %s\nnum_cr_points: %u\npoint_cr_value: %s\n"
@@ -455,6 +484,7 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_av1_film_grain_tmpl,
"ar_coeffs_cr_plus_128: %s\nar_coeff_shift_minus_6: %u\n"
"grain_scale_shift: %u\ncb_mult: %u\ncb_luma_mult: %u\ncr_luma_mult: %u\n"
"cb_offset: %u\ncr_offset: %u\n",
+ __entry->tgid, __entry->fd,
__print_flags(__entry->flags, "|",
{V4L2_AV1_FILM_GRAIN_FLAG_APPLY_GRAIN, "APPLY_GRAIN"},
{V4L2_AV1_FILM_GRAIN_FLAG_UPDATE_GRAIN, "UPDATE_GRAIN"},
@@ -507,31 +537,32 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_av1_film_grain_tmpl,
)
DEFINE_EVENT(v4l2_ctrl_av1_seq_tmpl, v4l2_ctrl_av1_sequence,
- TP_PROTO(const struct v4l2_ctrl_av1_sequence *s),
- TP_ARGS(s)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_av1_sequence *s),
+ TP_ARGS(tgid, fd, s)
);
DEFINE_EVENT(v4l2_ctrl_av1_frame_tmpl, v4l2_ctrl_av1_frame,
- TP_PROTO(const struct v4l2_ctrl_av1_frame *f),
- TP_ARGS(f)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_av1_frame *f),
+ TP_ARGS(tgid, fd, f)
);
DEFINE_EVENT(v4l2_ctrl_av1_tge_tmpl, v4l2_ctrl_av1_tile_group_entry,
- TP_PROTO(const struct v4l2_ctrl_av1_tile_group_entry *t),
- TP_ARGS(t)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_av1_tile_group_entry *t),
+ TP_ARGS(tgid, fd, t)
);
DEFINE_EVENT(v4l2_ctrl_av1_film_grain_tmpl, v4l2_ctrl_av1_film_grain,
- TP_PROTO(const struct v4l2_ctrl_av1_film_grain *f),
- TP_ARGS(f)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_av1_film_grain *f),
+ TP_ARGS(tgid, fd, f)
);
/* FWHT controls */
DECLARE_EVENT_CLASS(v4l2_ctrl_fwht_params_tmpl,
- TP_PROTO(const struct v4l2_ctrl_fwht_params *p),
- TP_ARGS(p),
- TP_STRUCT__entry(
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_fwht_params *p),
+ TP_ARGS(tgid, fd, p),
+ TP_STRUCT__entry(__field(u32, tgid)
+ __field(u32, fd)
__field(u64, backward_ref_ts)
__field(u32, version)
__field(u32, width)
@@ -542,7 +573,8 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_fwht_params_tmpl,
__field(u32, ycbcr_enc)
__field(u32, quantization)
),
- TP_fast_assign(
+ TP_fast_assign(__entry->tgid = tgid;
+ __entry->fd = fd;
__entry->backward_ref_ts = p->backward_ref_ts;
__entry->version = p->version;
__entry->width = p->width;
@@ -553,8 +585,10 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_fwht_params_tmpl,
__entry->ycbcr_enc = p->ycbcr_enc;
__entry->quantization = p->quantization;
),
- TP_printk("backward_ref_ts %llu version %u width %u height %u flags %s colorspace %u "
+ TP_printk("tgid = %u, fd = %u, "
+ "backward_ref_ts %llu version %u width %u height %u flags %s colorspace %u "
"xfer_func %u ycbcr_enc %u quantization %u",
+ __entry->tgid, __entry->fd,
__entry->backward_ref_ts, __entry->version, __entry->width, __entry->height,
__print_flags(__entry->flags, "|",
{V4L2_FWHT_FL_IS_INTERLACED, "IS_INTERLACED"},
@@ -574,16 +608,18 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_fwht_params_tmpl,
);
DEFINE_EVENT(v4l2_ctrl_fwht_params_tmpl, v4l2_ctrl_fwht_params,
- TP_PROTO(const struct v4l2_ctrl_fwht_params *p),
- TP_ARGS(p)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_fwht_params *p),
+ TP_ARGS(tgid, fd, p)
);
/* H264 controls */
DECLARE_EVENT_CLASS(v4l2_ctrl_h264_sps_tmpl,
- TP_PROTO(const struct v4l2_ctrl_h264_sps *s),
- TP_ARGS(s),
- TP_STRUCT__entry(__field(u8, profile_idc)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_h264_sps *s),
+ TP_ARGS(tgid, fd, s),
+ TP_STRUCT__entry(__field(u32, tgid)
+ __field(u32, fd)
+ __field(u8, profile_idc)
__field(u8, constraint_set_flags)
__field(u8, level_idc)
__field(u8, seq_parameter_set_id)
@@ -601,7 +637,9 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_h264_sps_tmpl,
__field(u16, pic_width_in_mbs_minus1)
__field(u16, pic_height_in_map_units_minus1)
__field(u32, flags)),
- TP_fast_assign(__entry->profile_idc = s->profile_idc;
+ TP_fast_assign(__entry->tgid = tgid;
+ __entry->fd = fd;
+ __entry->profile_idc = s->profile_idc;
__entry->constraint_set_flags = s->constraint_set_flags;
__entry->level_idc = s->level_idc;
__entry->seq_parameter_set_id = s->seq_parameter_set_id;
@@ -622,7 +660,8 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_h264_sps_tmpl,
__entry->pic_width_in_mbs_minus1 = s->pic_width_in_mbs_minus1;
__entry->pic_height_in_map_units_minus1 = s->pic_height_in_map_units_minus1;
__entry->flags = s->flags),
- TP_printk("\nprofile_idc %u\n"
+ TP_printk("tgid = %u, fd = %u, "
+ "\nprofile_idc %u\n"
"constraint_set_flags %s\n"
"level_idc %u\n"
"seq_parameter_set_id %u\n"
@@ -640,6 +679,7 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_h264_sps_tmpl,
"pic_width_in_mbs_minus1 %u\n"
"pic_height_in_map_units_minus1 %u\n"
"flags %s",
+ __entry->tgid, __entry->fd,
__entry->profile_idc,
__print_flags(__entry->constraint_set_flags, "|",
{V4L2_H264_SPS_CONSTRAINT_SET0_FLAG, "CONSTRAINT_SET0_FLAG"},
@@ -679,9 +719,11 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_h264_sps_tmpl,
);
DECLARE_EVENT_CLASS(v4l2_ctrl_h264_pps_tmpl,
- TP_PROTO(const struct v4l2_ctrl_h264_pps *p),
- TP_ARGS(p),
- TP_STRUCT__entry(__field(u8, pic_parameter_set_id)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_h264_pps *p),
+ TP_ARGS(tgid, fd, p),
+ TP_STRUCT__entry(__field(u32, tgid)
+ __field(u32, fd)
+ __field(u8, pic_parameter_set_id)
__field(u8, seq_parameter_set_id)
__field(u8, num_slice_groups_minus1)
__field(u8, num_ref_idx_l0_default_active_minus1)
@@ -692,7 +734,9 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_h264_pps_tmpl,
__field(__s8, chroma_qp_index_offset)
__field(__s8, second_chroma_qp_index_offset)
__field(u16, flags)),
- TP_fast_assign(__entry->pic_parameter_set_id = p->pic_parameter_set_id;
+ TP_fast_assign(__entry->tgid = tgid;
+ __entry->fd = fd;
+ __entry->pic_parameter_set_id = p->pic_parameter_set_id;
__entry->seq_parameter_set_id = p->seq_parameter_set_id;
__entry->num_slice_groups_minus1 = p->num_slice_groups_minus1;
__entry->num_ref_idx_l0_default_active_minus1 =
@@ -705,7 +749,8 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_h264_pps_tmpl,
__entry->chroma_qp_index_offset = p->chroma_qp_index_offset;
__entry->second_chroma_qp_index_offset = p->second_chroma_qp_index_offset;
__entry->flags = p->flags),
- TP_printk("\npic_parameter_set_id %u\n"
+ TP_printk("tgid = %u, fd = %u, "
+ "\npic_parameter_set_id %u\n"
"seq_parameter_set_id %u\n"
"num_slice_groups_minus1 %u\n"
"num_ref_idx_l0_default_active_minus1 %u\n"
@@ -716,6 +761,7 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_h264_pps_tmpl,
"chroma_qp_index_offset %d\n"
"second_chroma_qp_index_offset %d\n"
"flags %s",
+ __entry->tgid, __entry->fd,
__entry->pic_parameter_set_id,
__entry->seq_parameter_set_id,
__entry->num_slice_groups_minus1,
@@ -741,15 +787,21 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_h264_pps_tmpl,
);
DECLARE_EVENT_CLASS(v4l2_ctrl_h264_scaling_matrix_tmpl,
- TP_PROTO(const struct v4l2_ctrl_h264_scaling_matrix *s),
- TP_ARGS(s),
- TP_STRUCT__entry(__array(u8, scaling_list_4x4, 6 * 16)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_h264_scaling_matrix *s),
+ TP_ARGS(tgid, fd, s),
+ TP_STRUCT__entry(__field(u32, tgid)
+ __field(u32, fd)
+ __array(u8, scaling_list_4x4, 6 * 16)
__array(u8, scaling_list_8x8, 6 * 64)),
- TP_fast_assign(memcpy(__entry->scaling_list_4x4, s->scaling_list_4x4,
+ TP_fast_assign(__entry->tgid = tgid;
+ __entry->fd = fd;
+ memcpy(__entry->scaling_list_4x4, s->scaling_list_4x4,
sizeof(__entry->scaling_list_4x4));
memcpy(__entry->scaling_list_8x8, s->scaling_list_8x8,
sizeof(__entry->scaling_list_8x8))),
- TP_printk("\nscaling_list_4x4 {%s}\nscaling_list_8x8 {%s}",
+ TP_printk("tgid = %u, fd = %u, "
+ "\nscaling_list_4x4 {%s}\nscaling_list_8x8 {%s}",
+ __entry->tgid, __entry->fd,
__print_hex_dump("", DUMP_PREFIX_NONE, 32, 1,
__entry->scaling_list_4x4,
sizeof(__entry->scaling_list_4x4),
@@ -762,9 +814,11 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_h264_scaling_matrix_tmpl,
);
DECLARE_EVENT_CLASS(v4l2_ctrl_h264_pred_weights_tmpl,
- TP_PROTO(const struct v4l2_ctrl_h264_pred_weights *p),
- TP_ARGS(p),
- TP_STRUCT__entry(__field(u16, luma_log2_weight_denom)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_h264_pred_weights *p),
+ TP_ARGS(tgid, fd, p),
+ TP_STRUCT__entry(__field(u32, tgid)
+ __field(u32, fd)
+ __field(u16, luma_log2_weight_denom)
__field(u16, chroma_log2_weight_denom)
__array(__s16, weight_factors_0_luma_weight, 32)
__array(__s16, weight_factors_0_luma_offset, 32)
@@ -774,7 +828,9 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_h264_pred_weights_tmpl,
__array(__s16, weight_factors_1_luma_offset, 32)
__array(__s16, weight_factors_1_chroma_weight, 32 * 2)
__array(__s16, weight_factors_1_chroma_offset, 32 * 2)),
- TP_fast_assign(__entry->luma_log2_weight_denom = p->luma_log2_weight_denom;
+ TP_fast_assign(__entry->tgid = tgid;
+ __entry->fd = fd;
+ __entry->luma_log2_weight_denom = p->luma_log2_weight_denom;
__entry->chroma_log2_weight_denom = p->chroma_log2_weight_denom;
memcpy(__entry->weight_factors_0_luma_weight,
p->weight_factors[0].luma_weight,
@@ -800,7 +856,8 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_h264_pred_weights_tmpl,
memcpy(__entry->weight_factors_1_chroma_offset,
p->weight_factors[1].chroma_offset,
sizeof(__entry->weight_factors_1_chroma_offset))),
- TP_printk("\nluma_log2_weight_denom %u\n"
+ TP_printk("tgid = %u, fd = %u, "
+ "\nluma_log2_weight_denom %u\n"
"chroma_log2_weight_denom %u\n"
"weight_factor[0].luma_weight %s\n"
"weight_factor[0].luma_offset %s\n"
@@ -810,6 +867,7 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_h264_pred_weights_tmpl,
"weight_factor[1].luma_offset %s\n"
"weight_factor[1].chroma_weight {%s}\n"
"weight_factor[1].chroma_offset {%s}\n",
+ __entry->tgid, __entry->fd,
__entry->luma_log2_weight_denom,
__entry->chroma_log2_weight_denom,
__print_array(__entry->weight_factors_0_luma_weight,
@@ -844,9 +902,11 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_h264_pred_weights_tmpl,
);
DECLARE_EVENT_CLASS(v4l2_ctrl_h264_slice_params_tmpl,
- TP_PROTO(const struct v4l2_ctrl_h264_slice_params *s),
- TP_ARGS(s),
- TP_STRUCT__entry(__field(u32, header_bit_size)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_h264_slice_params *s),
+ TP_ARGS(tgid, fd, s),
+ TP_STRUCT__entry(__field(u32, tgid)
+ __field(u32, fd)
+ __field(u32, header_bit_size)
__field(u32, first_mb_in_slice)
__field(u8, slice_type)
__field(u8, colour_plane_id)
@@ -860,7 +920,9 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_h264_slice_params_tmpl,
__field(u8, num_ref_idx_l0_active_minus1)
__field(u8, num_ref_idx_l1_active_minus1)
__field(u32, flags)),
- TP_fast_assign(__entry->header_bit_size = s->header_bit_size;
+ TP_fast_assign(__entry->tgid = tgid;
+ __entry->fd = fd;
+ __entry->header_bit_size = s->header_bit_size;
__entry->first_mb_in_slice = s->first_mb_in_slice;
__entry->slice_type = s->slice_type;
__entry->colour_plane_id = s->colour_plane_id;
@@ -874,7 +936,8 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_h264_slice_params_tmpl,
__entry->num_ref_idx_l0_active_minus1 = s->num_ref_idx_l0_active_minus1;
__entry->num_ref_idx_l1_active_minus1 = s->num_ref_idx_l1_active_minus1;
__entry->flags = s->flags),
- TP_printk("\nheader_bit_size %u\n"
+ TP_printk("tgid = %u, fd = %u, "
+ "\nheader_bit_size %u\n"
"first_mb_in_slice %u\n"
"slice_type %s\n"
"colour_plane_id %u\n"
@@ -888,6 +951,7 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_h264_slice_params_tmpl,
"num_ref_idx_l0_active_minus1 %u\n"
"num_ref_idx_l1_active_minus1 %u\n"
"flags %s",
+ __entry->tgid, __entry->fd,
__entry->header_bit_size,
__entry->first_mb_in_slice,
__print_symbolic(__entry->slice_type,
@@ -913,15 +977,21 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_h264_slice_params_tmpl,
);
DECLARE_EVENT_CLASS(v4l2_h264_reference_tmpl,
- TP_PROTO(const struct v4l2_h264_reference *r, int i),
- TP_ARGS(r, i),
- TP_STRUCT__entry(__field(u8, fields)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_h264_reference *r, int i),
+ TP_ARGS(tgid, fd, r, i),
+ TP_STRUCT__entry(__field(u32, tgid)
+ __field(u32, fd)
+ __field(u8, fields)
__field(u8, index)
__field(int, i)),
- TP_fast_assign(__entry->fields = r->fields;
+ TP_fast_assign(__entry->tgid = tgid;
+ __entry->fd = fd;
+ __entry->fields = r->fields;
__entry->index = r->index;
__entry->i = i;),
- TP_printk("[%d]: fields %s index %u",
+ TP_printk("tgid = %u, fd = %u, "
+ "[%d]: fields %s index %u",
+ __entry->tgid, __entry->fd,
__entry->i,
__print_flags(__entry->fields, "|",
{V4L2_H264_TOP_FIELD_REF, "TOP_FIELD_REF"},
@@ -932,9 +1002,11 @@ DECLARE_EVENT_CLASS(v4l2_h264_reference_tmpl,
);
DECLARE_EVENT_CLASS(v4l2_ctrl_h264_decode_params_tmpl,
- TP_PROTO(const struct v4l2_ctrl_h264_decode_params *d),
- TP_ARGS(d),
- TP_STRUCT__entry(__field(u16, nal_ref_idc)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_h264_decode_params *d),
+ TP_ARGS(tgid, fd, d),
+ TP_STRUCT__entry(__field(u32, tgid)
+ __field(u32, fd)
+ __field(u16, nal_ref_idc)
__field(u16, frame_num)
__field(__s32, top_field_order_cnt)
__field(__s32, bottom_field_order_cnt)
@@ -947,7 +1019,9 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_h264_decode_params_tmpl,
__field(u32, pic_order_cnt_bit_size)
__field(u32, slice_group_change_cycle)
__field(u32, flags)),
- TP_fast_assign(__entry->nal_ref_idc = d->nal_ref_idc;
+ TP_fast_assign(__entry->tgid = tgid;
+ __entry->fd = fd;
+ __entry->nal_ref_idc = d->nal_ref_idc;
__entry->frame_num = d->frame_num;
__entry->top_field_order_cnt = d->top_field_order_cnt;
__entry->bottom_field_order_cnt = d->bottom_field_order_cnt;
@@ -960,7 +1034,8 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_h264_decode_params_tmpl,
__entry->pic_order_cnt_bit_size = d->pic_order_cnt_bit_size;
__entry->slice_group_change_cycle = d->slice_group_change_cycle;
__entry->flags = d->flags),
- TP_printk("\nnal_ref_idc %u\n"
+ TP_printk("tgid = %u, fd = %u, "
+ "\nnal_ref_idc %u\n"
"frame_num %u\n"
"top_field_order_cnt %d\n"
"bottom_field_order_cnt %d\n"
@@ -973,6 +1048,7 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_h264_decode_params_tmpl,
"pic_order_cnt_bit_size %u\n"
"slice_group_change_cycle %u\n"
"flags %s\n",
+ __entry->tgid, __entry->fd,
__entry->nal_ref_idc,
__entry->frame_num,
__entry->top_field_order_cnt,
@@ -995,9 +1071,11 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_h264_decode_params_tmpl,
);
DECLARE_EVENT_CLASS(v4l2_h264_dpb_entry_tmpl,
- TP_PROTO(const struct v4l2_h264_dpb_entry *e, int i),
- TP_ARGS(e, i),
- TP_STRUCT__entry(__field(u64, reference_ts)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_h264_dpb_entry *e, int i),
+ TP_ARGS(tgid, fd, e, i),
+ TP_STRUCT__entry(__field(u32, tgid)
+ __field(u32, fd)
+ __field(u64, reference_ts)
__field(u32, pic_num)
__field(u16, frame_num)
__field(u8, fields)
@@ -1005,7 +1083,9 @@ DECLARE_EVENT_CLASS(v4l2_h264_dpb_entry_tmpl,
__field(__s32, bottom_field_order_cnt)
__field(u32, flags)
__field(int, i)),
- TP_fast_assign(__entry->reference_ts = e->reference_ts;
+ TP_fast_assign(__entry->tgid = tgid;
+ __entry->fd = fd;
+ __entry->reference_ts = e->reference_ts;
__entry->pic_num = e->pic_num;
__entry->frame_num = e->frame_num;
__entry->fields = e->fields;
@@ -1013,8 +1093,10 @@ DECLARE_EVENT_CLASS(v4l2_h264_dpb_entry_tmpl,
__entry->bottom_field_order_cnt = e->bottom_field_order_cnt;
__entry->flags = e->flags;
__entry->i = i;),
- TP_printk("[%d]: reference_ts %llu, pic_num %u frame_num %u fields %s "
+ TP_printk("tgid = %u, fd = %u, "
+ "[%d]: reference_ts %llu, pic_num %u frame_num %u fields %s "
"top_field_order_cnt %d bottom_field_order_cnt %d flags %s",
+ __entry->tgid, __entry->fd,
__entry->i,
__entry->reference_ts,
__entry->pic_num,
@@ -1035,56 +1117,58 @@ DECLARE_EVENT_CLASS(v4l2_h264_dpb_entry_tmpl,
);
DEFINE_EVENT(v4l2_ctrl_h264_sps_tmpl, v4l2_ctrl_h264_sps,
- TP_PROTO(const struct v4l2_ctrl_h264_sps *s),
- TP_ARGS(s)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_h264_sps *s),
+ TP_ARGS(tgid, fd, s)
);
DEFINE_EVENT(v4l2_ctrl_h264_pps_tmpl, v4l2_ctrl_h264_pps,
- TP_PROTO(const struct v4l2_ctrl_h264_pps *p),
- TP_ARGS(p)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_h264_pps *p),
+ TP_ARGS(tgid, fd, p)
);
DEFINE_EVENT(v4l2_ctrl_h264_scaling_matrix_tmpl, v4l2_ctrl_h264_scaling_matrix,
- TP_PROTO(const struct v4l2_ctrl_h264_scaling_matrix *s),
- TP_ARGS(s)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_h264_scaling_matrix *s),
+ TP_ARGS(tgid, fd, s)
);
DEFINE_EVENT(v4l2_ctrl_h264_pred_weights_tmpl, v4l2_ctrl_h264_pred_weights,
- TP_PROTO(const struct v4l2_ctrl_h264_pred_weights *p),
- TP_ARGS(p)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_h264_pred_weights *p),
+ TP_ARGS(tgid, fd, p)
);
DEFINE_EVENT(v4l2_ctrl_h264_slice_params_tmpl, v4l2_ctrl_h264_slice_params,
- TP_PROTO(const struct v4l2_ctrl_h264_slice_params *s),
- TP_ARGS(s)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_h264_slice_params *s),
+ TP_ARGS(tgid, fd, s)
);
DEFINE_EVENT(v4l2_h264_reference_tmpl, v4l2_h264_ref_pic_list0,
- TP_PROTO(const struct v4l2_h264_reference *r, int i),
- TP_ARGS(r, i)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_h264_reference *r, int i),
+ TP_ARGS(tgid, fd, r, i)
);
DEFINE_EVENT(v4l2_h264_reference_tmpl, v4l2_h264_ref_pic_list1,
- TP_PROTO(const struct v4l2_h264_reference *r, int i),
- TP_ARGS(r, i)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_h264_reference *r, int i),
+ TP_ARGS(tgid, fd, r, i)
);
DEFINE_EVENT(v4l2_ctrl_h264_decode_params_tmpl, v4l2_ctrl_h264_decode_params,
- TP_PROTO(const struct v4l2_ctrl_h264_decode_params *d),
- TP_ARGS(d)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_h264_decode_params *d),
+ TP_ARGS(tgid, fd, d)
);
DEFINE_EVENT(v4l2_h264_dpb_entry_tmpl, v4l2_h264_dpb_entry,
- TP_PROTO(const struct v4l2_h264_dpb_entry *e, int i),
- TP_ARGS(e, i)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_h264_dpb_entry *e, int i),
+ TP_ARGS(tgid, fd, e, i)
);
/* HEVC controls */
DECLARE_EVENT_CLASS(v4l2_ctrl_hevc_sps_tmpl,
- TP_PROTO(const struct v4l2_ctrl_hevc_sps *s),
- TP_ARGS(s),
- TP_STRUCT__entry(__field(__u8, video_parameter_set_id)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_hevc_sps *s),
+ TP_ARGS(tgid, fd, s),
+ TP_STRUCT__entry(__field(u32, tgid)
+ __field(u32, fd)
+ __field(__u8, video_parameter_set_id)
__field(__u8, seq_parameter_set_id)
__field(__u16, pic_width_in_luma_samples)
__field(__u16, pic_height_in_luma_samples)
@@ -1109,7 +1193,9 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_hevc_sps_tmpl,
__field(__u8, chroma_format_idc)
__field(__u8, sps_max_sub_layers_minus1)
__field(__u64, flags)),
- TP_fast_assign(__entry->video_parameter_set_id = s->video_parameter_set_id;
+ TP_fast_assign(__entry->tgid = tgid;
+ __entry->fd = fd;
+ __entry->video_parameter_set_id = s->video_parameter_set_id;
__entry->seq_parameter_set_id = s->seq_parameter_set_id;
__entry->pic_width_in_luma_samples = s->pic_width_in_luma_samples;
__entry->pic_height_in_luma_samples = s->pic_height_in_luma_samples;
@@ -1146,7 +1232,8 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_hevc_sps_tmpl,
__entry->chroma_format_idc = s->chroma_format_idc;
__entry->sps_max_sub_layers_minus1 = s->sps_max_sub_layers_minus1;
__entry->flags = s->flags;),
- TP_printk("\nvideo_parameter_set_id %u\n"
+ TP_printk("tgid = %u, fd = %u, "
+ "\nvideo_parameter_set_id %u\n"
"seq_parameter_set_id %u\n"
"pic_width_in_luma_samples %u\n"
"pic_height_in_luma_samples %u\n"
@@ -1171,6 +1258,7 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_hevc_sps_tmpl,
"chroma_format_idc %u\n"
"sps_max_sub_layers_minus1 %u\n"
"flags %s",
+ __entry->tgid, __entry->fd,
__entry->video_parameter_set_id,
__entry->seq_parameter_set_id,
__entry->pic_width_in_luma_samples,
@@ -1213,9 +1301,11 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_hevc_sps_tmpl,
DECLARE_EVENT_CLASS(v4l2_ctrl_hevc_pps_tmpl,
- TP_PROTO(const struct v4l2_ctrl_hevc_pps *p),
- TP_ARGS(p),
- TP_STRUCT__entry(__field(__u8, pic_parameter_set_id)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_hevc_pps *p),
+ TP_ARGS(tgid, fd, p),
+ TP_STRUCT__entry(__field(u32, tgid)
+ __field(u32, fd)
+ __field(__u8, pic_parameter_set_id)
__field(__u8, num_extra_slice_header_bits)
__field(__u8, num_ref_idx_l0_default_active_minus1)
__field(__u8, num_ref_idx_l1_default_active_minus1)
@@ -1231,7 +1321,9 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_hevc_pps_tmpl,
__field(__s8, pps_tc_offset_div2)
__field(__u8, log2_parallel_merge_level_minus2)
__field(__u64, flags)),
- TP_fast_assign(__entry->pic_parameter_set_id = p->pic_parameter_set_id;
+ TP_fast_assign(__entry->tgid = tgid;
+ __entry->fd = fd;
+ __entry->pic_parameter_set_id = p->pic_parameter_set_id;
__entry->num_extra_slice_header_bits = p->num_extra_slice_header_bits;
__entry->num_ref_idx_l0_default_active_minus1 =
p->num_ref_idx_l0_default_active_minus1;
@@ -1252,7 +1344,8 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_hevc_pps_tmpl,
__entry->log2_parallel_merge_level_minus2 =
p->log2_parallel_merge_level_minus2;
__entry->flags = p->flags;),
- TP_printk("\npic_parameter_set_id %u\n"
+ TP_printk("tgid = %u, fd = %u, "
+ "\npic_parameter_set_id %u\n"
"num_extra_slice_header_bits %u\n"
"num_ref_idx_l0_default_active_minus1 %u\n"
"num_ref_idx_l1_default_active_minus1 %u\n"
@@ -1268,6 +1361,7 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_hevc_pps_tmpl,
"pps_tc_offset_div2 %d\n"
"log2_parallel_merge_level_minus2 %u\n"
"flags %s",
+ __entry->tgid, __entry->fd,
__entry->pic_parameter_set_id,
__entry->num_extra_slice_header_bits,
__entry->num_ref_idx_l0_default_active_minus1,
@@ -1322,9 +1416,11 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_hevc_pps_tmpl,
DECLARE_EVENT_CLASS(v4l2_ctrl_hevc_slice_params_tmpl,
- TP_PROTO(const struct v4l2_ctrl_hevc_slice_params *s),
- TP_ARGS(s),
- TP_STRUCT__entry(__field(__u32, bit_size)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_hevc_slice_params *s),
+ TP_ARGS(tgid, fd, s),
+ TP_STRUCT__entry(__field(u32, tgid)
+ __field(u32, fd)
+ __field(__u32, bit_size)
__field(__u32, data_byte_offset)
__field(__u32, num_entry_point_offsets)
__field(__u8, nal_unit_type)
@@ -1351,7 +1447,9 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_hevc_slice_params_tmpl,
__field(__u16, short_term_ref_pic_set_size)
__field(__u16, long_term_ref_pic_set_size)
__field(__u64, flags)),
- TP_fast_assign(__entry->bit_size = s->bit_size;
+ TP_fast_assign(__entry->tgid = tgid;
+ __entry->fd = fd;
+ __entry->bit_size = s->bit_size;
__entry->data_byte_offset = s->data_byte_offset;
__entry->num_entry_point_offsets = s->num_entry_point_offsets;
__entry->nal_unit_type = s->nal_unit_type;
@@ -1378,7 +1476,8 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_hevc_slice_params_tmpl,
__entry->short_term_ref_pic_set_size = s->short_term_ref_pic_set_size;
__entry->long_term_ref_pic_set_size = s->long_term_ref_pic_set_size;
__entry->flags = s->flags;),
- TP_printk("\nbit_size %u\n"
+ TP_printk("tgid = %u, fd = %u, "
+ "\nbit_size %u\n"
"data_byte_offset %u\n"
"num_entry_point_offsets %u\n"
"nal_unit_type %u\n"
@@ -1405,6 +1504,7 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_hevc_slice_params_tmpl,
"short_term_ref_pic_set_size %u\n"
"long_term_ref_pic_set_size %u\n"
"flags %s",
+ __entry->tgid, __entry->fd,
__entry->bit_size,
__entry->data_byte_offset,
__entry->num_entry_point_offsets,
@@ -1454,9 +1554,11 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_hevc_slice_params_tmpl,
);
DECLARE_EVENT_CLASS(v4l2_hevc_pred_weight_table_tmpl,
- TP_PROTO(const struct v4l2_hevc_pred_weight_table *p),
- TP_ARGS(p),
- TP_STRUCT__entry(__array(__s8, delta_luma_weight_l0, V4L2_HEVC_DPB_ENTRIES_NUM_MAX)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_hevc_pred_weight_table *p),
+ TP_ARGS(tgid, fd, p),
+ TP_STRUCT__entry(__field(u32, tgid)
+ __field(u32, fd)
+ __array(__s8, delta_luma_weight_l0, V4L2_HEVC_DPB_ENTRIES_NUM_MAX)
__array(__s8, luma_offset_l0, V4L2_HEVC_DPB_ENTRIES_NUM_MAX)
__array(__s8, delta_chroma_weight_l0, V4L2_HEVC_DPB_ENTRIES_NUM_MAX * 2)
__array(__s8, chroma_offset_l0, V4L2_HEVC_DPB_ENTRIES_NUM_MAX * 2)
@@ -1466,7 +1568,9 @@ DECLARE_EVENT_CLASS(v4l2_hevc_pred_weight_table_tmpl,
__array(__s8, chroma_offset_l1, V4L2_HEVC_DPB_ENTRIES_NUM_MAX * 2)
__field(__u8, luma_log2_weight_denom)
__field(__s8, delta_chroma_log2_weight_denom)),
- TP_fast_assign(memcpy(__entry->delta_luma_weight_l0, p->delta_luma_weight_l0,
+ TP_fast_assign(__entry->tgid = tgid;
+ __entry->fd = fd;
+ memcpy(__entry->delta_luma_weight_l0, p->delta_luma_weight_l0,
sizeof(__entry->delta_luma_weight_l0));
memcpy(__entry->luma_offset_l0, p->luma_offset_l0,
sizeof(__entry->luma_offset_l0));
@@ -1485,7 +1589,8 @@ DECLARE_EVENT_CLASS(v4l2_hevc_pred_weight_table_tmpl,
__entry->luma_log2_weight_denom = p->luma_log2_weight_denom;
__entry->delta_chroma_log2_weight_denom =
p->delta_chroma_log2_weight_denom;),
- TP_printk("\ndelta_luma_weight_l0 %s\n"
+ TP_printk("tgid = %u, fd = %u, "
+ "\ndelta_luma_weight_l0 %s\n"
"luma_offset_l0 %s\n"
"delta_chroma_weight_l0 {%s}\n"
"chroma_offset_l0 {%s}\n"
@@ -1495,6 +1600,7 @@ DECLARE_EVENT_CLASS(v4l2_hevc_pred_weight_table_tmpl,
"chroma_offset_l1 {%s}\n"
"luma_log2_weight_denom %d\n"
"delta_chroma_log2_weight_denom %d\n",
+ __entry->tgid, __entry->fd,
__print_array(__entry->delta_luma_weight_l0,
ARRAY_SIZE(__entry->delta_luma_weight_l0),
sizeof(__entry->delta_luma_weight_l0[0])),
@@ -1529,15 +1635,19 @@ DECLARE_EVENT_CLASS(v4l2_hevc_pred_weight_table_tmpl,
))
DECLARE_EVENT_CLASS(v4l2_ctrl_hevc_scaling_matrix_tmpl,
- TP_PROTO(const struct v4l2_ctrl_hevc_scaling_matrix *s),
- TP_ARGS(s),
- TP_STRUCT__entry(__array(__u8, scaling_list_4x4, 6 * 16)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_hevc_scaling_matrix *s),
+ TP_ARGS(tgid, fd, s),
+ TP_STRUCT__entry(__field(u32, tgid)
+ __field(u32, fd)
+ __array(__u8, scaling_list_4x4, 6 * 16)
__array(__u8, scaling_list_8x8, 6 * 64)
__array(__u8, scaling_list_16x16, 6 * 64)
__array(__u8, scaling_list_32x32, 2 * 64)
__array(__u8, scaling_list_dc_coef_16x16, 6)
__array(__u8, scaling_list_dc_coef_32x32, 2)),
- TP_fast_assign(memcpy(__entry->scaling_list_4x4,
+ TP_fast_assign(__entry->tgid = tgid;
+ __entry->fd = fd;
+ memcpy(__entry->scaling_list_4x4,
s->scaling_list_4x4, sizeof(__entry->scaling_list_4x4));
memcpy(__entry->scaling_list_8x8,
s->scaling_list_8x8, sizeof(__entry->scaling_list_8x8));
@@ -1551,12 +1661,14 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_hevc_scaling_matrix_tmpl,
memcpy(__entry->scaling_list_dc_coef_32x32,
s->scaling_list_dc_coef_32x32,
sizeof(__entry->scaling_list_dc_coef_32x32));),
- TP_printk("\nscaling_list_4x4 {%s}\n"
+ TP_printk("tgid = %u, fd = %u, "
+ "\nscaling_list_4x4 {%s}\n"
"scaling_list_8x8 {%s}\n"
"scaling_list_16x16 {%s}\n"
"scaling_list_32x32 {%s}\n"
"scaling_list_dc_coef_16x16 %s\n"
"scaling_list_dc_coef_32x32 %s\n",
+ __entry->tgid, __entry->fd,
__print_hex_dump("", DUMP_PREFIX_NONE, 32, 1,
__entry->scaling_list_4x4,
sizeof(__entry->scaling_list_4x4),
@@ -1582,9 +1694,11 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_hevc_scaling_matrix_tmpl,
))
DECLARE_EVENT_CLASS(v4l2_ctrl_hevc_decode_params_tmpl,
- TP_PROTO(const struct v4l2_ctrl_hevc_decode_params *d),
- TP_ARGS(d),
- TP_STRUCT__entry(__field(__s32, pic_order_cnt_val)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_hevc_decode_params *d),
+ TP_ARGS(tgid, fd, d),
+ TP_STRUCT__entry(__field(u32, tgid)
+ __field(u32, fd)
+ __field(__s32, pic_order_cnt_val)
__field(__u16, short_term_ref_pic_set_size)
__field(__u16, long_term_ref_pic_set_size)
__field(__u8, num_active_dpb_entries)
@@ -1595,7 +1709,9 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_hevc_decode_params_tmpl,
__array(__u8, poc_st_curr_after, V4L2_HEVC_DPB_ENTRIES_NUM_MAX)
__array(__u8, poc_lt_curr, V4L2_HEVC_DPB_ENTRIES_NUM_MAX)
__field(__u64, flags)),
- TP_fast_assign(__entry->pic_order_cnt_val = d->pic_order_cnt_val;
+ TP_fast_assign(__entry->tgid = tgid;
+ __entry->fd = fd;
+ __entry->pic_order_cnt_val = d->pic_order_cnt_val;
__entry->short_term_ref_pic_set_size = d->short_term_ref_pic_set_size;
__entry->long_term_ref_pic_set_size = d->long_term_ref_pic_set_size;
__entry->num_active_dpb_entries = d->num_active_dpb_entries;
@@ -1608,7 +1724,8 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_hevc_decode_params_tmpl,
sizeof(__entry->poc_st_curr_after));
memcpy(__entry->poc_lt_curr, d->poc_lt_curr, sizeof(__entry->poc_lt_curr));
__entry->flags = d->flags;),
- TP_printk("\npic_order_cnt_val %d\n"
+ TP_printk("tgid = %u, fd = %u, "
+ "\npic_order_cnt_val %d\n"
"short_term_ref_pic_set_size %u\n"
"long_term_ref_pic_set_size %u\n"
"num_active_dpb_entries %u\n"
@@ -1619,6 +1736,7 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_hevc_decode_params_tmpl,
"poc_st_curr_after %s\n"
"poc_lt_curr %s\n"
"flags %s",
+ __entry->tgid, __entry->fd,
__entry->pic_order_cnt_val,
__entry->short_term_ref_pic_set_size,
__entry->long_term_ref_pic_set_size,
@@ -1643,14 +1761,20 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_hevc_decode_params_tmpl,
);
DECLARE_EVENT_CLASS(v4l2_ctrl_hevc_ext_sps_lt_rps_tmpl,
- TP_PROTO(const struct v4l2_ctrl_hevc_ext_sps_lt_rps *lt),
- TP_ARGS(lt),
- TP_STRUCT__entry(__field(__u8, flags)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_hevc_ext_sps_lt_rps *lt),
+ TP_ARGS(tgid, fd, lt),
+ TP_STRUCT__entry(__field(u32, tgid)
+ __field(u32, fd)
+ __field(__u8, flags)
__field(__u32, lt_ref_pic_poc_lsb_sps)),
- TP_fast_assign(__entry->flags = lt->flags;
+ TP_fast_assign(__entry->tgid = tgid;
+ __entry->fd = fd;
+ __entry->flags = lt->flags;
__entry->lt_ref_pic_poc_lsb_sps = lt->lt_ref_pic_poc_lsb_sps;),
- TP_printk("\nflags %s\n"
+ TP_printk("tgid = %u, fd = %u, "
+ "\nflags %s\n"
"lt_ref_pic_poc_lsb_sps %x\n",
+ __entry->tgid, __entry->fd,
__print_flags(__entry->flags, "|",
{V4L2_HEVC_EXT_SPS_LT_RPS_FLAG_USED_LT, "USED_LT"}
),
@@ -1659,9 +1783,11 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_hevc_ext_sps_lt_rps_tmpl,
);
DECLARE_EVENT_CLASS(v4l2_ctrl_hevc_ext_sps_st_rps_tmpl,
- TP_PROTO(const struct v4l2_ctrl_hevc_ext_sps_st_rps *st),
- TP_ARGS(st),
- TP_STRUCT__entry(__field(__u8, flags)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_hevc_ext_sps_st_rps *st),
+ TP_ARGS(tgid, fd, st),
+ TP_STRUCT__entry(__field(u32, tgid)
+ __field(u32, fd)
+ __field(__u8, flags)
__field(__u8, delta_idx_minus1)
__field(__u8, delta_rps_sign)
__field(__u16, abs_delta_rps_minus1)
@@ -1671,7 +1797,9 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_hevc_ext_sps_st_rps_tmpl,
__field(__u32, use_delta_flag)
__array(__u32, delta_poc_s0_minus1, 16)
__array(__u32, delta_poc_s1_minus1, 16)),
- TP_fast_assign(__entry->flags = st->flags;
+ TP_fast_assign(__entry->tgid = tgid;
+ __entry->fd = fd;
+ __entry->flags = st->flags;
__entry->delta_idx_minus1 = st->delta_idx_minus1;
__entry->delta_rps_sign = st->delta_rps_sign;
__entry->abs_delta_rps_minus1 = st->abs_delta_rps_minus1;
@@ -1683,7 +1811,8 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_hevc_ext_sps_st_rps_tmpl,
sizeof(__entry->delta_poc_s0_minus1));
memcpy(__entry->delta_poc_s1_minus1, st->delta_poc_s1_minus1,
sizeof(__entry->delta_poc_s1_minus1));),
- TP_printk("\nflags %s\n"
+ TP_printk("tgid = %u, fd = %u, "
+ "\nflags %s\n"
"delta_idx_minus1: %u\n"
"delta_rps_sign: %u\n"
"abs_delta_rps_minus1: %u\n"
@@ -1693,6 +1822,7 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_hevc_ext_sps_st_rps_tmpl,
"use_delta_flag: %08x\n"
"delta_poc_s0_minus1: %s\n"
"delta_poc_s1_minus1: %s\n",
+ __entry->tgid, __entry->fd,
__print_flags(__entry->flags, "|",
{V4L2_HEVC_EXT_SPS_ST_RPS_FLAG_INTER_REF_PIC_SET_PRED, "INTER_REF_PIC_SET_PRED"}
),
@@ -1713,20 +1843,26 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_hevc_ext_sps_st_rps_tmpl,
);
DECLARE_EVENT_CLASS(v4l2_hevc_dpb_entry_tmpl,
- TP_PROTO(const struct v4l2_hevc_dpb_entry *e),
- TP_ARGS(e),
- TP_STRUCT__entry(__field(__u64, timestamp)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_hevc_dpb_entry *e),
+ TP_ARGS(tgid, fd, e),
+ TP_STRUCT__entry(__field(u32, tgid)
+ __field(u32, fd)
+ __field(__u64, timestamp)
__field(__u8, flags)
__field(__u8, field_pic)
__field(__s32, pic_order_cnt_val)),
- TP_fast_assign(__entry->timestamp = e->timestamp;
+ TP_fast_assign(__entry->tgid = tgid;
+ __entry->fd = fd;
+ __entry->timestamp = e->timestamp;
__entry->flags = e->flags;
__entry->field_pic = e->field_pic;
__entry->pic_order_cnt_val = e->pic_order_cnt_val;),
- TP_printk("\ntimestamp %llu\n"
+ TP_printk("tgid = %u, fd = %u, "
+ "\ntimestamp %llu\n"
"flags %s\n"
"field_pic %u\n"
"pic_order_cnt_val %d\n",
+ __entry->tgid, __entry->fd,
__entry->timestamp,
__print_flags(__entry->flags, "|",
{V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE, "LONG_TERM_REFERENCE"}
@@ -1736,69 +1872,75 @@ DECLARE_EVENT_CLASS(v4l2_hevc_dpb_entry_tmpl,
))
DEFINE_EVENT(v4l2_ctrl_hevc_sps_tmpl, v4l2_ctrl_hevc_sps,
- TP_PROTO(const struct v4l2_ctrl_hevc_sps *s),
- TP_ARGS(s)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_hevc_sps *s),
+ TP_ARGS(tgid, fd, s)
);
DEFINE_EVENT(v4l2_ctrl_hevc_pps_tmpl, v4l2_ctrl_hevc_pps,
- TP_PROTO(const struct v4l2_ctrl_hevc_pps *p),
- TP_ARGS(p)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_hevc_pps *p),
+ TP_ARGS(tgid, fd, p)
);
DEFINE_EVENT(v4l2_ctrl_hevc_slice_params_tmpl, v4l2_ctrl_hevc_slice_params,
- TP_PROTO(const struct v4l2_ctrl_hevc_slice_params *s),
- TP_ARGS(s)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_hevc_slice_params *s),
+ TP_ARGS(tgid, fd, s)
);
DEFINE_EVENT(v4l2_hevc_pred_weight_table_tmpl, v4l2_hevc_pred_weight_table,
- TP_PROTO(const struct v4l2_hevc_pred_weight_table *p),
- TP_ARGS(p)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_hevc_pred_weight_table *p),
+ TP_ARGS(tgid, fd, p)
);
DEFINE_EVENT(v4l2_ctrl_hevc_scaling_matrix_tmpl, v4l2_ctrl_hevc_scaling_matrix,
- TP_PROTO(const struct v4l2_ctrl_hevc_scaling_matrix *s),
- TP_ARGS(s)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_hevc_scaling_matrix *s),
+ TP_ARGS(tgid, fd, s)
);
DEFINE_EVENT(v4l2_ctrl_hevc_decode_params_tmpl, v4l2_ctrl_hevc_decode_params,
- TP_PROTO(const struct v4l2_ctrl_hevc_decode_params *d),
- TP_ARGS(d)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_hevc_decode_params *d),
+ TP_ARGS(tgid, fd, d)
);
DEFINE_EVENT(v4l2_ctrl_hevc_ext_sps_lt_rps_tmpl, v4l2_ctrl_hevc_ext_sps_lt_rps,
- TP_PROTO(const struct v4l2_ctrl_hevc_ext_sps_lt_rps *lt),
- TP_ARGS(lt)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_hevc_ext_sps_lt_rps *lt),
+ TP_ARGS(tgid, fd, lt)
);
DEFINE_EVENT(v4l2_ctrl_hevc_ext_sps_st_rps_tmpl, v4l2_ctrl_hevc_ext_sps_st_rps,
- TP_PROTO(const struct v4l2_ctrl_hevc_ext_sps_st_rps *st),
- TP_ARGS(st)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_hevc_ext_sps_st_rps *st),
+ TP_ARGS(tgid, fd, st)
);
DEFINE_EVENT(v4l2_hevc_dpb_entry_tmpl, v4l2_hevc_dpb_entry,
- TP_PROTO(const struct v4l2_hevc_dpb_entry *e),
- TP_ARGS(e)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_hevc_dpb_entry *e),
+ TP_ARGS(tgid, fd, e)
);
/* MPEG2 controls */
DECLARE_EVENT_CLASS(v4l2_ctrl_mpeg2_seq_tmpl,
- TP_PROTO(const struct v4l2_ctrl_mpeg2_sequence *s),
- TP_ARGS(s),
- TP_STRUCT__entry(__field(__u16, horizontal_size)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_mpeg2_sequence *s),
+ TP_ARGS(tgid, fd, s),
+ TP_STRUCT__entry(__field(u32, tgid)
+ __field(u32, fd)
+ __field(__u16, horizontal_size)
__field(__u16, vertical_size)
__field(__u32, vbv_buffer_size)
__field(__u16, profile_and_level_indication)
__field(__u8, chroma_format)
__field(__u8, flags)),
- TP_fast_assign(__entry->horizontal_size = s->horizontal_size;
+ TP_fast_assign(__entry->tgid = tgid;
+ __entry->fd = fd;
+ __entry->horizontal_size = s->horizontal_size;
__entry->vertical_size = s->vertical_size;
__entry->vbv_buffer_size = s->vbv_buffer_size;
__entry->profile_and_level_indication = s->profile_and_level_indication;
__entry->chroma_format = s->chroma_format;
__entry->flags = s->flags;),
- TP_printk("\nhorizontal_size %u\nvertical_size %u\nvbv_buffer_size %u\n"
+ TP_printk("tgid = %u, fd = %u, "
+ "\nhorizontal_size %u\nvertical_size %u\nvbv_buffer_size %u\n"
"profile_and_level_indication %u\nchroma_format %u\nflags %s\n",
+ __entry->tgid, __entry->fd,
__entry->horizontal_size,
__entry->vertical_size,
__entry->vbv_buffer_size,
@@ -1810,24 +1952,30 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_mpeg2_seq_tmpl,
);
DECLARE_EVENT_CLASS(v4l2_ctrl_mpeg2_pic_tmpl,
- TP_PROTO(const struct v4l2_ctrl_mpeg2_picture *p),
- TP_ARGS(p),
- TP_STRUCT__entry(__field(__u64, backward_ref_ts)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_mpeg2_picture *p),
+ TP_ARGS(tgid, fd, p),
+ TP_STRUCT__entry(__field(u32, tgid)
+ __field(u32, fd)
+ __field(__u64, backward_ref_ts)
__field(__u64, forward_ref_ts)
__field(__u32, flags)
__array(__u8, f_code, 4)
__field(__u8, picture_coding_type)
__field(__u8, picture_structure)
__field(__u8, intra_dc_precision)),
- TP_fast_assign(__entry->backward_ref_ts = p->backward_ref_ts;
+ TP_fast_assign(__entry->tgid = tgid;
+ __entry->fd = fd;
+ __entry->backward_ref_ts = p->backward_ref_ts;
__entry->forward_ref_ts = p->forward_ref_ts;
__entry->flags = p->flags;
memcpy(__entry->f_code, p->f_code, sizeof(__entry->f_code));
__entry->picture_coding_type = p->picture_coding_type;
__entry->picture_structure = p->picture_structure;
__entry->intra_dc_precision = p->intra_dc_precision;),
- TP_printk("\nbackward_ref_ts %llu\nforward_ref_ts %llu\nflags %s\nf_code {%s}\n"
+ TP_printk("tgid = %u, fd = %u, "
+ "\nbackward_ref_ts %llu\nforward_ref_ts %llu\nflags %s\nf_code {%s}\n"
"picture_coding_type: %u\npicture_structure %u\nintra_dc_precision %u\n",
+ __entry->tgid, __entry->fd,
__entry->backward_ref_ts,
__entry->forward_ref_ts,
__print_flags(__entry->flags, "|",
@@ -1850,13 +1998,17 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_mpeg2_pic_tmpl,
);
DECLARE_EVENT_CLASS(v4l2_ctrl_mpeg2_quant_tmpl,
- TP_PROTO(const struct v4l2_ctrl_mpeg2_quantisation *q),
- TP_ARGS(q),
- TP_STRUCT__entry(__array(__u8, intra_quantiser_matrix, 64)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_mpeg2_quantisation *q),
+ TP_ARGS(tgid, fd, q),
+ TP_STRUCT__entry(__field(u32, tgid)
+ __field(u32, fd)
+ __array(__u8, intra_quantiser_matrix, 64)
__array(__u8, non_intra_quantiser_matrix, 64)
__array(__u8, chroma_intra_quantiser_matrix, 64)
__array(__u8, chroma_non_intra_quantiser_matrix, 64)),
- TP_fast_assign(memcpy(__entry->intra_quantiser_matrix, q->intra_quantiser_matrix,
+ TP_fast_assign(__entry->tgid = tgid;
+ __entry->fd = fd;
+ memcpy(__entry->intra_quantiser_matrix, q->intra_quantiser_matrix,
sizeof(__entry->intra_quantiser_matrix));
memcpy(__entry->non_intra_quantiser_matrix, q->non_intra_quantiser_matrix,
sizeof(__entry->non_intra_quantiser_matrix));
@@ -1866,8 +2018,10 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_mpeg2_quant_tmpl,
memcpy(__entry->chroma_non_intra_quantiser_matrix,
q->chroma_non_intra_quantiser_matrix,
sizeof(__entry->chroma_non_intra_quantiser_matrix));),
- TP_printk("\nintra_quantiser_matrix %s\nnon_intra_quantiser_matrix %s\n"
+ TP_printk("tgid = %u, fd = %u, "
+ "\nintra_quantiser_matrix %s\nnon_intra_quantiser_matrix %s\n"
"chroma_intra_quantiser_matrix %s\nchroma_non_intra_quantiser_matrix %s\n",
+ __entry->tgid, __entry->fd,
__print_array(__entry->intra_quantiser_matrix,
ARRAY_SIZE(__entry->intra_quantiser_matrix),
sizeof(__entry->intra_quantiser_matrix[0])),
@@ -1884,30 +2038,34 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_mpeg2_quant_tmpl,
)
DEFINE_EVENT(v4l2_ctrl_mpeg2_seq_tmpl, v4l2_ctrl_mpeg2_sequence,
- TP_PROTO(const struct v4l2_ctrl_mpeg2_sequence *s),
- TP_ARGS(s)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_mpeg2_sequence *s),
+ TP_ARGS(tgid, fd, s)
);
DEFINE_EVENT(v4l2_ctrl_mpeg2_pic_tmpl, v4l2_ctrl_mpeg2_picture,
- TP_PROTO(const struct v4l2_ctrl_mpeg2_picture *p),
- TP_ARGS(p)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_mpeg2_picture *p),
+ TP_ARGS(tgid, fd, p)
);
DEFINE_EVENT(v4l2_ctrl_mpeg2_quant_tmpl, v4l2_ctrl_mpeg2_quantisation,
- TP_PROTO(const struct v4l2_ctrl_mpeg2_quantisation *q),
- TP_ARGS(q)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_mpeg2_quantisation *q),
+ TP_ARGS(tgid, fd, q)
);
/* VP8 controls */
DECLARE_EVENT_CLASS(v4l2_ctrl_vp8_entropy_tmpl,
- TP_PROTO(const struct v4l2_ctrl_vp8_frame *f),
- TP_ARGS(f),
- TP_STRUCT__entry(__array(__u8, entropy_coeff_probs, 4 * 8 * 3 * V4L2_VP8_COEFF_PROB_CNT)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_vp8_frame *f),
+ TP_ARGS(tgid, fd, f),
+ TP_STRUCT__entry(__field(u32, tgid)
+ __field(u32, fd)
+ __array(__u8, entropy_coeff_probs, 4 * 8 * 3 * V4L2_VP8_COEFF_PROB_CNT)
__array(__u8, entropy_y_mode_probs, 4)
__array(__u8, entropy_uv_mode_probs, 3)
__array(__u8, entropy_mv_probs, 2 * 19)),
- TP_fast_assign(memcpy(__entry->entropy_coeff_probs, f->entropy.coeff_probs,
+ TP_fast_assign(__entry->tgid = tgid;
+ __entry->fd = fd;
+ memcpy(__entry->entropy_coeff_probs, f->entropy.coeff_probs,
sizeof(__entry->entropy_coeff_probs));
memcpy(__entry->entropy_y_mode_probs, f->entropy.y_mode_probs,
sizeof(__entry->entropy_y_mode_probs));
@@ -1915,10 +2073,12 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_vp8_entropy_tmpl,
sizeof(__entry->entropy_uv_mode_probs));
memcpy(__entry->entropy_mv_probs, f->entropy.mv_probs,
sizeof(__entry->entropy_mv_probs));),
- TP_printk("\nentropy.coeff_probs {%s}\n"
+ TP_printk("tgid = %u, fd = %u, "
+ "\nentropy.coeff_probs {%s}\n"
"entropy.y_mode_probs %s\n"
"entropy.uv_mode_probs %s\n"
"entropy.mv_probs {%s}",
+ __entry->tgid, __entry->fd,
__print_hex_dump("", DUMP_PREFIX_NONE, 32, 1,
__entry->entropy_coeff_probs,
sizeof(__entry->entropy_coeff_probs),
@@ -1937,9 +2097,11 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_vp8_entropy_tmpl,
)
DECLARE_EVENT_CLASS(v4l2_ctrl_vp8_frame_tmpl,
- TP_PROTO(const struct v4l2_ctrl_vp8_frame *f),
- TP_ARGS(f),
- TP_STRUCT__entry(__array(__s8, segment_quant_update, 4)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_vp8_frame *f),
+ TP_ARGS(tgid, fd, f),
+ TP_STRUCT__entry(__field(u32, tgid)
+ __field(u32, fd)
+ __array(__s8, segment_quant_update, 4)
__array(__s8, segment_lf_update, 4)
__array(__u8, segment_segment_probs, 3)
__field(__u32, segment_flags)
@@ -1974,7 +2136,9 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_vp8_frame_tmpl,
__field(__u64, golden_frame_ts)
__field(__u64, alt_frame_ts)
__field(__u64, flags)),
- TP_fast_assign(memcpy(__entry->segment_quant_update, f->segment.quant_update,
+ TP_fast_assign(__entry->tgid = tgid;
+ __entry->fd = fd;
+ memcpy(__entry->segment_quant_update, f->segment.quant_update,
sizeof(__entry->segment_quant_update));
memcpy(__entry->segment_lf_update, f->segment.lf_update,
sizeof(__entry->segment_lf_update));
@@ -2015,7 +2179,8 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_vp8_frame_tmpl,
__entry->golden_frame_ts = f->golden_frame_ts;
__entry->alt_frame_ts = f->alt_frame_ts;
__entry->flags = f->flags;),
- TP_printk("\nsegment.quant_update %s\n"
+ TP_printk("tgid = %u, fd = %u, "
+ "\nsegment.quant_update %s\n"
"segment.lf_update %s\n"
"segment.segment_probs %s\n"
"segment.flags %s\n"
@@ -2050,6 +2215,7 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_vp8_frame_tmpl,
"golden_frame_ts %llu\n"
"alt_frame_ts %llu\n"
"flags %s",
+ __entry->tgid, __entry->fd,
__print_array(__entry->segment_quant_update,
ARRAY_SIZE(__entry->segment_quant_update),
sizeof(__entry->segment_quant_update[0])),
@@ -2114,21 +2280,23 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_vp8_frame_tmpl,
);
DEFINE_EVENT(v4l2_ctrl_vp8_frame_tmpl, v4l2_ctrl_vp8_frame,
- TP_PROTO(const struct v4l2_ctrl_vp8_frame *f),
- TP_ARGS(f)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_vp8_frame *f),
+ TP_ARGS(tgid, fd, f)
);
DEFINE_EVENT(v4l2_ctrl_vp8_entropy_tmpl, v4l2_ctrl_vp8_entropy,
- TP_PROTO(const struct v4l2_ctrl_vp8_frame *f),
- TP_ARGS(f)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_vp8_frame *f),
+ TP_ARGS(tgid, fd, f)
);
/* VP9 controls */
DECLARE_EVENT_CLASS(v4l2_ctrl_vp9_frame_tmpl,
- TP_PROTO(const struct v4l2_ctrl_vp9_frame *f),
- TP_ARGS(f),
- TP_STRUCT__entry(__array(__s8, lf_ref_deltas, 4)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_vp9_frame *f),
+ TP_ARGS(tgid, fd, f),
+ TP_STRUCT__entry(__field(u32, tgid)
+ __field(u32, fd)
+ __array(__s8, lf_ref_deltas, 4)
__array(__s8, lf_mode_deltas, 2)
__field(__u8, lf_level)
__field(__u8, lf_sharpness)
@@ -2161,7 +2329,9 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_vp9_frame_tmpl,
__field(__u8, tile_cols_log2)
__field(__u8, tile_rows_log2)
__field(__u8, reference_mode)),
- TP_fast_assign(memcpy(__entry->lf_ref_deltas, f->lf.ref_deltas,
+ TP_fast_assign(__entry->tgid = tgid;
+ __entry->fd = fd;
+ memcpy(__entry->lf_ref_deltas, f->lf.ref_deltas,
sizeof(__entry->lf_ref_deltas));
memcpy(__entry->lf_mode_deltas, f->lf.mode_deltas,
sizeof(__entry->lf_mode_deltas));
@@ -2200,7 +2370,8 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_vp9_frame_tmpl,
__entry->tile_cols_log2 = f->tile_cols_log2;
__entry->tile_rows_log2 = f->tile_rows_log2;
__entry->reference_mode = f->reference_mode;),
- TP_printk("\nlf.ref_deltas %s\n"
+ TP_printk("tgid = %u, fd = %u, "
+ "\nlf.ref_deltas %s\n"
"lf.mode_deltas %s\n"
"lf.level %u\n"
"lf.sharpness %u\n"
@@ -2233,6 +2404,7 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_vp9_frame_tmpl,
"tile_cols_log2 %u\n"
"tile_rows_log_2 %u\n"
"reference_mode %s\n",
+ __entry->tgid, __entry->fd,
__print_array(__entry->lf_ref_deltas,
ARRAY_SIZE(__entry->lf_ref_deltas),
sizeof(__entry->lf_ref_deltas[0])),
@@ -2313,9 +2485,11 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_vp9_frame_tmpl,
);
DECLARE_EVENT_CLASS(v4l2_ctrl_vp9_compressed_hdr_tmpl,
- TP_PROTO(const struct v4l2_ctrl_vp9_compressed_hdr *h),
- TP_ARGS(h),
- TP_STRUCT__entry(__field(__u8, tx_mode)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_vp9_compressed_hdr *h),
+ TP_ARGS(tgid, fd, h),
+ TP_STRUCT__entry(__field(u32, tgid)
+ __field(u32, fd)
+ __field(__u8, tx_mode)
__array(__u8, tx8, 2 * 1)
__array(__u8, tx16, 2 * 2)
__array(__u8, tx32, 2 * 3)
@@ -2329,7 +2503,9 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_vp9_compressed_hdr_tmpl,
__array(__u8, y_mode, 4 * 9)
__array(__u8, uv_mode, 10 * 9)
__array(__u8, partition, 16 * 3)),
- TP_fast_assign(__entry->tx_mode = h->tx_mode;
+ TP_fast_assign(__entry->tgid = tgid;
+ __entry->fd = fd;
+ __entry->tx_mode = h->tx_mode;
memcpy(__entry->tx8, h->tx8, sizeof(__entry->tx8));
memcpy(__entry->tx16, h->tx16, sizeof(__entry->tx16));
memcpy(__entry->tx32, h->tx32, sizeof(__entry->tx32));
@@ -2344,7 +2520,8 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_vp9_compressed_hdr_tmpl,
memcpy(__entry->y_mode, h->y_mode, sizeof(__entry->y_mode));
memcpy(__entry->uv_mode, h->uv_mode, sizeof(__entry->uv_mode));
memcpy(__entry->partition, h->partition, sizeof(__entry->partition));),
- TP_printk("\ntx_mode %s\n"
+ TP_printk("tgid = %u, fd = %u, "
+ "\ntx_mode %s\n"
"tx8 {%s}\n"
"tx16 {%s}\n"
"tx32 {%s}\n"
@@ -2358,6 +2535,7 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_vp9_compressed_hdr_tmpl,
"y_mode {%s}\n"
"uv_mode {%s}\n"
"partition {%s}\n",
+ __entry->tgid, __entry->fd,
__print_symbolic(__entry->tx_mode,
{V4L2_VP9_TX_MODE_ONLY_4X4, "TX_MODE_ONLY_4X4"},
{V4L2_VP9_TX_MODE_ALLOW_8X8, "TX_MODE_ALLOW_8X8"},
@@ -2416,11 +2594,17 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_vp9_compressed_hdr_tmpl,
);
DECLARE_EVENT_CLASS(v4l2_ctrl_vp9_compressed_coef_tmpl,
- TP_PROTO(const struct v4l2_ctrl_vp9_compressed_hdr *h),
- TP_ARGS(h),
- TP_STRUCT__entry(__array(__u8, coef, 4 * 2 * 2 * 6 * 6 * 3)),
- TP_fast_assign(memcpy(__entry->coef, h->coef, sizeof(__entry->coef));),
- TP_printk("\n coef {%s}",
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_vp9_compressed_hdr *h),
+ TP_ARGS(tgid, fd, h),
+ TP_STRUCT__entry(__field(u32, tgid)
+ __field(u32, fd)
+ __array(__u8, coef, 4 * 2 * 2 * 6 * 6 * 3)),
+ TP_fast_assign(__entry->tgid = tgid;
+ __entry->fd = fd;
+ memcpy(__entry->coef, h->coef, sizeof(__entry->coef));),
+ TP_printk("tgid = %u, fd = %u, "
+ "\n coef {%s}",
+ __entry->tgid, __entry->fd,
__print_hex_dump("", DUMP_PREFIX_NONE, 32, 1,
__entry->coef,
sizeof(__entry->coef),
@@ -2429,9 +2613,11 @@ DECLARE_EVENT_CLASS(v4l2_ctrl_vp9_compressed_coef_tmpl,
);
DECLARE_EVENT_CLASS(v4l2_vp9_mv_probs_tmpl,
- TP_PROTO(const struct v4l2_vp9_mv_probs *p),
- TP_ARGS(p),
- TP_STRUCT__entry(__array(__u8, joint, 3)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_vp9_mv_probs *p),
+ TP_ARGS(tgid, fd, p),
+ TP_STRUCT__entry(__field(u32, tgid)
+ __field(u32, fd)
+ __array(__u8, joint, 3)
__array(__u8, sign, 2)
__array(__u8, classes, 2 * 10)
__array(__u8, class0_bit, 2)
@@ -2440,7 +2626,9 @@ DECLARE_EVENT_CLASS(v4l2_vp9_mv_probs_tmpl,
__array(__u8, fr, 2 * 3)
__array(__u8, class0_hp, 2)
__array(__u8, hp, 2)),
- TP_fast_assign(memcpy(__entry->joint, p->joint, sizeof(__entry->joint));
+ TP_fast_assign(__entry->tgid = tgid;
+ __entry->fd = fd;
+ memcpy(__entry->joint, p->joint, sizeof(__entry->joint));
memcpy(__entry->sign, p->sign, sizeof(__entry->sign));
memcpy(__entry->classes, p->classes, sizeof(__entry->classes));
memcpy(__entry->class0_bit, p->class0_bit, sizeof(__entry->class0_bit));
@@ -2449,7 +2637,8 @@ DECLARE_EVENT_CLASS(v4l2_vp9_mv_probs_tmpl,
memcpy(__entry->fr, p->fr, sizeof(__entry->fr));
memcpy(__entry->class0_hp, p->class0_hp, sizeof(__entry->class0_hp));
memcpy(__entry->hp, p->hp, sizeof(__entry->hp));),
- TP_printk("\n joint %s\n"
+ TP_printk("tgid = %u, fd = %u, "
+ "\n joint %s\n"
"sign %s\n"
"classes {%s}\n"
"class0_bit %s\n"
@@ -2458,6 +2647,7 @@ DECLARE_EVENT_CLASS(v4l2_vp9_mv_probs_tmpl,
"fr {%s}\n"
"class0_hp %s\n"
"hp %s\n",
+ __entry->tgid, __entry->fd,
__print_array(__entry->joint,
ARRAY_SIZE(__entry->joint),
sizeof(__entry->joint[0])),
@@ -2493,24 +2683,24 @@ DECLARE_EVENT_CLASS(v4l2_vp9_mv_probs_tmpl,
);
DEFINE_EVENT(v4l2_ctrl_vp9_frame_tmpl, v4l2_ctrl_vp9_frame,
- TP_PROTO(const struct v4l2_ctrl_vp9_frame *f),
- TP_ARGS(f)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_vp9_frame *f),
+ TP_ARGS(tgid, fd, f)
);
DEFINE_EVENT(v4l2_ctrl_vp9_compressed_hdr_tmpl, v4l2_ctrl_vp9_compressed_hdr,
- TP_PROTO(const struct v4l2_ctrl_vp9_compressed_hdr *h),
- TP_ARGS(h)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_vp9_compressed_hdr *h),
+ TP_ARGS(tgid, fd, h)
);
DEFINE_EVENT(v4l2_ctrl_vp9_compressed_coef_tmpl, v4l2_ctrl_vp9_compressed_coeff,
- TP_PROTO(const struct v4l2_ctrl_vp9_compressed_hdr *h),
- TP_ARGS(h)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_ctrl_vp9_compressed_hdr *h),
+ TP_ARGS(tgid, fd, h)
);
DEFINE_EVENT(v4l2_vp9_mv_probs_tmpl, v4l2_vp9_mv_probs,
- TP_PROTO(const struct v4l2_vp9_mv_probs *p),
- TP_ARGS(p)
+ TP_PROTO(u32 tgid, u32 fd, const struct v4l2_vp9_mv_probs *p),
+ TP_ARGS(tgid, fd, p)
);
#endif /* if !defined(_TRACE_V4L2_CONTROLS_H_) || defined(TRACE_HEADER_MULTI_READ) */
--
2.54.0
^ permalink raw reply related
* Re: [PATCH] ASoC: meson: axg-tdm-formatter: Use guard() for mutex locks
From: Mark Brown @ 2026-06-10 15:46 UTC (permalink / raw)
To: Jerome Brunet
Cc: phucduc.bui, Liam Girdwood, Neil Armstrong, Kevin Hilman,
Martin Blumenstingl, Jaroslav Kysela, Takashi Iwai, linux-sound,
linux-arm-kernel, linux-amlogic, linux-kernel
In-Reply-To: <1j8q8mfte7.fsf@starbuckisacylon.baylibre.com>
[-- Attachment #1: Type: text/plain, Size: 608 bytes --]
On Wed, Jun 10, 2026 at 02:54:08PM +0200, Jerome Brunet wrote:
> On mer. 10 juin 2026 at 17:21, phucduc.bui@gmail.com wrote:
> > Clean up the code using guard() for mutex locks.
> > Merely code refactoring, and no behavior change.
> I suppose it is OK but it does not seem to really clean anything and
> make the code easier to follow in that instance, from my perspective at
> least.
> If there is policy to systematically use guard() whenever
> possible then OK, otherwise it seems unnecessary.
I don't know about policy but there's definitely people who are keen on
converting things to this pattern.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply
* [GIT PULL] i.MX arm64 device tree changes for v7.2 (part2)
From: Frank.Li @ 2026-06-10 15:39 UTC (permalink / raw)
To: soc, arm; +Cc: Frank.Li, kernel, imx, linux-arm-kernel
From: Frank.Li@nxp.com
The following changes since commit c10cfc952215644956284a42fa7b7860dfbcb5f5:
arm64: dts: imx{91,93}-phyboard-segin: Add peb-av-18 overlays (2026-06-05 13:21:22 -0400)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/frank.li/linux.git tags/imx-dt64-7.2-part2
for you to fetch changes up to de8c602d5a2180c737e55dcd3dbcbf9dcc4af292:
arm64: dts: lx2160a-rev2: avoid 32-bit pcie window system ram overlap (2026-06-10 11:27:22 -0400)
----------------------------------------------------------------
i.MX arm64 device tree changes for v7.2 (part2)
- Revert the 32-bit non-prefetchable PCIe window from 3 GiB back to 1 GiB
to prevent overlap between inbound DMA address space and low system RAM.
Such overlap can cause DMA transactions to be routed to a BAR on the same
host bridge instead of system memory.
----------------------------------------------------------------
Josua Mayer (1):
arm64: dts: lx2160a-rev2: avoid 32-bit pcie window system ram overlap
arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
^ permalink raw reply
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