* Re: [PATCH net-next] net: airoha: better handle MIBs for GDM ports with multiple devs attached
From: Lorenzo Bianconi @ 2026-06-12 11:04 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni
Cc: linux-arm-kernel, linux-mediatek, netdev, Christian Marangi
In-Reply-To: <20260611-airoha-eth-multi-serdes-stats-v1-1-42442ae42064@kernel.org>
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> In the context of a GDM port that can have multiple net_devices attached
> (GDM3 and GDM4), the HW counters (MIBs) are global for the GDM port.
> This cause duplicated stats reported to the kernel for the related
> net_device.
> The SoC supports a split MIB feature where each counter is tracked based
> on the relevant HW channel (NBQ) to account for this scenario and
> provide a way to select the related counter on accessing the MIB
> registers.
> Enable this feature for GDM3 and GDM4 and configure the relevant HW
> channel before updating the HW stats to report correct HW counter to the
> kernel for the related interface.
> Move the stats struct from port to dev since HW counter are now specific
> to the network device instead of the GDM port. Refactor
> airoha_update_hw_stats() to take airoha_eth and airoha_gdm_port
> parameters since the function operates on the entire port.
>
> Co-developed-by: Christian Marangi <ansuelsmth@gmail.com>
> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
commenting on sashiko's report:
https://sashiko.dev/#/patchset/20260611-airoha-eth-multi-serdes-stats-v1-1-42442ae42064%40kernel.org
[...]
>
> - /* reset mib counters */
> - airoha_fe_set(eth, REG_FE_GDM_MIB_CLEAR(port->id),
> +static void airoha_update_hw_stats(struct airoha_gdm_dev *dev)
> +{
> + struct airoha_gdm_port *port = dev->port;
> + int i;
> +
> + spin_lock(&port->stats_lock);
> +
> + for (i = 0; i < ARRAY_SIZE(port->devs); i++) {
> + if (port->devs[i])
> + airoha_dev_get_hw_stats(port->devs[i]);
> + }
> +
> + /* Reset MIB counters */
> + airoha_fe_set(dev->eth, REG_FE_GDM_MIB_CLEAR(port->id),
> FE_GDM_MIB_RX_CLEAR_MASK | FE_GDM_MIB_TX_CLEAR_MASK);
- Does clearing the MIB counters outside the device loop cause issues with the
split MIB feature?
airoha_dev_get_hw_stats() modifies REG_FE_GDM_MIB_CFG to select the specific
nbq channel. Since REG_FE_GDM_MIB_CLEAR is called after the loop, does it only
clear the hardware counters for the last selected nbq? If so, the uncleared
counters for the other channels might accumulate in hardware, and adding them
repeatedly to the software stats (e.g., dev->stats.tx_ok_pkts += val) could
result in exponential growth.
Alternatively, if REG_FE_GDM_MIB_CLEAR globally clears all nbq counters for
the port, calling it here could drop packets that arrived for earlier devices
between their respective read operations and this clear.
- REG_FE_GDM_MIB_CLEAR is global and it clears all nbq counters for the port.
There's a tiny window where packets arriving for dev[0] between its read
and the global clear are lost, but that's microseconds of register reads,
so I guess that's negligible.
Regards,
Lorenzo
>
> - u64_stats_update_end(&port->stats.syncp);
> - spin_unlock(&port->stats.lock);
> + spin_unlock(&port->stats_lock);
> }
>
> static int airoha_dev_open(struct net_device *netdev)
> @@ -2043,23 +2071,22 @@ static void airoha_dev_get_stats64(struct net_device *netdev,
> struct rtnl_link_stats64 *storage)
> {
> struct airoha_gdm_dev *dev = netdev_priv(netdev);
> - struct airoha_gdm_port *port = dev->port;
> unsigned int start;
>
> airoha_update_hw_stats(dev);
> do {
> - start = u64_stats_fetch_begin(&port->stats.syncp);
> - storage->rx_packets = port->stats.rx_ok_pkts;
> - storage->tx_packets = port->stats.tx_ok_pkts;
> - storage->rx_bytes = port->stats.rx_ok_bytes;
> - storage->tx_bytes = port->stats.tx_ok_bytes;
> - storage->multicast = port->stats.rx_multicast;
> - storage->rx_errors = port->stats.rx_errors;
> - storage->rx_dropped = port->stats.rx_drops;
> - storage->tx_dropped = port->stats.tx_drops;
> - storage->rx_crc_errors = port->stats.rx_crc_error;
> - storage->rx_over_errors = port->stats.rx_over_errors;
> - } while (u64_stats_fetch_retry(&port->stats.syncp, start));
> + start = u64_stats_fetch_begin(&dev->stats.syncp);
> + storage->rx_packets = dev->stats.rx_ok_pkts;
> + storage->tx_packets = dev->stats.tx_ok_pkts;
> + storage->rx_bytes = dev->stats.rx_ok_bytes;
> + storage->tx_bytes = dev->stats.tx_ok_bytes;
> + storage->multicast = dev->stats.rx_multicast;
> + storage->rx_errors = dev->stats.rx_errors;
> + storage->rx_dropped = dev->stats.rx_drops;
> + storage->tx_dropped = dev->stats.tx_drops;
> + storage->rx_crc_errors = dev->stats.rx_crc_error;
> + storage->rx_over_errors = dev->stats.rx_over_errors;
> + } while (u64_stats_fetch_retry(&dev->stats.syncp, start));
> }
>
> static int airoha_dev_change_mtu(struct net_device *netdev, int mtu)
> @@ -2310,20 +2337,19 @@ static void airoha_ethtool_get_mac_stats(struct net_device *netdev,
> struct ethtool_eth_mac_stats *stats)
> {
> struct airoha_gdm_dev *dev = netdev_priv(netdev);
> - struct airoha_gdm_port *port = dev->port;
> unsigned int start;
>
> airoha_update_hw_stats(dev);
> do {
> - start = u64_stats_fetch_begin(&port->stats.syncp);
> - stats->FramesTransmittedOK = port->stats.tx_ok_pkts;
> - stats->OctetsTransmittedOK = port->stats.tx_ok_bytes;
> - stats->MulticastFramesXmittedOK = port->stats.tx_multicast;
> - stats->BroadcastFramesXmittedOK = port->stats.tx_broadcast;
> - stats->FramesReceivedOK = port->stats.rx_ok_pkts;
> - stats->OctetsReceivedOK = port->stats.rx_ok_bytes;
> - stats->BroadcastFramesReceivedOK = port->stats.rx_broadcast;
> - } while (u64_stats_fetch_retry(&port->stats.syncp, start));
> + start = u64_stats_fetch_begin(&dev->stats.syncp);
> + stats->FramesTransmittedOK = dev->stats.tx_ok_pkts;
> + stats->OctetsTransmittedOK = dev->stats.tx_ok_bytes;
> + stats->MulticastFramesXmittedOK = dev->stats.tx_multicast;
> + stats->BroadcastFramesXmittedOK = dev->stats.tx_broadcast;
> + stats->FramesReceivedOK = dev->stats.rx_ok_pkts;
> + stats->OctetsReceivedOK = dev->stats.rx_ok_bytes;
> + stats->BroadcastFramesReceivedOK = dev->stats.rx_broadcast;
> + } while (u64_stats_fetch_retry(&dev->stats.syncp, start));
> }
>
> static const struct ethtool_rmon_hist_range airoha_ethtool_rmon_ranges[] = {
> @@ -2343,8 +2369,7 @@ airoha_ethtool_get_rmon_stats(struct net_device *netdev,
> const struct ethtool_rmon_hist_range **ranges)
> {
> struct airoha_gdm_dev *dev = netdev_priv(netdev);
> - struct airoha_gdm_port *port = dev->port;
> - struct airoha_hw_stats *hw_stats = &port->stats;
> + struct airoha_hw_stats *hw_stats = &dev->stats;
> unsigned int start;
>
> BUILD_BUG_ON(ARRAY_SIZE(airoha_ethtool_rmon_ranges) !=
> @@ -2357,7 +2382,7 @@ airoha_ethtool_get_rmon_stats(struct net_device *netdev,
> do {
> int i;
>
> - start = u64_stats_fetch_begin(&port->stats.syncp);
> + start = u64_stats_fetch_begin(&dev->stats.syncp);
> stats->fragments = hw_stats->rx_fragment;
> stats->jabbers = hw_stats->rx_jabber;
> for (i = 0; i < ARRAY_SIZE(airoha_ethtool_rmon_ranges) - 1;
> @@ -2365,7 +2390,7 @@ airoha_ethtool_get_rmon_stats(struct net_device *netdev,
> stats->hist[i] = hw_stats->rx_len[i];
> stats->hist_tx[i] = hw_stats->tx_len[i];
> }
> - } while (u64_stats_fetch_retry(&port->stats.syncp, start));
> + } while (u64_stats_fetch_retry(&dev->stats.syncp, start));
> }
>
> static int airoha_qdma_set_chan_tx_sched(struct net_device *netdev,
> @@ -3205,6 +3230,7 @@ static int airoha_alloc_gdm_device(struct airoha_eth *eth,
>
> netdev->dev.of_node = of_node_get(np);
> dev = netdev_priv(netdev);
> + u64_stats_init(&dev->stats.syncp);
> dev->port = port;
> dev->eth = eth;
> dev->nbq = nbq;
> @@ -3244,9 +3270,8 @@ static int airoha_alloc_gdm_port(struct airoha_eth *eth,
> if (!port)
> return -ENOMEM;
>
> - u64_stats_init(&port->stats.syncp);
> - spin_lock_init(&port->stats.lock);
> port->id = id;
> + spin_lock_init(&port->stats_lock);
> eth->ports[p] = port;
>
> err = airoha_metadata_dst_alloc(port);
> diff --git a/drivers/net/ethernet/airoha/airoha_eth.h b/drivers/net/ethernet/airoha/airoha_eth.h
> index 8f42973f9cf5..46b1c31939de 100644
> --- a/drivers/net/ethernet/airoha/airoha_eth.h
> +++ b/drivers/net/ethernet/airoha/airoha_eth.h
> @@ -215,8 +215,6 @@ struct airoha_tx_irq_queue {
> };
>
> struct airoha_hw_stats {
> - /* protect concurrent hw_stats accesses */
> - spinlock_t lock;
> struct u64_stats_sync syncp;
>
> /* get_stats64 */
> @@ -554,6 +552,8 @@ struct airoha_gdm_dev {
>
> u32 flags;
> int nbq;
> +
> + struct airoha_hw_stats stats;
> };
>
> struct airoha_gdm_port {
> @@ -561,7 +561,8 @@ struct airoha_gdm_port {
> int id;
> int users;
>
> - struct airoha_hw_stats stats;
> + /* protect concurrent hw_stats accesses */
> + spinlock_t stats_lock;
>
> struct metadata_dst *dsa_meta[AIROHA_MAX_DSA_PORTS];
> };
>
> ---
> base-commit: c8459ee2fef502d6ef6c063751c33d9ac7943eab
> change-id: 20260611-airoha-eth-multi-serdes-stats-df2dc16c2dd6
>
> Best regards,
> --
> Lorenzo Bianconi <lorenzo@kernel.org>
>
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^ permalink raw reply
* [PATCH v3] virt: arm-cca-guest: use migrate_disable() for attestation token requests
From: Kohei Enju @ 2026-06-12 11:09 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel
Cc: Catalin Marinas, Will Deacon, Suzuki K Poulose, Sami Mujawar,
Steven Price, Gavin Shan, Kohei Enju
The RSI attestation token init and continue calls must be issued from
the same CPU. arm_cca_report_new() currently snapshots the CPU number
and uses smp_call_function_single() to issue those calls on that CPU.
With CONFIG_DEBUG_PREEMPT=y, the smp_processor_id() call used for the
snapshot triggers a debug splat [0] because it runs in preemptible
context. The snapshot does not pin the task to that CPU; it is only used
to choose the target CPU for smp_call_function_single(), which can fail
if that CPU is no longer available.
Use migrate_disable() and issue the token init and continue operations
directly, without the smp_call_function_single() callbacks. This keeps
the token request sequence on the same CPU while preserving a sleepable
context for the GFP_KERNEL allocations needed after the init call.
[0]
BUG: using smp_processor_id() in preemptible [00000000] code: cca-workload-at/264
caller is debug_smp_processor_id+0x20/0x30
CPU: 0 UID: 0 PID: 264 Comm: cca-workload-at Not tainted 7.1.0-rc1-00044-g55542ab273f2 #80 PREEMPT(lazy)
Hardware name: linux,dummy-virt (DT)
Call trace:
[...]
check_preemption_disabled+0xd8/0xf8
debug_smp_processor_id+0x20/0x30
arm_cca_report_new+0x48/0x278
tsm_report_read+0x154/0x1f8
tsm_report_outblob_read+0x20/0x38
configfs_bin_read_iter+0x118/0x208
vfs_read+0x220/0x318
[...]
Fixes: 7999edc484ca ("virt: arm-cca-guest: TSM_REPORT support for realms")
Signed-off-by: Kohei Enju <enju.kohei@fujitsu.com>
---
Changes:
v3:
- Switch to migrate_disable() and call RSI directly, removing
smp_call_function_single() (Will, Suzuki)
- Remove arm_cca_attestation_init() helper and unused fields from
arm_cca_token_info
- Drop Reviewed-by tags since the approach changed from v2
v2: https://lore.kernel.org/linux-arm-kernel/20260519101217.155740-1-enju.kohei@fujitsu.com/
- Add comment about why this path doesn't use migrate_disable()
v1: https://lore.kernel.org/linux-arm-kernel/20260518033157.1865498-1-enju.kohei@fujitsu.com/
---
.../virt/coco/arm-cca-guest/arm-cca-guest.c | 97 +++++++------------
1 file changed, 36 insertions(+), 61 deletions(-)
diff --git a/drivers/virt/coco/arm-cca-guest/arm-cca-guest.c b/drivers/virt/coco/arm-cca-guest/arm-cca-guest.c
index 66d00b6ceb78..a38df08da6fa 100644
--- a/drivers/virt/coco/arm-cca-guest/arm-cca-guest.c
+++ b/drivers/virt/coco/arm-cca-guest/arm-cca-guest.c
@@ -16,54 +16,38 @@
/**
* struct arm_cca_token_info - a descriptor for the token buffer.
- * @challenge: Pointer to the challenge data
- * @challenge_size: Size of the challenge data
* @granule: PA of the granule to which the token will be written
* @offset: Offset within granule to start of buffer in bytes
- * @result: result of rsi_attestation_token_continue operation
*/
struct arm_cca_token_info {
- void *challenge;
- unsigned long challenge_size;
phys_addr_t granule;
unsigned long offset;
- unsigned long result;
};
-static void arm_cca_attestation_init(void *param)
-{
- struct arm_cca_token_info *info;
-
- info = (struct arm_cca_token_info *)param;
-
- info->result = rsi_attestation_token_init(info->challenge,
- info->challenge_size);
-}
-
/**
* arm_cca_attestation_continue - Retrieve the attestation token data.
*
- * @param: pointer to the arm_cca_token_info
+ * @info: pointer to the arm_cca_token_info
*
* Attestation token generation is a long running operation and therefore
* the token data may not be retrieved in a single call. Moreover, the
* token retrieval operation must be requested on the same CPU on which the
* attestation token generation was initialised.
- * This helper function is therefore scheduled on the same CPU multiple
+ * This helper function must therefore be executed on the same CPU multiple
* times until the entire token data is retrieved.
*/
-static void arm_cca_attestation_continue(void *param)
+static unsigned long
+arm_cca_attestation_continue(struct arm_cca_token_info *info)
{
+ unsigned long ret;
unsigned long len;
unsigned long size;
- struct arm_cca_token_info *info;
-
- info = (struct arm_cca_token_info *)param;
size = RSI_GRANULE_SIZE - info->offset;
- info->result = rsi_attestation_token_continue(info->granule,
- info->offset, size, &len);
+ ret = rsi_attestation_token_continue(info->granule, info->offset, size,
+ &len);
info->offset += len;
+ return ret;
}
/**
@@ -74,8 +58,8 @@ static void arm_cca_attestation_continue(void *param)
*
* Initialise the attestation token generation using the challenge data
* passed in the TSM descriptor. Allocate memory for the attestation token
- * and schedule calls to retrieve the attestation token on the same CPU
- * on which the attestation token generation was initialised.
+ * and retrieve the attestation token on the same CPU on which the
+ * attestation token generation was initialised.
*
* The challenge data must be at least 32 bytes and no more than 64 bytes. If
* less than 64 bytes are provided it will be zero padded to 64 bytes.
@@ -85,12 +69,11 @@ static void arm_cca_attestation_continue(void *param)
* * %-EINVAL - A parameter was not valid.
* * %-ENOMEM - Out of memory.
* * %-EFAULT - Failed to get IPA for memory page(s).
- * * A negative status code as returned by smp_call_function_single().
*/
static int arm_cca_report_new(struct tsm_report *report, void *data)
{
- int ret;
- int cpu;
+ int ret = 0;
+ unsigned long rsi_result;
long max_size;
unsigned long token_size = 0;
struct arm_cca_token_info info;
@@ -103,37 +86,33 @@ static int arm_cca_report_new(struct tsm_report *report, void *data)
/*
* The attestation token 'init' and 'continue' calls must be
- * performed on the same CPU. smp_call_function_single() is used
- * instead of simply calling get_cpu() because of the need to
- * allocate outblob based on the returned value from the 'init'
- * call and that cannot be done in an atomic context.
+ * performed on the same CPU, so disable CPU migration around
+ * those operations.
*/
- cpu = smp_processor_id();
+ migrate_disable();
- info.challenge = desc->inblob;
- info.challenge_size = desc->inblob_len;
-
- ret = smp_call_function_single(cpu, arm_cca_attestation_init,
- &info, true);
- if (ret)
- return ret;
- max_size = info.result;
-
- if (max_size <= 0)
- return -EINVAL;
+ max_size = rsi_attestation_token_init(desc->inblob, desc->inblob_len);
+ if (max_size <= 0) {
+ ret = -EINVAL;
+ goto exit_migrate_enable;
+ }
/* Allocate outblob */
token = kvzalloc(max_size, GFP_KERNEL);
- if (!token)
- return -ENOMEM;
+ if (!token) {
+ ret = -ENOMEM;
+ goto exit_migrate_enable;
+ }
/*
* Since the outblob may not be physically contiguous, use a page
* to bounce the buffer from RMM.
*/
buf = alloc_pages_exact(RSI_GRANULE_SIZE, GFP_KERNEL);
- if (!buf)
- return -ENOMEM;
+ if (!buf) {
+ ret = -ENOMEM;
+ goto exit_migrate_enable;
+ }
/* Get the PA of the memory page(s) that were allocated */
info.granule = (unsigned long)virt_to_phys(buf);
@@ -144,21 +123,15 @@ static int arm_cca_report_new(struct tsm_report *report, void *data)
info.offset = 0;
do {
/*
- * Schedule a call to retrieve a sub-granule chunk
- * of data per loop iteration.
+ * Retrieve a sub-granule chunk of data per loop
+ * iteration.
*/
- ret = smp_call_function_single(cpu,
- arm_cca_attestation_continue,
- (void *)&info, true);
- if (ret != 0) {
- token_size = 0;
- goto exit_free_granule_page;
- }
- } while (info.result == RSI_INCOMPLETE &&
+ rsi_result = arm_cca_attestation_continue(&info);
+ } while (rsi_result == RSI_INCOMPLETE &&
info.offset < RSI_GRANULE_SIZE);
/* Break out in case of failure */
- if (info.result != RSI_SUCCESS && info.result != RSI_INCOMPLETE) {
+ if (rsi_result != RSI_SUCCESS && rsi_result != RSI_INCOMPLETE) {
ret = -ENXIO;
token_size = 0;
goto exit_free_granule_page;
@@ -173,12 +146,14 @@ static int arm_cca_report_new(struct tsm_report *report, void *data)
break;
memcpy(&token[token_size], buf, info.offset);
token_size += info.offset;
- } while (info.result == RSI_INCOMPLETE);
+ } while (rsi_result == RSI_INCOMPLETE);
report->outblob = no_free_ptr(token);
exit_free_granule_page:
report->outblob_len = token_size;
free_pages_exact(buf, RSI_GRANULE_SIZE);
+exit_migrate_enable:
+ migrate_enable();
return ret;
}
--
2.43.0
^ permalink raw reply related
* [PATCH] KVM: arm64: Sync SPSR_EL1 when injecting an exception into a pVM
From: Fuad Tabba @ 2026-06-12 11:34 UTC (permalink / raw)
To: Marc Zyngier, Oliver Upton, linux-arm-kernel, kvmarm,
linux-kernel
Cc: Joey Gouly, Steffen Eiden, Suzuki K Poulose, Zenghui Yu,
Catalin Marinas, Will Deacon, Sascha Bischoff, Andrew Jones,
tabba
When pKVM injects a synchronous exception into a protected guest, it
re-enters without restoring the guest's EL1 sysregs and writes the EL1
exception registers to hardware by hand: ESR_EL1 and ELR_EL1, but not
SPSR_EL1. enter_exception64() sets SPSR_EL1 (the interrupted PSTATE)
only in memory, so the guest's handler reads a stale SPSR_EL1 and
restores the wrong PSTATE on eret.
Write SPSR_EL1 alongside the other exception registers.
Fixes: 6c30bfb18d0b ("KVM: arm64: Add handlers for protected VM System Registers")
Reported-by: sashiko <sashiko@sashiko.dev>
Signed-off-by: Fuad Tabba <tabba@google.com>
---
arch/arm64/kvm/hyp/nvhe/sys_regs.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/kvm/hyp/nvhe/sys_regs.c b/arch/arm64/kvm/hyp/nvhe/sys_regs.c
index 8c3fbb413a06..1a7d5cd16d72 100644
--- a/arch/arm64/kvm/hyp/nvhe/sys_regs.c
+++ b/arch/arm64/kvm/hyp/nvhe/sys_regs.c
@@ -268,6 +268,7 @@ static void inject_sync64(struct kvm_vcpu *vcpu, u64 esr)
write_sysreg_el1(esr, SYS_ESR);
write_sysreg_el1(read_sysreg_el2(SYS_ELR), SYS_ELR);
+ write_sysreg_el1(read_sysreg_el2(SYS_SPSR), SYS_SPSR);
write_sysreg_el2(*vcpu_pc(vcpu), SYS_ELR);
write_sysreg_el2(*vcpu_cpsr(vcpu), SYS_SPSR);
}
--
2.54.0.1136.gdb2ca164c4-goog
^ permalink raw reply related
* Re: [PATCH v2] spi: xilinx: use FIFO occupancy register to determine buffer size
From: Michal Simek @ 2026-06-12 11:45 UTC (permalink / raw)
To: lars.poeschel.linux, Mark Brown, linux-spi, linux-arm-kernel,
linux-kernel
Cc: Amit Kumar, Lars Pöschel
In-Reply-To: <20260612105244.9076-1-lars.poeschel.linux@edag.com>
On 6/12/26 12:52, lars.poeschel.linux@edag.com wrote:
> From: Lars Pöschel <lars.poeschel@edag.com>
>
> The method the driver uses to determine the size of the FIFO has a
> problem. What it currently does is this:
> It stops the SPI hardware and writes to the TX FIFO register until TX
> FIFO FULL asserts in the status register. But the hardware does not only
> have the FIFO, it also has a shift register which can hold a byte. This
> can be seen, when writing a byte to the FIFO (while the SPI hardware is
> stopped,) the TX FIFO EMPTY is still empty. So, if we have a FIFO size
> of 16 for example, the current method returns a 17.
> This is a problem, at least when using the driver in irq mode. The same
> size determined for the TX FIFO is also assumed for the RX FIFO. When a
> SPI transaction wants to write the amount of the FIFO size or more
> bytes, the following happens, for example with 16 bytes FIFO size:
> The driver stops the SPI hardware and writes 17 bytes to the TX FIFO and
> starts the SPI hardware and goes sleep.
> The hardware then shifts out 17 bytes (FIFO + shift register) and
> simultaneously reads bytes into the RX FIFO, but it only has 16 places,
> so it looses one byte. Then TX FIFO empty asserts, wakes the driver
> again, which has a fast path and reads 16 bytes from the RX FIFO, but
> before reading the last 17th byte (which is lost) it does this:
>
> sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
> if (!(sr & XSPI_SR_RX_EMPTY_MASK)) {
> xilinx_spi_rx(xspi);
> rx_words--;
> }
>
> It reads the status register and checks if the RX FIFO is not empty.
> But it is empty in our case. So this check spins in a while loop
> forever locking the driver.
>
> This patch fixes the logic to determine the FIFO size.
>
> Fixes: 4c9a761402d7 ("spi/xilinx: Simplify spi_fill_tx_fifo")
> Signed-off-by: Lars Pöschel <lars.poeschel@edag.com>
> ---
> drivers/spi/spi-xilinx.c | 11 +++++++++--
> 1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/spi/spi-xilinx.c b/drivers/spi/spi-xilinx.c
> index 9f065d4e27d1..b95485710e2f 100644
> --- a/drivers/spi/spi-xilinx.c
> +++ b/drivers/spi/spi-xilinx.c
> @@ -371,11 +371,18 @@ static int xilinx_spi_find_buffer_size(struct xilinx_spi *xspi)
> xspi->regs + XIPIF_V123B_RESETR_OFFSET);
>
> /* Fill the Tx FIFO with as many words as possible */
> - do {
> + while (1) {
> xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
> sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
> + if (sr & XSPI_SR_TX_FULL_MASK)
> + break;
> +
> n_words++;
> - } while (!(sr & XSPI_SR_TX_FULL_MASK));
> + }
> +
> + /* Handle the NO FIFO case separately */
> + if (!n_words)
> + return 1;
>
> return n_words;
> }
Reviewed-by: Michal Simek <michal.simek@amd.com>
Thanks,
Michal
^ permalink raw reply
* [PATCH v9 0/9] Add support for i.MX94 DCIF
From: Laurentiu Palcu @ 2026-06-12 11:58 UTC (permalink / raw)
To: Ying Liu, Luca Ceresoli, Abel Vesa, Peng Fan, Michael Turquette,
Stephen Boyd, Brian Masney, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Frank Li, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, Andrzej Hajda, Neil Armstrong, Robert Foss,
Laurent Pinchart, Jonas Karlman, Jernej Skrabec, David Airlie,
Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Philipp Zabel, Marek Vasut
Cc: Laurentiu Palcu, linux-clk, imx, devicetree, linux-arm-kernel,
linux-kernel, dri-devel
Hi,
This patch-set adds support for the i.MX94 Display Control Interface.
Also, included in the patch-set is patch that the DCIF driver depends on
for functioning properly:
* 1/9 - 3/9 : add support for i.MX94 to fsl-ldb driver. It also
contains a patch (2/9) from Liu Ying that was already reviewed
and was part of another patch-set ([1]), but was never merged;
Thanks,
Laurentiu
[1] https://lkml.org/lkml/2024/11/14/262
---
Changes in v9:
- Rebased to latest linux-next (next-20260611);
- 2/9: Reworked to store the next bridge in fsl_ldb->bridge.next_bridge
(taking a reference with drm_bridge_get()) instead of adding a new
dedicated field. Removed the r-b tags for this patch since it needs a
fresh review;
- 3/9: Fixed the i.MX94 LDB max_clk_khz limit (165 MHz -> 148.5 MHz) to
match the actual hardware limit. Removed the r-b tags for this patch
since it needs a fresh review;
- 4/9: Added a 'required:' properties list to the binding. Removed
Krzysztof's r-b tag for this patch since it needs a fresh review;
- 5/9: Renamed the CRC source helpers (dcif_crc_source_*) and made them
unconditionally available, dropping the CONFIG_DEBUG_FS stubs;
improved CRC source parsing (auto ROI for the full-frame source,
unsigned params, safer string handling); rebased onto the
drm_atomic_state -> drm_atomic_commit rename in linux-next; reworked
CRC/modeset gating with new has_crc and crtc_pm_enabled flags and
proper PM error handling; switched event_lock to spinlock_irq; removed
a redundant connector-attach call and fixed an error format string;
added new pixel formats and full alpha/blend-mode support;
- 6/9: YAML quoting style fix only, no functional change;
- 7/9: Combined the former "arm64: dts: imx943: Add LVDS/DISPLAY CSR
nodes" prerequisite and the "arm64: dts: imx943: Add display pipeline
nodes" patch into a single new patch targeting the shared imx94.dtsi
instead of imx943.dtsi, removing the dependency on Peng Fan's
not-yet-merged patch;
- 8/9: Renamed the IT6263 bridge node to 'hdmi@4c' and fixed its
reset-gpios polarity to GPIO_ACTIVE_LOW;
- Link to v8: https://lore.kernel.org/r/20260304-dcif-upstreaming-v8-0-bec5c047edd4@oss.nxp.com
Changes in v8:
- Rebased to latest linux-next (next-20260303). Patch 2/9 had a minor
conflict bacause of a patch introduced recently;
- 8/9: Fixed CHECK_DTBS errors reported by Rob's bot due to missing
regulators. Removed the r-b tag for this patch because it needs a
fresh review;
- Link to v7: https://lore.kernel.org/r/20260122-dcif-upstreaming-v7-0-19ea17eb046f@oss.nxp.com
Changes in v7:
- Rebased to latest linux-next;
- Addressed some new checkpatch warnings: kzalloc -> kzalloc_obj;
- Fixed a couple of static check warnings in probe();
- Added Luca's r-b tag for bridge refcounting;
- Link to v6: https://lore.kernel.org/r/20251103-dcif-upstreaming-v6-0-76fcecfda919@oss.nxp.com
Changes in v6:
- 2/9: Collected r-b tag from Francesco;
- 3/9: Removed ch_max_clk_khz variable as suggested by Luca and added
his r-b tag;
- 4/9: Collected r-b tag;
- 5/9: Call drm_bridge_put() automatically in
dcif_crtc_query_output_bus_format() by using a cleanup action (Luca);
- 6/9: Moved allOf: block after required: block (Krzysztof). Collected
r-b tag;
- Link to v5: https://lore.kernel.org/r/20250911-dcif-upstreaming-v5-0-a1e8dab8ae40@oss.nxp.com
Changes in v5:
- 4/9: Removed "bindings for" from the title, changed the port
definition and simplified the example;
- 6/9: Fixed the way 'ldb' child node is declared: declare the
'ldb' child node out of if:then: block and set the property
to false for compatibles other than nxp,imx94-lvds-csr;
- Link to v4: https://lore.kernel.org/r/20250903123332.2569241-1-laurentiu.palcu@oss.nxp.com
Changes in v4:
- Addressed remaining DCIF driver comments from Frank;
- Limit the 'ldb' child node only to CSRs compatible with 'nxp,imx94-lvds-csr'
in the binding file. Since LVDS CSRs are a minority, I chose to
use the if:then: construct instead of if:not:then:;
- Remove the '#address-cells' and '#size-cells' from the ldb node, in
imx94.dtsi, as they're not needed;
- Link to v3: https://lore.kernel.org/r/20250806150521.2174797-1-laurentiu.palcu@oss.nxp.com
Changes in v3:
- Removed the BLK CTL patches and created a separate patch set [2] for them;
- Collected r-b tags for 1/9, 2/9, 3/9 and 9/9;
- Removed the DCIF QoS functionality until I find a better way to
implement it through syscon. QoS functionality will be added in
subsequent patches. Also, used devm_clk_bulk_get_all() and used
dev_err_probe() as suggested;
- Addressed Frank's and Krzysztof's comments on the DCIF bindings;
- Addressed Frank's comments on dtsi and dts files;
- Added a new binding patch, 6/9, for adding 'ldb' optional property to
nxp,imx95-blk-ctl.yaml;
- Link to v2: https://lore.kernel.org/r/20250716081519.3400158-1-laurentiu.palcu@oss.nxp.com
Changes in v2:
- reworked the BLK_CTL patch and split in 2 to make it easier for
review;
- split the dts and dtsi patch in 2 separate ones;
- addressed Frank's comments in DCIF driver;
- addressed Rob's comments for the bindings files;
- addressed a couple of checkpatch issues;
- Link to v1: https://lore.kernel.org/r/20250709122332.2874632-1-laurentiu.palcu@oss.nxp.com
---
Laurentiu Palcu (7):
dt-bindings: display: fsl,ldb: Add i.MX94 LDB
drm/bridge: fsl-ldb: Add support for i.MX94
dt-bindings: display: imx: Add i.MX94 DCIF
dt-bindings: clock: nxp,imx95-blk-ctl: Add ldb child node
arm64: dts: imx94: Add display pipeline nodes
arm64: dts: imx943-evk: Add display support using IT6263
MAINTAINERS: Add entry for i.MX94 DCIF driver
Liu Ying (1):
drm/bridge: fsl-ldb: Get the next non-panel bridge
Sandor Yu (1):
drm/imx: Add support for i.MX94 DCIF
.../bindings/clock/nxp,imx95-blk-ctl.yaml | 26 +
.../bindings/display/bridge/fsl,ldb.yaml | 2 +
.../bindings/display/imx/nxp,imx94-dcif.yaml | 90 +++
MAINTAINERS | 9 +
arch/arm64/boot/dts/freescale/imx94.dtsi | 82 +++
arch/arm64/boot/dts/freescale/imx943-evk.dts | 86 +++
drivers/gpu/drm/bridge/fsl-ldb.c | 46 +-
drivers/gpu/drm/imx/Kconfig | 1 +
drivers/gpu/drm/imx/Makefile | 1 +
drivers/gpu/drm/imx/dcif/Kconfig | 15 +
drivers/gpu/drm/imx/dcif/Makefile | 5 +
drivers/gpu/drm/imx/dcif/dcif-crc.c | 215 +++++++
drivers/gpu/drm/imx/dcif/dcif-crc.h | 43 ++
drivers/gpu/drm/imx/dcif/dcif-crtc.c | 705 +++++++++++++++++++++
drivers/gpu/drm/imx/dcif/dcif-drv.c | 233 +++++++
drivers/gpu/drm/imx/dcif/dcif-drv.h | 89 +++
drivers/gpu/drm/imx/dcif/dcif-kms.c | 96 +++
drivers/gpu/drm/imx/dcif/dcif-plane.c | 308 +++++++++
drivers/gpu/drm/imx/dcif/dcif-reg.h | 267 ++++++++
19 files changed, 2299 insertions(+), 20 deletions(-)
---
base-commit: e7b907ffb2cd66314df92360e41f7bd5fdaa8182
change-id: 20260602-dcif-upstreaming-fb177f3c9351
Best regards,
--
Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
^ permalink raw reply
* [PATCH v9 2/9] drm/bridge: fsl-ldb: Get the next non-panel bridge
From: Laurentiu Palcu @ 2026-06-12 11:58 UTC (permalink / raw)
To: Ying Liu, Luca Ceresoli, Andrzej Hajda, Neil Armstrong,
Robert Foss, Laurent Pinchart, Jonas Karlman, Jernej Skrabec,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter
Cc: Laurentiu Palcu, linux-clk, imx, devicetree, linux-arm-kernel,
linux-kernel, dri-devel
In-Reply-To: <20260612-dcif-upstreaming-v9-0-8d0ff89aa3c5@oss.nxp.com>
From: Liu Ying <victor.liu@nxp.com>
The next bridge in bridge chain could be a panel bridge or a non-panel
bridge. Use devm_drm_of_get_bridge() to replace the combination
function calls of of_drm_find_panel() and devm_drm_panel_bridge_add()
to get either a panel bridge or a non-panel bridge, instead of getting
a panel bridge only.
Signed-off-by: Liu Ying <victor.liu@nxp.com>
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
---
drivers/gpu/drm/bridge/fsl-ldb.c | 31 ++++++++++++-------------------
1 file changed, 12 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/bridge/fsl-ldb.c b/drivers/gpu/drm/bridge/fsl-ldb.c
index 9bfaa3f933709..bd03c36ee696c 100644
--- a/drivers/gpu/drm/bridge/fsl-ldb.c
+++ b/drivers/gpu/drm/bridge/fsl-ldb.c
@@ -15,7 +15,6 @@
#include <drm/drm_atomic_helper.h>
#include <drm/drm_bridge.h>
#include <drm/drm_of.h>
-#include <drm/drm_panel.h>
#define LDB_CTRL_CH0_ENABLE BIT(0)
#define LDB_CTRL_CH0_DI_SELECT BIT(1)
@@ -86,7 +85,6 @@ static const struct fsl_ldb_devdata fsl_ldb_devdata[] = {
struct fsl_ldb {
struct device *dev;
struct drm_bridge bridge;
- struct drm_bridge *panel_bridge;
struct clk *clk;
struct regmap *regmap;
const struct fsl_ldb_devdata *devdata;
@@ -119,7 +117,7 @@ static int fsl_ldb_attach(struct drm_bridge *bridge,
{
struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge);
- return drm_bridge_attach(encoder, fsl_ldb->panel_bridge,
+ return drm_bridge_attach(encoder, fsl_ldb->bridge.next_bridge,
bridge, flags);
}
@@ -296,9 +294,8 @@ static const struct drm_bridge_funcs funcs = {
static int fsl_ldb_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
- struct device_node *panel_node;
struct device_node *remote1, *remote2;
- struct drm_panel *panel;
+ struct drm_bridge *next_bridge;
struct fsl_ldb *fsl_ldb;
int dual_link;
@@ -321,36 +318,32 @@ static int fsl_ldb_probe(struct platform_device *pdev)
if (IS_ERR(fsl_ldb->regmap))
return PTR_ERR(fsl_ldb->regmap);
- /* Locate the remote ports and the panel node */
+ /* Locate the remote ports. */
remote1 = of_graph_get_remote_node(dev->of_node, 1, 0);
remote2 = of_graph_get_remote_node(dev->of_node, 2, 0);
fsl_ldb->ch0_enabled = (remote1 != NULL);
fsl_ldb->ch1_enabled = (remote2 != NULL);
- panel_node = of_node_get(remote1 ? remote1 : remote2);
of_node_put(remote1);
of_node_put(remote2);
- if (!fsl_ldb->ch0_enabled && !fsl_ldb->ch1_enabled) {
- of_node_put(panel_node);
- return dev_err_probe(dev, -ENXIO, "No panel node found");
- }
+ if (!fsl_ldb->ch0_enabled && !fsl_ldb->ch1_enabled)
+ return dev_err_probe(dev, -ENXIO, "No next bridge node found");
dev_dbg(dev, "Using %s\n",
fsl_ldb_is_dual(fsl_ldb) ? "dual-link mode" :
fsl_ldb->ch0_enabled ? "channel 0" : "channel 1");
- panel = of_drm_find_panel(panel_node);
- of_node_put(panel_node);
- if (IS_ERR(panel))
- return PTR_ERR(panel);
-
if (of_property_present(dev->of_node, "nxp,enable-termination-resistor"))
fsl_ldb->use_termination_resistor = true;
- fsl_ldb->panel_bridge = devm_drm_panel_bridge_add(dev, panel);
- if (IS_ERR(fsl_ldb->panel_bridge))
- return PTR_ERR(fsl_ldb->panel_bridge);
+ next_bridge = devm_drm_of_get_bridge(dev, dev->of_node,
+ fsl_ldb->ch0_enabled ? 1 : 2,
+ 0);
+ if (IS_ERR(next_bridge))
+ return dev_err_probe(dev, PTR_ERR(next_bridge),
+ "failed to get next bridge\n");
+ fsl_ldb->bridge.next_bridge = drm_bridge_get(next_bridge);
if (fsl_ldb_is_dual(fsl_ldb)) {
struct device_node *port1, *port2;
--
2.51.0
^ permalink raw reply related
* [PATCH v9 1/9] dt-bindings: display: fsl,ldb: Add i.MX94 LDB
From: Laurentiu Palcu @ 2026-06-12 11:58 UTC (permalink / raw)
To: Ying Liu, Luca Ceresoli, Andrzej Hajda, Neil Armstrong,
Robert Foss, Laurent Pinchart, Jonas Karlman, Jernej Skrabec,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Marek Vasut
Cc: Laurentiu Palcu, linux-clk, imx, devicetree, linux-arm-kernel,
linux-kernel, dri-devel
In-Reply-To: <20260612-dcif-upstreaming-v9-0-8d0ff89aa3c5@oss.nxp.com>
i.MX94 has a single LVDS port and share similar LDB and LVDS control
registers as i.MX8MP and i.MX93.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml
index 7f380879fffdf..fb70409161fc0 100644
--- a/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml
+++ b/Documentation/devicetree/bindings/display/bridge/fsl,ldb.yaml
@@ -20,6 +20,7 @@ properties:
- fsl,imx6sx-ldb
- fsl,imx8mp-ldb
- fsl,imx93-ldb
+ - fsl,imx94-ldb
clocks:
maxItems: 1
@@ -78,6 +79,7 @@ allOf:
enum:
- fsl,imx6sx-ldb
- fsl,imx93-ldb
+ - fsl,imx94-ldb
then:
properties:
ports:
--
2.51.0
^ permalink raw reply related
* [PATCH v9 3/9] drm/bridge: fsl-ldb: Add support for i.MX94
From: Laurentiu Palcu @ 2026-06-12 11:58 UTC (permalink / raw)
To: Ying Liu, Luca Ceresoli, Andrzej Hajda, Neil Armstrong,
Robert Foss, Laurent Pinchart, Jonas Karlman, Jernej Skrabec,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter
Cc: Laurentiu Palcu, linux-clk, imx, devicetree, linux-arm-kernel,
linux-kernel, dri-devel
In-Reply-To: <20260612-dcif-upstreaming-v9-0-8d0ff89aa3c5@oss.nxp.com>
i.MX94 series LDB controller shares the same LDB and LVDS control
registers as i.MX8MP and i.MX93 but supports a higher maximum clock
frequency.
Add a 'max_clk_khz' member to the fsl_ldb_devdata structure in order to
be able to set different max frequencies for other platforms.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
---
drivers/gpu/drm/bridge/fsl-ldb.c | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/bridge/fsl-ldb.c b/drivers/gpu/drm/bridge/fsl-ldb.c
index bd03c36ee696c..b4959f654f2ac 100644
--- a/drivers/gpu/drm/bridge/fsl-ldb.c
+++ b/drivers/gpu/drm/bridge/fsl-ldb.c
@@ -57,6 +57,7 @@ enum fsl_ldb_devtype {
IMX6SX_LDB,
IMX8MP_LDB,
IMX93_LDB,
+ IMX94_LDB,
};
struct fsl_ldb_devdata {
@@ -64,21 +65,31 @@ struct fsl_ldb_devdata {
u32 lvds_ctrl;
bool lvds_en_bit;
bool single_ctrl_reg;
+ u32 max_clk_khz;
};
static const struct fsl_ldb_devdata fsl_ldb_devdata[] = {
[IMX6SX_LDB] = {
.ldb_ctrl = 0x18,
.single_ctrl_reg = true,
+ .max_clk_khz = 80000,
},
[IMX8MP_LDB] = {
.ldb_ctrl = 0x5c,
.lvds_ctrl = 0x128,
+ .max_clk_khz = 80000,
},
[IMX93_LDB] = {
.ldb_ctrl = 0x20,
.lvds_ctrl = 0x24,
.lvds_en_bit = true,
+ .max_clk_khz = 80000,
+ },
+ [IMX94_LDB] = {
+ .ldb_ctrl = 0x04,
+ .lvds_ctrl = 0x08,
+ .lvds_en_bit = true,
+ .max_clk_khz = 148500,
},
};
@@ -274,7 +285,7 @@ fsl_ldb_mode_valid(struct drm_bridge *bridge,
{
struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge);
- if (mode->clock > (fsl_ldb_is_dual(fsl_ldb) ? 160000 : 80000))
+ if (mode->clock > (fsl_ldb_is_dual(fsl_ldb) ? 2 : 1) * fsl_ldb->devdata->max_clk_khz)
return MODE_CLOCK_HIGH;
return MODE_OK;
@@ -386,6 +397,8 @@ static const struct of_device_id fsl_ldb_match[] = {
.data = &fsl_ldb_devdata[IMX8MP_LDB], },
{ .compatible = "fsl,imx93-ldb",
.data = &fsl_ldb_devdata[IMX93_LDB], },
+ { .compatible = "fsl,imx94-ldb",
+ .data = &fsl_ldb_devdata[IMX94_LDB], },
{ /* sentinel */ },
};
MODULE_DEVICE_TABLE(of, fsl_ldb_match);
--
2.51.0
^ permalink raw reply related
* [PATCH v9 4/9] dt-bindings: display: imx: Add i.MX94 DCIF
From: Laurentiu Palcu @ 2026-06-12 11:58 UTC (permalink / raw)
To: Ying Liu, Luca Ceresoli, Philipp Zabel, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, David Airlie, Simona Vetter,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: Laurentiu Palcu, linux-clk, imx, devicetree, linux-arm-kernel,
linux-kernel, dri-devel
In-Reply-To: <20260612-dcif-upstreaming-v9-0-8d0ff89aa3c5@oss.nxp.com>
DCIF is the i.MX94 Display Controller Interface which is used to
drive a TFT LCD panel or connects to a display interface depending
on the chip configuration.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
---
.../bindings/display/imx/nxp,imx94-dcif.yaml | 90 ++++++++++++++++++++++
1 file changed, 90 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/imx/nxp,imx94-dcif.yaml b/Documentation/devicetree/bindings/display/imx/nxp,imx94-dcif.yaml
new file mode 100644
index 0000000000000..8894e87666972
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/nxp,imx94-dcif.yaml
@@ -0,0 +1,90 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2025 NXP
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/nxp,imx94-dcif.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: i.MX94 Display Control Interface (DCIF)
+
+maintainers:
+ - Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
+
+description:
+ The Display Control Interface(DCIF) is a system master that fetches graphics
+ stored in memory and displays them on a TFT LCD panel or connects to a
+ display interface depending on the chip configuration.
+
+properties:
+ compatible:
+ const: nxp,imx94-dcif
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ items:
+ - description: CPU domain 0 (controlled by common registers group).
+ - description: CPU domain 1 (controlled by background layer registers group).
+ - description: CPU domain 2 (controlled by foreground layer registers group).
+
+ interrupt-names:
+ items:
+ - const: common
+ - const: bg_layer
+ - const: fg_layer
+
+ clocks:
+ maxItems: 3
+
+ clock-names:
+ items:
+ - const: apb
+ - const: axi
+ - const: pix
+
+ power-domains:
+ maxItems: 1
+
+ port:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+ description: Display Pixel Interface(DPI) output port
+
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - power-domains
+ - port
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ display-controller@4b120000 {
+ compatible = "nxp,imx94-dcif";
+ reg = <0x4b120000 0x300000>;
+ interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "common", "bg_layer", "fg_layer";
+ clocks = <&scmi_clk 69>, <&scmi_clk 70>, <&dispmix_csr 0>;
+ clock-names = "apb", "axi", "pix";
+ assigned-clocks = <&dispmix_csr 0>;
+ assigned-clock-parents = <&ldb_pll_pixel>;
+ power-domains = <&scmi_devpd 11>;
+ port {
+ dcif_out: endpoint {
+ remote-endpoint = <&ldb_in>;
+ };
+ };
+ };
--
2.51.0
^ permalink raw reply related
* [PATCH v9 5/9] drm/imx: Add support for i.MX94 DCIF
From: Laurentiu Palcu @ 2026-06-12 11:58 UTC (permalink / raw)
To: Ying Liu, Luca Ceresoli, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: Laurentiu Palcu, linux-clk, imx, devicetree, linux-arm-kernel,
linux-kernel, dri-devel
In-Reply-To: <20260612-dcif-upstreaming-v9-0-8d0ff89aa3c5@oss.nxp.com>
From: Sandor Yu <sandor.yu@nxp.com>
The i.MX94 Display Control Interface features:
* Up to maximum 3 layers of alpha blending:
- 1 background layer(Layer 0);
- 1 foreground layer(Layer 1);
- A programmable constant color behind the background layer;
* Each layer supports:
- programmable plane size;
- programmable background color;
- embedded alpha and global alpha;
* Data output with CRC checksum for 4 programmable regions;
Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com> # bridge refcounting
Signed-off-by: Sandor Yu <sandor.yu@nxp.com>
Co-developed-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
---
drivers/gpu/drm/imx/Kconfig | 1 +
drivers/gpu/drm/imx/Makefile | 1 +
drivers/gpu/drm/imx/dcif/Kconfig | 15 +
drivers/gpu/drm/imx/dcif/Makefile | 5 +
drivers/gpu/drm/imx/dcif/dcif-crc.c | 215 +++++++++++
drivers/gpu/drm/imx/dcif/dcif-crc.h | 43 +++
drivers/gpu/drm/imx/dcif/dcif-crtc.c | 705 ++++++++++++++++++++++++++++++++++
drivers/gpu/drm/imx/dcif/dcif-drv.c | 233 +++++++++++
drivers/gpu/drm/imx/dcif/dcif-drv.h | 89 +++++
drivers/gpu/drm/imx/dcif/dcif-kms.c | 96 +++++
drivers/gpu/drm/imx/dcif/dcif-plane.c | 308 +++++++++++++++
drivers/gpu/drm/imx/dcif/dcif-reg.h | 267 +++++++++++++
12 files changed, 1978 insertions(+)
diff --git a/drivers/gpu/drm/imx/Kconfig b/drivers/gpu/drm/imx/Kconfig
index 3e8c6edbc17c2..1b6ced5c60b51 100644
--- a/drivers/gpu/drm/imx/Kconfig
+++ b/drivers/gpu/drm/imx/Kconfig
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only
source "drivers/gpu/drm/imx/dc/Kconfig"
+source "drivers/gpu/drm/imx/dcif/Kconfig"
source "drivers/gpu/drm/imx/dcss/Kconfig"
source "drivers/gpu/drm/imx/ipuv3/Kconfig"
source "drivers/gpu/drm/imx/lcdc/Kconfig"
diff --git a/drivers/gpu/drm/imx/Makefile b/drivers/gpu/drm/imx/Makefile
index c7b317640d71d..2b9fd85eefaa3 100644
--- a/drivers/gpu/drm/imx/Makefile
+++ b/drivers/gpu/drm/imx/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_DRM_IMX8_DC) += dc/
+obj-$(CONFIG_DRM_IMX_DCIF) += dcif/
obj-$(CONFIG_DRM_IMX_DCSS) += dcss/
obj-$(CONFIG_DRM_IMX) += ipuv3/
obj-$(CONFIG_DRM_IMX_LCDC) += lcdc/
diff --git a/drivers/gpu/drm/imx/dcif/Kconfig b/drivers/gpu/drm/imx/dcif/Kconfig
new file mode 100644
index 0000000000000..c33c662721d36
--- /dev/null
+++ b/drivers/gpu/drm/imx/dcif/Kconfig
@@ -0,0 +1,15 @@
+config DRM_IMX_DCIF
+ tristate "DRM support for NXP i.MX94 DCIF"
+ select DRM_KMS_HELPER
+ select VIDEOMODE_HELPERS
+ select DRM_GEM_DMA_HELPER
+ select DRM_DISPLAY_HELPER
+ select DRM_BRIDGE_CONNECTOR
+ select DRM_CLIENT_SELECTION
+ depends on DRM && OF && ARCH_MXC
+ depends on COMMON_CLK
+ help
+ Enable NXP i.MX94 Display Control Interface(DCIF) support. The DCIF is
+ a system master that fetches graphics stored in memory and displays
+ them on a TFT LCD panel or connects to a display interface depending
+ on the chip configuration.
diff --git a/drivers/gpu/drm/imx/dcif/Makefile b/drivers/gpu/drm/imx/dcif/Makefile
new file mode 100644
index 0000000000000..b429572040f0e
--- /dev/null
+++ b/drivers/gpu/drm/imx/dcif/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0
+
+imx-dcif-drm-objs := dcif-crc.o dcif-crtc.o dcif-drv.o dcif-kms.o dcif-plane.o
+
+obj-$(CONFIG_DRM_IMX_DCIF) += imx-dcif-drm.o
diff --git a/drivers/gpu/drm/imx/dcif/dcif-crc.c b/drivers/gpu/drm/imx/dcif/dcif-crc.c
new file mode 100644
index 0000000000000..dee36e5ca6793
--- /dev/null
+++ b/drivers/gpu/drm/imx/dcif/dcif-crc.c
@@ -0,0 +1,215 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+ * Copyright 2025 NXP
+ */
+
+#include <linux/regmap.h>
+
+#include <drm/drm_atomic.h>
+#include <drm/drm_rect.h>
+
+#include "dcif-crc.h"
+#include "dcif-reg.h"
+
+#define MAX_DCIF_CRC_NUM 4
+
+static int dcif_crc_config(struct dcif_dev *dcif, struct drm_rect *roi, int ncrc)
+{
+ int pos, size;
+
+ if (ncrc >= MAX_DCIF_CRC_NUM)
+ return -EINVAL;
+
+ pos = DCIF_CRC_POS_CRC_HOR_POS(roi->x1) |
+ DCIF_CRC_POS_CRC_VER_POS(roi->y1);
+ size = DCIF_CRC_SIZE_CRC_HOR_SIZE(roi->x2 - roi->x1) |
+ DCIF_CRC_SIZE_CRC_VER_SIZE(roi->y2 - roi->y1);
+
+ regmap_write(dcif->regmap, DCIF_CRC_POS_R(ncrc), pos);
+ regmap_write(dcif->regmap, DCIF_CRC_SIZE_R(ncrc), size);
+
+ regmap_set_bits(dcif->regmap, DCIF_CRC_CTRL,
+ DCIF_CRC_CTRL_CRC_EN(ncrc) | DCIF_CRC_CTRL_CRC_ERR_CNT_RST);
+
+ return 0;
+}
+
+void dcif_crc_source_enable(struct dcif_dev *dcif, enum dcif_crc_source source,
+ struct drm_rect *roi, int ncrc)
+{
+ if (ncrc >= MAX_DCIF_CRC_NUM)
+ return;
+
+ if (source == DCIF_CRC_SRC_NONE)
+ return;
+
+ if (dcif->crc_is_enabled)
+ return;
+
+ dcif_crc_config(dcif, roi, ncrc);
+
+ regmap_set_bits(dcif->regmap, DCIF_CRC_CTRL,
+ DCIF_CRC_CTRL_CRC_MODE | DCIF_CRC_CTRL_CRC_SHADOW_LOAD_EN |
+ DCIF_CRC_CTRL_CRC_TRIG);
+
+ dcif->crc_is_enabled = true;
+}
+
+void dcif_crc_source_disable(struct dcif_dev *dcif, int ncrc)
+{
+ if (!dcif->crc_is_enabled)
+ return;
+
+ if (ncrc >= MAX_DCIF_CRC_NUM)
+ return;
+
+ regmap_clear_bits(dcif->regmap, DCIF_CRC_CTRL, DCIF_CRC_CTRL_CRC_EN(ncrc));
+
+ dcif->crc_is_enabled = false;
+}
+
+/*
+ * Supported modes and source names:
+ * 1) auto mode:
+ * "auto" should be selected as the source name.
+ * The evaluation window is the same to the display region as
+ * indicated by drm_crtc_state->adjusted_mode.
+ *
+ * 2) region of interest(ROI) mode:
+ * "roi:x1,y1,x2,y2" should be selected as the source name.
+ * The region of interest is defined by the inclusive upper left
+ * position at (x1, y1) and the exclusive lower right position
+ * at (x2, y2), see struct drm_rect for the same idea.
+ * The evaluation window is the region of interest.
+ */
+static int dcif_crc_source_parse(struct drm_crtc *crtc, const char *source_name,
+ enum dcif_crc_source *s, struct drm_rect *roi)
+{
+ static const char roi_prefix[] = "roi:";
+
+ if (!source_name) {
+ *s = DCIF_CRC_SRC_NONE;
+ } else if (!strcmp(source_name, "auto")) {
+ struct drm_display_mode *mode = &crtc->state->adjusted_mode;
+
+ roi->x1 = 0;
+ roi->y1 = 0;
+ roi->x2 = mode->hdisplay;
+ roi->y2 = mode->vdisplay;
+
+ *s = DCIF_CRC_SRC_FRAME;
+ } else if (strstarts(source_name, roi_prefix)) {
+ int len = strlen(roi_prefix);
+ unsigned int params[4];
+ char *options, *opt;
+ int i = 0, ret;
+
+ char *buf __free(kfree) = kstrdup(source_name + len, GFP_KERNEL);
+ if (!buf)
+ return -ENOMEM;
+
+ options = buf;
+
+ while ((opt = strsep(&options, ",")) != NULL) {
+ if (i > 3)
+ return -EINVAL;
+
+ ret = kstrtouint(opt, 10, ¶ms[i]);
+ if (ret < 0)
+ return ret;
+
+ i++;
+ }
+
+ if (i != 4)
+ return -EINVAL;
+
+ roi->x1 = params[0];
+ roi->y1 = params[1];
+ roi->x2 = params[2];
+ roi->y2 = params[3];
+
+ if (!drm_rect_visible(roi))
+ return -EINVAL;
+
+ *s = DCIF_CRC_SRC_FRAME_ROI;
+ } else {
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+int dcif_crc_source_verify(struct drm_crtc *crtc, const char *source_name,
+ size_t *values_cnt)
+{
+ struct dcif_dev *dcif = crtc_to_dcif_dev(crtc);
+ enum dcif_crc_source source;
+ struct drm_rect roi;
+
+ if (dcif_crc_source_parse(crtc, source_name, &source, &roi) < 0) {
+ dev_dbg(dcif->drm.dev, "unknown source %s\n", source_name);
+ return -EINVAL;
+ }
+
+ *values_cnt = 1;
+
+ return 0;
+}
+
+int dcif_crc_source_set(struct drm_crtc *crtc, const char *source_name)
+{
+ struct dcif_dev *dcif = crtc_to_dcif_dev(crtc);
+ struct drm_modeset_acquire_ctx ctx;
+ struct drm_crtc_state *crtc_state;
+ struct drm_atomic_commit *state;
+ struct drm_rect roi = {0, 0, 0, 0};
+ enum dcif_crc_source source;
+ int ret;
+
+ if (dcif_crc_source_parse(crtc, source_name, &source, &roi) < 0) {
+ dev_dbg(dcif->drm.dev, "unknown source %s\n", source_name);
+ return -EINVAL;
+ }
+
+ /* Perform an atomic commit to set the CRC source. */
+ drm_modeset_acquire_init(&ctx, 0);
+
+ state = drm_atomic_commit_alloc(crtc->dev);
+ if (!state) {
+ ret = -ENOMEM;
+ goto unlock;
+ }
+
+ state->acquire_ctx = &ctx;
+
+retry:
+ crtc_state = drm_atomic_get_crtc_state(state, crtc);
+ if (!IS_ERR(crtc_state)) {
+ struct dcif_crtc_state *dcif_crtc_state;
+
+ dcif_crtc_state = to_dcif_crtc_state(crtc_state);
+
+ dcif_crtc_state->crc.source = source;
+ dcif_copy_roi(&roi, &dcif_crtc_state->crc.roi);
+
+ ret = drm_atomic_commit(state);
+ } else {
+ ret = PTR_ERR(crtc_state);
+ }
+
+ if (ret == -EDEADLK) {
+ drm_atomic_commit_clear(state);
+ drm_modeset_backoff(&ctx);
+ goto retry;
+ }
+
+ drm_atomic_commit_put(state);
+
+unlock:
+ drm_modeset_drop_locks(&ctx);
+ drm_modeset_acquire_fini(&ctx);
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/imx/dcif/dcif-crc.h b/drivers/gpu/drm/imx/dcif/dcif-crc.h
new file mode 100644
index 0000000000000..6ccb1b7186732
--- /dev/null
+++ b/drivers/gpu/drm/imx/dcif/dcif-crc.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+/*
+ * Copyright 2025 NXP
+ */
+
+#ifndef __DCIF_CRC_H__
+#define __DCIF_CRC_H__
+
+#include <linux/types.h>
+
+#include "dcif-drv.h"
+
+static inline bool enable_dcif_crc_needed(struct dcif_crtc_state *new_dcstate,
+ struct dcif_crtc_state *old_dcstate)
+{
+ return old_dcstate->crc.source == DCIF_CRC_SRC_NONE &&
+ new_dcstate->crc.source != DCIF_CRC_SRC_NONE;
+}
+
+static inline bool disable_dcif_crc_needed(struct dcif_crtc_state *new_dcstate,
+ struct dcif_crtc_state *old_dcstate)
+{
+ return old_dcstate->crc.source != DCIF_CRC_SRC_NONE &&
+ new_dcstate->crc.source == DCIF_CRC_SRC_NONE;
+}
+
+static inline void dcif_copy_roi(struct drm_rect *from, struct drm_rect *to)
+{
+ to->x1 = from->x1;
+ to->y1 = from->y1;
+ to->x2 = from->x2;
+ to->y2 = from->y2;
+}
+
+int dcif_crc_source_verify(struct drm_crtc *crtc, const char *source_name,
+ size_t *values_cnt);
+int dcif_crc_source_set(struct drm_crtc *crtc, const char *source_name);
+void dcif_crc_source_enable(struct dcif_dev *dcif, enum dcif_crc_source source,
+ struct drm_rect *roi, int ncrc);
+void dcif_crc_source_disable(struct dcif_dev *dcif, int ncrc);
+
+#endif /* __DCIF_CRC_H__ */
diff --git a/drivers/gpu/drm/imx/dcif/dcif-crtc.c b/drivers/gpu/drm/imx/dcif/dcif-crtc.c
new file mode 100644
index 0000000000000..1fa2dfb2e0b98
--- /dev/null
+++ b/drivers/gpu/drm/imx/dcif/dcif-crtc.c
@@ -0,0 +1,705 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+ * Copyright 2025 NXP
+ */
+
+#include <linux/irqreturn.h>
+#include <linux/media-bus-format.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_atomic_state_helper.h>
+#include <drm/drm_bridge.h>
+#include <drm/drm_fb_dma_helper.h>
+#include <drm/drm_fourcc.h>
+#include <drm/drm_framebuffer.h>
+#include <drm/drm_plane.h>
+#include <drm/drm_print.h>
+#include <drm/drm_vblank.h>
+
+#include "dcif-crc.h"
+#include "dcif-drv.h"
+#include "dcif-reg.h"
+
+#define DCIF_MAX_PIXEL_CLOCK 148500000
+
+/* -----------------------------------------------------------------------------
+ * CRTC
+ */
+
+/*
+ * For conversion from YCbCr to RGB, the CSC operates as follows:
+ *
+ * |R| |A1 A2 A3| |Y + D1|
+ * |G| = |B1 B2 B3| * |Cb + D2|
+ * |B| |C1 C2 C3| |Cr + D3|
+ *
+ * The A, B and C coefficients are expressed as signed Q3.8 fixed point values and
+ * the D coefficients as signed Q9.0.
+ */
+static const u32 dcif_yuv2rgb_coeffs[3][2][6] = {
+ [DRM_COLOR_YCBCR_BT601] = {
+ [DRM_COLOR_YCBCR_LIMITED_RANGE] = {
+ /*
+ * BT.601 limited range:
+ *
+ * |R| |1.1644 0.0000 1.5960| |Y - 16 |
+ * |G| = |1.1644 -0.3917 -0.8129| * |Cb - 128|
+ * |B| |1.1644 2.0172 0.0000| |Cr - 128|
+ */
+ DCIF_CSC_COEF0_L0_A1(0x12a) | DCIF_CSC_COEF0_L0_A2(0x000),
+ DCIF_CSC_COEF1_L0_A3(0x199) | DCIF_CSC_COEF1_L0_B1(0x12a),
+ DCIF_CSC_COEF2_L0_B2(0x79c) | DCIF_CSC_COEF2_L0_B3(0x730),
+ DCIF_CSC_COEF3_L0_C1(0x12a) | DCIF_CSC_COEF3_L0_C2(0x204),
+ DCIF_CSC_COEF4_L0_C3(0x000) | DCIF_CSC_COEF4_L0_D1(0x1f0),
+ DCIF_CSC_COEF5_L0_D2(0x180) | DCIF_CSC_COEF5_L0_D3(0x180),
+ },
+ [DRM_COLOR_YCBCR_FULL_RANGE] = {
+ /*
+ * BT.601 full range:
+ *
+ * |R| |1.0000 0.0000 1.4020| |Y - 0 |
+ * |G| = |1.0000 -0.3441 -0.7141| * |Cb - 128|
+ * |B| |1.0000 1.7720 0.0000| |Cr - 128|
+ */
+ DCIF_CSC_COEF0_L0_A1(0x100) | DCIF_CSC_COEF0_L0_A2(0x000),
+ DCIF_CSC_COEF1_L0_A3(0x167) | DCIF_CSC_COEF1_L0_B1(0x100),
+ DCIF_CSC_COEF2_L0_B2(0x7a8) | DCIF_CSC_COEF2_L0_B3(0x749),
+ DCIF_CSC_COEF3_L0_C1(0x100) | DCIF_CSC_COEF3_L0_C2(0x1c6),
+ DCIF_CSC_COEF4_L0_C3(0x000) | DCIF_CSC_COEF4_L0_D1(0x000),
+ DCIF_CSC_COEF5_L0_D2(0x180) | DCIF_CSC_COEF5_L0_D3(0x180),
+ },
+ },
+ [DRM_COLOR_YCBCR_BT709] = {
+ [DRM_COLOR_YCBCR_LIMITED_RANGE] = {
+ /*
+ * Rec.709 limited range:
+ *
+ * |R| |1.1644 0.0000 1.7927| |Y - 16 |
+ * |G| = |1.1644 -0.2132 -0.5329| * |Cb - 128|
+ * |B| |1.1644 2.1124 0.0000| |Cr - 128|
+ */
+ DCIF_CSC_COEF0_L0_A1(0x12a) | DCIF_CSC_COEF0_L0_A2(0x000),
+ DCIF_CSC_COEF1_L0_A3(0x1cb) | DCIF_CSC_COEF1_L0_B1(0x12a),
+ DCIF_CSC_COEF2_L0_B2(0x7c9) | DCIF_CSC_COEF2_L0_B3(0x778),
+ DCIF_CSC_COEF3_L0_C1(0x12a) | DCIF_CSC_COEF3_L0_C2(0x21d),
+ DCIF_CSC_COEF4_L0_C3(0x000) | DCIF_CSC_COEF4_L0_D1(0x1f0),
+ DCIF_CSC_COEF5_L0_D2(0x180) | DCIF_CSC_COEF5_L0_D3(0x180),
+ },
+ [DRM_COLOR_YCBCR_FULL_RANGE] = {
+ /*
+ * Rec.709 full range:
+ *
+ * |R| |1.0000 0.0000 1.5748| |Y - 0 |
+ * |G| = |1.0000 -0.1873 -0.4681| * |Cb - 128|
+ * |B| |1.0000 1.8556 0.0000| |Cr - 128|
+ */
+ DCIF_CSC_COEF0_L0_A1(0x100) | DCIF_CSC_COEF0_L0_A2(0x000),
+ DCIF_CSC_COEF1_L0_A3(0x193) | DCIF_CSC_COEF1_L0_B1(0x100),
+ DCIF_CSC_COEF2_L0_B2(0x7d0) | DCIF_CSC_COEF2_L0_B3(0x788),
+ DCIF_CSC_COEF3_L0_C1(0x100) | DCIF_CSC_COEF3_L0_C2(0x1db),
+ DCIF_CSC_COEF4_L0_C3(0x000) | DCIF_CSC_COEF4_L0_D1(0x000),
+ DCIF_CSC_COEF5_L0_D2(0x180) | DCIF_CSC_COEF5_L0_D3(0x180),
+ },
+ },
+ [DRM_COLOR_YCBCR_BT2020] = {
+ [DRM_COLOR_YCBCR_LIMITED_RANGE] = {
+ /*
+ * BT.2020 limited range:
+ *
+ * |R| |1.1644 0.0000 1.6787| |Y - 16 |
+ * |G| = |1.1644 -0.1874 -0.6505| * |Cb - 128|
+ * |B| |1.1644 2.1418 0.0000| |Cr - 128|
+ */
+ DCIF_CSC_COEF0_L0_A1(0x12a) | DCIF_CSC_COEF0_L0_A2(0x000),
+ DCIF_CSC_COEF1_L0_A3(0x1ae) | DCIF_CSC_COEF1_L0_B1(0x12a),
+ DCIF_CSC_COEF2_L0_B2(0x7d0) | DCIF_CSC_COEF2_L0_B3(0x759),
+ DCIF_CSC_COEF3_L0_C1(0x12a) | DCIF_CSC_COEF3_L0_C2(0x224),
+ DCIF_CSC_COEF4_L0_C3(0x000) | DCIF_CSC_COEF4_L0_D1(0x1f0),
+ DCIF_CSC_COEF5_L0_D2(0x180) | DCIF_CSC_COEF5_L0_D3(0x180),
+ },
+ [DRM_COLOR_YCBCR_FULL_RANGE] = {
+ /*
+ * BT.2020 full range:
+ *
+ * |R| |1.0000 0.0000 1.4746| |Y - 0 |
+ * |G| = |1.0000 -0.1646 -0.5714| * |Cb - 128|
+ * |B| |1.0000 1.8814 0.0000| |Cr - 128|
+ */
+ DCIF_CSC_COEF0_L0_A1(0x100) | DCIF_CSC_COEF0_L0_A2(0x000),
+ DCIF_CSC_COEF1_L0_A3(0x179) | DCIF_CSC_COEF1_L0_B1(0x100),
+ DCIF_CSC_COEF2_L0_B2(0x7d6) | DCIF_CSC_COEF2_L0_B3(0x76e),
+ DCIF_CSC_COEF3_L0_C1(0x100) | DCIF_CSC_COEF3_L0_C2(0x1e2),
+ DCIF_CSC_COEF4_L0_C3(0x000) | DCIF_CSC_COEF4_L0_D1(0x000),
+ DCIF_CSC_COEF5_L0_D2(0x180) | DCIF_CSC_COEF5_L0_D3(0x180),
+ },
+ },
+};
+
+static enum drm_mode_status dcif_crtc_mode_valid(struct drm_crtc *crtc,
+ const struct drm_display_mode *mode)
+{
+ if (mode->crtc_clock > DCIF_MAX_PIXEL_CLOCK)
+ return MODE_CLOCK_HIGH;
+
+ return MODE_OK;
+}
+
+static void dcif_set_formats(struct dcif_dev *dcif, struct drm_plane_state *plane_state,
+ const u32 bus_format)
+{
+ const u32 format = plane_state->fb->format->format;
+ struct drm_device *drm = &dcif->drm;
+ bool in_yuv = false;
+ u32 reg = 0;
+
+ switch (bus_format) {
+ case MEDIA_BUS_FMT_RGB565_1X16:
+ reg |= DCIF_DPI_CTRL_DATA_PATTERN(PATTERN_RGB565);
+ break;
+ case MEDIA_BUS_FMT_RGB888_1X24:
+ reg |= DCIF_DPI_CTRL_DATA_PATTERN(PATTERN_RGB888);
+ break;
+ case MEDIA_BUS_FMT_RBG888_1X24:
+ reg |= DCIF_DPI_CTRL_DATA_PATTERN(PATTERN_RBG888);
+ break;
+ case MEDIA_BUS_FMT_BGR888_1X24:
+ reg |= DCIF_DPI_CTRL_DATA_PATTERN(PATTERN_BGR888);
+ break;
+ case MEDIA_BUS_FMT_GBR888_1X24:
+ reg |= DCIF_DPI_CTRL_DATA_PATTERN(PATTERN_GBR888);
+ break;
+ default:
+ dev_err(drm->dev, "Unknown media bus format 0x%x\n", bus_format);
+ break;
+ }
+
+ regmap_update_bits(dcif->regmap, DCIF_DPI_CTRL, DCIF_DPI_CTRL_DATA_PATTERN_MASK, reg);
+
+ reg = 0;
+ switch (format) {
+ /* RGB Formats */
+ case DRM_FORMAT_RGB565:
+ reg |= DCIF_CTRLDESC0_FORMAT(CTRLDESCL0_FORMAT_RGB565);
+ break;
+ case DRM_FORMAT_RGB888:
+ reg |= DCIF_CTRLDESC0_FORMAT(CTRLDESCL0_FORMAT_RGB888);
+ break;
+ case DRM_FORMAT_XRGB1555:
+ case DRM_FORMAT_ARGB1555:
+ reg |= DCIF_CTRLDESC0_FORMAT(CTRLDESCL0_FORMAT_ARGB1555);
+ break;
+ case DRM_FORMAT_XRGB4444:
+ case DRM_FORMAT_ARGB4444:
+ reg |= DCIF_CTRLDESC0_FORMAT(CTRLDESCL0_FORMAT_ARGB4444);
+ break;
+ case DRM_FORMAT_XBGR8888:
+ case DRM_FORMAT_ABGR8888:
+ reg |= DCIF_CTRLDESC0_FORMAT(CTRLDESCL0_FORMAT_ABGR8888);
+ break;
+ case DRM_FORMAT_XRGB8888:
+ case DRM_FORMAT_ARGB8888:
+ reg |= DCIF_CTRLDESC0_FORMAT(CTRLDESCL0_FORMAT_ARGB8888);
+ break;
+
+ /* YUV Formats */
+ case DRM_FORMAT_YUYV:
+ reg |= DCIF_CTRLDESC0_FORMAT(CTRLDESCL0_FORMAT_YCBCR422) |
+ DCIF_CTRLDESC0_YUV_FORMAT(CTRLDESCL0_YUV_FORMAT_VY2UY1);
+ in_yuv = true;
+ break;
+ case DRM_FORMAT_YVYU:
+ reg |= DCIF_CTRLDESC0_FORMAT(CTRLDESCL0_FORMAT_YCBCR422) |
+ DCIF_CTRLDESC0_YUV_FORMAT(CTRLDESCL0_YUV_FORMAT_UY2VY1);
+ in_yuv = true;
+ break;
+ case DRM_FORMAT_UYVY:
+ reg |= DCIF_CTRLDESC0_FORMAT(CTRLDESCL0_FORMAT_YCBCR422) |
+ DCIF_CTRLDESC0_YUV_FORMAT(CTRLDESCL0_YUV_FORMAT_Y2VY1U);
+ in_yuv = true;
+ break;
+ case DRM_FORMAT_VYUY:
+ reg |= DCIF_CTRLDESC0_FORMAT(CTRLDESCL0_FORMAT_YCBCR422) |
+ DCIF_CTRLDESC0_YUV_FORMAT(CTRLDESCL0_YUV_FORMAT_Y2UY1V);
+ in_yuv = true;
+ break;
+
+ default:
+ dev_err(drm->dev, "Unknown pixel format 0x%x\n", format);
+ break;
+ }
+
+ regmap_update_bits(dcif->regmap, DCIF_CTRLDESC0(0),
+ DCIF_CTRLDESC0_FORMAT_MASK | DCIF_CTRLDESC0_YUV_FORMAT_MASK,
+ reg);
+
+ if (in_yuv) {
+ /* Enable CSC YCbCr -> RGB */
+ const u32 *coeffs =
+ dcif_yuv2rgb_coeffs[plane_state->color_encoding][plane_state->color_range];
+
+ regmap_bulk_write(dcif->regmap, DCIF_CSC_COEF0_L0, coeffs, 6);
+
+ regmap_write(dcif->regmap, DCIF_CSC_CTRL_L0,
+ DCIF_CSC_CTRL_L0_CSC_EN |
+ DCIF_CSC_CTRL_L0_CSC_MODE_YCBCR2RGB);
+ } else {
+ regmap_write(dcif->regmap, DCIF_CSC_CTRL_L0, 0);
+ }
+}
+
+static void dcif_set_mode(struct dcif_dev *dcif, u32 bus_flags)
+{
+ struct drm_display_mode *m = &dcif->crtc.state->adjusted_mode;
+ u32 reg = 0;
+
+ if (m->flags & DRM_MODE_FLAG_NHSYNC)
+ reg |= DCIF_DPI_CTRL_HSYNC_POL_LOW;
+ if (m->flags & DRM_MODE_FLAG_NVSYNC)
+ reg |= DCIF_DPI_CTRL_VSYNC_POL_LOW;
+ if (bus_flags & DRM_BUS_FLAG_DE_LOW)
+ reg |= DCIF_DPI_CTRL_DE_POL_LOW;
+ if (bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
+ reg |= DCIF_DPI_CTRL_PCLK_EDGE_FALLING;
+
+ regmap_update_bits(dcif->regmap, DCIF_DPI_CTRL, DCIF_DPI_CTRL_POL_MASK, reg);
+
+ /* config display timings */
+ reg = DCIF_DISP_SIZE_DISP_WIDTH(m->hdisplay) |
+ DCIF_DISP_SIZE_DISP_HEIGHT(m->vdisplay);
+ regmap_write(dcif->regmap, DCIF_DISP_SIZE, reg);
+
+ reg = DCIF_DPI_HSYN_PAR_BP_H(m->htotal - m->hsync_end) |
+ DCIF_DPI_HSYN_PAR_FP_H(m->hsync_start - m->hdisplay);
+ regmap_write(dcif->regmap, DCIF_DPI_HSYN_PAR, reg);
+
+ reg = DCIF_DPI_VSYN_PAR_BP_V(m->vtotal - m->vsync_end) |
+ DCIF_DPI_VSYN_PAR_FP_V(m->vsync_start - m->vdisplay);
+ regmap_write(dcif->regmap, DCIF_DPI_VSYN_PAR, reg);
+
+ reg = DCIF_DPI_VSYN_HSYN_WIDTH_PW_V(m->vsync_end - m->vsync_start) |
+ DCIF_DPI_VSYN_HSYN_WIDTH_PW_H(m->hsync_end - m->hsync_start);
+ regmap_write(dcif->regmap, DCIF_DPI_VSYN_HSYN_WIDTH, reg);
+
+ /* Layer 0 frame size */
+ reg = DCIF_CTRLDESC2_HEIGHT(m->vdisplay) |
+ DCIF_CTRLDESC2_WIDTH(m->hdisplay);
+ regmap_write(dcif->regmap, DCIF_CTRLDESC2(0), reg);
+
+ /*
+ * Configure P_SIZE, T_SIZE and pitch
+ * 1. P_SIZE and T_SIZE should never be less than AXI bus width.
+ * 2. P_SIZE should never be less than T_SIZE.
+ */
+ reg = DCIF_CTRLDESC3_P_SIZE(2) | DCIF_CTRLDESC3_T_SIZE(2) |
+ DCIF_CTRLDESC3_PITCH(dcif->crtc.primary->state->fb->pitches[0]);
+ regmap_write(dcif->regmap, DCIF_CTRLDESC3(0), reg);
+}
+
+static void dcif_enable_plane_panic(struct dcif_dev *dcif)
+{
+ u32 reg;
+
+ /* Set FIFO Panic watermarks, low 1/3, high 2/3. */
+ reg = DCIF_PANIC_THRES_LOW(1 * PANIC0_THRES_MAX / 3) |
+ DCIF_PANIC_THRES_HIGH(2 * PANIC0_THRES_MAX / 3) |
+ DCIF_PANIC_THRES_REQ_EN;
+ regmap_write(dcif->regmap, DCIF_PANIC_THRES(0), reg);
+ regmap_write(dcif->regmap, DCIF_PANIC_THRES(1), reg);
+
+ regmap_set_bits(dcif->regmap, DCIF_IE1(dcif->cpu_domain),
+ DCIF_INT1_FIFO_PANIC0 | DCIF_INT1_FIFO_PANIC1);
+}
+
+static void dcif_disable_plane_panic(struct dcif_dev *dcif)
+{
+ regmap_clear_bits(dcif->regmap, DCIF_IE1(dcif->cpu_domain),
+ DCIF_INT1_FIFO_PANIC0 | DCIF_INT1_FIFO_PANIC1);
+ regmap_clear_bits(dcif->regmap, DCIF_PANIC_THRES(0), DCIF_PANIC_THRES_REQ_EN);
+ regmap_clear_bits(dcif->regmap, DCIF_PANIC_THRES(1), DCIF_PANIC_THRES_REQ_EN);
+}
+
+static void dcif_enable_controller(struct dcif_dev *dcif)
+{
+ /* Enable Display */
+ regmap_set_bits(dcif->regmap, DCIF_DISP_CTRL, DCIF_DISP_CTRL_DISP_ON);
+
+ /* Enable layer 0 */
+ regmap_set_bits(dcif->regmap, DCIF_CTRLDESC0(0), DCIF_CTRLDESC0_EN);
+}
+
+static void dcif_disable_controller(struct dcif_dev *dcif)
+{
+ u32 reg;
+ int ret;
+
+ /* Disable layer 0 */
+ regmap_clear_bits(dcif->regmap, DCIF_CTRLDESC0(0), DCIF_CTRLDESC0_EN);
+
+ ret = regmap_read_poll_timeout(dcif->regmap, DCIF_CTRLDESC0(0), reg,
+ !(reg & DCIF_CTRLDESC0_EN), 0,
+ 36000); /* Wait ~2 frame times max */
+ if (ret)
+ drm_err(&dcif->drm, "Failed to disable controller!\n");
+
+ /* Disable Display */
+ regmap_clear_bits(dcif->regmap, DCIF_DISP_CTRL, DCIF_DISP_CTRL_DISP_ON);
+}
+
+static void dcif_shadow_load_enable(struct dcif_dev *dcif)
+{
+ regmap_write_bits(dcif->regmap, DCIF_CTRLDESC0(0), DCIF_CTRLDESC0_SHADOW_LOAD_EN,
+ DCIF_CTRLDESC0_SHADOW_LOAD_EN);
+}
+
+static void dcif_reset_block(struct dcif_dev *dcif)
+{
+ regmap_set_bits(dcif->regmap, DCIF_DISP_CTRL, DCIF_DISP_CTRL_SW_RST);
+
+ regmap_clear_bits(dcif->regmap, DCIF_DISP_CTRL, DCIF_DISP_CTRL_SW_RST);
+}
+
+static void dcif_crtc_atomic_destroy_state(struct drm_crtc *crtc,
+ struct drm_crtc_state *state)
+{
+ __drm_atomic_helper_crtc_destroy_state(state);
+ kfree(to_dcif_crtc_state(state));
+}
+
+static void dcif_crtc_reset(struct drm_crtc *crtc)
+{
+ struct dcif_crtc_state *state;
+
+ if (crtc->state)
+ dcif_crtc_atomic_destroy_state(crtc, crtc->state);
+
+ crtc->state = NULL;
+
+ state = kzalloc_obj(*state, GFP_KERNEL);
+ if (state)
+ __drm_atomic_helper_crtc_reset(crtc, &state->base);
+}
+
+static struct drm_crtc_state *dcif_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
+{
+ struct dcif_crtc_state *old = to_dcif_crtc_state(crtc->state);
+ struct dcif_crtc_state *new;
+
+ if (WARN_ON(!crtc->state))
+ return NULL;
+
+ new = kzalloc_obj(*new, GFP_KERNEL);
+ if (!new)
+ return NULL;
+
+ __drm_atomic_helper_crtc_duplicate_state(crtc, &new->base);
+
+ new->bus_format = old->bus_format;
+ new->bus_flags = old->bus_flags;
+ new->crc.source = old->crc.source;
+ dcif_copy_roi(&old->crc.roi, &new->crc.roi);
+
+ return &new->base;
+}
+
+static void dcif_crtc_mode_set_nofb(struct drm_crtc_state *crtc_state,
+ struct drm_plane_state *plane_state)
+{
+ struct dcif_crtc_state *dcif_crtc_state = to_dcif_crtc_state(crtc_state);
+ struct drm_device *drm = crtc_state->crtc->dev;
+ struct dcif_dev *dcif = crtc_to_dcif_dev(crtc_state->crtc);
+ struct drm_display_mode *m = &crtc_state->adjusted_mode;
+
+ dev_dbg(drm->dev, "Pixel clock: %dkHz\n", m->crtc_clock);
+ dev_dbg(drm->dev, "Bridge bus_flags: 0x%08X\n", dcif_crtc_state->bus_flags);
+ dev_dbg(drm->dev, "Mode flags: 0x%08X\n", m->flags);
+
+ dcif_reset_block(dcif);
+
+ dcif_set_formats(dcif, plane_state, dcif_crtc_state->bus_format);
+
+ dcif_set_mode(dcif, dcif_crtc_state->bus_flags);
+}
+
+static void dcif_crtc_queue_state_event(struct drm_crtc *crtc)
+{
+ struct dcif_dev *dcif = crtc_to_dcif_dev(crtc);
+
+ scoped_guard(spinlock_irq, &crtc->dev->event_lock) {
+ if (crtc->state->event) {
+ WARN_ON(drm_crtc_vblank_get(crtc));
+ WARN_ON(dcif->event);
+ dcif->event = crtc->state->event;
+ crtc->state->event = NULL;
+ }
+ }
+}
+
+static struct drm_bridge *dcif_crtc_get_bridge(struct drm_crtc *crtc,
+ struct drm_crtc_state *crtc_state)
+{
+ struct drm_connector_state *conn_state;
+ struct drm_encoder *encoder;
+ struct drm_connector *conn;
+ struct drm_bridge *bridge;
+ int i;
+
+ for_each_new_connector_in_state(crtc_state->state, conn, conn_state, i) {
+ if (crtc != conn_state->crtc)
+ continue;
+
+ encoder = conn_state->best_encoder;
+
+ bridge = drm_bridge_chain_get_first_bridge(encoder);
+ if (bridge)
+ return bridge;
+ }
+
+ return NULL;
+}
+
+static void dcif_crtc_query_output_bus_format(struct drm_crtc *crtc,
+ struct drm_crtc_state *crtc_state)
+{
+ struct dcif_crtc_state *dcif_state = to_dcif_crtc_state(crtc_state);
+ struct drm_bridge *bridge __free(drm_bridge_put) = NULL;
+ struct drm_bridge_state *bridge_state;
+
+ dcif_state->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
+ dcif_state->bus_flags = 0;
+
+ bridge = dcif_crtc_get_bridge(crtc, crtc_state);
+ if (!bridge)
+ return;
+
+ bridge_state = drm_atomic_get_new_bridge_state(crtc_state->state, bridge);
+ if (!bridge_state)
+ return;
+
+ dcif_state->bus_format = bridge_state->input_bus_cfg.format;
+ dcif_state->bus_flags = bridge_state->input_bus_cfg.flags;
+}
+
+static int dcif_crtc_atomic_check(struct drm_crtc *crtc, struct drm_atomic_commit *state)
+{
+ struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
+ bool enable_primary = crtc_state->plane_mask & drm_plane_mask(crtc->primary);
+ int ret;
+
+ if (crtc_state->active && !enable_primary)
+ return -EINVAL;
+
+ dcif_crtc_query_output_bus_format(crtc, crtc_state);
+
+ if (crtc_state->active_changed && crtc_state->active) {
+ if (!crtc_state->mode_changed) {
+ crtc_state->mode_changed = true;
+ ret = drm_atomic_helper_check_modeset(crtc->dev, state);
+ if (ret)
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static void dcif_crtc_atomic_flush(struct drm_crtc *crtc,
+ struct drm_atomic_commit *state)
+{
+ struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc);
+ struct dcif_crtc_state *old_dcif_crtc_state = to_dcif_crtc_state(old_crtc_state);
+ struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
+ struct dcif_crtc_state *dcif_crtc_state = to_dcif_crtc_state(crtc_state);
+ struct dcif_dev *dcif = crtc_to_dcif_dev(crtc);
+
+ dcif_shadow_load_enable(dcif);
+
+ if (drm_atomic_crtc_needs_modeset(crtc->state))
+ return;
+
+ if (dcif->has_crc && disable_dcif_crc_needed(dcif_crtc_state,
+ old_dcif_crtc_state))
+ dcif_crc_source_disable(dcif, 0);
+
+ dcif_crtc_queue_state_event(crtc);
+
+ if (dcif->has_crc && enable_dcif_crc_needed(dcif_crtc_state,
+ old_dcif_crtc_state))
+ dcif_crc_source_enable(dcif, dcif_crtc_state->crc.source,
+ &dcif_crtc_state->crc.roi, 0);
+}
+
+static void dcif_crtc_atomic_enable(struct drm_crtc *crtc,
+ struct drm_atomic_commit *state)
+{
+ struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
+ struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state, crtc->primary);
+ struct dcif_crtc_state *dcif_crtc_state = to_dcif_crtc_state(crtc_state);
+ struct drm_display_mode *adj = &crtc_state->adjusted_mode;
+ struct dcif_dev *dcif = crtc_to_dcif_dev(crtc);
+ struct drm_device *drm = crtc->dev;
+ dma_addr_t baseaddr;
+ int ret;
+
+ dev_dbg(drm->dev, "mode " DRM_MODE_FMT "\n", DRM_MODE_ARG(adj));
+
+ /* enable power when we start to set mode for CRTC */
+ ret = pm_runtime_resume_and_get(drm->dev);
+ if (ret < 0) {
+ drm_err(drm, "failed to resume DCIF, ret = %d\n", ret);
+ return;
+ }
+ dcif->crtc_pm_enabled = true;
+
+ drm_crtc_vblank_on(crtc);
+
+ dcif_crtc_mode_set_nofb(crtc_state, plane_state);
+
+ baseaddr = drm_fb_dma_get_gem_addr(plane_state->fb, plane_state, 0);
+ if (baseaddr)
+ regmap_write(dcif->regmap, DCIF_CTRLDESC4(0), baseaddr);
+
+ dcif_enable_plane_panic(dcif);
+ dcif_enable_controller(dcif);
+
+ dcif_crtc_queue_state_event(crtc);
+
+ if (dcif->has_crc && dcif_crtc_state->crc.source != DCIF_CRC_SRC_NONE)
+ dcif_crc_source_enable(dcif, dcif_crtc_state->crc.source,
+ &dcif_crtc_state->crc.roi, 0);
+}
+
+static void dcif_crtc_atomic_disable(struct drm_crtc *crtc,
+ struct drm_atomic_commit *state)
+{
+ struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
+ struct dcif_crtc_state *dcif_crtc_state = to_dcif_crtc_state(crtc_state);
+ struct dcif_dev *dcif = crtc_to_dcif_dev(crtc);
+ struct drm_device *drm = crtc->dev;
+
+ if (dcif->has_crc && dcif_crtc_state->crc.source != DCIF_CRC_SRC_NONE)
+ dcif_crc_source_disable(dcif, 0);
+
+ dcif_disable_controller(dcif);
+ dcif_disable_plane_panic(dcif);
+
+ drm_crtc_vblank_off(crtc);
+
+ if (dcif->crtc_pm_enabled) {
+ dcif->crtc_pm_enabled = false;
+ pm_runtime_put_sync(drm->dev);
+ }
+
+ scoped_guard(spinlock_irq, &crtc->dev->event_lock) {
+ if (crtc->state->event && !crtc->state->active) {
+ drm_crtc_send_vblank_event(crtc, crtc->state->event);
+ crtc->state->event = NULL;
+ }
+ }
+}
+
+static const struct drm_crtc_helper_funcs dcif_crtc_helper_funcs = {
+ .mode_valid = dcif_crtc_mode_valid,
+ .atomic_check = dcif_crtc_atomic_check,
+ .atomic_flush = dcif_crtc_atomic_flush,
+ .atomic_enable = dcif_crtc_atomic_enable,
+ .atomic_disable = dcif_crtc_atomic_disable,
+};
+
+static int dcif_crtc_enable_vblank(struct drm_crtc *crtc)
+{
+ struct dcif_dev *dcif = crtc_to_dcif_dev(crtc);
+ int domain = dcif->cpu_domain;
+
+ /* Clear and enable VS_BLANK IRQ */
+ regmap_set_bits(dcif->regmap, DCIF_IS0(domain), DCIF_INT0_VS_BLANK);
+ regmap_set_bits(dcif->regmap, DCIF_IE0(domain), DCIF_INT0_VS_BLANK);
+
+ return 0;
+}
+
+static void dcif_crtc_disable_vblank(struct drm_crtc *crtc)
+{
+ struct dcif_dev *dcif = crtc_to_dcif_dev(crtc);
+ int domain = dcif->cpu_domain;
+
+ /* Disable and clear VS_BLANK IRQ */
+ regmap_clear_bits(dcif->regmap, DCIF_IE0(domain), DCIF_INT0_VS_BLANK);
+ regmap_clear_bits(dcif->regmap, DCIF_IS0(domain), DCIF_INT0_VS_BLANK);
+}
+
+static const struct drm_crtc_funcs dcif_crtc_funcs = {
+ .reset = dcif_crtc_reset,
+ .destroy = drm_crtc_cleanup,
+ .set_config = drm_atomic_helper_set_config,
+ .page_flip = drm_atomic_helper_page_flip,
+ .atomic_duplicate_state = dcif_crtc_atomic_duplicate_state,
+ .atomic_destroy_state = dcif_crtc_atomic_destroy_state,
+ .enable_vblank = dcif_crtc_enable_vblank,
+ .disable_vblank = dcif_crtc_disable_vblank,
+ .set_crc_source = dcif_crc_source_set,
+ .verify_crc_source = dcif_crc_source_verify,
+};
+
+irqreturn_t dcif_irq_handler(int irq, void *data)
+{
+ struct drm_device *drm = data;
+ struct dcif_dev *dcif = to_dcif_dev(drm);
+ int domain = dcif->cpu_domain;
+ u32 stat0, stat1, crc;
+
+ regmap_read(dcif->regmap, DCIF_IS0(domain), &stat0);
+ regmap_read(dcif->regmap, DCIF_IS1(domain), &stat1);
+ regmap_write(dcif->regmap, DCIF_IS0(domain), stat0);
+ regmap_write(dcif->regmap, DCIF_IS1(domain), stat1);
+
+ if (stat0 & DCIF_INT0_VS_BLANK) {
+ drm_crtc_handle_vblank(&dcif->crtc);
+
+ scoped_guard(spinlock_irqsave, &drm->event_lock) {
+ if (dcif->event) {
+ drm_crtc_send_vblank_event(&dcif->crtc, dcif->event);
+ dcif->event = NULL;
+ drm_crtc_vblank_put(&dcif->crtc);
+ }
+ if (dcif->crc_is_enabled) {
+ regmap_read(dcif->regmap, DCIF_CRC_VAL_R(0), &crc);
+ drm_crtc_add_crc_entry(&dcif->crtc, false, 0, &crc);
+ dev_dbg(drm->dev, "crc=0x%x\n", crc);
+ }
+ }
+ }
+
+ if (stat1 & (DCIF_INT1_FIFO_PANIC0 | DCIF_INT1_FIFO_PANIC1)) {
+ u32 panic = stat1 & (DCIF_INT1_FIFO_PANIC0 | DCIF_INT1_FIFO_PANIC1);
+
+ dev_dbg_ratelimited(drm->dev, "FIFO panic on %s\n",
+ panic == (DCIF_INT1_FIFO_PANIC0 | DCIF_INT1_FIFO_PANIC1) ?
+ "layers 0 & 1" : panic == DCIF_INT1_FIFO_PANIC0 ? "layer 0" :
+ "layer 1");
+ }
+
+ return IRQ_HANDLED;
+}
+
+int dcif_crtc_init(struct dcif_dev *dcif)
+{
+ int ret;
+
+ ret = dcif_plane_init(dcif);
+ if (ret)
+ return ret;
+
+ drm_crtc_helper_add(&dcif->crtc, &dcif_crtc_helper_funcs);
+ ret = drm_crtc_init_with_planes(&dcif->drm, &dcif->crtc, &dcif->planes.primary, NULL,
+ &dcif_crtc_funcs, NULL);
+ if (ret) {
+ drm_err(&dcif->drm, "failed to initialize CRTC: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/imx/dcif/dcif-drv.c b/drivers/gpu/drm/imx/dcif/dcif-drv.c
new file mode 100644
index 0000000000000..50ca6461ffb30
--- /dev/null
+++ b/drivers/gpu/drm/imx/dcif/dcif-drv.c
@@ -0,0 +1,233 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+ * Copyright 2025 NXP
+ */
+
+#include <linux/dma-mapping.h>
+#include <linux/interrupt.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mod_devicetable.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+
+#include <drm/clients/drm_client_setup.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_drv.h>
+#include <drm/drm_fbdev_dma.h>
+#include <drm/drm_gem_dma_helper.h>
+#include <drm/drm_modeset_helper.h>
+#include <drm/drm_print.h>
+
+#include "dcif-drv.h"
+#include "dcif-reg.h"
+
+#define DCIF_CPU_DOMAIN 0
+
+DEFINE_DRM_GEM_DMA_FOPS(dcif_driver_fops);
+
+static struct drm_driver dcif_driver = {
+ .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC,
+ DRM_GEM_DMA_DRIVER_OPS,
+ DRM_FBDEV_DMA_DRIVER_OPS,
+ .fops = &dcif_driver_fops,
+ .name = "imx-dcif",
+ .desc = "i.MX DCIF DRM graphics",
+ .major = 1,
+ .minor = 0,
+ .patchlevel = 0,
+};
+
+static void dcif_read_chip_info(struct dcif_dev *dcif)
+{
+ struct drm_device *drm = &dcif->drm;
+ u32 val, vmin, vmaj;
+ int ret;
+
+ ret = pm_runtime_resume_and_get(drm->dev);
+ if (ret < 0) {
+ drm_err(drm, "failed to resume DCIF: %d\n", ret);
+ return;
+ }
+
+ regmap_read(dcif->regmap, DCIF_VER, &val);
+
+ dcif->has_crc = val & DCIF_FEATURE_CRC;
+
+ vmin = DCIF_VER_GET_MINOR(val);
+ vmaj = DCIF_VER_GET_MAJOR(val);
+ DRM_DEV_DEBUG(drm->dev, "DCIF version is %d.%d\n", vmaj, vmin);
+
+ pm_runtime_put_sync(drm->dev);
+}
+
+static const struct regmap_config dcif_regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .fast_io = true,
+ .max_register = 0x20250,
+ .cache_type = REGCACHE_NONE,
+ .disable_locking = true,
+};
+
+static int dcif_probe(struct platform_device *pdev)
+{
+ struct dcif_dev *dcif;
+ struct drm_device *drm;
+ int ret;
+ int i;
+
+ dcif = devm_drm_dev_alloc(&pdev->dev, &dcif_driver, struct dcif_dev, drm);
+ if (IS_ERR(dcif))
+ return PTR_ERR(dcif);
+
+ /* CPU 0 domain for interrupt control */
+ dcif->cpu_domain = DCIF_CPU_DOMAIN;
+
+ drm = &dcif->drm;
+ dev_set_drvdata(&pdev->dev, dcif);
+
+ dcif->reg_base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(dcif->reg_base))
+ return dev_err_probe(drm->dev, PTR_ERR(dcif->reg_base),
+ "failed to get reg base\n");
+
+ for (i = 0; i < 3; i++) {
+ dcif->irq[i] = platform_get_irq(pdev, i);
+ if (dcif->irq[i] < 0)
+ return dev_err_probe(drm->dev, dcif->irq[i],
+ "failed to get domain%d irq\n", i);
+ }
+
+ dcif->regmap = devm_regmap_init_mmio(drm->dev, dcif->reg_base, &dcif_regmap_config);
+ if (IS_ERR(dcif->regmap))
+ return dev_err_probe(drm->dev, PTR_ERR(dcif->regmap),
+ "failed to init DCIF regmap\n");
+
+ dcif->num_clks = devm_clk_bulk_get_all(drm->dev, &dcif->clks);
+ if (dcif->num_clks < 0)
+ return dev_err_probe(drm->dev, dcif->num_clks,
+ "cannot get required clocks\n");
+
+ dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32));
+
+ devm_pm_runtime_enable(drm->dev);
+
+ ret = devm_request_irq(drm->dev, dcif->irq[dcif->cpu_domain],
+ dcif_irq_handler, 0, drm->driver->name, drm);
+ if (ret < 0)
+ return dev_err_probe(drm->dev, ret, "failed to install IRQ handler\n");
+
+ dcif_read_chip_info(dcif);
+
+ ret = dcif_kms_prepare(dcif);
+ if (ret)
+ return ret;
+
+ ret = drm_dev_register(drm, 0);
+ if (ret)
+ return dev_err_probe(drm->dev, ret, "failed to register drm device\n");
+
+ drm_client_setup(drm, NULL);
+
+ return 0;
+}
+
+static void dcif_remove(struct platform_device *pdev)
+{
+ struct dcif_dev *dcif = dev_get_drvdata(&pdev->dev);
+ struct drm_device *drm = &dcif->drm;
+
+ drm_dev_unregister(drm);
+
+ drm_atomic_helper_shutdown(drm);
+}
+
+static void dcif_shutdown(struct platform_device *pdev)
+{
+ struct dcif_dev *dcif = dev_get_drvdata(&pdev->dev);
+ struct drm_device *drm = &dcif->drm;
+
+ drm_atomic_helper_shutdown(drm);
+}
+
+static int dcif_runtime_suspend(struct device *dev)
+{
+ struct dcif_dev *dcif = dev_get_drvdata(dev);
+
+ clk_bulk_disable_unprepare(dcif->num_clks, dcif->clks);
+
+ return 0;
+}
+
+static int dcif_runtime_resume(struct device *dev)
+{
+ struct dcif_dev *dcif = dev_get_drvdata(dev);
+ int ret;
+
+ ret = clk_bulk_prepare_enable(dcif->num_clks, dcif->clks);
+ if (ret) {
+ dev_err(dev, "failed to enable clocks: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int dcif_suspend(struct device *dev)
+{
+ struct dcif_dev *dcif = dev_get_drvdata(dev);
+ int ret;
+
+ ret = drm_mode_config_helper_suspend(&dcif->drm);
+ if (ret < 0)
+ return ret;
+
+ if (pm_runtime_suspended(dev))
+ return 0;
+
+ return dcif_runtime_suspend(dev);
+}
+
+static int dcif_resume(struct device *dev)
+{
+ struct dcif_dev *dcif = dev_get_drvdata(dev);
+ int ret;
+
+ if (!pm_runtime_suspended(dev)) {
+ ret = dcif_runtime_resume(dev);
+ if (ret < 0)
+ return ret;
+ }
+
+ return drm_mode_config_helper_resume(&dcif->drm);
+}
+
+static const struct dev_pm_ops dcif_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(dcif_suspend, dcif_resume)
+ SET_RUNTIME_PM_OPS(dcif_runtime_suspend, dcif_runtime_resume, NULL)
+};
+
+static const struct of_device_id dcif_dt_ids[] = {
+ { .compatible = "nxp,imx94-dcif", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, dcif_dt_ids);
+
+static struct platform_driver dcif_platform_driver = {
+ .probe = dcif_probe,
+ .remove = dcif_remove,
+ .shutdown = dcif_shutdown,
+ .driver = {
+ .name = "imx-dcif-drm",
+ .of_match_table = dcif_dt_ids,
+ .pm = pm_ptr(&dcif_pm_ops),
+ },
+};
+module_platform_driver(dcif_platform_driver);
+
+MODULE_AUTHOR("NXP Semiconductor");
+MODULE_DESCRIPTION("i.MX94 DCIF DRM driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/gpu/drm/imx/dcif/dcif-drv.h b/drivers/gpu/drm/imx/dcif/dcif-drv.h
new file mode 100644
index 0000000000000..895b2efc51a26
--- /dev/null
+++ b/drivers/gpu/drm/imx/dcif/dcif-drv.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+/*
+ * Copyright 2025 NXP
+ */
+
+#ifndef __DCIF_DRV_H__
+#define __DCIF_DRV_H__
+
+#include <linux/clk.h>
+#include <linux/irqreturn.h>
+
+#include <drm/drm_crtc.h>
+#include <drm/drm_device.h>
+#include <drm/drm_encoder.h>
+#include <drm/drm_plane.h>
+#include <drm/drm_vblank.h>
+
+#define DCIF_CPU_DOMAINS 3
+
+struct dcif_dev {
+ struct drm_device drm;
+ void __iomem *reg_base;
+
+ struct regmap *regmap;
+ int irq[DCIF_CPU_DOMAINS];
+
+ int num_clks;
+ struct clk_bulk_data *clks;
+
+ struct drm_crtc crtc;
+ struct {
+ struct drm_plane primary;
+ struct drm_plane overlay;
+ } planes;
+ struct drm_encoder encoder;
+
+ struct drm_pending_vblank_event *event;
+
+ /* Implement crc */
+ bool has_crc;
+ bool crc_is_enabled;
+
+ /* Tracks whether atomic_enable obtained a PM runtime reference */
+ bool crtc_pm_enabled;
+
+ /* CPU domain for interrupt control */
+ int cpu_domain;
+};
+
+enum dcif_crc_source {
+ DCIF_CRC_SRC_NONE,
+ DCIF_CRC_SRC_FRAME,
+ DCIF_CRC_SRC_FRAME_ROI,
+};
+
+struct dcif_crc {
+ enum dcif_crc_source source;
+ struct drm_rect roi;
+};
+
+struct dcif_crtc_state {
+ struct drm_crtc_state base;
+ struct dcif_crc crc;
+ u32 bus_format;
+ u32 bus_flags;
+};
+
+static inline struct dcif_dev *to_dcif_dev(struct drm_device *drm_dev)
+{
+ return container_of(drm_dev, struct dcif_dev, drm);
+}
+
+static inline struct dcif_dev *crtc_to_dcif_dev(struct drm_crtc *crtc)
+{
+ return to_dcif_dev(crtc->dev);
+}
+
+static inline struct dcif_crtc_state *to_dcif_crtc_state(struct drm_crtc_state *s)
+{
+ return container_of(s, struct dcif_crtc_state, base);
+}
+
+irqreturn_t dcif_irq_handler(int irq, void *data);
+int dcif_crtc_init(struct dcif_dev *dcif);
+int dcif_plane_init(struct dcif_dev *dcif);
+int dcif_kms_prepare(struct dcif_dev *dcif);
+
+#endif
diff --git a/drivers/gpu/drm/imx/dcif/dcif-kms.c b/drivers/gpu/drm/imx/dcif/dcif-kms.c
new file mode 100644
index 0000000000000..8981434b0a803
--- /dev/null
+++ b/drivers/gpu/drm/imx/dcif/dcif-kms.c
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+ * Copyright 2025 NXP
+ */
+
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_bridge.h>
+#include <drm/drm_bridge_connector.h>
+#include <drm/drm_gem_framebuffer_helper.h>
+#include <drm/drm_print.h>
+#include <drm/drm_probe_helper.h>
+#include <drm/drm_simple_kms_helper.h>
+
+#include "dcif-drv.h"
+
+static int dcif_kms_init(struct dcif_dev *dcif)
+{
+ struct drm_device *drm = &dcif->drm;
+ struct device_node *np = drm->dev->of_node;
+ struct drm_connector *connector;
+ struct drm_bridge *bridge;
+ int ret;
+
+ ret = dcif_crtc_init(dcif);
+ if (ret)
+ return ret;
+
+ bridge = devm_drm_of_get_bridge(drm->dev, np, 0, 0);
+ if (IS_ERR(bridge))
+ return dev_err_probe(drm->dev, PTR_ERR(bridge), "Failed to find bridge\n");
+
+ dcif->encoder.possible_crtcs = drm_crtc_mask(&dcif->crtc);
+ ret = drm_simple_encoder_init(drm, &dcif->encoder, DRM_MODE_ENCODER_NONE);
+ if (ret) {
+ drm_err(drm, "failed to initialize encoder: %d\n", ret);
+ return ret;
+ }
+
+ ret = drm_bridge_attach(&dcif->encoder, bridge, NULL, DRM_BRIDGE_ATTACH_NO_CONNECTOR);
+ if (ret) {
+ drm_err(drm, "failed to attach bridge to encoder: %d\n", ret);
+ return ret;
+ }
+
+ connector = drm_bridge_connector_init(drm, &dcif->encoder);
+ if (IS_ERR(connector)) {
+ drm_err(drm, "failed to initialize bridge connector: %ld\n", PTR_ERR(connector));
+ return PTR_ERR(connector);
+ }
+
+ return 0;
+}
+
+static const struct drm_mode_config_funcs dcif_mode_config_funcs = {
+ .fb_create = drm_gem_fb_create,
+ .atomic_check = drm_atomic_helper_check,
+ .atomic_commit = drm_atomic_helper_commit,
+};
+
+static const struct drm_mode_config_helper_funcs dcif_mode_config_helpers = {
+ .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
+};
+
+int dcif_kms_prepare(struct dcif_dev *dcif)
+{
+ struct drm_device *drm = &dcif->drm;
+ int ret;
+
+ ret = drmm_mode_config_init(drm);
+ if (ret)
+ return ret;
+
+ ret = dcif_kms_init(dcif);
+ if (ret)
+ return ret;
+
+ drm->mode_config.min_width = 1;
+ drm->mode_config.min_height = 1;
+ drm->mode_config.max_width = 1920;
+ drm->mode_config.max_height = 1920;
+ drm->mode_config.funcs = &dcif_mode_config_funcs;
+ drm->mode_config.helper_private = &dcif_mode_config_helpers;
+
+ ret = drm_vblank_init(drm, 1);
+ if (ret < 0) {
+ drm_err(drm, "failed to initialize vblank: %d\n", ret);
+ return ret;
+ }
+
+ drm_mode_config_reset(drm);
+
+ drmm_kms_helper_poll_init(drm);
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/imx/dcif/dcif-plane.c b/drivers/gpu/drm/imx/dcif/dcif-plane.c
new file mode 100644
index 0000000000000..7b5a68dab6587
--- /dev/null
+++ b/drivers/gpu/drm/imx/dcif/dcif-plane.c
@@ -0,0 +1,308 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+ * Copyright 2025 NXP
+ */
+
+#include <linux/regmap.h>
+
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_blend.h>
+#include <drm/drm_fb_dma_helper.h>
+#include <drm/drm_fourcc.h>
+#include <drm/drm_framebuffer.h>
+#include <drm/drm_gem_atomic_helper.h>
+#include <drm/drm_gem_dma_helper.h>
+#include <drm/drm_print.h>
+#include <drm/drm_rect.h>
+
+#include "dcif-drv.h"
+#include "dcif-reg.h"
+
+static const u32 dcif_primary_plane_formats[] = {
+ /* RGB */
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_RGB888,
+ DRM_FORMAT_XBGR8888,
+ DRM_FORMAT_ABGR8888,
+ DRM_FORMAT_XRGB1555,
+ DRM_FORMAT_ARGB1555,
+ DRM_FORMAT_XRGB4444,
+ DRM_FORMAT_ARGB4444,
+ DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_ARGB8888,
+
+ /* Packed YCbCr */
+ DRM_FORMAT_YUYV,
+ DRM_FORMAT_YVYU,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_VYUY,
+};
+
+static const u32 dcif_overlay_plane_formats[] = {
+ /* RGB */
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_RGB888,
+ DRM_FORMAT_XBGR8888,
+ DRM_FORMAT_ABGR8888,
+ DRM_FORMAT_XRGB1555,
+ DRM_FORMAT_ARGB1555,
+ DRM_FORMAT_XRGB4444,
+ DRM_FORMAT_ARGB4444,
+ DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_ARGB8888,
+};
+
+static inline struct dcif_dev *plane_to_dcif_dev(struct drm_plane *plane)
+{
+ return to_dcif_dev(plane->dev);
+}
+
+static inline dma_addr_t drm_plane_state_to_baseaddr(struct drm_plane_state *state)
+{
+ struct drm_framebuffer *fb = state->fb;
+ struct drm_gem_dma_object *dma_obj;
+ unsigned int x = state->src.x1 >> 16;
+ unsigned int y = state->src.y1 >> 16;
+
+ dma_obj = drm_fb_dma_get_gem_obj(fb, 0);
+ if (!dma_obj)
+ return 0;
+
+ return dma_obj->dma_addr + fb->offsets[0] + fb->pitches[0] * y + fb->format->cpp[0] * x;
+}
+
+static int dcif_plane_get_layer_id(struct drm_plane *plane)
+{
+ return (plane->type == DRM_PLANE_TYPE_PRIMARY) ? 0 : 1;
+}
+
+static int dcif_plane_atomic_check(struct drm_plane *plane, struct drm_atomic_commit *state)
+{
+ struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane);
+ struct drm_plane_state *old_plane_state = drm_atomic_get_old_plane_state(state, plane);
+ struct dcif_dev *dcif = plane_to_dcif_dev(plane);
+ struct drm_framebuffer *fb = new_plane_state->fb;
+ struct drm_framebuffer *old_fb = old_plane_state->fb;
+ struct drm_crtc_state *crtc_state;
+ int ret;
+
+ if (!fb)
+ return 0;
+
+ crtc_state = drm_atomic_get_new_crtc_state(state, &dcif->crtc);
+ if (WARN_ON(!crtc_state))
+ return -EINVAL;
+
+ /*
+ * Force CRTC mode change if framebuffer stride or pixel format have changed.
+ */
+ if (plane->type == DRM_PLANE_TYPE_PRIMARY && old_fb &&
+ (fb->pitches[0] != old_fb->pitches[0] || fb->format->format != old_fb->format->format))
+ crtc_state->mode_changed = true;
+
+ ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
+ DRM_PLANE_NO_SCALING,
+ DRM_PLANE_NO_SCALING,
+ true,
+ true);
+ if (ret)
+ return ret;
+
+ if (new_plane_state->fb->format->has_alpha &&
+ new_plane_state->pixel_blend_mode != DRM_MODE_BLEND_PIXEL_NONE &&
+ new_plane_state->alpha != DRM_BLEND_ALPHA_OPAQUE)
+ return -EINVAL;
+
+ return 0;
+}
+
+static void dcif_plane_atomic_update(struct drm_plane *plane, struct drm_atomic_commit *state)
+{
+ struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane);
+ struct dcif_dev *dcif = plane_to_dcif_dev(plane);
+ int layer_id = dcif_plane_get_layer_id(plane);
+ struct drm_framebuffer *fb = new_state->fb;
+ u32 crtc_x, crtc_y, crtc_h, crtc_w;
+ u32 layer_fmt = 0, yuv_fmt = 0;
+ dma_addr_t baseaddr;
+ u32 reg;
+
+ if (!fb)
+ return;
+
+ crtc_x = new_state->dst.x1;
+ crtc_y = new_state->dst.y1;
+ crtc_w = drm_rect_width(&new_state->dst);
+ crtc_h = drm_rect_height(&new_state->dst);
+
+ /* visible portion of plane on crtc */
+ regmap_write(dcif->regmap, DCIF_CTRLDESC1(layer_id),
+ DCIF_CTRLDESC1_POSX(crtc_x) | DCIF_CTRLDESC1_POSY(crtc_y));
+ regmap_write(dcif->regmap, DCIF_CTRLDESC2(layer_id),
+ DCIF_CTRLDESC2_WIDTH(crtc_w) | DCIF_CTRLDESC2_HEIGHT(crtc_h));
+
+ /* pitch size */
+ reg = DCIF_CTRLDESC3_P_SIZE(2) | DCIF_CTRLDESC3_T_SIZE(2) |
+ DCIF_CTRLDESC3_PITCH(fb->pitches[0]);
+ regmap_write(dcif->regmap, DCIF_CTRLDESC3(layer_id), reg);
+
+ /* address */
+ baseaddr = drm_plane_state_to_baseaddr(new_state);
+
+ drm_dbg_kms(plane->dev, "[PLANE:%d:%s] fb address %pad, pitch 0x%08x\n",
+ plane->base.id, plane->name, &baseaddr, fb->pitches[0]);
+
+ regmap_write(dcif->regmap, DCIF_CTRLDESC4(layer_id), baseaddr);
+
+ /* Format */
+ switch (fb->format->format) {
+ /* RGB Formats */
+ case DRM_FORMAT_RGB565:
+ layer_fmt = CTRLDESCL0_FORMAT_RGB565;
+ break;
+ case DRM_FORMAT_RGB888:
+ layer_fmt = CTRLDESCL0_FORMAT_RGB888;
+ break;
+ case DRM_FORMAT_XRGB1555:
+ case DRM_FORMAT_ARGB1555:
+ layer_fmt = CTRLDESCL0_FORMAT_ARGB1555;
+ break;
+ case DRM_FORMAT_XRGB4444:
+ case DRM_FORMAT_ARGB4444:
+ layer_fmt = CTRLDESCL0_FORMAT_ARGB4444;
+ break;
+ case DRM_FORMAT_XBGR8888:
+ case DRM_FORMAT_ABGR8888:
+ layer_fmt = CTRLDESCL0_FORMAT_ABGR8888;
+ break;
+ case DRM_FORMAT_XRGB8888:
+ case DRM_FORMAT_ARGB8888:
+ layer_fmt = CTRLDESCL0_FORMAT_ARGB8888;
+ break;
+
+ /* YUV Formats */
+ case DRM_FORMAT_YUYV:
+ layer_fmt = CTRLDESCL0_FORMAT_YCBCR422;
+ yuv_fmt = CTRLDESCL0_YUV_FORMAT_VY2UY1;
+ break;
+ case DRM_FORMAT_YVYU:
+ layer_fmt = CTRLDESCL0_FORMAT_YCBCR422;
+ yuv_fmt = CTRLDESCL0_YUV_FORMAT_UY2VY1;
+ break;
+ case DRM_FORMAT_UYVY:
+ layer_fmt = CTRLDESCL0_FORMAT_YCBCR422;
+ yuv_fmt = CTRLDESCL0_YUV_FORMAT_Y2VY1U;
+ break;
+ case DRM_FORMAT_VYUY:
+ layer_fmt = CTRLDESCL0_FORMAT_YCBCR422;
+ yuv_fmt = CTRLDESCL0_YUV_FORMAT_Y2UY1V;
+ break;
+
+ default:
+ dev_err(dcif->drm.dev, "Unknown pixel format 0x%x\n", fb->format->format);
+ break;
+ }
+
+ reg = DCIF_CTRLDESC0_EN | DCIF_CTRLDESC0_SHADOW_LOAD_EN |
+ DCIF_CTRLDESC0_FORMAT(layer_fmt) | DCIF_CTRLDESC0_YUV_FORMAT(yuv_fmt);
+
+ /* Alpha */
+ if (new_state->pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE ||
+ !new_state->fb->format->has_alpha)
+ reg |= DCIF_CTRLDESC0_GLOBAL_ALPHA(new_state->alpha >> 8) | ALPHA_GLOBAL;
+ else if (new_state->pixel_blend_mode == DRM_MODE_BLEND_COVERAGE)
+ reg |= ALPHA_EMBEDDED;
+ else
+ /*
+ * DCIF does not support premultiplied per-pixel blending but,
+ * since PREMULTI's property presence is mandatory to not break
+ * userspace, we just disable alpha blending for this one.
+ */
+ reg |= DCIF_CTRLDESC0_GLOBAL_ALPHA(255) | ALPHA_GLOBAL;
+
+ regmap_write(dcif->regmap, DCIF_CTRLDESC0(layer_id), reg);
+}
+
+static void dcif_overlay_plane_atomic_disable(struct drm_plane *plane,
+ struct drm_atomic_commit *state)
+{
+ struct dcif_dev *dcif = plane_to_dcif_dev(plane);
+
+ regmap_update_bits(dcif->regmap, DCIF_CTRLDESC0(1),
+ DCIF_CTRLDESC0_EN | DCIF_CTRLDESC0_SHADOW_LOAD_EN,
+ DCIF_CTRLDESC0_SHADOW_LOAD_EN);
+}
+
+static const struct drm_plane_helper_funcs dcif_primary_plane_helper_funcs = {
+ .prepare_fb = drm_gem_plane_helper_prepare_fb,
+ .atomic_check = dcif_plane_atomic_check,
+ .atomic_update = dcif_plane_atomic_update,
+};
+
+static const struct drm_plane_helper_funcs dcif_overlay_plane_helper_funcs = {
+ .atomic_check = dcif_plane_atomic_check,
+ .atomic_update = dcif_plane_atomic_update,
+ .atomic_disable = dcif_overlay_plane_atomic_disable,
+};
+
+static const struct drm_plane_funcs dcif_plane_funcs = {
+ .update_plane = drm_atomic_helper_update_plane,
+ .disable_plane = drm_atomic_helper_disable_plane,
+ .destroy = drm_plane_cleanup,
+ .reset = drm_atomic_helper_plane_reset,
+ .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
+};
+
+int dcif_plane_init(struct dcif_dev *dcif)
+{
+ const u32 supported_encodings = BIT(DRM_COLOR_YCBCR_BT601) |
+ BIT(DRM_COLOR_YCBCR_BT709) |
+ BIT(DRM_COLOR_YCBCR_BT2020);
+ const u32 supported_ranges = BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
+ BIT(DRM_COLOR_YCBCR_FULL_RANGE);
+ int ret;
+
+ /* primary plane */
+ drm_plane_helper_add(&dcif->planes.primary, &dcif_primary_plane_helper_funcs);
+ ret = drm_universal_plane_init(&dcif->drm, &dcif->planes.primary, 1, &dcif_plane_funcs,
+ dcif_primary_plane_formats,
+ ARRAY_SIZE(dcif_primary_plane_formats), NULL,
+ DRM_PLANE_TYPE_PRIMARY, NULL);
+ if (ret) {
+ drm_err(&dcif->drm, "failed to initialize primary plane: %d\n", ret);
+ return ret;
+ }
+
+ ret = drm_plane_create_color_properties(&dcif->planes.primary, supported_encodings,
+ supported_ranges, DRM_COLOR_YCBCR_BT601,
+ DRM_COLOR_YCBCR_LIMITED_RANGE);
+ if (ret)
+ return ret;
+
+ ret = drm_plane_create_alpha_property(&dcif->planes.primary);
+ if (ret)
+ return ret;
+
+ /* overlay plane */
+ drm_plane_helper_add(&dcif->planes.overlay, &dcif_overlay_plane_helper_funcs);
+ ret = drm_universal_plane_init(&dcif->drm, &dcif->planes.overlay, 1, &dcif_plane_funcs,
+ dcif_overlay_plane_formats,
+ ARRAY_SIZE(dcif_overlay_plane_formats), NULL,
+ DRM_PLANE_TYPE_OVERLAY, NULL);
+ if (ret) {
+ drm_err(&dcif->drm, "failed to initialize overlay plane: %d\n", ret);
+ return ret;
+ }
+
+ ret = drm_plane_create_alpha_property(&dcif->planes.overlay);
+ if (ret)
+ return ret;
+
+ return drm_plane_create_blend_mode_property(&dcif->planes.overlay,
+ BIT(DRM_MODE_BLEND_PIXEL_NONE) |
+ BIT(DRM_MODE_BLEND_PREMULTI) |
+ BIT(DRM_MODE_BLEND_COVERAGE));
+}
diff --git a/drivers/gpu/drm/imx/dcif/dcif-reg.h b/drivers/gpu/drm/imx/dcif/dcif-reg.h
new file mode 100644
index 0000000000000..acf9e3071aa52
--- /dev/null
+++ b/drivers/gpu/drm/imx/dcif/dcif-reg.h
@@ -0,0 +1,267 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+/*
+ * Copyright 2025 NXP
+ */
+#ifndef __DCIF_REG_H__
+#define __DCIF_REG_H__
+
+#include <linux/bits.h>
+
+/* Version ID Register */
+#define DCIF_VER 0x0
+#define DCIF_VER_GET_FEATURE(x) FIELD_GET(GENMASK(15, 0), x)
+#define DCIF_VER_GET_MINOR(x) FIELD_GET(GENMASK(23, 16), x)
+#define DCIF_VER_GET_MAJOR(x) FIELD_GET(GENMASK(31, 24), x)
+#define DCIF_FEATURE_CRC BIT(1)
+
+/* Parameter Registers */
+#define DCIF_PAR_0 0x4
+#define DCIF_PAR_0_LAYER_NUM(x) FIELD_PREP(GENMASK(3, 0), x)
+#define DCIF_PAR_0_DOMAIN_NUM(x) FIELD_PREP(GENMASK(5, 4), x)
+#define DCIF_PAR_0_AXI_DATA_WIDTH(x) FIELD_PREP(GENMASK(7, 6), x)
+#define DCIF_PAR_0_CLUT_RAM_NUM(x) FIELD_PREP(GENMASK(11, 8), x)
+#define DCIF_PAR_0_CSC_NUM(x) FIELD_PREP(GENMASK(13, 12), x)
+#define DCIF_PAR_0_CRC_REGION_NUM(x) FIELD_PREP(GENMASK(18, 16), x)
+#define DCIF_PAR_0_BACKUP(x) FIELD_PREP(GENMASK(31, 28), x)
+
+#define DCIF_PAR_1 0x8
+#define DCIF_PAR_1_LAYER0_FIFO_SIZE(x) FIELD_PREP(GENMASK(3, 0), x)
+#define DCIF_PAR_1_LAYER1_FIFO_SIZE(x) FIELD_PREP(GENMASK(7, 4), x)
+
+/* Display Control and Parameter Registers */
+#define DCIF_DISP_CTRL 0x10
+#define DCIF_DISP_CTRL_DISP_ON BIT(0)
+#define DCIF_DISP_CTRL_AXI_RD_HOLD BIT(30)
+#define DCIF_DISP_CTRL_SW_RST BIT(31)
+#define DCIF_DISP_PAR 0x14
+#define DCIF_DISP_PAR_BGND_B(x) FIELD_PREP(GENMASK(7, 0), x)
+#define DCIF_DISP_PAR_BGND_G(x) FIELD_PREP(GENMASK(15, 8), x)
+#define DCIF_DISP_PAR_BGND_R(x) FIELD_PREP(GENMASK(23, 16), x)
+#define DCIF_DISP_SIZE 0x18
+#define DCIF_DISP_SIZE_DISP_WIDTH(x) FIELD_PREP(GENMASK(11, 0), x)
+#define DCIF_DISP_SIZE_DISP_HEIGHT(x) FIELD_PREP(GENMASK(27, 16), x)
+
+/* Display Status Registers */
+#define DCIF_DISP_SR0 0x1C
+#define DCIF_DISP_SR0_AXI_RD_PEND(x) FIELD_PREP(GENMASK(4, 0), x)
+#define DCIF_DISP_SR0_DPI_BUSY(x) FIELD_PREP(GENMASK(14, 14), x)
+#define DCIF_DISP_SR0_AXI_RD_BUSY(x) FIELD_PREP(GENMASK(15, 15), x)
+#define DCIF_DISP_SR0_TXFIFO_CNT(x) FIELD_PREP(GENMASK(23, 16), x)
+
+#define DCIF_DISP_SR1 0x20
+#define DCIF_DISP_SR1_H_CNT(x) FIELD_PREP(GENMASK(11, 0), x)
+#define DCIF_DISP_SR1_V_CNT(x) FIELD_PREP(GENMASK(27, 16), x)
+
+/* Interrupt Enable and Status Registers, n=0-2*/
+#define DCIF_IE0(n) (0x24 + (n) * 0x10000)
+#define DCIF_IS0(n) (0x28 + (n) * 0x10000)
+#define DCIF_INT0_VSYNC BIT(0)
+#define DCIF_INT0_UNDERRUN BIT(1)
+#define DCIF_INT0_VS_BLANK BIT(2)
+#define DCIF_INT0_HIST_DONE BIT(5)
+#define DCIF_INT0_CRC_ERR BIT(6)
+#define DCIF_INT0_CRC_ERR_SAT BIT(7)
+
+#define DCIF_IE1(n) (0x2C + (n) * 0x10000)
+#define DCIF_IS1(n) (0x30 + (n) * 0x10000)
+#define DCIF_INT1_FIFO_PANIC0 BIT(0)
+#define DCIF_INT1_FIFO_PANIC1 BIT(1)
+#define DCIF_INT1_DMA_ERR0 BIT(8)
+#define DCIF_INT1_DMA_ERR1 BIT(9)
+#define DCIF_INT1_DMA_DONE0 BIT(16)
+#define DCIF_INT1_DMA_DONE1 BIT(17)
+#define DCIF_INT1_FIFO_EMPTY0 BIT(24)
+#define DCIF_INT1_FIFO_EMPTY1 BIT(25)
+
+/* DPI Control and Sync Parameter Registers */
+#define DCIF_DPI_CTRL 0x40
+#define DCIF_DPI_CTRL_HSYNC_POL_LOW BIT(0)
+#define DCIF_DPI_CTRL_VSYNC_POL_LOW BIT(1)
+#define DCIF_DPI_CTRL_DE_POL_LOW BIT(2)
+#define DCIF_DPI_CTRL_PCLK_EDGE_FALLING BIT(3)
+#define DCIF_DPI_CTRL_POL_MASK GENMASK(3, 0)
+#define DCIF_DPI_CTRL_DATA_INV(x) FIELD_PREP(GENMASK(4, 4), x)
+#define DCIF_DPI_CTRL_DEF_BGND_EN(x) FIELD_PREP(GENMASK(5, 5), x)
+#define DCIF_DPI_CTRL_FETCH_OPT(x) FIELD_PREP(GENMASK(9, 8), x)
+#define DCIF_DPI_CTRL_DISP_MODE(x) FIELD_PREP(GENMASK(13, 12), x)
+#define DCIF_DPI_CTRL_DATA_PATTERN_MASK GENMASK(18, 16)
+#define DCIF_DPI_CTRL_DATA_PATTERN(x) FIELD_PREP(GENMASK(18, 16), x)
+#define PATTERN_RGB888 0
+#define PATTERN_RBG888 1
+#define PATTERN_GBR888 2
+#define PATTERN_GRB888 3
+#define PATTERN_BRG888 4
+#define PATTERN_BGR888 5
+#define PATTERN_RGB555 6
+#define PATTERN_RGB565 7
+
+#define DCIF_DPI_HSYN_PAR 0x44
+#define DCIF_DPI_HSYN_PAR_FP_H(x) FIELD_PREP(GENMASK(11, 0), x)
+#define DCIF_DPI_HSYN_PAR_BP_H(x) FIELD_PREP(GENMASK(27, 16), x)
+
+#define DCIF_DPI_VSYN_PAR 0x48
+#define DCIF_DPI_VSYN_PAR_FP_V(x) FIELD_PREP(GENMASK(11, 0), x)
+#define DCIF_DPI_VSYN_PAR_BP_V(x) FIELD_PREP(GENMASK(27, 16), x)
+
+#define DCIF_DPI_VSYN_HSYN_WIDTH 0x4C
+#define DCIF_DPI_VSYN_HSYN_WIDTH_PW_H(x) FIELD_PREP(GENMASK(11, 0), x)
+#define DCIF_DPI_VSYN_HSYN_WIDTH_PW_V(x) FIELD_PREP(GENMASK(27, 16), x)
+
+/* Control Descriptor Registers, n=0-1*/
+#define DCIF_CTRLDESC0(n) (0x10000 + (n) * 0x10000)
+#define DCIF_CTRLDESC0_AB_MODE(x) FIELD_PREP(GENMASK(1, 0), x)
+#define ALPHA_EMBEDDED 0
+#define ALPHA_GLOBAL 1
+#define DCIF_CTRLDESC0_YUV_FORMAT_MASK GENMASK(15, 14)
+#define DCIF_CTRLDESC0_YUV_FORMAT(x) FIELD_PREP(GENMASK(15, 14), x)
+#define CTRLDESCL0_YUV_FORMAT_Y2VY1U 0x0
+#define CTRLDESCL0_YUV_FORMAT_Y2UY1V 0x1
+#define CTRLDESCL0_YUV_FORMAT_VY2UY1 0x2
+#define CTRLDESCL0_YUV_FORMAT_UY2VY1 0x3
+#define DCIF_CTRLDESC0_GLOBAL_ALPHA(x) FIELD_PREP(GENMASK(23, 16), x)
+#define DCIF_CTRLDESC0_FORMAT_MASK GENMASK(27, 24)
+#define DCIF_CTRLDESC0_FORMAT(x) FIELD_PREP(GENMASK(27, 24), x)
+#define CTRLDESCL0_FORMAT_RGB565 0x4
+#define CTRLDESCL0_FORMAT_ARGB1555 0x5
+#define CTRLDESCL0_FORMAT_ARGB4444 0x6
+#define CTRLDESCL0_FORMAT_YCBCR422 0x7
+#define CTRLDESCL0_FORMAT_RGB888 0x8
+#define CTRLDESCL0_FORMAT_ARGB8888 0x9
+#define CTRLDESCL0_FORMAT_ABGR8888 0xa
+#define DCIF_CTRLDESC0_SHADOW_LOAD_EN BIT(30)
+#define DCIF_CTRLDESC0_EN BIT(31)
+
+#define DCIF_CTRLDESC1(n) (0x10004 + (n) * 0x10000)
+#define DCIF_CTRLDESC1_POSX(x) FIELD_PREP(GENMASK(11, 0), x)
+#define DCIF_CTRLDESC1_POSY(x) FIELD_PREP(GENMASK(27, 16), x)
+
+#define DCIF_CTRLDESC2(n) (0x10008 + (n) * 0x10000)
+#define DCIF_CTRLDESC2_WIDTH(x) FIELD_PREP(GENMASK(11, 0), x)
+#define DCIF_CTRLDESC2_HEIGHT(x) FIELD_PREP(GENMASK(27, 16), x)
+
+#define DCIF_CTRLDESC3(n) (0x1000C + (n) * 0x10000)
+#define DCIF_CTRLDESC3_PITCH(x) FIELD_PREP(GENMASK(15, 0), x)
+#define DCIF_CTRLDESC3_T_SIZE(x) FIELD_PREP(GENMASK(17, 16), x)
+#define DCIF_CTRLDESC3_P_SIZE(x) FIELD_PREP(GENMASK(22, 20), x)
+
+#define DCIF_CTRLDESC4(n) (0x10010 + (n) * 0x10000)
+#define DCIF_CTRLDESC4_ADDR(x) FIELD_PREP(GENMASK(31, 0), x)
+
+#define DCIF_CTRLDESC5(n) (0x10014 + (n) * 0x10000)
+#define DCIF_CTRLDESC6(n) (0x10018 + (n) * 0x10000)
+#define DCIF_CTRLDESC6_BCLR_B(x) FIELD_PREP(GENMASK(7, 0), x)
+#define DCIF_CTRLDESC6_BCLR_G(x) FIELD_PREP(GENMASK(15, 8), x)
+#define DCIF_CTRLDESC6_BCLR_R(x) FIELD_PREP(GENMASK(23, 16), x)
+#define DCIF_CTRLDESC6_BCLR_A(x) FIELD_PREP(GENMASK(31, 24), x)
+
+/* CLUT control Register */
+#define DCIF_CLUT_CTRL 0x1003C
+#define DCIF_CLUT_CTRL_CLUT0_SEL(x) FIELD_PREP(GENMASK(0, 0), x)
+#define DCIF_CLUT_CTRL_CLUT1_SEL(x) FIELD_PREP(GENMASK(3, 3), x)
+#define DCIF_CLUT_CTRL_CLUT_MUX(x) FIELD_PREP(GENMASK(29, 28), x)
+#define DCIF_CLUT_CTRL_CLUT_SHADOW_LOAD_EN(x) FIELD_PREP(GENMASK(31, 31), x)
+
+/* FIFO Panic Threshold Register, n=0-1 */
+#define DCIF_PANIC_THRES(n) (0x10040 + (n) * 0x10000)
+#define DCIF_PANIC_THRES_LOW_MASK GENMASK(11, 0)
+#define DCIF_PANIC_THRES_LOW(x) FIELD_PREP(GENMASK(11, 00), x)
+#define DCIF_PANIC_THRES_HIGH_MASK GENMASK(27, 16)
+#define DCIF_PANIC_THRES_HIGH(x) FIELD_PREP(GENMASK(27, 16), x)
+#define DCIF_PANIC_THRES_REQ_EN BIT(31)
+#define PANIC0_THRES_MAX 511
+
+/* Layer Status Register 0, n=0-1 */
+#define DCIF_LAYER_SR0(n) (0x10044 + (n) * 0x10000)
+#define DCIF_LAYER_SR0_L0_FIFO_CNT_MASK GENMASK(9, 0)
+#define DCIF_LAYER_SR0_L0_FIFO_CNT(x) FIELD_PREP(GENMASK(9, 0), x)
+
+/* Color Space Conversion Control and Coefficient Registers for Layer 0 */
+#define DCIF_CSC_CTRL_L0 0x10050
+#define DCIF_CSC_CTRL_L0_CSC_EN BIT(0)
+#define DCIF_CSC_CTRL_L0_CSC_MODE_YCBCR2RGB BIT(1)
+
+#define DCIF_CSC_COEF0_L0 0x10054
+#define DCIF_CSC_COEF0_L0_A1(x) FIELD_PREP_CONST(GENMASK(10, 0), x)
+#define DCIF_CSC_COEF0_L0_A2(x) FIELD_PREP_CONST(GENMASK(26, 16), x)
+
+#define DCIF_CSC_COEF1_L0 0x10058
+#define DCIF_CSC_COEF1_L0_A3(x) FIELD_PREP_CONST(GENMASK(10, 0), x)
+#define DCIF_CSC_COEF1_L0_B1(x) FIELD_PREP_CONST(GENMASK(26, 16), x)
+
+#define DCIF_CSC_COEF2_L0 0x1005C
+#define DCIF_CSC_COEF2_L0_B2(x) FIELD_PREP_CONST(GENMASK(10, 0), x)
+#define DCIF_CSC_COEF2_L0_B3(x) FIELD_PREP_CONST(GENMASK(26, 16), x)
+
+#define DCIF_CSC_COEF3_L0 0x10060
+#define DCIF_CSC_COEF3_L0_C1(x) FIELD_PREP_CONST(GENMASK(10, 0), x)
+#define DCIF_CSC_COEF3_L0_C2(x) FIELD_PREP_CONST(GENMASK(26, 16), x)
+
+#define DCIF_CSC_COEF4_L0 0x10064
+#define DCIF_CSC_COEF4_L0_C3(x) FIELD_PREP_CONST(GENMASK(10, 0), x)
+#define DCIF_CSC_COEF4_L0_D1(x) FIELD_PREP_CONST(GENMASK(24, 16), x)
+
+#define DCIF_CSC_COEF5_L0 0x10068
+#define DCIF_CSC_COEF5_L0_D2(x) FIELD_PREP_CONST(GENMASK(8, 0), x)
+#define DCIF_CSC_COEF5_L0_D3(x) FIELD_PREP_CONST(GENMASK(24, 16), x)
+
+/* CRC Control, Threshold, and Histogram Coefficient Registers */
+#define DCIF_CRC_CTRL 0x20100
+#define DCIF_CRC_CTRL_CRC_EN(x) (1 << (x))
+#define DCIF_CRC_CTRL_HIST_REGION_SEL(x) FIELD_PREP(GENMASK(17, 16), x)
+#define DCIF_CRC_CTRL_HIST_MODE BIT(21)
+#define DCIF_CRC_CTRL_HIST_TRIG BIT(22)
+#define DCIF_CRC_CTRL_HIST_EN BIT(23)
+#define DCIF_CRC_CTRL_CRC_MODE BIT(28)
+#define DCIF_CRC_CTRL_CRC_TRIG BIT(29)
+#define DCIF_CRC_CTRL_CRC_ERR_CNT_RST BIT(30)
+#define DCIF_CRC_CTRL_CRC_SHADOW_LOAD_EN BIT(31)
+
+#define DCIF_CRC_THRES 0x20104
+#define DCIF_CRC_THRES_CRC_THRESHOLD_MASK GENMASK(31, 0)
+#define DCIF_CRC_THRES_CRC_THRESHOLD(x) FIELD_PREP(GENMASK(31, 0), x)
+
+#define DCIF_CRC_HIST_COEF 0x20108
+#define DCIF_CRC_HIST_COEF_HIST_WB_MASK GENMASK(7, 0)
+#define DCIF_CRC_HIST_COEF_HIST_WB(x) FIELD_PREP(GENMASK(7, 0), x)
+#define DCIF_CRC_HIST_COEF_HIST_WG_MASK GENMASK(15, 8)
+#define DCIF_CRC_HIST_COEF_HIST_WG(x) FIELD_PREP(GENMASK(15, 8), x)
+#define DCIF_CRC_HIST_COEF_HIST_WR_MASK GENMASK(23, 16)
+#define DCIF_CRC_HIST_COEF_HIST_WR(x) FIELD_PREP(GENMASK(23, 16), x)
+
+#define DCIF_CRC_ERR_CNT 0x2010C
+#define DCIF_CRC_ERR_CNT_CRC_ERR_CNT_MASK GENMASK(31, 0)
+#define DCIF_CRC_ERR_CNT_CRC_ERR_CNT(x) FIELD_PREP(GENMASK(31, 0), x)
+
+#define DCIF_CRC_SR 0x20110
+#define DCIF_CRC_SR_HIST_CNT_SAT_MASK BIT(13)
+#define DCIF_CRC_SR_HIST_CNT_SAT(x) FIELD_PREP(GENMASK(13, 13), x)
+#define DCIF_CRC_SR_HIST_SAT_MASK BIT(14)
+#define DCIF_CRC_SR_HIST_SAT(x) FIELD_PREP(GENMASK(14, 14), x)
+#define DCIF_CRC_SR_HIST_BUSY_MASK BIT(15)
+#define DCIF_CRC_SR_HIST_BUSY(x) FIELD_PREP(GENMASK(15, 15), x)
+#define DCIF_CRC_SR_CRC_STATUS_MASK BIT(31)
+#define DCIF_CRC_SR_CRC_STATUS(x) FIELD_PREP(GENMASK(31, 31), x)
+
+#define DCIF_CRC_HIST_CNT_B(n) (0x20114 + (n) * 4)
+#define DCIF_B_BIN_CNT_MASK GENMASK(20, 0)
+#define DCIF_B_BIN_CNT(x) FIELD_PREP(GENMASK(20, 0), x)
+
+/* CRC Region Position, Size, Value, and Expected Value Registers, n=0-3 */
+#define DCIF_CRC_POS_R(n) (0x20214 + (n) * 0x10)
+#define DCIF_CRC_POS_CRC_HOR_POS(x) FIELD_PREP(GENMASK(11, 0), x)
+#define DCIF_CRC_POS_CRC_VER_POS(x) FIELD_PREP(GENMASK(27, 16), x)
+
+#define DCIF_CRC_SIZE_R(n) (0x20218 + (n) * 0x10)
+#define DCIF_CRC_SIZE_CRC_HOR_SIZE(x) FIELD_PREP(GENMASK(11, 0), x)
+#define DCIF_CRC_SIZE_CRC_VER_SIZE(x) FIELD_PREP(GENMASK(27, 16), x)
+
+#define DCIF_CRC_VAL_R(n) (0x2021C + (n) * 0x10)
+#define DCIF_CRC_VAL_CRC_VAL_MASK GENMASK(31, 0)
+#define DCIF_CRC_VAL_CRC_VAL(x) FIELD_PREP(GENMASK(31, 0), x)
+
+#define DCIF_CRC_EXP_VAL_R(n) (0x20220 + (n) * 0x10)
+#define DCIF_CRC_EXP_VAL_CRC_EXP_VAL_MASK GENMASK(31, 0)
+#define DCIF_CRC_EXP_VAL_CRC_EXP_VAL(x) FIELD_PREP(GENMASK(31, 0), x)
+
+#endif /* __DCIF_REG_H__ */
--
2.51.0
^ permalink raw reply related
* [PATCH v9 6/9] dt-bindings: clock: nxp,imx95-blk-ctl: Add ldb child node
From: Laurentiu Palcu @ 2026-06-12 11:58 UTC (permalink / raw)
To: Ying Liu, Luca Ceresoli, Abel Vesa, Peng Fan, Michael Turquette,
Stephen Boyd, Brian Masney, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Frank Li, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam
Cc: Laurentiu Palcu, linux-clk, imx, devicetree, linux-arm-kernel,
linux-kernel, dri-devel
In-Reply-To: <20260612-dcif-upstreaming-v9-0-8d0ff89aa3c5@oss.nxp.com>
Since the BLK CTL registers, like the LVDS CSR, can be used to control the
LVDS Display Bridge controllers, add 'ldb' child node to handle
these use cases.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
---
.../bindings/clock/nxp,imx95-blk-ctl.yaml | 26 ++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml b/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml
index 27403b4c52d62..2b3c762aba1e0 100644
--- a/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml
+++ b/Documentation/devicetree/bindings/clock/nxp,imx95-blk-ctl.yaml
@@ -26,6 +26,12 @@ properties:
reg:
maxItems: 1
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 1
+
power-domains:
maxItems: 1
@@ -39,6 +45,11 @@ properties:
ID in its "clocks" phandle cell. See
include/dt-bindings/clock/nxp,imx95-clock.h
+patternProperties:
+ '^ldb@[0-9a-f]+$':
+ type: object
+ $ref: /schemas/display/bridge/fsl,ldb.yaml#
+
required:
- compatible
- reg
@@ -46,6 +57,21 @@ required:
- power-domains
- clocks
+allOf:
+ - if:
+ not:
+ properties:
+ compatible:
+ contains:
+ const: nxp,imx94-lvds-csr
+ then:
+ patternProperties:
+ "^ldb@[0-9a-f]+$": false
+ else:
+ required:
+ - '#address-cells'
+ - '#size-cells'
+
additionalProperties: false
examples:
--
2.51.0
^ permalink raw reply related
* [PATCH v9 7/9] arm64: dts: imx94: Add display pipeline nodes
From: Laurentiu Palcu @ 2026-06-12 11:58 UTC (permalink / raw)
To: Ying Liu, Luca Ceresoli, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Frank Li, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam
Cc: Laurentiu Palcu, linux-clk, imx, devicetree, linux-arm-kernel,
linux-kernel, dri-devel
In-Reply-To: <20260612-dcif-upstreaming-v9-0-8d0ff89aa3c5@oss.nxp.com>
Add the nodes necessary for the display pipeline on i.MX94:
* LVDS/DISPLAY CSR;
* clock-ldb-pll-div7 needed by DCIF and LDB;
* Display controller interface (DCIF);
* LVDS display bridge (LDB);
Co-developed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
---
arch/arm64/boot/dts/freescale/imx94.dtsi | 82 ++++++++++++++++++++++++++++++++
1 file changed, 82 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx94.dtsi b/arch/arm64/boot/dts/freescale/imx94.dtsi
index a6cb5a6e848b3..95d862682703c 100644
--- a/arch/arm64/boot/dts/freescale/imx94.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx94.dtsi
@@ -3,6 +3,7 @@
* Copyright 2024-2025 NXP
*/
+#include <dt-bindings/clock/nxp,imx94-clock.h>
#include <dt-bindings/dma/fsl-edma.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
@@ -39,6 +40,15 @@ clk_ext1: clock-ext1 {
clock-output-names = "clk_ext1";
};
+ clk_ldb_pll_div7: clock-ldb-pll-div7 {
+ compatible = "fixed-factor-clock";
+ #clock-cells = <0>;
+ clocks = <&scmi_clk IMX94_CLK_LDBPLL>;
+ clock-div = <7>;
+ clock-mult = <1>;
+ clock-output-names = "ldb_pll_div7";
+ };
+
sai1_mclk: clock-sai1-mclk1 {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -1305,6 +1315,78 @@ wdog4: watchdog@49230000 {
};
};
+ dispmix_csr: syscon@4b010000 {
+ compatible = "nxp,imx94-display-csr", "syscon";
+ reg = <0x0 0x4b010000 0x0 0x10000>;
+ clocks = <&scmi_clk IMX94_CLK_DISPAPB>;
+ #clock-cells = <1>;
+ power-domains = <&scmi_devpd IMX94_PD_DISPLAY>;
+ assigned-clocks = <&scmi_clk IMX94_CLK_DISPAXI>,
+ <&scmi_clk IMX94_CLK_DISPAPB>;
+ assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1>,
+ <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>;
+ assigned-clock-rates = <400000000>, <133333333>;
+ };
+
+ lvds_csr: syscon@4b0c0000 {
+ compatible = "nxp,imx94-lvds-csr", "syscon";
+ reg = <0x0 0x4b0c0000 0x0 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&scmi_clk IMX94_CLK_DISPAPB>;
+ #clock-cells = <1>;
+ power-domains = <&scmi_devpd IMX94_PD_DISPLAY>;
+
+ ldb: ldb@4 {
+ compatible = "fsl,imx94-ldb";
+ reg = <0x4 0x4>, <0x8 0x4>;
+ reg-names = "ldb", "lvds";
+ clocks = <&lvds_csr IMX94_CLK_DISPMIX_LVDS_CLK_GATE>;
+ clock-names = "ldb";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ lvds_in: endpoint {
+ remote-endpoint = <&dcif_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+ };
+ };
+ };
+
+ dcif: display-controller@4b120000 {
+ compatible = "nxp,imx94-dcif";
+ reg = <0x0 0x4b120000 0x0 0x300000>;
+ interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "common", "bg_layer", "fg_layer";
+ clocks = <&scmi_clk IMX94_CLK_DISPAPB>,
+ <&scmi_clk IMX94_CLK_DISPAXI>,
+ <&dispmix_csr IMX94_CLK_DISPMIX_CLK_SEL>;
+ clock-names = "apb", "axi", "pix";
+ assigned-clocks = <&dispmix_csr IMX94_CLK_DISPMIX_CLK_SEL>;
+ assigned-clock-parents = <&clk_ldb_pll_div7>;
+ power-domains = <&scmi_devpd IMX94_PD_DISPLAY>;
+ status = "disabled";
+
+ port {
+ dcif_out: endpoint {
+ remote-endpoint = <&lvds_in>;
+ };
+ };
+ };
+
hsio_blk_ctl: syscon@4c0100c0 {
compatible = "nxp,imx95-hsio-blk-ctl", "syscon";
reg = <0x0 0x4c0100c0 0x0 0x1>;
--
2.51.0
^ permalink raw reply related
* [PATCH v9 9/9] MAINTAINERS: Add entry for i.MX94 DCIF driver
From: Laurentiu Palcu @ 2026-06-12 11:58 UTC (permalink / raw)
To: Ying Liu, Luca Ceresoli
Cc: Laurentiu Palcu, linux-clk, imx, devicetree, linux-arm-kernel,
linux-kernel, dri-devel
In-Reply-To: <20260612-dcif-upstreaming-v9-0-8d0ff89aa3c5@oss.nxp.com>
The driver is part of DRM subsystem and is located in
drivers/gpu/drm/imx/dcif.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
---
MAINTAINERS | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index f1caa6e5198b9..e8931231b5b7e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19492,6 +19492,15 @@ S: Maintained
F: Documentation/devicetree/bindings/media/nxp,imx8-jpeg.yaml
F: drivers/media/platform/nxp/imx-jpeg
+NXP i.MX 94 DCIF DRIVER
+M: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
+L: dri-devel@lists.freedesktop.org
+L: imx@lists.linux.dev
+S: Maintained
+T: git https://gitlab.freedesktop.org/drm/misc/kernel.git
+F: Documentation/devicetree/bindings/display/imx/nxp,imx94-dcif.yaml
+F: drivers/gpu/drm/imx/dcif/
+
NXP i.MX CLOCK DRIVERS
M: Abel Vesa <abelvesa@kernel.org>
R: Peng Fan <peng.fan@nxp.com>
--
2.51.0
^ permalink raw reply related
* [PATCH v9 8/9] arm64: dts: imx943-evk: Add display support using IT6263
From: Laurentiu Palcu @ 2026-06-12 11:58 UTC (permalink / raw)
To: Ying Liu, Luca Ceresoli, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Frank Li, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam
Cc: Laurentiu Palcu, linux-clk, imx, devicetree, linux-arm-kernel,
linux-kernel, dri-devel
In-Reply-To: <20260612-dcif-upstreaming-v9-0-8d0ff89aa3c5@oss.nxp.com>
The ITE IT6263 based NXP LVDS to HDMI converter can be attached to the
i.MX943 EVK board LVDS port using the mini-SAS connector. Since this is
the default configuration for the EVK, add support for it here.
Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
---
arch/arm64/boot/dts/freescale/imx943-evk.dts | 86 ++++++++++++++++++++++++++++
1 file changed, 86 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx943-evk.dts b/arch/arm64/boot/dts/freescale/imx943-evk.dts
index 7cfd424689507..41a2a700a86a5 100644
--- a/arch/arm64/boot/dts/freescale/imx943-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx943-evk.dts
@@ -77,6 +77,36 @@ dmic: dmic {
#sound-dai-cells = <0>;
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ label = "hdmi";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&it6263_out>;
+ };
+ };
+ };
+
+ reg_1v8_ext: regulator-1v8-ext {
+ compatible = "regulator-fixed";
+ regulator-name = "1V8_EXT";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3v3_ext: regulator-3v3-ext {
+ compatible = "regulator-fixed";
+ regulator-name = "3V3_EXT";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
reg_m2_pwr: regulator-m2-pwr {
compatible = "regulator-fixed";
regulator-name = "M.2-power";
@@ -210,6 +240,10 @@ memory@80000000 {
};
};
+&dcif {
+ status = "okay";
+};
+
&enetc1 {
clocks = <&scmi_clk IMX94_CLK_MAC4>;
clock-names = "ref";
@@ -248,6 +282,21 @@ &flexcan4 {
status = "okay";
};
+&ldb {
+ assigned-clocks = <&scmi_clk IMX94_CLK_LDBPLL_VCO>,
+ <&scmi_clk IMX94_CLK_LDBPLL>;
+ assigned-clock-rates = <4158000000>, <1039500000>;
+ status = "okay";
+
+ ports {
+ port@1 {
+ lvds_out: endpoint {
+ remote-endpoint = <&it6263_in>;
+ };
+ };
+ };
+};
+
&lpi2c3 {
clock-frequency = <400000>;
pinctrl-0 = <&pinctrl_lpi2c3>;
@@ -331,6 +380,43 @@ i2c@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
+
+ hdmi@4c {
+ compatible = "ite,it6263";
+ reg = <0x4c>;
+ data-mapping = "jeida-24";
+ reset-gpios = <&pcal6416_i2c3_u171 8 GPIO_ACTIVE_LOW>;
+ ivdd-supply = <®_1v8_ext>;
+ ovdd-supply = <®_3v3_ext>;
+ txavcc18-supply = <®_1v8_ext>;
+ txavcc33-supply = <®_3v3_ext>;
+ pvcc1-supply = <®_1v8_ext>;
+ pvcc2-supply = <®_1v8_ext>;
+ avcc-supply = <®_3v3_ext>;
+ anvdd-supply = <®_1v8_ext>;
+ apvdd-supply = <®_1v8_ext>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ it6263_in: endpoint {
+ remote-endpoint = <&lvds_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ it6263_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+ };
};
i2c@4 {
--
2.51.0
^ permalink raw reply related
* Re: [PATCH v8 7/9] arm64: dts: imx943: Add display pipeline nodes
From: Laurentiu Palcu @ 2026-06-12 12:02 UTC (permalink / raw)
To: Liu Ying
Cc: imx, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, dri-devel,
devicetree, linux-arm-kernel, linux-kernel
In-Reply-To: <43be372e-8177-457c-9d4e-a2ed69e79c8a@nxp.com>
Hi Ying,
On Fri, Mar 06, 2026 at 04:27:48PM +0800, Liu Ying wrote:
> On Wed, Mar 04, 2026 at 11:34:16AM +0000, Laurentiu Palcu wrote:
> > Add display controller and LDB support in imx943.
> >
> > Signed-off-by: Laurentiu Palcu <laurentiu.palcu@oss.nxp.com>
> > ---
> > arch/arm64/boot/dts/freescale/imx943.dtsi | 53 ++++++++++++++++++++++++++++++-
> > 1 file changed, 52 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx943.dtsi b/arch/arm64/boot/dts/freescale/imx943.dtsi
> > index 657c81b6016f2..9a91beef54e86 100644
> > --- a/arch/arm64/boot/dts/freescale/imx943.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx943.dtsi
> > @@ -148,7 +148,7 @@ l3_cache: l3-cache {
> > };
> > };
> >
> > - clock-ldb-pll-div7 {
> > + clock_ldb_pll_div7: clock-ldb-pll-div7 {
> > compatible = "fixed-factor-clock";
> > #clock-cells = <0>;
> > clocks = <&scmi_clk IMX94_CLK_LDBPLL>;
> > @@ -174,9 +174,60 @@ dispmix_csr: syscon@4b010000 {
> > lvds_csr: syscon@4b0c0000 {
> > compatible = "nxp,imx94-lvds-csr", "syscon";
> > reg = <0x0 0x4b0c0000 0x0 0x10000>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > clocks = <&scmi_clk IMX94_CLK_DISPAPB>;
> > #clock-cells = <1>;
> > power-domains = <&scmi_devpd IMX94_PD_DISPLAY>;
> > +
> > + ldb: ldb@4 {
> > + compatible = "fsl,imx94-ldb";
>
> Should this be moved to imx94.dtsi, since the compatible string doesn't
> seem to be i.MX943 specific?
Agreed, I moved them to imx94.dtsi in v9.
--
Thanks,
Laurentiu
^ permalink raw reply
* Re: [PATCH v7 25/30] drm/vc4: hdmi: Convert to common HDMI 2.0 SCDC scrambling helpers
From: Maxime Ripard @ 2026-06-12 12:04 UTC (permalink / raw)
To: Cristian Ciocaltea
Cc: Maarten Lankhorst, Thomas Zimmermann, David Airlie, Simona Vetter,
Andrzej Hajda, Neil Armstrong, Robert Foss, Laurent Pinchart,
Jonas Karlman, Jernej Skrabec, Luca Ceresoli, Sandy Huang,
Heiko Stübner, Andy Yan, Daniel Stone, Dave Stevenson,
Maíra Canal, Raspberry Pi Kernel Maintenance, kernel,
dri-devel, linux-kernel, linux-arm-kernel, linux-rockchip
In-Reply-To: <20260602-dw-hdmi-qp-scramb-v7-25-445eb54ee1ed@collabora.com>
[-- Attachment #1: Type: text/plain, Size: 15614 bytes --]
Hi,
On Tue, Jun 02, 2026 at 01:44:25AM +0300, Cristian Ciocaltea wrote:
> Replace the vc4-local scrambling implementation with the newly
> introduced DRM common SCDC scrambling infrastructure:
>
> - Advertise source-side scrambling support by setting
> connector->hdmi.scrambling_supported based on the variant's
> max_pixel_clock before drmm_connector_hdmi_init().
>
> - Provide minimal .scrambler_{enable|disable} connector callbacks that
> only toggle the VC5 HDMI_SCRAMBLER_CTL register. Sink-side SCDC
> programming and periodic status monitoring are now delegated to
> drm_scdc_{start|stop}_scrambling().
>
> - Replace vc4_hdmi_enable_scrambling() with a conditional call to
> drm_scdc_start_scrambling() in post_crtc_enable, gated on
> conn_state->hdmi.scrambler_needed (computed by the HDMI state helper).
>
> - Replace vc4_hdmi_disable_scrambling() with drm_scdc_stop_scrambling()
> in post_crtc_disable.
>
> - Drop vc4_hdmi_reset_link() and vc4_hdmi_handle_hotplug(), switching
> the .detect_ctx() path to
> drm_atomic_helper_connector_hdmi_hotplug_ctx() which internally calls
> drm_scdc_sync_status() to trigger a CRTC reset on reconnection.
>
> - Drop the local scrambling_work delayed workqueue and scdc_enabled
> flag, now tracked by the common drm_connector_hdmi layer.
>
> - Drop vc4_hdmi_supports_scrambling() and
> vc4_hdmi_mode_needs_scrambling() helpers, inlining the remaining 4KP60
> warning with an explicit drm_hdmi_compute_mode_clock() check.
>
> - Seed connector->hdmi.scrambler_enabled = true in connector_init() to
> ensure drm_scdc_stop_scrambling() runs at boot and disables any stale
> scrambling state left by the bootloader.
>
> No functional change is expected for the supported modes.
>
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
I'd really like it to be broken down into several patches:
> ---
> drivers/gpu/drm/vc4/vc4_hdmi.c | 265 ++++++-----------------------------------
> drivers/gpu/drm/vc4/vc4_hdmi.h | 8 --
> 2 files changed, 35 insertions(+), 238 deletions(-)
>
> diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
> index 046ac4f43ba8..02f6ca6ab52b 100644
> --- a/drivers/gpu/drm/vc4/vc4_hdmi.c
> +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
> @@ -114,31 +114,6 @@
> #define HSM_MIN_CLOCK_FREQ 120000000
> #define CEC_CLOCK_FREQ 40000
>
> -static bool vc4_hdmi_supports_scrambling(struct vc4_hdmi *vc4_hdmi)
> -{
> - struct drm_display_info *display = &vc4_hdmi->connector.display_info;
> -
> - lockdep_assert_held(&vc4_hdmi->mutex);
> -
> - if (!display->is_hdmi)
> - return false;
> -
> - if (!display->hdmi.scdc.supported ||
> - !display->hdmi.scdc.scrambling.supported)
> - return false;
> -
> - return true;
> -}
> -
> -static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode,
> - unsigned int bpc,
> - enum drm_output_color_format fmt)
> -{
> - unsigned long long clock = drm_hdmi_compute_mode_clock(mode, bpc, fmt);
> -
> - return clock > HDMI_1_3_TMDS_CHAR_RATE_MAX_HZ;
> -}
> -
> static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
> {
> struct drm_debugfs_entry *entry = m->private;
> @@ -272,124 +247,6 @@ static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
> static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
> #endif
>
> -static int vc4_hdmi_reset_link(struct drm_connector *connector,
> - struct drm_modeset_acquire_ctx *ctx)
> -{
> - struct drm_device *drm;
> - struct vc4_hdmi *vc4_hdmi;
> - struct drm_connector_state *conn_state;
> - struct drm_crtc_state *crtc_state;
> - struct drm_crtc *crtc;
> - bool scrambling_needed;
> - u8 config;
> - int ret;
> -
> - if (!connector)
> - return 0;
> -
> - drm = connector->dev;
> - ret = drm_modeset_lock(&drm->mode_config.connection_mutex, ctx);
> - if (ret)
> - return ret;
> -
> - conn_state = connector->state;
> - crtc = conn_state->crtc;
> - if (!crtc)
> - return 0;
> -
> - ret = drm_modeset_lock(&crtc->mutex, ctx);
> - if (ret)
> - return ret;
> -
> - crtc_state = crtc->state;
> - if (!crtc_state->active)
> - return 0;
> -
> - vc4_hdmi = connector_to_vc4_hdmi(connector);
> - mutex_lock(&vc4_hdmi->mutex);
> -
> - if (!vc4_hdmi_supports_scrambling(vc4_hdmi)) {
> - mutex_unlock(&vc4_hdmi->mutex);
> - return 0;
> - }
> -
> - scrambling_needed = vc4_hdmi_mode_needs_scrambling(&vc4_hdmi->saved_adjusted_mode,
> - vc4_hdmi->output_bpc,
> - vc4_hdmi->output_format);
> - if (!scrambling_needed) {
> - mutex_unlock(&vc4_hdmi->mutex);
> - return 0;
> - }
> -
> - if (conn_state->commit &&
> - !try_wait_for_completion(&conn_state->commit->hw_done)) {
> - mutex_unlock(&vc4_hdmi->mutex);
> - return 0;
> - }
> -
> - ret = drm_scdc_readb(connector->ddc, SCDC_TMDS_CONFIG, &config);
> - if (ret < 0) {
> - drm_err(drm, "Failed to read TMDS config: %d\n", ret);
> - mutex_unlock(&vc4_hdmi->mutex);
> - return 0;
> - }
> -
> - if (!!(config & SCDC_SCRAMBLING_ENABLE) == scrambling_needed) {
> - mutex_unlock(&vc4_hdmi->mutex);
> - return 0;
> - }
> -
> - mutex_unlock(&vc4_hdmi->mutex);
> -
> - /*
> - * HDMI 2.0 says that one should not send scrambled data
> - * prior to configuring the sink scrambling, and that
> - * TMDS clock/data transmission should be suspended when
> - * changing the TMDS clock rate in the sink. So let's
> - * just do a full modeset here, even though some sinks
> - * would be perfectly happy if were to just reconfigure
> - * the SCDC settings on the fly.
> - */
> - return drm_atomic_helper_reset_crtc(crtc, ctx);
> -}
This one doesn't look functionally equivalent to me to
drm_scdc_reset_crtc: this part was, in part, making sure we would only
reset the scrambler if it was enabled in the first place.
drm_scdc_reset_crtc() doesn't and will always trigger a modeset on
hotplug. That's unnecessary and a significant functional different.
I'd argue that it's drm_scdc_reset_crtc() that needs to align to what
vc4 was doing, not the opposite.
> -static void vc4_hdmi_handle_hotplug(struct vc4_hdmi *vc4_hdmi,
> - struct drm_modeset_acquire_ctx *ctx,
> - enum drm_connector_status status)
> -{
> - struct drm_connector *connector = &vc4_hdmi->connector;
> - int ret;
> -
> - /*
> - * NOTE: This function should really be called with vc4_hdmi->mutex
> - * held, but doing so results in reentrancy issues since
> - * cec_s_phys_addr() might call .adap_enable, which leads to that
> - * funtion being called with our mutex held.
> - *
> - * A similar situation occurs with vc4_hdmi_reset_link() that
> - * will call into our KMS hooks if the scrambling was enabled.
> - *
> - * Concurrency isn't an issue at the moment since we don't share
> - * any state with any of the other frameworks so we can ignore
> - * the lock for now.
> - */
> -
> - drm_atomic_helper_connector_hdmi_hotplug(connector, status);
> -
> - if (status != connector_status_connected)
> - return;
> -
> - for (;;) {
> - ret = vc4_hdmi_reset_link(connector, ctx);
> - if (ret == -EDEADLK) {
> - drm_modeset_backoff(ctx);
> - continue;
> - }
> -
> - break;
> - }
> -}
> -
> static int vc4_hdmi_connector_detect_ctx(struct drm_connector *connector,
> struct drm_modeset_acquire_ctx *ctx,
> bool force)
> @@ -401,8 +258,8 @@ static int vc4_hdmi_connector_detect_ctx(struct drm_connector *connector,
> /*
> * NOTE: This function should really take vc4_hdmi->mutex, but
> * doing so results in reentrancy issues since
> - * vc4_hdmi_handle_hotplug() can call into other functions that
> - * would take the mutex while it's held here.
> + * drm_atomic_helper_connector_hdmi_hotplug_ctx() can call into other
> + * functions that would take the mutex while it's held here.
> *
> * Concurrency isn't an issue at the moment since we don't share
> * any state with any of the other frameworks so we can ignore
> @@ -425,10 +282,11 @@ static int vc4_hdmi_connector_detect_ctx(struct drm_connector *connector,
> status = connector_status_connected;
> }
>
> - vc4_hdmi_handle_hotplug(vc4_hdmi, ctx, status);
> + ret = drm_atomic_helper_connector_hdmi_hotplug_ctx(connector, status, ctx);
> +
> pm_runtime_put(&vc4_hdmi->pdev->dev);
>
> - return status;
> + return ret == -EDEADLK ? ret : status;
> }
>
> static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
> @@ -441,9 +299,12 @@ static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
> if (!vc4->hvs->vc5_hdmi_enable_hdmi_20) {
> struct drm_device *drm = connector->dev;
> const struct drm_display_mode *mode;
> + unsigned long long clock;
>
> list_for_each_entry(mode, &connector->probed_modes, head) {
> - if (vc4_hdmi_mode_needs_scrambling(mode, 8, DRM_OUTPUT_COLOR_FORMAT_RGB444)) {
> + clock = drm_hdmi_compute_mode_clock(mode, 8,
> + DRM_OUTPUT_COLOR_FORMAT_RGB444);
> + if (clock > HDMI_1_3_TMDS_CHAR_RATE_MAX_HZ) {
This should be a patch of its own, but I think we should turn
vc4_hdmi_mode_needs_scrambling() into a helper, instead of checking the
clock rate in every driver that might need it. From a logical standpoint
it's equivalent, but not from a semantic one.
> drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz.");
> drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60.");
> }
> @@ -540,6 +401,9 @@ static int vc4_hdmi_connector_init(struct drm_device *dev,
> if (vc4_hdmi->variant->supports_hdr)
> max_bpc = 12;
>
> + connector->hdmi.scrambler_supported =
> + vc4_hdmi->variant->max_pixel_clock > HDMI_1_3_TMDS_CHAR_RATE_MAX_HZ;
> +
> ret = drmm_connector_hdmi_init(dev, connector,
> "Broadcom", "Videocore",
> &vc4_hdmi_connector_funcs,
> @@ -561,6 +425,14 @@ static int vc4_hdmi_connector_init(struct drm_device *dev,
>
> drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
>
> + /*
> + * Since we don't know the state of the controller and its
> + * display (if any), let's assume it's always enabled.
> + * drm_scdc_stop_scrambling() will thus run at boot, make
> + * sure it's disabled, and avoid any inconsistency.
> + */
> + connector->hdmi.scrambler_enabled = connector->hdmi.scrambler_supported;
> +
> /*
> * Some of the properties below require access to state, like bpc.
> * Allocate some default initial connector state with our reset helper.
> @@ -786,93 +658,30 @@ static int vc4_hdmi_write_spd_infoframe(struct drm_connector *connector,
> buffer, len);
> }
>
> -#define SCRAMBLING_POLLING_DELAY_MS 1000
> -
> -static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
> +static int vc4_hdmi_scrambler_enable(struct drm_connector *connector)
> {
> - struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
> - struct drm_connector *connector = &vc4_hdmi->connector;
> - struct drm_device *drm = connector->dev;
> - const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
> + struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
> unsigned long flags;
> - int idx;
> -
> - lockdep_assert_held(&vc4_hdmi->mutex);
> -
> - if (!vc4_hdmi_supports_scrambling(vc4_hdmi))
> - return;
> -
> - if (!vc4_hdmi_mode_needs_scrambling(mode,
> - vc4_hdmi->output_bpc,
> - vc4_hdmi->output_format))
> - return;
> -
> - if (!drm_dev_enter(drm, &idx))
> - return;
drm_dev_enter should be kept here
> - drm_scdc_set_high_tmds_clock_ratio(connector, true);
> - drm_scdc_set_scrambling(connector, true);
>
> spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
> HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
> VC5_HDMI_SCRAMBLER_CTL_ENABLE);
> spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
>
> - drm_dev_exit(idx);
And exit here.
> -static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
> +static int vc4_hdmi_scrambler_disable(struct drm_connector *connector)
> {
> - struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
> - struct drm_connector *connector = &vc4_hdmi->connector;
> - struct drm_device *drm = connector->dev;
> + struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
> unsigned long flags;
> - int idx;
> -
> - lockdep_assert_held(&vc4_hdmi->mutex);
> -
> - if (!vc4_hdmi->scdc_enabled)
> - return;
> -
> - vc4_hdmi->scdc_enabled = false;
> -
> - if (delayed_work_pending(&vc4_hdmi->scrambling_work))
> - cancel_delayed_work_sync(&vc4_hdmi->scrambling_work);
> -
> - if (!drm_dev_enter(drm, &idx))
> - return;
Ditto
> spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
> HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
> ~VC5_HDMI_SCRAMBLER_CTL_ENABLE);
> spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
>
> - drm_scdc_set_scrambling(connector, false);
> - drm_scdc_set_high_tmds_clock_ratio(connector, false);
> -
> - drm_dev_exit(idx);
> -}
> -
> -static void vc4_hdmi_scrambling_wq(struct work_struct *work)
> -{
> - struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work),
> - struct vc4_hdmi,
> - scrambling_work);
> - struct drm_connector *connector = &vc4_hdmi->connector;
> -
> - if (drm_scdc_get_scrambling_status(connector))
> - return;
> -
> - drm_scdc_set_high_tmds_clock_ratio(connector, true);
> - drm_scdc_set_scrambling(connector, true);
> -
> - queue_delayed_work(system_percpu_wq, &vc4_hdmi->scrambling_work,
> - msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
> + return 0;
> }
>
> static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
> @@ -917,7 +726,7 @@ static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
> spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
> }
>
> - vc4_hdmi_disable_scrambling(encoder);
> + drm_scdc_stop_scrambling(&vc4_hdmi->connector);
I don't think the names here are right. It's not *only* related to scdc
but also to the HDMI controller. I'm fine with using a scdc prefix but
only for the things related to scdc. This is related (in part) to the
HDMI controller, so it should use a drm_connector_hdmi prefix.
> drm_dev_exit(idx);
>
> @@ -1625,6 +1434,7 @@ static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
> struct drm_display_info *display = &vc4_hdmi->connector.display_info;
> bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
> bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
> + struct drm_connector_state *conn_state;
> unsigned long flags;
> int ret;
> int idx;
> @@ -1693,7 +1503,10 @@ static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
> }
>
> vc4_hdmi_recenter_fifo(vc4_hdmi);
> - vc4_hdmi_enable_scrambling(encoder);
> +
> + conn_state = drm_atomic_get_new_connector_state(state, connector);
> + if (conn_state && conn_state->hdmi.scrambler_needed)
> + drm_scdc_start_scrambling(connector);
And the nice thing with a drm_connector_hdmi_* prefix is that you don't
have to shoehorn it into SCDC support anymore, so you can take a state
as an argument, and do the check in the helper instead of doing it in
every driver and hoping they get it right.
Maxime
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* Re: [PATCH v8 8/9] arm64: dts: imx943-evk: Add display support using IT6263
From: Laurentiu Palcu @ 2026-06-12 12:06 UTC (permalink / raw)
To: Liu Ying
Cc: imx, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam, dri-devel,
devicetree, linux-arm-kernel, linux-kernel
In-Reply-To: <1a3d466c-c1b5-49f1-a9ab-1c827e906e91@nxp.com>
Hi Ying,
On Fri, Mar 06, 2026 at 04:45:25PM +0800, Liu Ying wrote:
> On Wed, Mar 04, 2026 at 11:34:17AM +0000, Laurentiu Palcu wrote:
> > The ITE IT6263 based NXP LVDS to HDMI converter can be attached to the
> > i.MX943 EVK board LVDS port using the mini-SAS connector. Since this is
>
> Since the LVDS to HDMI converter can be attached or detached to the EVK
> board, it would be appropriate to use a DT overlay instead?
AFAIK, imx943 EVK ships with the IT6263 LVDS to HDMI adapter. So, I
believe it's preferable to have support for the adapter in the default
DTB instead of a DT overlay.
--
Thanks,
Laurentiu
^ permalink raw reply
* Re: [PATCH v7 02/30] drm/connector: Add HDMI 2.0 scrambler infrastructure
From: Maxime Ripard @ 2026-06-12 12:06 UTC (permalink / raw)
To: Cristian Ciocaltea
Cc: Maarten Lankhorst, Thomas Zimmermann, David Airlie, Simona Vetter,
Andrzej Hajda, Neil Armstrong, Robert Foss, Laurent Pinchart,
Jonas Karlman, Jernej Skrabec, Luca Ceresoli, Sandy Huang,
Heiko Stübner, Andy Yan, Daniel Stone, Dave Stevenson,
Maíra Canal, Raspberry Pi Kernel Maintenance, kernel,
dri-devel, linux-kernel, linux-arm-kernel, linux-rockchip
In-Reply-To: <20260602-dw-hdmi-qp-scramb-v7-2-445eb54ee1ed@collabora.com>
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On Tue, Jun 02, 2026 at 01:44:02AM +0300, Cristian Ciocaltea wrote:
> Add the connector-level infrastructure to support HDMI 2.0 scrambling:
>
> - A scrambler_supported flag to indicate whether the source supports the
> scrambling capability, in which case the newly introduced
> .scrambler_{enable|disable}() callbacks in drm_connector_hdmi_funcs
> are mandatory
> - A scrambler_needed flag to be managed by the hdmi state helpers based
> on the negotiated TMDS character rate and the source/sink scrambling
> capabilities
> - A scrambler_enabled flag to track whether scrambling is currently
> active
> - A delayed work item (scdc_work) with an associated callback (scdc_cb)
> to monitor sink-side scrambling status and retry the setup if the sink
> resets it
>
> These are intended to be used by SCDC scrambling helpers to coordinate
> scrambling setup and teardown between the source driver and the DRM
> core.
>
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
> ---
> drivers/gpu/drm/drm_connector.c | 18 +++++++++
> include/drm/drm_connector.h | 81 +++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 99 insertions(+)
>
> diff --git a/drivers/gpu/drm/drm_connector.c b/drivers/gpu/drm/drm_connector.c
> index a5d13b92b665..526dc2931b8a 100644
> --- a/drivers/gpu/drm/drm_connector.c
> +++ b/drivers/gpu/drm/drm_connector.c
> @@ -220,6 +220,19 @@ void drm_connector_free_work_fn(struct work_struct *work)
> }
> }
>
> +static void drm_connector_hdmi_scdc_work(struct work_struct *work)
> +{
> + struct drm_connector *connector;
> + struct drm_connector_hdmi *hdmi;
> +
> + hdmi = container_of(to_delayed_work(work), struct drm_connector_hdmi,
> + scdc_work);
> + connector = container_of(hdmi, struct drm_connector, hdmi);
> +
> + if (hdmi->scdc_cb)
> + hdmi->scdc_cb(connector);
> +}
> +
> static int drm_connector_init_only(struct drm_device *dev,
> struct drm_connector *connector,
> const struct drm_connector_funcs *funcs,
> @@ -285,6 +298,7 @@ static int drm_connector_init_only(struct drm_device *dev,
> mutex_init(&connector->edid_override_mutex);
> mutex_init(&connector->hdmi.infoframes.lock);
> mutex_init(&connector->hdmi_audio.lock);
> + INIT_DELAYED_WORK(&connector->hdmi.scdc_work, drm_connector_hdmi_scdc_work);
> connector->edid_blob_ptr = NULL;
> connector->epoch_counter = 0;
> connector->tile_blob_ptr = NULL;
> @@ -606,6 +620,10 @@ int drmm_connector_hdmi_init(struct drm_device *dev,
> !hdmi_funcs->hdmi.write_infoframe)
> return -EINVAL;
>
> + if (connector->hdmi.scrambler_supported &&
> + (!hdmi_funcs->scrambler_enable || !hdmi_funcs->scrambler_disable))
> + return -EINVAL;
> +
> ret = drmm_connector_init(dev, connector, funcs, connector_type, ddc);
> if (ret)
> return ret;
> diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h
> index 529755c2e862..f1c5c15a6cce 100644
> --- a/include/drm/drm_connector.h
> +++ b/include/drm/drm_connector.h
> @@ -28,6 +28,7 @@
> #include <linux/ctype.h>
> #include <linux/hdmi.h>
> #include <linux/notifier.h>
> +#include <linux/workqueue.h>
> #include <drm/drm_mode_object.h>
> #include <drm/drm_util.h>
> #include <drm/drm_property.h>
> @@ -1057,6 +1058,19 @@ struct drm_connector_hdmi_state {
> * @tmds_char_rate: TMDS Character Rate, in Hz.
> */
> unsigned long long tmds_char_rate;
> +
> + /**
> + * @scrambler_needed: Whether HDMI 2.0 SCDC scrambling is required
> + * for the negotiated mode/bpc/format.
> + *
> + * Computed by drm_atomic_helper_connector_hdmi_check() from
> + * @tmds_char_rate and the source/sink scrambling capabilities.
> + *
> + * Per HDMI 2.0, scrambling is mandatory above 340 MHz TMDS
> + * character rate. Optional scrambling at lower rates is
> + * deliberately not requested by the helper.
> + */
> + bool scrambler_needed;
> };
>
> /**
> @@ -1358,6 +1372,36 @@ struct drm_connector_hdmi_funcs {
> */
> const struct drm_edid *(*read_edid)(struct drm_connector *connector);
>
> + /**
> + * @scrambler_enable:
> + *
> + * This callback is invoked through @drm_scdc_start_scrambling during
> + * a commit to setup SCDC scrambling and high TMDS clock ratio on
> + * source side.
> + *
> + * The @scrambler_enable callback is mandatory if HDMI 2.0 is to be
> + * supported.
> + *
> + * Returns:
> + * 0 on success, a negative error code otherwise
> + */
> + int (*scrambler_enable)(struct drm_connector *connector);
> +
> + /**
> + * @scrambler_disable:
> + *
> + * This callback is invoked through @drm_scdc_stop_scrambling during
> + * a commit to disable SCDC scrambling and high TMDS clock ratio on
> + * source side.
> + *
> + * The @scrambler_disable callback is mandatory if HDMI 2.0 is to be
> + * supported.
> + *
> + * Returns:
> + * 0 on success, a negative error code otherwise
> + */
> + int (*scrambler_disable)(struct drm_connector *connector);
> +
> /**
> * @avi:
> *
> @@ -1960,6 +2004,43 @@ struct drm_connector_hdmi {
> */
> unsigned long supported_formats;
>
> + /**
> + * @scrambler_supported: Indicates whether the HDMI controller
> + * (source) supports HDMI 2.0 SCDC scrambling.
> + *
> + * When true, @drm_connector_hdmi_funcs.scrambler_enable and
> + * @drm_connector_hdmi_funcs.scrambler_disable are mandatory.
> + * This is enforced by drmm_connector_hdmi_init().
> + *
> + * For HDMI bridge based drivers using drm_bridge_connector_init(),
> + * this is propagated automatically from bridges that set the
> + * DRM_BRIDGE_OP_HDMI_SCRAMBLER flag in their &drm_bridge->ops.
> + * Other drivers must set this field on @connector->hdmi before calling
> + * drmm_connector_hdmi_init().
> + */
> + bool scrambler_supported;
> +
> + /**
> + * @scrambler_enabled: Tracks whether HDMI 2.0 scrambler is currently enabled.
> + */
> + bool scrambler_enabled;
This is already in the state. Why do you need to copy it over here, and
if you do, you'll need a lock.
Maxime
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* Re: [PATCH] net: macb: add TX stall timeout callback to recover from lost TSTART write
From: Nicolai Buchwitz @ 2026-06-12 12:23 UTC (permalink / raw)
To: Andrea della Porta
Cc: netdev, Theo Lebrun, Nicolas Ferre, Claudiu Beznea, Andrew Lunn,
David S . Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
linux-kernel, linux-arm-kernel, linux-rpi-kernel, Lukasz Raczylo,
Steffen Jaeckel
In-Reply-To: <771b8faeaee1fce4a84a5ba2661d60b35a65a6d5.1781253818.git.andrea.porta@suse.com>
Hi Andrea
On 12.6.2026 11:01, Andrea della Porta wrote:
> From: Lukasz Raczylo <lukasz@raczylo.com>
>
> The MACB found in the Raspberry Pi RP1 suffers from sporadic stalls on
> the TX queue.
> While the exact root cause is not yet fully understood, it is likely
> related to a hardware issue where a TSTART write to the NCR register
> is missed, preventing the transmission from being kicked off.
>
> Implement a timeout callback to handle TX queue stalls, triggering the
> existing restart mechanism to recover.
>
> Link:
> https://lore.kernel.org/all/20260514215459.36109-1-lukasz@raczylo.com/
> Fixes: dc110d1b23564 ("net: cadence: macb: Add support for Raspberry Pi
> RP1 ethernet controller")
> Signed-off-by: Lukasz Raczylo <lukasz@raczylo.com>
> Co-developed-by: Steffen Jaeckel <sjaeckel@suse.de>
> Signed-off-by: Steffen Jaeckel <sjaeckel@suse.de>
> Co-developed-by: Andrea della Porta <andrea.porta@suse.com>
> Signed-off-by: Andrea della Porta <andrea.porta@suse.com>
> ---
> drivers/net/ethernet/cadence/macb_main.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/drivers/net/ethernet/cadence/macb_main.c
> b/drivers/net/ethernet/cadence/macb_main.c
> index a12aa21244e83..615da65d5d68d 100644
> --- a/drivers/net/ethernet/cadence/macb_main.c
> +++ b/drivers/net/ethernet/cadence/macb_main.c
> @@ -4522,6 +4522,16 @@ static int macb_setup_tc(struct net_device *dev,
> enum tc_setup_type type,
> }
> }
>
> +static void macb_tx_timeout(struct net_device *dev, unsigned int q)
> +{
> + struct macb *bp = netdev_priv(dev);
> +
> + if (net_ratelimit())
Do we need the net_ratelimit() check (and message) here? AFAIU the
watchdog core already prints a message for every timeout.
> + netdev_err(dev, "TX stall detected, re-kicking TSTART\n");
> + dev->stats.tx_errors++;
> + macb_tx_restart(&bp->queues[q]);
> +}
> +
> static const struct net_device_ops macb_netdev_ops = {
> .ndo_open = macb_open,
> .ndo_stop = macb_close,
> @@ -4540,6 +4550,7 @@ static const struct net_device_ops
> macb_netdev_ops = {
> .ndo_hwtstamp_set = macb_hwtstamp_set,
> .ndo_hwtstamp_get = macb_hwtstamp_get,
> .ndo_setup_tc = macb_setup_tc,
> + .ndo_tx_timeout = macb_tx_timeout,
The commit message describes it as RP1 specific, but it gets applied to
all other variants?
> };
>
> /* Configure peripheral capabilities according to device tree
Thanks
Nicolai
^ permalink raw reply
* Re: [PATCH] spi: uniphier: Fix completion initialization order before devm_request_irq()
From: Mark Brown @ 2026-06-12 12:37 UTC (permalink / raw)
To: Kunihiko Hayashi
Cc: linux-spi, linux-arm-kernel, linux-kernel, Sangyun Kim,
Kyungwook Boo, stable, Masami Hiramatsu
In-Reply-To: <cd454dac-868d-43b9-9b50-9ba9f3f370a9@socionext.com>
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On Fri, Jun 12, 2026 at 05:17:49PM +0900, Kunihiko Hayashi wrote:
> On 2026/06/11 23:09, Mark Brown wrote:
> > This doesn't apply against current code, please check and resend.
> That seems a bit strange. I applied this patch to v7.0 and linux-next successfully.
> Which tree did you apply to and fail?
It applies to none of spi/for-7.1, spi/for-7.2 nor spi/for-next.
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* [PATCH net-next 0/9] net: sparx5: add L3 unicast routing offload
From: Jens Emil Schulz Østergaard @ 2026-06-12 12:37 UTC (permalink / raw)
To: Horatiu Vultur, UNGLinuxDriver, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Daniel Machon,
Steen Hegelund, Kees Cook, Gustavo A. R. Silva
Cc: netdev, linux-kernel, linux-arm-kernel, linux-hardening,
Jens Emil Schulz Østergaard
Add L3 unicast route offloading for IPv4 and IPv6 on Sparx5 and
LAN969x. This enables hardware-accelerated l3 routing between VLAN
upper interfaces on a bridge, with ECMP support.
This series covers the core unicast data path: FIB offload, nexthop
groups, ARP/NDP neighbour resolution, and router leg management.
Routes are programmed into the hardware LPM (Longest Prefix Match)
VCAP, with nexthops resolved through the hardware ARP table for ECMP
or inline VCAP actions for single nexthops.
The LPM VCAP also requires type_id-aware rule decoding, since it has
actionsets of identical length that differ only in their type_id
field.
Patch 1 fixes a latent bug in the VCAP rule-move algorithm that
becomes reachable once the LPM VCAP is added, since LPM is the first
VCAP to use rules of coprime size (2 and 3).
Patches 2-4 are the remaining preparatory commits for the shared VCAP
API. They add the LPM VCAP keysets and actionsets to the autogenerated
model for lan969x and sparx5, update the action-side rule decoder to
differentiate actionsets by type_id, and expose two helpers
(vcap_val_add_rule() and vcap_rule_mod_action_bit()) used by the LPM
driver.
Patch 5 adds autogenerated register macros for the L3 routing blocks
on sparx5 and lan969x.
Patch 6 adds the LPM VCAP implementation for sparx5 and lan969x.
Patches 7-9 add L3 unicast routing to sparx5 and lan969x. The router
code is split into three patches:
Patch 7 (infrastructure + legs): Router leg lifecycle tied to VLAN
uppers on a bridge, address event handling, base MAC tracking,
blackhole leg for blackhole routes, and the hardware enable sequence.
Patch 8 (FIB + nexthop + neighbour CRUD): This is a large patch, and
splitting it further is difficult due to the dependencies in FIB and
neighbour event paths. The destroy path for a FIB entry must update
neighbour state and notify nexthops, so neighbour CRUD functions are
called from both the FIB event path and the neighbour event path.
Patch 9 (neighbour events): Registers the netevent notifier for
NETEVENT_NEIGH_UPDATE used in ARP/NDP resolution, wiring up the final
piece.
Signed-off-by: Jens Emil Schulz Østergaard <jensemil.schulzostergaard@microchip.com>
---
Jens Emil Schulz Østergaard (9):
net: microchip: vcap: fix rule move for rules of coprime size
net: microchip: vcap: add lpm vcap to autogen vcap api
net: microchip: vcap: make vcap actionset decoding type_id aware
net: microchip: vcap: expose helpers in vcap api and update debugfs
net: sparx5: add l3 routing registers
net: sparx5: vcap: add lpm vcap implementation
net: sparx5: add L3 router infrastructure and leg management
net: sparx5: add L3 FIB, nexthop and neighbour entry management
net: sparx5: add neighbour event handling for L3 routing
drivers/net/ethernet/microchip/sparx5/Makefile | 2 +-
.../ethernet/microchip/sparx5/lan969x/lan969x.c | 2 +
.../microchip/sparx5/lan969x/lan969x_regs.c | 20 +-
.../microchip/sparx5/lan969x/lan969x_vcap_ag_api.c | 373 ++-
.../microchip/sparx5/lan969x/lan969x_vcap_impl.c | 12 +
.../net/ethernet/microchip/sparx5/sparx5_main.c | 13 +-
.../net/ethernet/microchip/sparx5/sparx5_main.h | 46 +
.../ethernet/microchip/sparx5/sparx5_main_regs.h | 691 ++++-
.../net/ethernet/microchip/sparx5/sparx5_regs.c | 20 +-
.../net/ethernet/microchip/sparx5/sparx5_regs.h | 20 +-
.../net/ethernet/microchip/sparx5/sparx5_router.c | 3095 ++++++++++++++++++++
.../ethernet/microchip/sparx5/sparx5_vcap_ag_api.c | 373 ++-
.../ethernet/microchip/sparx5/sparx5_vcap_ag_api.h | 6 +-
.../ethernet/microchip/sparx5/sparx5_vcap_impl.c | 159 +-
.../ethernet/microchip/sparx5/sparx5_vcap_impl.h | 5 +
drivers/net/ethernet/microchip/vcap/vcap_ag_api.h | 94 +-
drivers/net/ethernet/microchip/vcap/vcap_api.c | 219 +-
drivers/net/ethernet/microchip/vcap/vcap_api.h | 4 +-
.../net/ethernet/microchip/vcap/vcap_api_client.h | 6 +
.../net/ethernet/microchip/vcap/vcap_api_debugfs.c | 13 +-
.../net/ethernet/microchip/vcap/vcap_api_kunit.c | 81 +-
.../net/ethernet/microchip/vcap/vcap_model_kunit.c | 6 +-
22 files changed, 5123 insertions(+), 137 deletions(-)
---
base-commit: f6033078a9e671e3c8b83d387b91591a6f6a54e7
change-id: 20260210-sparx5_l3_routing-962458e4d3da
Best regards,
--
Jens Emil Schulz Østergaard <jensemil.schulzostergaard@microchip.com>
^ permalink raw reply
* [PATCH net-next 1/9] net: microchip: vcap: fix rule move for rules of coprime size
From: Jens Emil Schulz Østergaard @ 2026-06-12 12:37 UTC (permalink / raw)
To: Horatiu Vultur, UNGLinuxDriver, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Daniel Machon,
Steen Hegelund, Kees Cook, Gustavo A. R. Silva
Cc: netdev, linux-kernel, linux-arm-kernel, linux-hardening,
Jens Emil Schulz Østergaard
In-Reply-To: <20260612-sparx5_l3_routing-v1-0-fc3c10160f49@microchip.com>
Fix a discrepancy between how software and hardware moves rule
addresses on insert and delete. Hardware moves a block of addresses by a
uniform offset. The software representation stores the addresses of
rules. These are updated individually by computing a space-optimal
address relative to its neighbor.
This worked when all rule sizes in a VCAP formed a divisibility
chain (e.g. 1, 2, 6, 12), because any valid offset for the largest
rule was also valid for all smaller rules. At the moment all clients of
the VCAP library only uses rules for which this is true.
But the LPM VCAP, necessary for l3 routing, will introduce rule types of
coprime size, so the algorithm must be fixed. This is in preparation for
adding support for L3 routing to sparx5 and lan969x, which requires the
LPM VCAP with rules of size 2 and 3. This patch fixes the issue by
making sure the software representation is updated in the same way as
the hardware.
The VCAP rule model has the following properties:
- A rule has keyset size K and actionset size M; rule size N =
max(K, M).
- Rules are naturally aligned to their size (start_addr % N == 0).
- Rules are sorted by size with larger rules at higher addresses.
- HW moves a contiguous block of addresses by a uniform offset.
Introducing rules of coprime size 2 and 3 exposes these four bugs:
1) Move count on insert includes addresses beyond the moved block.
When padding exists between rules of different sizes, the count
overshoots, corrupting the rule above.
2) Move offset does not preserve alignment for the entire block.
Per-rule optimal offsets differ from the uniform HW offset,
causing HW/SW desync and misaligned rules.
3) On deletion, HW memory at the removed rule's addresses is not
initialized. The moved block may not fully cover them due to
padding, leaving stale data.
4) On deletion, padding between rules is not reclaimed.
Example for issue 1, insert corrupts rule above:
Starting state (X6 rule followed by X2):
Addr Rule
35 X6
34 X6
33 X6
32 X6
31 X6
30 X6
29 X2
28 X2
27
Insert X3 between X6 and X2. SW places rules optimally, X2 needs
padding:
Addr Rule (SW)
35 X6
34 X6
33 X6
32 X6
31 X6
30 X6
29 X3
28 X3
27 X3
26 (pad)
25 X2
24 X2
Move count = X3.addr - X2.addr = 27 - 24 = 3. HW moves 3 addresses
starting at 28: addrs {28, 29, 30}. But addr 30 is the base of X6,
so the move corrupts it:
Addr Rule (HW)
35 X6
34 X6
33 X6
32 X6
31 X6
30 ?? <- corrupted, was base of X6
...
26 X6 <- stale copy of addr 30
25 X2
24 X2
Example for issue 2, delete misaligns rule:
Starting state:
Addr Rule
38 <- LAST_VALID_ADDR
35 X6
34 X6
33 X6
32 X6
31 X6
30 X6
29 X3
28 X3
27 X3
26 (pad)
25 X2
24 X2
Delete X6. Old code computes: offset = 39 - 30 - 6 = 3, gap = 0,
each rule moves by 6 + 0 + 3 = 9:
X3: 27 + 9 = 36 (36 % 3 == 0, OK)
X2: 24 + 9 = 33 (33 % 2 == 1, MISALIGNED)
Offset 9 is not a multiple of LCM(3, 2) = 6, breaking X2 alignment.
Example for issues 1 + 2, insert desyncs HW/SW and misaligns:
Starting state:
Addr Rule
26 X3 <- LAST_VALID_ADDR
25 X3
24 X3
23 X2
22 X2
Insert X6. SW calculates different per-rule offsets:
X3 needs offset 9 (to addr 15)
X2 needs offset 10 (to addr 12)
Old code computes: count = 18 - 12 = 6 (should be 5), offset = 10.
HW applies uniform offset 10 to 6 addresses:
Addr Rule (SW) Addr Rule (HW)
17 X3 17
16 X3 16 X3
15 X3 15 X3
14 14 X3 <- misaligned (14 % 3 != 0)
13 X2 13 X2
12 X2 12 X2
HW and SW are out of sync, and X3 is misaligned in HW.
The new move algorithm computes a single uniform offset for the
entire block, aligned to the LCM of all rule sizes in that block.
This guarantees that every rule lands on a naturally aligned address
after the HW move, and that HW and SW stay in sync.
On insert:
1. Determine the move block: all rules below the insertion point.
2. Compute the LCM of all rule sizes in the block
(vcap_find_move_block_lcm).
3. Compute the move offset as the inserted rule's size rounded up
to the next LCM multiple (vcap_move_from_block). This is the
uniform offset applied to the entire block.
4. Move count is exactly the number of addresses occupied by the
block (no overshoot into the rule above).
5. Issue a single HW move, then update all SW rule addresses by
the same uniform offset (vcap_move_rules_sw).
6. Place the new rule in the gap created by the move.
On delete:
1. Initialize HW memory at the deleted rule's addresses before
moving, since the moved block may not fully cover them due to
padding.
2. Reclaim any padding between rules in the block.
3. Compute the LCM-aligned uniform offset and move count as above.
4. Issue a single HW move and update SW addresses uniformly.
No VCAP api client uses rules of coprime size today, so the bug does not
fire in any existing configuration. The LPM VCAP for sparx5 and lan969x,
added later in this series, is the first instance with rules of coprime
sizes (2 and 3), and therefore the first to reach this bug.
Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com>
Signed-off-by: Jens Emil Schulz Østergaard <jensemil.schulzostergaard@microchip.com>
---
drivers/net/ethernet/microchip/vcap/vcap_api.c | 178 +++++++++++++--------
.../net/ethernet/microchip/vcap/vcap_api_kunit.c | 81 ++++++----
2 files changed, 164 insertions(+), 95 deletions(-)
diff --git a/drivers/net/ethernet/microchip/vcap/vcap_api.c b/drivers/net/ethernet/microchip/vcap/vcap_api.c
index 0fdb5e363bad..6946fd738458 100644
--- a/drivers/net/ethernet/microchip/vcap/vcap_api.c
+++ b/drivers/net/ethernet/microchip/vcap/vcap_api.c
@@ -4,7 +4,9 @@
* Copyright (c) 2022 Microchip Technology Inc. and its subsidiaries.
*/
+#include <linux/lcm.h>
#include <linux/types.h>
+#include <linux/minmax.h>
#include "vcap_api_private.h"
@@ -2096,12 +2098,63 @@ static u32 vcap_set_rule_id(struct vcap_rule_internal *ri)
return ri->data.id;
}
+static void vcap_move_from_block(u32 base_addr,
+ struct vcap_rule_internal *block_first,
+ struct vcap_rule_internal *block_last,
+ int block_lcm, struct vcap_rule_move *move)
+{
+ int unaligned_offset;
+
+ if (!block_first || !block_last)
+ return;
+
+ move->addr = block_last->addr;
+ move->count = block_first->addr + block_first->size - block_last->addr;
+ /* Integer division rounds toward zero. We want to round toward +inf
+ * for the positive case (insertion) to ensure enough room.
+ */
+ unaligned_offset = (block_first->addr + block_first->size) - base_addr;
+ if (unaligned_offset > 0)
+ move->offset =
+ ((unaligned_offset + (block_lcm - 1)) / block_lcm) *
+ block_lcm;
+ else
+ move->offset = (unaligned_offset / block_lcm) * block_lcm;
+}
+
+static void vcap_move_rules_sw(struct vcap_admin *admin,
+ struct vcap_rule_internal *pos,
+ struct vcap_rule_move const *move)
+{
+ if (move->count == 0 || move->offset == 0)
+ return;
+
+ list_for_each_entry_continue(pos, &admin->rules, list)
+ pos->addr -= move->offset;
+}
+
+static int vcap_find_move_block_lcm(struct vcap_admin *admin,
+ struct vcap_rule_internal *pos)
+{
+ int block_lcm = 1;
+
+ list_for_each_entry_continue(pos, &admin->rules, list) {
+ block_lcm = lcm(block_lcm, pos->size);
+ if (pos->size <= 2)
+ break;
+ }
+
+ return block_lcm;
+}
+
static int vcap_insert_rule(struct vcap_rule_internal *ri,
struct vcap_rule_move *move)
{
+ struct vcap_rule_internal *duprule, *iter, *block_first = NULL,
+ *block_last;
int sw_count = ri->vctrl->vcaps[ri->admin->vtype].sw_count;
- struct vcap_rule_internal *duprule, *iter, *elem = NULL;
struct vcap_admin *admin = ri->admin;
+ int block_lcm;
u32 addr;
ri->sort_key = vcap_sort_key(sw_count, ri->size, ri->data.user,
@@ -2114,12 +2167,12 @@ static int vcap_insert_rule(struct vcap_rule_internal *ri,
*/
list_for_each_entry(iter, &admin->rules, list) {
if (ri->sort_key < iter->sort_key) {
- elem = iter;
+ block_first = iter;
break;
}
}
- if (!elem) {
+ if (!block_first) {
ri->addr = vcap_next_rule_addr(admin->last_used_addr, ri);
admin->last_used_addr = ri->addr;
@@ -2132,10 +2185,13 @@ static int vcap_insert_rule(struct vcap_rule_internal *ri,
return 0;
}
- /* Reuse the space of the current rule */
- addr = elem->addr + elem->size;
+ block_last = list_last_entry(&admin->rules, typeof(*ri), list);
+
+ /* Reuse the space and padding of the current rule */
+ addr = admin->last_valid_addr + 1;
+ if (!list_is_first(&block_first->list, &admin->rules))
+ addr = list_prev_entry(block_first, list)->addr;
ri->addr = vcap_next_rule_addr(addr, ri);
- addr = ri->addr;
/* Add a copy of the rule to the VCAP list */
duprule = vcap_dup_rule(ri, ri->state == VCAP_RS_DISABLED);
@@ -2143,29 +2199,34 @@ static int vcap_insert_rule(struct vcap_rule_internal *ri,
return PTR_ERR(duprule);
/* Add before the current entry */
- list_add_tail(&duprule->list, &elem->list);
+ list_add_tail(&duprule->list, &block_first->list);
- /* Update the current rule */
- elem->addr = vcap_next_rule_addr(addr, elem);
- addr = elem->addr;
+ /* Collect block move info in struct move, to update VCAP HW later */
+ block_lcm = vcap_find_move_block_lcm(admin, duprule);
+ vcap_move_from_block(ri->addr, block_first, block_last, block_lcm,
+ move);
- /* Update the address in the remaining rules in the list */
- list_for_each_entry_continue(elem, &admin->rules, list) {
- elem->addr = vcap_next_rule_addr(addr, elem);
- addr = elem->addr;
+ if ((int)block_last->addr - move->offset < admin->first_valid_addr) {
+ pr_err("%s:%d: No room for rule size: %u, %u\n", __func__,
+ __LINE__, duprule->size, admin->first_valid_addr);
+ list_del(&duprule->list);
+ vcap_free_rule(&duprule->data);
+ return -ENOSPC;
}
- /* Update the move info */
- move->addr = admin->last_used_addr;
- move->count = ri->addr - addr;
- move->offset = admin->last_used_addr - addr;
- admin->last_used_addr = addr;
+ /* Apply move to SW */
+ vcap_move_rules_sw(admin, duprule, move);
+ admin->last_used_addr =
+ list_last_entry(&admin->rules, typeof(*ri), list)->addr;
return 0;
}
static void vcap_move_rules(struct vcap_rule_internal *ri,
struct vcap_rule_move *move)
{
+ if (move->count == 0 || move->offset == 0)
+ return;
+
ri->vctrl->ops->move(ri->ndev, ri->admin, move->addr,
move->offset, move->count);
}
@@ -2275,8 +2336,7 @@ int vcap_add_rule(struct vcap_rule *rule)
__func__, __LINE__, ret);
goto out;
}
- if (move.count > 0)
- vcap_move_rules(ri, &move);
+ vcap_move_rules(ri, &move);
/* Set the counter to zero */
ret = vcap_write_counter(ri, &ctr);
@@ -2488,59 +2548,52 @@ int vcap_mod_rule(struct vcap_rule *rule)
}
EXPORT_SYMBOL_GPL(vcap_mod_rule);
-/* Return the alignment offset for a new rule address */
-static int vcap_valid_rule_move(struct vcap_rule_internal *el, int offset)
-{
- return (el->addr + offset) % el->size;
-}
-
-/* Update the rule address with an offset */
-static void vcap_adjust_rule_addr(struct vcap_rule_internal *el, int offset)
-{
- el->addr += offset;
-}
-
/* Rules needs to be moved to fill the gap of the deleted rule */
static int vcap_fill_rule_gap(struct vcap_rule_internal *ri)
{
+ struct vcap_rule_internal *block_first = NULL, *block_last = NULL;
struct vcap_admin *admin = ri->admin;
- struct vcap_rule_internal *elem;
- struct vcap_rule_move move;
- int gap = 0, offset = 0;
+ struct net_device *ndev = ri->ndev;
+ struct vcap_rule_move move = {};
+ int block_lcm, addr;
- /* If the first rule is deleted: Move other rules to the top */
- if (list_is_first(&ri->list, &admin->rules))
- offset = admin->last_valid_addr + 1 - ri->addr - ri->size;
+ if (!list_is_last(&ri->list, &admin->rules)) {
+ block_first = list_next_entry(ri, list);
+ block_last = list_last_entry(&admin->rules, typeof(*ri), list);
+ }
- /* Locate gaps between odd size rules and adjust the move */
- elem = ri;
- list_for_each_entry_continue(elem, &admin->rules, list)
- gap += vcap_valid_rule_move(elem, ri->size);
+ addr = admin->last_valid_addr + 1;
+ if (!list_is_first(&ri->list, &admin->rules))
+ addr = list_prev_entry(ri, list)->addr;
- /* Update the address in the remaining rules in the list */
- elem = ri;
- list_for_each_entry_continue(elem, &admin->rules, list)
- vcap_adjust_rule_addr(elem, ri->size + gap + offset);
+ block_lcm = vcap_find_move_block_lcm(admin, ri);
+ vcap_move_from_block(addr, block_first, block_last, block_lcm, &move);
- /* Update the move info */
- move.addr = admin->last_used_addr;
- move.count = ri->addr - admin->last_used_addr - gap;
- move.offset = -(ri->size + gap + offset);
+ /* Apply move to SW representation */
+ vcap_move_rules_sw(admin, ri, &move);
- /* Do the actual move operation */
+ /* Initialize space used by ri, as it may not be overwritten by move */
+ ri->vctrl->ops->init(ndev, admin, ri->addr, ri->size);
+
+ /* Apply move to HW. The VCAP move command automatically disables
+ * (initializes) the source addresses, so no separate init is needed
+ * for the vacated positions.
+ */
vcap_move_rules(ri, &move);
- return gap + offset;
+ if (block_last)
+ return block_last->addr;
+
+ return addr;
}
/* Delete rule in a VCAP instance */
int vcap_del_rule(struct vcap_control *vctrl, struct net_device *ndev, u32 id)
{
- struct vcap_rule_internal *ri, *elem;
+ struct vcap_rule_internal *ri;
struct vcap_admin *admin;
- int gap = 0, err;
+ int err;
- /* This will later also handle rule moving */
if (!ndev)
return -ENODEV;
err = vcap_api_check(vctrl);
@@ -2553,23 +2606,12 @@ int vcap_del_rule(struct vcap_control *vctrl, struct net_device *ndev, u32 id)
admin = ri->admin;
- if (ri->addr > admin->last_used_addr)
- gap = vcap_fill_rule_gap(ri);
+ admin->last_used_addr = vcap_fill_rule_gap(ri);
/* Delete the rule from the list of rules and the cache */
list_del(&ri->list);
- vctrl->ops->init(ndev, admin, admin->last_used_addr, ri->size + gap);
vcap_free_rule(&ri->data);
- /* Update the last used address, set to default when no rules */
- if (list_empty(&admin->rules)) {
- admin->last_used_addr = admin->last_valid_addr + 1;
- } else {
- elem = list_last_entry(&admin->rules, struct vcap_rule_internal,
- list);
- admin->last_used_addr = elem->addr;
- }
-
mutex_unlock(&admin->lock);
return err;
}
diff --git a/drivers/net/ethernet/microchip/vcap/vcap_api_kunit.c b/drivers/net/ethernet/microchip/vcap/vcap_api_kunit.c
index ce26ccbdccdf..cec818938ec9 100644
--- a/drivers/net/ethernet/microchip/vcap/vcap_api_kunit.c
+++ b/drivers/net/ethernet/microchip/vcap/vcap_api_kunit.c
@@ -1575,7 +1575,7 @@ static void vcap_api_rule_insert_in_order_test(struct kunit *test)
.lookups = 4,
.last_valid_addr = 3071,
.first_valid_addr = 0,
- .last_used_addr = 800,
+ .last_used_addr = 804,
.cache = {
.keystream = keydata,
.maskstream = mskdata,
@@ -1583,15 +1583,28 @@ static void vcap_api_rule_insert_in_order_test(struct kunit *test)
},
};
+ struct vcap_rule_internal ri0 = {
+ .data = {
+ .id = 2001,
+ },
+ .addr = 804,
+ .size = 12,
+ .sort_key = vcap_sort_key(12, 12, 0, 0),
+ .admin = &admin,
+ .counter_id = 2002,
+ .vctrl = &test_vctrl,
+ };
+
vcap_test_api_init(&admin);
+ list_add_tail(&ri0.list, &admin.rules);
/* Create rules with different sizes and check that they are placed
* at the correct address in the VCAP according to size
*/
- test_vcap_xn_rule_creator(test, 10000, VCAP_USER_QOS, 10, 500, 12, 780);
- test_vcap_xn_rule_creator(test, 10000, VCAP_USER_QOS, 20, 400, 6, 774);
- test_vcap_xn_rule_creator(test, 10000, VCAP_USER_QOS, 30, 300, 3, 771);
- test_vcap_xn_rule_creator(test, 10000, VCAP_USER_QOS, 40, 200, 2, 768);
+ test_vcap_xn_rule_creator(test, 10000, VCAP_USER_QOS, 10, 500, 12, 792);
+ test_vcap_xn_rule_creator(test, 10000, VCAP_USER_QOS, 20, 400, 6, 786);
+ test_vcap_xn_rule_creator(test, 10000, VCAP_USER_QOS, 30, 300, 3, 783);
+ test_vcap_xn_rule_creator(test, 10000, VCAP_USER_QOS, 40, 200, 2, 780);
vcap_del_rule(&test_vctrl, &test_netdev, 200);
vcap_del_rule(&test_vctrl, &test_netdev, 300);
@@ -1613,7 +1626,7 @@ static void vcap_api_rule_insert_reverse_order_test(struct kunit *test)
.lookups = 4,
.last_valid_addr = 3071,
.first_valid_addr = 0,
- .last_used_addr = 800,
+ .last_used_addr = 804,
.cache = {
.keystream = keydata,
.maskstream = mskdata,
@@ -1621,40 +1634,54 @@ static void vcap_api_rule_insert_reverse_order_test(struct kunit *test)
},
};
struct vcap_rule_internal *elem;
- u32 exp_addr[] = {780, 774, 771, 768, 767};
+ u32 exp_addr[] = {804, 792, 786, 783, 780};
int idx;
+ /* Existing X12 rule at last_used_addr */
+ struct vcap_rule_internal ri0 = {
+ .data = {
+ .id = 2001,
+ },
+ .addr = 804,
+ .size = 12,
+ .sort_key = vcap_sort_key(12, 12, 0, 0),
+ .admin = &admin,
+ .counter_id = 2002,
+ .vctrl = &test_vctrl,
+ };
+
vcap_test_api_init(&admin);
+ list_add_tail(&ri0.list, &admin.rules);
/* Create rules with different sizes and check that they are placed
* at the correct address in the VCAP according to size
*/
- test_vcap_xn_rule_creator(test, 10000, VCAP_USER_QOS, 20, 200, 2, 798);
+ test_vcap_xn_rule_creator(test, 10000, VCAP_USER_QOS, 20, 200, 2, 802);
KUNIT_EXPECT_EQ(test, 0, test_move_offset);
KUNIT_EXPECT_EQ(test, 0, test_move_count);
KUNIT_EXPECT_EQ(test, 0, test_move_addr);
- test_vcap_xn_rule_creator(test, 10000, VCAP_USER_QOS, 30, 300, 3, 795);
- KUNIT_EXPECT_EQ(test, 6, test_move_offset);
- KUNIT_EXPECT_EQ(test, 3, test_move_count);
- KUNIT_EXPECT_EQ(test, 798, test_move_addr);
+ test_vcap_xn_rule_creator(test, 10000, VCAP_USER_QOS, 30, 300, 3, 801);
+ KUNIT_EXPECT_EQ(test, 4, test_move_offset);
+ KUNIT_EXPECT_EQ(test, 2, test_move_count);
+ KUNIT_EXPECT_EQ(test, 802, test_move_addr);
- test_vcap_xn_rule_creator(test, 10000, VCAP_USER_QOS, 40, 400, 6, 792);
+ test_vcap_xn_rule_creator(test, 10000, VCAP_USER_QOS, 40, 400, 6, 798);
KUNIT_EXPECT_EQ(test, 6, test_move_offset);
KUNIT_EXPECT_EQ(test, 6, test_move_count);
- KUNIT_EXPECT_EQ(test, 792, test_move_addr);
+ KUNIT_EXPECT_EQ(test, 798, test_move_addr);
- test_vcap_xn_rule_creator(test, 10000, VCAP_USER_QOS, 50, 500, 12, 780);
- KUNIT_EXPECT_EQ(test, 18, test_move_offset);
+ test_vcap_xn_rule_creator(test, 10000, VCAP_USER_QOS, 50, 500, 12, 792);
+ KUNIT_EXPECT_EQ(test, 12, test_move_offset);
KUNIT_EXPECT_EQ(test, 12, test_move_count);
- KUNIT_EXPECT_EQ(test, 786, test_move_addr);
+ KUNIT_EXPECT_EQ(test, 792, test_move_addr);
idx = 0;
list_for_each_entry(elem, &admin.rules, list) {
KUNIT_EXPECT_EQ(test, exp_addr[idx], elem->addr);
++idx;
}
- KUNIT_EXPECT_EQ(test, 768, admin.last_used_addr);
+ KUNIT_EXPECT_EQ(test, 780, admin.last_used_addr);
vcap_del_rule(&test_vctrl, &test_netdev, 500);
vcap_del_rule(&test_vctrl, &test_netdev, 400);
@@ -1774,7 +1801,7 @@ static void vcap_api_rule_remove_in_middle_test(struct kunit *test)
KUNIT_EXPECT_EQ(test, 768, test_move_addr);
KUNIT_EXPECT_EQ(test, -6, test_move_offset);
KUNIT_EXPECT_EQ(test, 6, test_move_count);
- KUNIT_EXPECT_EQ(test, 768, test_init_start);
+ KUNIT_EXPECT_EQ(test, 774, test_init_start);
KUNIT_EXPECT_EQ(test, 6, test_init_count);
KUNIT_EXPECT_EQ(test, 774, admin.last_used_addr);
@@ -1784,8 +1811,8 @@ static void vcap_api_rule_remove_in_middle_test(struct kunit *test)
KUNIT_EXPECT_EQ(test, 774, test_move_addr);
KUNIT_EXPECT_EQ(test, -4, test_move_offset);
KUNIT_EXPECT_EQ(test, 2, test_move_count);
- KUNIT_EXPECT_EQ(test, 774, test_init_start);
- KUNIT_EXPECT_EQ(test, 4, test_init_count);
+ KUNIT_EXPECT_EQ(test, 777, test_init_start);
+ KUNIT_EXPECT_EQ(test, 3, test_init_count);
KUNIT_EXPECT_EQ(test, 778, admin.last_used_addr);
test_init_rule_deletion();
@@ -1794,8 +1821,8 @@ static void vcap_api_rule_remove_in_middle_test(struct kunit *test)
KUNIT_EXPECT_EQ(test, 778, test_move_addr);
KUNIT_EXPECT_EQ(test, -20, test_move_offset);
KUNIT_EXPECT_EQ(test, 2, test_move_count);
- KUNIT_EXPECT_EQ(test, 778, test_init_start);
- KUNIT_EXPECT_EQ(test, 20, test_init_count);
+ KUNIT_EXPECT_EQ(test, 780, test_init_start);
+ KUNIT_EXPECT_EQ(test, 12, test_init_count);
KUNIT_EXPECT_EQ(test, 798, admin.last_used_addr);
test_init_rule_deletion();
@@ -1855,11 +1882,11 @@ static void vcap_api_rule_remove_in_front_test(struct kunit *test)
ret = vcap_del_rule(&test_vctrl, &test_netdev, 400);
KUNIT_EXPECT_EQ(test, 0, ret);
KUNIT_EXPECT_EQ(test, 786, test_move_addr);
- KUNIT_EXPECT_EQ(test, -8, test_move_offset);
+ KUNIT_EXPECT_EQ(test, -6, test_move_offset);
KUNIT_EXPECT_EQ(test, 6, test_move_count);
- KUNIT_EXPECT_EQ(test, 786, test_init_start);
- KUNIT_EXPECT_EQ(test, 8, test_init_count);
- KUNIT_EXPECT_EQ(test, 794, admin.last_used_addr);
+ KUNIT_EXPECT_EQ(test, 792, test_init_start);
+ KUNIT_EXPECT_EQ(test, 6, test_init_count);
+ KUNIT_EXPECT_EQ(test, 792, admin.last_used_addr);
vcap_del_rule(&test_vctrl, &test_netdev, 200);
vcap_del_rule(&test_vctrl, &test_netdev, 300);
--
2.52.0
^ permalink raw reply related
* [PATCH net-next 2/9] net: microchip: vcap: add lpm vcap to autogen vcap api
From: Jens Emil Schulz Østergaard @ 2026-06-12 12:37 UTC (permalink / raw)
To: Horatiu Vultur, UNGLinuxDriver, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Daniel Machon,
Steen Hegelund, Kees Cook, Gustavo A. R. Silva
Cc: netdev, linux-kernel, linux-arm-kernel, linux-hardening,
Jens Emil Schulz Østergaard
In-Reply-To: <20260612-sparx5_l3_routing-v1-0-fc3c10160f49@microchip.com>
Add autogenerated VCAP rule encoding metadata, and VCAP parameters for
the LPM VCAP used for L3 routing.
Reviewed-by: Daniel Machon <daniel.machon@microchip.com>
Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com>
Signed-off-by: Jens Emil Schulz Østergaard <jensemil.schulzostergaard@microchip.com>
---
.../microchip/sparx5/lan969x/lan969x_vcap_ag_api.c | 373 ++++++++++++++++++++-
.../ethernet/microchip/sparx5/sparx5_vcap_ag_api.c | 373 ++++++++++++++++++++-
.../ethernet/microchip/sparx5/sparx5_vcap_ag_api.h | 6 +-
drivers/net/ethernet/microchip/vcap/vcap_ag_api.h | 94 +++++-
.../net/ethernet/microchip/vcap/vcap_model_kunit.c | 6 +-
5 files changed, 832 insertions(+), 20 deletions(-)
diff --git a/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x_vcap_ag_api.c b/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x_vcap_ag_api.c
index 7acc5bcf337a..e623b1dbe9cb 100644
--- a/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x_vcap_ag_api.c
+++ b/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x_vcap_ag_api.c
@@ -1,10 +1,10 @@
// SPDX-License-Identifier: BSD-3-Clause
-/* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries.
+/* Copyright (C) 2026 Microchip Technology Inc. and its subsidiaries.
* Microchip VCAP API
*/
-/* This file is autogenerated by cml-utils 2024-10-07 11:10:56 +0200.
- * Commit ID: b5ddc8e244eb2481a9524f1ddc630a8b41e7c391
+/* This file is autogenerated by cml-utils 2026-04-28 13:55:50 +0200.
+ * Commit ID: cd2494df16a1d3b14f650f720f6a8126b88b553a
*/
#include <linux/types.h>
@@ -1380,6 +1380,83 @@ static const struct vcap_field es0_isdx_keyfield[] = {
},
};
+static const struct vcap_field lpm_sgl_ip4_keyfield[] = {
+ [VCAP_KF_DST_FLAG] = {
+ .type = VCAP_FIELD_BIT,
+ .offset = 0,
+ .width = 1,
+ },
+ [VCAP_KF_AFFIX] = {
+ .type = VCAP_FIELD_U32,
+ .offset = 1,
+ .width = 10,
+ },
+ [VCAP_KF_IP4_XIP] = {
+ .type = VCAP_FIELD_U32,
+ .offset = 11,
+ .width = 32,
+ },
+};
+
+static const struct vcap_field lpm_dbl_ip4_keyfield[] = {
+ [VCAP_KF_TYPE] = {
+ .type = VCAP_FIELD_BIT,
+ .offset = 0,
+ .width = 1,
+ },
+ [VCAP_KF_AFFIX] = {
+ .type = VCAP_FIELD_U32,
+ .offset = 1,
+ .width = 10,
+ },
+ [VCAP_KF_IP4_SIP] = {
+ .type = VCAP_FIELD_U32,
+ .offset = 11,
+ .width = 32,
+ },
+ [VCAP_KF_IP4_DIP] = {
+ .type = VCAP_FIELD_U32,
+ .offset = 43,
+ .width = 32,
+ },
+};
+
+static const struct vcap_field lpm_sgl_ip6_keyfield[] = {
+ [VCAP_KF_DST_FLAG] = {
+ .type = VCAP_FIELD_BIT,
+ .offset = 0,
+ .width = 1,
+ },
+ [VCAP_KF_AFFIX] = {
+ .type = VCAP_FIELD_U32,
+ .offset = 1,
+ .width = 10,
+ },
+ [VCAP_KF_IP6_XIP] = {
+ .type = VCAP_FIELD_U128,
+ .offset = 11,
+ .width = 128,
+ },
+};
+
+static const struct vcap_field lpm_dbl_ip6_keyfield[] = {
+ [VCAP_KF_AFFIX] = {
+ .type = VCAP_FIELD_U32,
+ .offset = 0,
+ .width = 10,
+ },
+ [VCAP_KF_IP6_SIP] = {
+ .type = VCAP_FIELD_U128,
+ .offset = 10,
+ .width = 128,
+ },
+ [VCAP_KF_IP6_DIP] = {
+ .type = VCAP_FIELD_U128,
+ .offset = 138,
+ .width = 128,
+ },
+};
+
static const struct vcap_field es2_mac_etype_keyfield[] = {
[VCAP_KF_TYPE] = {
.type = VCAP_FIELD_U32,
@@ -2338,6 +2415,29 @@ static const struct vcap_set es0_keyfield_set[] = {
},
};
+static const struct vcap_set lpm_keyfield_set[] = {
+ [VCAP_KFS_SGL_IP4] = {
+ .type_id = -1,
+ .sw_per_item = 1,
+ .sw_cnt = 12,
+ },
+ [VCAP_KFS_DBL_IP4] = {
+ .type_id = 0,
+ .sw_per_item = 2,
+ .sw_cnt = 6,
+ },
+ [VCAP_KFS_SGL_IP6] = {
+ .type_id = -1,
+ .sw_per_item = 3,
+ .sw_cnt = 4,
+ },
+ [VCAP_KFS_DBL_IP6] = {
+ .type_id = -1,
+ .sw_per_item = 6,
+ .sw_cnt = 2,
+ },
+};
+
static const struct vcap_set es2_keyfield_set[] = {
[VCAP_KFS_MAC_ETYPE] = {
.type_id = 0,
@@ -2390,6 +2490,13 @@ static const struct vcap_field *es0_keyfield_set_map[] = {
[VCAP_KFS_ISDX] = es0_isdx_keyfield,
};
+static const struct vcap_field *lpm_keyfield_set_map[] = {
+ [VCAP_KFS_SGL_IP4] = lpm_sgl_ip4_keyfield,
+ [VCAP_KFS_DBL_IP4] = lpm_dbl_ip4_keyfield,
+ [VCAP_KFS_SGL_IP6] = lpm_sgl_ip6_keyfield,
+ [VCAP_KFS_DBL_IP6] = lpm_dbl_ip6_keyfield,
+};
+
static const struct vcap_field *es2_keyfield_set_map[] = {
[VCAP_KFS_MAC_ETYPE] = es2_mac_etype_keyfield,
[VCAP_KFS_ARP] = es2_arp_keyfield,
@@ -2418,6 +2525,13 @@ static int es0_keyfield_set_map_size[] = {
[VCAP_KFS_ISDX] = ARRAY_SIZE(es0_isdx_keyfield),
};
+static int lpm_keyfield_set_map_size[] = {
+ [VCAP_KFS_SGL_IP4] = ARRAY_SIZE(lpm_sgl_ip4_keyfield),
+ [VCAP_KFS_DBL_IP4] = ARRAY_SIZE(lpm_dbl_ip4_keyfield),
+ [VCAP_KFS_SGL_IP6] = ARRAY_SIZE(lpm_sgl_ip6_keyfield),
+ [VCAP_KFS_DBL_IP6] = ARRAY_SIZE(lpm_dbl_ip6_keyfield),
+};
+
static int es2_keyfield_set_map_size[] = {
[VCAP_KFS_MAC_ETYPE] = ARRAY_SIZE(es2_mac_etype_keyfield),
[VCAP_KFS_ARP] = ARRAY_SIZE(es2_arp_keyfield),
@@ -2993,6 +3107,92 @@ static const struct vcap_field es0_es0_actionfield[] = {
},
};
+static const struct vcap_field lpm_arp_ptr_actionfield[] = {
+ [VCAP_AF_TYPE] = {
+ .type = VCAP_FIELD_U32,
+ .offset = 0,
+ .width = 2,
+ },
+ [VCAP_AF_ARP_PTR] = {
+ .type = VCAP_FIELD_U32,
+ .offset = 2,
+ .width = 10,
+ },
+ [VCAP_AF_ARP_PTR_REMAP_ENA] = {
+ .type = VCAP_FIELD_BIT,
+ .offset = 12,
+ .width = 1,
+ },
+ [VCAP_AF_ECMP_CNT] = {
+ .type = VCAP_FIELD_U32,
+ .offset = 13,
+ .width = 4,
+ },
+ [VCAP_AF_RGID] = {
+ .type = VCAP_FIELD_U32,
+ .offset = 17,
+ .width = 3,
+ },
+};
+
+static const struct vcap_field lpm_arp_entry_actionfield[] = {
+ [VCAP_AF_TYPE] = {
+ .type = VCAP_FIELD_U32,
+ .offset = 0,
+ .width = 2,
+ },
+ [VCAP_AF_MAC_MSB] = {
+ .type = VCAP_FIELD_U32,
+ .offset = 2,
+ .width = 16,
+ },
+ [VCAP_AF_MAC_LSB] = {
+ .type = VCAP_FIELD_U32,
+ .offset = 18,
+ .width = 32,
+ },
+ [VCAP_AF_ARP_VMID] = {
+ .type = VCAP_FIELD_U32,
+ .offset = 50,
+ .width = 7,
+ },
+ [VCAP_AF_ZERO_DMAC_CPU_QU] = {
+ .type = VCAP_FIELD_U32,
+ .offset = 57,
+ .width = 3,
+ },
+ [VCAP_AF_SIP_RPF_ENA] = {
+ .type = VCAP_FIELD_BIT,
+ .offset = 60,
+ .width = 1,
+ },
+ [VCAP_AF_SECUR_MATCH_VMID_ENA] = {
+ .type = VCAP_FIELD_BIT,
+ .offset = 61,
+ .width = 1,
+ },
+ [VCAP_AF_SECUR_MATCH_MAC_ENA] = {
+ .type = VCAP_FIELD_BIT,
+ .offset = 62,
+ .width = 1,
+ },
+ [VCAP_AF_ARP_ENA] = {
+ .type = VCAP_FIELD_BIT,
+ .offset = 63,
+ .width = 1,
+ },
+ [VCAP_AF_ENCAP_ID] = {
+ .type = VCAP_FIELD_U32,
+ .offset = 64,
+ .width = 8,
+ },
+ [VCAP_AF_RSDX] = {
+ .type = VCAP_FIELD_U32,
+ .offset = 72,
+ .width = 10,
+ },
+};
+
static const struct vcap_field es2_base_type_actionfield[] = {
[VCAP_AF_HIT_ME_ONCE] = {
.type = VCAP_FIELD_BIT,
@@ -3101,6 +3301,19 @@ static const struct vcap_set es0_actionfield_set[] = {
},
};
+static const struct vcap_set lpm_actionfield_set[] = {
+ [VCAP_AFS_ARP_PTR] = {
+ .type_id = 0,
+ .sw_per_item = 1,
+ .sw_cnt = 12,
+ },
+ [VCAP_AFS_ARP_ENTRY] = {
+ .type_id = 2,
+ .sw_per_item = 1,
+ .sw_cnt = 12,
+ },
+};
+
static const struct vcap_set es2_actionfield_set[] = {
[VCAP_AFS_BASE_TYPE] = {
.type_id = -1,
@@ -3124,6 +3337,11 @@ static const struct vcap_field *es0_actionfield_set_map[] = {
[VCAP_AFS_ES0] = es0_es0_actionfield,
};
+static const struct vcap_field *lpm_actionfield_set_map[] = {
+ [VCAP_AFS_ARP_PTR] = lpm_arp_ptr_actionfield,
+ [VCAP_AFS_ARP_ENTRY] = lpm_arp_entry_actionfield,
+};
+
static const struct vcap_field *es2_actionfield_set_map[] = {
[VCAP_AFS_BASE_TYPE] = es2_base_type_actionfield,
};
@@ -3143,6 +3361,11 @@ static int es0_actionfield_set_map_size[] = {
[VCAP_AFS_ES0] = ARRAY_SIZE(es0_es0_actionfield),
};
+static int lpm_actionfield_set_map_size[] = {
+ [VCAP_AFS_ARP_PTR] = ARRAY_SIZE(lpm_arp_ptr_actionfield),
+ [VCAP_AFS_ARP_ENTRY] = ARRAY_SIZE(lpm_arp_entry_actionfield),
+};
+
static int es2_actionfield_set_map_size[] = {
[VCAP_AFS_BASE_TYPE] = ARRAY_SIZE(es2_base_type_actionfield),
};
@@ -3308,6 +3531,82 @@ static const struct vcap_typegroup es0_x1_keyfield_set_typegroups[] = {
{}
};
+static const struct vcap_typegroup lpm_x6_keyfield_set_typegroups[] = {
+ {
+ .offset = 0,
+ .width = 4,
+ .value = 8,
+ },
+ {
+ .offset = 52,
+ .width = 1,
+ .value = 0,
+ },
+ {
+ .offset = 104,
+ .width = 2,
+ .value = 0,
+ },
+ {
+ .offset = 156,
+ .width = 3,
+ .value = 0,
+ },
+ {
+ .offset = 208,
+ .width = 2,
+ .value = 0,
+ },
+ {
+ .offset = 260,
+ .width = 1,
+ .value = 0,
+ },
+ {}
+};
+
+static const struct vcap_typegroup lpm_x3_keyfield_set_typegroups[] = {
+ {
+ .offset = 0,
+ .width = 3,
+ .value = 4,
+ },
+ {
+ .offset = 52,
+ .width = 2,
+ .value = 0,
+ },
+ {
+ .offset = 104,
+ .width = 2,
+ .value = 0,
+ },
+ {}
+};
+
+static const struct vcap_typegroup lpm_x2_keyfield_set_typegroups[] = {
+ {
+ .offset = 0,
+ .width = 2,
+ .value = 2,
+ },
+ {
+ .offset = 52,
+ .width = 1,
+ .value = 0,
+ },
+ {}
+};
+
+static const struct vcap_typegroup lpm_x1_keyfield_set_typegroups[] = {
+ {
+ .offset = 0,
+ .width = 1,
+ .value = 1,
+ },
+ {}
+};
+
static const struct vcap_typegroup es2_x12_keyfield_set_typegroups[] = {
{
.offset = 0,
@@ -3376,6 +3675,14 @@ static const struct vcap_typegroup *es0_keyfield_set_typegroups[] = {
[2] = NULL,
};
+static const struct vcap_typegroup *lpm_keyfield_set_typegroups[] = {
+ [6] = lpm_x6_keyfield_set_typegroups,
+ [3] = lpm_x3_keyfield_set_typegroups,
+ [2] = lpm_x2_keyfield_set_typegroups,
+ [1] = lpm_x1_keyfield_set_typegroups,
+ [13] = NULL,
+};
+
static const struct vcap_typegroup *es2_keyfield_set_typegroups[] = {
[12] = es2_x12_keyfield_set_typegroups,
[6] = es2_x6_keyfield_set_typegroups,
@@ -3453,6 +3760,10 @@ static const struct vcap_typegroup es0_x1_actionfield_set_typegroups[] = {
{}
};
+static const struct vcap_typegroup lpm_x1_actionfield_set_typegroups[] = {
+ {}
+};
+
static const struct vcap_typegroup es2_x3_actionfield_set_typegroups[] = {
{
.offset = 0,
@@ -3494,6 +3805,11 @@ static const struct vcap_typegroup *es0_actionfield_set_typegroups[] = {
[2] = NULL,
};
+static const struct vcap_typegroup *lpm_actionfield_set_typegroups[] = {
+ [1] = lpm_x1_actionfield_set_typegroups,
+ [13] = NULL,
+};
+
static const struct vcap_typegroup *es2_actionfield_set_typegroups[] = {
[3] = es2_x3_actionfield_set_typegroups,
[1] = es2_x1_actionfield_set_typegroups,
@@ -3504,6 +3820,8 @@ static const struct vcap_typegroup *es2_actionfield_set_typegroups[] = {
static const char * const vcap_keyfield_set_names[] = {
[VCAP_KFS_NO_VALUE] = "(None)",
[VCAP_KFS_ARP] = "VCAP_KFS_ARP",
+ [VCAP_KFS_DBL_IP4] = "VCAP_KFS_DBL_IP4",
+ [VCAP_KFS_DBL_IP6] = "VCAP_KFS_DBL_IP6",
[VCAP_KFS_ETAG] = "VCAP_KFS_ETAG",
[VCAP_KFS_IP4_OTHER] = "VCAP_KFS_IP4_OTHER",
[VCAP_KFS_IP4_TCP_UDP] = "VCAP_KFS_IP4_TCP_UDP",
@@ -3522,6 +3840,8 @@ static const char * const vcap_keyfield_set_names[] = {
[VCAP_KFS_NORMAL_7TUPLE] = "VCAP_KFS_NORMAL_7TUPLE",
[VCAP_KFS_OAM] = "VCAP_KFS_OAM",
[VCAP_KFS_PURE_5TUPLE_IP4] = "VCAP_KFS_PURE_5TUPLE_IP4",
+ [VCAP_KFS_SGL_IP4] = "VCAP_KFS_SGL_IP4",
+ [VCAP_KFS_SGL_IP6] = "VCAP_KFS_SGL_IP6",
[VCAP_KFS_SMAC_SIP4] = "VCAP_KFS_SMAC_SIP4",
[VCAP_KFS_SMAC_SIP6] = "VCAP_KFS_SMAC_SIP6",
};
@@ -3529,6 +3849,8 @@ static const char * const vcap_keyfield_set_names[] = {
/* Actionfieldset names */
static const char * const vcap_actionfield_set_names[] = {
[VCAP_AFS_NO_VALUE] = "(None)",
+ [VCAP_AFS_ARP_ENTRY] = "VCAP_AFS_ARP_ENTRY",
+ [VCAP_AFS_ARP_PTR] = "VCAP_AFS_ARP_PTR",
[VCAP_AFS_BASE_TYPE] = "VCAP_AFS_BASE_TYPE",
[VCAP_AFS_CLASSIFICATION] = "VCAP_AFS_CLASSIFICATION",
[VCAP_AFS_CLASS_REDUCED] = "VCAP_AFS_CLASS_REDUCED",
@@ -3565,6 +3887,7 @@ static const char * const vcap_keyfield_names[] = {
[VCAP_KF_8021Q_VLAN_TAGGED_IS] = "8021Q_VLAN_TAGGED_IS",
[VCAP_KF_8021Q_VLAN_TAGS] = "8021Q_VLAN_TAGS",
[VCAP_KF_ACL_GRP_ID] = "ACL_GRP_ID",
+ [VCAP_KF_AFFIX] = "AFFIX",
[VCAP_KF_ARP_ADDR_SPACE_OK_IS] = "ARP_ADDR_SPACE_OK_IS",
[VCAP_KF_ARP_LEN_OK_IS] = "ARP_LEN_OK_IS",
[VCAP_KF_ARP_OPCODE] = "ARP_OPCODE",
@@ -3573,6 +3896,7 @@ static const char * const vcap_keyfield_names[] = {
[VCAP_KF_ARP_SENDER_MATCH_IS] = "ARP_SENDER_MATCH_IS",
[VCAP_KF_ARP_TGT_MATCH_IS] = "ARP_TGT_MATCH_IS",
[VCAP_KF_COSID_CLS] = "COSID_CLS",
+ [VCAP_KF_DST_FLAG] = "DST_FLAG",
[VCAP_KF_ES0_ISDX_KEY_ENA] = "ES0_ISDX_KEY_ENA",
[VCAP_KF_ETYPE] = "ETYPE",
[VCAP_KF_ETYPE_LEN_IS] = "ETYPE_LEN_IS",
@@ -3586,7 +3910,13 @@ static const char * const vcap_keyfield_names[] = {
[VCAP_KF_IF_IGR_PORT_MASK_RNG] = "IF_IGR_PORT_MASK_RNG",
[VCAP_KF_IF_IGR_PORT_MASK_SEL] = "IF_IGR_PORT_MASK_SEL",
[VCAP_KF_IF_IGR_PORT_SEL] = "IF_IGR_PORT_SEL",
+ [VCAP_KF_IP4_DIP] = "IP4_DIP",
[VCAP_KF_IP4_IS] = "IP4_IS",
+ [VCAP_KF_IP4_SIP] = "IP4_SIP",
+ [VCAP_KF_IP4_XIP] = "IP4_XIP",
+ [VCAP_KF_IP6_DIP] = "IP6_DIP",
+ [VCAP_KF_IP6_SIP] = "IP6_SIP",
+ [VCAP_KF_IP6_XIP] = "IP6_XIP",
[VCAP_KF_IP_MC_IS] = "IP_MC_IS",
[VCAP_KF_IP_PAYLOAD_5TUPLE] = "IP_PAYLOAD_5TUPLE",
[VCAP_KF_IP_SNAP_IS] = "IP_SNAP_IS",
@@ -3659,6 +3989,10 @@ static const char * const vcap_keyfield_names[] = {
static const char * const vcap_actionfield_names[] = {
[VCAP_AF_NO_VALUE] = "(None)",
[VCAP_AF_ACL_ID] = "ACL_ID",
+ [VCAP_AF_ARP_ENA] = "ARP_ENA",
+ [VCAP_AF_ARP_PTR] = "ARP_PTR",
+ [VCAP_AF_ARP_PTR_REMAP_ENA] = "ARP_PTR_REMAP_ENA",
+ [VCAP_AF_ARP_VMID] = "ARP_VMID",
[VCAP_AF_CLS_VID_SEL] = "CLS_VID_SEL",
[VCAP_AF_CNT_ID] = "CNT_ID",
[VCAP_AF_COPY_PORT_NUM] = "COPY_PORT_NUM",
@@ -3676,6 +4010,8 @@ static const char * const vcap_actionfield_names[] = {
[VCAP_AF_DSCP_ENA] = "DSCP_ENA",
[VCAP_AF_DSCP_SEL] = "DSCP_SEL",
[VCAP_AF_DSCP_VAL] = "DSCP_VAL",
+ [VCAP_AF_ECMP_CNT] = "ECMP_CNT",
+ [VCAP_AF_ENCAP_ID] = "ENCAP_ID",
[VCAP_AF_ES2_REW_CMD] = "ES2_REW_CMD",
[VCAP_AF_ESDX] = "ESDX",
[VCAP_AF_FWD_KILL_ENA] = "FWD_KILL_ENA",
@@ -3690,6 +4026,8 @@ static const char * const vcap_actionfield_names[] = {
[VCAP_AF_ISDX_VAL] = "ISDX_VAL",
[VCAP_AF_LOOP_ENA] = "LOOP_ENA",
[VCAP_AF_LRN_DIS] = "LRN_DIS",
+ [VCAP_AF_MAC_LSB] = "MAC_LSB",
+ [VCAP_AF_MAC_MSB] = "MAC_MSB",
[VCAP_AF_MAP_IDX] = "MAP_IDX",
[VCAP_AF_MAP_KEY] = "MAP_KEY",
[VCAP_AF_MAP_LOOKUP_SEL] = "MAP_LOOKUP_SEL",
@@ -3723,7 +4061,12 @@ static const char * const vcap_actionfield_names[] = {
[VCAP_AF_QOS_ENA] = "QOS_ENA",
[VCAP_AF_QOS_VAL] = "QOS_VAL",
[VCAP_AF_REW_OP] = "REW_OP",
+ [VCAP_AF_RGID] = "RGID",
+ [VCAP_AF_RSDX] = "RSDX",
[VCAP_AF_RT_DIS] = "RT_DIS",
+ [VCAP_AF_SECUR_MATCH_MAC_ENA] = "SECUR_MATCH_MAC_ENA",
+ [VCAP_AF_SECUR_MATCH_VMID_ENA] = "SECUR_MATCH_VMID_ENA",
+ [VCAP_AF_SIP_RPF_ENA] = "SIP_RPF_ENA",
[VCAP_AF_SWAP_MACS_ENA] = "SWAP_MACS_ENA",
[VCAP_AF_TAG_A_DEI_SEL] = "TAG_A_DEI_SEL",
[VCAP_AF_TAG_A_PCP_SEL] = "TAG_A_PCP_SEL",
@@ -3743,6 +4086,7 @@ static const char * const vcap_actionfield_names[] = {
[VCAP_AF_VID_B_VAL] = "VID_B_VAL",
[VCAP_AF_VID_C_VAL] = "VID_C_VAL",
[VCAP_AF_VID_VAL] = "VID_VAL",
+ [VCAP_AF_ZERO_DMAC_CPU_QU] = "ZERO_DMAC_CPU_QU",
};
/* VCAPs */
@@ -3810,6 +4154,27 @@ const struct vcap_info lan969x_vcaps[] = {
.keyfield_set_typegroups = es0_keyfield_set_typegroups,
.actionfield_set_typegroups = es0_actionfield_set_typegroups,
},
+ [VCAP_TYPE_LPM] = {
+ .name = "lpm",
+ .rows = 512,
+ .sw_count = 12,
+ .sw_width = 52,
+ .sticky_width = 1,
+ .act_width = 83,
+ .default_cnt = 0,
+ .require_cnt_dis = 0,
+ .version = 1,
+ .keyfield_set = lpm_keyfield_set,
+ .keyfield_set_size = ARRAY_SIZE(lpm_keyfield_set),
+ .actionfield_set = lpm_actionfield_set,
+ .actionfield_set_size = ARRAY_SIZE(lpm_actionfield_set),
+ .keyfield_set_map = lpm_keyfield_set_map,
+ .keyfield_set_map_size = lpm_keyfield_set_map_size,
+ .actionfield_set_map = lpm_actionfield_set_map,
+ .actionfield_set_map_size = lpm_actionfield_set_map_size,
+ .keyfield_set_typegroups = lpm_keyfield_set_typegroups,
+ .actionfield_set_typegroups = lpm_actionfield_set_typegroups,
+ },
[VCAP_TYPE_ES2] = {
.name = "es2",
.rows = 256,
@@ -3835,7 +4200,7 @@ const struct vcap_info lan969x_vcaps[] = {
const struct vcap_statistics lan969x_vcap_stats = {
.name = "lan969x",
- .count = 4,
+ .count = 5,
.keyfield_set_names = vcap_keyfield_set_names,
.actionfield_set_names = vcap_actionfield_set_names,
.keyfield_names = vcap_keyfield_names,
diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_vcap_ag_api.c b/drivers/net/ethernet/microchip/sparx5/sparx5_vcap_ag_api.c
index 556d6ea0acd1..7bc8b29757b1 100644
--- a/drivers/net/ethernet/microchip/sparx5/sparx5_vcap_ag_api.c
+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_vcap_ag_api.c
@@ -1,10 +1,10 @@
// SPDX-License-Identifier: BSD-3-Clause
-/* Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries.
+/* Copyright (C) 2026 Microchip Technology Inc. and its subsidiaries.
* Microchip VCAP API
*/
-/* This file is autogenerated by cml-utils 2023-02-10 11:15:56 +0100.
- * Commit ID: c30fb4bf0281cd4a7133bdab6682f9e43c872ada
+/* This file is autogenerated by cml-utils 2026-04-28 13:55:50 +0200.
+ * Commit ID: cd2494df16a1d3b14f650f720f6a8126b88b553a
*/
#include <linux/types.h>
@@ -1381,6 +1381,83 @@ static const struct vcap_field es0_isdx_keyfield[] = {
},
};
+static const struct vcap_field lpm_sgl_ip4_keyfield[] = {
+ [VCAP_KF_DST_FLAG] = {
+ .type = VCAP_FIELD_BIT,
+ .offset = 0,
+ .width = 1,
+ },
+ [VCAP_KF_AFFIX] = {
+ .type = VCAP_FIELD_U32,
+ .offset = 1,
+ .width = 10,
+ },
+ [VCAP_KF_IP4_XIP] = {
+ .type = VCAP_FIELD_U32,
+ .offset = 11,
+ .width = 32,
+ },
+};
+
+static const struct vcap_field lpm_dbl_ip4_keyfield[] = {
+ [VCAP_KF_TYPE] = {
+ .type = VCAP_FIELD_BIT,
+ .offset = 0,
+ .width = 1,
+ },
+ [VCAP_KF_AFFIX] = {
+ .type = VCAP_FIELD_U32,
+ .offset = 1,
+ .width = 10,
+ },
+ [VCAP_KF_IP4_SIP] = {
+ .type = VCAP_FIELD_U32,
+ .offset = 11,
+ .width = 32,
+ },
+ [VCAP_KF_IP4_DIP] = {
+ .type = VCAP_FIELD_U32,
+ .offset = 43,
+ .width = 32,
+ },
+};
+
+static const struct vcap_field lpm_sgl_ip6_keyfield[] = {
+ [VCAP_KF_DST_FLAG] = {
+ .type = VCAP_FIELD_BIT,
+ .offset = 0,
+ .width = 1,
+ },
+ [VCAP_KF_AFFIX] = {
+ .type = VCAP_FIELD_U32,
+ .offset = 1,
+ .width = 10,
+ },
+ [VCAP_KF_IP6_XIP] = {
+ .type = VCAP_FIELD_U128,
+ .offset = 11,
+ .width = 128,
+ },
+};
+
+static const struct vcap_field lpm_dbl_ip6_keyfield[] = {
+ [VCAP_KF_AFFIX] = {
+ .type = VCAP_FIELD_U32,
+ .offset = 0,
+ .width = 10,
+ },
+ [VCAP_KF_IP6_SIP] = {
+ .type = VCAP_FIELD_U128,
+ .offset = 10,
+ .width = 128,
+ },
+ [VCAP_KF_IP6_DIP] = {
+ .type = VCAP_FIELD_U128,
+ .offset = 138,
+ .width = 128,
+ },
+};
+
static const struct vcap_field es2_mac_etype_keyfield[] = {
[VCAP_KF_TYPE] = {
.type = VCAP_FIELD_U32,
@@ -2339,6 +2416,29 @@ static const struct vcap_set es0_keyfield_set[] = {
},
};
+static const struct vcap_set lpm_keyfield_set[] = {
+ [VCAP_KFS_SGL_IP4] = {
+ .type_id = -1,
+ .sw_per_item = 1,
+ .sw_cnt = 12,
+ },
+ [VCAP_KFS_DBL_IP4] = {
+ .type_id = 0,
+ .sw_per_item = 2,
+ .sw_cnt = 6,
+ },
+ [VCAP_KFS_SGL_IP6] = {
+ .type_id = -1,
+ .sw_per_item = 3,
+ .sw_cnt = 4,
+ },
+ [VCAP_KFS_DBL_IP6] = {
+ .type_id = -1,
+ .sw_per_item = 6,
+ .sw_cnt = 2,
+ },
+};
+
static const struct vcap_set es2_keyfield_set[] = {
[VCAP_KFS_MAC_ETYPE] = {
.type_id = 0,
@@ -2391,6 +2491,13 @@ static const struct vcap_field *es0_keyfield_set_map[] = {
[VCAP_KFS_ISDX] = es0_isdx_keyfield,
};
+static const struct vcap_field *lpm_keyfield_set_map[] = {
+ [VCAP_KFS_SGL_IP4] = lpm_sgl_ip4_keyfield,
+ [VCAP_KFS_DBL_IP4] = lpm_dbl_ip4_keyfield,
+ [VCAP_KFS_SGL_IP6] = lpm_sgl_ip6_keyfield,
+ [VCAP_KFS_DBL_IP6] = lpm_dbl_ip6_keyfield,
+};
+
static const struct vcap_field *es2_keyfield_set_map[] = {
[VCAP_KFS_MAC_ETYPE] = es2_mac_etype_keyfield,
[VCAP_KFS_ARP] = es2_arp_keyfield,
@@ -2419,6 +2526,13 @@ static int es0_keyfield_set_map_size[] = {
[VCAP_KFS_ISDX] = ARRAY_SIZE(es0_isdx_keyfield),
};
+static int lpm_keyfield_set_map_size[] = {
+ [VCAP_KFS_SGL_IP4] = ARRAY_SIZE(lpm_sgl_ip4_keyfield),
+ [VCAP_KFS_DBL_IP4] = ARRAY_SIZE(lpm_dbl_ip4_keyfield),
+ [VCAP_KFS_SGL_IP6] = ARRAY_SIZE(lpm_sgl_ip6_keyfield),
+ [VCAP_KFS_DBL_IP6] = ARRAY_SIZE(lpm_dbl_ip6_keyfield),
+};
+
static int es2_keyfield_set_map_size[] = {
[VCAP_KFS_MAC_ETYPE] = ARRAY_SIZE(es2_mac_etype_keyfield),
[VCAP_KFS_ARP] = ARRAY_SIZE(es2_arp_keyfield),
@@ -2994,6 +3108,92 @@ static const struct vcap_field es0_es0_actionfield[] = {
},
};
+static const struct vcap_field lpm_arp_ptr_actionfield[] = {
+ [VCAP_AF_TYPE] = {
+ .type = VCAP_FIELD_U32,
+ .offset = 0,
+ .width = 2,
+ },
+ [VCAP_AF_ARP_PTR] = {
+ .type = VCAP_FIELD_U32,
+ .offset = 2,
+ .width = 11,
+ },
+ [VCAP_AF_ARP_PTR_REMAP_ENA] = {
+ .type = VCAP_FIELD_BIT,
+ .offset = 13,
+ .width = 1,
+ },
+ [VCAP_AF_ECMP_CNT] = {
+ .type = VCAP_FIELD_U32,
+ .offset = 14,
+ .width = 4,
+ },
+ [VCAP_AF_RGID] = {
+ .type = VCAP_FIELD_U32,
+ .offset = 18,
+ .width = 3,
+ },
+};
+
+static const struct vcap_field lpm_arp_entry_actionfield[] = {
+ [VCAP_AF_TYPE] = {
+ .type = VCAP_FIELD_U32,
+ .offset = 0,
+ .width = 2,
+ },
+ [VCAP_AF_MAC_MSB] = {
+ .type = VCAP_FIELD_U32,
+ .offset = 2,
+ .width = 16,
+ },
+ [VCAP_AF_MAC_LSB] = {
+ .type = VCAP_FIELD_U32,
+ .offset = 18,
+ .width = 32,
+ },
+ [VCAP_AF_ARP_VMID] = {
+ .type = VCAP_FIELD_U32,
+ .offset = 50,
+ .width = 9,
+ },
+ [VCAP_AF_ZERO_DMAC_CPU_QU] = {
+ .type = VCAP_FIELD_U32,
+ .offset = 59,
+ .width = 3,
+ },
+ [VCAP_AF_SIP_RPF_ENA] = {
+ .type = VCAP_FIELD_BIT,
+ .offset = 62,
+ .width = 1,
+ },
+ [VCAP_AF_SECUR_MATCH_VMID_ENA] = {
+ .type = VCAP_FIELD_BIT,
+ .offset = 63,
+ .width = 1,
+ },
+ [VCAP_AF_SECUR_MATCH_MAC_ENA] = {
+ .type = VCAP_FIELD_BIT,
+ .offset = 64,
+ .width = 1,
+ },
+ [VCAP_AF_ARP_ENA] = {
+ .type = VCAP_FIELD_BIT,
+ .offset = 65,
+ .width = 1,
+ },
+ [VCAP_AF_ENCAP_ID] = {
+ .type = VCAP_FIELD_U32,
+ .offset = 66,
+ .width = 10,
+ },
+ [VCAP_AF_RSDX] = {
+ .type = VCAP_FIELD_U32,
+ .offset = 76,
+ .width = 12,
+ },
+};
+
static const struct vcap_field es2_base_type_actionfield[] = {
[VCAP_AF_HIT_ME_ONCE] = {
.type = VCAP_FIELD_BIT,
@@ -3102,6 +3302,19 @@ static const struct vcap_set es0_actionfield_set[] = {
},
};
+static const struct vcap_set lpm_actionfield_set[] = {
+ [VCAP_AFS_ARP_PTR] = {
+ .type_id = 0,
+ .sw_per_item = 1,
+ .sw_cnt = 12,
+ },
+ [VCAP_AFS_ARP_ENTRY] = {
+ .type_id = 2,
+ .sw_per_item = 1,
+ .sw_cnt = 12,
+ },
+};
+
static const struct vcap_set es2_actionfield_set[] = {
[VCAP_AFS_BASE_TYPE] = {
.type_id = -1,
@@ -3125,6 +3338,11 @@ static const struct vcap_field *es0_actionfield_set_map[] = {
[VCAP_AFS_ES0] = es0_es0_actionfield,
};
+static const struct vcap_field *lpm_actionfield_set_map[] = {
+ [VCAP_AFS_ARP_PTR] = lpm_arp_ptr_actionfield,
+ [VCAP_AFS_ARP_ENTRY] = lpm_arp_entry_actionfield,
+};
+
static const struct vcap_field *es2_actionfield_set_map[] = {
[VCAP_AFS_BASE_TYPE] = es2_base_type_actionfield,
};
@@ -3144,6 +3362,11 @@ static int es0_actionfield_set_map_size[] = {
[VCAP_AFS_ES0] = ARRAY_SIZE(es0_es0_actionfield),
};
+static int lpm_actionfield_set_map_size[] = {
+ [VCAP_AFS_ARP_PTR] = ARRAY_SIZE(lpm_arp_ptr_actionfield),
+ [VCAP_AFS_ARP_ENTRY] = ARRAY_SIZE(lpm_arp_entry_actionfield),
+};
+
static int es2_actionfield_set_map_size[] = {
[VCAP_AFS_BASE_TYPE] = ARRAY_SIZE(es2_base_type_actionfield),
};
@@ -3334,6 +3557,82 @@ static const struct vcap_typegroup es0_x1_keyfield_set_typegroups[] = {
{}
};
+static const struct vcap_typegroup lpm_x6_keyfield_set_typegroups[] = {
+ {
+ .offset = 0,
+ .width = 4,
+ .value = 8,
+ },
+ {
+ .offset = 52,
+ .width = 1,
+ .value = 0,
+ },
+ {
+ .offset = 104,
+ .width = 2,
+ .value = 0,
+ },
+ {
+ .offset = 156,
+ .width = 3,
+ .value = 0,
+ },
+ {
+ .offset = 208,
+ .width = 2,
+ .value = 0,
+ },
+ {
+ .offset = 260,
+ .width = 1,
+ .value = 0,
+ },
+ {}
+};
+
+static const struct vcap_typegroup lpm_x3_keyfield_set_typegroups[] = {
+ {
+ .offset = 0,
+ .width = 3,
+ .value = 4,
+ },
+ {
+ .offset = 52,
+ .width = 2,
+ .value = 0,
+ },
+ {
+ .offset = 104,
+ .width = 2,
+ .value = 0,
+ },
+ {}
+};
+
+static const struct vcap_typegroup lpm_x2_keyfield_set_typegroups[] = {
+ {
+ .offset = 0,
+ .width = 2,
+ .value = 2,
+ },
+ {
+ .offset = 52,
+ .width = 1,
+ .value = 0,
+ },
+ {}
+};
+
+static const struct vcap_typegroup lpm_x1_keyfield_set_typegroups[] = {
+ {
+ .offset = 0,
+ .width = 1,
+ .value = 1,
+ },
+ {}
+};
+
static const struct vcap_typegroup es2_x12_keyfield_set_typegroups[] = {
{
.offset = 0,
@@ -3407,6 +3706,14 @@ static const struct vcap_typegroup *es0_keyfield_set_typegroups[] = {
[2] = NULL,
};
+static const struct vcap_typegroup *lpm_keyfield_set_typegroups[] = {
+ [6] = lpm_x6_keyfield_set_typegroups,
+ [3] = lpm_x3_keyfield_set_typegroups,
+ [2] = lpm_x2_keyfield_set_typegroups,
+ [1] = lpm_x1_keyfield_set_typegroups,
+ [13] = NULL,
+};
+
static const struct vcap_typegroup *es2_keyfield_set_typegroups[] = {
[12] = es2_x12_keyfield_set_typegroups,
[6] = es2_x6_keyfield_set_typegroups,
@@ -3484,6 +3791,10 @@ static const struct vcap_typegroup es0_x1_actionfield_set_typegroups[] = {
{}
};
+static const struct vcap_typegroup lpm_x1_actionfield_set_typegroups[] = {
+ {}
+};
+
static const struct vcap_typegroup es2_x3_actionfield_set_typegroups[] = {
{
.offset = 0,
@@ -3525,6 +3836,11 @@ static const struct vcap_typegroup *es0_actionfield_set_typegroups[] = {
[2] = NULL,
};
+static const struct vcap_typegroup *lpm_actionfield_set_typegroups[] = {
+ [1] = lpm_x1_actionfield_set_typegroups,
+ [13] = NULL,
+};
+
static const struct vcap_typegroup *es2_actionfield_set_typegroups[] = {
[3] = es2_x3_actionfield_set_typegroups,
[1] = es2_x1_actionfield_set_typegroups,
@@ -3535,6 +3851,8 @@ static const struct vcap_typegroup *es2_actionfield_set_typegroups[] = {
static const char * const vcap_keyfield_set_names[] = {
[VCAP_KFS_NO_VALUE] = "(None)",
[VCAP_KFS_ARP] = "VCAP_KFS_ARP",
+ [VCAP_KFS_DBL_IP4] = "VCAP_KFS_DBL_IP4",
+ [VCAP_KFS_DBL_IP6] = "VCAP_KFS_DBL_IP6",
[VCAP_KFS_ETAG] = "VCAP_KFS_ETAG",
[VCAP_KFS_IP4_OTHER] = "VCAP_KFS_IP4_OTHER",
[VCAP_KFS_IP4_TCP_UDP] = "VCAP_KFS_IP4_TCP_UDP",
@@ -3553,6 +3871,8 @@ static const char * const vcap_keyfield_set_names[] = {
[VCAP_KFS_NORMAL_7TUPLE] = "VCAP_KFS_NORMAL_7TUPLE",
[VCAP_KFS_OAM] = "VCAP_KFS_OAM",
[VCAP_KFS_PURE_5TUPLE_IP4] = "VCAP_KFS_PURE_5TUPLE_IP4",
+ [VCAP_KFS_SGL_IP4] = "VCAP_KFS_SGL_IP4",
+ [VCAP_KFS_SGL_IP6] = "VCAP_KFS_SGL_IP6",
[VCAP_KFS_SMAC_SIP4] = "VCAP_KFS_SMAC_SIP4",
[VCAP_KFS_SMAC_SIP6] = "VCAP_KFS_SMAC_SIP6",
};
@@ -3560,6 +3880,8 @@ static const char * const vcap_keyfield_set_names[] = {
/* Actionfieldset names */
static const char * const vcap_actionfield_set_names[] = {
[VCAP_AFS_NO_VALUE] = "(None)",
+ [VCAP_AFS_ARP_ENTRY] = "VCAP_AFS_ARP_ENTRY",
+ [VCAP_AFS_ARP_PTR] = "VCAP_AFS_ARP_PTR",
[VCAP_AFS_BASE_TYPE] = "VCAP_AFS_BASE_TYPE",
[VCAP_AFS_CLASSIFICATION] = "VCAP_AFS_CLASSIFICATION",
[VCAP_AFS_CLASS_REDUCED] = "VCAP_AFS_CLASS_REDUCED",
@@ -3596,6 +3918,7 @@ static const char * const vcap_keyfield_names[] = {
[VCAP_KF_8021Q_VLAN_TAGGED_IS] = "8021Q_VLAN_TAGGED_IS",
[VCAP_KF_8021Q_VLAN_TAGS] = "8021Q_VLAN_TAGS",
[VCAP_KF_ACL_GRP_ID] = "ACL_GRP_ID",
+ [VCAP_KF_AFFIX] = "AFFIX",
[VCAP_KF_ARP_ADDR_SPACE_OK_IS] = "ARP_ADDR_SPACE_OK_IS",
[VCAP_KF_ARP_LEN_OK_IS] = "ARP_LEN_OK_IS",
[VCAP_KF_ARP_OPCODE] = "ARP_OPCODE",
@@ -3604,6 +3927,7 @@ static const char * const vcap_keyfield_names[] = {
[VCAP_KF_ARP_SENDER_MATCH_IS] = "ARP_SENDER_MATCH_IS",
[VCAP_KF_ARP_TGT_MATCH_IS] = "ARP_TGT_MATCH_IS",
[VCAP_KF_COSID_CLS] = "COSID_CLS",
+ [VCAP_KF_DST_FLAG] = "DST_FLAG",
[VCAP_KF_ES0_ISDX_KEY_ENA] = "ES0_ISDX_KEY_ENA",
[VCAP_KF_ETYPE] = "ETYPE",
[VCAP_KF_ETYPE_LEN_IS] = "ETYPE_LEN_IS",
@@ -3617,7 +3941,13 @@ static const char * const vcap_keyfield_names[] = {
[VCAP_KF_IF_IGR_PORT_MASK_RNG] = "IF_IGR_PORT_MASK_RNG",
[VCAP_KF_IF_IGR_PORT_MASK_SEL] = "IF_IGR_PORT_MASK_SEL",
[VCAP_KF_IF_IGR_PORT_SEL] = "IF_IGR_PORT_SEL",
+ [VCAP_KF_IP4_DIP] = "IP4_DIP",
[VCAP_KF_IP4_IS] = "IP4_IS",
+ [VCAP_KF_IP4_SIP] = "IP4_SIP",
+ [VCAP_KF_IP4_XIP] = "IP4_XIP",
+ [VCAP_KF_IP6_DIP] = "IP6_DIP",
+ [VCAP_KF_IP6_SIP] = "IP6_SIP",
+ [VCAP_KF_IP6_XIP] = "IP6_XIP",
[VCAP_KF_IP_MC_IS] = "IP_MC_IS",
[VCAP_KF_IP_PAYLOAD_5TUPLE] = "IP_PAYLOAD_5TUPLE",
[VCAP_KF_IP_SNAP_IS] = "IP_SNAP_IS",
@@ -3690,6 +4020,10 @@ static const char * const vcap_keyfield_names[] = {
static const char * const vcap_actionfield_names[] = {
[VCAP_AF_NO_VALUE] = "(None)",
[VCAP_AF_ACL_ID] = "ACL_ID",
+ [VCAP_AF_ARP_ENA] = "ARP_ENA",
+ [VCAP_AF_ARP_PTR] = "ARP_PTR",
+ [VCAP_AF_ARP_PTR_REMAP_ENA] = "ARP_PTR_REMAP_ENA",
+ [VCAP_AF_ARP_VMID] = "ARP_VMID",
[VCAP_AF_CLS_VID_SEL] = "CLS_VID_SEL",
[VCAP_AF_CNT_ID] = "CNT_ID",
[VCAP_AF_COPY_PORT_NUM] = "COPY_PORT_NUM",
@@ -3707,6 +4041,8 @@ static const char * const vcap_actionfield_names[] = {
[VCAP_AF_DSCP_ENA] = "DSCP_ENA",
[VCAP_AF_DSCP_SEL] = "DSCP_SEL",
[VCAP_AF_DSCP_VAL] = "DSCP_VAL",
+ [VCAP_AF_ECMP_CNT] = "ECMP_CNT",
+ [VCAP_AF_ENCAP_ID] = "ENCAP_ID",
[VCAP_AF_ES2_REW_CMD] = "ES2_REW_CMD",
[VCAP_AF_ESDX] = "ESDX",
[VCAP_AF_FWD_KILL_ENA] = "FWD_KILL_ENA",
@@ -3721,6 +4057,8 @@ static const char * const vcap_actionfield_names[] = {
[VCAP_AF_ISDX_VAL] = "ISDX_VAL",
[VCAP_AF_LOOP_ENA] = "LOOP_ENA",
[VCAP_AF_LRN_DIS] = "LRN_DIS",
+ [VCAP_AF_MAC_LSB] = "MAC_LSB",
+ [VCAP_AF_MAC_MSB] = "MAC_MSB",
[VCAP_AF_MAP_IDX] = "MAP_IDX",
[VCAP_AF_MAP_KEY] = "MAP_KEY",
[VCAP_AF_MAP_LOOKUP_SEL] = "MAP_LOOKUP_SEL",
@@ -3754,7 +4092,12 @@ static const char * const vcap_actionfield_names[] = {
[VCAP_AF_QOS_ENA] = "QOS_ENA",
[VCAP_AF_QOS_VAL] = "QOS_VAL",
[VCAP_AF_REW_OP] = "REW_OP",
+ [VCAP_AF_RGID] = "RGID",
+ [VCAP_AF_RSDX] = "RSDX",
[VCAP_AF_RT_DIS] = "RT_DIS",
+ [VCAP_AF_SECUR_MATCH_MAC_ENA] = "SECUR_MATCH_MAC_ENA",
+ [VCAP_AF_SECUR_MATCH_VMID_ENA] = "SECUR_MATCH_VMID_ENA",
+ [VCAP_AF_SIP_RPF_ENA] = "SIP_RPF_ENA",
[VCAP_AF_SWAP_MACS_ENA] = "SWAP_MACS_ENA",
[VCAP_AF_TAG_A_DEI_SEL] = "TAG_A_DEI_SEL",
[VCAP_AF_TAG_A_PCP_SEL] = "TAG_A_PCP_SEL",
@@ -3774,6 +4117,7 @@ static const char * const vcap_actionfield_names[] = {
[VCAP_AF_VID_B_VAL] = "VID_B_VAL",
[VCAP_AF_VID_C_VAL] = "VID_C_VAL",
[VCAP_AF_VID_VAL] = "VID_VAL",
+ [VCAP_AF_ZERO_DMAC_CPU_QU] = "ZERO_DMAC_CPU_QU",
};
/* VCAPs */
@@ -3841,6 +4185,27 @@ const struct vcap_info sparx5_vcaps[] = {
.keyfield_set_typegroups = es0_keyfield_set_typegroups,
.actionfield_set_typegroups = es0_actionfield_set_typegroups,
},
+ [VCAP_TYPE_LPM] = {
+ .name = "lpm",
+ .rows = 512,
+ .sw_count = 12,
+ .sw_width = 52,
+ .sticky_width = 1,
+ .act_width = 89,
+ .default_cnt = 0,
+ .require_cnt_dis = 0,
+ .version = 1,
+ .keyfield_set = lpm_keyfield_set,
+ .keyfield_set_size = ARRAY_SIZE(lpm_keyfield_set),
+ .actionfield_set = lpm_actionfield_set,
+ .actionfield_set_size = ARRAY_SIZE(lpm_actionfield_set),
+ .keyfield_set_map = lpm_keyfield_set_map,
+ .keyfield_set_map_size = lpm_keyfield_set_map_size,
+ .actionfield_set_map = lpm_actionfield_set_map,
+ .actionfield_set_map_size = lpm_actionfield_set_map_size,
+ .keyfield_set_typegroups = lpm_keyfield_set_typegroups,
+ .actionfield_set_typegroups = lpm_actionfield_set_typegroups,
+ },
[VCAP_TYPE_ES2] = {
.name = "es2",
.rows = 1024,
@@ -3866,7 +4231,7 @@ const struct vcap_info sparx5_vcaps[] = {
const struct vcap_statistics sparx5_vcap_stats = {
.name = "sparx5",
- .count = 4,
+ .count = 5,
.keyfield_set_names = vcap_keyfield_set_names,
.actionfield_set_names = vcap_actionfield_set_names,
.keyfield_names = vcap_keyfield_names,
diff --git a/drivers/net/ethernet/microchip/sparx5/sparx5_vcap_ag_api.h b/drivers/net/ethernet/microchip/sparx5/sparx5_vcap_ag_api.h
index e68f5639a40a..22bb416f433d 100644
--- a/drivers/net/ethernet/microchip/sparx5/sparx5_vcap_ag_api.h
+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_vcap_ag_api.h
@@ -1,10 +1,10 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries.
+/* Copyright (C) 2026 Microchip Technology Inc. and its subsidiaries.
* Microchip VCAP API
*/
-/* This file is autogenerated by cml-utils 2022-10-13 10:04:41 +0200.
- * Commit ID: fd7cafd175899f0672c73afb3a30fc872500ae86
+/* This file is autogenerated by cml-utils 2026-04-28 13:55:50 +0200.
+ * Commit ID: cd2494df16a1d3b14f650f720f6a8126b88b553a
*/
#ifndef __SPARX5_VCAP_AG_API_H__
diff --git a/drivers/net/ethernet/microchip/vcap/vcap_ag_api.h b/drivers/net/ethernet/microchip/vcap/vcap_ag_api.h
index 4735fad05708..487d56440936 100644
--- a/drivers/net/ethernet/microchip/vcap/vcap_ag_api.h
+++ b/drivers/net/ethernet/microchip/vcap/vcap_ag_api.h
@@ -1,10 +1,10 @@
/* SPDX-License-Identifier: BSD-3-Clause */
-/* Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries.
+/* Copyright (C) 2026 Microchip Technology Inc. and its subsidiaries.
* Microchip VCAP API
*/
-/* This file is autogenerated by cml-utils 2023-03-13 10:16:42 +0100.
- * Commit ID: 259f0efd6d6d91bfbf62858de153cc757b6bffa3 (dirty)
+/* This file is autogenerated by cml-utils 2026-04-28 13:55:50 +0200.
+ * Commit ID: cd2494df16a1d3b14f650f720f6a8126b88b553a
*/
#ifndef __VCAP_AG_API__
@@ -16,6 +16,7 @@ enum vcap_type {
VCAP_TYPE_IS0,
VCAP_TYPE_IS1,
VCAP_TYPE_IS2,
+ VCAP_TYPE_LPM,
VCAP_TYPE_MAX
};
@@ -26,6 +27,8 @@ enum vcap_keyfield_set {
VCAP_KFS_5TUPLE_IP6, /* lan966x is1 X4 */
VCAP_KFS_7TUPLE, /* lan966x is1 X4 */
VCAP_KFS_ARP, /* sparx5 is2 X6, sparx5 es2 X6, lan966x is2 X2 */
+ VCAP_KFS_DBL_IP4, /* sparx5 lpm X2 */
+ VCAP_KFS_DBL_IP6, /* sparx5 lpm X6 */
VCAP_KFS_DBL_VID, /* lan966x is1 X1 */
VCAP_KFS_DMAC_VID, /* lan966x is1 X1 */
VCAP_KFS_ETAG, /* sparx5 is0 X2 */
@@ -49,6 +52,8 @@ enum vcap_keyfield_set {
VCAP_KFS_OAM, /* lan966x is2 X2 */
VCAP_KFS_PURE_5TUPLE_IP4, /* sparx5 is0 X3 */
VCAP_KFS_RT, /* lan966x is1 X1 */
+ VCAP_KFS_SGL_IP4, /* sparx5 lpm X1 */
+ VCAP_KFS_SGL_IP6, /* sparx5 lpm X3 */
VCAP_KFS_SMAC_SIP4, /* lan966x is2 X1 */
VCAP_KFS_SMAC_SIP6, /* lan966x is2 X2 */
VCAP_KFS_VID, /* lan966x es0 X1 */
@@ -117,6 +122,10 @@ enum vcap_keyfield_set {
* tagged, 7: Triple tagged
* VCAP_KF_ACL_GRP_ID: W8, sparx5: es2
* Used in interface map table
+ * VCAP_KF_AFFIX: W10, sparx5: lpm
+ * LPM affix. Defaults to 0. Using the LPM affix, the VCAP LPM can be split into
+ * multiple logically separate routing tables, e.g. to support features such as
+ * VRF-lite.
* VCAP_KF_ARP_ADDR_SPACE_OK_IS: W1, sparx5: is2/es2, lan966x: is2
* Set if hardware address is Ethernet
* VCAP_KF_ARP_LEN_OK_IS: W1, sparx5: is2/es2, lan966x: is2
@@ -133,6 +142,9 @@ enum vcap_keyfield_set {
* Target Hardware Address = SMAC (RARP)
* VCAP_KF_COSID_CLS: W3, sparx5: es0/es2
* Class of service
+ * VCAP_KF_DST_FLAG: W1, sparx5: lpm
+ * 0: IP4_XIP/IP6_XIP is only to be used for SIP matching, 1: IP4_XIP/IP6_XIP is
+ * only to be used for DIP matching
* VCAP_KF_ES0_ISDX_KEY_ENA: W1, sparx5: es2
* The value taken from the IFH .FWD.ES0_ISDX_KEY_ENA
* VCAP_KF_ETYPE: W16, sparx5: is0/is2/es2, lan966x: is1/is2
@@ -167,8 +179,22 @@ enum vcap_keyfield_set {
* Mapping: 0: DEFAULT 1: LOOPBACK 2: MASQUERADE 3: CPU_VD
* VCAP_KF_IF_IGR_PORT_SEL: W1, sparx5: es2
* Selector for IF_IGR_PORT: physical port number or ERLEG
+ * VCAP_KF_IP4_DIP: W32, sparx5: lpm
+ * IPv4 destination address. Used for IPv4 MC routing.
* VCAP_KF_IP4_IS: W1, sparx5: is0/is2/es2, lan966x: is1/is2
* Set if frame has EtherType = 0x800 and IP version = 4
+ * VCAP_KF_IP4_SIP: W32, sparx5: lpm
+ * IPv4 source address. Used for IPv4 MC routing.
+ * VCAP_KF_IP4_XIP: W32, sparx5: lpm
+ * IPv4 address. Used for IPv4 UC routing as well as IPv4 Source/Destination
+ * Guard.
+ * VCAP_KF_IP6_DIP: W128, sparx5: lpm
+ * IPv6 destination address. Used for IPv6 MC routing.
+ * VCAP_KF_IP6_SIP: W128, sparx5: lpm
+ * IPv6 source address. Used for IPv6 MC routing.
+ * VCAP_KF_IP6_XIP: W128, sparx5: lpm
+ * IPv6 address. Used for IPv6 UC routing as well as IPv6 Source/Destination
+ * Guard.
* VCAP_KF_IP_MC_IS: W1, sparx5: is0, lan966x: is1
* Set if frame is IPv4 frame and frame's destination MAC address is an IPv4
* multicast address (0x01005E0 /25). Set if frame is IPv6 frame and frame's
@@ -352,8 +378,8 @@ enum vcap_keyfield_set {
* Set if frame is IPv4/IPv6 TCP or UDP frame (IP protocol/next header equals 6
* or 17)
* VCAP_KF_TYPE: sparx5 is0 W2, sparx5 is0 W1, sparx5 is2 W4, sparx5 is2 W2,
- * sparx5 es0 W1, sparx5 es2 W3, lan966x is1 W1, lan966x is1 W2, lan966x is2 W4,
- * lan966x is2 W2
+ * sparx5 es0 W1, sparx5 lpm W1, sparx5 es2 W3, lan966x is1 W1, lan966x is1 W2,
+ * lan966x is2 W4, lan966x is2 W2
* Keyset type id - set by the API
*/
@@ -387,6 +413,7 @@ enum vcap_key_field {
VCAP_KF_8021Q_VLAN_TAGGED_IS,
VCAP_KF_8021Q_VLAN_TAGS,
VCAP_KF_ACL_GRP_ID,
+ VCAP_KF_AFFIX,
VCAP_KF_ARP_ADDR_SPACE_OK_IS,
VCAP_KF_ARP_LEN_OK_IS,
VCAP_KF_ARP_OPCODE,
@@ -395,6 +422,7 @@ enum vcap_key_field {
VCAP_KF_ARP_SENDER_MATCH_IS,
VCAP_KF_ARP_TGT_MATCH_IS,
VCAP_KF_COSID_CLS,
+ VCAP_KF_DST_FLAG,
VCAP_KF_ES0_ISDX_KEY_ENA,
VCAP_KF_ETYPE,
VCAP_KF_ETYPE_LEN_IS,
@@ -408,7 +436,13 @@ enum vcap_key_field {
VCAP_KF_IF_IGR_PORT_MASK_RNG,
VCAP_KF_IF_IGR_PORT_MASK_SEL,
VCAP_KF_IF_IGR_PORT_SEL,
+ VCAP_KF_IP4_DIP,
VCAP_KF_IP4_IS,
+ VCAP_KF_IP4_SIP,
+ VCAP_KF_IP4_XIP,
+ VCAP_KF_IP6_DIP,
+ VCAP_KF_IP6_SIP,
+ VCAP_KF_IP6_XIP,
VCAP_KF_IP_MC_IS,
VCAP_KF_IP_PAYLOAD_5TUPLE,
VCAP_KF_IP_PAYLOAD_S1_IP6,
@@ -490,6 +524,8 @@ enum vcap_key_field {
/* Actionset names with origin information */
enum vcap_actionfield_set {
VCAP_AFS_NO_VALUE, /* initial value */
+ VCAP_AFS_ARP_ENTRY, /* sparx5 lpm X1 */
+ VCAP_AFS_ARP_PTR, /* sparx5 lpm X1 */
VCAP_AFS_BASE_TYPE, /* sparx5 is2 X3, sparx5 es2 X3, lan966x is2 X2 */
VCAP_AFS_CLASSIFICATION, /* sparx5 is0 X2 */
VCAP_AFS_CLASS_REDUCED, /* sparx5 is0 X1 */
@@ -506,6 +542,15 @@ enum vcap_actionfield_set {
* Logical ID for the entry. This ID is extracted together with the frame in the
* CPU extraction header. Only applicable to actions with CPU_COPY_ENA or
* HIT_ME_ONCE set.
+ * VCAP_AF_ARP_ENA: W1, sparx5: lpm
+ * Enable entry for address resolution usage.
+ * VCAP_AF_ARP_PTR: W11, sparx5: lpm
+ * Pointer to entry in ARP Table.
+ * VCAP_AF_ARP_PTR_REMAP_ENA: W1, sparx5: lpm
+ * If this bit is set, ARP_PTR is used to point to an entry in the ARP pointer
+ * remap table.
+ * VCAP_AF_ARP_VMID: W9, sparx5: lpm
+ * Routing lookup. Egress router leg (EVMID).
* VCAP_AF_CLS_VID_SEL: W3, sparx5: is0
* Controls the classified VID: 0: VID_NONE: No action. 1: VID_ADD: New VID =
* old VID + VID_VAL. 2: VID_REPLACE: New VID = VID_VAL. 3: VID_FIRST_TAG: New
@@ -562,6 +607,11 @@ enum vcap_actionfield_set {
* 7: Mapped using mapping table 3, otherwise use mapping table 2
* VCAP_AF_DSCP_VAL: W6, sparx5: is0/es0, lan966x: is1
* See DSCP_ENA.
+ * VCAP_AF_ECMP_CNT: W4, sparx5: lpm
+ * Number of equal cost, multiple paths routes to DIP.
+ * VCAP_AF_ENCAP_ID: W10, sparx5: lpm
+ * Index into REW:ENCAP_IP4 when encapsulating IP packet in IPv4. Disabled when
+ * set to 0.
* VCAP_AF_ES2_REW_CMD: W3, sparx5: es2
* Command forwarded to REW: 0: No action. 1: SWAP MAC addresses. 2: Do L2CP
* DMAC translation when entering or leaving a tunnel.
@@ -610,6 +660,12 @@ enum vcap_actionfield_set {
* 0: Forward based on PIPELINE_PT and FWD_SEL
* VCAP_AF_LRN_DIS: W1, sparx5: is2, lan966x: is2
* Setting this bit to 1 disables learning of frames hitting this action.
+ * VCAP_AF_MAC_LSB: W32, sparx5: lpm
+ * 32 least significant bits of MAC address. Used for ARP entry and/or
+ * (SMAC,SIP)/(DMAC,DIP) check.
+ * VCAP_AF_MAC_MSB: W16, sparx5: lpm
+ * 16 most significant bits of MAC address. Used for ARP entry and/or
+ * (SMAC,SIP)/(DMAC,DIP) check.
* VCAP_AF_MAP_IDX: W9, sparx5: is0
* Index for QoS mapping table lookup
* VCAP_AF_MAP_KEY: W3, sparx5: is0
@@ -715,9 +771,17 @@ enum vcap_actionfield_set {
* See QOS_ENA.
* VCAP_AF_REW_OP: W16, lan966x: is2
* Rewriter operation command.
+ * VCAP_AF_RGID: W3, sparx5: lpm
+ * Route Group ID. Used for SIP RPF check.
+ * VCAP_AF_RSDX: W12, sparx5: lpm
+ * Router Leg Service Index for ARP table entry.
* VCAP_AF_RT_DIS: W1, sparx5: is2
* If set, routing is disallowed. Only applies when IS_INNER_ACL is 0. See also
* IGR_ACL_ENA, EGR_ACL_ENA, and RLEG_STAT_IDX.
+ * VCAP_AF_SECUR_MATCH_MAC_ENA: W1, sparx5: lpm
+ * Enable Security MAC check.
+ * VCAP_AF_SECUR_MATCH_VMID_ENA: W1, sparx5: lpm
+ * Enable Security VMID check.
* VCAP_AF_SFID_ENA: W1, lan966x: is1
* If set, SFID_VAL is used to lookup ANA::SFID.
* VCAP_AF_SFID_VAL: W8, lan966x: is1
@@ -726,6 +790,8 @@ enum vcap_actionfield_set {
* If set, SGID_VAL is used to lookup ANA::SGID.
* VCAP_AF_SGID_VAL: W8, lan966x: is1
* Stream gate identifier.
+ * VCAP_AF_SIP_RPF_ENA: W1, sparx5: lpm
+ * Enable use for SIP RPF check.
* VCAP_AF_SWAP_MACS_ENA: W1, sparx5: es0
* This setting is only active when FWD_SEL = 1 or FWD_SEL = 2 and PIPELINE_ACT
* = LBK_ASM. 0: No action. 1: Swap MACs and clear bit 40 in new SMAC.
@@ -774,7 +840,7 @@ enum vcap_actionfield_set {
* VCAP_AF_TAG_C_VID_SEL: W2, sparx5: es0
* Selects VID for ES0 tag C. The resulting VID is termed C-TAG.VID. 0:
* Classified VID. 1: VID_C_VAL. 2: IFH.ENCAP.GVID. 3: Reserved.
- * VCAP_AF_TYPE: W1, sparx5: is0, lan966x: is1
+ * VCAP_AF_TYPE: sparx5 is0 W1, sparx5 lpm W2, lan966x is1 W1
* Actionset type id - Set by the API
* VCAP_AF_UNTAG_VID_ENA: W1, sparx5: es0
* Controls insertion of tag C. Untag or insert mode can be selected. See
@@ -798,12 +864,18 @@ enum vcap_actionfield_set {
* If set, use VLAN_POP_CNT as the number of VLAN tags to pop from the incoming
* frame. This number is used by the Rewriter. Otherwise, VLAN_POP_CNT from
* ANA:PORT:VLAN_CFG.VLAN_POP_CNT is used
+ * VCAP_AF_ZERO_DMAC_CPU_QU: W3, sparx5: lpm
+ * CPU queue used for CPU redirect if MAC address in ARP entry is all-zeros.
*/
/* Actionfield names */
enum vcap_action_field {
VCAP_AF_NO_VALUE, /* initial value */
VCAP_AF_ACL_ID,
+ VCAP_AF_ARP_ENA,
+ VCAP_AF_ARP_PTR,
+ VCAP_AF_ARP_PTR_REMAP_ENA,
+ VCAP_AF_ARP_VMID,
VCAP_AF_CLS_VID_SEL,
VCAP_AF_CNT_ID,
VCAP_AF_COPY_PORT_NUM,
@@ -823,6 +895,8 @@ enum vcap_action_field {
VCAP_AF_DSCP_ENA,
VCAP_AF_DSCP_SEL,
VCAP_AF_DSCP_VAL,
+ VCAP_AF_ECMP_CNT,
+ VCAP_AF_ENCAP_ID,
VCAP_AF_ES2_REW_CMD,
VCAP_AF_ESDX,
VCAP_AF_FWD_KILL_ENA,
@@ -839,6 +913,8 @@ enum vcap_action_field {
VCAP_AF_ISDX_VAL,
VCAP_AF_LOOP_ENA,
VCAP_AF_LRN_DIS,
+ VCAP_AF_MAC_LSB,
+ VCAP_AF_MAC_MSB,
VCAP_AF_MAP_IDX,
VCAP_AF_MAP_KEY,
VCAP_AF_MAP_LOOKUP_SEL,
@@ -874,11 +950,16 @@ enum vcap_action_field {
VCAP_AF_QOS_ENA,
VCAP_AF_QOS_VAL,
VCAP_AF_REW_OP,
+ VCAP_AF_RGID,
+ VCAP_AF_RSDX,
VCAP_AF_RT_DIS,
+ VCAP_AF_SECUR_MATCH_MAC_ENA,
+ VCAP_AF_SECUR_MATCH_VMID_ENA,
VCAP_AF_SFID_ENA,
VCAP_AF_SFID_VAL,
VCAP_AF_SGID_ENA,
VCAP_AF_SGID_VAL,
+ VCAP_AF_SIP_RPF_ENA,
VCAP_AF_SWAP_MACS_ENA,
VCAP_AF_TAG_A_DEI_SEL,
VCAP_AF_TAG_A_PCP_SEL,
@@ -901,6 +982,7 @@ enum vcap_action_field {
VCAP_AF_VID_VAL,
VCAP_AF_VLAN_POP_CNT,
VCAP_AF_VLAN_POP_CNT_ENA,
+ VCAP_AF_ZERO_DMAC_CPU_QU,
};
#endif /* __VCAP_AG_API__ */
diff --git a/drivers/net/ethernet/microchip/vcap/vcap_model_kunit.c b/drivers/net/ethernet/microchip/vcap/vcap_model_kunit.c
index 5dbfc0d0c369..75819b49e110 100644
--- a/drivers/net/ethernet/microchip/vcap/vcap_model_kunit.c
+++ b/drivers/net/ethernet/microchip/vcap/vcap_model_kunit.c
@@ -1,10 +1,10 @@
// SPDX-License-Identifier: BSD-3-Clause
-/* Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries.
+/* Copyright (C) 2026 Microchip Technology Inc. and its subsidiaries.
* Microchip VCAP test model interface for kunit testing
*/
-/* This file is autogenerated by cml-utils 2023-02-10 11:16:00 +0100.
- * Commit ID: c30fb4bf0281cd4a7133bdab6682f9e43c872ada
+/* This file is autogenerated by cml-utils 2026-04-28 13:55:50 +0200.
+ * Commit ID: cd2494df16a1d3b14f650f720f6a8126b88b553a
*/
#include <linux/types.h>
--
2.52.0
^ permalink raw reply related
* [PATCH net-next 3/9] net: microchip: vcap: make vcap actionset decoding type_id aware
From: Jens Emil Schulz Østergaard @ 2026-06-12 12:37 UTC (permalink / raw)
To: Horatiu Vultur, UNGLinuxDriver, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Daniel Machon,
Steen Hegelund, Kees Cook, Gustavo A. R. Silva
Cc: netdev, linux-kernel, linux-arm-kernel, linux-hardening,
Jens Emil Schulz Østergaard
In-Reply-To: <20260612-sparx5_l3_routing-v1-0-fc3c10160f49@microchip.com>
When reading a rule back from hardware, decoding has to identify which
actionset the rule was written as. The existing logic was only aware of
the actionset subword length, which cannot distinguish actionsets that
share a subword length but differ in their type_id field. The LPM VCAP
added in a following patch introduces this case: ARP_PTR, L3MC_PTR and
ARP_ENTRY all occupy one subword and differ only by type_id.
A helper is introduced to extract the type_id bits directly from
stream[0]. This is valid by construction: the VCAP model places the
type_id field (when present) immediately after the typegroup bits in
the first subword.
Reviewed-by: Daniel Machon <daniel.machon@microchip.com>
Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com>
Signed-off-by: Jens Emil Schulz Østergaard <jensemil.schulzostergaard@microchip.com>
---
drivers/net/ethernet/microchip/vcap/vcap_api.c | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/microchip/vcap/vcap_api.c b/drivers/net/ethernet/microchip/vcap/vcap_api.c
index 6946fd738458..30700648672f 100644
--- a/drivers/net/ethernet/microchip/vcap/vcap_api.c
+++ b/drivers/net/ethernet/microchip/vcap/vcap_api.c
@@ -216,6 +216,13 @@ static void vcap_decode_field(u32 *stream, struct vcap_stream_iter *itr,
}
}
+/* The type_id field is always right after the typegroup bits, if it exists */
+static u8 vcap_find_stream_type_id(u32 *stream, u16 tg_width,
+ u16 typefld_width)
+{
+ return (stream[0] >> tg_width) & GENMASK(typefld_width - 1, 0);
+}
+
/* Verify that the type id in the stream matches the type id of the keyset */
static bool vcap_verify_keystream_keyset(struct vcap_control *vctrl,
enum vcap_type vt,
@@ -1331,8 +1338,10 @@ vcap_verify_actionstream_actionset(struct vcap_control *vctrl,
enum vcap_actionfield_set actionset)
{
const struct vcap_typegroup *tgt;
+ const struct vcap_field *typefld;
const struct vcap_field *fields;
const struct vcap_set *info;
+ u8 value = 0;
if (vcap_actionfield_count(vctrl, vt, actionset) == 0)
return false;
@@ -1355,8 +1364,11 @@ vcap_verify_actionstream_actionset(struct vcap_control *vctrl,
if (!fields)
return false;
- /* Later this will be expanded with a check of the type id */
- return true;
+ typefld = &fields[VCAP_AF_TYPE];
+ value = vcap_find_stream_type_id(actionstream,
+ tgt->width, typefld->width);
+
+ return value == info->type_id;
}
/* Find the subword width of the action typegroup that matches the stream data
--
2.52.0
^ permalink raw reply related
* [PATCH net-next 4/9] net: microchip: vcap: expose helpers in vcap api and update debugfs
From: Jens Emil Schulz Østergaard @ 2026-06-12 12:37 UTC (permalink / raw)
To: Horatiu Vultur, UNGLinuxDriver, Andrew Lunn, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Daniel Machon,
Steen Hegelund, Kees Cook, Gustavo A. R. Silva
Cc: netdev, linux-kernel, linux-arm-kernel, linux-hardening,
Jens Emil Schulz Østergaard
In-Reply-To: <20260612-sparx5_l3_routing-v1-0-fc3c10160f49@microchip.com>
Add new helpers to the vcap client api, in preparation for L3 routing
functionality:
- vcap_val_add_rule(): wraps vcap_val_rule() + vcap_add_rule().
- vcap_rule_mod_action_bit(): modify a bit-typed action on an existing
rule.
Rename VCAP_CID_PREROUTING to VCAP_CID_PREROUTING_L0 and add
VCAP_USER_L3, both needed by the upcoming LPM VCAP user.
Extend the debugfs display to handle the new IP4_XIP and IP6_XIP key
fields.
Fix a latent undefined-behaviour bug in the debugfs action-field
printer. The old mask expression (1 << width) - 1 is UB when width is
32. The bug is unreachable before this series, since no existing field
in any client hits this, but the LPM VCAP introduces VCAP_AF_MAC_LSB
which is 32 bit wide.
Reviewed-by: Daniel Machon <daniel.machon@microchip.com>
Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com>
Signed-off-by: Jens Emil Schulz Østergaard <jensemil.schulzostergaard@microchip.com>
---
drivers/net/ethernet/microchip/vcap/vcap_api.c | 25 ++++++++++++++++++++++
drivers/net/ethernet/microchip/vcap/vcap_api.h | 4 +++-
.../net/ethernet/microchip/vcap/vcap_api_client.h | 6 ++++++
.../net/ethernet/microchip/vcap/vcap_api_debugfs.c | 13 ++++++++---
4 files changed, 44 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ethernet/microchip/vcap/vcap_api.c b/drivers/net/ethernet/microchip/vcap/vcap_api.c
index 30700648672f..0905e4f192a0 100644
--- a/drivers/net/ethernet/microchip/vcap/vcap_api.c
+++ b/drivers/net/ethernet/microchip/vcap/vcap_api.c
@@ -2379,6 +2379,19 @@ int vcap_add_rule(struct vcap_rule *rule)
}
EXPORT_SYMBOL_GPL(vcap_add_rule);
+/* Validate and add rule to a VCAP instance */
+int vcap_val_add_rule(struct vcap_rule *rule, u16 l3_proto)
+{
+ int err;
+
+ err = vcap_val_rule(rule, l3_proto);
+ if (err)
+ return err;
+
+ return vcap_add_rule(rule);
+}
+EXPORT_SYMBOL_GPL(vcap_val_add_rule);
+
/* Allocate a new rule with the provided arguments */
struct vcap_rule *vcap_alloc_rule(struct vcap_control *vctrl,
struct net_device *ndev, int vcap_chain_id,
@@ -3547,6 +3560,18 @@ int vcap_rule_mod_action_u32(struct vcap_rule *rule,
}
EXPORT_SYMBOL_GPL(vcap_rule_mod_action_u32);
+/* Modify a bit action with value in the rule */
+int vcap_rule_mod_action_bit(struct vcap_rule *rule,
+ enum vcap_action_field action,
+ enum vcap_bit val)
+{
+ struct vcap_client_actionfield_data data;
+
+ vcap_rule_set_action_bitsize(&data.u1, val);
+ return vcap_rule_mod_action(rule, action, VCAP_FIELD_BIT, &data);
+}
+EXPORT_SYMBOL_GPL(vcap_rule_mod_action_bit);
+
/* Drop keys in a keylist and any keys that are not supported by the keyset */
int vcap_filter_rule_keys(struct vcap_rule *rule,
enum vcap_key_field keylist[], int length,
diff --git a/drivers/net/ethernet/microchip/vcap/vcap_api.h b/drivers/net/ethernet/microchip/vcap/vcap_api.h
index 6069ad95c27e..e197e7257560 100644
--- a/drivers/net/ethernet/microchip/vcap/vcap_api.h
+++ b/drivers/net/ethernet/microchip/vcap/vcap_api.h
@@ -22,7 +22,7 @@
#define VCAP_CID_INGRESS_L5 1500000 /* Ingress Stage 1 Lookup 5 */
#define VCAP_CID_PREROUTING_IPV6 3000000 /* Prerouting Stage */
-#define VCAP_CID_PREROUTING 6000000 /* Prerouting Stage */
+#define VCAP_CID_PREROUTING_L0 6000000 /* Prerouting Stage Lookup 0 */
#define VCAP_CID_INGRESS_STAGE2_L0 8000000 /* Ingress Stage 2 Lookup 0 */
#define VCAP_CID_INGRESS_STAGE2_L1 8100000 /* Ingress Stage 2 Lookup 1 */
@@ -41,7 +41,9 @@ enum vcap_user {
VCAP_USER_MRP,
VCAP_USER_CFM,
VCAP_USER_VLAN,
+ VCAP_USER_L3,
VCAP_USER_QOS,
+ /* permanent enabled users above here */
VCAP_USER_VCAP_UTIL,
VCAP_USER_TC,
VCAP_USER_TC_EXTRA,
diff --git a/drivers/net/ethernet/microchip/vcap/vcap_api_client.h b/drivers/net/ethernet/microchip/vcap/vcap_api_client.h
index cdf79e17ca54..3f17e1e76b7d 100644
--- a/drivers/net/ethernet/microchip/vcap/vcap_api_client.h
+++ b/drivers/net/ethernet/microchip/vcap/vcap_api_client.h
@@ -167,6 +167,8 @@ void vcap_free_rule(struct vcap_rule *rule);
int vcap_val_rule(struct vcap_rule *rule, u16 l3_proto);
/* Add rule to a VCAP instance */
int vcap_add_rule(struct vcap_rule *rule);
+/* Validate and add rule to a VCAP instance */
+int vcap_val_add_rule(struct vcap_rule *rule, u16 l3_proto);
/* Delete rule in a VCAP instance */
int vcap_del_rule(struct vcap_control *vctrl, struct net_device *ndev, u32 id);
/* Make a full copy of an existing rule with a new rule id */
@@ -266,6 +268,10 @@ int vcap_rule_mod_key_u32(struct vcap_rule *rule, enum vcap_key_field key,
int vcap_rule_mod_action_u32(struct vcap_rule *rule,
enum vcap_action_field action,
u32 value);
+/* Modify a bit action with value in the rule */
+int vcap_rule_mod_action_bit(struct vcap_rule *rule,
+ enum vcap_action_field action,
+ enum vcap_bit val);
/* Get a 32 bit key field value and mask from the rule */
int vcap_rule_get_key_u32(struct vcap_rule *rule, enum vcap_key_field key,
diff --git a/drivers/net/ethernet/microchip/vcap/vcap_api_debugfs.c b/drivers/net/ethernet/microchip/vcap/vcap_api_debugfs.c
index 59bfbda29bb3..56464ece8e6b 100644
--- a/drivers/net/ethernet/microchip/vcap/vcap_api_debugfs.c
+++ b/drivers/net/ethernet/microchip/vcap/vcap_api_debugfs.c
@@ -40,7 +40,8 @@ static void vcap_debugfs_show_rule_keyfield(struct vcap_control *vctrl,
value = (u8 *)(&data->u32.value);
mask = (u8 *)(&data->u32.mask);
- if (key == VCAP_KF_L3_IP4_SIP || key == VCAP_KF_L3_IP4_DIP) {
+ if (key == VCAP_KF_L3_IP4_SIP || key == VCAP_KF_L3_IP4_DIP ||
+ key == VCAP_KF_IP4_XIP) {
out->prf(out->dst, "%pI4h/%pI4h", &data->u32.value,
&data->u32.mask);
} else if (key == VCAP_KF_ETYPE ||
@@ -88,7 +89,8 @@ static void vcap_debugfs_show_rule_keyfield(struct vcap_control *vctrl,
case VCAP_FIELD_U128:
value = data->u128.value;
mask = data->u128.mask;
- if (key == VCAP_KF_L3_IP6_SIP || key == VCAP_KF_L3_IP6_DIP) {
+ if (key == VCAP_KF_L3_IP6_SIP || key == VCAP_KF_L3_IP6_DIP ||
+ key == VCAP_KF_IP6_XIP) {
u8 nvalue[16], nmask[16];
vcap_netbytes_copy(nvalue, data->u128.value,
@@ -133,7 +135,12 @@ vcap_debugfs_show_rule_actionfield(struct vcap_control *vctrl,
out->prf(out->dst, "%d", value[0]);
break;
case VCAP_FIELD_U32:
- fmsk = (1 << actionfield[action].width) - 1;
+ if (action == VCAP_AF_MAC_LSB || action == VCAP_AF_MAC_MSB) {
+ hex = true;
+ break;
+ }
+ fmsk = actionfield[action].width ?
+ GENMASK(actionfield[action].width - 1, 0) : 0;
val = *(u32 *)value;
out->prf(out->dst, "%u", val & fmsk);
break;
--
2.52.0
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