* [PATCH] iommu/arm-smmu-v3: Add tracepoint for EVTQ events
From: Chen Jun @ 2026-06-13 13:00 UTC (permalink / raw)
To: will, robin.murphy, joro, linux-kernel, linux-arm-kernel
Cc: chenjun102, zhangyuwei20
Events reported by the SMMU can severely impact accelerator
performance. Currently, only events that the SMMU fails to handle are
printed to the kernel log, leaving most events invisible to users.
To analyze and optimize accelerator performance, complete visibility
into all SMMU-reported events is required.
Add a tracepoint in the EVTQ interrupt handler to capture every
event record reported by the SMMU. This allows users to collect all
event information via ftrace/perf for further analysis, complementing
the existing event decoder and error dump which only cover a subset
of events.
Signed-off-by: Chen Jun <chenjun102@huawei.com>
---
drivers/iommu/arm/arm-smmu-v3/Makefile | 2 +-
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 3 ++
drivers/iommu/arm/arm-smmu-v3/trace.c | 9 ++++
drivers/iommu/arm/arm-smmu-v3/trace.h | 53 +++++++++++++++++++++
4 files changed, 66 insertions(+), 1 deletion(-)
create mode 100644 drivers/iommu/arm/arm-smmu-v3/trace.c
create mode 100644 drivers/iommu/arm/arm-smmu-v3/trace.h
diff --git a/drivers/iommu/arm/arm-smmu-v3/Makefile b/drivers/iommu/arm/arm-smmu-v3/Makefile
index 493a659cc66b..63a8d71bfc93 100644
--- a/drivers/iommu/arm/arm-smmu-v3/Makefile
+++ b/drivers/iommu/arm/arm-smmu-v3/Makefile
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_ARM_SMMU_V3) += arm_smmu_v3.o
-arm_smmu_v3-y := arm-smmu-v3.o
+arm_smmu_v3-y := arm-smmu-v3.o trace.o
arm_smmu_v3-$(CONFIG_ARM_SMMU_V3_IOMMUFD) += arm-smmu-v3-iommufd.o
arm_smmu_v3-$(CONFIG_ARM_SMMU_V3_SVA) += arm-smmu-v3-sva.o
arm_smmu_v3-$(CONFIG_TEGRA241_CMDQV) += tegra241-cmdqv.o
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
index e8d7dbe495f0..85e6c25b73ed 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
@@ -34,6 +34,8 @@
#include "arm-smmu-v3.h"
#include "../../dma-iommu.h"
+#include "trace.h"
+
static bool disable_msipolling;
module_param(disable_msipolling, bool, 0444);
MODULE_PARM_DESC(disable_msipolling,
@@ -2271,6 +2273,7 @@ static irqreturn_t arm_smmu_evtq_thread(int irq, void *dev)
do {
while (!queue_remove_raw(q, evt)) {
+ trace_smmu_evtq_event(smmu, evt);
arm_smmu_decode_event(smmu, evt, &event);
if (arm_smmu_handle_event(smmu, evt, &event))
arm_smmu_dump_event(smmu, evt, &event, &rs);
diff --git a/drivers/iommu/arm/arm-smmu-v3/trace.c b/drivers/iommu/arm/arm-smmu-v3/trace.c
new file mode 100644
index 000000000000..77378698b1a3
--- /dev/null
+++ b/drivers/iommu/arm/arm-smmu-v3/trace.c
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * ARM SMMUv3 trace support
+ *
+ * Copyright (c) 2026 OpenCloudOS / openEuler
+ */
+
+#define CREATE_TRACE_POINTS
+#include "trace.h"
diff --git a/drivers/iommu/arm/arm-smmu-v3/trace.h b/drivers/iommu/arm/arm-smmu-v3/trace.h
new file mode 100644
index 000000000000..7cec8d41745e
--- /dev/null
+++ b/drivers/iommu/arm/arm-smmu-v3/trace.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * ARM SMMUv3 trace support
+ *
+ * Copyright (c) 2026 OpenCloudOS / openEuler
+ */
+
+#undef TRACE_SYSTEM
+#define TRACE_SYSTEM arm_smmu_v3
+
+#if !defined(_TRACE_ARM_SMMU_V3_H) || defined(TRACE_HEADER_MULTI_READ)
+#define _TRACE_ARM_SMMU_V3_H
+
+#include <linux/tracepoint.h>
+
+#include "arm-smmu-v3.h"
+
+TRACE_EVENT(smmu_evtq_event,
+
+ TP_PROTO(struct arm_smmu_device *smmu, u64 *evt),
+
+ TP_ARGS(smmu, evt),
+
+ TP_STRUCT__entry(
+ __string(iommu, dev_name(smmu->dev))
+ __field(u64, evt0)
+ __field(u64, evt1)
+ __field(u64, evt2)
+ __field(u64, evt3)
+ ),
+
+ TP_fast_assign(
+ __assign_str(iommu);
+ __entry->evt0 = evt[0];
+ __entry->evt1 = evt[1];
+ __entry->evt2 = evt[2];
+ __entry->evt3 = evt[3];
+ ),
+
+ TP_printk("%s evt: 0x%016llx 0x%016llx 0x%016llx 0x%016llx",
+ __get_str(iommu),
+ __entry->evt0, __entry->evt1,
+ __entry->evt2, __entry->evt3)
+);
+
+#endif /* _TRACE_ARM_SMMU_V3_H */
+
+/* This part must be outside protection */
+#undef TRACE_INCLUDE_PATH
+#undef TRACE_INCLUDE_FILE
+#define TRACE_INCLUDE_PATH ../../drivers/iommu/arm/arm-smmu-v3/
+#define TRACE_INCLUDE_FILE trace
+#include <trace/define_trace.h>
--
2.22.0
^ permalink raw reply related
* Re: [PATCH 4/4] arm64: dts: allwinner: add Radxa Cubie A7S
From: Enzo @ 2026-06-13 13:29 UTC (permalink / raw)
To: Jernej Škrabec
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Chen-Yu Tsai,
Samuel Holland, Maxime Ripard, Ulf Hansson, devicetree,
linux-arm-kernel, linux-sunxi, linux-kernel, linux-mmc
In-Reply-To: <yDDIdJcZRCmL2YwI2Wv_ng@gmail.com>
Hi Jernej,
Thanks for taking a look.
> Besides sashiko bot comments, these pins should go to main A733 DTSI,
> like it's done for other SoCs.
>
> In any case, it's a bit early for DT. At least clocks should land before.
Agreed on both points. I'll move the UART0 pin definition into the main
A733 DTSI for the next revision, following the other Allwinner SoCs.
I will also hold off on sending a v2 until the A733 clock prerequisites
are in a better state, unless maintainers prefer a different ordering.
For now I'll keep this series as a checkpoint and continue tracking/testing
the RTC, clock and pinctrl prerequisite work.
Best regards,
Enzo
On Sat, Jun 13, 2026 at 7:37 AM Jernej Škrabec <jernej.skrabec@gmail.com> wrote:
>
> Dne sobota, 13. junij 2026 ob 11:42:16 Srednjeevropski poletni čas je Enzo Adriano via B4 Relay napisal(a):
> > From: Enzo Adriano <enzo.adriano.code@gmail.com>
> >
> > Add the Radxa Cubie A7S board description with serial console and SD card
> > boot support.
> >
> > Ethernet remains disabled until the GMAC210 wrapper, clocks, resets,
> > MDIO, PHY reset, PHY power, and link behavior are proven.
> >
> > Signed-off-by: Enzo Adriano <enzo.adriano.code@gmail.com>
> > ---
> > arch/arm64/boot/dts/allwinner/Makefile | 1 +
> > .../boot/dts/allwinner/sun60i-a733-cubie-a7s.dts | 48 ++++++++++++++++++++++
> > 2 files changed, 49 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
> > index d116864b6c2b..824cc35152db 100644
> > --- a/arch/arm64/boot/dts/allwinner/Makefile
> > +++ b/arch/arm64/boot/dts/allwinner/Makefile
> > @@ -56,6 +56,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h700-anbernic-rg35xx-2024.dtb
> > dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h700-anbernic-rg35xx-h.dtb
> > dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h700-anbernic-rg35xx-plus.dtb
> > dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h700-anbernic-rg35xx-sp.dtb
> > +dtb-$(CONFIG_ARCH_SUNXI) += sun60i-a733-cubie-a7s.dtb
> > dtb-$(CONFIG_ARCH_SUNXI) += sun55i-a527-cubie-a5e.dtb
> > dtb-$(CONFIG_ARCH_SUNXI) += sun55i-h728-x96qpro+.dtb
> > dtb-$(CONFIG_ARCH_SUNXI) += sun55i-t527-avaota-a1.dtb
> > diff --git a/arch/arm64/boot/dts/allwinner/sun60i-a733-cubie-a7s.dts b/arch/arm64/boot/dts/allwinner/sun60i-a733-cubie-a7s.dts
> > new file mode 100644
> > index 000000000000..453761a96323
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/allwinner/sun60i-a733-cubie-a7s.dts
> > @@ -0,0 +1,48 @@
> > +// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
> > +
> > +/dts-v1/;
> > +
> > +#include "sun60i-a733.dtsi"
> > +
> > +/ {
> > + model = "Radxa Cubie A7S";
> > + compatible = "radxa,cubie-a7s", "allwinner,sun60i-a733";
> > +
> > + aliases {
> > + serial0 = &uart0;
> > + mmc0 = &mmc0;
> > + };
> > +
> > + chosen {
> > + stdout-path = "serial0:115200n8";
> > + };
> > +
> > + reg_vcc3v3: vcc3v3 {
> > + compatible = "regulator-fixed";
> > + regulator-name = "vcc-3v3";
> > + regulator-min-microvolt = <3300000>;
> > + regulator-max-microvolt = <3300000>;
> > + regulator-always-on;
> > + };
> > +};
> > +
> > +&mmc0 {
> > + vmmc-supply = <®_vcc3v3>;
> > + bus-width = <4>;
> > + no-mmc;
> > + no-sdio;
> > + status = "okay";
> > +};
> > +
> > +&pio {
> > + uart0_pb9_pb10_pins: uart0-pb9-pb10-pins {
> > + pins = "PB9", "PB10";
> > + function = "uart0";
> > + };
>
> Besides sashiko bot comments, these pins should go to main A733 DTSI,
> like it's done for other SoCs.
>
> In any case, it's a bit early for DT. At least clocks should land before.
>
> Best regards,
> Jernej
>
> > +};
> > +
> > +&uart0 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&uart0_pb9_pb10_pins>;
> > + status = "okay";
> > +};
> >
> >
>
>
>
>
^ permalink raw reply
* Re: [PATCH] iio: stm32-dfsdm: Treat flags as booleans
From: Andy Shevchenko @ 2026-06-13 13:39 UTC (permalink / raw)
To: Rob Herring (Arm)
Cc: Jonathan Cameron, David Lechner, Nuno Sá, Andy Shevchenko,
Maxime Coquelin, Alexandre Torgue, linux-iio, linux-stm32,
linux-arm-kernel, linux-kernel
In-Reply-To: <20260612215151.1886851-1-robh@kernel.org>
On Fri, Jun 12, 2026 at 04:51:50PM -0500, Rob Herring (Arm) wrote:
> The "st,adc-alt-channel" and "st,filter0-sync" properties are
> documented as boolean flags. The legacy parser read them as integer
> cells, unlike the child-node parser which already checks only for
> presence.
>
> Use presence and boolean helpers so both parsers follow the binding and
> the property type checker no longer reports the flags.
For the patch
Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com>
However one interesting remark below.
...
> - ret = of_property_read_u32_index(indio_dev->dev.of_node,
> - "st,adc-alt-channel", chan_idx,
> - &df_ch->alt_si);
> + df_ch->alt_si = of_property_present(indio_dev->dev.of_node,
I believe it still has another (serious?) issue. We usually don't use indio_dev
for device properties. It's not a device that is described in DT.
It seems the only driver in IIO that does that. Note, I haven't conducted any
deeper research, it might be (however I'm quite in doubt) that this is correct
use and one device registers a few indio_dev:s.
> + "st,adc-alt-channel");
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply
* i.MX95: EdgeLock Enclave secure storage
From: Fabio Estevam @ 2026-06-13 13:58 UTC (permalink / raw)
To: Pankaj Gupta
Cc: Schrempf Frieder,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
open list:HARDWARE RANDOM NUMBER GENERATOR CORE, Peng Fan,
Stefano Babic, Frank Li
Hi Pankaj,
First of all, thank you for your work on upstreaming the
EdgeLock Enclave (ELE) support. It is great to finally see the
ELE framework landing upstream after a long development effort.
I am currently evaluating the state of i.MX95 secure-boot and
storage-security support based on current linux-next, with the
goal of understanding what can already be achieved using
upstream software and what pieces are still under development.
From my review, it appears that the following infrastructure is
already available upstream:
- ELE/V2X mailbox support for i.MX95.
- OCOTP/ELE nvmem support for fuse access.
- Secure-enclave bindings documenting the i.MX95 ELE HSM.
However, I could not find upstream support for several
capabilities that would be useful for secure storage
deployments on i.MX95, including:
- An ELE-backed trusted-key provider for the Linux trusted key
framework.
- Integration allowing Linux to use ELE as a key-sealing/
unsealing backend.
- i.MX95-specific crypto acceleration exposed through the Linux
crypto API for dm-crypt use cases.
Are you aware of any ongoing upstream or planned development
activities in these areas, particularly for i.MX95?
Any information about the upstream roadmap, ongoing
development, or expected direction for these features would be
greatly appreciated.
Thanks again for your work and for any insights you can share.
Regards,
Fabio Estevam
^ permalink raw reply
* Re: [PATCH] crypto: atmel-ecc - reject hardware ECDH without a public key
From: Thorsten Blum @ 2026-06-13 14:21 UTC (permalink / raw)
To: Herbert Xu, David S. Miller, Nicolas Ferre, Alexandre Belloni,
Claudiu Beznea, Tudor Ambarus
Cc: linux-crypto, linux-arm-kernel, linux-kernel
In-Reply-To: <20260611213617.463552-2-thorsten.blum@linux.dev>
On Thu, Jun 11, 2026 at 11:36:17PM +0200, Thorsten Blum wrote:
> The hardware ECDH path in atmel_ecdh_compute_shared_secret() uses the
> private key stored in the device. However, the public key is cached only
> after atmel_ecdh_set_secret() successfully generated that private key
> for the current tfm.
>
> atmel_ecdh_generate_public_key() already rejects requests when no public
> key is cached. Add the same check to atmel_ecdh_compute_shared_secret()
> to prevent the device from using a private key that was not generated
> for the current tfm.
>
> Fixes: 11105693fa05 ("crypto: atmel-ecc - introduce Microchip / Atmel ECC driver")
> Signed-off-by: Thorsten Blum <thorsten.blum@linux.dev>
> ---
> drivers/crypto/atmel-ecc.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/crypto/atmel-ecc.c b/drivers/crypto/atmel-ecc.c
> index 93f219558c2f..542c8cc13a0f 100644
> --- a/drivers/crypto/atmel-ecc.c
> +++ b/drivers/crypto/atmel-ecc.c
> @@ -173,6 +173,9 @@ static int atmel_ecdh_compute_shared_secret(struct kpp_request *req)
> return crypto_kpp_compute_shared_secret(req);
> }
>
> + if (!ctx->public_key)
> + return -EINVAL;
> +
> /* must have exactly two points to be on the curve */
> if (req->src_len != ATMEL_ECC_PUBKEY_SIZE)
> return -EINVAL;
I'll need to rebase and resend this assuming [1] is applied first, as it
currently doesn't apply cleanly.
[1] https://lore.kernel.org/lkml/20260609100552.233494-3-thorsten.blum@linux.dev/
^ permalink raw reply
* Re: [PATCH] crypto: atmel-ecc - drop unused curve id from atmel_ecdh_ctx
From: Thorsten Blum @ 2026-06-13 14:23 UTC (permalink / raw)
To: Herbert Xu, David S. Miller, Nicolas Ferre, Alexandre Belloni,
Claudiu Beznea
Cc: linux-crypto, linux-arm-kernel, linux-kernel
In-Reply-To: <20260611105159.460794-3-thorsten.blum@linux.dev>
On Thu, Jun 11, 2026 at 12:52:01PM +0200, Thorsten Blum wrote:
> ->curve_id is only set once, but never used - remove it.
>
> Signed-off-by: Thorsten Blum <thorsten.blum@linux.dev>
> ---
> drivers/crypto/atmel-ecc.c | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/drivers/crypto/atmel-ecc.c b/drivers/crypto/atmel-ecc.c
> index 9da9dd6585df..93f219558c2f 100644
> --- a/drivers/crypto/atmel-ecc.c
> +++ b/drivers/crypto/atmel-ecc.c
> @@ -33,7 +33,6 @@ static struct atmel_ecc_driver_data driver_data;
> * @public_key : generated when calling set_secret(). It's the responsibility
> * of the user to not call set_secret() while
> * generate_public_key() or compute_shared_secret() are in flight.
> - * @curve_id : elliptic curve id
> * @do_fallback: true when the device doesn't support the curve or when the user
> * wants to use its own private key.
> */
> @@ -41,7 +40,6 @@ struct atmel_ecdh_ctx {
> struct i2c_client *client;
> struct crypto_kpp *fallback;
> const u8 *public_key;
> - unsigned int curve_id;
> bool do_fallback;
> };
>
> @@ -250,7 +248,6 @@ static int atmel_ecdh_init_tfm(struct crypto_kpp *tfm)
> struct crypto_kpp *fallback;
> struct atmel_ecdh_ctx *ctx = kpp_tfm_ctx(tfm);
>
> - ctx->curve_id = ECC_CURVE_NIST_P256;
> ctx->client = atmel_ecc_i2c_client_alloc();
> if (IS_ERR(ctx->client)) {
> pr_err("tfm - i2c_client binding failed\n");
I'll need to rebase and resend this assuming [1] is applied first, as it
currently doesn't apply cleanly.
[1] https://lore.kernel.org/lkml/20260609100552.233494-3-thorsten.blum@linux.dev/
^ permalink raw reply
* Re: [PATCH 4/7] drivers: staging: media: sunxi: cedrus: add H616 variant
From: Chen-Yu Tsai @ 2026-06-13 14:34 UTC (permalink / raw)
To: Jernej Škrabec
Cc: Maxime Ripard, Paul Kocialkowski, Mauro Carvalho Chehab,
Jernej Skrabec, Samuel Holland, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Greg Kroah-Hartman, linux-media, linux-staging,
devicetree, linux-sunxi, linux-arm-kernel, linux-kernel
In-Reply-To: <L1ZJMTqKQbak6NcKbwFkDg@gmail.com>
On Sat, Jun 13, 2026 at 6:33 PM Jernej Škrabec <jernej.skrabec@gmail.com> wrote:
>
> Dne sobota, 30. maj 2026 ob 18:43:05 Srednjeevropski poletni čas je Chen-Yu Tsai napisal(a):
> > On Tue, May 5, 2026 at 7:18 PM Jernej Škrabec <jernej.skrabec@gmail.com> wrote:
> > >
> > > Dne torek, 5. maj 2026 ob 15:48:08 Srednjeevropski poletni čas je Chen-Yu Tsai napisal(a):
> > > > The Allwinner H616 SoC has a video engine hardware block like the one
> > > > found on previous generations such as the H6. In addition to the
> > > > currently supported features of the H6, it is also supposed to include
> > >
> > > Remove "supposed".
> >
> > I can't actually verify that, so "supposed" is accurate from my point of
> > view.
>
> Isn't info from manual good enough?
The manual says the SoC supports it. Same was said for the H6. Then
we discovered that the VP9 decoder was a separate Hantro block.
So again, *I* cannot claim in the commit message that the hardware
block supports VP9 decoding, because I have not verified it.
> In the interest of unblocking this, I would be fine with "supposed" too,
> but manual and all my experiments show VP9 is supported.
Please give an ack or reviewed-by with a comment at the end stating
VP9 verified.
Thanks
ChenYu
> Best regards,
> Jernej
>
> >
> > ChenYu
> >
> > > > a VP9 decoder. However software support for this is currently missing
> > > > and still needs to be reverse engineered from the vendor BSP.
> > > >
> > > > Add the compatible for the H616 variant, using the H6 variant data.
> > > >
> > > > Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
> > >
> > > With that:
> > > Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
> > >
> > > Best regards,
> > > Jernej
> > >
> > >
> >
>
>
>
>
>
^ permalink raw reply
* Re: [PATCH] dt-bindings: dma: xilinx: Fix "xlnx,irq-delay" type
From: Pandey, Radhey Shyam @ 2026-06-13 14:48 UTC (permalink / raw)
To: Rob Herring (Arm), Vinod Koul, Frank Li, Krzysztof Kozlowski,
Conor Dooley, Michal Simek, Shyam Pandey, Abin Joseph
Cc: dmaengine, devicetree, linux-arm-kernel, linux-kernel
In-Reply-To: <20260612215226.1887726-1-robh@kernel.org>
> "xlnx,irq-delay" programs an 8-bit delay field in the DMA control
> register, and the driver stores and reads it as a byte. The binding
> described the property as a uint32 cell, which made the helper type
> check report the driver as wrong.
>
> Document "xlnx,irq-delay" as uint8 so the generated schema reflects
> the hardware field width and the existing driver access.
>
> Assisted-by: Codex:gpt-5-5
> Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Thanks!
> ---
> Documentation/devicetree/bindings/dma/xilinx/xlnx,axi-dma.yaml | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/dma/xilinx/xlnx,axi-dma.yaml b/Documentation/devicetree/bindings/dma/xilinx/xlnx,axi-dma.yaml
> index 340ae9e91cb0..ba0fc515d825 100644
> --- a/Documentation/devicetree/bindings/dma/xilinx/xlnx,axi-dma.yaml
> +++ b/Documentation/devicetree/bindings/dma/xilinx/xlnx,axi-dma.yaml
> @@ -93,7 +93,7 @@ properties:
> Width in bits of the length register as configured in hardware.
>
> xlnx,irq-delay:
> - $ref: /schemas/types.yaml#/definitions/uint32
> + $ref: /schemas/types.yaml#/definitions/uint8
> minimum: 0
> maximum: 255
> description:
^ permalink raw reply
* Re: [PATCH] dmaengine: xilinx: Treat "xlnx,flush-fsync" as a flag
From: Pandey, Radhey Shyam @ 2026-06-13 15:13 UTC (permalink / raw)
To: Rob Herring (Arm), Vinod Koul, Frank Li, Michal Simek
Cc: dmaengine, linux-arm-kernel, linux-kernel, harini.katakam,
Suraj.Gupta2
In-Reply-To: <20260612215233.1887921-1-robh@kernel.org>
> The Xilinx DMA binding documents "xlnx,flush-fsync" as a boolean flag.
> The driver read it as an integer cell and warned when it was absent,
> which does not match the documented property encoding.
The original .txt binding (before schema conversion) was not a boolean:
xlnx,flush-fsync: Tells which channel to Flush on Frame sync.
It takes following values:
{1}, flush both channels
{2}, flush mm2s channel
{3}, flush s2mm channel
xilinx_dma_device struct stored it in u32 flush_on_fsync. However yaml
conversion silently changed this to bool which was incorrect. I think
we should change in YAML to make xlnx,flush-fsync as u32?
>
> Use the boolean helper so the driver follows the binding. Leave
> "xlnx,irq-delay" as an 8-bit property read because the hardware field
> is 8 bits wide.
We can skip about irq-delay mention here.
Thanks,
Radhey>
> Assisted-by: Codex:gpt-5-5
> Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
> ---
> drivers/dma/xilinx/xilinx_dma.c | 7 ++-----
> 1 file changed, 2 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
> index 404235c17353..cbb23fd6e096 100644
> --- a/drivers/dma/xilinx/xilinx_dma.c
> +++ b/drivers/dma/xilinx/xilinx_dma.c
> @@ -3262,11 +3262,8 @@ static int xilinx_dma_probe(struct platform_device *pdev)
> goto disable_clks;
> }
>
> - err = of_property_read_u32(node, "xlnx,flush-fsync",
> - &xdev->flush_on_fsync);
> - if (err < 0)
> - dev_warn(xdev->dev,
> - "missing xlnx,flush-fsync property\n");
> + xdev->flush_on_fsync =
> + of_property_read_bool(node, "xlnx,flush-fsync");
> }
>
> err = of_property_read_u32(node, "xlnx,addrwidth", &addr_width);
^ permalink raw reply
* [PATCH v10 0/6] Allwinner A31/A83T MIPI CSI-2 and A31 ISP / Platform Support
From: Paul Kocialkowski @ 2026-06-13 15:26 UTC (permalink / raw)
To: linux-media, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel
Cc: Yong Deng, Paul Kocialkowski, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Chen-Yu Tsai, Jernej Skrabec,
Samuel Holland, Michael Turquette, Stephen Boyd, Brian Masney,
Maxime Ripard
This series adds platform support for the V3s/V3/S3 MIPI CSI-2 and ISP units
as well the as A83T MIPI CSI-2 unit in the respective device-trees.
The corresponding drivers and dt bindings were merged a long time ago but this
series was never actually picked up. It seems more than ready to be merged!
Changes since v9:
- Split clock definitions export;
- Added dedicated v3s d-phy compatible;
- Added interrupt to v3s d-phy definition;
- Removed a83t board overlays that need more work.
Changes since v8:
- Added collected review tags;
- Added the overlays to be built as full dtbs.
- Removed trailing whitespace.
Changes since v7:
- Added collected review tags;
- Added interconnect properties to bindings;
- Added compatible for device-tree overlays;
- Moved mclk pin to sensor node in bpi-m3 overlays;
- Removed duplicated assigned-clocks in bpi-m3 overlays.
Changes since v6:
- Rebased on top of the latest media tree, renamed dts to dtso for overlays.
Changes since v5:
- Added BananaPi M3 camera sensor support as device-tree overlays;
- Cleaned-up OV8865 regulator definitions;
- Always declared the internal links between CSI and MIPI CSI-2 on A83T
in device-tree.
Changes since v4:
- Removed mbus bindings patch: an equivalent change was merged;
- Added collected tags;
- Rebased on latest media tree.
Changes since v3:
- Reordered v3s mbus compatible in binding;
- Added collected tag;
- Removed rejected interconnects fix.
Changes since all-in-one v2:
- Corrected mbus index used for the interconnects;
- Used extended mbus binding and exported the DRAM clock for that;
- Reworked the description of the core openfirmware change to give
more insight about the situation.
Paul Kocialkowski (6):
dt-bindings: sun8i-v3s-ccu: Export MBUS and DRAM clocks to the public
header
clk: sunxi-ng: v3s: Remove exported clock definitions
ARM: dts: sun8i: v3s: Add mbus node to represent the interconnect
dt-bindings: sun6i-a31-mipi-dphy: Add V3s SoC compatible entry
ARM: dts: sun8i: v3s: Add nodes for MIPI CSI-2 support
ARM: dts: sun8i: v3s: Add support for the ISP
.../phy/allwinner,sun6i-a31-mipi-dphy.yaml | 3 +
arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi | 123 ++++++++++++++++++
drivers/clk/sunxi-ng/ccu-sun8i-v3s.h | 4 -
include/dt-bindings/clock/sun8i-v3s-ccu.h | 4 +-
4 files changed, 128 insertions(+), 6 deletions(-)
--
2.54.0
^ permalink raw reply
* [PATCH v10 1/6] dt-bindings: sun8i-v3s-ccu: Export MBUS and DRAM clocks to the public header
From: Paul Kocialkowski @ 2026-06-13 15:26 UTC (permalink / raw)
To: linux-media, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel
Cc: Yong Deng, Paul Kocialkowski, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Chen-Yu Tsai, Jernej Skrabec,
Samuel Holland, Michael Turquette, Stephen Boyd, Brian Masney,
Maxime Ripard
In-Reply-To: <20260613152655.212490-1-paulk@sys-base.io>
In order to declare a mbus node for the V3s, expose its associated
clocks to the public header.
Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
---
include/dt-bindings/clock/sun8i-v3s-ccu.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/dt-bindings/clock/sun8i-v3s-ccu.h b/include/dt-bindings/clock/sun8i-v3s-ccu.h
index c4055629c9f9..d635bffd6914 100644
--- a/include/dt-bindings/clock/sun8i-v3s-ccu.h
+++ b/include/dt-bindings/clock/sun8i-v3s-ccu.h
@@ -87,7 +87,7 @@
#define CLK_SPI0 55
#define CLK_USB_PHY0 56
#define CLK_USB_OHCI0 57
-
+#define CLK_DRAM 58
#define CLK_DRAM_VE 59
#define CLK_DRAM_CSI 60
#define CLK_DRAM_EHCI 61
@@ -101,7 +101,7 @@
#define CLK_VE 69
#define CLK_AC_DIG 70
#define CLK_AVS 71
-
+#define CLK_MBUS 72
#define CLK_MIPI_CSI 73
/* Clocks not available on V3s */
--
2.54.0
^ permalink raw reply related
* [PATCH v10 2/6] clk: sunxi-ng: v3s: Remove exported clock definitions
From: Paul Kocialkowski @ 2026-06-13 15:26 UTC (permalink / raw)
To: linux-media, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel
Cc: Yong Deng, Paul Kocialkowski, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Chen-Yu Tsai, Jernej Skrabec,
Samuel Holland, Michael Turquette, Stephen Boyd, Brian Masney,
Maxime Ripard
In-Reply-To: <20260613152655.212490-1-paulk@sys-base.io>
V3s MBUS and DRAM clock definitions are now exported in the dt-bindings
header. We can remove the duplicated definitons in the clock driver.
Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
---
drivers/clk/sunxi-ng/ccu-sun8i-v3s.h | 4 ----
1 file changed, 4 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.h b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.h
index 345cdbbab362..c933ef016570 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.h
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.h
@@ -39,14 +39,10 @@
/* The first bunch of module clocks are exported */
-#define CLK_DRAM 58
-
/* All the DRAM gates are exported */
/* Some more module clocks are exported */
-#define CLK_MBUS 72
-
/* And the GPU module clock is exported */
#define CLK_PLL_DDR1 74
--
2.54.0
^ permalink raw reply related
* [PATCH v10 3/6] ARM: dts: sun8i: v3s: Add mbus node to represent the interconnect
From: Paul Kocialkowski @ 2026-06-13 15:26 UTC (permalink / raw)
To: linux-media, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel
Cc: Yong Deng, Paul Kocialkowski, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Chen-Yu Tsai, Jernej Skrabec,
Samuel Holland, Michael Turquette, Stephen Boyd, Brian Masney,
Maxime Ripard, Paul Kocialkowski
In-Reply-To: <20260613152655.212490-1-paulk@sys-base.io>
From: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
The V3s uses the mbus interconnect to provide DRAM access for a
number of blocks. The SoC can only map 2 GiB of DRAM, which is
reflected in the dma-ranges property.
Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
---
arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
index fa54510319ac..02d6c62b3874 100644
--- a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
@@ -629,6 +629,21 @@ int_mii_phy: ethernet-phy@1 {
};
};
+ mbus: dram-controller@1c62000 {
+ compatible = "allwinner,sun8i-v3s-mbus";
+ reg = <0x01c62000 0x1000>,
+ <0x01c63000 0x1000>;
+ reg-names = "mbus", "dram";
+ clocks = <&ccu CLK_MBUS>,
+ <&ccu CLK_DRAM>,
+ <&ccu CLK_BUS_DRAM>;
+ clock-names = "mbus", "dram", "bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ dma-ranges = <0x00000000 0x40000000 0x80000000>;
+ #interconnect-cells = <1>;
+ };
+
spi0: spi@1c68000 {
compatible = "allwinner,sun8i-h3-spi";
reg = <0x01c68000 0x1000>;
--
2.54.0
^ permalink raw reply related
* [PATCH v10 4/6] dt-bindings: sun6i-a31-mipi-dphy: Add V3s SoC compatible entry
From: Paul Kocialkowski @ 2026-06-13 15:26 UTC (permalink / raw)
To: linux-media, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel
Cc: Yong Deng, Paul Kocialkowski, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Chen-Yu Tsai, Jernej Skrabec,
Samuel Holland, Michael Turquette, Stephen Boyd, Brian Masney,
Maxime Ripard
In-Reply-To: <20260613152655.212490-1-paulk@sys-base.io>
The V3s/V3/S3 comes with a rx-only D-PHY paired with the MIPI CSI-2
controller. It is compatible with the D-PHY found on the A31.
Add an entry with a new compatible and the A31 compatible as fallback.
Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
---
.../devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
index 6a4fd4929959..3ca1a1c47032 100644
--- a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
+++ b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
@@ -21,6 +21,9 @@ properties:
- items:
- const: allwinner,sun50i-a64-mipi-dphy
- const: allwinner,sun6i-a31-mipi-dphy
+ - items:
+ - const: allwinner,sun8i-v3s-mipi-dphy
+ - const: allwinner,sun6i-a31-mipi-dphy
- items:
- const: allwinner,sun20i-d1-mipi-dphy
- const: allwinner,sun50i-a100-mipi-dphy
--
2.54.0
^ permalink raw reply related
* [PATCH v10 5/6] ARM: dts: sun8i: v3s: Add nodes for MIPI CSI-2 support
From: Paul Kocialkowski @ 2026-06-13 15:26 UTC (permalink / raw)
To: linux-media, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel
Cc: Yong Deng, Paul Kocialkowski, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Chen-Yu Tsai, Jernej Skrabec,
Samuel Holland, Michael Turquette, Stephen Boyd, Brian Masney,
Maxime Ripard, Paul Kocialkowski
In-Reply-To: <20260613152655.212490-1-paulk@sys-base.io>
From: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
MIPI CSI-2 is supported on the V3s with an A31-based MIPI CSI-2 bridge
controller. The controller uses a separate D-PHY, which is the same
that is otherwise used for MIPI DSI, but used in Rx mode.
On the V3s, the CSI0 controller is dedicated to MIPI CSI-2 as it does
not have access to any parallel interface pins.
Add all the necessary nodes (CSI0, MIPI CSI-2 bridge and D-PHY) to
support the MIPI CSI-2 interface.
Note that a fwnode graph link is created between CSI0 and MIPI CSI-2
even when no sensor is connected. This will result in a probe failure
for the controller as long as no sensor is connected but this is fine
since no other interface is available.
The interconnects property is used to inherit the proper DMA offset.
Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
---
arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi | 73 ++++++++++++++++++++++
1 file changed, 73 insertions(+)
diff --git a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
index 02d6c62b3874..03a1739683b1 100644
--- a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
@@ -671,6 +671,79 @@ gic: interrupt-controller@1c81000 {
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
+ csi0: camera@1cb0000 {
+ compatible = "allwinner,sun8i-v3s-csi";
+ reg = <0x01cb0000 0x1000>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_CSI>,
+ <&ccu CLK_CSI_SCLK>,
+ <&ccu CLK_DRAM_CSI>;
+ clock-names = "bus", "mod", "ram";
+ resets = <&ccu RST_BUS_CSI>;
+ interconnects = <&mbus 5>;
+ interconnect-names = "dma-mem";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+
+ csi0_in_mipi_csi2: endpoint {
+ remote-endpoint = <&mipi_csi2_out_csi0>;
+ };
+ };
+ };
+ };
+
+ mipi_csi2: csi@1cb1000 {
+ compatible = "allwinner,sun8i-v3s-mipi-csi2",
+ "allwinner,sun6i-a31-mipi-csi2";
+ reg = <0x01cb1000 0x1000>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_CSI>,
+ <&ccu CLK_CSI_SCLK>;
+ clock-names = "bus", "mod";
+ resets = <&ccu RST_BUS_CSI>;
+ status = "disabled";
+
+ phys = <&dphy>;
+ phy-names = "dphy";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_csi2_in: port@0 {
+ reg = <0>;
+ };
+
+ mipi_csi2_out: port@1 {
+ reg = <1>;
+
+ mipi_csi2_out_csi0: endpoint {
+ remote-endpoint = <&csi0_in_mipi_csi2>;
+ };
+ };
+ };
+ };
+
+ dphy: d-phy@1cb2000 {
+ compatible = "allwinner,sun8i-v3s-mipi-dphy",
+ "allwinner,sun6i-a31-mipi-dphy";
+ reg = <0x01cb2000 0x1000>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_CSI>,
+ <&ccu CLK_MIPI_CSI>;
+ clock-names = "bus", "mod";
+ resets = <&ccu RST_BUS_CSI>;
+ allwinner,direction = "rx";
+ status = "disabled";
+ #phy-cells = <0>;
+ };
+
csi1: camera@1cb4000 {
compatible = "allwinner,sun8i-v3s-csi";
reg = <0x01cb4000 0x3000>;
--
2.54.0
^ permalink raw reply related
* [PATCH v10 6/6] ARM: dts: sun8i: v3s: Add support for the ISP
From: Paul Kocialkowski @ 2026-06-13 15:26 UTC (permalink / raw)
To: linux-media, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel
Cc: Yong Deng, Paul Kocialkowski, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Chen-Yu Tsai, Jernej Skrabec,
Samuel Holland, Michael Turquette, Stephen Boyd, Brian Masney,
Maxime Ripard, Paul Kocialkowski
In-Reply-To: <20260613152655.212490-1-paulk@sys-base.io>
From: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
The V3s (and related platforms) come with an instance of the A31 ISP.
Even though it is very close to the A31 ISP, it is not exactly
register-compatible and a dedicated compatible only is used as a
result.
Just like most other blocks of the camera pipeline, the ISP uses
the common CSI bus, module and ram clock as well as reset.
A port connection to the ISP is added to CSI0 for convenience since
CSI0 serves for MIPI CSI-2 interface support, which is likely to
receive raw data that will need to be processed by the ISP to produce
a final image.
The interconnects property is used to inherit the proper DMA offset.
Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
---
arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi | 35 ++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
index 03a1739683b1..628d5504c3ae 100644
--- a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
+++ b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
@@ -695,6 +695,14 @@ csi0_in_mipi_csi2: endpoint {
remote-endpoint = <&mipi_csi2_out_csi0>;
};
};
+
+ port@2 {
+ reg = <2>;
+
+ csi0_out_isp: endpoint {
+ remote-endpoint = <&isp_in_csi0>;
+ };
+ };
};
};
@@ -755,5 +763,32 @@ csi1: camera@1cb4000 {
resets = <&ccu RST_BUS_CSI>;
status = "disabled";
};
+
+ isp: isp@1cb8000 {
+ compatible = "allwinner,sun8i-v3s-isp";
+ reg = <0x01cb8000 0x1000>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_CSI>,
+ <&ccu CLK_CSI_SCLK>,
+ <&ccu CLK_DRAM_CSI>;
+ clock-names = "bus", "mod", "ram";
+ resets = <&ccu RST_BUS_CSI>;
+ interconnects = <&mbus 5>;
+ interconnect-names = "dma-mem";
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ isp_in_csi0: endpoint {
+ remote-endpoint = <&csi0_out_isp>;
+ };
+ };
+ };
+ };
};
};
--
2.54.0
^ permalink raw reply related
* Re: [PATCH net-next v2 8/8] net: dsa: mt7530: implement port_change_conduit op
From: Daniel Golle @ 2026-06-13 16:09 UTC (permalink / raw)
To: Chester A. Unal, Andrew Lunn, Vladimir Oltean, David S. Miller,
Eric Dumazet, Jakub Kicinski, Paolo Abeni, Matthias Brugger,
AngeloGioacchino Del Regno, Russell King, netdev, linux-kernel,
linux-arm-kernel, linux-mediatek
In-Reply-To: <8dd8cfe32bc8e38b92c49e30a6255090fb0998fb.1781312667.git.daniel@makrotopia.org>
On Sat, Jun 13, 2026 at 02:11:45AM +0100, Daniel Golle wrote:
> Allow changing the CPU port affinity of user ports at runtime via the
> IFLA_DSA_CONDUIT netlink attribute. This updates the port matrix to
> forward to the new CPU port instead of the old one.
>
> Limit the operation to MT7531. There, trapped link-local frames follow
> the per-port affinity, as the MT7531_CPU_PMAP destination mask is
> further restricted by the port matrix. A conduit change is hence fully
> honoured by the hardware, for regular traffic as well as for trapped
> frames.
>
> The MT7530 switch, including the variant embedded in the MT7621 SoC,
> instead traps frames to the single CPU port set in the CPU_PORT field
> of the MFC register, regardless of the affinity of the inbound user
> port. With user ports affine to different CPU ports there is no
> correct value for that field, so per-port CPU affinity cannot be fully
> implemented for trapped frames. Routing a WAN port via the second SoC
> GMAC is conventionally covered by the PHY muxing feature on these
> switches, which bypasses the switch fabric and does not involve a CPU
> port at all.
>
> The switches on the MT7988, EN7581 and AN7583 SoCs only have a
> single CPU port, leaving no other conduit to change to.
>
> Signed-off-by: Daniel Golle <daniel@makrotopia.org>
I forgot to include the previously received
Acked-by: Chester A. Unal <chester.a.unal@arinc9.com>
See also:
https://patchwork.kernel.org/comment/27003848/
https://lore.kernel.org/all/02ad5de0-ea6a-4267-8686-72e3f98fce4e@arinc9.com/
^ permalink raw reply
* Re: [PATCH 2/4] iio: adc: mt6323-auxadc: add mt6323 PMIC AUXADC driver
From: David Lechner @ 2026-06-13 16:42 UTC (permalink / raw)
To: Roman Vivchar, Nuno Sá
Cc: Jonathan Cameron, Nuno Sá, Andy Shevchenko, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Lee Jones, linux-iio, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek, Ben Grisdale
In-Reply-To: <RRvh9UBBrqdfKoCLaqgfcQ06UY-BSM2hQ0F6F1YkdB2k2RXYMQmlCG4phXk72oGY03t1g1kDI4z-SDeKlYkUv84-AjNLaWK7tDQlpEFQVKk=@protonmail.com>
On 6/3/26 6:24 AM, Roman Vivchar wrote:
> Hi Nuno,
>
> On Tuesday, June 2nd, 2026 at 7:42 PM, Nuno Sá <noname.nuno@gmail.com> wrote:
>
>> On Tue, 2026-06-02 at 15:46 +0300, Roman Vivchar via B4 Relay wrote:
>
> ...
>
>>>
>>> +MEDIATEK MT6323 PMIC AUXADC DRIVER
>>> +M: Roman Vivchar <rva333@protonmail.com>
>>> +L: linux-iio@vger.kernel.org
>>> +L: linux-mediatek@lists.infradead.org (moderated for non-subscribers)
>>> +S: Maintained
>>> +F: drivers/iio/adc/mt6323-auxadc.c
>>> +F: include/dt-bindings/iio/adc/mediatek,mt6323-auxadc.h
>>
>> The above file was not added in this patch
>
> The header file is added in patch 1 (dt-bindings). Following Krzysztof's
> feedback on the previous version, I squashed the MAINTAINERS into this patch.
> Please let me know if I misunderstood anything.
Usually, we want the MAINTAINERS entry in the same patch that
the file was added. It is fine to include MAINTAINERS changes
in the dt-bindings patch.
>>> + case IIO_CHAN_INFO_RAW:
>>> + scoped_guard(mutex, &auxadc->lock) {
We can avoid extra indent by making this:
case IIO_CHAN_INFO_RAW: {
guard(mutex)(&auxadc->lock);
...
return IIO_VAL_INT;
}
>>> + ret = mt6323_auxadc_prepare_channel(auxadc);
>>> + if (ret)
>>> + return ret;
>>> +
>>> + ret = mt6323_auxadc_request(auxadc, chan->channel);
>>> + if (ret)
>>> + return ret;
>>> +
>>> + /* Hardware limitation: the AUXADC needs a delay to become
>>> ready. */
>>> + fsleep(300);
>>> +
>>> + ret = mt6323_auxadc_read(auxadc, chan, val);
>>> + if (ret)
>>> + return ret;
>>
>> Could be return mt6323_auxadc_read(...)
>
> The mt6323_auxadc_read returns 0, while IIO expects IIO_VAL_INT (defined as 1).
> Should the mt6323_auxadc_read function return 1 for success?
mt6323_auxadc_read() would need to return IIO_VAL_INT.
^ permalink raw reply
* Re: [PATCH] net: correcting section tags for .init and .exit data/functions
From: Nathan Chancellor @ 2026-06-13 17:01 UTC (permalink / raw)
To: xur
Cc: David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
Simon Horman, Neal Cardwell, Kuniyuki Iwashima, Willem de Bruijn,
David Ahern, Ido Schimmel, Andreas Färber,
Manivannan Sadhasivam, Nick Desaulniers, Bill Wendling,
Justin Stitt, Maciej Żenczykowski, Yue Haibing, Jeff Layton,
Kees Cook, Fernando Fernandez Mancera, Gustavo A. R. Silva,
Sabrina Dubroca, Masahiro Yamada, Nicolas Schier, netdev,
linux-kernel, linux-arm-kernel, linux-actions, llvm,
kernel test robot
In-Reply-To: <20260612162257.896792-1-xur@google.com>
Hi Rong,
On Fri, Jun 12, 2026 at 09:22:57AM -0700, xur@google.com wrote:
> From: Rong Xu <xur@google.com>
>
> Fix modpost warnings that have surfaced during Clang's distributed ThinLTO
> builds.
>
> WARNING: modpost: vmlinux: section mismatch in reference: tcp4_net_ops.llvm.4527429266264891517+0x8 (section: .data) -> tcp4_proc_init_net (section: .init.text)
> WARNING: modpost: vmlinux: section mismatch in reference: udp4_net_ops.llvm.17425824324074326067+0x8 (section: .data) -> udp4_proc_init_net (section: .init.text)
> WARNING: modpost: vmlinux: section mismatch in reference: ping_v4_net_ops.llvm.5641696707737373282+0x8 (section: .data) -> ping_v4_proc_init_net (section: .init.text)
> WARNING: modpost: vmlinux: section mismatch in reference: if6_proc_net_ops.llvm.7870945277386035298+0x8 (section: .data) -> if6_proc_net_init (section: .init.text)
> WARNING: modpost: vmlinux: section mismatch in reference: ipv6_addr_label_ops.llvm.5745897517271459135+0x8 (section: .data) -> ip6addrlbl_net_init (section: .init.text)
> WARNING: modpost: vmlinux: section mismatch in reference: ndisc_net_ops.llvm.8806210167060761094+0x8 (section: .data) -> ndisc_net_init (section: .init.text)
> WARNING: modpost: vmlinux: section mismatch in reference: raw6_net_ops.llvm.3743523335772203324+0x8 (section: .data) -> raw6_init_net (section: .init.text)
> WARNING: modpost: vmlinux: section mismatch in reference: igmp6_net_ops.llvm.7071106350580158050+0x8 (section: .data) -> igmp6_net_init (section: .init.text)
> WARNING: modpost: vmlinux: section mismatch in reference: tcpv6_net_ops.llvm.17505177970592326146+0x8 (section: .data) -> tcpv6_net_init (section: .init.text)
> WARNING: modpost: vmlinux: section mismatch in reference: ip6_flowlabel_net_ops.llvm.6051723423336054316+0x8 (section: .data) -> ip6_flowlabel_proc_init (section: .init.text)
> WARNING: modpost: vmlinux: section mismatch in reference: ipv6_proc_ops.llvm.7829948594772821810+0x8 (section: .data) -> ipv6_proc_init_net (section: .init.text)
>
> Reported-by: kernel test robot <lkp@intel.com>
> Closes: https://lore.kernel.org/oe-kbuild-all/202606111233.kM8oo8Df-lkp@intel.com/
> Signed-off-by: Rong Xu <xur@google.com>
Thanks for sending this change to try and clear up those new warnings
from the distributed ThinLTO build. Based on the build reports that
appear from this change downthread, it does not seem like it is quite
right. Additionally, I think the commit message could be a little more
descriptive around the root cause of the warnings and how this patch
actually addresses it (I can infer but I think that information should
be up front and center).
> ---
> net/ipv4/ping.c | 6 +++---
> net/ipv4/tcp_ipv4.c | 6 +++---
> net/ipv4/udp.c | 6 +++---
> net/ipv6/addrconf.c | 6 +++---
> net/ipv6/addrlabel.c | 6 +++---
> net/ipv6/ip6_flowlabel.c | 6 +++---
> net/ipv6/mcast.c | 10 +++++-----
> net/ipv6/ndisc.c | 10 +++++-----
> net/ipv6/proc.c | 6 +++---
> net/ipv6/raw.c | 6 +++---
> net/ipv6/tcp_ipv6.c | 6 +++---
> 11 files changed, 37 insertions(+), 37 deletions(-)
>
> diff --git a/net/ipv4/ping.c b/net/ipv4/ping.c
> index d36f1e273fde..1dda6d661ad8 100644
> --- a/net/ipv4/ping.c
> +++ b/net/ipv4/ping.c
> @@ -1144,17 +1144,17 @@ static void __net_exit ping_v4_proc_exit_net(struct net *net)
> remove_proc_entry("icmp", net->proc_net);
> }
>
> -static struct pernet_operations ping_v4_net_ops = {
> +static struct pernet_operations ping_v4_net_ops __net_initdata = {
> .init = ping_v4_proc_init_net,
> .exit = ping_v4_proc_exit_net,
> };
>
> -int __init ping_proc_init(void)
> +int __net_init ping_proc_init(void)
> {
> return register_pernet_subsys(&ping_v4_net_ops);
> }
>
> -void ping_proc_exit(void)
> +void __net_exit ping_proc_exit(void)
> {
> unregister_pernet_subsys(&ping_v4_net_ops);
> }
> diff --git a/net/ipv4/tcp_ipv4.c b/net/ipv4/tcp_ipv4.c
> index fdc81150ff6c..9caca5879466 100644
> --- a/net/ipv4/tcp_ipv4.c
> +++ b/net/ipv4/tcp_ipv4.c
> @@ -3317,17 +3317,17 @@ static void __net_exit tcp4_proc_exit_net(struct net *net)
> remove_proc_entry("tcp", net->proc_net);
> }
>
> -static struct pernet_operations tcp4_net_ops = {
> +static struct pernet_operations tcp4_net_ops __net_initdata = {
> .init = tcp4_proc_init_net,
> .exit = tcp4_proc_exit_net,
> };
>
> -int __init tcp4_proc_init(void)
> +int __net_init tcp4_proc_init(void)
> {
> return register_pernet_subsys(&tcp4_net_ops);
> }
>
> -void tcp4_proc_exit(void)
> +void __net_exit tcp4_proc_exit(void)
> {
> unregister_pernet_subsys(&tcp4_net_ops);
> }
> diff --git a/net/ipv4/udp.c b/net/ipv4/udp.c
> index 70f6cbd4ef73..87f4cced2114 100644
> --- a/net/ipv4/udp.c
> +++ b/net/ipv4/udp.c
> @@ -3600,17 +3600,17 @@ static void __net_exit udp4_proc_exit_net(struct net *net)
> remove_proc_entry("udp", net->proc_net);
> }
>
> -static struct pernet_operations udp4_net_ops = {
> +static struct pernet_operations udp4_net_ops __net_initdata = {
> .init = udp4_proc_init_net,
> .exit = udp4_proc_exit_net,
> };
>
> -int __init udp4_proc_init(void)
> +int __net_init udp4_proc_init(void)
> {
> return register_pernet_subsys(&udp4_net_ops);
> }
>
> -void udp4_proc_exit(void)
> +void __net_exit udp4_proc_exit(void)
> {
> unregister_pernet_subsys(&udp4_net_ops);
> }
> diff --git a/net/ipv6/addrconf.c b/net/ipv6/addrconf.c
> index c9e5d3e48ab9..73d9439bd408 100644
> --- a/net/ipv6/addrconf.c
> +++ b/net/ipv6/addrconf.c
> @@ -4527,17 +4527,17 @@ static void __net_exit if6_proc_net_exit(struct net *net)
> remove_proc_entry("if_inet6", net->proc_net);
> }
>
> -static struct pernet_operations if6_proc_net_ops = {
> +static struct pernet_operations if6_proc_net_ops __net_initdata = {
> .init = if6_proc_net_init,
> .exit = if6_proc_net_exit,
> };
>
> -int __init if6_proc_init(void)
> +int __net_init if6_proc_init(void)
> {
> return register_pernet_subsys(&if6_proc_net_ops);
> }
>
> -void if6_proc_exit(void)
> +void __net_exit if6_proc_exit(void)
> {
> unregister_pernet_subsys(&if6_proc_net_ops);
> }
> diff --git a/net/ipv6/addrlabel.c b/net/ipv6/addrlabel.c
> index f4b2618446bd..50f6c1b1edaa 100644
> --- a/net/ipv6/addrlabel.c
> +++ b/net/ipv6/addrlabel.c
> @@ -340,17 +340,17 @@ static void __net_exit ip6addrlbl_net_exit(struct net *net)
> spin_unlock(&net->ipv6.ip6addrlbl_table.lock);
> }
>
> -static struct pernet_operations ipv6_addr_label_ops = {
> +static struct pernet_operations ipv6_addr_label_ops __net_initdata = {
> .init = ip6addrlbl_net_init,
> .exit = ip6addrlbl_net_exit,
> };
>
> -int __init ipv6_addr_label_init(void)
> +int __net_init ipv6_addr_label_init(void)
> {
> return register_pernet_subsys(&ipv6_addr_label_ops);
> }
>
> -void ipv6_addr_label_cleanup(void)
> +void __net_exit ipv6_addr_label_cleanup(void)
> {
> unregister_pernet_subsys(&ipv6_addr_label_ops);
> }
> diff --git a/net/ipv6/ip6_flowlabel.c b/net/ipv6/ip6_flowlabel.c
> index b1ccdf0dc646..f6980c403c68 100644
> --- a/net/ipv6/ip6_flowlabel.c
> +++ b/net/ipv6/ip6_flowlabel.c
> @@ -903,17 +903,17 @@ static void __net_exit ip6_flowlabel_net_exit(struct net *net)
> ip6_flowlabel_proc_fini(net);
> }
>
> -static struct pernet_operations ip6_flowlabel_net_ops = {
> +static struct pernet_operations ip6_flowlabel_net_ops __net_initdata = {
> .init = ip6_flowlabel_proc_init,
> .exit = ip6_flowlabel_net_exit,
> };
>
> -int ip6_flowlabel_init(void)
> +int __net_init ip6_flowlabel_init(void)
> {
> return register_pernet_subsys(&ip6_flowlabel_net_ops);
> }
>
> -void ip6_flowlabel_cleanup(void)
> +void __net_exit ip6_flowlabel_cleanup(void)
> {
> static_key_deferred_flush(&ipv6_flowlabel_exclusive);
> timer_delete(&ip6_fl_gc_timer);
> diff --git a/net/ipv6/mcast.c b/net/ipv6/mcast.c
> index d9b855d5191b..eef5bab1ee13 100644
> --- a/net/ipv6/mcast.c
> +++ b/net/ipv6/mcast.c
> @@ -3209,12 +3209,12 @@ static void __net_exit igmp6_net_exit(struct net *net)
> igmp6_proc_exit(net);
> }
>
> -static struct pernet_operations igmp6_net_ops = {
> +static struct pernet_operations igmp6_net_ops __net_initdata = {
> .init = igmp6_net_init,
> .exit = igmp6_net_exit,
> };
>
> -int __init igmp6_init(void)
> +int __net_init igmp6_init(void)
> {
> int err;
>
> @@ -3231,18 +3231,18 @@ int __init igmp6_init(void)
> return err;
> }
>
> -int __init igmp6_late_init(void)
> +int __net_init igmp6_late_init(void)
> {
> return register_netdevice_notifier(&igmp6_netdev_notifier);
> }
>
> -void igmp6_cleanup(void)
> +void __net_exit igmp6_cleanup(void)
> {
> unregister_pernet_subsys(&igmp6_net_ops);
> destroy_workqueue(mld_wq);
> }
>
> -void igmp6_late_cleanup(void)
> +void __net_exit igmp6_late_cleanup(void)
> {
> unregister_netdevice_notifier(&igmp6_netdev_notifier);
> }
> diff --git a/net/ipv6/ndisc.c b/net/ipv6/ndisc.c
> index e7ad13c5bd26..3a83280db29d 100644
> --- a/net/ipv6/ndisc.c
> +++ b/net/ipv6/ndisc.c
> @@ -1994,12 +1994,12 @@ static void __net_exit ndisc_net_exit(struct net *net)
> inet_ctl_sock_destroy(net->ipv6.ndisc_sk);
> }
>
> -static struct pernet_operations ndisc_net_ops = {
> +static struct pernet_operations ndisc_net_ops __net_initdata = {
> .init = ndisc_net_init,
> .exit = ndisc_net_exit,
> };
>
> -int __init ndisc_init(void)
> +int __net_init ndisc_init(void)
> {
> int err;
>
> @@ -2027,17 +2027,17 @@ int __init ndisc_init(void)
> #endif
> }
>
> -int __init ndisc_late_init(void)
> +int __net_init ndisc_late_init(void)
> {
> return register_netdevice_notifier(&ndisc_netdev_notifier);
> }
>
> -void ndisc_late_cleanup(void)
> +void __net_exit ndisc_late_cleanup(void)
> {
> unregister_netdevice_notifier(&ndisc_netdev_notifier);
> }
>
> -void ndisc_cleanup(void)
> +void __net_exit ndisc_cleanup(void)
> {
> #ifdef CONFIG_SYSCTL
> neigh_sysctl_unregister(&nd_tbl.parms);
> diff --git a/net/ipv6/proc.c b/net/ipv6/proc.c
> index 813013ca4e75..c59bade608cd 100644
> --- a/net/ipv6/proc.c
> +++ b/net/ipv6/proc.c
> @@ -298,17 +298,17 @@ static void __net_exit ipv6_proc_exit_net(struct net *net)
> remove_proc_entry("snmp6", net->proc_net);
> }
>
> -static struct pernet_operations ipv6_proc_ops = {
> +static struct pernet_operations ipv6_proc_ops __net_initdata = {
> .init = ipv6_proc_init_net,
> .exit = ipv6_proc_exit_net,
> };
>
> -int __init ipv6_misc_proc_init(void)
> +int __net_init ipv6_misc_proc_init(void)
> {
> return register_pernet_subsys(&ipv6_proc_ops);
> }
>
> -void ipv6_misc_proc_exit(void)
> +void __net_exit ipv6_misc_proc_exit(void)
> {
> unregister_pernet_subsys(&ipv6_proc_ops);
> }
> diff --git a/net/ipv6/raw.c b/net/ipv6/raw.c
> index 3cc58698cbbd..fe399675b8fc 100644
> --- a/net/ipv6/raw.c
> +++ b/net/ipv6/raw.c
> @@ -1256,17 +1256,17 @@ static void __net_exit raw6_exit_net(struct net *net)
> remove_proc_entry("raw6", net->proc_net);
> }
>
> -static struct pernet_operations raw6_net_ops = {
> +static struct pernet_operations raw6_net_ops __net_initdata = {
> .init = raw6_init_net,
> .exit = raw6_exit_net,
> };
>
> -int __init raw6_proc_init(void)
> +int __net_init raw6_proc_init(void)
> {
> return register_pernet_subsys(&raw6_net_ops);
> }
>
> -void raw6_proc_exit(void)
> +void __net_exit raw6_proc_exit(void)
> {
> unregister_pernet_subsys(&raw6_net_ops);
> }
> diff --git a/net/ipv6/tcp_ipv6.c b/net/ipv6/tcp_ipv6.c
> index 36d75fb50a70..d0737f16076b 100644
> --- a/net/ipv6/tcp_ipv6.c
> +++ b/net/ipv6/tcp_ipv6.c
> @@ -2335,12 +2335,12 @@ static void __net_exit tcpv6_net_exit(struct net *net)
> inet_ctl_sock_destroy(net->ipv6.tcp_sk);
> }
>
> -static struct pernet_operations tcpv6_net_ops = {
> +static struct pernet_operations tcpv6_net_ops __net_initdata = {
> .init = tcpv6_net_init,
> .exit = tcpv6_net_exit,
> };
>
> -int __init tcpv6_init(void)
> +int __net_init tcpv6_init(void)
> {
> int ret;
>
> @@ -2378,7 +2378,7 @@ int __init tcpv6_init(void)
> goto out;
> }
>
> -void tcpv6_exit(void)
> +void __net_exit tcpv6_exit(void)
> {
> unregister_pernet_subsys(&tcpv6_net_ops);
> inet6_unregister_protosw(&tcpv6_protosw);
>
> base-commit: 2b414a95b8f7307d42173ba9e580d6d3e2bcbfce
> --
> 2.54.0.1136.gdb2ca164c4-goog
>
>
--
Cheers,
Nathan
^ permalink raw reply
* Re: [PATCH] ARM: dts: exynos: Add bluetooth support to manta
From: Lukas Timmermann @ 2026-06-13 17:11 UTC (permalink / raw)
To: Krzysztof Kozlowski, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Alim Akhtar
Cc: devicetree, linux-arm-kernel, linux-samsung-soc, linux-kernel,
Alexandre Marquet
In-Reply-To: <653b640e-8b61-4c60-a455-63a400b308e7@kernel.org>
#include <atomic>
On Mon, Apr 27, 2026 at 03:49:34PM +0200, Krzysztof Kozlowski wrote:
> On 08/04/2026 13:56, Lukas Timmermann wrote:
> > Enable the bcm4330-bt device for manta boards on serial0.
> > Also adds the necessary pin definitions and interrupt handling for
> > wakeup.
> >
> > Signed-off-by: Lukas Timmermann <linux@timmermann.space>
> > Co-developed-by: Alexandre Marquet <tb@a-marquet.fr>
> > Signed-off-by: Alexandre Marquet <tb@a-marquet.fr>
>
> Incomplete/incorrect DCO chain. Please do not reorder tags. Git does
> them correctly, so you HAD to change them manually.
>
> You send the patch or you apply the patch so you must commit with sign off.
I developed the actual patch based on his findings. We both don't really
care about who is mentioned first or anything.
Sorry. Yes I rearranged stuff. So it should be:
co-dev: alex
sign-off: alex
co-dev: me
sign-off: me
Correct?
>
> Best regards,
> Krzysztof
>
Best regards,
Lukas
^ permalink raw reply
* Re: [PATCH v2] net: airoha: Fix error handling in airoha_ppe_flush_sram_entries()
From: patchwork-bot+netdevbpf @ 2026-06-13 17:40 UTC (permalink / raw)
To: Wayen.Yan; +Cc: netdev, lorenzo, linux-arm-kernel, linux-mediatek
In-Reply-To: <6a2bd37a.4034e349.1b41bb.1caf@mx.google.com>
Hello:
This patch was applied to netdev/net.git (main)
by Jakub Kicinski <kuba@kernel.org>:
On Fri, 12 Jun 2026 17:37:00 +0800 you wrote:
> In airoha_ppe_flush_sram_entries(), the outer "err" variable was never
> updated when the inner loop variable shadowed it, causing the function
> to always return 0 even when airoha_ppe_foe_commit_sram_entry() fails.
>
> Drop the outer "err" variable and return directly on error, propagating
> the error code from airoha_ppe_foe_commit_sram_entry() correctly.
>
> [...]
Here is the summary with links:
- [v2] net: airoha: Fix error handling in airoha_ppe_flush_sram_entries()
https://git.kernel.org/netdev/net/c/d7d81b003013
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
^ permalink raw reply
* Re: [PATCH v10 1/6] dt-bindings: sun8i-v3s-ccu: Export MBUS and DRAM clocks to the public header
From: Krzysztof Kozlowski @ 2026-06-13 18:20 UTC (permalink / raw)
To: Paul Kocialkowski
Cc: linux-media, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel, Yong Deng, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Chen-Yu Tsai, Jernej Skrabec,
Samuel Holland, Michael Turquette, Stephen Boyd, Brian Masney,
Maxime Ripard
In-Reply-To: <20260613152655.212490-2-paulk@sys-base.io>
On Sat, Jun 13, 2026 at 05:26:50PM +0200, Paul Kocialkowski wrote:
> In order to declare a mbus node for the V3s, expose its associated
> clocks to the public header.
>
> Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
> ---
> include/dt-bindings/clock/sun8i-v3s-ccu.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v10 4/6] dt-bindings: sun6i-a31-mipi-dphy: Add V3s SoC compatible entry
From: Krzysztof Kozlowski @ 2026-06-13 18:22 UTC (permalink / raw)
To: Paul Kocialkowski
Cc: linux-media, devicetree, linux-arm-kernel, linux-sunxi,
linux-kernel, Yong Deng, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Chen-Yu Tsai, Jernej Skrabec,
Samuel Holland, Michael Turquette, Stephen Boyd, Brian Masney,
Maxime Ripard
In-Reply-To: <20260613152655.212490-5-paulk@sys-base.io>
On Sat, Jun 13, 2026 at 05:26:53PM +0200, Paul Kocialkowski wrote:
> The V3s/V3/S3 comes with a rx-only D-PHY paired with the MIPI CSI-2
> controller. It is compatible with the D-PHY found on the A31.
>
> Add an entry with a new compatible and the A31 compatible as fallback.
>
> Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
> ---
> .../devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
> index 6a4fd4929959..3ca1a1c47032 100644
> --- a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
> +++ b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
> @@ -21,6 +21,9 @@ properties:
> - items:
> - const: allwinner,sun50i-a64-mipi-dphy
> - const: allwinner,sun6i-a31-mipi-dphy
> + - items:
> + - const: allwinner,sun8i-v3s-mipi-dphy
So that's enum with previous first entry (50i-a64) - same fallback.
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v4 1/2] arm: dts: st: align node patterns with established convention
From: Krzysztof Kozlowski @ 2026-06-13 18:23 UTC (permalink / raw)
To: Charan Pedumuru
Cc: Ulf Hansson, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Peter Griffin, Patrice Chotard, linux-mmc, devicetree,
linux-kernel, linux-arm-kernel
In-Reply-To: <20260613-st-mmc-v4-1-b3c385617c16@gmail.com>
On Sat, Jun 13, 2026 at 09:39:39AM +0000, Charan Pedumuru wrote:
> Update ST MMC DTS node patterns to match established convention.
>
> Signed-off-by: Charan Pedumuru <charan.pedumuru@gmail.com>
> ---
> arch/arm/boot/dts/st/stih407-family.dtsi | 4 ++--
Thanks, but please fix all the files of stih in one commit, not file by
file. git grep gives more instances of it.
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/st/stih407-family.dtsi b/arch/arm/boot/dts/st/stih407-family.dtsi
> index 3e6a0542e3ae..08acba209c56 100644
> --- a/arch/arm/boot/dts/st/stih407-family.dtsi
Best regards,
Krzysztof
^ permalink raw reply
* Re: [PATCH v4 1/2] arm: dts: st: align node patterns with established convention
From: Krzysztof Kozlowski @ 2026-06-13 18:25 UTC (permalink / raw)
To: Charan Pedumuru
Cc: Ulf Hansson, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Peter Griffin, Patrice Chotard, linux-mmc, devicetree,
linux-kernel, linux-arm-kernel
In-Reply-To: <20260613-wondrous-shapeless-pelican-6b927d@quoll>
On 13/06/2026 20:23, Krzysztof Kozlowski wrote:
> On Sat, Jun 13, 2026 at 09:39:39AM +0000, Charan Pedumuru wrote:
>> Update ST MMC DTS node patterns to match established convention.
>>
>> Signed-off-by: Charan Pedumuru <charan.pedumuru@gmail.com>
>> ---
>> arch/arm/boot/dts/st/stih407-family.dtsi | 4 ++--
>
> Thanks, but please fix all the files of stih in one commit, not file by
> file. git grep gives more instances of it.
>
Heh, no it isn't only that. You actually broke other users! And you
received that comment already at v3 which you completely ignored.
This looks like introducing real bugs.
Best regards,
Krzysztof
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox