* [PATCH 11/11] pinctrl: nxp: lpc: Remove NOMMU platform support
From: Frank.Li @ 2026-06-19 15:41 UTC (permalink / raw)
To: Arnd Bergmann, Sascha Hauer, Pengutronix Kernel Team,
Stefan Agner, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Russell King, Abel Vesa, Peng Fan,
Michael Turquette, Stephen Boyd, Brian Masney, Dong Aisheng,
Jacky Bai, NXP S32 Linux Team, Linus Walleij, Vladimir Zapolskiy,
Piotr Wojtaszczyk, Kees Cook, Gustavo A. R. Silva
Cc: linux-arm-kernel, imx, devicetree, linux-kernel, linux-clk,
linux-gpio, linux-hardening, Frank Li
In-Reply-To: <20260619-dts_cleanup_arm_mcore-v1-0-0101795a2662@nxp.com>
From: Frank Li <Frank.Li@nxp.com>
Commercial users and hardware vendors migrated to Zephyr or other RTOS
solutions years ago, leaving the NOMMU platform support effectively
unused and unmaintained.
Remove the obsolete support to reduce maintenance burden and simplify the
NXP/Freescale platform code.
The pinctrl driver is highly SoC-specific and provides little opportunity
for reuse on future hardware
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
drivers/pinctrl/Kconfig | 9 -
drivers/pinctrl/Makefile | 1 -
drivers/pinctrl/pinctrl-lpc18xx.c | 1382 -------------------------------------
3 files changed, 1392 deletions(-)
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index c2cdd7b2c49b0..35a379570becd 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -364,15 +364,6 @@ config PINCTRL_XWAY
depends on SOC_TYPE_XWAY
depends on PINCTRL_LANTIQ
-config PINCTRL_LPC18XX
- bool "NXP LPC18XX/43XX SCU pinctrl driver"
- depends on OF && (ARCH_LPC18XX || COMPILE_TEST)
- default ARCH_LPC18XX
- select PINMUX
- select GENERIC_PINCONF
- help
- Pinctrl driver for NXP LPC18xx/43xx System Control Unit (SCU).
-
config PINCTRL_MAX7360
tristate "MAX7360 Pincontrol support"
depends on MFD_MAX7360
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index a35d71135abfb..2176baf2ec3fc 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -38,7 +38,6 @@ obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o
obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o
obj-$(CONFIG_PINCTRL_LOONGSON2) += pinctrl-loongson2.o
obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o
-obj-$(CONFIG_PINCTRL_LPC18XX) += pinctrl-lpc18xx.o
obj-$(CONFIG_PINCTRL_MAX7360) += pinctrl-max7360.o
obj-$(CONFIG_PINCTRL_MAX77620) += pinctrl-max77620.o
obj-$(CONFIG_PINCTRL_MCP23S08_I2C) += pinctrl-mcp23s08_i2c.o
diff --git a/drivers/pinctrl/pinctrl-lpc18xx.c b/drivers/pinctrl/pinctrl-lpc18xx.c
deleted file mode 100644
index 5e02017683235..0000000000000
--- a/drivers/pinctrl/pinctrl-lpc18xx.c
+++ /dev/null
@@ -1,1382 +0,0 @@
-/*
- * Pinctrl driver for NXP LPC18xx/LPC43xx System Control Unit (SCU)
- *
- * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/bitops.h>
-#include <linux/clk.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/mod_devicetable.h>
-#include <linux/platform_device.h>
-
-#include <linux/pinctrl/pinconf-generic.h>
-#include <linux/pinctrl/pinconf.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/pinctrl/pinmux.h>
-
-#include "core.h"
-#include "pinctrl-utils.h"
-
-/* LPC18XX SCU analog function registers */
-#define LPC18XX_SCU_REG_ENAIO0 0xc88
-#define LPC18XX_SCU_REG_ENAIO1 0xc8c
-#define LPC18XX_SCU_REG_ENAIO2 0xc90
-#define LPC18XX_SCU_REG_ENAIO2_DAC BIT(0)
-
-/* LPC18XX SCU pin register definitions */
-#define LPC18XX_SCU_PIN_MODE_MASK 0x7
-#define LPC18XX_SCU_PIN_EPD BIT(3)
-#define LPC18XX_SCU_PIN_EPUN BIT(4)
-#define LPC18XX_SCU_PIN_EHS BIT(5)
-#define LPC18XX_SCU_PIN_EZI BIT(6)
-#define LPC18XX_SCU_PIN_ZIF BIT(7)
-#define LPC18XX_SCU_PIN_EHD_MASK 0x300
-#define LPC18XX_SCU_PIN_EHD_POS 8
-
-#define LPC18XX_SCU_USB1_EPD BIT(2)
-#define LPC18XX_SCU_USB1_EPWR BIT(4)
-
-#define LPC18XX_SCU_I2C0_EFP BIT(0)
-#define LPC18XX_SCU_I2C0_EHD BIT(2)
-#define LPC18XX_SCU_I2C0_EZI BIT(3)
-#define LPC18XX_SCU_I2C0_ZIF BIT(7)
-#define LPC18XX_SCU_I2C0_SCL_SHIFT 0
-#define LPC18XX_SCU_I2C0_SDA_SHIFT 8
-
-#define LPC18XX_SCU_FUNC_PER_PIN 8
-
-/* LPC18XX SCU pin interrupt select registers */
-#define LPC18XX_SCU_PINTSEL0 0xe00
-#define LPC18XX_SCU_PINTSEL1 0xe04
-#define LPC18XX_SCU_PINTSEL_VAL_MASK 0xff
-#define LPC18XX_SCU_PINTSEL_PORT_SHIFT 5
-#define LPC18XX_SCU_IRQ_PER_PINTSEL 4
-#define LPC18XX_GPIO_PINS_PER_PORT 32
-#define LPC18XX_GPIO_PIN_INT_MAX 8
-
-#define LPC18XX_SCU_PINTSEL_VAL(val, n) \
- ((val) << (((n) % LPC18XX_SCU_IRQ_PER_PINTSEL) * 8))
-
-/* LPC18xx pin types */
-enum {
- TYPE_ND, /* Normal-drive */
- TYPE_HD, /* High-drive */
- TYPE_HS, /* High-speed */
- TYPE_I2C0,
- TYPE_USB1,
-};
-
-/* LPC18xx pin functions */
-enum {
- FUNC_R, /* Reserved */
- FUNC_ADC,
- FUNC_ADCTRIG,
- FUNC_CAN0,
- FUNC_CAN1,
- FUNC_CGU_OUT,
- FUNC_CLKIN,
- FUNC_CLKOUT,
- FUNC_CTIN,
- FUNC_CTOUT,
- FUNC_DAC,
- FUNC_EMC,
- FUNC_EMC_ALT,
- FUNC_ENET,
- FUNC_ENET_ALT,
- FUNC_GPIO,
- FUNC_I2C0,
- FUNC_I2C1,
- FUNC_I2S0_RX_MCLK,
- FUNC_I2S0_RX_SCK,
- FUNC_I2S0_RX_SDA,
- FUNC_I2S0_RX_WS,
- FUNC_I2S0_TX_MCLK,
- FUNC_I2S0_TX_SCK,
- FUNC_I2S0_TX_SDA,
- FUNC_I2S0_TX_WS,
- FUNC_I2S1,
- FUNC_LCD,
- FUNC_LCD_ALT,
- FUNC_MCTRL,
- FUNC_NMI,
- FUNC_QEI,
- FUNC_SDMMC,
- FUNC_SGPIO,
- FUNC_SPI,
- FUNC_SPIFI,
- FUNC_SSP0,
- FUNC_SSP0_ALT,
- FUNC_SSP1,
- FUNC_TIMER0,
- FUNC_TIMER1,
- FUNC_TIMER2,
- FUNC_TIMER3,
- FUNC_TRACE,
- FUNC_UART0,
- FUNC_UART1,
- FUNC_UART2,
- FUNC_UART3,
- FUNC_USB0,
- FUNC_USB1,
- FUNC_MAX
-};
-
-static const char *const lpc18xx_function_names[] = {
- [FUNC_R] = "reserved",
- [FUNC_ADC] = "adc",
- [FUNC_ADCTRIG] = "adctrig",
- [FUNC_CAN0] = "can0",
- [FUNC_CAN1] = "can1",
- [FUNC_CGU_OUT] = "cgu_out",
- [FUNC_CLKIN] = "clkin",
- [FUNC_CLKOUT] = "clkout",
- [FUNC_CTIN] = "ctin",
- [FUNC_CTOUT] = "ctout",
- [FUNC_DAC] = "dac",
- [FUNC_EMC] = "emc",
- [FUNC_EMC_ALT] = "emc_alt",
- [FUNC_ENET] = "enet",
- [FUNC_ENET_ALT] = "enet_alt",
- [FUNC_GPIO] = "gpio",
- [FUNC_I2C0] = "i2c0",
- [FUNC_I2C1] = "i2c1",
- [FUNC_I2S0_RX_MCLK] = "i2s0_rx_mclk",
- [FUNC_I2S0_RX_SCK] = "i2s0_rx_sck",
- [FUNC_I2S0_RX_SDA] = "i2s0_rx_sda",
- [FUNC_I2S0_RX_WS] = "i2s0_rx_ws",
- [FUNC_I2S0_TX_MCLK] = "i2s0_tx_mclk",
- [FUNC_I2S0_TX_SCK] = "i2s0_tx_sck",
- [FUNC_I2S0_TX_SDA] = "i2s0_tx_sda",
- [FUNC_I2S0_TX_WS] = "i2s0_tx_ws",
- [FUNC_I2S1] = "i2s1",
- [FUNC_LCD] = "lcd",
- [FUNC_LCD_ALT] = "lcd_alt",
- [FUNC_MCTRL] = "mctrl",
- [FUNC_NMI] = "nmi",
- [FUNC_QEI] = "qei",
- [FUNC_SDMMC] = "sdmmc",
- [FUNC_SGPIO] = "sgpio",
- [FUNC_SPI] = "spi",
- [FUNC_SPIFI] = "spifi",
- [FUNC_SSP0] = "ssp0",
- [FUNC_SSP0_ALT] = "ssp0_alt",
- [FUNC_SSP1] = "ssp1",
- [FUNC_TIMER0] = "timer0",
- [FUNC_TIMER1] = "timer1",
- [FUNC_TIMER2] = "timer2",
- [FUNC_TIMER3] = "timer3",
- [FUNC_TRACE] = "trace",
- [FUNC_UART0] = "uart0",
- [FUNC_UART1] = "uart1",
- [FUNC_UART2] = "uart2",
- [FUNC_UART3] = "uart3",
- [FUNC_USB0] = "usb0",
- [FUNC_USB1] = "usb1",
-};
-
-struct lpc18xx_pmx_func {
- const char **groups;
- unsigned ngroups;
-};
-
-struct lpc18xx_scu_data {
- struct pinctrl_dev *pctl;
- void __iomem *base;
- struct clk *clk;
- struct lpc18xx_pmx_func func[FUNC_MAX];
-};
-
-struct lpc18xx_pin_caps {
- unsigned int offset;
- unsigned char functions[LPC18XX_SCU_FUNC_PER_PIN];
- unsigned char analog;
- unsigned char type;
-};
-
-/* Analog pins are required to have both bias and input disabled */
-#define LPC18XX_SCU_ANALOG_PIN_CFG 0x10
-
-/* Macros to maniupluate analog member in lpc18xx_pin_caps */
-#define LPC18XX_ANALOG_PIN BIT(7)
-#define LPC18XX_ANALOG_ADC(a) ((a >> 5) & 0x3)
-#define LPC18XX_ANALOG_BIT_MASK 0x1f
-#define ADC0 (LPC18XX_ANALOG_PIN | (0x00 << 5))
-#define ADC1 (LPC18XX_ANALOG_PIN | (0x01 << 5))
-#define DAC LPC18XX_ANALOG_PIN
-
-#define LPC_P(port, pin, f0, f1, f2, f3, f4, f5, f6, f7, a, t) \
-static struct lpc18xx_pin_caps lpc18xx_pin_p##port##_##pin = { \
- .offset = 0x##port * 32 * 4 + pin * 4, \
- .functions = { \
- FUNC_##f0, FUNC_##f1, FUNC_##f2, \
- FUNC_##f3, FUNC_##f4, FUNC_##f5, \
- FUNC_##f6, FUNC_##f7, \
- }, \
- .analog = a, \
- .type = TYPE_##t, \
-}
-
-#define LPC_N(pname, off, f0, f1, f2, f3, f4, f5, f6, f7, a, t) \
-static struct lpc18xx_pin_caps lpc18xx_pin_##pname = { \
- .offset = off, \
- .functions = { \
- FUNC_##f0, FUNC_##f1, FUNC_##f2, \
- FUNC_##f3, FUNC_##f4, FUNC_##f5, \
- FUNC_##f6, FUNC_##f7, \
- }, \
- .analog = a, \
- .type = TYPE_##t, \
-}
-
-
-/* Pinmuxing table taken from data sheet */
-/* Pin FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 ANALOG TYPE */
-LPC_P(0,0, GPIO, SSP1, ENET, SGPIO, R, R, I2S0_TX_WS,I2S1, 0, ND);
-LPC_P(0,1, GPIO, SSP1,ENET_ALT,SGPIO, R, R, ENET, I2S1, 0, ND);
-LPC_P(1,0, GPIO, CTIN, EMC, R, R, SSP0, SGPIO, R, 0, ND);
-LPC_P(1,1, GPIO, CTOUT, EMC, SGPIO, R, SSP0, R, R, 0, ND);
-LPC_P(1,2, GPIO, CTOUT, EMC, SGPIO, R, SSP0, R, R, 0, ND);
-LPC_P(1,3, GPIO, CTOUT, SGPIO, EMC, USB0, SSP1, R, SDMMC, 0, ND);
-LPC_P(1,4, GPIO, CTOUT, SGPIO, EMC, USB0, SSP1, R, SDMMC, 0, ND);
-LPC_P(1,5, GPIO, CTOUT, R, EMC, USB0, SSP1, SGPIO, SDMMC, 0, ND);
-LPC_P(1,6, GPIO, CTIN, R, EMC, R, R, SGPIO, SDMMC, 0, ND);
-LPC_P(1,7, GPIO, UART1, CTOUT, EMC, USB0, R, R, R, 0, ND);
-LPC_P(1,8, GPIO, UART1, CTOUT, EMC, R, R, R, SDMMC, 0, ND);
-LPC_P(1,9, GPIO, UART1, CTOUT, EMC, R, R, R, SDMMC, 0, ND);
-LPC_P(1,10, GPIO, UART1, CTOUT, EMC, R, R, R, SDMMC, 0, ND);
-LPC_P(1,11, GPIO, UART1, CTOUT, EMC, R, R, R, SDMMC, 0, ND);
-LPC_P(1,12, GPIO, UART1, R, EMC, TIMER0, R, SGPIO, SDMMC, 0, ND);
-LPC_P(1,13, GPIO, UART1, R, EMC, TIMER0, R, SGPIO, SDMMC, 0, ND);
-LPC_P(1,14, GPIO, UART1, R, EMC, TIMER0, R, SGPIO, R, 0, ND);
-LPC_P(1,15, GPIO, UART2, SGPIO, ENET, TIMER0, R, R, R, 0, ND);
-LPC_P(1,16, GPIO, UART2, SGPIO,ENET_ALT,TIMER0, R, R, ENET, 0, ND);
-LPC_P(1,17, GPIO, UART2, R, ENET, TIMER0, CAN1, SGPIO, R, 0, HD);
-LPC_P(1,18, GPIO, UART2, R, ENET, TIMER0, CAN1, SGPIO, R, 0, ND);
-LPC_P(1,19, ENET, SSP1, R, R, CLKOUT, R, I2S0_RX_MCLK,I2S1, 0, ND);
-LPC_P(1,20, GPIO, SSP1, R, ENET, TIMER0, R, SGPIO, R, 0, ND);
-LPC_P(2,0, SGPIO, UART0, EMC, USB0, GPIO, R, TIMER3, ENET, 0, ND);
-LPC_P(2,1, SGPIO, UART0, EMC, USB0, GPIO, R, TIMER3, R, 0, ND);
-LPC_P(2,2, SGPIO, UART0, EMC, USB0, GPIO, CTIN, TIMER3, R, 0, ND);
-LPC_P(2,3, SGPIO, I2C1, UART3, CTIN, GPIO, R, TIMER3, USB0, 0, HD);
-LPC_P(2,4, SGPIO, I2C1, UART3, CTIN, GPIO, R, TIMER3, USB0, 0, HD);
-LPC_P(2,5, SGPIO, CTIN, USB1, ADCTRIG, GPIO, R, TIMER3, USB0, 0, HD);
-LPC_P(2,6, SGPIO, UART0, EMC, USB0, GPIO, CTIN, TIMER3, R, 0, ND);
-LPC_P(2,7, GPIO, CTOUT, UART3, EMC, R, R, TIMER3, R, 0, ND);
-LPC_P(2,8, SGPIO, CTOUT, UART3, EMC, GPIO, R, R, R, 0, ND);
-LPC_P(2,9, GPIO, CTOUT, UART3, EMC, R, R, R, R, 0, ND);
-LPC_P(2,10, GPIO, CTOUT, UART2, EMC, R, R, R, R, 0, ND);
-LPC_P(2,11, GPIO, CTOUT, UART2, EMC, R, R, R, R, 0, ND);
-LPC_P(2,12, GPIO, CTOUT, R, EMC, R, R, R, UART2, 0, ND);
-LPC_P(2,13, GPIO, CTIN, R, EMC, R, R, R, UART2, 0, ND);
-LPC_P(3,0, I2S0_RX_SCK, I2S0_RX_MCLK, I2S0_TX_SCK, I2S0_TX_MCLK,SSP0,R,R,R, 0, ND);
-LPC_P(3,1, I2S0_TX_WS, I2S0_RX_WS,CAN0,USB1,GPIO, R, LCD, R, 0, ND);
-LPC_P(3,2, I2S0_TX_SDA, I2S0_RX_SDA,CAN0,USB1,GPIO, R, LCD, R, 0, ND);
-LPC_P(3,3, R, SPI, SSP0, SPIFI, CGU_OUT,R, I2S0_TX_MCLK, I2S1, 0, HS);
-LPC_P(3,4, GPIO, R, R, SPIFI, UART1, I2S0_TX_WS, I2S1, LCD, 0, ND);
-LPC_P(3,5, GPIO, R, R, SPIFI, UART1, I2S0_TX_SDA,I2S1, LCD, 0, ND);
-LPC_P(3,6, GPIO, SPI, SSP0, SPIFI, R, SSP0_ALT, R, R, 0, ND);
-LPC_P(3,7, R, SPI, SSP0, SPIFI, GPIO, SSP0_ALT, R, R, 0, ND);
-LPC_P(3,8, R, SPI, SSP0, SPIFI, GPIO, SSP0_ALT, R, R, 0, ND);
-LPC_P(4,0, GPIO, MCTRL, NMI, R, R, LCD, UART3, R, 0, ND);
-LPC_P(4,1, GPIO, CTOUT, LCD, R, R, LCD_ALT, UART3, ENET, ADC0|1, ND);
-LPC_P(4,2, GPIO, CTOUT, LCD, R, R, LCD_ALT, UART3, SGPIO, 0, ND);
-LPC_P(4,3, GPIO, CTOUT, LCD, R, R, LCD_ALT, UART3, SGPIO, ADC0|0, ND);
-LPC_P(4,4, GPIO, CTOUT, LCD, R, R, LCD_ALT, UART3, SGPIO, DAC, ND);
-LPC_P(4,5, GPIO, CTOUT, LCD, R, R, R, R, SGPIO, 0, ND);
-LPC_P(4,6, GPIO, CTOUT, LCD, R, R, R, R, SGPIO, 0, ND);
-LPC_P(4,7, LCD, CLKIN, R, R, R, R, I2S1,I2S0_TX_SCK, 0, ND);
-LPC_P(4,8, R, CTIN, LCD, R, GPIO, LCD_ALT, CAN1, SGPIO, 0, ND);
-LPC_P(4,9, R, CTIN, LCD, R, GPIO, LCD_ALT, CAN1, SGPIO, 0, ND);
-LPC_P(4,10, R, CTIN, LCD, R, GPIO, LCD_ALT, R, SGPIO, 0, ND);
-LPC_P(5,0, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
-LPC_P(5,1, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
-LPC_P(5,2, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
-LPC_P(5,3, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
-LPC_P(5,4, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
-LPC_P(5,5, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
-LPC_P(5,6, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
-LPC_P(5,7, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
-LPC_P(6,0, R, I2S0_RX_MCLK,R, R, I2S0_RX_SCK, R, R, R, 0, ND);
-LPC_P(6,1, GPIO, EMC, UART0, I2S0_RX_WS, R, TIMER2, R, R, 0, ND);
-LPC_P(6,2, GPIO, EMC, UART0, I2S0_RX_SDA, R, TIMER2, R, R, 0, ND);
-LPC_P(6,3, GPIO, USB0, SGPIO, EMC, R, TIMER2, R, R, 0, ND);
-LPC_P(6,4, GPIO, CTIN, UART0, EMC, R, R, R, R, 0, ND);
-LPC_P(6,5, GPIO, CTOUT, UART0, EMC, R, R, R, R, 0, ND);
-LPC_P(6,6, GPIO, EMC, SGPIO, USB0, R, TIMER2, R, R, 0, ND);
-LPC_P(6,7, R, EMC, SGPIO, USB0, GPIO, TIMER2, R, R, 0, ND);
-LPC_P(6,8, R, EMC, SGPIO, USB0, GPIO, TIMER2, R, R, 0, ND);
-LPC_P(6,9, GPIO, R, R, EMC, R, TIMER2, R, R, 0, ND);
-LPC_P(6,10, GPIO, MCTRL, R, EMC, R, R, R, R, 0, ND);
-LPC_P(6,11, GPIO, R, R, EMC, R, TIMER2, R, R, 0, ND);
-LPC_P(6,12, GPIO, CTOUT, R, EMC, R, R, R, R, 0, ND);
-LPC_P(7,0, GPIO, CTOUT, R, LCD, R, R, R, SGPIO, 0, ND);
-LPC_P(7,1, GPIO, CTOUT,I2S0_TX_WS,LCD,LCD_ALT, R, UART2, SGPIO, 0, ND);
-LPC_P(7,2, GPIO, CTIN,I2S0_TX_SDA,LCD,LCD_ALT, R, UART2, SGPIO, 0, ND);
-LPC_P(7,3, GPIO, CTIN, R, LCD,LCD_ALT, R, R, R, 0, ND);
-LPC_P(7,4, GPIO, CTOUT, R, LCD,LCD_ALT, TRACE, R, R, ADC0|4, ND);
-LPC_P(7,5, GPIO, CTOUT, R, LCD,LCD_ALT, TRACE, R, R, ADC0|3, ND);
-LPC_P(7,6, GPIO, CTOUT, R, LCD, R, TRACE, R, R, 0, ND);
-LPC_P(7,7, GPIO, CTOUT, R, LCD, R, TRACE, ENET, SGPIO, ADC1|6, ND);
-LPC_P(8,0, GPIO, USB0, R, MCTRL, SGPIO, R, R, TIMER0, 0, HD);
-LPC_P(8,1, GPIO, USB0, R, MCTRL, SGPIO, R, R, TIMER0, 0, HD);
-LPC_P(8,2, GPIO, USB0, R, MCTRL, SGPIO, R, R, TIMER0, 0, HD);
-LPC_P(8,3, GPIO, USB1, R, LCD, LCD_ALT, R, R, TIMER0, 0, ND);
-LPC_P(8,4, GPIO, USB1, R, LCD, LCD_ALT, R, R, TIMER0, 0, ND);
-LPC_P(8,5, GPIO, USB1, R, LCD, LCD_ALT, R, R, TIMER0, 0, ND);
-LPC_P(8,6, GPIO, USB1, R, LCD, LCD_ALT, R, R, TIMER0, 0, ND);
-LPC_P(8,7, GPIO, USB1, R, LCD, LCD_ALT, R, R, TIMER0, 0, ND);
-LPC_P(8,8, R, USB1, R, R, R, R,CGU_OUT, I2S1, 0, ND);
-LPC_P(9,0, GPIO, MCTRL, R, R, R, ENET, SGPIO, SSP0, 0, ND);
-LPC_P(9,1, GPIO, MCTRL, R, R, I2S0_TX_WS,ENET, SGPIO, SSP0, 0, ND);
-LPC_P(9,2, GPIO, MCTRL, R, R, I2S0_TX_SDA,ENET,SGPIO, SSP0, 0, ND);
-LPC_P(9,3, GPIO, MCTRL, USB1, R, R, ENET, SGPIO, UART3, 0, ND);
-LPC_P(9,4, R, MCTRL, USB1, R, GPIO, ENET, SGPIO, UART3, 0, ND);
-LPC_P(9,5, R, MCTRL, USB1, R, GPIO, ENET, SGPIO, UART0, 0, ND);
-LPC_P(9,6, GPIO, MCTRL, USB1, R, R, ENET, SGPIO, UART0, 0, ND);
-LPC_P(a,0, R, R, R, R, R, I2S1, CGU_OUT, R, 0, ND);
-LPC_P(a,1, GPIO, QEI, R, UART2, R, R, R, R, 0, HD);
-LPC_P(a,2, GPIO, QEI, R, UART2, R, R, R, R, 0, HD);
-LPC_P(a,3, GPIO, QEI, R, R, R, R, R, R, 0, HD);
-LPC_P(a,4, R, CTOUT, R, EMC, GPIO, R, R, R, 0, ND);
-LPC_P(b,0, R, CTOUT, LCD, R, GPIO, R, R, R, 0, ND);
-LPC_P(b,1, R, USB1, LCD, R, GPIO, CTOUT, R, R, 0, ND);
-LPC_P(b,2, R, USB1, LCD, R, GPIO, CTOUT, R, R, 0, ND);
-LPC_P(b,3, R, USB1, LCD, R, GPIO, CTOUT, R, R, 0, ND);
-LPC_P(b,4, R, USB1, LCD, R, GPIO, CTIN, R, R, 0, ND);
-LPC_P(b,5, R, USB1, LCD, R, GPIO, CTIN, LCD_ALT, R, 0, ND);
-LPC_P(b,6, R, USB1, LCD, R, GPIO, CTIN, LCD_ALT, R, ADC0|6, ND);
-LPC_P(c,0, R, USB1, R, ENET, LCD, R, R, SDMMC, ADC1|1, ND);
-LPC_P(c,1, USB1, R, UART1, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
-LPC_P(c,2, USB1, R, UART1, ENET, GPIO, R, R, SDMMC, 0, ND);
-LPC_P(c,3, USB1, R, UART1, ENET, GPIO, R, R, SDMMC, ADC1|0, ND);
-LPC_P(c,4, R, USB1, R, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
-LPC_P(c,5, R, USB1, R, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
-LPC_P(c,6, R, USB1, R, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
-LPC_P(c,7, R, USB1, R, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
-LPC_P(c,8, R, USB1, R, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
-LPC_P(c,9, R, USB1, R, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
-LPC_P(c,10, R, USB1, UART1, R, GPIO, R, TIMER3, SDMMC, 0, ND);
-LPC_P(c,11, R, USB1, UART1, R, GPIO, R, R, SDMMC, 0, ND);
-LPC_P(c,12, R, R, UART1, R, GPIO, SGPIO, I2S0_TX_SDA,SDMMC, 0, ND);
-LPC_P(c,13, R, R, UART1, R, GPIO, SGPIO, I2S0_TX_WS, SDMMC, 0, ND);
-LPC_P(c,14, R, R, UART1, R, GPIO, SGPIO, ENET, SDMMC, 0, ND);
-LPC_P(d,0, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
-LPC_P(d,1, R, R, EMC, R, GPIO, SDMMC, R, SGPIO, 0, ND);
-LPC_P(d,2, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
-LPC_P(d,3, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
-LPC_P(d,4, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
-LPC_P(d,5, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
-LPC_P(d,6, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
-LPC_P(d,7, R, CTIN, EMC, R, GPIO, R, R, SGPIO, 0, ND);
-LPC_P(d,8, R, CTIN, EMC, R, GPIO, R, R, SGPIO, 0, ND);
-LPC_P(d,9, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
-LPC_P(d,10, R, CTIN, EMC, R, GPIO, R, R, R, 0, ND);
-LPC_P(d,11, R, R, EMC, R, GPIO, USB1, CTOUT, R, 0, ND);
-LPC_P(d,12, R, R, EMC, R, GPIO, R, CTOUT, R, 0, ND);
-LPC_P(d,13, R, CTIN, EMC, R, GPIO, R, CTOUT, R, 0, ND);
-LPC_P(d,14, R, R, EMC, R, GPIO, R, CTOUT, R, 0, ND);
-LPC_P(d,15, R, R, EMC, R, GPIO, SDMMC, CTOUT, R, 0, ND);
-LPC_P(d,16, R, R, EMC, R, GPIO, SDMMC, CTOUT, R, 0, ND);
-LPC_P(e,0, R, R, R, EMC, GPIO, CAN1, R, R, 0, ND);
-LPC_P(e,1, R, R, R, EMC, GPIO, CAN1, R, R, 0, ND);
-LPC_P(e,2,ADCTRIG, CAN0, R, EMC, GPIO, R, R, R, 0, ND);
-LPC_P(e,3, R, CAN0,ADCTRIG, EMC, GPIO, R, R, R, 0, ND);
-LPC_P(e,4, R, NMI, R, EMC, GPIO, R, R, R, 0, ND);
-LPC_P(e,5, R, CTOUT, UART1, EMC, GPIO, R, R, R, 0, ND);
-LPC_P(e,6, R, CTOUT, UART1, EMC, GPIO, R, R, R, 0, ND);
-LPC_P(e,7, R, CTOUT, UART1, EMC, GPIO, R, R, R, 0, ND);
-LPC_P(e,8, R, CTOUT, UART1, EMC, GPIO, R, R, R, 0, ND);
-LPC_P(e,9, R, CTIN, UART1, EMC, GPIO, R, R, R, 0, ND);
-LPC_P(e,10, R, CTIN, UART1, EMC, GPIO, R, R, R, 0, ND);
-LPC_P(e,11, R, CTOUT, UART1, EMC, GPIO, R, R, R, 0, ND);
-LPC_P(e,12, R, CTOUT, UART1, EMC, GPIO, R, R, R, 0, ND);
-LPC_P(e,13, R, CTOUT, I2C1, EMC, GPIO, R, R, R, 0, ND);
-LPC_P(e,14, R, R, R, EMC, GPIO, R, R, R, 0, ND);
-LPC_P(e,15, R, CTOUT, I2C1, EMC, GPIO, R, R, R, 0, ND);
-LPC_P(f,0, SSP0, CLKIN, R, R, R, R, R, I2S1, 0, ND);
-LPC_P(f,1, R, R, SSP0, R, GPIO, R, SGPIO, R, 0, ND);
-LPC_P(f,2, R, UART3, SSP0, R, GPIO, R, SGPIO, R, 0, ND);
-LPC_P(f,3, R, UART3, SSP0, R, GPIO, R, SGPIO, R, 0, ND);
-LPC_P(f,4, SSP1, CLKIN, TRACE, R, R, R, I2S0_TX_MCLK,I2S0_RX_SCK, 0, ND);
-LPC_P(f,5, R, UART3, SSP1, TRACE, GPIO, R, SGPIO, R, ADC1|4, ND);
-LPC_P(f,6, R, UART3, SSP1, TRACE, GPIO, R, SGPIO, I2S1, ADC1|3, ND);
-LPC_P(f,7, R, UART3, SSP1, TRACE, GPIO, R, SGPIO, I2S1, ADC1|7, ND);
-LPC_P(f,8, R, UART0, CTIN, TRACE, GPIO, R, SGPIO, R, ADC0|2, ND);
-LPC_P(f,9, R, UART0, CTOUT, R, GPIO, R, SGPIO, R, ADC1|2, ND);
-LPC_P(f,10, R, UART0, R, R, GPIO, R, SDMMC, R, ADC0|5, ND);
-LPC_P(f,11, R, UART0, R, R, GPIO, R, SDMMC, R, ADC1|5, ND);
-
-/* Pin Offset FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 ANALOG TYPE */
-LPC_N(clk0, 0xc00, EMC, CLKOUT, R, R, SDMMC, EMC_ALT, SSP1, ENET, 0, HS);
-LPC_N(clk1, 0xc04, EMC, CLKOUT, R, R, R, CGU_OUT, R, I2S1, 0, HS);
-LPC_N(clk2, 0xc08, EMC, CLKOUT, R, R, SDMMC, EMC_ALT,I2S0_TX_MCLK,I2S1, 0, HS);
-LPC_N(clk3, 0xc0c, EMC, CLKOUT, R, R, R, CGU_OUT, R, I2S1, 0, HS);
-LPC_N(usb1_dm, 0xc80, R, R, R, R, R, R, R, R, 0, USB1);
-LPC_N(usb1_dp, 0xc80, R, R, R, R, R, R, R, R, 0, USB1);
-LPC_N(i2c0_scl, 0xc84, R, R, R, R, R, R, R, R, 0, I2C0);
-LPC_N(i2c0_sda, 0xc84, R, R, R, R, R, R, R, R, 0, I2C0);
-
-#define LPC18XX_PIN_P(port, pin) { \
- .number = 0x##port * 32 + pin, \
- .name = "p"#port"_"#pin, \
- .drv_data = &lpc18xx_pin_p##port##_##pin \
-}
-
-/* Pin numbers for special pins */
-enum {
- PIN_CLK0 = 600,
- PIN_CLK1,
- PIN_CLK2,
- PIN_CLK3,
- PIN_USB1_DM,
- PIN_USB1_DP,
- PIN_I2C0_SCL,
- PIN_I2C0_SDA,
-};
-
-#define LPC18XX_PIN(pname, n) { \
- .number = n, \
- .name = #pname, \
- .drv_data = &lpc18xx_pin_##pname \
-}
-
-static const struct pinctrl_pin_desc lpc18xx_pins[] = {
- LPC18XX_PIN_P(0,0),
- LPC18XX_PIN_P(0,1),
- LPC18XX_PIN_P(1,0),
- LPC18XX_PIN_P(1,1),
- LPC18XX_PIN_P(1,2),
- LPC18XX_PIN_P(1,3),
- LPC18XX_PIN_P(1,4),
- LPC18XX_PIN_P(1,5),
- LPC18XX_PIN_P(1,6),
- LPC18XX_PIN_P(1,7),
- LPC18XX_PIN_P(1,8),
- LPC18XX_PIN_P(1,9),
- LPC18XX_PIN_P(1,10),
- LPC18XX_PIN_P(1,11),
- LPC18XX_PIN_P(1,12),
- LPC18XX_PIN_P(1,13),
- LPC18XX_PIN_P(1,14),
- LPC18XX_PIN_P(1,15),
- LPC18XX_PIN_P(1,16),
- LPC18XX_PIN_P(1,17),
- LPC18XX_PIN_P(1,18),
- LPC18XX_PIN_P(1,19),
- LPC18XX_PIN_P(1,20),
- LPC18XX_PIN_P(2,0),
- LPC18XX_PIN_P(2,1),
- LPC18XX_PIN_P(2,2),
- LPC18XX_PIN_P(2,3),
- LPC18XX_PIN_P(2,4),
- LPC18XX_PIN_P(2,5),
- LPC18XX_PIN_P(2,6),
- LPC18XX_PIN_P(2,7),
- LPC18XX_PIN_P(2,8),
- LPC18XX_PIN_P(2,9),
- LPC18XX_PIN_P(2,10),
- LPC18XX_PIN_P(2,11),
- LPC18XX_PIN_P(2,12),
- LPC18XX_PIN_P(2,13),
- LPC18XX_PIN_P(3,0),
- LPC18XX_PIN_P(3,1),
- LPC18XX_PIN_P(3,2),
- LPC18XX_PIN_P(3,3),
- LPC18XX_PIN_P(3,4),
- LPC18XX_PIN_P(3,5),
- LPC18XX_PIN_P(3,6),
- LPC18XX_PIN_P(3,7),
- LPC18XX_PIN_P(3,8),
- LPC18XX_PIN_P(4,0),
- LPC18XX_PIN_P(4,1),
- LPC18XX_PIN_P(4,2),
- LPC18XX_PIN_P(4,3),
- LPC18XX_PIN_P(4,4),
- LPC18XX_PIN_P(4,5),
- LPC18XX_PIN_P(4,6),
- LPC18XX_PIN_P(4,7),
- LPC18XX_PIN_P(4,8),
- LPC18XX_PIN_P(4,9),
- LPC18XX_PIN_P(4,10),
- LPC18XX_PIN_P(5,0),
- LPC18XX_PIN_P(5,1),
- LPC18XX_PIN_P(5,2),
- LPC18XX_PIN_P(5,3),
- LPC18XX_PIN_P(5,4),
- LPC18XX_PIN_P(5,5),
- LPC18XX_PIN_P(5,6),
- LPC18XX_PIN_P(5,7),
- LPC18XX_PIN_P(6,0),
- LPC18XX_PIN_P(6,1),
- LPC18XX_PIN_P(6,2),
- LPC18XX_PIN_P(6,3),
- LPC18XX_PIN_P(6,4),
- LPC18XX_PIN_P(6,5),
- LPC18XX_PIN_P(6,6),
- LPC18XX_PIN_P(6,7),
- LPC18XX_PIN_P(6,8),
- LPC18XX_PIN_P(6,9),
- LPC18XX_PIN_P(6,10),
- LPC18XX_PIN_P(6,11),
- LPC18XX_PIN_P(6,12),
- LPC18XX_PIN_P(7,0),
- LPC18XX_PIN_P(7,1),
- LPC18XX_PIN_P(7,2),
- LPC18XX_PIN_P(7,3),
- LPC18XX_PIN_P(7,4),
- LPC18XX_PIN_P(7,5),
- LPC18XX_PIN_P(7,6),
- LPC18XX_PIN_P(7,7),
- LPC18XX_PIN_P(8,0),
- LPC18XX_PIN_P(8,1),
- LPC18XX_PIN_P(8,2),
- LPC18XX_PIN_P(8,3),
- LPC18XX_PIN_P(8,4),
- LPC18XX_PIN_P(8,5),
- LPC18XX_PIN_P(8,6),
- LPC18XX_PIN_P(8,7),
- LPC18XX_PIN_P(8,8),
- LPC18XX_PIN_P(9,0),
- LPC18XX_PIN_P(9,1),
- LPC18XX_PIN_P(9,2),
- LPC18XX_PIN_P(9,3),
- LPC18XX_PIN_P(9,4),
- LPC18XX_PIN_P(9,5),
- LPC18XX_PIN_P(9,6),
- LPC18XX_PIN_P(a,0),
- LPC18XX_PIN_P(a,1),
- LPC18XX_PIN_P(a,2),
- LPC18XX_PIN_P(a,3),
- LPC18XX_PIN_P(a,4),
- LPC18XX_PIN_P(b,0),
- LPC18XX_PIN_P(b,1),
- LPC18XX_PIN_P(b,2),
- LPC18XX_PIN_P(b,3),
- LPC18XX_PIN_P(b,4),
- LPC18XX_PIN_P(b,5),
- LPC18XX_PIN_P(b,6),
- LPC18XX_PIN_P(c,0),
- LPC18XX_PIN_P(c,1),
- LPC18XX_PIN_P(c,2),
- LPC18XX_PIN_P(c,3),
- LPC18XX_PIN_P(c,4),
- LPC18XX_PIN_P(c,5),
- LPC18XX_PIN_P(c,6),
- LPC18XX_PIN_P(c,7),
- LPC18XX_PIN_P(c,8),
- LPC18XX_PIN_P(c,9),
- LPC18XX_PIN_P(c,10),
- LPC18XX_PIN_P(c,11),
- LPC18XX_PIN_P(c,12),
- LPC18XX_PIN_P(c,13),
- LPC18XX_PIN_P(c,14),
- LPC18XX_PIN_P(d,0),
- LPC18XX_PIN_P(d,1),
- LPC18XX_PIN_P(d,2),
- LPC18XX_PIN_P(d,3),
- LPC18XX_PIN_P(d,4),
- LPC18XX_PIN_P(d,5),
- LPC18XX_PIN_P(d,6),
- LPC18XX_PIN_P(d,7),
- LPC18XX_PIN_P(d,8),
- LPC18XX_PIN_P(d,9),
- LPC18XX_PIN_P(d,10),
- LPC18XX_PIN_P(d,11),
- LPC18XX_PIN_P(d,12),
- LPC18XX_PIN_P(d,13),
- LPC18XX_PIN_P(d,14),
- LPC18XX_PIN_P(d,15),
- LPC18XX_PIN_P(d,16),
- LPC18XX_PIN_P(e,0),
- LPC18XX_PIN_P(e,1),
- LPC18XX_PIN_P(e,2),
- LPC18XX_PIN_P(e,3),
- LPC18XX_PIN_P(e,4),
- LPC18XX_PIN_P(e,5),
- LPC18XX_PIN_P(e,6),
- LPC18XX_PIN_P(e,7),
- LPC18XX_PIN_P(e,8),
- LPC18XX_PIN_P(e,9),
- LPC18XX_PIN_P(e,10),
- LPC18XX_PIN_P(e,11),
- LPC18XX_PIN_P(e,12),
- LPC18XX_PIN_P(e,13),
- LPC18XX_PIN_P(e,14),
- LPC18XX_PIN_P(e,15),
- LPC18XX_PIN_P(f,0),
- LPC18XX_PIN_P(f,1),
- LPC18XX_PIN_P(f,2),
- LPC18XX_PIN_P(f,3),
- LPC18XX_PIN_P(f,4),
- LPC18XX_PIN_P(f,5),
- LPC18XX_PIN_P(f,6),
- LPC18XX_PIN_P(f,7),
- LPC18XX_PIN_P(f,8),
- LPC18XX_PIN_P(f,9),
- LPC18XX_PIN_P(f,10),
- LPC18XX_PIN_P(f,11),
-
- LPC18XX_PIN(clk0, PIN_CLK0),
- LPC18XX_PIN(clk1, PIN_CLK1),
- LPC18XX_PIN(clk2, PIN_CLK2),
- LPC18XX_PIN(clk3, PIN_CLK3),
- LPC18XX_PIN(usb1_dm, PIN_USB1_DM),
- LPC18XX_PIN(usb1_dp, PIN_USB1_DP),
- LPC18XX_PIN(i2c0_scl, PIN_I2C0_SCL),
- LPC18XX_PIN(i2c0_sda, PIN_I2C0_SDA),
-};
-
-/* PIN_CONFIG_GPIO_PIN_INT: route gpio to the gpio pin interrupt controller */
-#define PIN_CONFIG_GPIO_PIN_INT (PIN_CONFIG_END + 1)
-
-static const struct pinconf_generic_params lpc18xx_params[] = {
- {"nxp,gpio-pin-interrupt", PIN_CONFIG_GPIO_PIN_INT, 0},
-};
-
-#ifdef CONFIG_DEBUG_FS
-static const struct pin_config_item lpc18xx_conf_items[ARRAY_SIZE(lpc18xx_params)] = {
- PCONFDUMP(PIN_CONFIG_GPIO_PIN_INT, "gpio pin int", NULL, true),
-};
-#endif
-
-static int lpc18xx_pconf_get_usb1(enum pin_config_param param, int *arg, u32 reg)
-{
- switch (param) {
- case PIN_CONFIG_MODE_LOW_POWER:
- if (reg & LPC18XX_SCU_USB1_EPWR)
- *arg = 0;
- else
- *arg = 1;
- break;
-
- case PIN_CONFIG_BIAS_DISABLE:
- if (reg & LPC18XX_SCU_USB1_EPD)
- return -EINVAL;
- break;
-
- case PIN_CONFIG_BIAS_PULL_DOWN:
- if (reg & LPC18XX_SCU_USB1_EPD)
- *arg = 1;
- else
- return -EINVAL;
- break;
-
- default:
- return -ENOTSUPP;
- }
-
- return 0;
-}
-
-static int lpc18xx_pconf_get_i2c0(enum pin_config_param param, int *arg, u32 reg,
- unsigned pin)
-{
- u8 shift;
-
- if (pin == PIN_I2C0_SCL)
- shift = LPC18XX_SCU_I2C0_SCL_SHIFT;
- else
- shift = LPC18XX_SCU_I2C0_SDA_SHIFT;
-
- switch (param) {
- case PIN_CONFIG_INPUT_ENABLE:
- if (reg & (LPC18XX_SCU_I2C0_EZI << shift))
- *arg = 1;
- else
- return -EINVAL;
- break;
-
- case PIN_CONFIG_SLEW_RATE:
- if (reg & (LPC18XX_SCU_I2C0_EHD << shift))
- *arg = 1;
- else
- *arg = 0;
- break;
-
- case PIN_CONFIG_INPUT_SCHMITT:
- if (reg & (LPC18XX_SCU_I2C0_EFP << shift))
- *arg = 3;
- else
- *arg = 50;
- break;
-
- case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
- if (reg & (LPC18XX_SCU_I2C0_ZIF << shift))
- return -EINVAL;
- else
- *arg = 1;
- break;
-
- default:
- return -ENOTSUPP;
- }
-
- return 0;
-}
-
-static int lpc18xx_pin_to_gpio(struct pinctrl_dev *pctldev, unsigned pin)
-{
- struct pinctrl_gpio_range *range;
-
- range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
- if (!range)
- return -EINVAL;
-
- return pin - range->pin_base + range->base;
-}
-
-static int lpc18xx_get_pintsel(void __iomem *addr, u32 val, int *arg)
-{
- u32 reg_val;
- int i;
-
- reg_val = readl(addr);
- for (i = 0; i < LPC18XX_SCU_IRQ_PER_PINTSEL; i++) {
- if ((reg_val & LPC18XX_SCU_PINTSEL_VAL_MASK) == val)
- return 0;
-
- reg_val >>= BITS_PER_BYTE;
- *arg += 1;
- }
-
- return -EINVAL;
-}
-
-static u32 lpc18xx_gpio_to_pintsel_val(int gpio)
-{
- unsigned int gpio_port, gpio_pin;
-
- gpio_port = gpio / LPC18XX_GPIO_PINS_PER_PORT;
- gpio_pin = gpio % LPC18XX_GPIO_PINS_PER_PORT;
-
- return gpio_pin | (gpio_port << LPC18XX_SCU_PINTSEL_PORT_SHIFT);
-}
-
-static int lpc18xx_pconf_get_gpio_pin_int(struct pinctrl_dev *pctldev,
- int *arg, unsigned pin)
-{
- struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
- int gpio, ret;
- u32 val;
-
- gpio = lpc18xx_pin_to_gpio(pctldev, pin);
- if (gpio < 0)
- return -ENOTSUPP;
-
- val = lpc18xx_gpio_to_pintsel_val(gpio);
-
- /*
- * Check if this pin has been enabled as a interrupt in any of the two
- * PINTSEL registers. *arg indicates which interrupt number (0-7).
- */
- *arg = 0;
- ret = lpc18xx_get_pintsel(scu->base + LPC18XX_SCU_PINTSEL0, val, arg);
- if (ret == 0)
- return ret;
-
- return lpc18xx_get_pintsel(scu->base + LPC18XX_SCU_PINTSEL1, val, arg);
-}
-
-static int lpc18xx_pconf_get_pin(struct pinctrl_dev *pctldev, unsigned param,
- int *arg, u32 reg, unsigned pin,
- struct lpc18xx_pin_caps *pin_cap)
-{
- switch (param) {
- case PIN_CONFIG_BIAS_DISABLE:
- if ((!(reg & LPC18XX_SCU_PIN_EPD)) && (reg & LPC18XX_SCU_PIN_EPUN))
- ;
- else
- return -EINVAL;
- break;
-
- case PIN_CONFIG_BIAS_PULL_UP:
- if (reg & LPC18XX_SCU_PIN_EPUN)
- return -EINVAL;
- else
- *arg = 1;
- break;
-
- case PIN_CONFIG_BIAS_PULL_DOWN:
- if (reg & LPC18XX_SCU_PIN_EPD)
- *arg = 1;
- else
- return -EINVAL;
- break;
-
- case PIN_CONFIG_INPUT_ENABLE:
- if (reg & LPC18XX_SCU_PIN_EZI)
- *arg = 1;
- else
- return -EINVAL;
- break;
-
- case PIN_CONFIG_SLEW_RATE:
- if (pin_cap->type == TYPE_HD)
- return -ENOTSUPP;
-
- if (reg & LPC18XX_SCU_PIN_EHS)
- *arg = 1;
- else
- *arg = 0;
- break;
-
- case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
- if (reg & LPC18XX_SCU_PIN_ZIF)
- return -EINVAL;
- else
- *arg = 1;
- break;
-
- case PIN_CONFIG_DRIVE_STRENGTH:
- if (pin_cap->type != TYPE_HD)
- return -ENOTSUPP;
-
- *arg = (reg & LPC18XX_SCU_PIN_EHD_MASK) >> LPC18XX_SCU_PIN_EHD_POS;
- switch (*arg) {
- case 3: *arg += 5;
- fallthrough;
- case 2: *arg += 5;
- fallthrough;
- case 1: *arg += 3;
- fallthrough;
- case 0: *arg += 4;
- }
- break;
-
- case PIN_CONFIG_GPIO_PIN_INT:
- return lpc18xx_pconf_get_gpio_pin_int(pctldev, arg, pin);
-
- default:
- return -ENOTSUPP;
- }
-
- return 0;
-}
-
-static struct lpc18xx_pin_caps *lpc18xx_get_pin_caps(unsigned pin)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(lpc18xx_pins); i++) {
- if (lpc18xx_pins[i].number == pin)
- return lpc18xx_pins[i].drv_data;
- }
-
- return NULL;
-}
-
-static int lpc18xx_pconf_get(struct pinctrl_dev *pctldev, unsigned pin,
- unsigned long *config)
-{
- struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
- enum pin_config_param param = pinconf_to_config_param(*config);
- struct lpc18xx_pin_caps *pin_cap;
- int ret, arg = 0;
- u32 reg;
-
- pin_cap = lpc18xx_get_pin_caps(pin);
- if (!pin_cap)
- return -EINVAL;
-
- reg = readl(scu->base + pin_cap->offset);
-
- if (pin_cap->type == TYPE_I2C0)
- ret = lpc18xx_pconf_get_i2c0(param, &arg, reg, pin);
- else if (pin_cap->type == TYPE_USB1)
- ret = lpc18xx_pconf_get_usb1(param, &arg, reg);
- else
- ret = lpc18xx_pconf_get_pin(pctldev, param, &arg, reg, pin, pin_cap);
-
- if (ret < 0)
- return ret;
-
- *config = pinconf_to_config_packed(param, (u16)arg);
-
- return 0;
-}
-
-static int lpc18xx_pconf_set_usb1(struct pinctrl_dev *pctldev,
- enum pin_config_param param,
- u32 param_val, u32 *reg)
-{
- switch (param) {
- case PIN_CONFIG_MODE_LOW_POWER:
- if (param_val)
- *reg &= ~LPC18XX_SCU_USB1_EPWR;
- else
- *reg |= LPC18XX_SCU_USB1_EPWR;
- break;
-
- case PIN_CONFIG_BIAS_DISABLE:
- *reg &= ~LPC18XX_SCU_USB1_EPD;
- break;
-
- case PIN_CONFIG_BIAS_PULL_DOWN:
- *reg |= LPC18XX_SCU_USB1_EPD;
- break;
-
- default:
- dev_err(pctldev->dev, "Property not supported\n");
- return -ENOTSUPP;
- }
-
- return 0;
-}
-
-static int lpc18xx_pconf_set_i2c0(struct pinctrl_dev *pctldev,
- enum pin_config_param param,
- u32 param_val, u32 *reg,
- unsigned pin)
-{
- u8 shift;
-
- if (pin == PIN_I2C0_SCL)
- shift = LPC18XX_SCU_I2C0_SCL_SHIFT;
- else
- shift = LPC18XX_SCU_I2C0_SDA_SHIFT;
-
- switch (param) {
- case PIN_CONFIG_INPUT_ENABLE:
- if (param_val)
- *reg |= (LPC18XX_SCU_I2C0_EZI << shift);
- else
- *reg &= ~(LPC18XX_SCU_I2C0_EZI << shift);
- break;
-
- case PIN_CONFIG_SLEW_RATE:
- if (param_val)
- *reg |= (LPC18XX_SCU_I2C0_EHD << shift);
- else
- *reg &= ~(LPC18XX_SCU_I2C0_EHD << shift);
- break;
-
- case PIN_CONFIG_INPUT_SCHMITT:
- if (param_val == 3)
- *reg |= (LPC18XX_SCU_I2C0_EFP << shift);
- else if (param_val == 50)
- *reg &= ~(LPC18XX_SCU_I2C0_EFP << shift);
- else
- return -ENOTSUPP;
- break;
-
- case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
- if (param_val)
- *reg &= ~(LPC18XX_SCU_I2C0_ZIF << shift);
- else
- *reg |= (LPC18XX_SCU_I2C0_ZIF << shift);
- break;
-
- default:
- dev_err(pctldev->dev, "Property not supported\n");
- return -ENOTSUPP;
- }
-
- return 0;
-}
-
-static int lpc18xx_pconf_set_gpio_pin_int(struct pinctrl_dev *pctldev,
- u32 param_val, unsigned pin)
-{
- struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
- u32 val, reg_val, reg_offset = LPC18XX_SCU_PINTSEL0;
- int gpio;
-
- if (param_val >= LPC18XX_GPIO_PIN_INT_MAX)
- return -EINVAL;
-
- gpio = lpc18xx_pin_to_gpio(pctldev, pin);
- if (gpio < 0)
- return -ENOTSUPP;
-
- val = lpc18xx_gpio_to_pintsel_val(gpio);
-
- reg_offset += (param_val / LPC18XX_SCU_IRQ_PER_PINTSEL) * sizeof(u32);
-
- reg_val = readl(scu->base + reg_offset);
- reg_val &= ~LPC18XX_SCU_PINTSEL_VAL(LPC18XX_SCU_PINTSEL_VAL_MASK, param_val);
- reg_val |= LPC18XX_SCU_PINTSEL_VAL(val, param_val);
- writel(reg_val, scu->base + reg_offset);
-
- return 0;
-}
-
-static int lpc18xx_pconf_set_pin(struct pinctrl_dev *pctldev, unsigned param,
- u32 param_val, u32 *reg, unsigned pin,
- struct lpc18xx_pin_caps *pin_cap)
-{
- switch (param) {
- case PIN_CONFIG_BIAS_DISABLE:
- *reg &= ~LPC18XX_SCU_PIN_EPD;
- *reg |= LPC18XX_SCU_PIN_EPUN;
- break;
-
- case PIN_CONFIG_BIAS_PULL_UP:
- *reg &= ~LPC18XX_SCU_PIN_EPUN;
- break;
-
- case PIN_CONFIG_BIAS_PULL_DOWN:
- *reg |= LPC18XX_SCU_PIN_EPD;
- break;
-
- case PIN_CONFIG_INPUT_ENABLE:
- if (param_val)
- *reg |= LPC18XX_SCU_PIN_EZI;
- else
- *reg &= ~LPC18XX_SCU_PIN_EZI;
- break;
-
- case PIN_CONFIG_SLEW_RATE:
- if (pin_cap->type == TYPE_HD) {
- dev_err(pctldev->dev, "Slew rate unsupported on high-drive pins\n");
- return -ENOTSUPP;
- }
-
- if (param_val == 0)
- *reg &= ~LPC18XX_SCU_PIN_EHS;
- else
- *reg |= LPC18XX_SCU_PIN_EHS;
- break;
-
- case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
- if (param_val)
- *reg &= ~LPC18XX_SCU_PIN_ZIF;
- else
- *reg |= LPC18XX_SCU_PIN_ZIF;
- break;
-
- case PIN_CONFIG_DRIVE_STRENGTH:
- if (pin_cap->type != TYPE_HD) {
- dev_err(pctldev->dev, "Drive strength available only on high-drive pins\n");
- return -ENOTSUPP;
- }
- *reg &= ~LPC18XX_SCU_PIN_EHD_MASK;
-
- switch (param_val) {
- case 20: param_val -= 5;
- fallthrough;
- case 14: param_val -= 5;
- fallthrough;
- case 8: param_val -= 3;
- fallthrough;
- case 4: param_val -= 4;
- break;
- default:
- dev_err(pctldev->dev, "Drive strength %u unsupported\n", param_val);
- return -ENOTSUPP;
- }
- *reg |= param_val << LPC18XX_SCU_PIN_EHD_POS;
- break;
-
- case PIN_CONFIG_GPIO_PIN_INT:
- return lpc18xx_pconf_set_gpio_pin_int(pctldev, param_val, pin);
-
- default:
- dev_err(pctldev->dev, "Property not supported\n");
- return -ENOTSUPP;
- }
-
- return 0;
-}
-
-static int lpc18xx_pconf_set(struct pinctrl_dev *pctldev, unsigned pin,
- unsigned long *configs, unsigned num_configs)
-{
- struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
- struct lpc18xx_pin_caps *pin_cap;
- enum pin_config_param param;
- u32 param_val;
- u32 reg;
- int ret;
- int i;
-
- pin_cap = lpc18xx_get_pin_caps(pin);
- if (!pin_cap)
- return -EINVAL;
-
- reg = readl(scu->base + pin_cap->offset);
-
- for (i = 0; i < num_configs; i++) {
- param = pinconf_to_config_param(configs[i]);
- param_val = pinconf_to_config_argument(configs[i]);
-
- if (pin_cap->type == TYPE_I2C0)
- ret = lpc18xx_pconf_set_i2c0(pctldev, param, param_val, ®, pin);
- else if (pin_cap->type == TYPE_USB1)
- ret = lpc18xx_pconf_set_usb1(pctldev, param, param_val, ®);
- else
- ret = lpc18xx_pconf_set_pin(pctldev, param, param_val, ®, pin, pin_cap);
-
- if (ret)
- return ret;
- }
-
- writel(reg, scu->base + pin_cap->offset);
-
- return 0;
-}
-
-static const struct pinconf_ops lpc18xx_pconf_ops = {
- .is_generic = true,
- .pin_config_get = lpc18xx_pconf_get,
- .pin_config_set = lpc18xx_pconf_set,
-};
-
-static int lpc18xx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
-{
- return ARRAY_SIZE(lpc18xx_function_names);
-}
-
-static const char *lpc18xx_pmx_get_func_name(struct pinctrl_dev *pctldev,
- unsigned function)
-{
- return lpc18xx_function_names[function];
-}
-
-static int lpc18xx_pmx_get_func_groups(struct pinctrl_dev *pctldev,
- unsigned function,
- const char *const **groups,
- unsigned *const num_groups)
-{
- struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
-
- *groups = scu->func[function].groups;
- *num_groups = scu->func[function].ngroups;
-
- return 0;
-}
-
-static int lpc18xx_pmx_set(struct pinctrl_dev *pctldev, unsigned function,
- unsigned group)
-{
- struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
- struct lpc18xx_pin_caps *pin = lpc18xx_pins[group].drv_data;
- int func;
- u32 reg;
-
- /* Dedicated USB1 and I2C0 pins doesn't support muxing */
- if (pin->type == TYPE_USB1) {
- if (function == FUNC_USB1)
- return 0;
-
- goto fail;
- }
-
- if (pin->type == TYPE_I2C0) {
- if (function == FUNC_I2C0)
- return 0;
-
- goto fail;
- }
-
- if (function == FUNC_ADC && (pin->analog & LPC18XX_ANALOG_PIN)) {
- u32 offset;
-
- writel(LPC18XX_SCU_ANALOG_PIN_CFG, scu->base + pin->offset);
-
- if (LPC18XX_ANALOG_ADC(pin->analog) == 0)
- offset = LPC18XX_SCU_REG_ENAIO0;
- else
- offset = LPC18XX_SCU_REG_ENAIO1;
-
- reg = readl(scu->base + offset);
- reg |= pin->analog & LPC18XX_ANALOG_BIT_MASK;
- writel(reg, scu->base + offset);
-
- return 0;
- }
-
- if (function == FUNC_DAC && (pin->analog & LPC18XX_ANALOG_PIN)) {
- writel(LPC18XX_SCU_ANALOG_PIN_CFG, scu->base + pin->offset);
-
- reg = readl(scu->base + LPC18XX_SCU_REG_ENAIO2);
- reg |= LPC18XX_SCU_REG_ENAIO2_DAC;
- writel(reg, scu->base + LPC18XX_SCU_REG_ENAIO2);
-
- return 0;
- }
-
- for (func = 0; func < LPC18XX_SCU_FUNC_PER_PIN; func++) {
- if (function == pin->functions[func])
- break;
- }
-
- if (func >= LPC18XX_SCU_FUNC_PER_PIN)
- goto fail;
-
- reg = readl(scu->base + pin->offset);
- reg &= ~LPC18XX_SCU_PIN_MODE_MASK;
- writel(reg | func, scu->base + pin->offset);
-
- return 0;
-fail:
- dev_err(pctldev->dev, "Pin %s can't be %s\n", lpc18xx_pins[group].name,
- lpc18xx_function_names[function]);
- return -EINVAL;
-}
-
-static const struct pinmux_ops lpc18xx_pmx_ops = {
- .get_functions_count = lpc18xx_pmx_get_funcs_count,
- .get_function_name = lpc18xx_pmx_get_func_name,
- .get_function_groups = lpc18xx_pmx_get_func_groups,
- .set_mux = lpc18xx_pmx_set,
-};
-
-static int lpc18xx_pctl_get_groups_count(struct pinctrl_dev *pctldev)
-{
- return ARRAY_SIZE(lpc18xx_pins);
-}
-
-static const char *lpc18xx_pctl_get_group_name(struct pinctrl_dev *pctldev,
- unsigned group)
-{
- return lpc18xx_pins[group].name;
-}
-
-static int lpc18xx_pctl_get_group_pins(struct pinctrl_dev *pctldev,
- unsigned group,
- const unsigned **pins,
- unsigned *num_pins)
-{
- *pins = &lpc18xx_pins[group].number;
- *num_pins = 1;
-
- return 0;
-}
-
-static const struct pinctrl_ops lpc18xx_pctl_ops = {
- .get_groups_count = lpc18xx_pctl_get_groups_count,
- .get_group_name = lpc18xx_pctl_get_group_name,
- .get_group_pins = lpc18xx_pctl_get_group_pins,
- .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
- .dt_free_map = pinctrl_utils_free_map,
-};
-
-static const struct pinctrl_desc lpc18xx_scu_desc = {
- .name = "lpc18xx/43xx-scu",
- .pins = lpc18xx_pins,
- .npins = ARRAY_SIZE(lpc18xx_pins),
- .pctlops = &lpc18xx_pctl_ops,
- .pmxops = &lpc18xx_pmx_ops,
- .confops = &lpc18xx_pconf_ops,
- .num_custom_params = ARRAY_SIZE(lpc18xx_params),
- .custom_params = lpc18xx_params,
-#ifdef CONFIG_DEBUG_FS
- .custom_conf_items = lpc18xx_conf_items,
-#endif
- .owner = THIS_MODULE,
-};
-
-static bool lpc18xx_valid_pin_function(unsigned pin, unsigned function)
-{
- struct lpc18xx_pin_caps *p = lpc18xx_pins[pin].drv_data;
- int i;
-
- if (function == FUNC_DAC && p->analog == DAC)
- return true;
-
- if (function == FUNC_ADC && p->analog)
- return true;
-
- if (function == FUNC_I2C0 && p->type == TYPE_I2C0)
- return true;
-
- if (function == FUNC_USB1 && p->type == TYPE_USB1)
- return true;
-
- for (i = 0; i < LPC18XX_SCU_FUNC_PER_PIN; i++) {
- if (function == p->functions[i])
- return true;
- }
-
- return false;
-}
-
-static int lpc18xx_create_group_func_map(struct device *dev,
- struct lpc18xx_scu_data *scu)
-{
- u16 pins[ARRAY_SIZE(lpc18xx_pins)];
- int func, ngroups, i;
-
- for (func = 0; func < FUNC_MAX; func++) {
- for (ngroups = 0, i = 0; i < ARRAY_SIZE(lpc18xx_pins); i++) {
- if (lpc18xx_valid_pin_function(i, func))
- pins[ngroups++] = i;
- }
-
- scu->func[func].ngroups = ngroups;
- scu->func[func].groups = devm_kcalloc(dev,
- ngroups, sizeof(char *),
- GFP_KERNEL);
- if (!scu->func[func].groups)
- return -ENOMEM;
-
- for (i = 0; i < ngroups; i++)
- scu->func[func].groups[i] = lpc18xx_pins[pins[i]].name;
- }
-
- return 0;
-}
-
-static int lpc18xx_scu_probe(struct platform_device *pdev)
-{
- struct lpc18xx_scu_data *scu;
- int ret;
-
- scu = devm_kzalloc(&pdev->dev, sizeof(*scu), GFP_KERNEL);
- if (!scu)
- return -ENOMEM;
-
- scu->base = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(scu->base))
- return PTR_ERR(scu->base);
-
- scu->clk = devm_clk_get(&pdev->dev, NULL);
- if (IS_ERR(scu->clk)) {
- dev_err(&pdev->dev, "Input clock not found.\n");
- return PTR_ERR(scu->clk);
- }
-
- ret = lpc18xx_create_group_func_map(&pdev->dev, scu);
- if (ret) {
- dev_err(&pdev->dev, "Unable to create group func map.\n");
- return ret;
- }
-
- ret = clk_prepare_enable(scu->clk);
- if (ret) {
- dev_err(&pdev->dev, "Unable to enable clock.\n");
- return ret;
- }
-
- platform_set_drvdata(pdev, scu);
-
- scu->pctl = devm_pinctrl_register(&pdev->dev, &lpc18xx_scu_desc, scu);
- if (IS_ERR(scu->pctl)) {
- dev_err(&pdev->dev, "Could not register pinctrl driver\n");
- clk_disable_unprepare(scu->clk);
- return PTR_ERR(scu->pctl);
- }
-
- return 0;
-}
-
-static const struct of_device_id lpc18xx_scu_match[] = {
- { .compatible = "nxp,lpc1850-scu" },
- {},
-};
-
-static struct platform_driver lpc18xx_scu_driver = {
- .probe = lpc18xx_scu_probe,
- .driver = {
- .name = "lpc18xx-scu",
- .of_match_table = lpc18xx_scu_match,
- .suppress_bind_attrs = true,
- },
-};
-builtin_platform_driver(lpc18xx_scu_driver);
--
2.43.0
^ permalink raw reply related
* [PATCH 09/11] ARM: configs: lpc*: Remove NOMMU platform support
From: Frank.Li @ 2026-06-19 15:41 UTC (permalink / raw)
To: Arnd Bergmann, Sascha Hauer, Pengutronix Kernel Team,
Stefan Agner, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Russell King, Abel Vesa, Peng Fan,
Michael Turquette, Stephen Boyd, Brian Masney, Dong Aisheng,
Jacky Bai, NXP S32 Linux Team, Linus Walleij, Vladimir Zapolskiy,
Piotr Wojtaszczyk, Kees Cook, Gustavo A. R. Silva
Cc: linux-arm-kernel, imx, devicetree, linux-kernel, linux-clk,
linux-gpio, linux-hardening, Frank Li
In-Reply-To: <20260619-dts_cleanup_arm_mcore-v1-0-0101795a2662@nxp.com>
From: Frank Li <Frank.Li@nxp.com>
Commercial users and hardware vendors migrated to Zephyr or other RTOS
solutions years ago, leaving the NOMMU platform support effectively
unused and unmaintained.
Remove the obsolete support to reduce maintenance burden and simplify the
NXP/Freescale platform code.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm/configs/lpc18xx_defconfig | 158 ------------------------------
arch/arm/configs/lpc32xx_defconfig | 192 -------------------------------------
2 files changed, 350 deletions(-)
diff --git a/arch/arm/configs/lpc18xx_defconfig b/arch/arm/configs/lpc18xx_defconfig
deleted file mode 100644
index f142a6637edee..0000000000000
--- a/arch/arm/configs/lpc18xx_defconfig
+++ /dev/null
@@ -1,158 +0,0 @@
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_RD_BZIP2 is not set
-# CONFIG_RD_LZMA is not set
-# CONFIG_RD_XZ is not set
-# CONFIG_RD_LZO is not set
-# CONFIG_RD_LZ4 is not set
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-# CONFIG_UID16 is not set
-CONFIG_BASE_SMALL=y
-# CONFIG_FUTEX is not set
-# CONFIG_EPOLL is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_EXPERT=y
-# CONFIG_MMU is not set
-CONFIG_ARCH_LPC18XX=y
-CONFIG_SET_MEM_PARAM=y
-CONFIG_DRAM_BASE=0x28000000
-CONFIG_DRAM_SIZE=0x02000000
-CONFIG_FLASH_MEM_BASE=0x1b000000
-CONFIG_FLASH_SIZE=0x00080000
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-# CONFIG_COREDUMP is not set
-# CONFIG_VM_EVENT_COUNTERS is not set
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PHYSMAP_OF=y
-CONFIG_MTD_SPI_NOR=y
-# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
-CONFIG_SPI_NXP_SPIFI=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_SRAM=y
-CONFIG_EEPROM_AT24=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-# CONFIG_NET_VENDOR_ARC is not set
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CIRRUS is not set
-# CONFIG_NET_VENDOR_FARADAY is not set
-# CONFIG_NET_VENDOR_HISILICON is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_QUALCOMM is not set
-# CONFIG_NET_VENDOR_ROCKER is not set
-# CONFIG_NET_VENDOR_SAMSUNG is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-# CONFIG_NET_VENDOR_SMSC is not set
-CONFIG_STMMAC_ETH=y
-# CONFIG_NET_VENDOR_VIA is not set
-# CONFIG_NET_VENDOR_WIZNET is not set
-CONFIG_SMSC_PHY=y
-# CONFIG_USB_NET_DRIVERS is not set
-# CONFIG_WLAN is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_GPIO=y
-CONFIG_KEYBOARD_GPIO_POLLED=y
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_UNIX98_PTYS is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIAL_NONSTANDARD=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C_LPC2K=y
-CONFIG_SPI=y
-CONFIG_SPI_PL022=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_74XX_MMIO=y
-CONFIG_GPIO_PCF857X=y
-CONFIG_SENSORS_JC42=y
-CONFIG_SENSORS_LM75=y
-CONFIG_WATCHDOG=y
-CONFIG_LPC18XX_WATCHDOG=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_DRM=y
-CONFIG_DRM_PL111=y
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_ROOT_HUB_TT=y
-CONFIG_USB_EHCI_HCD_PLATFORM=y
-CONFIG_USB_STORAGE=y
-CONFIG_MMC=y
-CONFIG_MMC_DW=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_PCA9532=y
-CONFIG_LEDS_PCA9532_GPIO=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_LPC24XX=y
-CONFIG_DMADEVICES=y
-CONFIG_AMBA_PL08X=y
-CONFIG_LPC18XX_DMAMUX=y
-CONFIG_MEMORY=y
-CONFIG_ARM_PL172_MPMC=y
-CONFIG_IIO=y
-CONFIG_MMA7455_I2C=y
-CONFIG_LPC18XX_ADC=y
-CONFIG_LPC18XX_DAC=y
-CONFIG_IIO_SYSFS_TRIGGER=y
-CONFIG_PWM=y
-CONFIG_PWM_LPC18XX_SCT=y
-CONFIG_PHY_LPC18XX_USB_OTG=y
-CONFIG_NVMEM_LPC18XX_EEPROM=y
-CONFIG_EXT2_FS=y
-# CONFIG_FILE_LOCKING is not set
-# CONFIG_DNOTIFY is not set
-# CONFIG_INOTIFY_USER is not set
-CONFIG_JFFS2_FS=y
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PRINTK_TIME=y
-# CONFIG_ENABLE_MUST_CHECK is not set
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_FS=y
-# CONFIG_SLUB_DEBUG is not set
-# CONFIG_SCHED_DEBUG is not set
-CONFIG_DEBUG_LL=y
-CONFIG_EARLY_PRINTK=y
diff --git a/arch/arm/configs/lpc32xx_defconfig b/arch/arm/configs/lpc32xx_defconfig
deleted file mode 100644
index b9e2e603cd95e..0000000000000
--- a/arch/arm/configs/lpc32xx_defconfig
+++ /dev/null
@@ -1,192 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=16
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_EXPERT=y
-# CONFIG_ARCH_MULTI_V7 is not set
-CONFIG_ARCH_LPC32XX=y
-CONFIG_AEABI=y
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ATAG_DTB_COMPAT=y
-CONFIG_CMDLINE="console=ttyS0,115200n81 root=/dev/ram0"
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_JUMP_LABEL=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_WIRELESS is not set
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_NAND_SLC_LPC32XX=y
-CONFIG_MTD_NAND_MLC_LPC32XX=y
-CONFIG_MTD_UBI=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_CRYPTOLOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=1
-CONFIG_BLK_DEV_RAM_SIZE=16384
-CONFIG_SRAM=y
-CONFIG_EEPROM_AT24=y
-CONFIG_EEPROM_AT25=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_NETDEVICES=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CIRRUS is not set
-# CONFIG_NET_VENDOR_FARADAY is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-CONFIG_LPC_ENET=y
-# CONFIG_NET_VENDOR_SEEQ is not set
-# CONFIG_NET_VENDOR_SMSC is not set
-# CONFIG_NET_VENDOR_STMICRO is not set
-CONFIG_SMSC_PHY=y
-# CONFIG_WLAN is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_GPIO=y
-CONFIG_KEYBOARD_GPIO_POLLED=y
-CONFIG_KEYBOARD_LPC32XX=y
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_LPC32XX=y
-CONFIG_SERIO_LIBPS2=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIAL_HS_LPC32XX=y
-CONFIG_SERIAL_HS_LPC32XX_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_PNX=y
-CONFIG_SPI=y
-CONFIG_SPI_PL022=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_GENERIC_PLATFORM=y
-CONFIG_GPIO_LPC32XX=y
-CONFIG_GPIO_PCA953X=y
-CONFIG_GPIO_PCF857X=y
-CONFIG_SENSORS_DS620=y
-CONFIG_SENSORS_MAX6639=y
-CONFIG_WATCHDOG=y
-CONFIG_PNX4008_WATCHDOG=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_DRM=y
-CONFIG_DRM_PANEL_SIMPLE=y
-CONFIG_DRM_PANEL_EDP=y
-CONFIG_DRM_PL111=y
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_VERBOSE_PROCFS is not set
-CONFIG_SND_DEBUG=y
-CONFIG_SND_DEBUG_VERBOSE=y
-CONFIG_SND_SEQUENCER=y
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-# CONFIG_SND_SPI is not set
-CONFIG_SND_SOC=y
-CONFIG_USB=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_LPC32XX=y
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_MMC=y
-CONFIG_MMC_ARMMMCI=y
-CONFIG_MMC_SPI=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_PCA9532=y
-CONFIG_LEDS_PCA9532_GPIO=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_PWM=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_LEDS_TRIGGER_BACKLIGHT=y
-CONFIG_LEDS_TRIGGER_GPIO=y
-CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_INTF_DEV_UIE_EMUL=y
-CONFIG_RTC_DRV_DS1374=y
-CONFIG_RTC_DRV_PCF8563=y
-CONFIG_RTC_DRV_LPC32XX=y
-CONFIG_DMADEVICES=y
-CONFIG_AMBA_PL08X=y
-CONFIG_STAGING=y
-CONFIG_MEMORY=y
-CONFIG_ARM_PL172_MPMC=y
-CONFIG_IIO=y
-CONFIG_LPC32XX_ADC=y
-CONFIG_MAX517=y
-CONFIG_PWM=y
-CONFIG_PWM_LPC32XX=y
-CONFIG_EXT2_FS=y
-CONFIG_AUTOFS_FS=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_FS_WBUF_VERIFY=y
-CONFIG_UBIFS_FS=y
-CONFIG_CRAMFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V4=y
-CONFIG_NFS_V4_1=y
-CONFIG_NFS_V4_2=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_UTF8=y
-# CONFIG_CRYPTO_HW is not set
-CONFIG_PRINTK_TIME=y
-CONFIG_DYNAMIC_DEBUG=y
-CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
-CONFIG_GDB_SCRIPTS=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_FS=y
-CONFIG_PANIC_ON_OOPS=y
-CONFIG_PANIC_TIMEOUT=5
-# CONFIG_SCHED_DEBUG is not set
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_LL=y
-CONFIG_EARLY_PRINTK=y
--
2.43.0
^ permalink raw reply related
* [PATCH 06/11] ARM: imxrt_defconfig: Remove NOMMU platform support
From: Frank.Li @ 2026-06-19 15:41 UTC (permalink / raw)
To: Arnd Bergmann, Sascha Hauer, Pengutronix Kernel Team,
Stefan Agner, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Russell King, Abel Vesa, Peng Fan,
Michael Turquette, Stephen Boyd, Brian Masney, Dong Aisheng,
Jacky Bai, NXP S32 Linux Team, Linus Walleij, Vladimir Zapolskiy,
Piotr Wojtaszczyk, Kees Cook, Gustavo A. R. Silva
Cc: linux-arm-kernel, imx, devicetree, linux-kernel, linux-clk,
linux-gpio, linux-hardening, Frank Li
In-Reply-To: <20260619-dts_cleanup_arm_mcore-v1-0-0101795a2662@nxp.com>
From: Frank Li <Frank.Li@nxp.com>
Commercial users and hardware vendors migrated to Zephyr or other RTOS
solutions years ago, leaving the NOMMU platform support effectively
unused and unmaintained.
Remove the obsolete support to reduce maintenance burden and simplify the
i.MX platform code.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm/configs/imxrt_defconfig | 35 -----------------------------------
1 file changed, 35 deletions(-)
diff --git a/arch/arm/configs/imxrt_defconfig b/arch/arm/configs/imxrt_defconfig
deleted file mode 100644
index 52dba3762996c..0000000000000
--- a/arch/arm/configs/imxrt_defconfig
+++ /dev/null
@@ -1,35 +0,0 @@
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_BPF_SYSCALL=y
-CONFIG_SCHED_AUTOGROUP=y
-# CONFIG_MMU is not set
-CONFIG_ARCH_MXC=y
-CONFIG_SOC_IMXRT=y
-CONFIG_SET_MEM_PARAM=y
-CONFIG_DRAM_BASE=0x80000000
-CONFIG_DRAM_SIZE=0x02000000
-CONFIG_BINFMT_FLAT=y
-CONFIG_UEVENT_HELPER=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_IMX_WEIM=y
-CONFIG_LEGACY_PTY_COUNT=2
-CONFIG_SERIAL_FSL_LPUART=y
-CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
-CONFIG_SERIAL_DEV_BUS=y
-CONFIG_PINCTRL_IMXRT1050=y
-CONFIG_GPIO_MXC=y
-CONFIG_MMC=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MMC_SDHCI_ESDHC_IMX=y
-CONFIG_DMADEVICES=y
-CONFIG_FSL_EDMA=y
-CONFIG_CLK_IMXRT1050=y
-CONFIG_EXT4_FS=y
-CONFIG_EXT4_FS_POSIX_ACL=y
-CONFIG_EXT4_FS_SECURITY=y
-CONFIG_VFAT_FS=y
-CONFIG_FAT_DEFAULT_UTF8=y
-CONFIG_EXFAT_FS=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_UTF8=y
--
2.43.0
^ permalink raw reply related
* [PATCH 05/11] pinctrl: freescale: IMXRT: Remove NOMMU platform support
From: Frank.Li @ 2026-06-19 15:41 UTC (permalink / raw)
To: Arnd Bergmann, Sascha Hauer, Pengutronix Kernel Team,
Stefan Agner, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Russell King, Abel Vesa, Peng Fan,
Michael Turquette, Stephen Boyd, Brian Masney, Dong Aisheng,
Jacky Bai, NXP S32 Linux Team, Linus Walleij, Vladimir Zapolskiy,
Piotr Wojtaszczyk, Kees Cook, Gustavo A. R. Silva
Cc: linux-arm-kernel, imx, devicetree, linux-kernel, linux-clk,
linux-gpio, linux-hardening, Frank Li
In-Reply-To: <20260619-dts_cleanup_arm_mcore-v1-0-0101795a2662@nxp.com>
From: Frank Li <Frank.Li@nxp.com>
Commercial users and hardware vendors migrated to Zephyr or other RTOS
solutions years ago, leaving the NOMMU platform support effectively
unused and unmaintained.
Remove the obsolete support to reduce maintenance burden and simplify the
i.MX platform code.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
.../devicetree/bindings/pinctrl/fsl,imxrt1050.yaml | 79 -----
.../devicetree/bindings/pinctrl/fsl,imxrt1170.yaml | 77 -----
drivers/pinctrl/freescale/Kconfig | 16 -
drivers/pinctrl/freescale/Makefile | 2 -
drivers/pinctrl/freescale/pinctrl-imxrt1050.c | 309 ------------------
drivers/pinctrl/freescale/pinctrl-imxrt1170.c | 349 ---------------------
6 files changed, 832 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1050.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1050.yaml
deleted file mode 100644
index db5fe66ad8733..0000000000000
--- a/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1050.yaml
+++ /dev/null
@@ -1,79 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/pinctrl/fsl,imxrt1050.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Freescale IMXRT1050 IOMUX Controller
-
-maintainers:
- - Giulio Benetti <giulio.benetti@benettiengineering.com>
- - Jesse Taube <Mr.Bossman075@gmail.com>
-
-description:
- Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
- for common binding part and usage.
-
-properties:
- compatible:
- const: fsl,imxrt1050-iomuxc
-
- reg:
- maxItems: 1
-
-# Client device subnode's properties
-patternProperties:
- 'grp$':
- type: object
- description:
- Pinctrl node's client devices use subnodes for desired pin configuration.
- Client device subnodes use below standard properties.
-
- properties:
- fsl,pins:
- description:
- each entry consists of 6 integers and represents the mux and config
- setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
- mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
- be found in <arch/arm/boot/dts/imxrt1050-pinfunc.h>. The last
- integer CONFIG is the pad setting value like pull-up on this pin. Please
- refer to i.MXRT1050 Reference Manual for detailed CONFIG settings.
- $ref: /schemas/types.yaml#/definitions/uint32-matrix
- items:
- items:
- - description: |
- "mux_reg" indicates the offset of mux register.
- - description: |
- "conf_reg" indicates the offset of pad configuration register.
- - description: |
- "input_reg" indicates the offset of select input register.
- - description: |
- "mux_val" indicates the mux value to be applied.
- - description: |
- "input_val" indicates the select input value to be applied.
- - description: |
- "pad_setting" indicates the pad configuration value to be applied.
-
- required:
- - fsl,pins
-
- additionalProperties: false
-
-required:
- - compatible
- - reg
-
-additionalProperties: false
-
-examples:
- - |
- iomuxc: iomuxc@401f8000 {
- compatible = "fsl,imxrt1050-iomuxc";
- reg = <0x401f8000 0x4000>;
-
- pinctrl_lpuart1: lpuart1grp {
- fsl,pins =
- <0x0EC 0x2DC 0x000 0x2 0x0 0xf1>,
- <0x0F0 0x2E0 0x000 0x2 0x0 0xf1>;
- };
- };
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1170.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1170.yaml
deleted file mode 100644
index 2e880b3e537c1..0000000000000
--- a/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1170.yaml
+++ /dev/null
@@ -1,77 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/pinctrl/fsl,imxrt1170.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Freescale i.MXRT1170 IOMUX Controller
-
-maintainers:
- - Giulio Benetti <giulio.benetti@benettiengineering.com>
- - Jesse Taube <Mr.Bossman075@gmail.com>
-
-description:
- Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
- for common binding part and usage.
-
-properties:
- compatible:
- const: fsl,imxrt1170-iomuxc
-
- reg:
- maxItems: 1
-
-# Client device subnode's properties
-patternProperties:
- 'grp$':
- type: object
- description:
- Pinctrl node's client devices use subnodes for desired pin configuration.
- Client device subnodes use below standard properties.
-
- properties:
- fsl,pins:
- description:
- each entry consists of 6 integers and represents the mux and config
- setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
- mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
- be found in <arch/arm/boot/dts/imxrt1170-pinfunc.h>. The last
- integer CONFIG is the pad setting value like pull-up on this pin. Please
- refer to i.MXRT1170 Reference Manual for detailed CONFIG settings.
- $ref: /schemas/types.yaml#/definitions/uint32-matrix
- items:
- items:
- - description: |
- "mux_reg" indicates the offset of mux register.
- - description: |
- "conf_reg" indicates the offset of pad configuration register.
- - description: |
- "input_reg" indicates the offset of select input register.
- - description: |
- "mux_val" indicates the mux value to be applied.
- - description: |
- "input_val" indicates the select input value to be applied.
- - description: |
- "pad_setting" indicates the pad configuration value to be applied.
- required:
- - fsl,pins
-
- additionalProperties: false
-
-required:
- - compatible
- - reg
-
-additionalProperties: false
-
-examples:
- - |
- iomuxc: iomuxc@400e8000 {
- compatible = "fsl,imxrt1170-iomuxc";
- reg = <0x400e8000 0x4000>;
- pinctrl_lpuart1: lpuart1grp {
- fsl,pins =
- <0x16C 0x3B0 0x620 0x0 0x0 0xf1>,
- <0x170 0x3B4 0x61C 0x0 0x0 0xf1>;
- };
- };
diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig
index fd53cf5bb843d..9baf222abdecf 100644
--- a/drivers/pinctrl/freescale/Kconfig
+++ b/drivers/pinctrl/freescale/Kconfig
@@ -229,15 +229,6 @@ config PINCTRL_IMX8ULP
help
Say Y here to enable the imx8ulp pinctrl driver
-config PINCTRL_IMXRT1050
- bool "IMXRT1050 pinctrl driver"
- depends on OF
- depends on SOC_IMXRT || COMPILE_TEST
- default SOC_IMXRT
- select PINCTRL_IMX
- help
- Say Y here to enable the imxrt1050 pinctrl driver
-
config PINCTRL_IMX91
tristate "IMX91 pinctrl driver"
depends on ARCH_MXC
@@ -276,10 +267,3 @@ config PINCTRL_IMX28
bool
select PINCTRL_MXS
-config PINCTRL_IMXRT1170
- bool "IMXRT1170 pinctrl driver"
- depends on OF
- depends on SOC_IMXRT || COMPILE_TEST
- select PINCTRL_IMX
- help
- Say Y here to enable the imxrt1170 pinctrl driver
diff --git a/drivers/pinctrl/freescale/Makefile b/drivers/pinctrl/freescale/Makefile
index d27085c2b4c45..72de53db68eb8 100644
--- a/drivers/pinctrl/freescale/Makefile
+++ b/drivers/pinctrl/freescale/Makefile
@@ -33,5 +33,3 @@ obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
obj-$(CONFIG_PINCTRL_IMX25) += pinctrl-imx25.o
obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o
-obj-$(CONFIG_PINCTRL_IMXRT1050) += pinctrl-imxrt1050.o
-obj-$(CONFIG_PINCTRL_IMXRT1170) += pinctrl-imxrt1170.o
diff --git a/drivers/pinctrl/freescale/pinctrl-imxrt1050.c b/drivers/pinctrl/freescale/pinctrl-imxrt1050.c
deleted file mode 100644
index f6435227d4fbb..0000000000000
--- a/drivers/pinctrl/freescale/pinctrl-imxrt1050.c
+++ /dev/null
@@ -1,309 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2020
- * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
- */
-
-#include <linux/err.h>
-#include <linux/init.h>
-#include <linux/of.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/platform_device.h>
-
-#include "pinctrl-imx.h"
-
-enum imxrt1050_pads {
- IMXRT1050_PAD_RESERVE0,
- IMXRT1050_PAD_RESERVE1,
- IMXRT1050_PAD_RESERVE2,
- IMXRT1050_PAD_RESERVE3,
- IMXRT1050_PAD_RESERVE4,
- IMXRT1050_PAD_EMC_00,
- IMXRT1050_PAD_EMC_01,
- IMXRT1050_PAD_EMC_02,
- IMXRT1050_PAD_EMC_03,
- IMXRT1050_PAD_EMC_04,
- IMXRT1050_PAD_EMC_05,
- IMXRT1050_PAD_EMC_06,
- IMXRT1050_PAD_EMC_07,
- IMXRT1050_PAD_EMC_08,
- IMXRT1050_PAD_EMC_09,
- IMXRT1050_PAD_EMC_10,
- IMXRT1050_PAD_EMC_11,
- IMXRT1050_PAD_EMC_12,
- IMXRT1050_PAD_EMC_13,
- IMXRT1050_PAD_EMC_14,
- IMXRT1050_PAD_EMC_15,
- IMXRT1050_PAD_EMC_16,
- IMXRT1050_PAD_EMC_17,
- IMXRT1050_PAD_EMC_18,
- IMXRT1050_PAD_EMC_19,
- IMXRT1050_PAD_EMC_20,
- IMXRT1050_PAD_EMC_21,
- IMXRT1050_PAD_EMC_22,
- IMXRT1050_PAD_EMC_23,
- IMXRT1050_PAD_EMC_24,
- IMXRT1050_PAD_EMC_25,
- IMXRT1050_PAD_EMC_26,
- IMXRT1050_PAD_EMC_27,
- IMXRT1050_PAD_EMC_28,
- IMXRT1050_PAD_EMC_29,
- IMXRT1050_PAD_EMC_30,
- IMXRT1050_PAD_EMC_31,
- IMXRT1050_PAD_EMC_32,
- IMXRT1050_PAD_EMC_33,
- IMXRT1050_PAD_EMC_34,
- IMXRT1050_PAD_EMC_35,
- IMXRT1050_PAD_EMC_36,
- IMXRT1050_PAD_EMC_37,
- IMXRT1050_PAD_EMC_38,
- IMXRT1050_PAD_EMC_39,
- IMXRT1050_PAD_EMC_40,
- IMXRT1050_PAD_EMC_41,
- IMXRT1050_PAD_AD_B0_00,
- IMXRT1050_PAD_AD_B0_01,
- IMXRT1050_PAD_AD_B0_02,
- IMXRT1050_PAD_AD_B0_03,
- IMXRT1050_PAD_AD_B0_04,
- IMXRT1050_PAD_AD_B0_05,
- IMXRT1050_PAD_AD_B0_06,
- IMXRT1050_PAD_AD_B0_07,
- IMXRT1050_PAD_AD_B0_08,
- IMXRT1050_PAD_AD_B0_09,
- IMXRT1050_PAD_AD_B0_10,
- IMXRT1050_PAD_AD_B0_11,
- IMXRT1050_PAD_AD_B0_12,
- IMXRT1050_PAD_AD_B0_13,
- IMXRT1050_PAD_AD_B0_14,
- IMXRT1050_PAD_AD_B0_15,
- IMXRT1050_PAD_AD_B1_00,
- IMXRT1050_PAD_AD_B1_01,
- IMXRT1050_PAD_AD_B1_02,
- IMXRT1050_PAD_AD_B1_03,
- IMXRT1050_PAD_AD_B1_04,
- IMXRT1050_PAD_AD_B1_05,
- IMXRT1050_PAD_AD_B1_06,
- IMXRT1050_PAD_AD_B1_07,
- IMXRT1050_PAD_AD_B1_08,
- IMXRT1050_PAD_AD_B1_09,
- IMXRT1050_PAD_AD_B1_10,
- IMXRT1050_PAD_AD_B1_11,
- IMXRT1050_PAD_AD_B1_12,
- IMXRT1050_PAD_AD_B1_13,
- IMXRT1050_PAD_AD_B1_14,
- IMXRT1050_PAD_AD_B1_15,
- IMXRT1050_PAD_B0_00,
- IMXRT1050_PAD_B0_01,
- IMXRT1050_PAD_B0_02,
- IMXRT1050_PAD_B0_03,
- IMXRT1050_PAD_B0_04,
- IMXRT1050_PAD_B0_05,
- IMXRT1050_PAD_B0_06,
- IMXRT1050_PAD_B0_07,
- IMXRT1050_PAD_B0_08,
- IMXRT1050_PAD_B0_09,
- IMXRT1050_PAD_B0_10,
- IMXRT1050_PAD_B0_11,
- IMXRT1050_PAD_B0_12,
- IMXRT1050_PAD_B0_13,
- IMXRT1050_PAD_B0_14,
- IMXRT1050_PAD_B0_15,
- IMXRT1050_PAD_B1_00,
- IMXRT1050_PAD_B1_01,
- IMXRT1050_PAD_B1_02,
- IMXRT1050_PAD_B1_03,
- IMXRT1050_PAD_B1_04,
- IMXRT1050_PAD_B1_05,
- IMXRT1050_PAD_B1_06,
- IMXRT1050_PAD_B1_07,
- IMXRT1050_PAD_B1_08,
- IMXRT1050_PAD_B1_09,
- IMXRT1050_PAD_B1_10,
- IMXRT1050_PAD_B1_11,
- IMXRT1050_PAD_B1_12,
- IMXRT1050_PAD_B1_13,
- IMXRT1050_PAD_B1_14,
- IMXRT1050_PAD_B1_15,
- IMXRT1050_PAD_SD_B0_00,
- IMXRT1050_PAD_SD_B0_01,
- IMXRT1050_PAD_SD_B0_02,
- IMXRT1050_PAD_SD_B0_03,
- IMXRT1050_PAD_SD_B0_04,
- IMXRT1050_PAD_SD_B0_05,
- IMXRT1050_PAD_SD_B1_00,
- IMXRT1050_PAD_SD_B1_01,
- IMXRT1050_PAD_SD_B1_02,
- IMXRT1050_PAD_SD_B1_03,
- IMXRT1050_PAD_SD_B1_04,
- IMXRT1050_PAD_SD_B1_05,
- IMXRT1050_PAD_SD_B1_06,
- IMXRT1050_PAD_SD_B1_07,
- IMXRT1050_PAD_SD_B1_08,
- IMXRT1050_PAD_SD_B1_09,
- IMXRT1050_PAD_SD_B1_10,
- IMXRT1050_PAD_SD_B1_11,
-};
-
-/* Pad names for the pinmux subsystem */
-static const struct pinctrl_pin_desc imxrt1050_pinctrl_pads[] = {
- IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE0),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE1),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE2),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE3),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE4),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_00),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_01),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_02),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_03),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_04),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_05),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_06),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_07),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_08),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_09),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_10),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_11),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_12),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_13),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_14),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_15),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_16),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_17),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_18),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_19),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_20),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_21),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_22),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_23),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_24),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_25),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_26),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_27),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_28),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_29),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_30),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_31),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_32),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_33),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_34),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_35),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_36),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_37),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_38),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_39),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_40),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_41),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_00),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_01),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_02),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_03),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_04),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_05),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_06),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_07),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_08),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_09),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_10),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_11),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_12),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_13),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_14),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_15),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_00),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_01),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_02),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_03),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_04),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_05),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_06),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_07),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_08),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_09),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_10),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_11),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_12),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_13),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_14),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_15),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_00),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_01),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_02),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_03),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_04),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_05),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_06),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_07),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_08),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_09),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_10),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_11),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_12),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_13),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_14),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_15),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_00),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_01),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_02),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_03),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_04),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_05),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_06),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_07),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_08),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_09),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_10),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_11),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_12),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_13),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_14),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_15),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B0_00),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B0_01),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B0_02),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B0_03),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B0_04),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B0_05),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_00),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_01),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_02),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_03),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_04),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_05),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_06),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_07),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_08),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_09),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_10),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_11),
-};
-
-static const struct imx_pinctrl_soc_info imxrt1050_pinctrl_info = {
- .pins = imxrt1050_pinctrl_pads,
- .npins = ARRAY_SIZE(imxrt1050_pinctrl_pads),
- .gpr_compatible = "fsl,imxrt1050-iomuxc-gpr",
-};
-
-static const struct of_device_id imxrt1050_pinctrl_of_match[] = {
- { .compatible = "fsl,imxrt1050-iomuxc", .data = &imxrt1050_pinctrl_info, },
- { /* sentinel */ }
-};
-
-static int imxrt1050_pinctrl_probe(struct platform_device *pdev)
-{
- return imx_pinctrl_probe(pdev, &imxrt1050_pinctrl_info);
-}
-
-static struct platform_driver imxrt1050_pinctrl_driver = {
- .driver = {
- .name = "imxrt1050-pinctrl",
- .of_match_table = of_match_ptr(imxrt1050_pinctrl_of_match),
- .suppress_bind_attrs = true,
- },
- .probe = imxrt1050_pinctrl_probe,
-};
-
-static int __init imxrt1050_pinctrl_init(void)
-{
- return platform_driver_register(&imxrt1050_pinctrl_driver);
-}
-arch_initcall(imxrt1050_pinctrl_init);
diff --git a/drivers/pinctrl/freescale/pinctrl-imxrt1170.c b/drivers/pinctrl/freescale/pinctrl-imxrt1170.c
deleted file mode 100644
index d8857f329e253..0000000000000
--- a/drivers/pinctrl/freescale/pinctrl-imxrt1170.c
+++ /dev/null
@@ -1,349 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2022
- * Author(s): Jesse Taube <Mr.Bossman075@gmail.com>
- */
-
-#include <linux/err.h>
-#include <linux/init.h>
-#include <linux/of.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/platform_device.h>
-
-#include "pinctrl-imx.h"
-
-enum imxrt1170_pads {
- IMXRT1170_PAD_RESERVE0,
- IMXRT1170_PAD_RESERVE1,
- IMXRT1170_PAD_RESERVE2,
- IMXRT1170_PAD_RESERVE3,
- IMXRT1170_PAD_EMC_B1_00,
- IMXRT1170_PAD_EMC_B1_01,
- IMXRT1170_PAD_EMC_B1_02,
- IMXRT1170_PAD_EMC_B1_03,
- IMXRT1170_PAD_EMC_B1_04,
- IMXRT1170_PAD_EMC_B1_05,
- IMXRT1170_PAD_EMC_B1_06,
- IMXRT1170_PAD_EMC_B1_07,
- IMXRT1170_PAD_EMC_B1_08,
- IMXRT1170_PAD_EMC_B1_09,
- IMXRT1170_PAD_EMC_B1_10,
- IMXRT1170_PAD_EMC_B1_11,
- IMXRT1170_PAD_EMC_B1_12,
- IMXRT1170_PAD_EMC_B1_13,
- IMXRT1170_PAD_EMC_B1_14,
- IMXRT1170_PAD_EMC_B1_15,
- IMXRT1170_PAD_EMC_B1_16,
- IMXRT1170_PAD_EMC_B1_17,
- IMXRT1170_PAD_EMC_B1_18,
- IMXRT1170_PAD_EMC_B1_19,
- IMXRT1170_PAD_EMC_B1_20,
- IMXRT1170_PAD_EMC_B1_21,
- IMXRT1170_PAD_EMC_B1_22,
- IMXRT1170_PAD_EMC_B1_23,
- IMXRT1170_PAD_EMC_B1_24,
- IMXRT1170_PAD_EMC_B1_25,
- IMXRT1170_PAD_EMC_B1_26,
- IMXRT1170_PAD_EMC_B1_27,
- IMXRT1170_PAD_EMC_B1_28,
- IMXRT1170_PAD_EMC_B1_29,
- IMXRT1170_PAD_EMC_B1_30,
- IMXRT1170_PAD_EMC_B1_31,
- IMXRT1170_PAD_EMC_B1_32,
- IMXRT1170_PAD_EMC_B1_33,
- IMXRT1170_PAD_EMC_B1_34,
- IMXRT1170_PAD_EMC_B1_35,
- IMXRT1170_PAD_EMC_B1_36,
- IMXRT1170_PAD_EMC_B1_37,
- IMXRT1170_PAD_EMC_B1_38,
- IMXRT1170_PAD_EMC_B1_39,
- IMXRT1170_PAD_EMC_B1_40,
- IMXRT1170_PAD_EMC_B1_41,
- IMXRT1170_PAD_EMC_B2_00,
- IMXRT1170_PAD_EMC_B2_01,
- IMXRT1170_PAD_EMC_B2_02,
- IMXRT1170_PAD_EMC_B2_03,
- IMXRT1170_PAD_EMC_B2_04,
- IMXRT1170_PAD_EMC_B2_05,
- IMXRT1170_PAD_EMC_B2_06,
- IMXRT1170_PAD_EMC_B2_07,
- IMXRT1170_PAD_EMC_B2_08,
- IMXRT1170_PAD_EMC_B2_09,
- IMXRT1170_PAD_EMC_B2_10,
- IMXRT1170_PAD_EMC_B2_11,
- IMXRT1170_PAD_EMC_B2_12,
- IMXRT1170_PAD_EMC_B2_13,
- IMXRT1170_PAD_EMC_B2_14,
- IMXRT1170_PAD_EMC_B2_15,
- IMXRT1170_PAD_EMC_B2_16,
- IMXRT1170_PAD_EMC_B2_17,
- IMXRT1170_PAD_EMC_B2_18,
- IMXRT1170_PAD_EMC_B2_19,
- IMXRT1170_PAD_EMC_B2_20,
- IMXRT1170_PAD_AD_00,
- IMXRT1170_PAD_AD_01,
- IMXRT1170_PAD_AD_02,
- IMXRT1170_PAD_AD_03,
- IMXRT1170_PAD_AD_04,
- IMXRT1170_PAD_AD_05,
- IMXRT1170_PAD_AD_06,
- IMXRT1170_PAD_AD_07,
- IMXRT1170_PAD_AD_08,
- IMXRT1170_PAD_AD_09,
- IMXRT1170_PAD_AD_10,
- IMXRT1170_PAD_AD_11,
- IMXRT1170_PAD_AD_12,
- IMXRT1170_PAD_AD_13,
- IMXRT1170_PAD_AD_14,
- IMXRT1170_PAD_AD_15,
- IMXRT1170_PAD_AD_16,
- IMXRT1170_PAD_AD_17,
- IMXRT1170_PAD_AD_18,
- IMXRT1170_PAD_AD_19,
- IMXRT1170_PAD_AD_20,
- IMXRT1170_PAD_AD_21,
- IMXRT1170_PAD_AD_22,
- IMXRT1170_PAD_AD_23,
- IMXRT1170_PAD_AD_24,
- IMXRT1170_PAD_AD_25,
- IMXRT1170_PAD_AD_26,
- IMXRT1170_PAD_AD_27,
- IMXRT1170_PAD_AD_28,
- IMXRT1170_PAD_AD_29,
- IMXRT1170_PAD_AD_30,
- IMXRT1170_PAD_AD_31,
- IMXRT1170_PAD_AD_32,
- IMXRT1170_PAD_AD_33,
- IMXRT1170_PAD_AD_34,
- IMXRT1170_PAD_AD_35,
- IMXRT1170_PAD_SD_B1_00,
- IMXRT1170_PAD_SD_B1_01,
- IMXRT1170_PAD_SD_B1_02,
- IMXRT1170_PAD_SD_B1_03,
- IMXRT1170_PAD_SD_B1_04,
- IMXRT1170_PAD_SD_B1_05,
- IMXRT1170_PAD_SD_B2_00,
- IMXRT1170_PAD_SD_B2_01,
- IMXRT1170_PAD_SD_B2_02,
- IMXRT1170_PAD_SD_B2_03,
- IMXRT1170_PAD_SD_B2_04,
- IMXRT1170_PAD_SD_B2_05,
- IMXRT1170_PAD_SD_B2_06,
- IMXRT1170_PAD_SD_B2_07,
- IMXRT1170_PAD_SD_B2_08,
- IMXRT1170_PAD_SD_B2_09,
- IMXRT1170_PAD_SD_B2_10,
- IMXRT1170_PAD_SD_B2_11,
- IMXRT1170_PAD_DISP_B1_00,
- IMXRT1170_PAD_DISP_B1_01,
- IMXRT1170_PAD_DISP_B1_02,
- IMXRT1170_PAD_DISP_B1_03,
- IMXRT1170_PAD_DISP_B1_04,
- IMXRT1170_PAD_DISP_B1_05,
- IMXRT1170_PAD_DISP_B1_06,
- IMXRT1170_PAD_DISP_B1_07,
- IMXRT1170_PAD_DISP_B1_08,
- IMXRT1170_PAD_DISP_B1_09,
- IMXRT1170_PAD_DISP_B1_10,
- IMXRT1170_PAD_DISP_B1_11,
- IMXRT1170_PAD_DISP_B2_00,
- IMXRT1170_PAD_DISP_B2_01,
- IMXRT1170_PAD_DISP_B2_02,
- IMXRT1170_PAD_DISP_B2_03,
- IMXRT1170_PAD_DISP_B2_04,
- IMXRT1170_PAD_DISP_B2_05,
- IMXRT1170_PAD_DISP_B2_06,
- IMXRT1170_PAD_DISP_B2_07,
- IMXRT1170_PAD_DISP_B2_08,
- IMXRT1170_PAD_DISP_B2_09,
- IMXRT1170_PAD_DISP_B2_10,
- IMXRT1170_PAD_DISP_B2_11,
- IMXRT1170_PAD_DISP_B2_12,
- IMXRT1170_PAD_DISP_B2_13,
- IMXRT1170_PAD_DISP_B2_14,
- IMXRT1170_PAD_DISP_B2_15,
-};
-
-/* Pad names for the pinmux subsystem */
-static const struct pinctrl_pin_desc imxrt1170_pinctrl_pads[] = {
- IMX_PINCTRL_PIN(IMXRT1170_PAD_RESERVE0),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_RESERVE1),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_RESERVE2),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_RESERVE3),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_00),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_01),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_02),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_03),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_04),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_05),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_06),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_07),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_08),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_09),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_10),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_11),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_12),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_13),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_14),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_15),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_16),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_17),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_18),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_19),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_20),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_21),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_22),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_23),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_24),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_25),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_26),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_27),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_28),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_29),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_30),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_31),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_32),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_33),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_34),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_35),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_36),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_37),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_38),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_39),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_40),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_41),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_00),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_01),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_02),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_03),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_04),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_05),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_06),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_07),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_08),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_09),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_10),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_11),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_12),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_13),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_14),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_15),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_16),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_17),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_18),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_19),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_20),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_00),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_01),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_02),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_03),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_04),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_05),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_06),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_07),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_08),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_09),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_10),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_11),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_12),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_13),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_14),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_15),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_16),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_17),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_18),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_19),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_20),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_21),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_22),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_23),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_24),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_25),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_26),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_27),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_28),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_29),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_30),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_31),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_32),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_33),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_34),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_35),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B1_00),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B1_01),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B1_02),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B1_03),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B1_04),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B1_05),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_00),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_01),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_02),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_03),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_04),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_05),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_06),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_07),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_08),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_09),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_10),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_11),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_00),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_01),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_02),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_03),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_04),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_05),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_06),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_07),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_08),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_09),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_10),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_11),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_00),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_01),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_02),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_03),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_04),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_05),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_06),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_07),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_08),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_09),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_10),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_11),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_12),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_13),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_14),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_15),
-};
-
-static const struct imx_pinctrl_soc_info imxrt1170_pinctrl_info = {
- .pins = imxrt1170_pinctrl_pads,
- .npins = ARRAY_SIZE(imxrt1170_pinctrl_pads),
- .gpr_compatible = "fsl,imxrt1170-iomuxc-gpr",
-};
-
-static const struct of_device_id imxrt1170_pinctrl_of_match[] = {
- { .compatible = "fsl,imxrt1170-iomuxc", .data = &imxrt1170_pinctrl_info, },
- { /* sentinel */ }
-};
-
-static int imxrt1170_pinctrl_probe(struct platform_device *pdev)
-{
- return imx_pinctrl_probe(pdev, &imxrt1170_pinctrl_info);
-}
-
-static struct platform_driver imxrt1170_pinctrl_driver = {
- .driver = {
- .name = "imxrt1170-pinctrl",
- .of_match_table = of_match_ptr(imxrt1170_pinctrl_of_match),
- .suppress_bind_attrs = true,
- },
- .probe = imxrt1170_pinctrl_probe,
-};
-
-static int __init imxrt1170_pinctrl_init(void)
-{
- return platform_driver_register(&imxrt1170_pinctrl_driver);
-}
-arch_initcall(imxrt1170_pinctrl_init);
--
2.43.0
^ permalink raw reply related
* [PATCH 04/11] clk: imx: imxrt1050: Remove NOMMU platform support
From: Frank.Li @ 2026-06-19 15:41 UTC (permalink / raw)
To: Arnd Bergmann, Sascha Hauer, Pengutronix Kernel Team,
Stefan Agner, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Russell King, Abel Vesa, Peng Fan,
Michael Turquette, Stephen Boyd, Brian Masney, Dong Aisheng,
Jacky Bai, NXP S32 Linux Team, Linus Walleij, Vladimir Zapolskiy,
Piotr Wojtaszczyk, Kees Cook, Gustavo A. R. Silva
Cc: linux-arm-kernel, imx, devicetree, linux-kernel, linux-clk,
linux-gpio, linux-hardening, Frank Li
In-Reply-To: <20260619-dts_cleanup_arm_mcore-v1-0-0101795a2662@nxp.com>
From: Frank Li <Frank.Li@nxp.com>
Commercial users and hardware vendors migrated to Zephyr or other RTOS
solutions years ago, leaving the NOMMU platform support effectively
unused and unmaintained.
Remove the obsolete support to reduce maintenance burden and simplify the
i.MX platform code.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
drivers/clk/imx/Kconfig | 6 -
drivers/clk/imx/Makefile | 1 -
drivers/clk/imx/clk-imxrt1050.c | 182 ----------------------------
include/dt-bindings/clock/imxrt1050-clock.h | 72 -----------
4 files changed, 261 deletions(-)
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index b292e7ca5c248..92ae6e095fadb 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -123,9 +123,3 @@ config CLK_IMX95_BLK_CTL
help
Build the clock driver for i.MX95 BLK CTL
-config CLK_IMXRT1050
- tristate "IMXRT1050 CCM Clock Driver"
- depends on SOC_IMXRT || COMPILE_TEST
- select MXC_CLK
- help
- Build the driver for i.MXRT1050 CCM Clock Driver
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 208b46873a18c..e71a6a8f8b04f 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -56,5 +56,4 @@ obj-$(CONFIG_CLK_IMX6SX) += clk-imx6sx.o
obj-$(CONFIG_CLK_IMX6UL) += clk-imx6ul.o
obj-$(CONFIG_CLK_IMX7D) += clk-imx7d.o
obj-$(CONFIG_CLK_IMX7ULP) += clk-imx7ulp.o
-obj-$(CONFIG_CLK_IMXRT1050) += clk-imxrt1050.o
obj-$(CONFIG_CLK_VF610) += clk-vf610.o
diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c
deleted file mode 100644
index efd1ac9d8eeb7..0000000000000
--- a/drivers/clk/imx/clk-imxrt1050.c
+++ /dev/null
@@ -1,182 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) 2021
- * Author(s):
- * Jesse Taube <Mr.Bossman075@gmail.com>
- * Giulio Benetti <giulio.benetti@benettiengineering.com>
- */
-#include <linux/clk.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/platform_device.h>
-#include <dt-bindings/clock/imxrt1050-clock.h>
-
-#include "clk.h"
-
-static const char * const pll_ref_sels[] = {"osc", "dummy", };
-static const char * const per_sels[] = {"ipg_pdof", "osc", };
-static const char * const pll1_bypass_sels[] = {"pll1_arm", "pll1_arm_ref_sel", };
-static const char * const pll2_bypass_sels[] = {"pll2_sys", "pll2_sys_ref_sel", };
-static const char * const pll3_bypass_sels[] = {"pll3_usb_otg", "pll3_usb_otg_ref_sel", };
-static const char * const pll5_bypass_sels[] = {"pll5_video", "pll5_video_ref_sel", };
-static const char *const pre_periph_sels[] = {
- "pll2_sys", "pll2_pfd2_396m", "pll2_pfd0_352m", "arm_podf", };
-static const char *const periph_sels[] = { "pre_periph_sel", "todo", };
-static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
-static const char *const lpuart_sels[] = { "pll3_80m", "osc", };
-static const char *const lcdif_sels[] = {
- "pll2_sys", "pll3_pfd3_454_74m", "pll5_video", "pll2_pfd0_352m",
- "pll2_pfd1_594m", "pll3_pfd1_664_62m", };
-static const char *const semc_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_664_62m", };
-static const char *const semc_sels[] = { "periph_sel", "semc_alt_sel", };
-
-static struct clk_hw **hws;
-static struct clk_hw_onecell_data *clk_hw_data;
-
-static int imxrt1050_clocks_probe(struct platform_device *pdev)
-{
- void __iomem *ccm_base;
- void __iomem *pll_base;
- struct device *dev = &pdev->dev;
- struct device_node *np = dev->of_node;
- struct device_node *anp;
- int ret;
-
- clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws,
- IMXRT1050_CLK_END), GFP_KERNEL);
- if (WARN_ON(!clk_hw_data))
- return -ENOMEM;
-
- clk_hw_data->num = IMXRT1050_CLK_END;
- hws = clk_hw_data->hws;
-
- hws[IMXRT1050_CLK_OSC] = imx_get_clk_hw_by_name(np, "osc");
-
- anp = of_find_compatible_node(NULL, NULL, "fsl,imxrt-anatop");
- pll_base = devm_of_iomap(dev, anp, 0, NULL);
- of_node_put(anp);
- if (WARN_ON(IS_ERR(pll_base))) {
- ret = PTR_ERR(pll_base);
- goto unregister_hws;
- }
-
- /* Anatop clocks */
- hws[IMXRT1050_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0UL);
-
- hws[IMXRT1050_CLK_PLL1_REF_SEL] = imx_clk_hw_mux("pll1_arm_ref_sel",
- pll_base + 0x0, 14, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
- hws[IMXRT1050_CLK_PLL2_REF_SEL] = imx_clk_hw_mux("pll2_sys_ref_sel",
- pll_base + 0x30, 14, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
- hws[IMXRT1050_CLK_PLL3_REF_SEL] = imx_clk_hw_mux("pll3_usb_otg_ref_sel",
- pll_base + 0x10, 14, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
- hws[IMXRT1050_CLK_PLL5_REF_SEL] = imx_clk_hw_mux("pll5_video_ref_sel",
- pll_base + 0xa0, 14, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
-
- hws[IMXRT1050_CLK_PLL1_ARM] = imx_clk_hw_pllv3(IMX_PLLV3_SYS, "pll1_arm",
- "pll1_arm_ref_sel", pll_base + 0x0, 0x7f);
- hws[IMXRT1050_CLK_PLL2_SYS] = imx_clk_hw_pllv3(IMX_PLLV3_GENERIC, "pll2_sys",
- "pll2_sys_ref_sel", pll_base + 0x30, 0x1);
- hws[IMXRT1050_CLK_PLL3_USB_OTG] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll3_usb_otg",
- "pll3_usb_otg_ref_sel", pll_base + 0x10, 0x1);
- hws[IMXRT1050_CLK_PLL5_VIDEO] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll5_video",
- "pll5_video_ref_sel", pll_base + 0xa0, 0x7f);
-
- /* PLL bypass out */
- hws[IMXRT1050_CLK_PLL1_BYPASS] = imx_clk_hw_mux_flags("pll1_bypass", pll_base + 0x0, 16, 1,
- pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);
- hws[IMXRT1050_CLK_PLL2_BYPASS] = imx_clk_hw_mux_flags("pll2_bypass", pll_base + 0x30, 16, 1,
- pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);
- hws[IMXRT1050_CLK_PLL3_BYPASS] = imx_clk_hw_mux_flags("pll3_bypass", pll_base + 0x10, 16, 1,
- pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT);
- hws[IMXRT1050_CLK_PLL5_BYPASS] = imx_clk_hw_mux_flags("pll5_bypass", pll_base + 0xa0, 16, 1,
- pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT);
-
- hws[IMXRT1050_CLK_VIDEO_POST_DIV_SEL] = imx_clk_hw_divider("video_post_div_sel",
- "pll5_video", pll_base + 0xa0, 19, 2);
- hws[IMXRT1050_CLK_VIDEO_DIV] = imx_clk_hw_divider("video_div",
- "video_post_div_sel", pll_base + 0x170, 30, 2);
-
- hws[IMXRT1050_CLK_PLL3_80M] = imx_clk_hw_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
-
- hws[IMXRT1050_CLK_PLL2_PFD0_352M] = imx_clk_hw_pfd("pll2_pfd0_352m", "pll2_sys", pll_base + 0x100, 0);
- hws[IMXRT1050_CLK_PLL2_PFD1_594M] = imx_clk_hw_pfd("pll2_pfd1_594m", "pll2_sys", pll_base + 0x100, 1);
- hws[IMXRT1050_CLK_PLL2_PFD2_396M] = imx_clk_hw_pfd("pll2_pfd2_396m", "pll2_sys", pll_base + 0x100, 2);
- hws[IMXRT1050_CLK_PLL3_PFD1_664_62M] = imx_clk_hw_pfd("pll3_pfd1_664_62m", "pll3_usb_otg", pll_base + 0xf0, 1);
- hws[IMXRT1050_CLK_PLL3_PFD3_454_74M] = imx_clk_hw_pfd("pll3_pfd3_454_74m", "pll3_usb_otg", pll_base + 0xf0, 3);
-
- /* CCM clocks */
- ccm_base = devm_platform_ioremap_resource(pdev, 0);
- if (WARN_ON(IS_ERR(ccm_base))) {
- ret = PTR_ERR(ccm_base);
- goto unregister_hws;
- }
-
- hws[IMXRT1050_CLK_ARM_PODF] = imx_clk_hw_divider("arm_podf", "pll1_arm", ccm_base + 0x10, 0, 3);
- hws[IMXRT1050_CLK_PRE_PERIPH_SEL] = imx_clk_hw_mux("pre_periph_sel", ccm_base + 0x18, 18, 2,
- pre_periph_sels, ARRAY_SIZE(pre_periph_sels));
- hws[IMXRT1050_CLK_PERIPH_SEL] = imx_clk_hw_mux("periph_sel", ccm_base + 0x14, 25, 1,
- periph_sels, ARRAY_SIZE(periph_sels));
- hws[IMXRT1050_CLK_USDHC1_SEL] = imx_clk_hw_mux("usdhc1_sel", ccm_base + 0x1c, 16, 1,
- usdhc_sels, ARRAY_SIZE(usdhc_sels));
- hws[IMXRT1050_CLK_USDHC2_SEL] = imx_clk_hw_mux("usdhc2_sel", ccm_base + 0x1c, 17, 1,
- usdhc_sels, ARRAY_SIZE(usdhc_sels));
- hws[IMXRT1050_CLK_LPUART_SEL] = imx_clk_hw_mux("lpuart_sel", ccm_base + 0x24, 6, 1,
- lpuart_sels, ARRAY_SIZE(lpuart_sels));
- hws[IMXRT1050_CLK_LCDIF_SEL] = imx_clk_hw_mux("lcdif_sel", ccm_base + 0x38, 15, 3,
- lcdif_sels, ARRAY_SIZE(lcdif_sels));
- hws[IMXRT1050_CLK_PER_CLK_SEL] = imx_clk_hw_mux("per_sel", ccm_base + 0x1C, 6, 1,
- per_sels, ARRAY_SIZE(per_sels));
- hws[IMXRT1050_CLK_SEMC_ALT_SEL] = imx_clk_hw_mux("semc_alt_sel", ccm_base + 0x14, 7, 1,
- semc_alt_sels, ARRAY_SIZE(semc_alt_sels));
- hws[IMXRT1050_CLK_SEMC_SEL] = imx_clk_hw_mux_flags("semc_sel", ccm_base + 0x14, 6, 1,
- semc_sels, ARRAY_SIZE(semc_sels), CLK_IS_CRITICAL);
-
- hws[IMXRT1050_CLK_AHB_PODF] = imx_clk_hw_divider("ahb", "periph_sel", ccm_base + 0x14, 10, 3);
- hws[IMXRT1050_CLK_IPG_PDOF] = imx_clk_hw_divider("ipg", "ahb", ccm_base + 0x14, 8, 2);
- hws[IMXRT1050_CLK_PER_PDOF] = imx_clk_hw_divider("per", "per_sel", ccm_base + 0x1C, 0, 5);
-
- hws[IMXRT1050_CLK_USDHC1_PODF] = imx_clk_hw_divider("usdhc1_podf", "usdhc1_sel", ccm_base + 0x24, 11, 3);
- hws[IMXRT1050_CLK_USDHC2_PODF] = imx_clk_hw_divider("usdhc2_podf", "usdhc2_sel", ccm_base + 0x24, 16, 3);
- hws[IMXRT1050_CLK_LPUART_PODF] = imx_clk_hw_divider("lpuart_podf", "lpuart_sel", ccm_base + 0x24, 0, 6);
- hws[IMXRT1050_CLK_LCDIF_PRED] = imx_clk_hw_divider("lcdif_pred", "lcdif_sel", ccm_base + 0x38, 12, 3);
- hws[IMXRT1050_CLK_LCDIF_PODF] = imx_clk_hw_divider("lcdif_podf", "lcdif_pred", ccm_base + 0x18, 23, 3);
-
- hws[IMXRT1050_CLK_USDHC1] = imx_clk_hw_gate2("usdhc1", "usdhc1_podf", ccm_base + 0x80, 2);
- hws[IMXRT1050_CLK_USDHC2] = imx_clk_hw_gate2("usdhc2", "usdhc2_podf", ccm_base + 0x80, 4);
- hws[IMXRT1050_CLK_LPUART1] = imx_clk_hw_gate2("lpuart1", "lpuart_podf", ccm_base + 0x7c, 24);
- hws[IMXRT1050_CLK_LCDIF_APB] = imx_clk_hw_gate2("lcdif", "lcdif_podf", ccm_base + 0x70, 28);
- hws[IMXRT1050_CLK_LCDIF_PIX] = imx_clk_hw_gate2("lcdif_pix", "lcdif", ccm_base + 0x74, 10);
- hws[IMXRT1050_CLK_DMA] = imx_clk_hw_gate("dma", "ipg", ccm_base + 0x7C, 6);
- hws[IMXRT1050_CLK_DMA_MUX] = imx_clk_hw_gate("dmamux0", "ipg", ccm_base + 0x7C, 7);
- imx_check_clk_hws(hws, IMXRT1050_CLK_END);
-
- ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
- if (ret < 0) {
- dev_err(dev, "Failed to register clks for i.MXRT1050.\n");
- goto unregister_hws;
- }
- return 0;
-
-unregister_hws:
- imx_unregister_hw_clocks(hws, IMXRT1050_CLK_END);
- return ret;
-}
-static const struct of_device_id imxrt1050_clk_of_match[] = {
- { .compatible = "fsl,imxrt1050-ccm" },
- { /* Sentinel */ }
-};
-MODULE_DEVICE_TABLE(of, imxrt1050_clk_of_match);
-
-static struct platform_driver imxrt1050_clk_driver = {
- .probe = imxrt1050_clocks_probe,
- .driver = {
- .name = "imxrt1050-ccm",
- .of_match_table = imxrt1050_clk_of_match,
- },
-};
-module_platform_driver(imxrt1050_clk_driver);
-
-MODULE_DESCRIPTION("NXP i.MX RT1050 clock driver");
-MODULE_LICENSE("Dual BSD/GPL");
-MODULE_AUTHOR("Jesse Taube <Mr.Bossman075@gmail.com>");
-MODULE_AUTHOR("Giulio Benetti <giulio.benetti@benettiengineering.com>");
diff --git a/include/dt-bindings/clock/imxrt1050-clock.h b/include/dt-bindings/clock/imxrt1050-clock.h
deleted file mode 100644
index 93bef0832d16d..0000000000000
--- a/include/dt-bindings/clock/imxrt1050-clock.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
-/*
- * Copyright(C) 2019
- * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
- */
-
-#ifndef __DT_BINDINGS_CLOCK_IMXRT1050_H
-#define __DT_BINDINGS_CLOCK_IMXRT1050_H
-
-#define IMXRT1050_CLK_DUMMY 0
-#define IMXRT1050_CLK_CKIL 1
-#define IMXRT1050_CLK_CKIH 2
-#define IMXRT1050_CLK_OSC 3
-#define IMXRT1050_CLK_PLL2_PFD0_352M 4
-#define IMXRT1050_CLK_PLL2_PFD1_594M 5
-#define IMXRT1050_CLK_PLL2_PFD2_396M 6
-#define IMXRT1050_CLK_PLL3_PFD0_720M 7
-#define IMXRT1050_CLK_PLL3_PFD1_664_62M 8
-#define IMXRT1050_CLK_PLL3_PFD2_508_24M 9
-#define IMXRT1050_CLK_PLL3_PFD3_454_74M 10
-#define IMXRT1050_CLK_PLL2_198M 11
-#define IMXRT1050_CLK_PLL3_120M 12
-#define IMXRT1050_CLK_PLL3_80M 13
-#define IMXRT1050_CLK_PLL3_60M 14
-#define IMXRT1050_CLK_PLL1_BYPASS 15
-#define IMXRT1050_CLK_PLL2_BYPASS 16
-#define IMXRT1050_CLK_PLL3_BYPASS 17
-#define IMXRT1050_CLK_PLL5_BYPASS 19
-#define IMXRT1050_CLK_PLL1_REF_SEL 20
-#define IMXRT1050_CLK_PLL2_REF_SEL 21
-#define IMXRT1050_CLK_PLL3_REF_SEL 22
-#define IMXRT1050_CLK_PLL5_REF_SEL 23
-#define IMXRT1050_CLK_PRE_PERIPH_SEL 24
-#define IMXRT1050_CLK_PERIPH_SEL 25
-#define IMXRT1050_CLK_SEMC_ALT_SEL 26
-#define IMXRT1050_CLK_SEMC_SEL 27
-#define IMXRT1050_CLK_USDHC1_SEL 28
-#define IMXRT1050_CLK_USDHC2_SEL 29
-#define IMXRT1050_CLK_LPUART_SEL 30
-#define IMXRT1050_CLK_LCDIF_SEL 31
-#define IMXRT1050_CLK_VIDEO_POST_DIV_SEL 32
-#define IMXRT1050_CLK_VIDEO_DIV 33
-#define IMXRT1050_CLK_ARM_PODF 34
-#define IMXRT1050_CLK_LPUART_PODF 35
-#define IMXRT1050_CLK_USDHC1_PODF 36
-#define IMXRT1050_CLK_USDHC2_PODF 37
-#define IMXRT1050_CLK_SEMC_PODF 38
-#define IMXRT1050_CLK_AHB_PODF 39
-#define IMXRT1050_CLK_LCDIF_PRED 40
-#define IMXRT1050_CLK_LCDIF_PODF 41
-#define IMXRT1050_CLK_USDHC1 42
-#define IMXRT1050_CLK_USDHC2 43
-#define IMXRT1050_CLK_LPUART1 44
-#define IMXRT1050_CLK_SEMC 45
-#define IMXRT1050_CLK_LCDIF_APB 46
-#define IMXRT1050_CLK_PLL1_ARM 47
-#define IMXRT1050_CLK_PLL2_SYS 48
-#define IMXRT1050_CLK_PLL3_USB_OTG 49
-#define IMXRT1050_CLK_PLL4_AUDIO 50
-#define IMXRT1050_CLK_PLL5_VIDEO 51
-#define IMXRT1050_CLK_PLL6_ENET 52
-#define IMXRT1050_CLK_PLL7_USB_HOST 53
-#define IMXRT1050_CLK_LCDIF_PIX 54
-#define IMXRT1050_CLK_USBOH3 55
-#define IMXRT1050_CLK_IPG_PDOF 56
-#define IMXRT1050_CLK_PER_CLK_SEL 57
-#define IMXRT1050_CLK_PER_PDOF 58
-#define IMXRT1050_CLK_DMA 59
-#define IMXRT1050_CLK_DMA_MUX 60
-#define IMXRT1050_CLK_END 61
-
-#endif /* __DT_BINDINGS_CLOCK_IMXRT1050_H */
--
2.43.0
^ permalink raw reply related
* [PATCH 03/11] ARM: imx: Remove NOMMU platform support
From: Frank.Li @ 2026-06-19 15:41 UTC (permalink / raw)
To: Arnd Bergmann, Sascha Hauer, Pengutronix Kernel Team,
Stefan Agner, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Russell King, Abel Vesa, Peng Fan,
Michael Turquette, Stephen Boyd, Brian Masney, Dong Aisheng,
Jacky Bai, NXP S32 Linux Team, Linus Walleij, Vladimir Zapolskiy,
Piotr Wojtaszczyk, Kees Cook, Gustavo A. R. Silva
Cc: linux-arm-kernel, imx, devicetree, linux-kernel, linux-clk,
linux-gpio, linux-hardening, Frank Li
In-Reply-To: <20260619-dts_cleanup_arm_mcore-v1-0-0101795a2662@nxp.com>
From: Frank Li <Frank.Li@nxp.com>
Commercial users and hardware vendors migrated to Zephyr or other RTOS
solutions years ago, leaving the NOMMU platform support effectively unused
and unmaintained.
Remove the obsolete support to reduce maintenance burden and simplify the
i.MX platform code.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm/mach-imx/Kconfig | 7 -------
arch/arm/mach-imx/Makefile | 2 --
arch/arm/mach-imx/mach-imxrt.c | 19 -------------------
3 files changed, 28 deletions(-)
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index a361840d7a047..081f08bb01ae1 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -213,13 +213,6 @@ config SOC_IMX7ULP
help
This enables support for Freescale i.MX7 Ultra Low Power processor.
-config SOC_IMXRT
- bool "i.MXRT support"
- depends on ARM_SINGLE_ARMV7M
- select ARMV7M_SYSTICK if ARM_SINGLE_ARMV7M
- help
- This enables support for Freescale i.MXRT Crossover processor.
-
config SOC_VF610
bool "Vybrid Family VF610 support"
select ARM_GIC if ARCH_MULTI_V7
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 5c650bf40e024..b14e9a0ec7501 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -60,8 +60,6 @@ obj-$(CONFIG_SOC_IMX50) += mach-imx50.o
obj-$(CONFIG_SOC_IMX51) += mach-imx51.o
obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
-obj-$(CONFIG_SOC_IMXRT) += mach-imxrt.o
-
obj-$(CONFIG_SOC_VF610) += mach-vf610.o
obj-$(CONFIG_SOC_LS1021A) += mach-ls1021a.o
diff --git a/arch/arm/mach-imx/mach-imxrt.c b/arch/arm/mach-imx/mach-imxrt.c
deleted file mode 100644
index 2063a3059c849..0000000000000
--- a/arch/arm/mach-imx/mach-imxrt.c
+++ /dev/null
@@ -1,19 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2019
- * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
- */
-
-#include <linux/kernel.h>
-#include <asm/mach/arch.h>
-#include <asm/v7m.h>
-
-static const char *const imxrt_compat[] __initconst = {
- "fsl,imxrt1050",
- NULL
-};
-
-DT_MACHINE_START(IMXRTDT, "IMXRT (Device Tree Support)")
- .dt_compat = imxrt_compat,
- .restart = armv7m_restart,
-MACHINE_END
--
2.43.0
^ permalink raw reply related
* [PATCH 01/11] ARM: dts: vf610m4: Remove NOMMU platform support
From: Frank.Li @ 2026-06-19 15:40 UTC (permalink / raw)
To: Arnd Bergmann, Sascha Hauer, Pengutronix Kernel Team,
Stefan Agner, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Russell King, Abel Vesa, Peng Fan,
Michael Turquette, Stephen Boyd, Brian Masney, Dong Aisheng,
Jacky Bai, NXP S32 Linux Team, Linus Walleij, Vladimir Zapolskiy,
Piotr Wojtaszczyk, Kees Cook, Gustavo A. R. Silva
Cc: linux-arm-kernel, imx, devicetree, linux-kernel, linux-clk,
linux-gpio, linux-hardening, Frank Li
In-Reply-To: <20260619-dts_cleanup_arm_mcore-v1-0-0101795a2662@nxp.com>
From: Frank Li <Frank.Li@nxp.com>
The Vybrid M4 NOMMU platform support was added as a proof-of-concept and
has not seen practical use in production systems.
Commercial users and hardware vendors migrated to Zephyr or other RTOS
solutions years ago, leaving the NOMMU platform support effectively
unused and unmaintained.
Remove the obsolete support to reduce maintenance burden and simplify the
code.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
Cc: Stefan Agner <stefan@agner.ch>
---
arch/arm/boot/dts/nxp/vf/Makefile | 2 -
arch/arm/boot/dts/nxp/vf/vf610m4-colibri.dts | 61 -------------------
arch/arm/boot/dts/nxp/vf/vf610m4-cosmic.dts | 88 ----------------------------
arch/arm/boot/dts/nxp/vf/vf610m4.dtsi | 61 -------------------
4 files changed, 212 deletions(-)
diff --git a/arch/arm/boot/dts/nxp/vf/Makefile b/arch/arm/boot/dts/nxp/vf/Makefile
index 0a4a7f9dd43e4..1733506c0c725 100644
--- a/arch/arm/boot/dts/nxp/vf/Makefile
+++ b/arch/arm/boot/dts/nxp/vf/Makefile
@@ -3,9 +3,7 @@ dtb-$(CONFIG_SOC_VF610) += \
vf500-colibri-eval-v3.dtb \
vf610-bk4.dtb \
vf610-colibri-eval-v3.dtb \
- vf610m4-colibri.dtb \
vf610-cosmic.dtb \
- vf610m4-cosmic.dtb \
vf610-twr.dtb \
vf610-zii-cfu1.dtb \
vf610-zii-dev-rev-b.dtb \
diff --git a/arch/arm/boot/dts/nxp/vf/vf610m4-colibri.dts b/arch/arm/boot/dts/nxp/vf/vf610m4-colibri.dts
deleted file mode 100644
index 86d32f54c250f..0000000000000
--- a/arch/arm/boot/dts/nxp/vf/vf610m4-colibri.dts
+++ /dev/null
@@ -1,61 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
-/*
- * Device tree for Colibri VF61 Cortex-M4 support
- *
- * Copyright (C) 2015 Stefan Agner
- */
-
-/dts-v1/;
-#include "vf610m4.dtsi"
-
-/ {
- model = "VF610 Cortex-M4";
- compatible = "fsl,vf610m4";
-
- chosen {
- bootargs = "clk_ignore_unused init=/linuxrc rw";
- stdout-path = "serial2:115200";
- };
-
- memory@8c000000 {
- device_type = "memory";
- reg = <0x8c000000 0x3000000>;
- };
-};
-
-&gpio0 {
- status = "disabled";
-};
-
-&gpio1 {
- status = "disabled";
-};
-
-&gpio2 {
- status = "disabled";
-};
-
-&gpio3 {
- status = "disabled";
-};
-
-&gpio4 {
- status = "disabled";
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- VF610_PAD_PTD0__UART2_TX 0x21a2
- VF610_PAD_PTD1__UART2_RX 0x21a1
- VF610_PAD_PTD2__UART2_RTS 0x21a2
- VF610_PAD_PTD3__UART2_CTS 0x21a1
- >;
- };
-};
diff --git a/arch/arm/boot/dts/nxp/vf/vf610m4-cosmic.dts b/arch/arm/boot/dts/nxp/vf/vf610m4-cosmic.dts
deleted file mode 100644
index 454b484368cb7..0000000000000
--- a/arch/arm/boot/dts/nxp/vf/vf610m4-cosmic.dts
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * Device tree for Cosmic+ VF6xx Cortex-M4 support
- *
- * Copyright (C) 2015
- *
- * Based on vf610m4 Colibri
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-#include "vf610m4.dtsi"
-
-/ {
- model = "VF610 Cortex-M4";
- compatible = "fsl,vf610m4";
-};
-
-&gpio0 {
- status = "disabled";
-};
-
-&gpio1 {
- status = "disabled";
-};
-
-&gpio2 {
- status = "disabled";
-};
-
-&gpio3 {
- status = "disabled";
-};
-
-&gpio4 {
- status = "disabled";
-};
-
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl_uart3: uart3grp {
- fsl,pins = <
- VF610_PAD_PTA20__UART3_TX 0x21a2
- VF610_PAD_PTA21__UART3_RX 0x21a1
- >;
- };
-};
diff --git a/arch/arm/boot/dts/nxp/vf/vf610m4.dtsi b/arch/arm/boot/dts/nxp/vf/vf610m4.dtsi
deleted file mode 100644
index 648d219e1d0ed..0000000000000
--- a/arch/arm/boot/dts/nxp/vf/vf610m4.dtsi
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * Device tree for VF6xx Cortex-M4 support
- *
- * Copyright (C) 2015 Stefan Agner
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include "../../armv7-m.dtsi"
-#include "vfxxx.dtsi"
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
- chosen { };
- aliases { };
-};
-
-&mscm_ir {
- interrupt-parent = <&nvic>;
-};
-
-&nvic {
- arm,num-irq-priority-bits = <4>;
-};
--
2.43.0
^ permalink raw reply related
* [PATCH 00/11] ARM: NXP: Drop NOMMU platform support
From: Frank.Li @ 2026-06-19 15:40 UTC (permalink / raw)
To: Arnd Bergmann, Sascha Hauer, Pengutronix Kernel Team,
Stefan Agner, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Russell King, Abel Vesa, Peng Fan,
Michael Turquette, Stephen Boyd, Brian Masney, Dong Aisheng,
Jacky Bai, NXP S32 Linux Team, Linus Walleij, Vladimir Zapolskiy,
Piotr Wojtaszczyk, Kees Cook, Gustavo A. R. Silva
Cc: linux-arm-kernel, imx, devicetree, linux-kernel, linux-clk,
linux-gpio, linux-hardening, Frank Li
Commercial users and hardware vendors migrated to Zephyr or other RTOS
solutions years ago, leaving the NOMMU platform support effectively
unused and unmaintained.
Remove the obsolete support to reduce maintenance burden and simplify the
Freescale/nxp platform code.
Some driver code still be kept and may clean up later since it is possible
reused by other SoC.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
Frank Li (11):
ARM: dts: vf610m4: Remove NOMMU platform support
ARM: dts: imxrt1050: Remove NOMMU platform support
ARM: imx: Remove NOMMU platform support
clk: imx: imxrt1050: Remove NOMMU platform support
pinctrl: freescale: IMXRT: Remove NOMMU platform support
ARM: imxrt_defconfig: Remove NOMMU platform support
ARM: dts: lpc: Remove NOMMU platform support
ARM: mach-lpc: Remove NOMMU platform support
ARM: configs: lpc*: Remove NOMMU platform support
clk: nxp: lpc: Remove NOMMU platform support
pinctrl: nxp: lpc: Remove NOMMU platform support
.../devicetree/bindings/pinctrl/fsl,imxrt1050.yaml | 79 -
.../devicetree/bindings/pinctrl/fsl,imxrt1170.yaml | 77 -
arch/arm/Kconfig | 12 -
arch/arm/Makefile | 2 -
arch/arm/boot/dts/nxp/Makefile | 1 -
arch/arm/boot/dts/nxp/imx/Makefile | 2 -
arch/arm/boot/dts/nxp/imx/imxrt1050-evk.dts | 72 -
arch/arm/boot/dts/nxp/imx/imxrt1050-pinfunc.h | 993 ------------
arch/arm/boot/dts/nxp/imx/imxrt1050.dtsi | 160 --
arch/arm/boot/dts/nxp/imx/imxrt1170-pinfunc.h | 1561 -------------------
arch/arm/boot/dts/nxp/lpc/Makefile | 9 -
arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi | 543 -------
arch/arm/boot/dts/nxp/lpc/lpc3250-ea3250.dts | 273 ----
arch/arm/boot/dts/nxp/lpc/lpc3250-phy3250.dts | 236 ---
arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 540 -------
arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dts | 221 ---
arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts | 485 ------
arch/arm/boot/dts/nxp/lpc/lpc4350.dtsi | 48 -
.../arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts | 624 --------
arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts | 621 --------
arch/arm/boot/dts/nxp/lpc/lpc4357.dtsi | 52 -
arch/arm/boot/dts/nxp/vf/Makefile | 2 -
arch/arm/boot/dts/nxp/vf/vf610m4-colibri.dts | 61 -
arch/arm/boot/dts/nxp/vf/vf610m4-cosmic.dts | 88 --
arch/arm/boot/dts/nxp/vf/vf610m4.dtsi | 61 -
arch/arm/configs/imxrt_defconfig | 35 -
arch/arm/configs/lpc18xx_defconfig | 158 --
arch/arm/configs/lpc32xx_defconfig | 192 ---
arch/arm/mach-imx/Kconfig | 7 -
arch/arm/mach-imx/Makefile | 2 -
arch/arm/mach-imx/mach-imxrt.c | 19 -
arch/arm/mach-lpc18xx/Makefile | 2 -
arch/arm/mach-lpc18xx/board-dt.c | 19 -
arch/arm/mach-lpc32xx/Kconfig | 13 -
arch/arm/mach-lpc32xx/Makefile | 8 -
arch/arm/mach-lpc32xx/common.c | 125 --
arch/arm/mach-lpc32xx/common.h | 32 -
arch/arm/mach-lpc32xx/lpc32xx.h | 717 ---------
arch/arm/mach-lpc32xx/phy3250.c | 92 --
arch/arm/mach-lpc32xx/pm.c | 135 --
arch/arm/mach-lpc32xx/serial.c | 148 --
arch/arm/mach-lpc32xx/suspend.S | 148 --
drivers/clk/Kconfig | 7 -
drivers/clk/Makefile | 1 -
drivers/clk/imx/Kconfig | 6 -
drivers/clk/imx/Makefile | 1 -
drivers/clk/imx/clk-imxrt1050.c | 182 ---
drivers/clk/nxp/Makefile | 5 -
drivers/clk/nxp/clk-lpc18xx-ccu.c | 301 ----
drivers/clk/nxp/clk-lpc18xx-cgu.c | 668 --------
drivers/clk/nxp/clk-lpc18xx-creg.c | 225 ---
drivers/clk/nxp/clk-lpc32xx.c | 1591 --------------------
drivers/pinctrl/Kconfig | 9 -
drivers/pinctrl/Makefile | 1 -
drivers/pinctrl/freescale/Kconfig | 16 -
drivers/pinctrl/freescale/Makefile | 2 -
drivers/pinctrl/freescale/pinctrl-imxrt1050.c | 309 ----
drivers/pinctrl/freescale/pinctrl-imxrt1170.c | 349 -----
drivers/pinctrl/pinctrl-lpc18xx.c | 1382 -----------------
include/dt-bindings/clock/imxrt1050-clock.h | 72 -
60 files changed, 13802 deletions(-)
---
base-commit: 598c7067dd8b65b93f3ccada47e9014a13137f1b
change-id: 20260618-dts_cleanup_arm_mcore-e7e933da798a
Best regards,
--
Frank Li <Frank.Li@nxp.com>
^ permalink raw reply
* Re: [PATCH v4 4/6] arm64: dts: qcom: shikra: Add pin configuration for mclks
From: Konrad Dybcio @ 2026-06-19 15:36 UTC (permalink / raw)
To: Nihal Kumar Gupta, Bryan O'Donoghue, Vladimir Zapolskiy,
Loic Poulain, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Robert Foss, Andi Shyti,
Bryan O'Donoghue, Bjorn Andersson, Konrad Dybcio, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel, linux-i2c,
imx, linux-arm-kernel, Suresh Vankadara, Vikram Sharma
In-Reply-To: <20260615-shikra-camss-review-v4-4-bcb51081735b@oss.qualcomm.com>
On 6/15/26 10:33 AM, Nihal Kumar Gupta wrote:
> Add pinctrl configuration for the four available camera master clocks.
>
> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
> Signed-off-by: Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/shikra.dtsi | 28 ++++++++++++++++++++++++++++
> 1 file changed, 28 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
> index 57732804a6c6a114a407a4a541a1cc7af7635ea2..16b547131e8b14541abc68ff7cda126ba777ad80 100644
> --- a/arch/arm64/boot/dts/qcom/shikra.dtsi
> +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
> @@ -380,6 +380,34 @@ cci_i2c1_sleep: cci-i2c1-sleep-state {
> bias-pull-down;
> };
>
> + cam_mclk0_default: cam-mclk0-default-state {
> + pins = "gpio34";
> + function = "cam_mclk";
> + drive-strength = <2>;
> + bias-disable;
> + };
> +
> + cam_mclk1_default: cam-mclk1-default-state {
> + pins = "gpio35";
> + function = "cam_mclk";
> + drive-strength = <2>;
> + bias-disable;
> + };
> +
> + cam_mclk2_default: cam-mclk2-default-state {
> + pins = "gpio96";
> + function = "cam_mclk";
> + drive-strength = <2>;
> + bias-disable;
> + };
> +
> + cam_mclk3_default: cam-mclk3-default-state {
> + pins = "gpio98";
> + function = "cam_mclk";
> + drive-strength = <2>;
> + bias-disable;
> + };
Please try to keep the entries roughly sorted by the pin index
For the entries themselves:
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply
* Re: [PATCH v2] arm64: tlbflush: Don't broadcast if mm was only active on local cpu
From: Will Deacon @ 2026-06-19 15:34 UTC (permalink / raw)
To: Ryan Roberts
Cc: Linu Cherian, Catalin Marinas, Kevin Brodsky, Anshuman Khandual,
Yang Shi, Mark Rutland, Huang Ying, linux-arm-kernel,
linux-kernel, shameerali.kolothum.thodi
In-Reply-To: <4aa78619-5a79-4fd0-aaac-a990b8c3fd05@arm.com>
On Mon, Jun 15, 2026 at 04:41:04PM +0100, Ryan Roberts wrote:
> On 15/06/2026 15:43, Will Deacon wrote:
> > On Mon, Jun 15, 2026 at 12:21:19PM +0100, Ryan Roberts wrote:
> >>>> + self = smp_processor_id();
> >>>> +
> >>>> + /*
> >>>> + * The load of mm->context.active_cpu must not be reordered before the
> >>>> + * store to the pgtable that necessitated this flush. This ensures that
> >>>> + * if the value read is our cpu id, then no other cpu can have seen the
> >>>> + * old pgtable value and therefore does not need this old value to be
> >>>> + * flushed from its tlb. But we don't want to upgrade the dsb(ishst),
> >>>> + * needed to make the pgtable updates visible to the walker, to a
> >>>> + * dsb(ish) by default. So speculatively load without a barrier and if
> >>>> + * it indicates our cpu id, then upgrade the barrier and re-load.
> >>>> + */
> >>>> + active = READ_ONCE(mm->context.active_cpu);
> >>>> + if (active == self) {
> >>>> + dsb(ish);
> >>>> + active = READ_ONCE(mm->context.active_cpu);
> >>>> + } else {
> >>>> + dsb(ishst);
> >>>> + }
> >>>
> >>> Why can't you just do:
> >>>
> >>> dsb(ishst);
> >>> active = READ_ONCE(mm->context.active_cpu);
> >>>
> >>> ?
> >>
> >> Prior to this optimization, we always issued a dsb(ishst) here. Catalin
> >> suggested the same simplification against the RFC. I believe Linu tried it but
> >> saw regressions; Hopefully Linu can provide the details.
> >
> > I don't follow...
> >
> > The old code always did dsb(ishst). The proposed code here does either
> > dsb(ish) or dsb(ishst). How can that possibly be faster?
>
> Ugh, sorry - I read your suggestion as unconditionally issuing a dsb(ish).
>
> Ignore my previous answer, and now I'll demonstrate my total lack of
> understanding of barriers instead...
>
> As the comment says, "The load of mm->context.active_cpu must not be reordered
> before the store to the pgtable that necessitated this flush". I thought that a
> dsb(ishst) would only provide ordering between stores. Don't we need the
> dsb(ish) to prevent the load from being reordered before the store?
dsb(ishst) orders prior stores -> everything later. That's why it works
today for ordered a PTE write before a TLBI (which isn't a store).
Will
^ permalink raw reply
* [PATCH v6 18/23] phy: rockchip: usbdp: Re-init the PHY on orientation change
From: Sebastian Reichel @ 2026-06-19 15:29 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Heiko Stuebner, Frank Wang,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Andy Yan, Dmitry Baryshkov, Yubing Zhang, Alexey Charkov,
linux-phy, linux-arm-kernel, linux-rockchip, linux-kernel, kernel,
devicetree, Sebastian Reichel
In-Reply-To: <20260619-rockchip-usbdp-cleanup-v6-0-3bb1f54b3f35@collabora.com>
Changing the cable orientation reconfigures the lane muxing, which
requires re-initializing the PHY. Without this DP functionality
breaks, if the cable is re-plugged with swapped orientation.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/phy/rockchip/phy-rockchip-usbdp.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c
index c210aaeb283a..402f3cafcf0a 100644
--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
@@ -622,6 +622,7 @@ static int rk_udphy_orien_sw_set(struct typec_switch_dev *sw,
enum typec_orientation orien)
{
struct rk_udphy *udphy = typec_switch_get_drvdata(sw);
+ bool flipped = orien == TYPEC_ORIENTATION_REVERSE;
mutex_lock(&udphy->mutex);
@@ -633,7 +634,10 @@ static int rk_udphy_orien_sw_set(struct typec_switch_dev *sw,
goto unlock_ret;
}
- udphy->flip = orien == TYPEC_ORIENTATION_REVERSE;
+ if (udphy->flip != flipped)
+ udphy->phy_needs_reinit = true;
+
+ udphy->flip = flipped;
rk_udphy_set_typec_default_mapping(udphy);
rk_udphy_usb_bvalid_enable(udphy, true);
--
2.53.0
^ permalink raw reply related
* [PATCH v6 21/23] phy: rockchip: usbdp: Support going from DP-only mode to USB mode
From: Sebastian Reichel @ 2026-06-19 15:29 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Heiko Stuebner, Frank Wang,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Andy Yan, Dmitry Baryshkov, Yubing Zhang, Alexey Charkov,
linux-phy, linux-arm-kernel, linux-rockchip, linux-kernel, kernel,
devicetree, Sebastian Reichel
In-Reply-To: <20260619-rockchip-usbdp-cleanup-v6-0-3bb1f54b3f35@collabora.com>
When a USB-C adapter, which maps all Superspeed lanes to DP is plugged
in, the USB support is disabled in the PHY. When the adapter is
unplugged and a different adapter with USB functionality is plugged in
afterwards, USB functionality is not restored as the USB controller
keeps the PHY enabled for the entire time.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/phy/rockchip/phy-rockchip-usbdp.c | 29 ++++++++++++++++++++++++++++-
1 file changed, 28 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c
index 81aae3bc5747..7f26b74cb515 100644
--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
@@ -178,6 +178,7 @@ struct rk_udphy {
/* utilized for USB */
bool hs; /* flag for high-speed */
+ bool usb_in_use;
/* utilized for DP */
struct gpio_desc *sbu1_dc_gpio;
@@ -1015,6 +1016,10 @@ static int rk_udphy_power_on(struct rk_udphy *udphy, u8 mode)
ret = rk_udphy_init(udphy);
if (ret)
return ret;
+
+ if (udphy->mode & UDPHY_MODE_USB)
+ rk_udphy_u3_port_disable(udphy, false);
+
udphy->phy_needs_reinit = false;
}
@@ -1278,6 +1283,7 @@ static const struct phy_ops rk_udphy_dp_phy_ops = {
static int rk_udphy_usb3_phy_init(struct phy *phy)
{
struct rk_udphy *udphy = phy_get_drvdata(phy);
+ int ret;
guard(mutex)(&udphy->mutex);
@@ -1287,7 +1293,13 @@ static int rk_udphy_usb3_phy_init(struct phy *phy)
return 0;
}
- return rk_udphy_power_on(udphy, UDPHY_MODE_USB);
+ ret = rk_udphy_power_on(udphy, UDPHY_MODE_USB);
+ if (ret)
+ return ret;
+
+ udphy->usb_in_use = true;
+
+ return 0;
}
static int rk_udphy_usb3_phy_exit(struct phy *phy)
@@ -1296,6 +1308,8 @@ static int rk_udphy_usb3_phy_exit(struct phy *phy)
guard(mutex)(&udphy->mutex);
+ udphy->usb_in_use = false;
+
/* DP only or high-speed */
if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs)
return 0;
@@ -1315,6 +1329,7 @@ static int rk_udphy_typec_mux_set(struct typec_mux_dev *mux,
struct typec_mux_state *state)
{
struct rk_udphy *udphy = typec_mux_get_drvdata(mux);
+ u8 old_mode;
/*
* Ignore mux events not involving DP AltMode, because
@@ -1326,8 +1341,20 @@ static int rk_udphy_typec_mux_set(struct typec_mux_dev *mux,
guard(mutex)(&udphy->mutex);
+ old_mode = udphy->mode;
+
rk_udphy_set_typec_state(udphy, state->mode);
+ /*
+ * If the new mode includes USB but the old one didn't (e.g. leaving
+ * DP-only), and the USB PHY was already initialized by the USB
+ * controller, we need to power on the USB side now since no
+ * subsequent phy_init call will come from the controller.
+ */
+ if ((udphy->mode & UDPHY_MODE_USB) && !(old_mode & UDPHY_MODE_USB) &&
+ udphy->usb_in_use && !udphy->hs)
+ return rk_udphy_power_on(udphy, UDPHY_MODE_USB);
+
return 0;
}
--
2.53.0
^ permalink raw reply related
* [PATCH v6 16/23] phy: rockchip: usbdp: Drop DP HPD handling
From: Sebastian Reichel @ 2026-06-19 15:29 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Heiko Stuebner, Frank Wang,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Andy Yan, Dmitry Baryshkov, Yubing Zhang, Alexey Charkov,
linux-phy, linux-arm-kernel, linux-rockchip, linux-kernel, kernel,
devicetree, Sebastian Reichel
In-Reply-To: <20260619-rockchip-usbdp-cleanup-v6-0-3bb1f54b3f35@collabora.com>
Drop the HPD handling logic from the USBDP PHY. The registers involved
require the display controller power domain being enabled and thus the
HPD signal should be handled by the displayport controller itself.
Apart from that the HPD handling as it is done here is incorrect and
misses hotplug events happening after the USB-C connector (e.g. when
a USB-C to HDMI adapter is involved and the HDMI cable is replugged).
Proper USB-C DP HPD support requires some restructuring of the DP
controller driver, which will happen independent of this patch. The
mainline kernel does not yet support USB-C DP AltMode on RK3588 and
RK3576, so it is fine to drop this code without adding the counterpart
in the DRM in an atomic change.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/phy/rockchip/phy-rockchip-usbdp.c | 85 ++++---------------------------
1 file changed, 9 insertions(+), 76 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c
index b75c190a4311..383e68b24506 100644
--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
@@ -128,7 +128,6 @@ struct rk_udphy_grf_cfg {
struct rk_udphy_vogrf_cfg {
/* vo-grf */
- struct rk_udphy_grf_reg hpd_trigger;
u32 dp_lane_reg;
};
@@ -186,14 +185,11 @@ struct rk_udphy {
u32 dp_lane_sel[4];
u32 dp_aux_dout_sel;
u32 dp_aux_din_sel;
- bool dp_sink_hpd_sel;
- bool dp_sink_hpd_cfg;
unsigned int link_rate;
unsigned int lanes;
u8 bw;
int id;
- bool dp_in_use;
int dp_lanes;
/* PHY const config */
@@ -579,19 +575,6 @@ static void rk_udphy_dp_lane_enable(struct rk_udphy *udphy, int dp_lanes)
CMN_DP_CMN_RSTN, FIELD_PREP(CMN_DP_CMN_RSTN, 0x0));
}
-static void rk_udphy_dp_hpd_event_trigger(struct rk_udphy *udphy, bool hpd)
-{
- const struct rk_udphy_cfg *cfg = udphy->cfgs;
-
- udphy->dp_sink_hpd_sel = true;
- udphy->dp_sink_hpd_cfg = hpd;
-
- if (!udphy->dp_in_use)
- return;
-
- rk_udphy_grfreg_write(udphy->vogrf, &cfg->vogrfcfg[udphy->id].hpd_trigger, hpd);
-}
-
static void rk_udphy_mode_set(struct rk_udphy *udphy, u8 mode)
{
if (udphy->mode == mode)
@@ -1024,29 +1007,6 @@ static void rk_udphy_power_off(struct rk_udphy *udphy, u8 mode)
rk_udphy_disable(udphy);
}
-static int rk_udphy_dp_phy_init(struct phy *phy)
-{
- struct rk_udphy *udphy = phy_get_drvdata(phy);
-
- mutex_lock(&udphy->mutex);
-
- udphy->dp_in_use = true;
-
- mutex_unlock(&udphy->mutex);
-
- return 0;
-}
-
-static int rk_udphy_dp_phy_exit(struct phy *phy)
-{
- struct rk_udphy *udphy = phy_get_drvdata(phy);
-
- mutex_lock(&udphy->mutex);
- udphy->dp_in_use = false;
- mutex_unlock(&udphy->mutex);
- return 0;
-}
-
static int rk_udphy_dp_phy_power_on(struct phy *phy)
{
struct rk_udphy *udphy = phy_get_drvdata(phy);
@@ -1278,8 +1238,6 @@ static int rk_udphy_dp_phy_configure(struct phy *phy,
}
static const struct phy_ops rk_udphy_dp_phy_ops = {
- .init = rk_udphy_dp_phy_init,
- .exit = rk_udphy_dp_phy_exit,
.power_on = rk_udphy_dp_phy_power_on,
.power_off = rk_udphy_dp_phy_power_off,
.configure = rk_udphy_dp_phy_configure,
@@ -1333,6 +1291,14 @@ static int rk_udphy_typec_mux_set(struct typec_mux_dev *mux,
struct rk_udphy *udphy = typec_mux_get_drvdata(mux);
u8 mode;
+ /*
+ * Ignore mux events not involving DP AltMode, because
+ * the mode field is being reused, e.g. state->mode == 4
+ * could be either TYPEC_MODE_USB4 or TYPEC_DP_STATE_C.
+ */
+ if (!state->alt || state->alt->svid != USB_TYPEC_DP_SID)
+ return 0;
+
mutex_lock(&udphy->mutex);
switch (state->mode) {
@@ -1364,22 +1330,7 @@ static int rk_udphy_typec_mux_set(struct typec_mux_dev *mux,
break;
}
- if (state->alt && state->alt->svid == USB_TYPEC_DP_SID) {
- struct typec_displayport_data *data = state->data;
-
- if (!data) {
- rk_udphy_dp_hpd_event_trigger(udphy, false);
- } else if (data->status & DP_STATUS_IRQ_HPD) {
- rk_udphy_dp_hpd_event_trigger(udphy, false);
- usleep_range(750, 800);
- rk_udphy_dp_hpd_event_trigger(udphy, true);
- } else if (data->status & DP_STATUS_HPD_STATE) {
- rk_udphy_mode_set(udphy, mode);
- rk_udphy_dp_hpd_event_trigger(udphy, true);
- } else {
- rk_udphy_dp_hpd_event_trigger(udphy, false);
- }
- }
+ rk_udphy_mode_set(udphy, mode);
mutex_unlock(&udphy->mutex);
return 0;
@@ -1535,20 +1486,6 @@ static int rk_udphy_probe(struct platform_device *pdev)
return 0;
}
-static int __maybe_unused rk_udphy_resume(struct device *dev)
-{
- struct rk_udphy *udphy = dev_get_drvdata(dev);
-
- if (udphy->dp_sink_hpd_sel)
- rk_udphy_dp_hpd_event_trigger(udphy, udphy->dp_sink_hpd_cfg);
-
- return 0;
-}
-
-static const struct dev_pm_ops rk_udphy_pm_ops = {
- SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, rk_udphy_resume)
-};
-
static const char * const rk_udphy_rst_list[] = {
"init", "cmn", "lane", "pcs_apb", "pma_apb"
};
@@ -1572,7 +1509,6 @@ static const struct rk_udphy_cfg rk3576_udphy_cfgs = {
},
.vogrfcfg = {
{
- .hpd_trigger = RK_UDPHY_GEN_GRF_REG(0x0000, 11, 10, 1, 3),
.dp_lane_reg = 0x0000,
},
},
@@ -1613,11 +1549,9 @@ static const struct rk_udphy_cfg rk3588_udphy_cfgs = {
},
.vogrfcfg = {
{
- .hpd_trigger = RK_UDPHY_GEN_GRF_REG(0x0000, 11, 10, 1, 3),
.dp_lane_reg = 0x0000,
},
{
- .hpd_trigger = RK_UDPHY_GEN_GRF_REG(0x0008, 11, 10, 1, 3),
.dp_lane_reg = 0x0008,
},
},
@@ -1653,7 +1587,6 @@ static struct platform_driver rk_udphy_driver = {
.driver = {
.name = "rockchip-usbdp-phy",
.of_match_table = rk_udphy_dt_match,
- .pm = &rk_udphy_pm_ops,
},
};
module_platform_driver(rk_udphy_driver);
--
2.53.0
^ permalink raw reply related
* Re: [PATCH v2 0/3] arm64: perf: Skip device memory during user callchain unwinding
From: Will Deacon @ 2026-06-19 15:31 UTC (permalink / raw)
To: Fredrik Markstrom
Cc: Catalin Marinas, Shuah Khan, Peter Zijlstra, Ingo Molnar,
Arnaldo Carvalho de Melo, Namhyung Kim, Mark Rutland,
Alexander Shishkin, Jiri Olsa, Ian Rogers, Adrian Hunter,
James Clark, Santosh Shilimkar, Olof Johansson, Tony Lindgren,
linux-arm-kernel, linux-kernel, linux-kselftest, linux-perf-users,
Nicolas Pitre, Ivar Holmqvist, Malin Jonsson
In-Reply-To: <agweYAbxRWOs41BE@elx-5cg6022w5t>
On Tue, May 19, 2026 at 10:25:04AM +0200, Fredrik Markstrom wrote:
> On Mon, May 18, 2026 at 04:06:11PM +0100, Will Deacon wrote:
> > On Thu, Apr 30, 2026 at 12:55:12PM +0200, Fredrik Markstrom wrote:
> > > Perf callchain unwinding follows userspace frame pointers via
> > > copy_from_user. A corrupted or malicious frame pointer can point
> > > into device I/O memory mapped into the process (e.g. via UIO or
> > > /dev/mem), causing the kernel to read from MMIO regions in PMU
> > > interrupt context. Such reads can have side effects on hardware
> > > (clearing status registers, advancing FIFOs, triggering DMA) and
> > > on arm64 can produce a synchronous external abort that panics the
> > > kernel.
> >
> > Hmm, but why is unwinding special in this case? If userspace has access
> > to sensitive MMIO/device mappings, it can presumably pass them to
> > syscalls and trigger crashes all over the place?
>
> You’re totally right, a broken app with access to hardware like this can
> already cause chaos by passing bad pointers to syscalls etc. But the big
> difference here is who is to blame when things crash.
>
> If an app passes a bad pointer to a syscall, it’s self-inflicted.
So I was going to argue that building arm64 code without frame-pointers
is self-inflicted, but it looks like that's the default in GCC for some
bizarre reason.
> Unwinding here is asynchronous and unrelated to the application.
> Perf interrupts a perfectly healthy app at a random moment. If that app
> is using the frame pointer as a normal register (totally legal in
> optimized code), it might hold a junk value that points to MMIO memory.
>
> If the kernel blindly follows that junk pointer during an unwind, perf
> causes the crash. I think it's acceptable that an app (with hardware
> access) causes a crash if buggy, but I don't think it's acceptable that
> a profiling tool is causing a crash just by looking at it.
I can see your argument, but I'm also not hugely keen to add fastgup to
our stack unwinder for each frame record. It's also not clear to me how
you avoid the mapping changing between the check and the access, given
that you still appear to use the user mapping for the unwind. Do other
architectures have this issue and, if so, how do they solve it?
If we could guarantee that the fault is synchronous, then we could
presumably hook up the uaccess exception fixup handlers.
Will
^ permalink raw reply
* Re: [PATCH v7 0/2] PCI: Configure Root Port MPS during host probing
From: Hans Zhang @ 2026-06-19 15:29 UTC (permalink / raw)
To: bhelgaas, Manivannan Sadhasivam, Bjorn Helgaas
Cc: lpieralisi, kwilczynski, heiko, yue.wang, pali, neil.armstrong,
robh, jingoohan1, khilman, jbrunet, martin.blumenstingl, cassel,
linux-pci, linux-kernel, linux-arm-kernel, linux-amlogic,
linux-rockchip
In-Reply-To: <vpuzlzry7uulctur7kwtlogniuhogd5ybmrwjtos2v7yryf47v@yj2ocobbog6s>
On 5/6/26 22:00, Manivannan Sadhasivam wrote:
> On Fri, Nov 28, 2025 at 01:09:06AM +0800, Hans Zhang wrote:
>> Current PCIe initialization exhibits a key optimization gap: Root Ports
>> may operate with non-optimal Maximum Payload Size (MPS) settings. While
>> downstream device configuration is handled during bus enumeration, Root
>> Port MPS values inherited from firmware or hardware defaults often fail
>> to utilize the full capabilities supported by controller hardware. This
>> results in suboptimal data transfer efficiency throughout the PCIe
>> hierarchy.
>>
>> This patch series addresses this by:
>>
>> 1. Core PCI enhancement (Patch 1):
>> - Proactively configures Root Port MPS during host controller probing
>> - Sets initial MPS to hardware maximum (128 << dev->pcie_mpss)
>> - Conditional on PCIe bus tuning being enabled (PCIE_BUS_TUNE_OFF unset)
>> and not in PCIE_BUS_PEER2PEER mode (which requires default 128 bytes)
>> - Maintains backward compatibility via PCIE_BUS_TUNE_OFF check
>> - Preserves standard MPS negotiation during downstream enumeration
>>
>> 2. Driver cleanup (Patch 2):
>> - Removes redundant MPS configuration from Meson PCIe controller driver
>> - Functionality is now centralized in PCI core
>> - Simplifies driver maintenance long-term
>>
>
> For the series,
>
> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
>
> Bjorn: Could you please take a look? This series has been floating for a
> while...
Hello Bjorn,
Any chance for this series to be applied?
Best regards,
Hans
>
> - Mani
>
>> ---
>> Changes in v7:
>> - Exclude PCIE_BUS_PEER2PEER mode from Root Port MPS configuration
>> - Remove redundant check for upstream bridge (Root Ports don't have one)
>> - Improve commit message and code comments as per Bjorn.
>>
>> Changes for v6:
>> https://patchwork.kernel.org/project/linux-pci/patch/20251104165125.174168-1-18255117159@163.com/
>>
>> - Modify the commit message and comments. (Bjorn)
>> - Patch 1/2 code logic: Add !bridge check to configure MPS only for Root Ports
>> without an upstream bridge (root bridges), avoiding incorrect handling of
>> non-root-bridge Root Ports (Niklas).
>>
>> Changes for v5:
>> https://patchwork.kernel.org/project/linux-pci/patch/20250620155507.1022099-1-18255117159@163.com/
>>
>> - Use pcie_set_mps directly instead of pcie_write_mps.
>> - The patch 1 commit message were modified.
>>
>> Changes for v4:
>> https://patchwork.kernel.org/project/linux-pci/patch/20250510155607.390687-1-18255117159@163.com/
>>
>> - The patch [v4 1/2] add a comment to explain why it was done this way.
>> - The patch [v4 2/2] have not been modified.
>> - Drop patch [v3 3/3]. The Maintainer of the pci-aardvark.c file suggests
>> that this patch cannot be submitted. In addition, Mani also suggests
>> dropping this patch until this series of issues is resolved.
>>
>> Changes for v3:
>> https://patchwork.kernel.org/project/linux-pci/patch/20250506173439.292460-1-18255117159@163.com/
>>
>> - The new split is patch 2/3 and 3/3.
>> - Modify the patch 1/3 according to Niklas' suggestion.
>>
>> Changes for v2:
>> https://patchwork.kernel.org/project/linux-pci/patch/20250425095708.32662-1-18255117159@163.com/
>>
>> - According to the Maintainer's suggestion, limit the setting of MPS
>> changes to platforms with controller drivers.
>> - Delete the MPS code set by the SOC manufacturer.
>> ---
>>
>> Hans Zhang (2):
>> PCI: Configure Root Port MPS during host probing
>> PCI: dwc: Remove redundant MPS configuration
>>
>> drivers/pci/controller/dwc/pci-meson.c | 17 -----------------
>> drivers/pci/probe.c | 12 ++++++++++++
>> 2 files changed, 12 insertions(+), 17 deletions(-)
>>
>>
>> base-commit: 765e56e41a5af2d456ddda6cbd617b9d3295ab4e
>> --
>> 2.34.1
>>
>
^ permalink raw reply
* [PATCH v6 20/23] phy: rockchip: usbdp: Use guard functions for mutex
From: Sebastian Reichel @ 2026-06-19 15:29 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Heiko Stuebner, Frank Wang,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Andy Yan, Dmitry Baryshkov, Yubing Zhang, Alexey Charkov,
linux-phy, linux-arm-kernel, linux-rockchip, linux-kernel, kernel,
devicetree, Sebastian Reichel
In-Reply-To: <20260619-rockchip-usbdp-cleanup-v6-0-3bb1f54b3f35@collabora.com>
Convert the driver to use guard functions for mutex handling as
a small cleanup. There is a small functional change in the DP PHY
power up function, which no longer sleeps if the internal powerup
code returns an error. This is not a problem as the sleep is only
relevant for successful power-up.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/phy/rockchip/phy-rockchip-usbdp.c | 54 +++++++++++++------------------
1 file changed, 23 insertions(+), 31 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c
index 46ab9fb45ca4..81aae3bc5747 100644
--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
@@ -10,6 +10,7 @@
#include <dt-bindings/phy/phy.h>
#include <linux/bitfield.h>
#include <linux/bits.h>
+#include <linux/cleanup.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/gpio.h>
@@ -652,14 +653,15 @@ static int rk_udphy_orien_sw_set(struct typec_switch_dev *sw,
struct rk_udphy *udphy = typec_switch_get_drvdata(sw);
bool flipped = orien == TYPEC_ORIENTATION_REVERSE;
- mutex_lock(&udphy->mutex);
+ guard(mutex)(&udphy->mutex);
if (orien == TYPEC_ORIENTATION_NONE) {
gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 0);
gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 0);
/* unattached */
rk_udphy_usb_bvalid_enable(udphy, false);
- goto unlock_ret;
+
+ return 0;
}
if (udphy->flip != flipped)
@@ -669,8 +671,6 @@ static int rk_udphy_orien_sw_set(struct typec_switch_dev *sw,
rk_udphy_set_typec_default_mapping(udphy);
rk_udphy_usb_bvalid_enable(udphy, true);
-unlock_ret:
- mutex_unlock(&udphy->mutex);
return 0;
}
@@ -1044,26 +1044,25 @@ static int rk_udphy_dp_phy_power_on(struct phy *phy)
struct rk_udphy *udphy = phy_get_drvdata(phy);
int ret;
- mutex_lock(&udphy->mutex);
+ scoped_guard(mutex, &udphy->mutex) {
+ phy_set_bus_width(phy, udphy->dp_lanes);
- phy_set_bus_width(phy, udphy->dp_lanes);
-
- ret = rk_udphy_power_on(udphy, UDPHY_MODE_DP);
- if (ret)
- goto unlock;
+ ret = rk_udphy_power_on(udphy, UDPHY_MODE_DP);
+ if (ret)
+ return ret;
- rk_udphy_dp_lane_enable(udphy, udphy->dp_lanes);
+ rk_udphy_dp_lane_enable(udphy, udphy->dp_lanes);
- rk_udphy_dp_lane_select(udphy);
+ rk_udphy_dp_lane_select(udphy);
+ }
-unlock:
- mutex_unlock(&udphy->mutex);
/*
* If data send by aux channel too fast after phy power on,
* the aux may be not ready which will cause aux error. Adding
* delay to avoid this issue.
*/
usleep_range(10000, 11000);
+
return ret;
}
@@ -1071,10 +1070,10 @@ static int rk_udphy_dp_phy_power_off(struct phy *phy)
{
struct rk_udphy *udphy = phy_get_drvdata(phy);
- mutex_lock(&udphy->mutex);
+ guard(mutex)(&udphy->mutex);
+
rk_udphy_dp_lane_enable(udphy, 0);
rk_udphy_power_off(udphy, UDPHY_MODE_DP);
- mutex_unlock(&udphy->mutex);
return 0;
}
@@ -1279,35 +1278,30 @@ static const struct phy_ops rk_udphy_dp_phy_ops = {
static int rk_udphy_usb3_phy_init(struct phy *phy)
{
struct rk_udphy *udphy = phy_get_drvdata(phy);
- int ret = 0;
- mutex_lock(&udphy->mutex);
+ guard(mutex)(&udphy->mutex);
+
/* DP only or high-speed, disable U3 port */
if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) {
rk_udphy_u3_port_disable(udphy, true);
- goto unlock;
+ return 0;
}
- ret = rk_udphy_power_on(udphy, UDPHY_MODE_USB);
-
-unlock:
- mutex_unlock(&udphy->mutex);
- return ret;
+ return rk_udphy_power_on(udphy, UDPHY_MODE_USB);
}
static int rk_udphy_usb3_phy_exit(struct phy *phy)
{
struct rk_udphy *udphy = phy_get_drvdata(phy);
- mutex_lock(&udphy->mutex);
+ guard(mutex)(&udphy->mutex);
+
/* DP only or high-speed */
if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs)
- goto unlock;
+ return 0;
rk_udphy_power_off(udphy, UDPHY_MODE_USB);
-unlock:
- mutex_unlock(&udphy->mutex);
return 0;
}
@@ -1330,12 +1324,10 @@ static int rk_udphy_typec_mux_set(struct typec_mux_dev *mux,
if (!state->alt || state->alt->svid != USB_TYPEC_DP_SID)
return 0;
- mutex_lock(&udphy->mutex);
+ guard(mutex)(&udphy->mutex);
rk_udphy_set_typec_state(udphy, state->mode);
- mutex_unlock(&udphy->mutex);
-
return 0;
}
--
2.53.0
^ permalink raw reply related
* [PATCH v6 23/23] phy: rockchip: usbdp: Add some extra debug messages
From: Sebastian Reichel @ 2026-06-19 15:29 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Heiko Stuebner, Frank Wang,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Andy Yan, Dmitry Baryshkov, Yubing Zhang, Alexey Charkov,
linux-phy, linux-arm-kernel, linux-rockchip, linux-kernel, kernel,
devicetree, Sebastian Reichel
In-Reply-To: <20260619-rockchip-usbdp-cleanup-v6-0-3bb1f54b3f35@collabora.com>
It's useful to log PHY reinit to ease debugging issues around
USB-C hotplugging.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/phy/rockchip/phy-rockchip-usbdp.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c
index 8c59c50f207e..6e80dfeee0e5 100644
--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
@@ -24,6 +24,7 @@
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/reset.h>
+#include <linux/string_choices.h>
#include <linux/usb/ch9.h>
#include <linux/usb/typec_dp.h>
#include <linux/usb/typec_mux.h>
@@ -491,6 +492,8 @@ static void rk_udphy_u3_port_disable(struct rk_udphy *udphy, u8 disable)
const struct rk_udphy_cfg *cfg = udphy->cfgs;
const struct rk_udphy_grf_reg *preg;
+ dev_dbg(udphy->dev, "USB3 port %s\n", str_on_off(!disable));
+
preg = udphy->id ? &cfg->grfcfg.usb3otg1_cfg : &cfg->grfcfg.usb3otg0_cfg;
rk_udphy_grfreg_write(udphy->usbgrf, preg, disable);
}
@@ -784,6 +787,10 @@ static int rk_udphy_init(struct rk_udphy *udphy)
const struct rk_udphy_cfg *cfg = udphy->cfgs;
int ret;
+ dev_dbg(udphy->dev, "(re-)init PHY with USB=%s and DP=%s\n",
+ str_enabled_disabled(udphy->mode & UDPHY_MODE_USB),
+ str_enabled_disabled(udphy->mode & UDPHY_MODE_DP));
+
rk_udphy_reset_assert_all(udphy);
usleep_range(10000, 11000);
@@ -854,6 +861,8 @@ static int rk_udphy_setup(struct rk_udphy *udphy)
{
int ret;
+ dev_dbg(udphy->dev, "enable PHY\n");
+
ret = clk_bulk_prepare_enable(udphy->num_clks, udphy->clks);
if (ret) {
dev_err(udphy->dev, "failed to enable clk\n");
@@ -872,6 +881,7 @@ static int rk_udphy_setup(struct rk_udphy *udphy)
static void rk_udphy_disable(struct rk_udphy *udphy)
{
+ dev_dbg(udphy->dev, "disable PHY\n");
clk_bulk_disable_unprepare(udphy->num_clks, udphy->clks);
rk_udphy_reset_assert_all(udphy);
}
--
2.53.0
^ permalink raw reply related
* [PATCH v6 15/23] phy: rockchip: usbdp: Register DP aux bridge
From: Sebastian Reichel @ 2026-06-19 15:29 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Heiko Stuebner, Frank Wang,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Andy Yan, Dmitry Baryshkov, Yubing Zhang, Alexey Charkov,
linux-phy, linux-arm-kernel, linux-rockchip, linux-kernel, kernel,
devicetree, Sebastian Reichel
In-Reply-To: <20260619-rockchip-usbdp-cleanup-v6-0-3bb1f54b3f35@collabora.com>
Add support to use USB-C connectors with the DP altmode helper code on
devicetree based platforms. To get this working there must be a DRM
bridge chain from the DisplayPort controller to the USB-C connector.
E.g. on Rockchip RK3576:
root@rk3576 # cat /sys/kernel/debug/dri/0/encoder-0/bridges
bridge[0]: dw_dp_bridge_funcs
refcount: 7
type: [10] DP
OF: /soc/dp@27e40000:rockchip,rk3576-dp
ops: [0x47] detect edid hpd
bridge[1]: drm_aux_bridge_funcs
refcount: 4
type: [0] Unknown
OF: /soc/phy@2b010000:rockchip,rk3576-usbdp-phy
ops: [0x0]
bridge[2]: drm_aux_hpd_bridge_funcs
refcount: 5
type: [10] DP
OF: /soc/i2c@2ac50000/typec-portc@22/connector:usb-c-connector
ops: [0x4] hpd
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/phy/rockchip/Kconfig | 2 ++
drivers/phy/rockchip/phy-rockchip-usbdp.c | 14 ++++++++++++++
2 files changed, 16 insertions(+)
diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig
index 14698571b607..39759bb2fa1d 100644
--- a/drivers/phy/rockchip/Kconfig
+++ b/drivers/phy/rockchip/Kconfig
@@ -136,8 +136,10 @@ config PHY_ROCKCHIP_USBDP
tristate "Rockchip USBDP COMBO PHY Driver"
depends on ARCH_ROCKCHIP && OF
depends on TYPEC
+ depends on DRM || DRM=n
select GENERIC_PHY
select USB_COMMON
+ select DRM_AUX_BRIDGE if DRM_BRIDGE
help
Enable this to support the Rockchip USB3.0/DP combo PHY with
Samsung IP block. This is required for USB3 support on RK3588.
diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c
index da769790df98..b75c190a4311 100644
--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
@@ -6,6 +6,7 @@
* Copyright (C) 2024 Collabora Ltd
*/
+#include <drm/bridge/aux-bridge.h>
#include <dt-bindings/phy/phy.h>
#include <linux/bitfield.h>
#include <linux/bits.h>
@@ -1438,6 +1439,7 @@ static int rk_udphy_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct phy_provider *phy_provider;
+ struct fwnode_handle *dp_aux_ep;
struct resource *res;
struct rk_udphy *udphy;
void __iomem *base;
@@ -1496,6 +1498,18 @@ static int rk_udphy_probe(struct platform_device *pdev)
return ret;
}
+ /*
+ * Only register the DRM bridge, if the DP aux channel is connected.
+ * Some boards use the USBDP PHY only for its USB3 capabilities.
+ */
+ dp_aux_ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), 3, 0, 0);
+ if (dp_aux_ep) {
+ ret = drm_aux_bridge_register(dev);
+ fwnode_handle_put(dp_aux_ep);
+ if (ret)
+ return ret;
+ }
+
udphy->phy_u3 = devm_phy_create(dev, dev->of_node, &rk_udphy_usb3_phy_ops);
if (IS_ERR(udphy->phy_u3)) {
ret = PTR_ERR(udphy->phy_u3);
--
2.53.0
^ permalink raw reply related
* [PATCH v6 22/23] phy: rockchip: usbdp: Hold mutex in DP PHY configure
From: Sebastian Reichel @ 2026-06-19 15:29 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Heiko Stuebner, Frank Wang,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Andy Yan, Dmitry Baryshkov, Yubing Zhang, Alexey Charkov,
linux-phy, linux-arm-kernel, linux-rockchip, linux-kernel, kernel,
devicetree, Sebastian Reichel, Sashiko
In-Reply-To: <20260619-rockchip-usbdp-cleanup-v6-0-3bb1f54b3f35@collabora.com>
rk_udphy_dp_phy_configure() accesses some variables from the struct
rk_udphy, which are updated independently from the USB-C framework.
The USB-C mux/orientation switch functions already hold a mutex to
ensure mutual exclusive access to the struct rk_udphy states, so
simply hold the same one in the DP PHY configuration function.
Reproducing problems due to this on real hardware would be really hard,
but could be possible when quickly re-connecting the USB-C connector.
Fixes: 2f70bbddeb45 ("phy: rockchip: add usbdp combo phy driver")
Reported-by: Sashiko <sashiko-bot@kernel.org>
Closes: https://lore.kernel.org/linux-phy/20260612164627.23D391F000E9@smtp.kernel.org/
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/phy/rockchip/phy-rockchip-usbdp.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c
index 7f26b74cb515..8c59c50f207e 100644
--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
@@ -1183,6 +1183,8 @@ static int rk_udphy_dp_phy_configure(struct phy *phy,
u32 i, val, lane;
int ret;
+ guard(mutex)(&udphy->mutex);
+
if (dp->set_rate) {
ret = rk_udphy_dp_phy_verify_link_rate(udphy, dp);
if (ret)
--
2.53.0
^ permalink raw reply related
* [PATCH v6 17/23] phy: rockchip: usbdp: Rename mode_change to phy_needs_reinit
From: Sebastian Reichel @ 2026-06-19 15:29 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Heiko Stuebner, Frank Wang,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Andy Yan, Dmitry Baryshkov, Yubing Zhang, Alexey Charkov,
linux-phy, linux-arm-kernel, linux-rockchip, linux-kernel, kernel,
devicetree, Sebastian Reichel
In-Reply-To: <20260619-rockchip-usbdp-cleanup-v6-0-3bb1f54b3f35@collabora.com>
Right now the mode_change property is set whenever the mode changes
between USB-only, DP-only and USB-DP. It is needed, because on any
mode change the PHY needs to be re-initialized. Apparently at least
DP also requires a re-init when the cable orientation is changed,
which is currently not being done (except when the orientation switch
also involves a mode change). Prepare for this by renaming mode_change
to phy_needs_reinit.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/phy/rockchip/phy-rockchip-usbdp.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c
index 383e68b24506..c210aaeb283a 100644
--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
@@ -171,7 +171,7 @@ struct rk_udphy {
/* PHY status management */
bool flip;
- bool mode_change;
+ bool phy_needs_reinit;
u8 mode;
u8 status;
@@ -580,7 +580,7 @@ static void rk_udphy_mode_set(struct rk_udphy *udphy, u8 mode)
if (udphy->mode == mode)
return;
- udphy->mode_change = true;
+ udphy->phy_needs_reinit = true;
udphy->mode = mode;
}
@@ -975,15 +975,15 @@ static int rk_udphy_power_on(struct rk_udphy *udphy, u8 mode)
if (udphy->mode & UDPHY_MODE_USB)
rk_udphy_u3_port_disable(udphy, false);
- udphy->mode_change = false;
- } else if (udphy->mode_change) {
+ udphy->phy_needs_reinit = false;
+ } else if (udphy->phy_needs_reinit) {
if (udphy->mode == UDPHY_MODE_DP)
rk_udphy_u3_port_disable(udphy, true);
ret = rk_udphy_init(udphy);
if (ret)
return ret;
- udphy->mode_change = false;
+ udphy->phy_needs_reinit = false;
}
udphy->status |= mode;
--
2.53.0
^ permalink raw reply related
* [PATCH v6 19/23] phy: rockchip: usbdp: Factor out lane_mux_sel setup
From: Sebastian Reichel @ 2026-06-19 15:29 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Heiko Stuebner, Frank Wang,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Andy Yan, Dmitry Baryshkov, Yubing Zhang, Alexey Charkov,
linux-phy, linux-arm-kernel, linux-rockchip, linux-kernel, kernel,
devicetree, Sebastian Reichel
In-Reply-To: <20260619-rockchip-usbdp-cleanup-v6-0-3bb1f54b3f35@collabora.com>
Avoid describing the USB+DP lane_mux_sel logic twice by introducing
a helper function to reduce code duplication.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/phy/rockchip/phy-rockchip-usbdp.c | 81 +++++++++++++++----------------
1 file changed, 40 insertions(+), 41 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c
index 402f3cafcf0a..46ab9fb45ca4 100644
--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
@@ -584,6 +584,42 @@ static void rk_udphy_mode_set(struct rk_udphy *udphy, u8 mode)
udphy->mode = mode;
}
+static void rk_udphy_set_typec_state(struct rk_udphy *udphy, unsigned long state)
+{
+ u8 mode;
+
+ switch (state) {
+ case TYPEC_DP_STATE_C:
+ case TYPEC_DP_STATE_E:
+ udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP;
+ udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP;
+ udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP;
+ udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP;
+ mode = UDPHY_MODE_DP;
+ udphy->dp_lanes = 4;
+ break;
+
+ case TYPEC_DP_STATE_D:
+ default:
+ if (udphy->flip) {
+ udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP;
+ udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP;
+ udphy->lane_mux_sel[2] = PHY_LANE_MUX_USB;
+ udphy->lane_mux_sel[3] = PHY_LANE_MUX_USB;
+ } else {
+ udphy->lane_mux_sel[0] = PHY_LANE_MUX_USB;
+ udphy->lane_mux_sel[1] = PHY_LANE_MUX_USB;
+ udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP;
+ udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP;
+ }
+ mode = UDPHY_MODE_DP_USB;
+ udphy->dp_lanes = 2;
+ break;
+ }
+
+ rk_udphy_mode_set(udphy, mode);
+}
+
static void rk_udphy_set_typec_default_mapping(struct rk_udphy *udphy)
{
if (udphy->flip) {
@@ -591,10 +627,6 @@ static void rk_udphy_set_typec_default_mapping(struct rk_udphy *udphy)
udphy->dp_lane_sel[1] = 1;
udphy->dp_lane_sel[2] = 3;
udphy->dp_lane_sel[3] = 2;
- udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP;
- udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP;
- udphy->lane_mux_sel[2] = PHY_LANE_MUX_USB;
- udphy->lane_mux_sel[3] = PHY_LANE_MUX_USB;
udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_INVERT;
udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_INVERT;
gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 1);
@@ -604,18 +636,14 @@ static void rk_udphy_set_typec_default_mapping(struct rk_udphy *udphy)
udphy->dp_lane_sel[1] = 3;
udphy->dp_lane_sel[2] = 1;
udphy->dp_lane_sel[3] = 0;
- udphy->lane_mux_sel[0] = PHY_LANE_MUX_USB;
- udphy->lane_mux_sel[1] = PHY_LANE_MUX_USB;
- udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP;
- udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP;
udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_NORMAL;
udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_NORMAL;
gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 0);
gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 1);
}
- rk_udphy_mode_set(udphy, UDPHY_MODE_DP_USB);
- udphy->dp_lanes = 2;
+ /* default to USB3 + DP as 4 lane USB is not supported */
+ rk_udphy_set_typec_state(udphy, TYPEC_DP_STATE_D);
}
static int rk_udphy_orien_sw_set(struct typec_switch_dev *sw,
@@ -1293,7 +1321,6 @@ static int rk_udphy_typec_mux_set(struct typec_mux_dev *mux,
struct typec_mux_state *state)
{
struct rk_udphy *udphy = typec_mux_get_drvdata(mux);
- u8 mode;
/*
* Ignore mux events not involving DP AltMode, because
@@ -1305,38 +1332,10 @@ static int rk_udphy_typec_mux_set(struct typec_mux_dev *mux,
mutex_lock(&udphy->mutex);
- switch (state->mode) {
- case TYPEC_DP_STATE_C:
- case TYPEC_DP_STATE_E:
- udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP;
- udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP;
- udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP;
- udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP;
- mode = UDPHY_MODE_DP;
- udphy->dp_lanes = 4;
- break;
-
- case TYPEC_DP_STATE_D:
- default:
- if (udphy->flip) {
- udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP;
- udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP;
- udphy->lane_mux_sel[2] = PHY_LANE_MUX_USB;
- udphy->lane_mux_sel[3] = PHY_LANE_MUX_USB;
- } else {
- udphy->lane_mux_sel[0] = PHY_LANE_MUX_USB;
- udphy->lane_mux_sel[1] = PHY_LANE_MUX_USB;
- udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP;
- udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP;
- }
- mode = UDPHY_MODE_DP_USB;
- udphy->dp_lanes = 2;
- break;
- }
-
- rk_udphy_mode_set(udphy, mode);
+ rk_udphy_set_typec_state(udphy, state->mode);
mutex_unlock(&udphy->mutex);
+
return 0;
}
--
2.53.0
^ permalink raw reply related
* [PATCH v6 13/23] phy: rockchip: usbdp: Use FIELD_PREP_WM16_CONST
From: Sebastian Reichel @ 2026-06-19 15:29 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Heiko Stuebner, Frank Wang,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Andy Yan, Dmitry Baryshkov, Yubing Zhang, Alexey Charkov,
linux-phy, linux-arm-kernel, linux-rockchip, linux-kernel, kernel,
devicetree, Sebastian Reichel
In-Reply-To: <20260619-rockchip-usbdp-cleanup-v6-0-3bb1f54b3f35@collabora.com>
Cleanup code by replacing open-coded version of FIELD_PREP_WM16_CONST
with the existing helper macro.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/phy/rockchip/phy-rockchip-usbdp.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c
index e8b2adecb08a..ceaf091b9101 100644
--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
@@ -12,6 +12,7 @@
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/gpio.h>
+#include <linux/hw_bitfield.h>
#include <linux/mfd/syscon.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
@@ -75,7 +76,6 @@
#define TRSV_LN2_MON_RX_CDR_DONE_OFFSET 0x1b84 /* trsv_reg06E1 */
#define TRSV_LN2_MON_RX_CDR_LOCK_DONE BIT(0)
-#define BIT_WRITEABLE_SHIFT 16
#define PHY_AUX_DP_DATA_POL_NORMAL 0
#define PHY_AUX_DP_DATA_POL_INVERT 1
#define PHY_LANE_MUX_USB 0
@@ -104,8 +104,8 @@ struct rk_udphy_grf_reg {
#define _RK_UDPHY_GEN_GRF_REG(offset, mask, disable, enable) \
{\
offset, \
- FIELD_PREP_CONST(mask, disable) | (mask << BIT_WRITEABLE_SHIFT), \
- FIELD_PREP_CONST(mask, enable) | (mask << BIT_WRITEABLE_SHIFT), \
+ FIELD_PREP_WM16_CONST(mask, disable), \
+ FIELD_PREP_WM16_CONST(mask, enable), \
}
#define RK_UDPHY_GEN_GRF_REG(offset, bitend, bitstart, disable, enable) \
--
2.53.0
^ permalink raw reply related
* [PATCH v6 14/23] phy: rockchip: usbdp: Cleanup DP lane selection function
From: Sebastian Reichel @ 2026-06-19 15:29 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Heiko Stuebner, Frank Wang,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Andy Yan, Dmitry Baryshkov, Yubing Zhang, Alexey Charkov,
linux-phy, linux-arm-kernel, linux-rockchip, linux-kernel, kernel,
devicetree, Sebastian Reichel
In-Reply-To: <20260619-rockchip-usbdp-cleanup-v6-0-3bb1f54b3f35@collabora.com>
Use FIELD_PREP_WM16() helpers to simplify the DP lane selection
logic.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/phy/rockchip/phy-rockchip-usbdp.c | 28 +++++++---------------------
1 file changed, 7 insertions(+), 21 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c
index ceaf091b9101..da769790df98 100644
--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
@@ -550,30 +550,16 @@ static void rk_udphy_usb_bvalid_enable(struct rk_udphy *udphy, u8 enable)
static void rk_udphy_dp_lane_select(struct rk_udphy *udphy)
{
const struct rk_udphy_cfg *cfg = udphy->cfgs;
- u32 value = 0;
-
- switch (udphy->dp_lanes) {
- case 4:
- value |= 3 << udphy->dp_lane_sel[3] * 2;
- value |= 2 << udphy->dp_lane_sel[2] * 2;
- fallthrough;
-
- case 2:
- value |= 1 << udphy->dp_lane_sel[1] * 2;
- fallthrough;
+ u32 value = FIELD_PREP_WM16(DP_LANE_SEL_ALL, 0);
+ int i;
- case 1:
- value |= 0 << udphy->dp_lane_sel[0] * 2;
- break;
+ for (i = 0; i < udphy->dp_lanes; i++)
+ value |= field_prep(DP_LANE_SEL_N(udphy->dp_lane_sel[i]), i);
- default:
- break;
- }
+ value |= FIELD_PREP_WM16(DP_AUX_DIN_SEL, udphy->dp_aux_din_sel);
+ value |= FIELD_PREP_WM16(DP_AUX_DOUT_SEL, udphy->dp_aux_dout_sel);
- regmap_write(udphy->vogrf, cfg->vogrfcfg[udphy->id].dp_lane_reg,
- ((DP_AUX_DIN_SEL | DP_AUX_DOUT_SEL | DP_LANE_SEL_ALL) << 16) |
- FIELD_PREP(DP_AUX_DIN_SEL, udphy->dp_aux_din_sel) |
- FIELD_PREP(DP_AUX_DOUT_SEL, udphy->dp_aux_dout_sel) | value);
+ regmap_write(udphy->vogrf, cfg->vogrfcfg[udphy->id].dp_lane_reg, value);
}
static void rk_udphy_dp_lane_enable(struct rk_udphy *udphy, int dp_lanes)
--
2.53.0
^ permalink raw reply related
* [PATCH v6 08/23] phy: rockchip: usbdp: Amend SSC modulation deviation
From: Sebastian Reichel @ 2026-06-19 15:28 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Heiko Stuebner, Frank Wang,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Andy Yan, Dmitry Baryshkov, Yubing Zhang, Alexey Charkov,
linux-phy, linux-arm-kernel, linux-rockchip, linux-kernel, kernel,
devicetree, Sebastian Reichel
In-Reply-To: <20260619-rockchip-usbdp-cleanup-v6-0-3bb1f54b3f35@collabora.com>
From: Frank Wang <frank.wang@rock-chips.com>
Move SSC modulation deviation into private config of clock
- 24M: 0x00d4[5:0] = 0x30
- 26M: 0x00d4[5:0] = 0x33
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
[Taken over from rockchip's kernel tree; register 0x00d4 is not
described in the TRM]
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/phy/rockchip/phy-rockchip-usbdp.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c
index c05ee65a9f73..a44babac3517 100644
--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
@@ -350,7 +350,8 @@ static const struct reg_sequence rk_udphy_24m_refclk_cfg[] = {
{0x0a64, 0xa8}, {0x1a3c, 0xd0},
{0x1a44, 0xd0}, {0x1a48, 0x01},
{0x1a4c, 0x0d}, {0x1a54, 0xe0},
- {0x1a5c, 0xe0}, {0x1a64, 0xa8}
+ {0x1a5c, 0xe0}, {0x1a64, 0xa8},
+ {0x00d4, 0x30}
};
static const struct reg_sequence rk_udphy_26m_refclk_cfg[] = {
@@ -377,7 +378,7 @@ static const struct reg_sequence rk_udphy_26m_refclk_cfg[] = {
{0x0c30, 0x0e}, {0x0c48, 0x06},
{0x1c30, 0x0e}, {0x1c48, 0x06},
{0x028c, 0x18}, {0x0af0, 0x00},
- {0x1af0, 0x00}
+ {0x1af0, 0x00}, {0x00d4, 0x33}
};
static const struct reg_sequence rk_udphy_init_sequence[] = {
@@ -412,8 +413,7 @@ static const struct reg_sequence rk_udphy_init_sequence[] = {
{0x0070, 0x7d}, {0x0074, 0x68},
{0x0af4, 0x1a}, {0x1af4, 0x1a},
{0x0440, 0x3f}, {0x10d4, 0x08},
- {0x20d4, 0x08}, {0x00d4, 0x30},
- {0x0024, 0x6e},
+ {0x20d4, 0x08}, {0x0024, 0x6e}
};
static inline int rk_udphy_grfreg_write(struct regmap *base,
--
2.53.0
^ permalink raw reply related
* [PATCH v6 07/23] phy: rockchip: usbdp: Keep clocks running on PHY re-init
From: Sebastian Reichel @ 2026-06-19 15:28 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Heiko Stuebner, Frank Wang,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Andy Yan, Dmitry Baryshkov, Yubing Zhang, Alexey Charkov,
linux-phy, linux-arm-kernel, linux-rockchip, linux-kernel, kernel,
devicetree, Sebastian Reichel
In-Reply-To: <20260619-rockchip-usbdp-cleanup-v6-0-3bb1f54b3f35@collabora.com>
When a mode change is required rk_udphy_power_on() disables
the clocks and then calls rk_udphy_setup(), which then enables
all the clocks again before continuing with rk_udphy_init().
Considering that rk_udphy_init() does assert the reset lines,
re-enabling the clocks is just delaying things. Avoid it by
directly calling rk_udphy_init().
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/phy/rockchip/phy-rockchip-usbdp.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c
index 6dff4dfc9363..c05ee65a9f73 100644
--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
@@ -1011,8 +1011,7 @@ static int rk_udphy_power_on(struct rk_udphy *udphy, u8 mode)
if (udphy->mode == UDPHY_MODE_DP)
rk_udphy_u3_port_disable(udphy, true);
- rk_udphy_disable(udphy);
- ret = rk_udphy_setup(udphy);
+ ret = rk_udphy_init(udphy);
if (ret)
return ret;
udphy->mode_change = false;
--
2.53.0
^ permalink raw reply related
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