* [PATCH 08/11] ARM: mach-lpc: Remove NOMMU platform support
From: Frank.Li @ 2026-06-19 15:41 UTC (permalink / raw)
To: Arnd Bergmann, Sascha Hauer, Pengutronix Kernel Team,
Stefan Agner, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Russell King, Abel Vesa, Peng Fan,
Michael Turquette, Stephen Boyd, Brian Masney, Dong Aisheng,
Jacky Bai, NXP S32 Linux Team, Linus Walleij, Vladimir Zapolskiy,
Piotr Wojtaszczyk, Kees Cook, Gustavo A. R. Silva
Cc: linux-arm-kernel, imx, devicetree, linux-kernel, linux-clk,
linux-gpio, linux-hardening, Frank Li
In-Reply-To: <20260619-dts_cleanup_arm_mcore-v1-0-0101795a2662@nxp.com>
From: Frank Li <Frank.Li@nxp.com>
Commercial users and hardware vendors migrated to Zephyr or other RTOS
solutions years ago, leaving the NOMMU platform support effectively
unused and unmaintained.
Remove the obsolete support to reduce maintenance burden and simplify the
NXP/Freescale platform code.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm/Kconfig | 12 -
arch/arm/Makefile | 2 -
arch/arm/mach-lpc18xx/Makefile | 2 -
arch/arm/mach-lpc18xx/board-dt.c | 19 --
arch/arm/mach-lpc32xx/Kconfig | 13 -
arch/arm/mach-lpc32xx/Makefile | 8 -
arch/arm/mach-lpc32xx/common.c | 125 -------
arch/arm/mach-lpc32xx/common.h | 32 --
arch/arm/mach-lpc32xx/lpc32xx.h | 717 ---------------------------------------
arch/arm/mach-lpc32xx/phy3250.c | 92 -----
arch/arm/mach-lpc32xx/pm.c | 135 --------
arch/arm/mach-lpc32xx/serial.c | 148 --------
arch/arm/mach-lpc32xx/suspend.S | 148 --------
13 files changed, 1453 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9187240a02db5..fe67d41f4a107 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -401,8 +401,6 @@ source "arch/arm/mach-ixp4xx/Kconfig"
source "arch/arm/mach-keystone/Kconfig"
-source "arch/arm/mach-lpc32xx/Kconfig"
-
source "arch/arm/mach-mediatek/Kconfig"
source "arch/arm/mach-meson/Kconfig"
@@ -470,16 +468,6 @@ source "arch/arm/mach-zte/Kconfig"
source "arch/arm/mach-zynq/Kconfig"
# ARMv7-M architecture
-config ARCH_LPC18XX
- bool "NXP LPC18xx/LPC43xx"
- depends on ARM_SINGLE_ARMV7M
- select ARCH_HAS_RESET_CONTROLLER
- select ARM_AMBA
- select CLKSRC_LPC32XX
- select PINCTRL
- help
- Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
- high performance microcontrollers.
config ARCH_MPS2
bool "ARM MPS2 platform"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 573813ef5e77a..dd30c256780d9 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -191,8 +191,6 @@ machine-$(CONFIG_ARCH_HIGHBANK) += highbank
machine-$(CONFIG_ARCH_HISI) += hisi
machine-$(CONFIG_ARCH_IXP4XX) += ixp4xx
machine-$(CONFIG_ARCH_KEYSTONE) += keystone
-machine-$(CONFIG_ARCH_LPC18XX) += lpc18xx
-machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx
machine-$(CONFIG_ARCH_MESON) += meson
machine-$(CONFIG_ARCH_MMP) += mmp
machine-$(CONFIG_ARCH_MV78XX0) += mv78xx0
diff --git a/arch/arm/mach-lpc18xx/Makefile b/arch/arm/mach-lpc18xx/Makefile
deleted file mode 100644
index c80d80c199d37..0000000000000
--- a/arch/arm/mach-lpc18xx/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-obj-y += board-dt.o
diff --git a/arch/arm/mach-lpc18xx/board-dt.c b/arch/arm/mach-lpc18xx/board-dt.c
deleted file mode 100644
index 4729eb83401ae..0000000000000
--- a/arch/arm/mach-lpc18xx/board-dt.c
+++ /dev/null
@@ -1,19 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Device Tree board file for NXP LPC18xx/43xx
- *
- * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
- */
-
-#include <asm/mach/arch.h>
-
-static const char *const lpc18xx_43xx_compat[] __initconst = {
- "nxp,lpc1850",
- "nxp,lpc4350",
- "nxp,lpc4370",
- NULL
-};
-
-DT_MACHINE_START(LPC18XXDT, "NXP LPC18xx/43xx (Device Tree)")
- .dt_compat = lpc18xx_43xx_compat,
-MACHINE_END
diff --git a/arch/arm/mach-lpc32xx/Kconfig b/arch/arm/mach-lpc32xx/Kconfig
deleted file mode 100644
index 138599545c24c..0000000000000
--- a/arch/arm/mach-lpc32xx/Kconfig
+++ /dev/null
@@ -1,13 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-config ARCH_LPC32XX
- bool "NXP LPC32XX"
- depends on ARCH_MULTI_V5
- depends on CPU_LITTLE_ENDIAN
- select ARM_AMBA
- select CLKSRC_LPC32XX
- select CPU_ARM926T
- select GPIOLIB
- select LPC32XX_DMAMUX if AMBA_PL08X
- help
- Support for the NXP LPC32XX family of processors
diff --git a/arch/arm/mach-lpc32xx/Makefile b/arch/arm/mach-lpc32xx/Makefile
deleted file mode 100644
index 3bac1d17a207b..0000000000000
--- a/arch/arm/mach-lpc32xx/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-#
-# Makefile for the linux kernel.
-#
-
-obj-y := common.o serial.o
-obj-y += pm.o suspend.o
-obj-y += phy3250.o
diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c
deleted file mode 100644
index 304ea61a07160..0000000000000
--- a/arch/arm/mach-lpc32xx/common.c
+++ /dev/null
@@ -1,125 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * arch/arm/mach-lpc32xx/common.c
- *
- * Author: Kevin Wells <kevin.wells@nxp.com>
- *
- * Copyright (C) 2010 NXP Semiconductors
- */
-
-#include <linux/init.h>
-#include <linux/soc/nxp/lpc32xx-misc.h>
-
-#include <asm/mach/map.h>
-#include <asm/system_info.h>
-
-#include "lpc32xx.h"
-#include "common.h"
-
-/*
- * Returns the unique ID for the device
- */
-void lpc32xx_get_uid(u32 devid[4])
-{
- int i;
-
- for (i = 0; i < 4; i++)
- devid[i] = __raw_readl(LPC32XX_CLKPWR_DEVID(i << 2));
-}
-
-/*
- * Detects and returns IRAM size for the device variation
- */
-#define LPC32XX_IRAM_BANK_SIZE SZ_128K
-static u32 iram_size;
-u32 lpc32xx_return_iram(void __iomem **mapbase, dma_addr_t *dmaaddr)
-{
- if (iram_size == 0) {
- u32 savedval1, savedval2;
- void __iomem *iramptr1, *iramptr2;
-
- iramptr1 = io_p2v(LPC32XX_IRAM_BASE);
- iramptr2 = io_p2v(LPC32XX_IRAM_BASE + LPC32XX_IRAM_BANK_SIZE);
- savedval1 = __raw_readl(iramptr1);
- savedval2 = __raw_readl(iramptr2);
-
- if (savedval1 == savedval2) {
- __raw_writel(savedval2 + 1, iramptr2);
- if (__raw_readl(iramptr1) == savedval2 + 1)
- iram_size = LPC32XX_IRAM_BANK_SIZE;
- else
- iram_size = LPC32XX_IRAM_BANK_SIZE * 2;
- __raw_writel(savedval2, iramptr2);
- } else
- iram_size = LPC32XX_IRAM_BANK_SIZE * 2;
- }
- if (dmaaddr)
- *dmaaddr = LPC32XX_IRAM_BASE;
- if (mapbase)
- *mapbase = io_p2v(LPC32XX_IRAM_BASE);
-
- return iram_size;
-}
-EXPORT_SYMBOL_GPL(lpc32xx_return_iram);
-
-void lpc32xx_set_phy_interface_mode(phy_interface_t mode)
-{
- u32 tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL);
- tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK;
- if (mode == PHY_INTERFACE_MODE_MII)
- tmp |= LPC32XX_CLKPWR_MACCTRL_USE_MII_PINS;
- else
- tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS;
- __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL);
-}
-EXPORT_SYMBOL_GPL(lpc32xx_set_phy_interface_mode);
-
-static struct map_desc lpc32xx_io_desc[] __initdata = {
- {
- .virtual = (unsigned long)IO_ADDRESS(LPC32XX_AHB0_START),
- .pfn = __phys_to_pfn(LPC32XX_AHB0_START),
- .length = LPC32XX_AHB0_SIZE,
- .type = MT_DEVICE
- },
- {
- .virtual = (unsigned long)IO_ADDRESS(LPC32XX_AHB1_START),
- .pfn = __phys_to_pfn(LPC32XX_AHB1_START),
- .length = LPC32XX_AHB1_SIZE,
- .type = MT_DEVICE
- },
- {
- .virtual = (unsigned long)IO_ADDRESS(LPC32XX_FABAPB_START),
- .pfn = __phys_to_pfn(LPC32XX_FABAPB_START),
- .length = LPC32XX_FABAPB_SIZE,
- .type = MT_DEVICE
- },
- {
- .virtual = (unsigned long)IO_ADDRESS(LPC32XX_IRAM_BASE),
- .pfn = __phys_to_pfn(LPC32XX_IRAM_BASE),
- .length = (LPC32XX_IRAM_BANK_SIZE * 2),
- .type = MT_DEVICE
- },
-};
-
-void __init lpc32xx_map_io(void)
-{
- iotable_init(lpc32xx_io_desc, ARRAY_SIZE(lpc32xx_io_desc));
-}
-
-static int __init lpc32xx_check_uid(void)
-{
- u32 uid[4];
-
- lpc32xx_get_uid(uid);
-
- printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n",
- uid[3], uid[2], uid[1], uid[0]);
-
- if (!system_serial_low && !system_serial_high) {
- system_serial_low = uid[0];
- system_serial_high = uid[1];
- }
-
- return 1;
-}
-arch_initcall(lpc32xx_check_uid);
diff --git a/arch/arm/mach-lpc32xx/common.h b/arch/arm/mach-lpc32xx/common.h
deleted file mode 100644
index 32f0ad2178077..0000000000000
--- a/arch/arm/mach-lpc32xx/common.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * arch/arm/mach-lpc32xx/common.h
- *
- * Author: Kevin Wells <kevin.wells@nxp.com>
- *
- * Copyright (C) 2009-2010 NXP Semiconductors
- */
-
-#ifndef __LPC32XX_COMMON_H
-#define __LPC32XX_COMMON_H
-
-#include <linux/init.h>
-
-/*
- * Other arch specific structures and functions
- */
-extern void __init lpc32xx_map_io(void);
-extern void __init lpc32xx_serial_init(void);
-
-/*
- * Returns the LPC32xx unique 128-bit chip ID
- */
-extern void lpc32xx_get_uid(u32 devid[4]);
-
-/*
- * Pointers used for sizing and copying suspend function data
- */
-extern int lpc32xx_sys_suspend(void);
-extern int lpc32xx_sys_suspend_sz;
-
-#endif
diff --git a/arch/arm/mach-lpc32xx/lpc32xx.h b/arch/arm/mach-lpc32xx/lpc32xx.h
deleted file mode 100644
index 5eeb884a19939..0000000000000
--- a/arch/arm/mach-lpc32xx/lpc32xx.h
+++ /dev/null
@@ -1,717 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * arch/arm/mach-lpc32xx/include/mach/platform.h
- *
- * Author: Kevin Wells <kevin.wells@nxp.com>
- *
- * Copyright (C) 2010 NXP Semiconductors
- */
-
-#ifndef __ARM_LPC32XX_H
-#define __ARM_LPC32XX_H
-
-#define _SBF(f, v) ((v) << (f))
-#define _BIT(n) _SBF(n, 1)
-
-/*
- * AHB 0 physical base addresses
- */
-#define LPC32XX_SLC_BASE 0x20020000
-#define LPC32XX_SSP0_BASE 0x20084000
-#define LPC32XX_SPI1_BASE 0x20088000
-#define LPC32XX_SSP1_BASE 0x2008C000
-#define LPC32XX_SPI2_BASE 0x20090000
-#define LPC32XX_I2S0_BASE 0x20094000
-#define LPC32XX_SD_BASE 0x20098000
-#define LPC32XX_I2S1_BASE 0x2009C000
-#define LPC32XX_MLC_BASE 0x200A8000
-#define LPC32XX_AHB0_START LPC32XX_SLC_BASE
-#define LPC32XX_AHB0_SIZE 0x00089000
-
-/*
- * AHB 1 physical base addresses
- */
-#define LPC32XX_DMA_BASE 0x31000000
-#define LPC32XX_USB_BASE 0x31020000
-#define LPC32XX_USBH_BASE 0x31020000
-#define LPC32XX_USB_OTG_BASE 0x31020000
-#define LPC32XX_OTG_I2C_BASE 0x31020300
-#define LPC32XX_LCD_BASE 0x31040000
-#define LPC32XX_ETHERNET_BASE 0x31060000
-#define LPC32XX_EMC_BASE 0x31080000
-#define LPC32XX_ETB_CFG_BASE 0x310C0000
-#define LPC32XX_ETB_DATA_BASE 0x310E0000
-#define LPC32XX_AHB1_START LPC32XX_DMA_BASE
-#define LPC32XX_AHB1_SIZE 0x000E1000
-
-/*
- * FAB physical base addresses
- */
-#define LPC32XX_CLK_PM_BASE 0x40004000
-#define LPC32XX_MIC_BASE 0x40008000
-#define LPC32XX_SIC1_BASE 0x4000C000
-#define LPC32XX_SIC2_BASE 0x40010000
-#define LPC32XX_HS_UART1_BASE 0x40014000
-#define LPC32XX_HS_UART2_BASE 0x40018000
-#define LPC32XX_HS_UART7_BASE 0x4001C000
-#define LPC32XX_RTC_BASE 0x40024000
-#define LPC32XX_RTC_RAM_BASE 0x40024080
-#define LPC32XX_GPIO_BASE 0x40028000
-#define LPC32XX_PWM3_BASE 0x4002C000
-#define LPC32XX_PWM4_BASE 0x40030000
-#define LPC32XX_MSTIM_BASE 0x40034000
-#define LPC32XX_HSTIM_BASE 0x40038000
-#define LPC32XX_WDTIM_BASE 0x4003C000
-#define LPC32XX_DEBUG_CTRL_BASE 0x40040000
-#define LPC32XX_TIMER0_BASE 0x40044000
-#define LPC32XX_ADC_BASE 0x40048000
-#define LPC32XX_TIMER1_BASE 0x4004C000
-#define LPC32XX_KSCAN_BASE 0x40050000
-#define LPC32XX_UART_CTRL_BASE 0x40054000
-#define LPC32XX_TIMER2_BASE 0x40058000
-#define LPC32XX_PWM1_BASE 0x4005C000
-#define LPC32XX_PWM2_BASE 0x4005C004
-#define LPC32XX_TIMER3_BASE 0x40060000
-
-/*
- * APB physical base addresses
- */
-#define LPC32XX_UART3_BASE 0x40080000
-#define LPC32XX_UART4_BASE 0x40088000
-#define LPC32XX_UART5_BASE 0x40090000
-#define LPC32XX_UART6_BASE 0x40098000
-#define LPC32XX_I2C1_BASE 0x400A0000
-#define LPC32XX_I2C2_BASE 0x400A8000
-
-/*
- * FAB and APB base and sizing
- */
-#define LPC32XX_FABAPB_START LPC32XX_CLK_PM_BASE
-#define LPC32XX_FABAPB_SIZE 0x000A5000
-
-/*
- * Internal memory bases and sizes
- */
-#define LPC32XX_IRAM_BASE 0x08000000
-#define LPC32XX_IROM_BASE 0x0C000000
-
-/*
- * External Static Memory Bank Address Space Bases
- */
-#define LPC32XX_EMC_CS0_BASE 0xE0000000
-#define LPC32XX_EMC_CS1_BASE 0xE1000000
-#define LPC32XX_EMC_CS2_BASE 0xE2000000
-#define LPC32XX_EMC_CS3_BASE 0xE3000000
-
-/*
- * External SDRAM Memory Bank Address Space Bases
- */
-#define LPC32XX_EMC_DYCS0_BASE 0x80000000
-#define LPC32XX_EMC_DYCS1_BASE 0xA0000000
-
-/*
- * Clock and crystal information
- */
-#define LPC32XX_MAIN_OSC_FREQ 13000000
-#define LPC32XX_CLOCK_OSC_FREQ 32768
-
-/*
- * Clock and Power control register offsets
- */
-#define _PMREG(x) io_p2v(LPC32XX_CLK_PM_BASE +\
- (x))
-#define LPC32XX_CLKPWR_DEBUG_CTRL _PMREG(0x000)
-#define LPC32XX_CLKPWR_BOOTMAP _PMREG(0x014)
-#define LPC32XX_CLKPWR_P01_ER _PMREG(0x018)
-#define LPC32XX_CLKPWR_USBCLK_PDIV _PMREG(0x01C)
-#define LPC32XX_CLKPWR_INT_ER _PMREG(0x020)
-#define LPC32XX_CLKPWR_INT_RS _PMREG(0x024)
-#define LPC32XX_CLKPWR_INT_SR _PMREG(0x028)
-#define LPC32XX_CLKPWR_INT_AP _PMREG(0x02C)
-#define LPC32XX_CLKPWR_PIN_ER _PMREG(0x030)
-#define LPC32XX_CLKPWR_PIN_RS _PMREG(0x034)
-#define LPC32XX_CLKPWR_PIN_SR _PMREG(0x038)
-#define LPC32XX_CLKPWR_PIN_AP _PMREG(0x03C)
-#define LPC32XX_CLKPWR_HCLK_DIV _PMREG(0x040)
-#define LPC32XX_CLKPWR_PWR_CTRL _PMREG(0x044)
-#define LPC32XX_CLKPWR_PLL397_CTRL _PMREG(0x048)
-#define LPC32XX_CLKPWR_MAIN_OSC_CTRL _PMREG(0x04C)
-#define LPC32XX_CLKPWR_SYSCLK_CTRL _PMREG(0x050)
-#define LPC32XX_CLKPWR_LCDCLK_CTRL _PMREG(0x054)
-#define LPC32XX_CLKPWR_HCLKPLL_CTRL _PMREG(0x058)
-#define LPC32XX_CLKPWR_ADC_CLK_CTRL_1 _PMREG(0x060)
-#define LPC32XX_CLKPWR_USB_CTRL _PMREG(0x064)
-#define LPC32XX_CLKPWR_SDRAMCLK_CTRL _PMREG(0x068)
-#define LPC32XX_CLKPWR_DDR_LAP_NOM _PMREG(0x06C)
-#define LPC32XX_CLKPWR_DDR_LAP_COUNT _PMREG(0x070)
-#define LPC32XX_CLKPWR_DDR_LAP_DELAY _PMREG(0x074)
-#define LPC32XX_CLKPWR_SSP_CLK_CTRL _PMREG(0x078)
-#define LPC32XX_CLKPWR_I2S_CLK_CTRL _PMREG(0x07C)
-#define LPC32XX_CLKPWR_MS_CTRL _PMREG(0x080)
-#define LPC32XX_CLKPWR_MACCLK_CTRL _PMREG(0x090)
-#define LPC32XX_CLKPWR_TEST_CLK_SEL _PMREG(0x0A4)
-#define LPC32XX_CLKPWR_SFW_INT _PMREG(0x0A8)
-#define LPC32XX_CLKPWR_I2C_CLK_CTRL _PMREG(0x0AC)
-#define LPC32XX_CLKPWR_KEY_CLK_CTRL _PMREG(0x0B0)
-#define LPC32XX_CLKPWR_ADC_CLK_CTRL _PMREG(0x0B4)
-#define LPC32XX_CLKPWR_PWM_CLK_CTRL _PMREG(0x0B8)
-#define LPC32XX_CLKPWR_TIMER_CLK_CTRL _PMREG(0x0BC)
-#define LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1 _PMREG(0x0C0)
-#define LPC32XX_CLKPWR_SPI_CLK_CTRL _PMREG(0x0C4)
-#define LPC32XX_CLKPWR_NAND_CLK_CTRL _PMREG(0x0C8)
-#define LPC32XX_CLKPWR_UART3_CLK_CTRL _PMREG(0x0D0)
-#define LPC32XX_CLKPWR_UART4_CLK_CTRL _PMREG(0x0D4)
-#define LPC32XX_CLKPWR_UART5_CLK_CTRL _PMREG(0x0D8)
-#define LPC32XX_CLKPWR_UART6_CLK_CTRL _PMREG(0x0DC)
-#define LPC32XX_CLKPWR_IRDA_CLK_CTRL _PMREG(0x0E0)
-#define LPC32XX_CLKPWR_UART_CLK_CTRL _PMREG(0x0E4)
-#define LPC32XX_CLKPWR_DMA_CLK_CTRL _PMREG(0x0E8)
-#define LPC32XX_CLKPWR_AUTOCLOCK _PMREG(0x0EC)
-#define LPC32XX_CLKPWR_DEVID(x) _PMREG(0x130 + (x))
-
-/*
- * clkpwr_debug_ctrl register definitions
-*/
-#define LPC32XX_CLKPWR_VFP_CLOCK_ENABLE_BIT _BIT(4)
-
-/*
- * clkpwr_bootmap register definitions
- */
-#define LPC32XX_CLKPWR_BOOTMAP_SEL_BIT _BIT(1)
-
-/*
- * clkpwr_start_gpio register bit definitions
- */
-#define LPC32XX_CLKPWR_GPIOSRC_P1IO23_BIT _BIT(31)
-#define LPC32XX_CLKPWR_GPIOSRC_P1IO22_BIT _BIT(30)
-#define LPC32XX_CLKPWR_GPIOSRC_P1IO21_BIT _BIT(29)
-#define LPC32XX_CLKPWR_GPIOSRC_P1IO20_BIT _BIT(28)
-#define LPC32XX_CLKPWR_GPIOSRC_P1IO19_BIT _BIT(27)
-#define LPC32XX_CLKPWR_GPIOSRC_P1IO18_BIT _BIT(26)
-#define LPC32XX_CLKPWR_GPIOSRC_P1IO17_BIT _BIT(25)
-#define LPC32XX_CLKPWR_GPIOSRC_P1IO16_BIT _BIT(24)
-#define LPC32XX_CLKPWR_GPIOSRC_P1IO15_BIT _BIT(23)
-#define LPC32XX_CLKPWR_GPIOSRC_P1IO14_BIT _BIT(22)
-#define LPC32XX_CLKPWR_GPIOSRC_P1IO13_BIT _BIT(21)
-#define LPC32XX_CLKPWR_GPIOSRC_P1IO12_BIT _BIT(20)
-#define LPC32XX_CLKPWR_GPIOSRC_P1IO11_BIT _BIT(19)
-#define LPC32XX_CLKPWR_GPIOSRC_P1IO10_BIT _BIT(18)
-#define LPC32XX_CLKPWR_GPIOSRC_P1IO9_BIT _BIT(17)
-#define LPC32XX_CLKPWR_GPIOSRC_P1IO8_BIT _BIT(16)
-#define LPC32XX_CLKPWR_GPIOSRC_P1IO7_BIT _BIT(15)
-#define LPC32XX_CLKPWR_GPIOSRC_P1IO6_BIT _BIT(14)
-#define LPC32XX_CLKPWR_GPIOSRC_P1IO5_BIT _BIT(13)
-#define LPC32XX_CLKPWR_GPIOSRC_P1IO4_BIT _BIT(12)
-#define LPC32XX_CLKPWR_GPIOSRC_P1IO3_BIT _BIT(11)
-#define LPC32XX_CLKPWR_GPIOSRC_P1IO2_BIT _BIT(10)
-#define LPC32XX_CLKPWR_GPIOSRC_P1IO1_BIT _BIT(9)
-#define LPC32XX_CLKPWR_GPIOSRC_P1IO0_BIT _BIT(8)
-#define LPC32XX_CLKPWR_GPIOSRC_P0IO7_BIT _BIT(7)
-#define LPC32XX_CLKPWR_GPIOSRC_P0IO6_BIT _BIT(6)
-#define LPC32XX_CLKPWR_GPIOSRC_P0IO5_BIT _BIT(5)
-#define LPC32XX_CLKPWR_GPIOSRC_P0IO4_BIT _BIT(4)
-#define LPC32XX_CLKPWR_GPIOSRC_P0IO3_BIT _BIT(3)
-#define LPC32XX_CLKPWR_GPIOSRC_P0IO2_BIT _BIT(2)
-#define LPC32XX_CLKPWR_GPIOSRC_P0IO1_BIT _BIT(1)
-#define LPC32XX_CLKPWR_GPIOSRC_P0IO0_BIT _BIT(0)
-
-/*
- * clkpwr_usbclk_pdiv register definitions
- */
-#define LPC32XX_CLKPWR_USBPDIV_PLL_MASK 0xF
-
-/*
- * clkpwr_start_int, clkpwr_start_raw_sts_int, clkpwr_start_sts_int,
- * clkpwr_start_pol_int, register bit definitions
- */
-#define LPC32XX_CLKPWR_INTSRC_ADC_BIT _BIT(31)
-#define LPC32XX_CLKPWR_INTSRC_TS_P_BIT _BIT(30)
-#define LPC32XX_CLKPWR_INTSRC_TS_AUX_BIT _BIT(29)
-#define LPC32XX_CLKPWR_INTSRC_USBAHNEEDCLK_BIT _BIT(26)
-#define LPC32XX_CLKPWR_INTSRC_MSTIMER_BIT _BIT(25)
-#define LPC32XX_CLKPWR_INTSRC_RTC_BIT _BIT(24)
-#define LPC32XX_CLKPWR_INTSRC_USBNEEDCLK_BIT _BIT(23)
-#define LPC32XX_CLKPWR_INTSRC_USB_BIT _BIT(22)
-#define LPC32XX_CLKPWR_INTSRC_I2C_BIT _BIT(21)
-#define LPC32XX_CLKPWR_INTSRC_USBOTGTIMER_BIT _BIT(20)
-#define LPC32XX_CLKPWR_INTSRC_USBATXINT_BIT _BIT(19)
-#define LPC32XX_CLKPWR_INTSRC_KEY_BIT _BIT(16)
-#define LPC32XX_CLKPWR_INTSRC_MAC_BIT _BIT(7)
-#define LPC32XX_CLKPWR_INTSRC_P0P1_BIT _BIT(6)
-#define LPC32XX_CLKPWR_INTSRC_GPIO_05_BIT _BIT(5)
-#define LPC32XX_CLKPWR_INTSRC_GPIO_04_BIT _BIT(4)
-#define LPC32XX_CLKPWR_INTSRC_GPIO_03_BIT _BIT(3)
-#define LPC32XX_CLKPWR_INTSRC_GPIO_02_BIT _BIT(2)
-#define LPC32XX_CLKPWR_INTSRC_GPIO_01_BIT _BIT(1)
-#define LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT _BIT(0)
-
-/*
- * clkpwr_start_pin, clkpwr_start_raw_sts_pin, clkpwr_start_sts_pin,
- * clkpwr_start_pol_pin register bit definitions
- */
-#define LPC32XX_CLKPWR_EXTSRC_U7_RX_BIT _BIT(31)
-#define LPC32XX_CLKPWR_EXTSRC_U7_HCTS_BIT _BIT(30)
-#define LPC32XX_CLKPWR_EXTSRC_U6_IRRX_BIT _BIT(28)
-#define LPC32XX_CLKPWR_EXTSRC_U5_RX_BIT _BIT(26)
-#define LPC32XX_CLKPWR_EXTSRC_GPI_28_BIT _BIT(25)
-#define LPC32XX_CLKPWR_EXTSRC_U3_RX_BIT _BIT(24)
-#define LPC32XX_CLKPWR_EXTSRC_U2_HCTS_BIT _BIT(23)
-#define LPC32XX_CLKPWR_EXTSRC_U2_RX_BIT _BIT(22)
-#define LPC32XX_CLKPWR_EXTSRC_U1_RX_BIT _BIT(21)
-#define LPC32XX_CLKPWR_EXTSRC_MSDIO_INT_BIT _BIT(18)
-#define LPC32XX_CLKPWR_EXTSRC_MSDIO_SRT_BIT _BIT(17)
-#define LPC32XX_CLKPWR_EXTSRC_GPI_06_BIT _BIT(16)
-#define LPC32XX_CLKPWR_EXTSRC_GPI_05_BIT _BIT(15)
-#define LPC32XX_CLKPWR_EXTSRC_GPI_04_BIT _BIT(14)
-#define LPC32XX_CLKPWR_EXTSRC_GPI_03_BIT _BIT(13)
-#define LPC32XX_CLKPWR_EXTSRC_GPI_02_BIT _BIT(12)
-#define LPC32XX_CLKPWR_EXTSRC_GPI_01_BIT _BIT(11)
-#define LPC32XX_CLKPWR_EXTSRC_GPI_00_BIT _BIT(10)
-#define LPC32XX_CLKPWR_EXTSRC_SYSCLKEN_BIT _BIT(9)
-#define LPC32XX_CLKPWR_EXTSRC_SPI1_DATIN_BIT _BIT(8)
-#define LPC32XX_CLKPWR_EXTSRC_GPI_07_BIT _BIT(7)
-#define LPC32XX_CLKPWR_EXTSRC_SPI2_DATIN_BIT _BIT(6)
-#define LPC32XX_CLKPWR_EXTSRC_GPI_19_BIT _BIT(5)
-#define LPC32XX_CLKPWR_EXTSRC_GPI_09_BIT _BIT(4)
-#define LPC32XX_CLKPWR_EXTSRC_GPI_08_BIT _BIT(3)
-
-/*
- * clkpwr_hclk_div register definitions
- */
-#define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_STOP (0x0 << 7)
-#define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_NORM (0x1 << 7)
-#define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_HALF (0x2 << 7)
-#define LPC32XX_CLKPWR_HCLKDIV_PCLK_DIV(n) (((n) & 0x1F) << 2)
-#define LPC32XX_CLKPWR_HCLKDIV_DIV_2POW(n) ((n) & 0x3)
-
-/*
- * clkpwr_pwr_ctrl register definitions
- */
-#define LPC32XX_CLKPWR_CTRL_FORCE_PCLK _BIT(10)
-#define LPC32XX_CLKPWR_SDRAM_SELF_RFSH _BIT(9)
-#define LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH _BIT(8)
-#define LPC32XX_CLKPWR_AUTO_SDRAM_SELF_RFSH _BIT(7)
-#define LPC32XX_CLKPWR_HIGHCORE_STATE_BIT _BIT(5)
-#define LPC32XX_CLKPWR_SYSCLKEN_STATE_BIT _BIT(4)
-#define LPC32XX_CLKPWR_SYSCLKEN_GPIO_EN _BIT(3)
-#define LPC32XX_CLKPWR_SELECT_RUN_MODE _BIT(2)
-#define LPC32XX_CLKPWR_HIGHCORE_GPIO_EN _BIT(1)
-#define LPC32XX_CLKPWR_STOP_MODE_CTRL _BIT(0)
-
-/*
- * clkpwr_pll397_ctrl register definitions
- */
-#define LPC32XX_CLKPWR_PLL397_MSLOCK_STS _BIT(10)
-#define LPC32XX_CLKPWR_PLL397_BYPASS _BIT(9)
-#define LPC32XX_CLKPWR_PLL397_BIAS_NORM 0x000
-#define LPC32XX_CLKPWR_PLL397_BIAS_N12_5 0x040
-#define LPC32XX_CLKPWR_PLL397_BIAS_N25 0x080
-#define LPC32XX_CLKPWR_PLL397_BIAS_N37_5 0x0C0
-#define LPC32XX_CLKPWR_PLL397_BIAS_P12_5 0x100
-#define LPC32XX_CLKPWR_PLL397_BIAS_P25 0x140
-#define LPC32XX_CLKPWR_PLL397_BIAS_P37_5 0x180
-#define LPC32XX_CLKPWR_PLL397_BIAS_P50 0x1C0
-#define LPC32XX_CLKPWR_PLL397_BIAS_MASK 0x1C0
-#define LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS _BIT(1)
-#define LPC32XX_CLKPWR_SYSCTRL_PLL397_STS _BIT(0)
-
-/*
- * clkpwr_main_osc_ctrl register definitions
- */
-#define LPC32XX_CLKPWR_MOSC_ADD_CAP(n) (((n) & 0x7F) << 2)
-#define LPC32XX_CLKPWR_MOSC_CAP_MASK (0x7F << 2)
-#define LPC32XX_CLKPWR_TEST_MODE _BIT(1)
-#define LPC32XX_CLKPWR_MOSC_DISABLE _BIT(0)
-
-/*
- * clkpwr_sysclk_ctrl register definitions
- */
-#define LPC32XX_CLKPWR_SYSCTRL_BP_TRIG(n) (((n) & 0x3FF) << 2)
-#define LPC32XX_CLKPWR_SYSCTRL_BP_MASK (0x3FF << 2)
-#define LPC32XX_CLKPWR_SYSCTRL_USEPLL397 _BIT(1)
-#define LPC32XX_CLKPWR_SYSCTRL_SYSCLKMUX _BIT(0)
-
-/*
- * clkpwr_lcdclk_ctrl register definitions
- */
-#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT12 0x000
-#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16 0x040
-#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT15 0x080
-#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT24 0x0C0
-#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_STN4M 0x100
-#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_STN8C 0x140
-#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_DSTN4M 0x180
-#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_DSTN8C 0x1C0
-#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK 0x01C0
-#define LPC32XX_CLKPWR_LCDCTRL_CLK_EN 0x020
-#define LPC32XX_CLKPWR_LCDCTRL_SET_PSCALE(n) ((n - 1) & 0x1F)
-#define LPC32XX_CLKPWR_LCDCTRL_PSCALE_MSK 0x001F
-
-/*
- * clkpwr_hclkpll_ctrl register definitions
- */
-#define LPC32XX_CLKPWR_HCLKPLL_POWER_UP _BIT(16)
-#define LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS _BIT(15)
-#define LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS _BIT(14)
-#define LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK _BIT(13)
-#define LPC32XX_CLKPWR_HCLKPLL_POSTDIV_2POW(n) (((n) & 0x3) << 11)
-#define LPC32XX_CLKPWR_HCLKPLL_PREDIV_PLUS1(n) (((n) & 0x3) << 9)
-#define LPC32XX_CLKPWR_HCLKPLL_PLLM(n) (((n) & 0xFF) << 1)
-#define LPC32XX_CLKPWR_HCLKPLL_PLL_STS _BIT(0)
-
-/*
- * clkpwr_adc_clk_ctrl_1 register definitions
- */
-#define LPC32XX_CLKPWR_ADCCTRL1_RTDIV(n) (((n) & 0xFF) << 0)
-#define LPC32XX_CLKPWR_ADCCTRL1_PCLK_SEL _BIT(8)
-
-/*
- * clkpwr_usb_ctrl register definitions
- */
-#define LPC32XX_CLKPWR_USBCTRL_HCLK_EN _BIT(24)
-#define LPC32XX_CLKPWR_USBCTRL_USBI2C_EN _BIT(23)
-#define LPC32XX_CLKPWR_USBCTRL_USBDVND_EN _BIT(22)
-#define LPC32XX_CLKPWR_USBCTRL_USBHSTND_EN _BIT(21)
-#define LPC32XX_CLKPWR_USBCTRL_PU_ADD (0x0 << 19)
-#define LPC32XX_CLKPWR_USBCTRL_BUS_KEEPER (0x1 << 19)
-#define LPC32XX_CLKPWR_USBCTRL_PD_ADD (0x3 << 19)
-#define LPC32XX_CLKPWR_USBCTRL_CLK_EN2 _BIT(18)
-#define LPC32XX_CLKPWR_USBCTRL_CLK_EN1 _BIT(17)
-#define LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP _BIT(16)
-#define LPC32XX_CLKPWR_USBCTRL_CCO_BYPASS _BIT(15)
-#define LPC32XX_CLKPWR_USBCTRL_POSTDIV_BYPASS _BIT(14)
-#define LPC32XX_CLKPWR_USBCTRL_FDBK_SEL_FCLK _BIT(13)
-#define LPC32XX_CLKPWR_USBCTRL_POSTDIV_2POW(n) (((n) & 0x3) << 11)
-#define LPC32XX_CLKPWR_USBCTRL_PREDIV_PLUS1(n) (((n) & 0x3) << 9)
-#define LPC32XX_CLKPWR_USBCTRL_FDBK_PLUS1(n) (((n) & 0xFF) << 1)
-#define LPC32XX_CLKPWR_USBCTRL_PLL_STS _BIT(0)
-
-/*
- * clkpwr_sdramclk_ctrl register definitions
- */
-#define LPC32XX_CLKPWR_SDRCLK_FASTSLEW_CLK _BIT(22)
-#define LPC32XX_CLKPWR_SDRCLK_FASTSLEW _BIT(21)
-#define LPC32XX_CLKPWR_SDRCLK_FASTSLEW_DAT _BIT(20)
-#define LPC32XX_CLKPWR_SDRCLK_SW_DDR_RESET _BIT(19)
-#define LPC32XX_CLKPWR_SDRCLK_HCLK_DLY(n) (((n) & 0x1F) << 14)
-#define LPC32XX_CLKPWR_SDRCLK_DLY_ADDR_STS _BIT(13)
-#define LPC32XX_CLKPWR_SDRCLK_SENS_FACT(n) (((n) & 0x7) << 10)
-#define LPC32XX_CLKPWR_SDRCLK_USE_CAL _BIT(9)
-#define LPC32XX_CLKPWR_SDRCLK_DO_CAL _BIT(8)
-#define LPC32XX_CLKPWR_SDRCLK_CAL_ON_RTC _BIT(7)
-#define LPC32XX_CLKPWR_SDRCLK_DQS_DLY(n) (((n) & 0x1F) << 2)
-#define LPC32XX_CLKPWR_SDRCLK_USE_DDR _BIT(1)
-#define LPC32XX_CLKPWR_SDRCLK_CLK_DIS _BIT(0)
-
-/*
- * clkpwr_ssp_blk_ctrl register definitions
- */
-#define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP1RX _BIT(5)
-#define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP1TX _BIT(4)
-#define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP0RX _BIT(3)
-#define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP0TX _BIT(2)
-#define LPC32XX_CLKPWR_SSPCTRL_SSPCLK1_EN _BIT(1)
-#define LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN _BIT(0)
-
-/*
- * clkpwr_i2s_clk_ctrl register definitions
- */
-#define LPC32XX_CLKPWR_I2SCTRL_I2S1_RX_FOR_TX _BIT(6)
-#define LPC32XX_CLKPWR_I2SCTRL_I2S1_TX_FOR_RX _BIT(5)
-#define LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA _BIT(4)
-#define LPC32XX_CLKPWR_I2SCTRL_I2S0_RX_FOR_TX _BIT(3)
-#define LPC32XX_CLKPWR_I2SCTRL_I2S0_TX_FOR_RX _BIT(2)
-#define LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN _BIT(1)
-#define LPC32XX_CLKPWR_I2SCTRL_I2SCLK0_EN _BIT(0)
-
-/*
- * clkpwr_ms_ctrl register definitions
- */
-#define LPC32XX_CLKPWR_MSCARD_MSDIO_PIN_DIS _BIT(10)
-#define LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN _BIT(9)
-#define LPC32XX_CLKPWR_MSCARD_MSDIO23_DIS _BIT(8)
-#define LPC32XX_CLKPWR_MSCARD_MSDIO1_DIS _BIT(7)
-#define LPC32XX_CLKPWR_MSCARD_MSDIO0_DIS _BIT(6)
-#define LPC32XX_CLKPWR_MSCARD_SDCARD_EN _BIT(5)
-#define LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(n) ((n) & 0xF)
-
-/*
- * clkpwr_macclk_ctrl register definitions
- */
-#define LPC32XX_CLKPWR_MACCTRL_NO_ENET_PIS 0x00
-#define LPC32XX_CLKPWR_MACCTRL_USE_MII_PINS 0x08
-#define LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS 0x18
-#define LPC32XX_CLKPWR_MACCTRL_PINS_MSK 0x18
-#define LPC32XX_CLKPWR_MACCTRL_DMACLK_EN _BIT(2)
-#define LPC32XX_CLKPWR_MACCTRL_MMIOCLK_EN _BIT(1)
-#define LPC32XX_CLKPWR_MACCTRL_HRCCLK_EN _BIT(0)
-
-/*
- * clkpwr_test_clk_sel register definitions
- */
-#define LPC32XX_CLKPWR_TESTCLK1_SEL_PERCLK (0x0 << 5)
-#define LPC32XX_CLKPWR_TESTCLK1_SEL_RTC (0x1 << 5)
-#define LPC32XX_CLKPWR_TESTCLK1_SEL_MOSC (0x2 << 5)
-#define LPC32XX_CLKPWR_TESTCLK1_SEL_MASK (0x3 << 5)
-#define LPC32XX_CLKPWR_TESTCLK_TESTCLK1_EN _BIT(4)
-#define LPC32XX_CLKPWR_TESTCLK2_SEL_HCLK (0x0 << 1)
-#define LPC32XX_CLKPWR_TESTCLK2_SEL_PERCLK (0x1 << 1)
-#define LPC32XX_CLKPWR_TESTCLK2_SEL_USBCLK (0x2 << 1)
-#define LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC (0x5 << 1)
-#define LPC32XX_CLKPWR_TESTCLK2_SEL_PLL397 (0x7 << 1)
-#define LPC32XX_CLKPWR_TESTCLK2_SEL_MASK (0x7 << 1)
-#define LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN _BIT(0)
-
-/*
- * clkpwr_sw_int register definitions
- */
-#define LPC32XX_CLKPWR_SW_INT(n) (_BIT(0) | (((n) & 0x7F) << 1))
-#define LPC32XX_CLKPWR_SW_GET_ARG(n) (((n) & 0xFE) >> 1)
-
-/*
- * clkpwr_i2c_clk_ctrl register definitions
- */
-#define LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE _BIT(4)
-#define LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE _BIT(3)
-#define LPC32XX_CLKPWR_I2CCLK_I2C1HI_DRIVE _BIT(2)
-#define LPC32XX_CLKPWR_I2CCLK_I2C2CLK_EN _BIT(1)
-#define LPC32XX_CLKPWR_I2CCLK_I2C1CLK_EN _BIT(0)
-
-/*
- * clkpwr_key_clk_ctrl register definitions
- */
-#define LPC32XX_CLKPWR_KEYCLKCTRL_CLK_EN 0x1
-
-/*
- * clkpwr_adc_clk_ctrl register definitions
- */
-#define LPC32XX_CLKPWR_ADC32CLKCTRL_CLK_EN 0x1
-
-/*
- * clkpwr_pwm_clk_ctrl register definitions
- */
-#define LPC32XX_CLKPWR_PWMCLK_PWM2_DIV(n) (((n) & 0xF) << 8)
-#define LPC32XX_CLKPWR_PWMCLK_PWM1_DIV(n) (((n) & 0xF) << 4)
-#define LPC32XX_CLKPWR_PWMCLK_PWM2SEL_PCLK 0x8
-#define LPC32XX_CLKPWR_PWMCLK_PWM2CLK_EN 0x4
-#define LPC32XX_CLKPWR_PWMCLK_PWM1SEL_PCLK 0x2
-#define LPC32XX_CLKPWR_PWMCLK_PWM1CLK_EN 0x1
-
-/*
- * clkpwr_timer_clk_ctrl register definitions
- */
-#define LPC32XX_CLKPWR_PWMCLK_HSTIMER_EN 0x2
-#define LPC32XX_CLKPWR_PWMCLK_WDOG_EN 0x1
-
-/*
- * clkpwr_timers_pwms_clk_ctrl_1 register definitions
- */
-#define LPC32XX_CLKPWR_TMRPWMCLK_MPWM_EN 0x40
-#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN 0x20
-#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN 0x10
-#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN 0x08
-#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN 0x04
-#define LPC32XX_CLKPWR_TMRPWMCLK_PWM4_EN 0x02
-#define LPC32XX_CLKPWR_TMRPWMCLK_PWM3_EN 0x01
-
-/*
- * clkpwr_spi_clk_ctrl register definitions
- */
-#define LPC32XX_CLKPWR_SPICLK_SET_SPI2DATIO 0x80
-#define LPC32XX_CLKPWR_SPICLK_SET_SPI2CLK 0x40
-#define LPC32XX_CLKPWR_SPICLK_USE_SPI2 0x20
-#define LPC32XX_CLKPWR_SPICLK_SPI2CLK_EN 0x10
-#define LPC32XX_CLKPWR_SPICLK_SET_SPI1DATIO 0x08
-#define LPC32XX_CLKPWR_SPICLK_SET_SPI1CLK 0x04
-#define LPC32XX_CLKPWR_SPICLK_USE_SPI1 0x02
-#define LPC32XX_CLKPWR_SPICLK_SPI1CLK_EN 0x01
-
-/*
- * clkpwr_nand_clk_ctrl register definitions
- */
-#define LPC32XX_CLKPWR_NANDCLK_INTSEL_MLC 0x20
-#define LPC32XX_CLKPWR_NANDCLK_DMA_RNB 0x10
-#define LPC32XX_CLKPWR_NANDCLK_DMA_INT 0x08
-#define LPC32XX_CLKPWR_NANDCLK_SEL_SLC 0x04
-#define LPC32XX_CLKPWR_NANDCLK_MLCCLK_EN 0x02
-#define LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN 0x01
-
-/*
- * clkpwr_uart3_clk_ctrl, clkpwr_uart4_clk_ctrl, clkpwr_uart5_clk_ctrl
- * and clkpwr_uart6_clk_ctrl register definitions
- */
-#define LPC32XX_CLKPWR_UART_Y_DIV(y) ((y) & 0xFF)
-#define LPC32XX_CLKPWR_UART_X_DIV(x) (((x) & 0xFF) << 8)
-#define LPC32XX_CLKPWR_UART_USE_HCLK _BIT(16)
-
-/*
- * clkpwr_irda_clk_ctrl register definitions
- */
-#define LPC32XX_CLKPWR_IRDA_Y_DIV(y) ((y) & 0xFF)
-#define LPC32XX_CLKPWR_IRDA_X_DIV(x) (((x) & 0xFF) << 8)
-
-/*
- * clkpwr_uart_clk_ctrl register definitions
- */
-#define LPC32XX_CLKPWR_UARTCLKCTRL_UART6_EN _BIT(3)
-#define LPC32XX_CLKPWR_UARTCLKCTRL_UART5_EN _BIT(2)
-#define LPC32XX_CLKPWR_UARTCLKCTRL_UART4_EN _BIT(1)
-#define LPC32XX_CLKPWR_UARTCLKCTRL_UART3_EN _BIT(0)
-
-/*
- * clkpwr_dmaclk_ctrl register definitions
- */
-#define LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN 0x1
-
-/*
- * clkpwr_autoclock register definitions
- */
-#define LPC32XX_CLKPWR_AUTOCLK_USB_EN 0x40
-#define LPC32XX_CLKPWR_AUTOCLK_IRAM_EN 0x02
-#define LPC32XX_CLKPWR_AUTOCLK_IROM_EN 0x01
-
-/*
- * Interrupt controller register offsets
- */
-#define LPC32XX_INTC_MASK(x) io_p2v((x) + 0x00)
-#define LPC32XX_INTC_RAW_STAT(x) io_p2v((x) + 0x04)
-#define LPC32XX_INTC_STAT(x) io_p2v((x) + 0x08)
-#define LPC32XX_INTC_POLAR(x) io_p2v((x) + 0x0C)
-#define LPC32XX_INTC_ACT_TYPE(x) io_p2v((x) + 0x10)
-#define LPC32XX_INTC_TYPE(x) io_p2v((x) + 0x14)
-
-/*
- * Timer/counter register offsets
- */
-#define LPC32XX_TIMER_IR(x) io_p2v((x) + 0x00)
-#define LPC32XX_TIMER_TCR(x) io_p2v((x) + 0x04)
-#define LPC32XX_TIMER_TC(x) io_p2v((x) + 0x08)
-#define LPC32XX_TIMER_PR(x) io_p2v((x) + 0x0C)
-#define LPC32XX_TIMER_PC(x) io_p2v((x) + 0x10)
-#define LPC32XX_TIMER_MCR(x) io_p2v((x) + 0x14)
-#define LPC32XX_TIMER_MR0(x) io_p2v((x) + 0x18)
-#define LPC32XX_TIMER_MR1(x) io_p2v((x) + 0x1C)
-#define LPC32XX_TIMER_MR2(x) io_p2v((x) + 0x20)
-#define LPC32XX_TIMER_MR3(x) io_p2v((x) + 0x24)
-#define LPC32XX_TIMER_CCR(x) io_p2v((x) + 0x28)
-#define LPC32XX_TIMER_CR0(x) io_p2v((x) + 0x2C)
-#define LPC32XX_TIMER_CR1(x) io_p2v((x) + 0x30)
-#define LPC32XX_TIMER_CR2(x) io_p2v((x) + 0x34)
-#define LPC32XX_TIMER_CR3(x) io_p2v((x) + 0x38)
-#define LPC32XX_TIMER_EMR(x) io_p2v((x) + 0x3C)
-#define LPC32XX_TIMER_CTCR(x) io_p2v((x) + 0x70)
-
-/*
- * ir register definitions
- */
-#define LPC32XX_TIMER_CNTR_MTCH_BIT(n) (1 << ((n) & 0x3))
-#define LPC32XX_TIMER_CNTR_CAPT_BIT(n) (1 << (4 + ((n) & 0x3)))
-
-/*
- * tcr register definitions
- */
-#define LPC32XX_TIMER_CNTR_TCR_EN 0x1
-#define LPC32XX_TIMER_CNTR_TCR_RESET 0x2
-
-/*
- * mcr register definitions
- */
-#define LPC32XX_TIMER_CNTR_MCR_MTCH(n) (0x1 << ((n) * 3))
-#define LPC32XX_TIMER_CNTR_MCR_RESET(n) (0x1 << (((n) * 3) + 1))
-#define LPC32XX_TIMER_CNTR_MCR_STOP(n) (0x1 << (((n) * 3) + 2))
-
-/*
- * Standard UART register offsets
- */
-#define LPC32XX_UART_DLL_FIFO(x) io_p2v((x) + 0x00)
-#define LPC32XX_UART_DLM_IER(x) io_p2v((x) + 0x04)
-#define LPC32XX_UART_IIR_FCR(x) io_p2v((x) + 0x08)
-#define LPC32XX_UART_LCR(x) io_p2v((x) + 0x0C)
-#define LPC32XX_UART_MODEM_CTRL(x) io_p2v((x) + 0x10)
-#define LPC32XX_UART_LSR(x) io_p2v((x) + 0x14)
-#define LPC32XX_UART_MODEM_STATUS(x) io_p2v((x) + 0x18)
-#define LPC32XX_UART_RXLEV(x) io_p2v((x) + 0x1C)
-
-/*
- * UART control structure offsets
- */
-#define _UCREG(x) io_p2v(\
- LPC32XX_UART_CTRL_BASE + (x))
-#define LPC32XX_UARTCTL_CTRL _UCREG(0x00)
-#define LPC32XX_UARTCTL_CLKMODE _UCREG(0x04)
-#define LPC32XX_UARTCTL_CLOOP _UCREG(0x08)
-
-/*
- * ctrl register definitions
- */
-#define LPC32XX_UART_U3_MD_CTRL_EN _BIT(11)
-#define LPC32XX_UART_IRRX6_INV_EN _BIT(10)
-#define LPC32XX_UART_HDPX_EN _BIT(9)
-#define LPC32XX_UART_UART6_IRDAMOD_BYPASS _BIT(5)
-#define LPC32XX_RT_IRTX6_INV_EN _BIT(4)
-#define LPC32XX_RT_IRTX6_INV_MIR_EN _BIT(3)
-#define LPC32XX_RT_RX_IRPULSE_3_16_115K _BIT(2)
-#define LPC32XX_RT_TX_IRPULSE_3_16_115K _BIT(1)
-#define LPC32XX_UART_U5_ROUTE_TO_USB _BIT(0)
-
-/*
- * clkmode register definitions
- */
-#define LPC32XX_UART_ENABLED_CLOCKS(n) (((n) >> 16) & 0x7F)
-#define LPC32XX_UART_ENABLED_CLOCK(n, u) (((n) >> (16 + (u))) & 0x1)
-#define LPC32XX_UART_ENABLED_CLKS_ANY _BIT(14)
-#define LPC32XX_UART_CLKMODE_OFF 0x0
-#define LPC32XX_UART_CLKMODE_ON 0x1
-#define LPC32XX_UART_CLKMODE_AUTO 0x2
-#define LPC32XX_UART_CLKMODE_MASK(u) (0x3 << ((((u) - 3) * 2) + 4))
-#define LPC32XX_UART_CLKMODE_LOAD(m, u) ((m) << ((((u) - 3) * 2) + 4))
-
-/*
- * GPIO Module Register offsets
- */
-#define _GPREG(x) io_p2v(LPC32XX_GPIO_BASE + (x))
-#define LPC32XX_GPIO_P_MUX_SET _GPREG(0x100)
-#define LPC32XX_GPIO_P_MUX_CLR _GPREG(0x104)
-#define LPC32XX_GPIO_P_MUX_STATE _GPREG(0x108)
-#define LPC32XX_GPIO_P3_MUX_SET _GPREG(0x110)
-#define LPC32XX_GPIO_P3_MUX_CLR _GPREG(0x114)
-#define LPC32XX_GPIO_P3_MUX_STATE _GPREG(0x118)
-#define LPC32XX_GPIO_P0_MUX_SET _GPREG(0x120)
-#define LPC32XX_GPIO_P0_MUX_CLR _GPREG(0x124)
-#define LPC32XX_GPIO_P0_MUX_STATE _GPREG(0x128)
-#define LPC32XX_GPIO_P1_MUX_SET _GPREG(0x130)
-#define LPC32XX_GPIO_P1_MUX_CLR _GPREG(0x134)
-#define LPC32XX_GPIO_P1_MUX_STATE _GPREG(0x138)
-#define LPC32XX_GPIO_P2_MUX_SET _GPREG(0x028)
-#define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C)
-#define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030)
-
-/*
- * USB Otg Registers
- */
-#define _OTGREG(x) io_p2v(LPC32XX_USB_OTG_BASE + (x))
-#define LPC32XX_USB_OTG_CLK_CTRL _OTGREG(0xFF4)
-#define LPC32XX_USB_OTG_CLK_STAT _OTGREG(0xFF8)
-
-/* USB OTG CLK CTRL bit defines */
-#define LPC32XX_USB_OTG_AHB_M_CLOCK_ON _BIT(4)
-#define LPC32XX_USB_OTG_OTG_CLOCK_ON _BIT(3)
-#define LPC32XX_USB_OTG_I2C_CLOCK_ON _BIT(2)
-#define LPC32XX_USB_OTG_DEV_CLOCK_ON _BIT(1)
-#define LPC32XX_USB_OTG_HOST_CLOCK_ON _BIT(0)
-
-/*
- * Start of virtual addresses for IO devices
- */
-#define IO_BASE 0xF0000000
-
-/*
- * This macro relies on fact that for all HW i/o addresses bits 20-23 are 0
- */
-#define IO_ADDRESS(x) IOMEM(((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\
- IO_BASE)
-
-#define io_p2v(x) ((void __iomem *) (unsigned long) IO_ADDRESS(x))
-#define io_v2p(x) ((((x) & 0x0ff00000) << 4) | ((x) & 0x000fffff))
-
-#endif
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
deleted file mode 100644
index 66701bf432488..0000000000000
--- a/arch/arm/mach-lpc32xx/phy3250.c
+++ /dev/null
@@ -1,92 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Platform support for LPC32xx SoC
- *
- * Author: Kevin Wells <kevin.wells@nxp.com>
- *
- * Copyright (C) 2012 Roland Stigge <stigge@antcom.de>
- * Copyright (C) 2010 NXP Semiconductors
- */
-
-#include <linux/amba/pl08x.h>
-#include <linux/mtd/lpc32xx_mlc.h>
-#include <linux/mtd/lpc32xx_slc.h>
-#include <linux/of_platform.h>
-
-#include <asm/mach/arch.h>
-#include "common.h"
-
-static struct pl08x_channel_data pl08x_slave_channels[] = {
- {
- .bus_id = "nand-slc",
- .min_signal = 1, /* SLC NAND Flash */
- .max_signal = 1,
- .periph_buses = PL08X_AHB1,
- },
- {
- .bus_id = "nand-mlc",
- .min_signal = 12, /* MLC NAND Flash */
- .max_signal = 12,
- .periph_buses = PL08X_AHB1,
- },
-};
-
-static int pl08x_get_signal(const struct pl08x_channel_data *cd)
-{
- return cd->min_signal;
-}
-
-static void pl08x_put_signal(const struct pl08x_channel_data *cd, int ch)
-{
-}
-
-static struct pl08x_platform_data pl08x_pd = {
- /* Some reasonable memcpy defaults */
- .memcpy_burst_size = PL08X_BURST_SZ_256,
- .memcpy_bus_width = PL08X_BUS_WIDTH_32_BITS,
- .slave_channels = &pl08x_slave_channels[0],
- .num_slave_channels = ARRAY_SIZE(pl08x_slave_channels),
- .get_xfer_signal = pl08x_get_signal,
- .put_xfer_signal = pl08x_put_signal,
- .lli_buses = PL08X_AHB1,
- .mem_buses = PL08X_AHB1,
-};
-
-static struct lpc32xx_slc_platform_data lpc32xx_slc_data = {
- .dma_filter = pl08x_filter_id,
-};
-
-static struct lpc32xx_mlc_platform_data lpc32xx_mlc_data = {
- .dma_filter = pl08x_filter_id,
-};
-
-static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = {
- OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd),
- OF_DEV_AUXDATA("nxp,lpc3220-slc", 0x20020000, "20020000.flash",
- &lpc32xx_slc_data),
- OF_DEV_AUXDATA("nxp,lpc3220-mlc", 0x200a8000, "200a8000.flash",
- &lpc32xx_mlc_data),
- { }
-};
-
-static void __init lpc3250_machine_init(void)
-{
- lpc32xx_serial_init();
-
- of_platform_default_populate(NULL, lpc32xx_auxdata_lookup, NULL);
-}
-
-static const char *const lpc32xx_dt_compat[] __initconst = {
- "nxp,lpc3220",
- "nxp,lpc3230",
- "nxp,lpc3240",
- "nxp,lpc3250",
- NULL
-};
-
-DT_MACHINE_START(LPC32XX_DT, "LPC32XX SoC (Flattened Device Tree)")
- .atag_offset = 0x100,
- .map_io = lpc32xx_map_io,
- .init_machine = lpc3250_machine_init,
- .dt_compat = lpc32xx_dt_compat,
-MACHINE_END
diff --git a/arch/arm/mach-lpc32xx/pm.c b/arch/arm/mach-lpc32xx/pm.c
deleted file mode 100644
index 2572bd89a5e8d..0000000000000
--- a/arch/arm/mach-lpc32xx/pm.c
+++ /dev/null
@@ -1,135 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * arch/arm/mach-lpc32xx/pm.c
- *
- * Original authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
- * Modified by Kevin Wells <kevin.wells@nxp.com>
- *
- * 2005 (c) MontaVista Software, Inc.
- */
-
-/*
- * LPC32XX CPU and system power management
- *
- * The LPC32XX has three CPU modes for controlling system power: run,
- * direct-run, and halt modes. When switching between halt and run modes,
- * the CPU transistions through direct-run mode. For Linux, direct-run
- * mode is not used in normal operation. Halt mode is used when the
- * system is fully suspended.
- *
- * Run mode:
- * The ARM CPU clock (HCLK_PLL), HCLK bus clock, and PCLK bus clocks are
- * derived from the HCLK PLL. The HCLK and PCLK bus rates are divided from
- * the HCLK_PLL rate. Linux runs in this mode.
- *
- * Direct-run mode:
- * The ARM CPU clock, HCLK bus clock, and PCLK bus clocks are driven from
- * SYSCLK. SYSCLK is usually around 13MHz, but may vary based on SYSCLK
- * source or the frequency of the main oscillator. In this mode, the
- * HCLK_PLL can be safely enabled, changed, or disabled.
- *
- * Halt mode:
- * SYSCLK is gated off and the CPU and system clocks are halted.
- * Peripherals based on the 32KHz oscillator clock (ie, RTC, touch,
- * key scanner, etc.) still operate if enabled. In this state, an enabled
- * system event (ie, GPIO state change, RTC match, key press, etc.) will
- * wake the system up back into direct-run mode.
- *
- * DRAM refresh
- * DRAM clocking and refresh are slightly different for systems with DDR
- * DRAM or regular SDRAM devices. If SDRAM is used in the system, the
- * SDRAM will still be accessible in direct-run mode. In DDR based systems,
- * a transition to direct-run mode will stop all DDR accesses (no clocks).
- * Because of this, the code to switch power modes and the code to enter
- * and exit DRAM self-refresh modes must not be executed in DRAM. A small
- * section of IRAM is used instead for this.
- *
- * Suspend is handled with the following logic:
- * Backup a small area of IRAM used for the suspend code
- * Copy suspend code to IRAM
- * Transfer control to code in IRAM
- * Places DRAMs in self-refresh mode
- * Enter direct-run mode
- * Save state of HCLK_PLL PLL
- * Disable HCLK_PLL PLL
- * Enter halt mode - CPU and buses will stop
- * System enters direct-run mode when an enabled event occurs
- * HCLK PLL state is restored
- * Run mode is entered
- * DRAMS are placed back into normal mode
- * Code execution returns from IRAM
- * IRAM code are used for suspend is restored
- * Suspend mode is exited
- */
-
-#include <linux/suspend.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-
-#include <asm/cacheflush.h>
-
-#include "lpc32xx.h"
-#include "common.h"
-
-#define TEMP_IRAM_AREA IO_ADDRESS(LPC32XX_IRAM_BASE)
-
-/*
- * Both STANDBY and MEM suspend states are handled the same with no
- * loss of CPU or memory state
- */
-static int lpc32xx_pm_enter(suspend_state_t state)
-{
- int (*lpc32xx_suspend_ptr) (void);
- void *iram_swap_area;
-
- /* Allocate some space for temporary IRAM storage */
- iram_swap_area = kmemdup((void *)TEMP_IRAM_AREA,
- lpc32xx_sys_suspend_sz, GFP_KERNEL);
- if (!iram_swap_area)
- return -ENOMEM;
-
- /*
- * Copy code to suspend system into IRAM. The suspend code
- * needs to run from IRAM as DRAM may no longer be available
- * when the PLL is stopped.
- */
- memcpy((void *) TEMP_IRAM_AREA, &lpc32xx_sys_suspend,
- lpc32xx_sys_suspend_sz);
- flush_icache_range((unsigned long)TEMP_IRAM_AREA,
- (unsigned long)(TEMP_IRAM_AREA) + lpc32xx_sys_suspend_sz);
-
- /* Transfer to suspend code in IRAM */
- lpc32xx_suspend_ptr = (void *) TEMP_IRAM_AREA;
- flush_cache_all();
- (void) lpc32xx_suspend_ptr();
-
- /* Restore original IRAM contents */
- memcpy((void *) TEMP_IRAM_AREA, iram_swap_area,
- lpc32xx_sys_suspend_sz);
-
- kfree(iram_swap_area);
-
- return 0;
-}
-
-static const struct platform_suspend_ops lpc32xx_pm_ops = {
- .valid = suspend_valid_only_mem,
- .enter = lpc32xx_pm_enter,
-};
-
-#define EMC_DYN_MEM_CTRL_OFS 0x20
-#define EMC_SRMMC (1 << 3)
-#define EMC_CTRL_REG io_p2v(LPC32XX_EMC_BASE + EMC_DYN_MEM_CTRL_OFS)
-static int __init lpc32xx_pm_init(void)
-{
- /*
- * Setup SDRAM self-refresh clock to automatically disable o
- * start of self-refresh. This only needs to be done once.
- */
- __raw_writel(__raw_readl(EMC_CTRL_REG) | EMC_SRMMC, EMC_CTRL_REG);
-
- suspend_set_ops(&lpc32xx_pm_ops);
-
- return 0;
-}
-arch_initcall(lpc32xx_pm_init);
diff --git a/arch/arm/mach-lpc32xx/serial.c b/arch/arm/mach-lpc32xx/serial.c
deleted file mode 100644
index 3b1203db81b2c..0000000000000
--- a/arch/arm/mach-lpc32xx/serial.c
+++ /dev/null
@@ -1,148 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * arch/arm/mach-lpc32xx/serial.c
- *
- * Author: Kevin Wells <kevin.wells@nxp.com>
- *
- * Copyright (C) 2010 NXP Semiconductors
- */
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/serial.h>
-#include <linux/serial_core.h>
-#include <linux/serial_reg.h>
-#include <linux/serial_8250.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/soc/nxp/lpc32xx-misc.h>
-
-#include "lpc32xx.h"
-#include "common.h"
-
-#define LPC32XX_SUART_FIFO_SIZE 64
-
-struct uartinit {
- char *uart_ck_name;
- u32 ck_mode_mask;
- void __iomem *pdiv_clk_reg;
- resource_size_t mapbase;
-};
-
-static struct uartinit uartinit_data[] __initdata = {
- {
- .uart_ck_name = "uart5_ck",
- .ck_mode_mask =
- LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 5),
- .pdiv_clk_reg = LPC32XX_CLKPWR_UART5_CLK_CTRL,
- .mapbase = LPC32XX_UART5_BASE,
- },
- {
- .uart_ck_name = "uart3_ck",
- .ck_mode_mask =
- LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 3),
- .pdiv_clk_reg = LPC32XX_CLKPWR_UART3_CLK_CTRL,
- .mapbase = LPC32XX_UART3_BASE,
- },
- {
- .uart_ck_name = "uart4_ck",
- .ck_mode_mask =
- LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 4),
- .pdiv_clk_reg = LPC32XX_CLKPWR_UART4_CLK_CTRL,
- .mapbase = LPC32XX_UART4_BASE,
- },
- {
- .uart_ck_name = "uart6_ck",
- .ck_mode_mask =
- LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 6),
- .pdiv_clk_reg = LPC32XX_CLKPWR_UART6_CLK_CTRL,
- .mapbase = LPC32XX_UART6_BASE,
- },
-};
-
-/* LPC3250 Errata HSUART.1: Hang workaround via loopback mode on inactivity */
-void lpc32xx_loopback_set(resource_size_t mapbase, int state)
-{
- int bit;
- u32 tmp;
-
- switch (mapbase) {
- case LPC32XX_HS_UART1_BASE:
- bit = 0;
- break;
- case LPC32XX_HS_UART2_BASE:
- bit = 1;
- break;
- case LPC32XX_HS_UART7_BASE:
- bit = 6;
- break;
- default:
- WARN(1, "lpc32xx_hs: Warning: Unknown port at %08x\n", mapbase);
- return;
- }
-
- tmp = readl(LPC32XX_UARTCTL_CLOOP);
- if (state)
- tmp |= (1 << bit);
- else
- tmp &= ~(1 << bit);
- writel(tmp, LPC32XX_UARTCTL_CLOOP);
-}
-EXPORT_SYMBOL_GPL(lpc32xx_loopback_set);
-
-void __init lpc32xx_serial_init(void)
-{
- u32 tmp, clkmodes = 0;
- struct clk *clk;
- unsigned int puart;
- int i, j;
-
- for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) {
- clk = clk_get(NULL, uartinit_data[i].uart_ck_name);
- if (!IS_ERR(clk)) {
- clk_enable(clk);
- }
-
- /* Setup UART clock modes for all UARTs, disable autoclock */
- clkmodes |= uartinit_data[i].ck_mode_mask;
-
- /* pre-UART clock divider set to 1 */
- __raw_writel(0x0101, uartinit_data[i].pdiv_clk_reg);
-
- /*
- * Force a flush of the RX FIFOs to work around a
- * HW bug
- */
- puart = uartinit_data[i].mapbase;
- __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart));
- __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart));
- j = LPC32XX_SUART_FIFO_SIZE;
- while (j--)
- tmp = __raw_readl(
- LPC32XX_UART_DLL_FIFO(puart));
- __raw_writel(0, LPC32XX_UART_IIR_FCR(puart));
- }
-
- /* This needs to be done after all UART clocks are setup */
- __raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE);
- for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) {
- /* Force a flush of the RX FIFOs to work around a HW bug */
- puart = uartinit_data[i].mapbase;
- __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart));
- __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart));
- j = LPC32XX_SUART_FIFO_SIZE;
- while (j--)
- tmp = __raw_readl(LPC32XX_UART_DLL_FIFO(puart));
- __raw_writel(0, LPC32XX_UART_IIR_FCR(puart));
- }
-
- /* Disable IrDA pulsing support on UART6 */
- tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
- tmp |= LPC32XX_UART_UART6_IRDAMOD_BYPASS;
- __raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
-
- /* Disable UART5->USB transparent mode or USB won't work */
- tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
- tmp &= ~LPC32XX_UART_U5_ROUTE_TO_USB;
- __raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
-}
diff --git a/arch/arm/mach-lpc32xx/suspend.S b/arch/arm/mach-lpc32xx/suspend.S
deleted file mode 100644
index a95c5e0e40384..0000000000000
--- a/arch/arm/mach-lpc32xx/suspend.S
+++ /dev/null
@@ -1,148 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * arch/arm/mach-lpc32xx/suspend.S
- *
- * Original authors: Dmitry Chigirev, Vitaly Wool <source@mvista.com>
- * Modified by Kevin Wells <kevin.wells@nxp.com>
- *
- * 2005 (c) MontaVista Software, Inc.
- */
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-#include "lpc32xx.h"
-
-/* Using named register defines makes the code easier to follow */
-#define WORK1_REG r0
-#define WORK2_REG r1
-#define SAVED_HCLK_DIV_REG r2
-#define SAVED_HCLK_PLL_REG r3
-#define SAVED_DRAM_CLKCTRL_REG r4
-#define SAVED_PWR_CTRL_REG r5
-#define CLKPWRBASE_REG r6
-#define EMCBASE_REG r7
-
-#define LPC32XX_EMC_STATUS_OFFS 0x04
-#define LPC32XX_EMC_STATUS_BUSY 0x1
-#define LPC32XX_EMC_STATUS_SELF_RFSH 0x4
-
-#define LPC32XX_CLKPWR_PWR_CTRL_OFFS 0x44
-#define LPC32XX_CLKPWR_HCLK_DIV_OFFS 0x40
-#define LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS 0x58
-
-#define CLKPWR_PCLK_DIV_MASK 0xFFFFFE7F
-
- .text
-
-ENTRY(lpc32xx_sys_suspend)
- @ Save a copy of the used registers in IRAM, r0 is corrupted
- adr r0, tmp_stack_end
- stmfd r0!, {r3 - r7, sp, lr}
-
- @ Load a few common register addresses
- adr WORK1_REG, reg_bases
- ldr CLKPWRBASE_REG, [WORK1_REG, #0]
- ldr EMCBASE_REG, [WORK1_REG, #4]
-
- ldr SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
- #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
- orr WORK1_REG, SAVED_PWR_CTRL_REG, #LPC32XX_CLKPWR_SDRAM_SELF_RFSH
-
- @ Wait for SDRAM busy status to go busy and then idle
- @ This guarantees a small windows where DRAM isn't busy
-1:
- ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
- and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
- cmp WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
- bne 1b @ Branch while idle
-2:
- ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
- and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
- cmp WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
- beq 2b @ Branch until idle
-
- @ Setup self-refresh with support for manual exit of
- @ self-refresh mode
- str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
- orr WORK2_REG, WORK1_REG, #LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH
- str WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
- str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
-
- @ Wait for self-refresh acknowledge, clocks to the DRAM device
- @ will automatically stop on start of self-refresh
-3:
- ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
- and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH
- cmp WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH
- bne 3b @ Branch until self-refresh mode starts
-
- @ Enter direct-run mode from run mode
- bic WORK1_REG, WORK1_REG, #LPC32XX_CLKPWR_SELECT_RUN_MODE
- str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
-
- @ Safe disable of DRAM clock in EMC block, prevents DDR sync
- @ issues on restart
- ldr SAVED_HCLK_DIV_REG, [CLKPWRBASE_REG,\
- #LPC32XX_CLKPWR_HCLK_DIV_OFFS]
- and WORK2_REG, SAVED_HCLK_DIV_REG, #CLKPWR_PCLK_DIV_MASK
- str WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLK_DIV_OFFS]
-
- @ Save HCLK PLL state and disable HCLK PLL
- ldr SAVED_HCLK_PLL_REG, [CLKPWRBASE_REG,\
- #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
- bic WORK2_REG, SAVED_HCLK_PLL_REG, #LPC32XX_CLKPWR_HCLKPLL_POWER_UP
- str WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
-
- @ Enter stop mode until an enabled event occurs
- orr WORK1_REG, WORK1_REG, #LPC32XX_CLKPWR_STOP_MODE_CTRL
- str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
- .rept 9
- nop
- .endr
-
- @ Clear stop status
- bic WORK1_REG, WORK1_REG, #LPC32XX_CLKPWR_STOP_MODE_CTRL
-
- @ Restore original HCLK PLL value and wait for PLL lock
- str SAVED_HCLK_PLL_REG, [CLKPWRBASE_REG,\
- #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
-4:
- ldr WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
- and WORK2_REG, WORK2_REG, #LPC32XX_CLKPWR_HCLKPLL_PLL_STS
- bne 4b
-
- @ Re-enter run mode with self-refresh flag cleared, but no DRAM
- @ update yet. DRAM is still in self-refresh
- str SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
- #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
-
- @ Restore original DRAM clock mode to restore DRAM clocks
- str SAVED_HCLK_DIV_REG, [CLKPWRBASE_REG,\
- #LPC32XX_CLKPWR_HCLK_DIV_OFFS]
-
- @ Clear self-refresh mode
- orr WORK1_REG, SAVED_PWR_CTRL_REG,\
- #LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH
- str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
- str SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
- #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
-
- @ Wait for EMC to clear self-refresh mode
-5:
- ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
- and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH
- bne 5b @ Branch until self-refresh has exited
-
- @ restore regs and return
- adr r0, tmp_stack
- ldmfd r0!, {r3 - r7, sp, pc}
-
-reg_bases:
- .long IO_ADDRESS(LPC32XX_CLK_PM_BASE)
- .long IO_ADDRESS(LPC32XX_EMC_BASE)
-
-tmp_stack:
- .long 0, 0, 0, 0, 0, 0, 0
-tmp_stack_end:
-
-ENTRY(lpc32xx_sys_suspend_sz)
- .word . - lpc32xx_sys_suspend
--
2.43.0
^ permalink raw reply related
* Re: [PATCH 5/5] dt-bindings: dma: sun50i-a64-dma: Update device tree bindings documentation for A733
From: Frank Li @ 2026-06-19 15:55 UTC (permalink / raw)
To: Yuanshen Cao
Cc: Vinod Koul, Frank Li, Chen-Yu Tsai, Jernej Skrabec,
Samuel Holland, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Maxime Ripard, dmaengine, linux-arm-kernel, linux-sunxi,
linux-kernel, devicetree
In-Reply-To: <20260619-sun60i-a733-dma-v1-5-da4b649fc72a@gmail.com>
On Fri, Jun 19, 2026 at 04:53:34AM +0000, Yuanshen Cao wrote:
>
> To complete the support for the A733 DMA controller, added
> `allwinner,sun60i-a733-dma` to the list of compatible strings for
> `allwinner,sun50i-a64-dma` dt-binding documentations..
>
> Signed-off-by: Yuanshen Cao <alex.caoys@gmail.com>
> ---
Sorry, this patch should be moved to where before your driver, which use it
Frank
> Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml b/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml
> index c3e14eb6cfff..1cc3304b7414 100644
> --- a/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml
> +++ b/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml
> @@ -25,6 +25,7 @@ properties:
> - allwinner,sun50i-a64-dma
> - allwinner,sun50i-a100-dma
> - allwinner,sun50i-h6-dma
> + - allwinner,sun60i-a733-dma
> - items:
> - const: allwinner,sun8i-r40-dma
> - const: allwinner,sun50i-a64-dma
> @@ -70,6 +71,7 @@ if:
> - allwinner,sun20i-d1-dma
> - allwinner,sun50i-a100-dma
> - allwinner,sun50i-h6-dma
> + - allwinner,sun60i-a733-dma
>
> then:
> properties:
>
> --
> 2.54.0
>
^ permalink raw reply
* Re: [PATCH v2] arm64: tlbflush: Don't broadcast if mm was only active on local cpu
From: Ryan Roberts @ 2026-06-19 15:54 UTC (permalink / raw)
To: Will Deacon
Cc: Linu Cherian, Catalin Marinas, Kevin Brodsky, Anshuman Khandual,
Yang Shi, Mark Rutland, Huang Ying, linux-arm-kernel,
linux-kernel, shameerali.kolothum.thodi
In-Reply-To: <ajVhiCXYmbDq-qTi@willie-the-truck>
On 19/06/2026 16:34, Will Deacon wrote:
> On Mon, Jun 15, 2026 at 04:41:04PM +0100, Ryan Roberts wrote:
>> On 15/06/2026 15:43, Will Deacon wrote:
>>> On Mon, Jun 15, 2026 at 12:21:19PM +0100, Ryan Roberts wrote:
>>>>>> + self = smp_processor_id();
>>>>>> +
>>>>>> + /*
>>>>>> + * The load of mm->context.active_cpu must not be reordered before the
>>>>>> + * store to the pgtable that necessitated this flush. This ensures that
>>>>>> + * if the value read is our cpu id, then no other cpu can have seen the
>>>>>> + * old pgtable value and therefore does not need this old value to be
>>>>>> + * flushed from its tlb. But we don't want to upgrade the dsb(ishst),
>>>>>> + * needed to make the pgtable updates visible to the walker, to a
>>>>>> + * dsb(ish) by default. So speculatively load without a barrier and if
>>>>>> + * it indicates our cpu id, then upgrade the barrier and re-load.
>>>>>> + */
>>>>>> + active = READ_ONCE(mm->context.active_cpu);
>>>>>> + if (active == self) {
>>>>>> + dsb(ish);
>>>>>> + active = READ_ONCE(mm->context.active_cpu);
>>>>>> + } else {
>>>>>> + dsb(ishst);
>>>>>> + }
>>>>>
>>>>> Why can't you just do:
>>>>>
>>>>> dsb(ishst);
>>>>> active = READ_ONCE(mm->context.active_cpu);
>>>>>
>>>>> ?
>>>>
>>>> Prior to this optimization, we always issued a dsb(ishst) here. Catalin
>>>> suggested the same simplification against the RFC. I believe Linu tried it but
>>>> saw regressions; Hopefully Linu can provide the details.
>>>
>>> I don't follow...
>>>
>>> The old code always did dsb(ishst). The proposed code here does either
>>> dsb(ish) or dsb(ishst). How can that possibly be faster?
>>
>> Ugh, sorry - I read your suggestion as unconditionally issuing a dsb(ish).
>>
>> Ignore my previous answer, and now I'll demonstrate my total lack of
>> understanding of barriers instead...
>>
>> As the comment says, "The load of mm->context.active_cpu must not be reordered
>> before the store to the pgtable that necessitated this flush". I thought that a
>> dsb(ishst) would only provide ordering between stores. Don't we need the
>> dsb(ish) to prevent the load from being reordered before the store?
>
> dsb(ishst) orders prior stores -> everything later. That's why it works
> today for ordered a PTE write before a TLBI (which isn't a store).
Ahh, that simplifies things then!
>
> Will
^ permalink raw reply
* Re: [PATCH 5/5] dt-bindings: dma: sun50i-a64-dma: Update device tree bindings documentation for A733
From: Frank Li @ 2026-06-19 15:53 UTC (permalink / raw)
To: Yuanshen Cao
Cc: Vinod Koul, Frank Li, Chen-Yu Tsai, Jernej Skrabec,
Samuel Holland, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Maxime Ripard, dmaengine, linux-arm-kernel, linux-sunxi,
linux-kernel, devicetree
In-Reply-To: <20260619-sun60i-a733-dma-v1-5-da4b649fc72a@gmail.com>
On Fri, Jun 19, 2026 at 04:53:34AM +0000, Yuanshen Cao wrote:
Subject needn't talk about binding twice
dma: sun50i-a64-dma: Add a733 support
>
> To complete the support for the A733 DMA controller, added
> `allwinner,sun60i-a733-dma` to the list of compatible strings for
> `allwinner,sun50i-a64-dma` dt-binding documentations..
Add allwinner,sun60i-a733-dma compatible string. And list some differene
here to show why need it.
Frank
>
> Signed-off-by: Yuanshen Cao <alex.caoys@gmail.com>
> ---
> Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml b/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml
> index c3e14eb6cfff..1cc3304b7414 100644
> --- a/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml
> +++ b/Documentation/devicetree/bindings/dma/allwinner,sun50i-a64-dma.yaml
> @@ -25,6 +25,7 @@ properties:
> - allwinner,sun50i-a64-dma
> - allwinner,sun50i-a100-dma
> - allwinner,sun50i-h6-dma
> + - allwinner,sun60i-a733-dma
> - items:
> - const: allwinner,sun8i-r40-dma
> - const: allwinner,sun50i-a64-dma
> @@ -70,6 +71,7 @@ if:
> - allwinner,sun20i-d1-dma
> - allwinner,sun50i-a100-dma
> - allwinner,sun50i-h6-dma
> + - allwinner,sun60i-a733-dma
>
> then:
> properties:
>
> --
> 2.54.0
>
^ permalink raw reply
* Re: [PATCH v22 00/13] Implement PSCI reboot mode driver for PSCI resets
From: Lorenzo Pieralisi @ 2026-06-19 15:46 UTC (permalink / raw)
To: Shivendra Pratap
Cc: Arnd Bergmann, linux-pm, linux-kernel, linux-arm-msm,
linux-arm-kernel, devicetree, Florian Fainelli,
Krzysztof Kozlowski, Dmitry Baryshkov, Mukesh Ojha, Andre Draszik,
Greg Kroah-Hartman, Kathiravan Thirumoorthy, Srinivas Kandagatla,
Sebastian Reichel, Bartosz Golaszewski, Song Xue,
Sebastian Reichel, Mark Rutland, Rafael J. Wysocki,
Daniel Lezcano, Christian Loehle, Ulf Hansson, Lee Jones,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson,
Konrad Dybcio, Souvik Chakravarty, Andy Yan, Matthias Brugger,
John Stultz, Moritz Fischer, Bartosz Golaszewski, Sudeep Holla
In-Reply-To: <f0336ce8-e5e0-4629-ac51-f3c42bf3d9a9@oss.qualcomm.com>
On Wed, Jun 17, 2026 at 10:30:21PM +0530, Shivendra Pratap wrote:
>
>
> On 29-05-2026 19:00, Shivendra Pratap wrote:
> >
> >
> > On 14-05-2026 19:55, Shivendra Pratap wrote:
> > > Userspace should be able to initiate device reboots using the various
> > > PSCI SYSTEM_RESET and SYSTEM_RESET2 types defined by PSCI spec. This
> > > patch series introduces psci-reboot-mode driver that will induce
> > > command-based resets to psci driver for executing the device reset.
> > >
> > > The PSCI system reset calls takes two arguments: reset_type and cookie.
> > > It defines predefined reset types, such as warm and cold reset, and
> > > vendor-specific reset types which are SoC vendor specific. To support
> > > these requirements, the reboot-mode framework is enhanced in two key
> > > ways:
> >
> > Hi Lorenzo,
> >
> > Can you please review the if its aligning towards the suggestion in v20?
> >
>
> Hi Lorenzo,
>
> Was planning to address the mfd, and other comments, for re-post. Any
> feedbacks, that we should take care in next post?
I glanced over the code - it is better than it was but I could not find
time for a proper review. Go ahead and repost we will take it from there.
Apologies for the huge delay in reviewing it.
Thanks,
Lorenzo
^ permalink raw reply
* Re: [PATCH 3/5] dmaengine: sun6i-dma: Add num_channels_per_reg for flexible interrupt mapping
From: Frank Li @ 2026-06-19 15:46 UTC (permalink / raw)
To: Yuanshen Cao
Cc: Vinod Koul, Frank Li, Chen-Yu Tsai, Jernej Skrabec,
Samuel Holland, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Maxime Ripard, dmaengine, linux-arm-kernel, linux-sunxi,
linux-kernel, devicetree
In-Reply-To: <20260619-sun60i-a733-dma-v1-3-da4b649fc72a@gmail.com>
On Fri, Jun 19, 2026 at 04:53:32AM +0000, Yuanshen Cao wrote:
>
> The previous implementation of `sun6i-dma` had some implicit assumptions
> about the number of channels per interrupt register. Specifically,
> functions like `sun6i_kill_tasklet` were hardcoded to only disable
> interrupts for IRQ 0 and 1. `DMA_MAX_CHANNELS` is also not in used in
> the past, and the old SoCs never has more than 16 channels.
>
> The A733 has a different interrupt structure where the number of
> channels per register may differ. This patch introduces
> `num_channels_per_reg` to the `sun6i_dma_config`, similar to BSP, to
> make the interrupt handling logic hardware-agnostic. It also sets
> `DMA_MAX_CHANNELS` to 16 to align with the new BSP code and ensure loops
> over interrupts are correctly bounded.
>
> Changes:
> - Change `DMA_MAX_CHANNELS` definition to 16.
> - Added `num_channels_per_reg` to `struct sun6i_dma_config`.
> - Replaced hardcoded IRQ register calculations with values from
> `sdev->cfg->num_channels_per_reg`.
> - Updated `sun6i_kill_tasklet` to loop through all possible interrupt
> registers based on `DMA_MAX_CHANNELS` and the configuration.
>
> Signed-off-by: Yuanshen Cao <alex.caoys@gmail.com>
> ---
> drivers/dma/sun6i-dma.c | 25 ++++++++++++++++++-------
> 1 file changed, 18 insertions(+), 7 deletions(-)
>
...
> @@ -1171,6 +1174,7 @@ static struct sun6i_dma_config sun6i_a31_dma_cfg = {
> .dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
> BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
> BIT(DMA_SLAVE_BUSWIDTH_4_BYTES),
> + .num_channels_per_reg = DMA_IRQ_CHAN_NR,
if previous patch have MACRO, you can put it to there
Frank
^ permalink raw reply
* [PATCH 10/11] clk: nxp: lpc: Remove NOMMU platform support
From: Frank.Li @ 2026-06-19 15:41 UTC (permalink / raw)
To: Arnd Bergmann, Sascha Hauer, Pengutronix Kernel Team,
Stefan Agner, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Russell King, Abel Vesa, Peng Fan,
Michael Turquette, Stephen Boyd, Brian Masney, Dong Aisheng,
Jacky Bai, NXP S32 Linux Team, Linus Walleij, Vladimir Zapolskiy,
Piotr Wojtaszczyk, Kees Cook, Gustavo A. R. Silva
Cc: linux-arm-kernel, imx, devicetree, linux-kernel, linux-clk,
linux-gpio, linux-hardening, Frank Li
In-Reply-To: <20260619-dts_cleanup_arm_mcore-v1-0-0101795a2662@nxp.com>
From: Frank Li <Frank.Li@nxp.com>
Commercial users and hardware vendors migrated to Zephyr or other RTOS
solutions years ago, leaving the NOMMU platform support effectively
unused and unmaintained.
Remove the obsolete support to reduce maintenance burden and simplify the
NXP/Freescale platform code.
The clock driver is highly SoC-specific and provides little opportunity
for reuse on future hardware.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
drivers/clk/Kconfig | 7 -
drivers/clk/Makefile | 1 -
drivers/clk/nxp/Makefile | 5 -
drivers/clk/nxp/clk-lpc18xx-ccu.c | 301 -------
drivers/clk/nxp/clk-lpc18xx-cgu.c | 668 ---------------
drivers/clk/nxp/clk-lpc18xx-creg.c | 225 -----
drivers/clk/nxp/clk-lpc32xx.c | 1591 ------------------------------------
7 files changed, 2798 deletions(-)
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 1717ce75a907e..5e98cd8425851 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -367,13 +367,6 @@ config COMMON_CLK_LOONGSON2
peripherals within the SoC.
Say Y here to support Loongson-2 SoC clock driver.
-config COMMON_CLK_NXP
- def_bool COMMON_CLK && (ARCH_LPC18XX || ARCH_LPC32XX)
- select REGMAP_MMIO if ARCH_LPC32XX
- select MFD_SYSCON if ARCH_LPC18XX
- help
- Support for clock providers on NXP platforms.
-
config COMMON_CLK_PALMAS
tristate "Clock driver for TI Palmas devices"
depends on MFD_PALMAS
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index cc108a75a9008..23b14a934635d 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -136,7 +136,6 @@ obj-y += mstar/
obj-y += mvebu/
obj-$(CONFIG_ARCH_MXS) += mxs/
obj-$(CONFIG_ARCH_MA35) += nuvoton/
-obj-$(CONFIG_COMMON_CLK_NXP) += nxp/
obj-$(CONFIG_COMMON_CLK_PISTACHIO) += pistachio/
obj-$(CONFIG_COMMON_CLK_PXA) += pxa/
obj-$(CONFIG_COMMON_CLK_QCOM) += qcom/
diff --git a/drivers/clk/nxp/Makefile b/drivers/clk/nxp/Makefile
deleted file mode 100644
index 2cf6317d28531..0000000000000
--- a/drivers/clk/nxp/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-obj-$(CONFIG_ARCH_LPC18XX) += clk-lpc18xx-cgu.o
-obj-$(CONFIG_ARCH_LPC18XX) += clk-lpc18xx-ccu.o
-obj-$(CONFIG_ARCH_LPC18XX) += clk-lpc18xx-creg.o
-obj-$(CONFIG_ARCH_LPC32XX) += clk-lpc32xx.o
diff --git a/drivers/clk/nxp/clk-lpc18xx-ccu.c b/drivers/clk/nxp/clk-lpc18xx-ccu.c
deleted file mode 100644
index 3793e701835ff..0000000000000
--- a/drivers/clk/nxp/clk-lpc18xx-ccu.c
+++ /dev/null
@@ -1,301 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Clk driver for NXP LPC18xx/LPC43xx Clock Control Unit (CCU)
- *
- * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
- */
-
-#include <linux/clk.h>
-#include <linux/clk-provider.h>
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/slab.h>
-#include <linux/string.h>
-
-#include <dt-bindings/clock/lpc18xx-ccu.h>
-
-/* Bit defines for CCU branch configuration register */
-#define LPC18XX_CCU_RUN BIT(0)
-#define LPC18XX_CCU_AUTO BIT(1)
-#define LPC18XX_CCU_DIV BIT(5)
-#define LPC18XX_CCU_DIVSTAT BIT(27)
-
-/* CCU branch feature bits */
-#define CCU_BRANCH_IS_BUS BIT(0)
-#define CCU_BRANCH_HAVE_DIV2 BIT(1)
-
-struct lpc18xx_branch_clk_data {
- int num;
- const char *name[] __counted_by(num);
-};
-
-struct lpc18xx_clk_branch {
- const char *base_name;
- const char *name;
- u16 offset;
- u16 flags;
- struct clk *clk;
- struct clk_gate gate;
-};
-
-static struct lpc18xx_clk_branch clk_branches[] = {
- {"base_apb3_clk", "apb3_bus", CLK_APB3_BUS, CCU_BRANCH_IS_BUS},
- {"base_apb3_clk", "apb3_i2c1", CLK_APB3_I2C1, 0},
- {"base_apb3_clk", "apb3_dac", CLK_APB3_DAC, 0},
- {"base_apb3_clk", "apb3_adc0", CLK_APB3_ADC0, 0},
- {"base_apb3_clk", "apb3_adc1", CLK_APB3_ADC1, 0},
- {"base_apb3_clk", "apb3_can0", CLK_APB3_CAN0, 0},
-
- {"base_apb1_clk", "apb1_bus", CLK_APB1_BUS, CCU_BRANCH_IS_BUS},
- {"base_apb1_clk", "apb1_mc_pwm", CLK_APB1_MOTOCON_PWM, 0},
- {"base_apb1_clk", "apb1_i2c0", CLK_APB1_I2C0, 0},
- {"base_apb1_clk", "apb1_i2s", CLK_APB1_I2S, 0},
- {"base_apb1_clk", "apb1_can1", CLK_APB1_CAN1, 0},
-
- {"base_spifi_clk", "spifi", CLK_SPIFI, 0},
-
- {"base_cpu_clk", "cpu_bus", CLK_CPU_BUS, CCU_BRANCH_IS_BUS},
- {"base_cpu_clk", "cpu_spifi", CLK_CPU_SPIFI, 0},
- {"base_cpu_clk", "cpu_gpio", CLK_CPU_GPIO, 0},
- {"base_cpu_clk", "cpu_lcd", CLK_CPU_LCD, 0},
- {"base_cpu_clk", "cpu_ethernet", CLK_CPU_ETHERNET, 0},
- {"base_cpu_clk", "cpu_usb0", CLK_CPU_USB0, 0},
- {"base_cpu_clk", "cpu_emc", CLK_CPU_EMC, 0},
- {"base_cpu_clk", "cpu_sdio", CLK_CPU_SDIO, 0},
- {"base_cpu_clk", "cpu_dma", CLK_CPU_DMA, 0},
- {"base_cpu_clk", "cpu_core", CLK_CPU_CORE, 0},
- {"base_cpu_clk", "cpu_sct", CLK_CPU_SCT, 0},
- {"base_cpu_clk", "cpu_usb1", CLK_CPU_USB1, 0},
- {"base_cpu_clk", "cpu_emcdiv", CLK_CPU_EMCDIV, CCU_BRANCH_HAVE_DIV2},
- {"base_cpu_clk", "cpu_flasha", CLK_CPU_FLASHA, CCU_BRANCH_HAVE_DIV2},
- {"base_cpu_clk", "cpu_flashb", CLK_CPU_FLASHB, CCU_BRANCH_HAVE_DIV2},
- {"base_cpu_clk", "cpu_m0app", CLK_CPU_M0APP, CCU_BRANCH_HAVE_DIV2},
- {"base_cpu_clk", "cpu_adchs", CLK_CPU_ADCHS, CCU_BRANCH_HAVE_DIV2},
- {"base_cpu_clk", "cpu_eeprom", CLK_CPU_EEPROM, CCU_BRANCH_HAVE_DIV2},
- {"base_cpu_clk", "cpu_wwdt", CLK_CPU_WWDT, 0},
- {"base_cpu_clk", "cpu_uart0", CLK_CPU_UART0, 0},
- {"base_cpu_clk", "cpu_uart1", CLK_CPU_UART1, 0},
- {"base_cpu_clk", "cpu_ssp0", CLK_CPU_SSP0, 0},
- {"base_cpu_clk", "cpu_timer0", CLK_CPU_TIMER0, 0},
- {"base_cpu_clk", "cpu_timer1", CLK_CPU_TIMER1, 0},
- {"base_cpu_clk", "cpu_scu", CLK_CPU_SCU, 0},
- {"base_cpu_clk", "cpu_creg", CLK_CPU_CREG, 0},
- {"base_cpu_clk", "cpu_ritimer", CLK_CPU_RITIMER, 0},
- {"base_cpu_clk", "cpu_uart2", CLK_CPU_UART2, 0},
- {"base_cpu_clk", "cpu_uart3", CLK_CPU_UART3, 0},
- {"base_cpu_clk", "cpu_timer2", CLK_CPU_TIMER2, 0},
- {"base_cpu_clk", "cpu_timer3", CLK_CPU_TIMER3, 0},
- {"base_cpu_clk", "cpu_ssp1", CLK_CPU_SSP1, 0},
- {"base_cpu_clk", "cpu_qei", CLK_CPU_QEI, 0},
-
- {"base_periph_clk", "periph_bus", CLK_PERIPH_BUS, CCU_BRANCH_IS_BUS},
- {"base_periph_clk", "periph_core", CLK_PERIPH_CORE, 0},
- {"base_periph_clk", "periph_sgpio", CLK_PERIPH_SGPIO, 0},
-
- {"base_usb0_clk", "usb0", CLK_USB0, 0},
- {"base_usb1_clk", "usb1", CLK_USB1, 0},
- {"base_spi_clk", "spi", CLK_SPI, 0},
- {"base_adchs_clk", "adchs", CLK_ADCHS, 0},
-
- {"base_audio_clk", "audio", CLK_AUDIO, 0},
- {"base_uart3_clk", "apb2_uart3", CLK_APB2_UART3, 0},
- {"base_uart2_clk", "apb2_uart2", CLK_APB2_UART2, 0},
- {"base_uart1_clk", "apb0_uart1", CLK_APB0_UART1, 0},
- {"base_uart0_clk", "apb0_uart0", CLK_APB0_UART0, 0},
- {"base_ssp1_clk", "apb2_ssp1", CLK_APB2_SSP1, 0},
- {"base_ssp0_clk", "apb0_ssp0", CLK_APB0_SSP0, 0},
- {"base_sdio_clk", "sdio", CLK_SDIO, 0},
-};
-
-static struct clk *lpc18xx_ccu_branch_clk_get(struct of_phandle_args *clkspec,
- void *data)
-{
- struct lpc18xx_branch_clk_data *clk_data = data;
- unsigned int offset = clkspec->args[0];
- int i, j;
-
- for (i = 0; i < ARRAY_SIZE(clk_branches); i++) {
- if (clk_branches[i].offset != offset)
- continue;
-
- for (j = 0; j < clk_data->num; j++) {
- if (!strcmp(clk_branches[i].base_name, clk_data->name[j]))
- return clk_branches[i].clk;
- }
- }
-
- pr_err("%s: invalid clock offset %d\n", __func__, offset);
-
- return ERR_PTR(-EINVAL);
-}
-
-static int lpc18xx_ccu_gate_endisable(struct clk_hw *hw, bool enable)
-{
- struct clk_gate *gate = to_clk_gate(hw);
- u32 val;
-
- /*
- * Divider field is write only, so divider stat field must
- * be read so divider field can be set accordingly.
- */
- val = readl(gate->reg);
- if (val & LPC18XX_CCU_DIVSTAT)
- val |= LPC18XX_CCU_DIV;
-
- if (enable) {
- val |= LPC18XX_CCU_RUN;
- } else {
- /*
- * To safely disable a branch clock a sequence of two separate
- * writes must be used. First write should set the AUTO bit
- * and the next write should clear the RUN bit.
- */
- val |= LPC18XX_CCU_AUTO;
- writel(val, gate->reg);
-
- val &= ~LPC18XX_CCU_RUN;
- }
-
- writel(val, gate->reg);
-
- return 0;
-}
-
-static int lpc18xx_ccu_gate_enable(struct clk_hw *hw)
-{
- return lpc18xx_ccu_gate_endisable(hw, true);
-}
-
-static void lpc18xx_ccu_gate_disable(struct clk_hw *hw)
-{
- lpc18xx_ccu_gate_endisable(hw, false);
-}
-
-static int lpc18xx_ccu_gate_is_enabled(struct clk_hw *hw)
-{
- const struct clk_hw *parent;
-
- /*
- * The branch clock registers are only accessible
- * if the base (parent) clock is enabled. Register
- * access with a disabled base clock will hang the
- * system.
- */
- parent = clk_hw_get_parent(hw);
- if (!parent)
- return 0;
-
- if (!clk_hw_is_enabled(parent))
- return 0;
-
- return clk_gate_ops.is_enabled(hw);
-}
-
-static const struct clk_ops lpc18xx_ccu_gate_ops = {
- .enable = lpc18xx_ccu_gate_enable,
- .disable = lpc18xx_ccu_gate_disable,
- .is_enabled = lpc18xx_ccu_gate_is_enabled,
-};
-
-static void lpc18xx_ccu_register_branch_gate_div(struct lpc18xx_clk_branch *branch,
- void __iomem *reg_base,
- const char *parent)
-{
- const struct clk_ops *div_ops = NULL;
- struct clk_divider *div = NULL;
- struct clk_hw *div_hw = NULL;
-
- if (branch->flags & CCU_BRANCH_HAVE_DIV2) {
- div = kzalloc_obj(*div);
- if (!div)
- return;
-
- div->reg = branch->offset + reg_base;
- div->flags = CLK_DIVIDER_READ_ONLY;
- div->shift = 27;
- div->width = 1;
-
- div_hw = &div->hw;
- div_ops = &clk_divider_ro_ops;
- }
-
- branch->gate.reg = branch->offset + reg_base;
- branch->gate.bit_idx = 0;
-
- branch->clk = clk_register_composite(NULL, branch->name, &parent, 1,
- NULL, NULL,
- div_hw, div_ops,
- &branch->gate.hw, &lpc18xx_ccu_gate_ops, 0);
- if (IS_ERR(branch->clk)) {
- kfree(div);
- pr_warn("%s: failed to register %s\n", __func__, branch->name);
- return;
- }
-
- /* Grab essential branch clocks for CPU and SDRAM */
- switch (branch->offset) {
- case CLK_CPU_EMC:
- case CLK_CPU_CORE:
- case CLK_CPU_CREG:
- case CLK_CPU_EMCDIV:
- clk_prepare_enable(branch->clk);
- }
-}
-
-static void lpc18xx_ccu_register_branch_clks(void __iomem *reg_base,
- const char *base_name)
-{
- const char *parent = base_name;
- int i;
-
- for (i = 0; i < ARRAY_SIZE(clk_branches); i++) {
- if (strcmp(clk_branches[i].base_name, base_name))
- continue;
-
- lpc18xx_ccu_register_branch_gate_div(&clk_branches[i], reg_base,
- parent);
-
- if (clk_branches[i].flags & CCU_BRANCH_IS_BUS)
- parent = clk_branches[i].name;
- }
-}
-
-static void __init lpc18xx_ccu_init(struct device_node *np)
-{
- struct lpc18xx_branch_clk_data *clk_data;
- void __iomem *reg_base;
- size_t size;
- int i, ret;
-
- reg_base = of_iomap(np, 0);
- if (!reg_base) {
- pr_warn("%s: failed to map address range\n", __func__);
- return;
- }
-
- size = of_property_count_strings(np, "clock-names");
- clk_data = kzalloc_flex(*clk_data, name, size);
- if (!clk_data) {
- iounmap(reg_base);
- return;
- }
-
- clk_data->num = size;
-
- for (i = 0; i < clk_data->num; i++) {
- ret = of_property_read_string_index(np, "clock-names", i,
- &clk_data->name[i]);
- if (ret) {
- pr_warn("%s: failed to get clock name at idx %d\n",
- __func__, i);
- continue;
- }
-
- lpc18xx_ccu_register_branch_clks(reg_base, clk_data->name[i]);
- }
-
- of_clk_add_provider(np, lpc18xx_ccu_branch_clk_get, clk_data);
-}
-CLK_OF_DECLARE(lpc18xx_ccu, "nxp,lpc1850-ccu", lpc18xx_ccu_init);
diff --git a/drivers/clk/nxp/clk-lpc18xx-cgu.c b/drivers/clk/nxp/clk-lpc18xx-cgu.c
deleted file mode 100644
index b9e204d63a972..0000000000000
--- a/drivers/clk/nxp/clk-lpc18xx-cgu.c
+++ /dev/null
@@ -1,668 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Clk driver for NXP LPC18xx/LPC43xx Clock Generation Unit (CGU)
- *
- * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-
-#include <dt-bindings/clock/lpc18xx-cgu.h>
-
-/* Clock Generation Unit (CGU) registers */
-#define LPC18XX_CGU_XTAL_OSC_CTRL 0x018
-#define LPC18XX_CGU_PLL0USB_STAT 0x01c
-#define LPC18XX_CGU_PLL0USB_CTRL 0x020
-#define LPC18XX_CGU_PLL0USB_MDIV 0x024
-#define LPC18XX_CGU_PLL0USB_NP_DIV 0x028
-#define LPC18XX_CGU_PLL0AUDIO_STAT 0x02c
-#define LPC18XX_CGU_PLL0AUDIO_CTRL 0x030
-#define LPC18XX_CGU_PLL0AUDIO_MDIV 0x034
-#define LPC18XX_CGU_PLL0AUDIO_NP_DIV 0x038
-#define LPC18XX_CGU_PLL0AUDIO_FRAC 0x03c
-#define LPC18XX_CGU_PLL1_STAT 0x040
-#define LPC18XX_CGU_PLL1_CTRL 0x044
-#define LPC18XX_PLL1_CTRL_FBSEL BIT(6)
-#define LPC18XX_PLL1_CTRL_DIRECT BIT(7)
-#define LPC18XX_CGU_IDIV_CTRL(n) (0x048 + (n) * sizeof(u32))
-#define LPC18XX_CGU_BASE_CLK(id) (0x05c + (id) * sizeof(u32))
-#define LPC18XX_CGU_PLL_CTRL_OFFSET 0x4
-
-/* PLL0 bits common to both audio and USB PLL */
-#define LPC18XX_PLL0_STAT_LOCK BIT(0)
-#define LPC18XX_PLL0_CTRL_PD BIT(0)
-#define LPC18XX_PLL0_CTRL_BYPASS BIT(1)
-#define LPC18XX_PLL0_CTRL_DIRECTI BIT(2)
-#define LPC18XX_PLL0_CTRL_DIRECTO BIT(3)
-#define LPC18XX_PLL0_CTRL_CLKEN BIT(4)
-#define LPC18XX_PLL0_MDIV_MDEC_MASK 0x1ffff
-#define LPC18XX_PLL0_MDIV_SELP_SHIFT 17
-#define LPC18XX_PLL0_MDIV_SELI_SHIFT 22
-#define LPC18XX_PLL0_MSEL_MAX BIT(15)
-
-/* Register value that gives PLL0 post/pre dividers equal to 1 */
-#define LPC18XX_PLL0_NP_DIVS_1 0x00302062
-
-enum {
- CLK_SRC_OSC32,
- CLK_SRC_IRC,
- CLK_SRC_ENET_RX_CLK,
- CLK_SRC_ENET_TX_CLK,
- CLK_SRC_GP_CLKIN,
- CLK_SRC_RESERVED1,
- CLK_SRC_OSC,
- CLK_SRC_PLL0USB,
- CLK_SRC_PLL0AUDIO,
- CLK_SRC_PLL1,
- CLK_SRC_RESERVED2,
- CLK_SRC_RESERVED3,
- CLK_SRC_IDIVA,
- CLK_SRC_IDIVB,
- CLK_SRC_IDIVC,
- CLK_SRC_IDIVD,
- CLK_SRC_IDIVE,
- CLK_SRC_MAX
-};
-
-static const char *clk_src_names[CLK_SRC_MAX] = {
- [CLK_SRC_OSC32] = "osc32",
- [CLK_SRC_IRC] = "irc",
- [CLK_SRC_ENET_RX_CLK] = "enet_rx_clk",
- [CLK_SRC_ENET_TX_CLK] = "enet_tx_clk",
- [CLK_SRC_GP_CLKIN] = "gp_clkin",
- [CLK_SRC_OSC] = "osc",
- [CLK_SRC_PLL0USB] = "pll0usb",
- [CLK_SRC_PLL0AUDIO] = "pll0audio",
- [CLK_SRC_PLL1] = "pll1",
- [CLK_SRC_IDIVA] = "idiva",
- [CLK_SRC_IDIVB] = "idivb",
- [CLK_SRC_IDIVC] = "idivc",
- [CLK_SRC_IDIVD] = "idivd",
- [CLK_SRC_IDIVE] = "idive",
-};
-
-static const char *clk_base_names[BASE_CLK_MAX] = {
- [BASE_SAFE_CLK] = "base_safe_clk",
- [BASE_USB0_CLK] = "base_usb0_clk",
- [BASE_PERIPH_CLK] = "base_periph_clk",
- [BASE_USB1_CLK] = "base_usb1_clk",
- [BASE_CPU_CLK] = "base_cpu_clk",
- [BASE_SPIFI_CLK] = "base_spifi_clk",
- [BASE_SPI_CLK] = "base_spi_clk",
- [BASE_PHY_RX_CLK] = "base_phy_rx_clk",
- [BASE_PHY_TX_CLK] = "base_phy_tx_clk",
- [BASE_APB1_CLK] = "base_apb1_clk",
- [BASE_APB3_CLK] = "base_apb3_clk",
- [BASE_LCD_CLK] = "base_lcd_clk",
- [BASE_ADCHS_CLK] = "base_adchs_clk",
- [BASE_SDIO_CLK] = "base_sdio_clk",
- [BASE_SSP0_CLK] = "base_ssp0_clk",
- [BASE_SSP1_CLK] = "base_ssp1_clk",
- [BASE_UART0_CLK] = "base_uart0_clk",
- [BASE_UART1_CLK] = "base_uart1_clk",
- [BASE_UART2_CLK] = "base_uart2_clk",
- [BASE_UART3_CLK] = "base_uart3_clk",
- [BASE_OUT_CLK] = "base_out_clk",
- [BASE_AUDIO_CLK] = "base_audio_clk",
- [BASE_CGU_OUT0_CLK] = "base_cgu_out0_clk",
- [BASE_CGU_OUT1_CLK] = "base_cgu_out1_clk",
-};
-
-static u32 lpc18xx_cgu_pll0_src_ids[] = {
- CLK_SRC_OSC32, CLK_SRC_IRC, CLK_SRC_ENET_RX_CLK,
- CLK_SRC_ENET_TX_CLK, CLK_SRC_GP_CLKIN, CLK_SRC_OSC,
- CLK_SRC_PLL1, CLK_SRC_IDIVA, CLK_SRC_IDIVB, CLK_SRC_IDIVC,
- CLK_SRC_IDIVD, CLK_SRC_IDIVE,
-};
-
-static u32 lpc18xx_cgu_pll1_src_ids[] = {
- CLK_SRC_OSC32, CLK_SRC_IRC, CLK_SRC_ENET_RX_CLK,
- CLK_SRC_ENET_TX_CLK, CLK_SRC_GP_CLKIN, CLK_SRC_OSC,
- CLK_SRC_PLL0USB, CLK_SRC_PLL0AUDIO, CLK_SRC_IDIVA,
- CLK_SRC_IDIVB, CLK_SRC_IDIVC, CLK_SRC_IDIVD, CLK_SRC_IDIVE,
-};
-
-static u32 lpc18xx_cgu_idiva_src_ids[] = {
- CLK_SRC_OSC32, CLK_SRC_IRC, CLK_SRC_ENET_RX_CLK,
- CLK_SRC_ENET_TX_CLK, CLK_SRC_GP_CLKIN, CLK_SRC_OSC,
- CLK_SRC_PLL0USB, CLK_SRC_PLL0AUDIO, CLK_SRC_PLL1
-};
-
-static u32 lpc18xx_cgu_idivbcde_src_ids[] = {
- CLK_SRC_OSC32, CLK_SRC_IRC, CLK_SRC_ENET_RX_CLK,
- CLK_SRC_ENET_TX_CLK, CLK_SRC_GP_CLKIN, CLK_SRC_OSC,
- CLK_SRC_PLL0AUDIO, CLK_SRC_PLL1, CLK_SRC_IDIVA,
-};
-
-static u32 lpc18xx_cgu_base_irc_src_ids[] = {CLK_SRC_IRC};
-
-static u32 lpc18xx_cgu_base_usb0_src_ids[] = {CLK_SRC_PLL0USB};
-
-static u32 lpc18xx_cgu_base_common_src_ids[] = {
- CLK_SRC_OSC32, CLK_SRC_IRC, CLK_SRC_ENET_RX_CLK,
- CLK_SRC_ENET_TX_CLK, CLK_SRC_GP_CLKIN, CLK_SRC_OSC,
- CLK_SRC_PLL0AUDIO, CLK_SRC_PLL1, CLK_SRC_IDIVA,
- CLK_SRC_IDIVB, CLK_SRC_IDIVC, CLK_SRC_IDIVD, CLK_SRC_IDIVE,
-};
-
-static u32 lpc18xx_cgu_base_all_src_ids[] = {
- CLK_SRC_OSC32, CLK_SRC_IRC, CLK_SRC_ENET_RX_CLK,
- CLK_SRC_ENET_TX_CLK, CLK_SRC_GP_CLKIN, CLK_SRC_OSC,
- CLK_SRC_PLL0USB, CLK_SRC_PLL0AUDIO, CLK_SRC_PLL1,
- CLK_SRC_IDIVA, CLK_SRC_IDIVB, CLK_SRC_IDIVC,
- CLK_SRC_IDIVD, CLK_SRC_IDIVE,
-};
-
-struct lpc18xx_cgu_src_clk_div {
- u8 clk_id;
- u8 n_parents;
- struct clk_divider div;
- struct clk_mux mux;
- struct clk_gate gate;
-};
-
-#define LPC1XX_CGU_SRC_CLK_DIV(_id, _width, _table) \
-{ \
- .clk_id = CLK_SRC_ ##_id, \
- .n_parents = ARRAY_SIZE(lpc18xx_cgu_ ##_table), \
- .div = { \
- .shift = 2, \
- .width = _width, \
- }, \
- .mux = { \
- .mask = 0x1f, \
- .shift = 24, \
- .table = lpc18xx_cgu_ ##_table, \
- }, \
- .gate = { \
- .bit_idx = 0, \
- .flags = CLK_GATE_SET_TO_DISABLE, \
- }, \
-}
-
-static struct lpc18xx_cgu_src_clk_div lpc18xx_cgu_src_clk_divs[] = {
- LPC1XX_CGU_SRC_CLK_DIV(IDIVA, 2, idiva_src_ids),
- LPC1XX_CGU_SRC_CLK_DIV(IDIVB, 4, idivbcde_src_ids),
- LPC1XX_CGU_SRC_CLK_DIV(IDIVC, 4, idivbcde_src_ids),
- LPC1XX_CGU_SRC_CLK_DIV(IDIVD, 4, idivbcde_src_ids),
- LPC1XX_CGU_SRC_CLK_DIV(IDIVE, 8, idivbcde_src_ids),
-};
-
-struct lpc18xx_cgu_base_clk {
- u8 clk_id;
- u8 n_parents;
- struct clk_mux mux;
- struct clk_gate gate;
-};
-
-#define LPC1XX_CGU_BASE_CLK(_id, _table, _flags) \
-{ \
- .clk_id = BASE_ ##_id ##_CLK, \
- .n_parents = ARRAY_SIZE(lpc18xx_cgu_ ##_table), \
- .mux = { \
- .mask = 0x1f, \
- .shift = 24, \
- .table = lpc18xx_cgu_ ##_table, \
- .flags = _flags, \
- }, \
- .gate = { \
- .bit_idx = 0, \
- .flags = CLK_GATE_SET_TO_DISABLE, \
- }, \
-}
-
-static struct lpc18xx_cgu_base_clk lpc18xx_cgu_base_clks[] = {
- LPC1XX_CGU_BASE_CLK(SAFE, base_irc_src_ids, CLK_MUX_READ_ONLY),
- LPC1XX_CGU_BASE_CLK(USB0, base_usb0_src_ids, 0),
- LPC1XX_CGU_BASE_CLK(PERIPH, base_common_src_ids, 0),
- LPC1XX_CGU_BASE_CLK(USB1, base_all_src_ids, 0),
- LPC1XX_CGU_BASE_CLK(CPU, base_common_src_ids, 0),
- LPC1XX_CGU_BASE_CLK(SPIFI, base_common_src_ids, 0),
- LPC1XX_CGU_BASE_CLK(SPI, base_common_src_ids, 0),
- LPC1XX_CGU_BASE_CLK(PHY_RX, base_common_src_ids, 0),
- LPC1XX_CGU_BASE_CLK(PHY_TX, base_common_src_ids, 0),
- LPC1XX_CGU_BASE_CLK(APB1, base_common_src_ids, 0),
- LPC1XX_CGU_BASE_CLK(APB3, base_common_src_ids, 0),
- LPC1XX_CGU_BASE_CLK(LCD, base_common_src_ids, 0),
- LPC1XX_CGU_BASE_CLK(ADCHS, base_common_src_ids, 0),
- LPC1XX_CGU_BASE_CLK(SDIO, base_common_src_ids, 0),
- LPC1XX_CGU_BASE_CLK(SSP0, base_common_src_ids, 0),
- LPC1XX_CGU_BASE_CLK(SSP1, base_common_src_ids, 0),
- LPC1XX_CGU_BASE_CLK(UART0, base_common_src_ids, 0),
- LPC1XX_CGU_BASE_CLK(UART1, base_common_src_ids, 0),
- LPC1XX_CGU_BASE_CLK(UART2, base_common_src_ids, 0),
- LPC1XX_CGU_BASE_CLK(UART3, base_common_src_ids, 0),
- LPC1XX_CGU_BASE_CLK(OUT, base_all_src_ids, 0),
- { /* 21 reserved */ },
- { /* 22 reserved */ },
- { /* 23 reserved */ },
- { /* 24 reserved */ },
- LPC1XX_CGU_BASE_CLK(AUDIO, base_common_src_ids, 0),
- LPC1XX_CGU_BASE_CLK(CGU_OUT0, base_all_src_ids, 0),
- LPC1XX_CGU_BASE_CLK(CGU_OUT1, base_all_src_ids, 0),
-};
-
-struct lpc18xx_pll {
- struct clk_hw hw;
- void __iomem *reg;
- u8 flags;
-};
-
-#define to_lpc_pll(hw) container_of(hw, struct lpc18xx_pll, hw)
-
-struct lpc18xx_cgu_pll_clk {
- u8 clk_id;
- u8 n_parents;
- u8 reg_offset;
- struct clk_mux mux;
- struct clk_gate gate;
- struct lpc18xx_pll pll;
- const struct clk_ops *pll_ops;
-};
-
-#define LPC1XX_CGU_CLK_PLL(_id, _table, _pll_ops) \
-{ \
- .clk_id = CLK_SRC_ ##_id, \
- .n_parents = ARRAY_SIZE(lpc18xx_cgu_ ##_table), \
- .reg_offset = LPC18XX_CGU_ ##_id ##_STAT, \
- .mux = { \
- .mask = 0x1f, \
- .shift = 24, \
- .table = lpc18xx_cgu_ ##_table, \
- }, \
- .gate = { \
- .bit_idx = 0, \
- .flags = CLK_GATE_SET_TO_DISABLE, \
- }, \
- .pll_ops = &lpc18xx_ ##_pll_ops, \
-}
-
-/*
- * PLL0 uses a special register value encoding. The compute functions below
- * are taken or derived from the LPC1850 user manual (section 12.6.3.3).
- */
-
-/* Compute PLL0 multiplier from decoded version */
-static u32 lpc18xx_pll0_mdec2msel(u32 x)
-{
- int i;
-
- switch (x) {
- case 0x18003: return 1;
- case 0x10003: return 2;
- default:
- for (i = LPC18XX_PLL0_MSEL_MAX + 1; x != 0x4000 && i > 0; i--)
- x = ((x ^ x >> 14) & 1) | (x << 1 & 0x7fff);
- return i;
- }
-}
-/* Compute PLL0 decoded multiplier from binary version */
-static u32 lpc18xx_pll0_msel2mdec(u32 msel)
-{
- u32 i, x = 0x4000;
-
- switch (msel) {
- case 0: return 0;
- case 1: return 0x18003;
- case 2: return 0x10003;
- default:
- for (i = msel; i <= LPC18XX_PLL0_MSEL_MAX; i++)
- x = ((x ^ x >> 1) & 1) << 14 | (x >> 1 & 0xffff);
- return x;
- }
-}
-
-/* Compute PLL0 bandwidth SELI reg from multiplier */
-static u32 lpc18xx_pll0_msel2seli(u32 msel)
-{
- u32 tmp;
-
- if (msel > 16384) return 1;
- if (msel > 8192) return 2;
- if (msel > 2048) return 4;
- if (msel >= 501) return 8;
- if (msel >= 60) {
- tmp = 1024 / (msel + 9);
- return ((1024 == (tmp * (msel + 9))) == 0) ? tmp * 4 : (tmp + 1) * 4;
- }
-
- return (msel & 0x3c) + 4;
-}
-
-/* Compute PLL0 bandwidth SELP reg from multiplier */
-static u32 lpc18xx_pll0_msel2selp(u32 msel)
-{
- if (msel < 60)
- return (msel >> 1) + 1;
-
- return 31;
-}
-
-static unsigned long lpc18xx_pll0_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
-{
- struct lpc18xx_pll *pll = to_lpc_pll(hw);
- u32 ctrl, mdiv, msel, npdiv;
-
- ctrl = readl(pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
- mdiv = readl(pll->reg + LPC18XX_CGU_PLL0USB_MDIV);
- npdiv = readl(pll->reg + LPC18XX_CGU_PLL0USB_NP_DIV);
-
- if (ctrl & LPC18XX_PLL0_CTRL_BYPASS)
- return parent_rate;
-
- if (npdiv != LPC18XX_PLL0_NP_DIVS_1) {
- pr_warn("%s: pre/post dividers not supported\n", __func__);
- return 0;
- }
-
- msel = lpc18xx_pll0_mdec2msel(mdiv & LPC18XX_PLL0_MDIV_MDEC_MASK);
- if (msel)
- return 2 * msel * parent_rate;
-
- pr_warn("%s: unable to calculate rate\n", __func__);
-
- return 0;
-}
-
-static int lpc18xx_pll0_determine_rate(struct clk_hw *hw,
- struct clk_rate_request *req)
-{
- unsigned long m;
-
- if (req->best_parent_rate < req->rate) {
- pr_warn("%s: pll dividers not supported\n", __func__);
- return -EINVAL;
- }
-
- m = DIV_ROUND_UP_ULL(req->best_parent_rate, req->rate * 2);
- if (m == 0 || m > LPC18XX_PLL0_MSEL_MAX) {
- pr_warn("%s: unable to support rate %lu\n", __func__, req->rate);
- return -EINVAL;
- }
-
- req->rate = 2 * req->best_parent_rate * m;
-
- return 0;
-}
-
-static int lpc18xx_pll0_set_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long parent_rate)
-{
- struct lpc18xx_pll *pll = to_lpc_pll(hw);
- u32 ctrl, stat, m;
- int retry = 3;
-
- if (parent_rate < rate) {
- pr_warn("%s: pll dividers not supported\n", __func__);
- return -EINVAL;
- }
-
- m = DIV_ROUND_UP_ULL(parent_rate, rate * 2);
- if (m == 0 || m > LPC18XX_PLL0_MSEL_MAX) {
- pr_warn("%s: unable to support rate %lu\n", __func__, rate);
- return -EINVAL;
- }
-
- m = lpc18xx_pll0_msel2mdec(m);
- m |= lpc18xx_pll0_msel2selp(m) << LPC18XX_PLL0_MDIV_SELP_SHIFT;
- m |= lpc18xx_pll0_msel2seli(m) << LPC18XX_PLL0_MDIV_SELI_SHIFT;
-
- /* Power down PLL, disable clk output and dividers */
- ctrl = readl(pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
- ctrl |= LPC18XX_PLL0_CTRL_PD;
- ctrl &= ~(LPC18XX_PLL0_CTRL_BYPASS | LPC18XX_PLL0_CTRL_DIRECTI |
- LPC18XX_PLL0_CTRL_DIRECTO | LPC18XX_PLL0_CTRL_CLKEN);
- writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
-
- /* Configure new PLL settings */
- writel(m, pll->reg + LPC18XX_CGU_PLL0USB_MDIV);
- writel(LPC18XX_PLL0_NP_DIVS_1, pll->reg + LPC18XX_CGU_PLL0USB_NP_DIV);
-
- /* Power up PLL and wait for lock */
- ctrl &= ~LPC18XX_PLL0_CTRL_PD;
- writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
- do {
- udelay(10);
- stat = readl(pll->reg + LPC18XX_CGU_PLL0USB_STAT);
- if (stat & LPC18XX_PLL0_STAT_LOCK) {
- ctrl |= LPC18XX_PLL0_CTRL_CLKEN;
- writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
-
- return 0;
- }
- } while (retry--);
-
- pr_warn("%s: unable to lock pll\n", __func__);
-
- return -EINVAL;
-}
-
-static const struct clk_ops lpc18xx_pll0_ops = {
- .recalc_rate = lpc18xx_pll0_recalc_rate,
- .determine_rate = lpc18xx_pll0_determine_rate,
- .set_rate = lpc18xx_pll0_set_rate,
-};
-
-static unsigned long lpc18xx_pll1_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
-{
- struct lpc18xx_pll *pll = to_lpc_pll(hw);
- u16 msel, nsel, psel;
- bool direct, fbsel;
- u32 ctrl;
-
- ctrl = readl(pll->reg + LPC18XX_CGU_PLL1_CTRL);
-
- direct = (ctrl & LPC18XX_PLL1_CTRL_DIRECT) ? true : false;
- fbsel = (ctrl & LPC18XX_PLL1_CTRL_FBSEL) ? true : false;
-
- msel = ((ctrl >> 16) & 0xff) + 1;
- nsel = ((ctrl >> 12) & 0x3) + 1;
-
- if (direct || fbsel)
- return msel * (parent_rate / nsel);
-
- psel = (ctrl >> 8) & 0x3;
- psel = 1 << psel;
-
- return (msel / (2 * psel)) * (parent_rate / nsel);
-}
-
-static const struct clk_ops lpc18xx_pll1_ops = {
- .recalc_rate = lpc18xx_pll1_recalc_rate,
-};
-
-static int lpc18xx_cgu_gate_enable(struct clk_hw *hw)
-{
- return clk_gate_ops.enable(hw);
-}
-
-static void lpc18xx_cgu_gate_disable(struct clk_hw *hw)
-{
- clk_gate_ops.disable(hw);
-}
-
-static int lpc18xx_cgu_gate_is_enabled(struct clk_hw *hw)
-{
- const struct clk_hw *parent;
-
- /*
- * The consumer of base clocks needs know if the
- * base clock is really enabled before it can be
- * accessed. It is therefore necessary to verify
- * this all the way up.
- */
- parent = clk_hw_get_parent(hw);
- if (!parent)
- return 0;
-
- if (!clk_hw_is_enabled(parent))
- return 0;
-
- return clk_gate_ops.is_enabled(hw);
-}
-
-static const struct clk_ops lpc18xx_gate_ops = {
- .enable = lpc18xx_cgu_gate_enable,
- .disable = lpc18xx_cgu_gate_disable,
- .is_enabled = lpc18xx_cgu_gate_is_enabled,
-};
-
-static struct lpc18xx_cgu_pll_clk lpc18xx_cgu_src_clk_plls[] = {
- LPC1XX_CGU_CLK_PLL(PLL0USB, pll0_src_ids, pll0_ops),
- LPC1XX_CGU_CLK_PLL(PLL0AUDIO, pll0_src_ids, pll0_ops),
- LPC1XX_CGU_CLK_PLL(PLL1, pll1_src_ids, pll1_ops),
-};
-
-static void lpc18xx_fill_parent_names(const char **parent, const u32 *id, int size)
-{
- int i;
-
- for (i = 0; i < size; i++)
- parent[i] = clk_src_names[id[i]];
-}
-
-static struct clk *lpc18xx_cgu_register_div(struct lpc18xx_cgu_src_clk_div *clk,
- void __iomem *base, int n)
-{
- void __iomem *reg = base + LPC18XX_CGU_IDIV_CTRL(n);
- const char *name = clk_src_names[clk->clk_id];
- const char *parents[CLK_SRC_MAX];
-
- clk->div.reg = reg;
- clk->mux.reg = reg;
- clk->gate.reg = reg;
-
- lpc18xx_fill_parent_names(parents, clk->mux.table, clk->n_parents);
-
- return clk_register_composite(NULL, name, parents, clk->n_parents,
- &clk->mux.hw, &clk_mux_ops,
- &clk->div.hw, &clk_divider_ops,
- &clk->gate.hw, &lpc18xx_gate_ops, 0);
-}
-
-
-static struct clk *lpc18xx_register_base_clk(struct lpc18xx_cgu_base_clk *clk,
- void __iomem *reg_base, int n)
-{
- void __iomem *reg = reg_base + LPC18XX_CGU_BASE_CLK(n);
- const char *name = clk_base_names[clk->clk_id];
- const char *parents[CLK_SRC_MAX];
-
- if (clk->n_parents == 0)
- return ERR_PTR(-ENOENT);
-
- clk->mux.reg = reg;
- clk->gate.reg = reg;
-
- lpc18xx_fill_parent_names(parents, clk->mux.table, clk->n_parents);
-
- /* SAFE_CLK can not be turned off */
- if (n == BASE_SAFE_CLK)
- return clk_register_composite(NULL, name, parents, clk->n_parents,
- &clk->mux.hw, &clk_mux_ops,
- NULL, NULL, NULL, NULL, 0);
-
- return clk_register_composite(NULL, name, parents, clk->n_parents,
- &clk->mux.hw, &clk_mux_ops,
- NULL, NULL,
- &clk->gate.hw, &lpc18xx_gate_ops, 0);
-}
-
-
-static struct clk *lpc18xx_cgu_register_pll(struct lpc18xx_cgu_pll_clk *clk,
- void __iomem *base)
-{
- const char *name = clk_src_names[clk->clk_id];
- const char *parents[CLK_SRC_MAX];
-
- clk->pll.reg = base;
- clk->mux.reg = base + clk->reg_offset + LPC18XX_CGU_PLL_CTRL_OFFSET;
- clk->gate.reg = base + clk->reg_offset + LPC18XX_CGU_PLL_CTRL_OFFSET;
-
- lpc18xx_fill_parent_names(parents, clk->mux.table, clk->n_parents);
-
- return clk_register_composite(NULL, name, parents, clk->n_parents,
- &clk->mux.hw, &clk_mux_ops,
- &clk->pll.hw, clk->pll_ops,
- &clk->gate.hw, &lpc18xx_gate_ops, 0);
-}
-
-static void __init lpc18xx_cgu_register_source_clks(struct device_node *np,
- void __iomem *base)
-{
- const char *parents[CLK_SRC_MAX];
- struct clk *clk;
- int i;
-
- /* Register the internal 12 MHz RC oscillator (IRC) */
- clk = clk_register_fixed_rate(NULL, clk_src_names[CLK_SRC_IRC],
- NULL, 0, 12000000);
- if (IS_ERR(clk))
- pr_warn("%s: failed to register irc clk\n", __func__);
-
- /* Register crystal oscillator controller */
- parents[0] = of_clk_get_parent_name(np, 0);
- clk = clk_register_gate(NULL, clk_src_names[CLK_SRC_OSC], parents[0],
- 0, base + LPC18XX_CGU_XTAL_OSC_CTRL,
- 0, CLK_GATE_SET_TO_DISABLE, NULL);
- if (IS_ERR(clk))
- pr_warn("%s: failed to register osc clk\n", __func__);
-
- /* Register all PLLs */
- for (i = 0; i < ARRAY_SIZE(lpc18xx_cgu_src_clk_plls); i++) {
- clk = lpc18xx_cgu_register_pll(&lpc18xx_cgu_src_clk_plls[i],
- base);
- if (IS_ERR(clk))
- pr_warn("%s: failed to register pll (%d)\n", __func__, i);
- }
-
- /* Register all clock dividers A-E */
- for (i = 0; i < ARRAY_SIZE(lpc18xx_cgu_src_clk_divs); i++) {
- clk = lpc18xx_cgu_register_div(&lpc18xx_cgu_src_clk_divs[i],
- base, i);
- if (IS_ERR(clk))
- pr_warn("%s: failed to register div %d\n", __func__, i);
- }
-}
-
-static struct clk *clk_base[BASE_CLK_MAX];
-static struct clk_onecell_data clk_base_data = {
- .clks = clk_base,
- .clk_num = BASE_CLK_MAX,
-};
-
-static void __init lpc18xx_cgu_register_base_clks(void __iomem *reg_base)
-{
- int i;
-
- for (i = BASE_SAFE_CLK; i < BASE_CLK_MAX; i++) {
- clk_base[i] = lpc18xx_register_base_clk(&lpc18xx_cgu_base_clks[i],
- reg_base, i);
- if (IS_ERR(clk_base[i]) && PTR_ERR(clk_base[i]) != -ENOENT)
- pr_warn("%s: register base clk %d failed\n", __func__, i);
- }
-}
-
-static void __init lpc18xx_cgu_init(struct device_node *np)
-{
- void __iomem *reg_base;
-
- reg_base = of_iomap(np, 0);
- if (!reg_base) {
- pr_warn("%s: failed to map address range\n", __func__);
- return;
- }
-
- lpc18xx_cgu_register_source_clks(np, reg_base);
- lpc18xx_cgu_register_base_clks(reg_base);
-
- of_clk_add_provider(np, of_clk_src_onecell_get, &clk_base_data);
-}
-CLK_OF_DECLARE(lpc18xx_cgu, "nxp,lpc1850-cgu", lpc18xx_cgu_init);
diff --git a/drivers/clk/nxp/clk-lpc18xx-creg.c b/drivers/clk/nxp/clk-lpc18xx-creg.c
deleted file mode 100644
index 3d3982e9c661a..0000000000000
--- a/drivers/clk/nxp/clk-lpc18xx-creg.c
+++ /dev/null
@@ -1,225 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Clk driver for NXP LPC18xx/43xx Configuration Registers (CREG)
- *
- * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
- */
-
-#include <linux/clk-provider.h>
-#include <linux/delay.h>
-#include <linux/kernel.h>
-#include <linux/mfd/syscon.h>
-#include <linux/of.h>
-#include <linux/platform_device.h>
-#include <linux/regmap.h>
-
-#define LPC18XX_CREG_CREG0 0x004
-#define LPC18XX_CREG_CREG0_EN1KHZ BIT(0)
-#define LPC18XX_CREG_CREG0_EN32KHZ BIT(1)
-#define LPC18XX_CREG_CREG0_RESET32KHZ BIT(2)
-#define LPC18XX_CREG_CREG0_PD32KHZ BIT(3)
-
-#define to_clk_creg(_hw) container_of(_hw, struct clk_creg_data, hw)
-
-enum {
- CREG_CLK_1KHZ,
- CREG_CLK_32KHZ,
- CREG_CLK_MAX,
-};
-
-struct clk_creg_data {
- struct clk_hw hw;
- const char *name;
- struct regmap *reg;
- unsigned int en_mask;
- const struct clk_ops *ops;
-};
-
-#define CREG_CLK(_name, _emask, _ops) \
-{ \
- .name = _name, \
- .en_mask = LPC18XX_CREG_CREG0_##_emask, \
- .ops = &_ops, \
-}
-
-static int clk_creg_32k_prepare(struct clk_hw *hw)
-{
- struct clk_creg_data *creg = to_clk_creg(hw);
- int ret;
-
- ret = regmap_update_bits(creg->reg, LPC18XX_CREG_CREG0,
- LPC18XX_CREG_CREG0_PD32KHZ |
- LPC18XX_CREG_CREG0_RESET32KHZ, 0);
-
- /*
- * Powering up the 32k oscillator takes a long while
- * and sadly there aren't any status bit to poll.
- */
- msleep(2500);
-
- return ret;
-}
-
-static void clk_creg_32k_unprepare(struct clk_hw *hw)
-{
- struct clk_creg_data *creg = to_clk_creg(hw);
-
- regmap_update_bits(creg->reg, LPC18XX_CREG_CREG0,
- LPC18XX_CREG_CREG0_PD32KHZ,
- LPC18XX_CREG_CREG0_PD32KHZ);
-}
-
-static int clk_creg_32k_is_prepared(struct clk_hw *hw)
-{
- struct clk_creg_data *creg = to_clk_creg(hw);
- u32 reg;
-
- regmap_read(creg->reg, LPC18XX_CREG_CREG0, ®);
-
- return !(reg & LPC18XX_CREG_CREG0_PD32KHZ) &&
- !(reg & LPC18XX_CREG_CREG0_RESET32KHZ);
-}
-
-static unsigned long clk_creg_1k_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
-{
- return parent_rate / 32;
-}
-
-static int clk_creg_enable(struct clk_hw *hw)
-{
- struct clk_creg_data *creg = to_clk_creg(hw);
-
- return regmap_update_bits(creg->reg, LPC18XX_CREG_CREG0,
- creg->en_mask, creg->en_mask);
-}
-
-static void clk_creg_disable(struct clk_hw *hw)
-{
- struct clk_creg_data *creg = to_clk_creg(hw);
-
- regmap_update_bits(creg->reg, LPC18XX_CREG_CREG0,
- creg->en_mask, 0);
-}
-
-static int clk_creg_is_enabled(struct clk_hw *hw)
-{
- struct clk_creg_data *creg = to_clk_creg(hw);
- u32 reg;
-
- regmap_read(creg->reg, LPC18XX_CREG_CREG0, ®);
-
- return !!(reg & creg->en_mask);
-}
-
-static const struct clk_ops clk_creg_32k = {
- .enable = clk_creg_enable,
- .disable = clk_creg_disable,
- .is_enabled = clk_creg_is_enabled,
- .prepare = clk_creg_32k_prepare,
- .unprepare = clk_creg_32k_unprepare,
- .is_prepared = clk_creg_32k_is_prepared,
-};
-
-static const struct clk_ops clk_creg_1k = {
- .enable = clk_creg_enable,
- .disable = clk_creg_disable,
- .is_enabled = clk_creg_is_enabled,
- .recalc_rate = clk_creg_1k_recalc_rate,
-};
-
-static struct clk_creg_data clk_creg_clocks[] = {
- [CREG_CLK_1KHZ] = CREG_CLK("1khz_clk", EN1KHZ, clk_creg_1k),
- [CREG_CLK_32KHZ] = CREG_CLK("32khz_clk", EN32KHZ, clk_creg_32k),
-};
-
-static struct clk *clk_register_creg_clk(struct device *dev,
- struct clk_creg_data *creg_clk,
- const char **parent_name,
- struct regmap *syscon)
-{
- struct clk_init_data init;
-
- init.ops = creg_clk->ops;
- init.name = creg_clk->name;
- init.parent_names = parent_name;
- init.num_parents = 1;
- init.flags = 0;
-
- creg_clk->reg = syscon;
- creg_clk->hw.init = &init;
-
- if (dev)
- return devm_clk_register(dev, &creg_clk->hw);
-
- return clk_register(NULL, &creg_clk->hw);
-}
-
-static struct clk *clk_creg_early[CREG_CLK_MAX];
-static struct clk_onecell_data clk_creg_early_data = {
- .clks = clk_creg_early,
- .clk_num = CREG_CLK_MAX,
-};
-
-static void __init lpc18xx_creg_clk_init(struct device_node *np)
-{
- const char *clk_32khz_parent;
- struct regmap *syscon;
-
- syscon = syscon_node_to_regmap(np->parent);
- if (IS_ERR(syscon)) {
- pr_err("%s: syscon lookup failed\n", __func__);
- return;
- }
-
- clk_32khz_parent = of_clk_get_parent_name(np, 0);
-
- clk_creg_early[CREG_CLK_32KHZ] =
- clk_register_creg_clk(NULL, &clk_creg_clocks[CREG_CLK_32KHZ],
- &clk_32khz_parent, syscon);
- clk_creg_early[CREG_CLK_1KHZ] = ERR_PTR(-EPROBE_DEFER);
-
- of_clk_add_provider(np, of_clk_src_onecell_get, &clk_creg_early_data);
-}
-CLK_OF_DECLARE_DRIVER(lpc18xx_creg_clk, "nxp,lpc1850-creg-clk",
- lpc18xx_creg_clk_init);
-
-static struct clk *clk_creg[CREG_CLK_MAX];
-static struct clk_onecell_data clk_creg_data = {
- .clks = clk_creg,
- .clk_num = CREG_CLK_MAX,
-};
-
-static int lpc18xx_creg_clk_probe(struct platform_device *pdev)
-{
- struct device_node *np = pdev->dev.of_node;
- struct regmap *syscon;
-
- syscon = syscon_node_to_regmap(np->parent);
- if (IS_ERR(syscon)) {
- dev_err(&pdev->dev, "syscon lookup failed\n");
- return PTR_ERR(syscon);
- }
-
- clk_creg[CREG_CLK_32KHZ] = clk_creg_early[CREG_CLK_32KHZ];
- clk_creg[CREG_CLK_1KHZ] =
- clk_register_creg_clk(NULL, &clk_creg_clocks[CREG_CLK_1KHZ],
- &clk_creg_clocks[CREG_CLK_32KHZ].name,
- syscon);
-
- return of_clk_add_provider(np, of_clk_src_onecell_get, &clk_creg_data);
-}
-
-static const struct of_device_id lpc18xx_creg_clk_of_match[] = {
- { .compatible = "nxp,lpc1850-creg-clk" },
- {},
-};
-
-static struct platform_driver lpc18xx_creg_clk_driver = {
- .probe = lpc18xx_creg_clk_probe,
- .driver = {
- .name = "lpc18xx-creg-clk",
- .of_match_table = lpc18xx_creg_clk_of_match,
- },
-};
-builtin_platform_driver(lpc18xx_creg_clk_driver);
diff --git a/drivers/clk/nxp/clk-lpc32xx.c b/drivers/clk/nxp/clk-lpc32xx.c
deleted file mode 100644
index ae2fa5341a2e4..0000000000000
--- a/drivers/clk/nxp/clk-lpc32xx.c
+++ /dev/null
@@ -1,1591 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Copyright 2015 Vladimir Zapolskiy <vz@mleia.com>
- */
-
-#include <linux/clk.h>
-#include <linux/clk-provider.h>
-#include <linux/io.h>
-#include <linux/of_address.h>
-#include <linux/regmap.h>
-
-#include <dt-bindings/clock/lpc32xx-clock.h>
-
-#undef pr_fmt
-#define pr_fmt(fmt) "%s: " fmt, __func__
-
-/* Common bitfield definitions for x397 PLL (lock), USB PLL and HCLK PLL */
-#define PLL_CTRL_ENABLE BIT(16)
-#define PLL_CTRL_BYPASS BIT(15)
-#define PLL_CTRL_DIRECT BIT(14)
-#define PLL_CTRL_FEEDBACK BIT(13)
-#define PLL_CTRL_POSTDIV (BIT(12)|BIT(11))
-#define PLL_CTRL_PREDIV (BIT(10)|BIT(9))
-#define PLL_CTRL_FEEDDIV (0xFF << 1)
-#define PLL_CTRL_LOCK BIT(0)
-
-/* Clock registers on System Control Block */
-#define LPC32XX_CLKPWR_DEBUG_CTRL 0x00
-#define LPC32XX_CLKPWR_USB_DIV 0x1C
-#define LPC32XX_CLKPWR_HCLKDIV_CTRL 0x40
-#define LPC32XX_CLKPWR_PWR_CTRL 0x44
-#define LPC32XX_CLKPWR_PLL397_CTRL 0x48
-#define LPC32XX_CLKPWR_OSC_CTRL 0x4C
-#define LPC32XX_CLKPWR_SYSCLK_CTRL 0x50
-#define LPC32XX_CLKPWR_LCDCLK_CTRL 0x54
-#define LPC32XX_CLKPWR_HCLKPLL_CTRL 0x58
-#define LPC32XX_CLKPWR_ADCCLK_CTRL1 0x60
-#define LPC32XX_CLKPWR_USB_CTRL 0x64
-#define LPC32XX_CLKPWR_SSP_CTRL 0x78
-#define LPC32XX_CLKPWR_I2S_CTRL 0x7C
-#define LPC32XX_CLKPWR_MS_CTRL 0x80
-#define LPC32XX_CLKPWR_MACCLK_CTRL 0x90
-#define LPC32XX_CLKPWR_TEST_CLK_CTRL 0xA4
-#define LPC32XX_CLKPWR_I2CCLK_CTRL 0xAC
-#define LPC32XX_CLKPWR_KEYCLK_CTRL 0xB0
-#define LPC32XX_CLKPWR_ADCCLK_CTRL 0xB4
-#define LPC32XX_CLKPWR_PWMCLK_CTRL 0xB8
-#define LPC32XX_CLKPWR_TIMCLK_CTRL 0xBC
-#define LPC32XX_CLKPWR_TIMCLK_CTRL1 0xC0
-#define LPC32XX_CLKPWR_SPI_CTRL 0xC4
-#define LPC32XX_CLKPWR_FLASHCLK_CTRL 0xC8
-#define LPC32XX_CLKPWR_UART3_CLK_CTRL 0xD0
-#define LPC32XX_CLKPWR_UART4_CLK_CTRL 0xD4
-#define LPC32XX_CLKPWR_UART5_CLK_CTRL 0xD8
-#define LPC32XX_CLKPWR_UART6_CLK_CTRL 0xDC
-#define LPC32XX_CLKPWR_IRDA_CLK_CTRL 0xE0
-#define LPC32XX_CLKPWR_UART_CLK_CTRL 0xE4
-#define LPC32XX_CLKPWR_DMA_CLK_CTRL 0xE8
-
-/* Clock registers on USB controller */
-#define LPC32XX_USB_CLK_CTRL 0xF4
-#define LPC32XX_USB_CLK_STS 0xF8
-
-static const struct regmap_config lpc32xx_scb_regmap_config = {
- .name = "scb",
- .reg_bits = 32,
- .val_bits = 32,
- .reg_stride = 4,
- .val_format_endian = REGMAP_ENDIAN_LITTLE,
- .max_register = 0x114,
-};
-
-static struct regmap *clk_regmap;
-static void __iomem *usb_clk_vbase;
-
-enum {
- LPC32XX_USB_CLK_OTG = LPC32XX_USB_CLK_HOST + 1,
- LPC32XX_USB_CLK_AHB,
-
- LPC32XX_USB_CLK_MAX = LPC32XX_USB_CLK_AHB + 1,
-};
-
-enum {
- /* Start from the last defined clock in dt bindings */
- LPC32XX_CLK_ADC_DIV = LPC32XX_CLK_PERIPH + 1,
- LPC32XX_CLK_ADC_RTC,
- LPC32XX_CLK_TEST1,
- LPC32XX_CLK_TEST2,
-
- /* System clocks, PLL 397x and HCLK PLL clocks */
- LPC32XX_CLK_OSC,
- LPC32XX_CLK_SYS,
- LPC32XX_CLK_PLL397X,
- LPC32XX_CLK_HCLK_DIV_PERIPH,
- LPC32XX_CLK_HCLK_DIV,
- LPC32XX_CLK_HCLK,
- LPC32XX_CLK_ARM,
- LPC32XX_CLK_ARM_VFP,
-
- /* USB clocks */
- LPC32XX_CLK_USB_PLL,
- LPC32XX_CLK_USB_DIV,
- LPC32XX_CLK_USB,
-
- /* Only one control PWR_CTRL[10] for both muxes */
- LPC32XX_CLK_PERIPH_HCLK_MUX,
- LPC32XX_CLK_PERIPH_ARM_MUX,
-
- /* Only one control PWR_CTRL[2] for all three muxes */
- LPC32XX_CLK_SYSCLK_PERIPH_MUX,
- LPC32XX_CLK_SYSCLK_HCLK_MUX,
- LPC32XX_CLK_SYSCLK_ARM_MUX,
-
- /* Two clock sources external to the driver */
- LPC32XX_CLK_XTAL_32K,
- LPC32XX_CLK_XTAL,
-
- /* Renumbered USB clocks, may have a parent from SCB table */
- LPC32XX_CLK_USB_OFFSET,
- LPC32XX_CLK_USB_I2C = LPC32XX_USB_CLK_I2C + LPC32XX_CLK_USB_OFFSET,
- LPC32XX_CLK_USB_DEV = LPC32XX_USB_CLK_DEVICE + LPC32XX_CLK_USB_OFFSET,
- LPC32XX_CLK_USB_HOST = LPC32XX_USB_CLK_HOST + LPC32XX_CLK_USB_OFFSET,
- LPC32XX_CLK_USB_OTG = LPC32XX_USB_CLK_OTG + LPC32XX_CLK_USB_OFFSET,
- LPC32XX_CLK_USB_AHB = LPC32XX_USB_CLK_AHB + LPC32XX_CLK_USB_OFFSET,
-
- /* Stub for composite clocks */
- LPC32XX_CLK__NULL,
-
- /* Subclocks of composite clocks, clocks above are for CCF */
- LPC32XX_CLK_PWM1_MUX,
- LPC32XX_CLK_PWM1_DIV,
- LPC32XX_CLK_PWM1_GATE,
- LPC32XX_CLK_PWM2_MUX,
- LPC32XX_CLK_PWM2_DIV,
- LPC32XX_CLK_PWM2_GATE,
- LPC32XX_CLK_UART3_MUX,
- LPC32XX_CLK_UART3_DIV,
- LPC32XX_CLK_UART3_GATE,
- LPC32XX_CLK_UART4_MUX,
- LPC32XX_CLK_UART4_DIV,
- LPC32XX_CLK_UART4_GATE,
- LPC32XX_CLK_UART5_MUX,
- LPC32XX_CLK_UART5_DIV,
- LPC32XX_CLK_UART5_GATE,
- LPC32XX_CLK_UART6_MUX,
- LPC32XX_CLK_UART6_DIV,
- LPC32XX_CLK_UART6_GATE,
- LPC32XX_CLK_TEST1_MUX,
- LPC32XX_CLK_TEST1_GATE,
- LPC32XX_CLK_TEST2_MUX,
- LPC32XX_CLK_TEST2_GATE,
- LPC32XX_CLK_USB_DIV_DIV,
- LPC32XX_CLK_USB_DIV_GATE,
- LPC32XX_CLK_SD_DIV,
- LPC32XX_CLK_SD_GATE,
- LPC32XX_CLK_LCD_DIV,
- LPC32XX_CLK_LCD_GATE,
-
- LPC32XX_CLK_HW_MAX,
- LPC32XX_CLK_MAX = LPC32XX_CLK_SYSCLK_ARM_MUX + 1,
- LPC32XX_CLK_CCF_MAX = LPC32XX_CLK_USB_AHB + 1,
-};
-
-static struct clk *clk[LPC32XX_CLK_MAX];
-static struct clk_onecell_data clk_data = {
- .clks = clk,
- .clk_num = LPC32XX_CLK_MAX,
-};
-
-static struct clk *usb_clk[LPC32XX_USB_CLK_MAX];
-static struct clk_onecell_data usb_clk_data = {
- .clks = usb_clk,
- .clk_num = LPC32XX_USB_CLK_MAX,
-};
-
-#define LPC32XX_CLK_PARENTS_MAX 5
-
-struct clk_proto_t {
- const char *name;
- const u8 parents[LPC32XX_CLK_PARENTS_MAX];
- u8 num_parents;
- unsigned long flags;
-};
-
-#define CLK_PREFIX(LITERAL) LPC32XX_CLK_ ## LITERAL
-#define NUMARGS(...) (sizeof((int[]){__VA_ARGS__})/sizeof(int))
-
-#define LPC32XX_CLK_DEFINE(_idx, _name, _flags, ...) \
- [CLK_PREFIX(_idx)] = { \
- .name = _name, \
- .flags = _flags, \
- .parents = { __VA_ARGS__ }, \
- .num_parents = NUMARGS(__VA_ARGS__), \
- }
-
-static const struct clk_proto_t clk_proto[LPC32XX_CLK_CCF_MAX] __initconst = {
- LPC32XX_CLK_DEFINE(XTAL, "xtal", 0x0),
- LPC32XX_CLK_DEFINE(XTAL_32K, "xtal_32k", 0x0),
-
- LPC32XX_CLK_DEFINE(RTC, "rtc", 0x0, LPC32XX_CLK_XTAL_32K),
- LPC32XX_CLK_DEFINE(OSC, "osc", CLK_IGNORE_UNUSED, LPC32XX_CLK_XTAL),
- LPC32XX_CLK_DEFINE(SYS, "sys", CLK_IGNORE_UNUSED,
- LPC32XX_CLK_OSC, LPC32XX_CLK_PLL397X),
- LPC32XX_CLK_DEFINE(PLL397X, "pll_397x", CLK_IGNORE_UNUSED,
- LPC32XX_CLK_RTC),
- LPC32XX_CLK_DEFINE(HCLK_PLL, "hclk_pll", CLK_IGNORE_UNUSED,
- LPC32XX_CLK_SYS),
- LPC32XX_CLK_DEFINE(HCLK_DIV_PERIPH, "hclk_div_periph",
- CLK_IGNORE_UNUSED, LPC32XX_CLK_HCLK_PLL),
- LPC32XX_CLK_DEFINE(HCLK_DIV, "hclk_div", CLK_IGNORE_UNUSED,
- LPC32XX_CLK_HCLK_PLL),
- LPC32XX_CLK_DEFINE(HCLK, "hclk", CLK_IGNORE_UNUSED,
- LPC32XX_CLK_PERIPH_HCLK_MUX),
- LPC32XX_CLK_DEFINE(PERIPH, "pclk", CLK_IGNORE_UNUSED,
- LPC32XX_CLK_SYSCLK_PERIPH_MUX),
- LPC32XX_CLK_DEFINE(ARM, "arm", CLK_IGNORE_UNUSED,
- LPC32XX_CLK_PERIPH_ARM_MUX),
-
- LPC32XX_CLK_DEFINE(PERIPH_HCLK_MUX, "periph_hclk_mux",
- CLK_IGNORE_UNUSED,
- LPC32XX_CLK_SYSCLK_HCLK_MUX, LPC32XX_CLK_SYSCLK_PERIPH_MUX),
- LPC32XX_CLK_DEFINE(PERIPH_ARM_MUX, "periph_arm_mux", CLK_IGNORE_UNUSED,
- LPC32XX_CLK_SYSCLK_ARM_MUX, LPC32XX_CLK_SYSCLK_PERIPH_MUX),
- LPC32XX_CLK_DEFINE(SYSCLK_PERIPH_MUX, "sysclk_periph_mux",
- CLK_IGNORE_UNUSED,
- LPC32XX_CLK_SYS, LPC32XX_CLK_HCLK_DIV_PERIPH),
- LPC32XX_CLK_DEFINE(SYSCLK_HCLK_MUX, "sysclk_hclk_mux",
- CLK_IGNORE_UNUSED,
- LPC32XX_CLK_SYS, LPC32XX_CLK_HCLK_DIV),
- LPC32XX_CLK_DEFINE(SYSCLK_ARM_MUX, "sysclk_arm_mux", CLK_IGNORE_UNUSED,
- LPC32XX_CLK_SYS, LPC32XX_CLK_HCLK_PLL),
-
- LPC32XX_CLK_DEFINE(ARM_VFP, "vfp9", CLK_IGNORE_UNUSED,
- LPC32XX_CLK_ARM),
- LPC32XX_CLK_DEFINE(USB_PLL, "usb_pll",
- CLK_SET_RATE_GATE | CLK_SET_RATE_PARENT, LPC32XX_CLK_USB_DIV),
- LPC32XX_CLK_DEFINE(USB_DIV, "usb_div", 0x0, LPC32XX_CLK_OSC),
- LPC32XX_CLK_DEFINE(USB, "usb", 0x0, LPC32XX_CLK_USB_PLL),
- LPC32XX_CLK_DEFINE(DMA, "dma", 0x0, LPC32XX_CLK_HCLK),
- LPC32XX_CLK_DEFINE(MLC, "mlc", 0x0, LPC32XX_CLK_HCLK),
- LPC32XX_CLK_DEFINE(SLC, "slc", 0x0, LPC32XX_CLK_HCLK),
- LPC32XX_CLK_DEFINE(LCD, "lcd", 0x0, LPC32XX_CLK_HCLK),
- LPC32XX_CLK_DEFINE(MAC, "mac", 0x0, LPC32XX_CLK_HCLK),
- LPC32XX_CLK_DEFINE(SD, "sd", 0x0, LPC32XX_CLK_ARM),
- LPC32XX_CLK_DEFINE(DDRAM, "ddram", CLK_GET_RATE_NOCACHE,
- LPC32XX_CLK_SYSCLK_ARM_MUX),
- LPC32XX_CLK_DEFINE(SSP0, "ssp0", 0x0, LPC32XX_CLK_HCLK),
- LPC32XX_CLK_DEFINE(SSP1, "ssp1", 0x0, LPC32XX_CLK_HCLK),
-
- /*
- * CLK_GET_RATE_NOCACHE is needed, if UART clock is disabled, its
- * divider register does not contain information about selected rate.
- */
- LPC32XX_CLK_DEFINE(UART3, "uart3", CLK_GET_RATE_NOCACHE,
- LPC32XX_CLK_PERIPH, LPC32XX_CLK_HCLK),
- LPC32XX_CLK_DEFINE(UART4, "uart4", CLK_GET_RATE_NOCACHE,
- LPC32XX_CLK_PERIPH, LPC32XX_CLK_HCLK),
- LPC32XX_CLK_DEFINE(UART5, "uart5", CLK_GET_RATE_NOCACHE,
- LPC32XX_CLK_PERIPH, LPC32XX_CLK_HCLK),
- LPC32XX_CLK_DEFINE(UART6, "uart6", CLK_GET_RATE_NOCACHE,
- LPC32XX_CLK_PERIPH, LPC32XX_CLK_HCLK),
- LPC32XX_CLK_DEFINE(IRDA, "irda", 0x0, LPC32XX_CLK_PERIPH),
- LPC32XX_CLK_DEFINE(I2C1, "i2c1", 0x0, LPC32XX_CLK_HCLK),
- LPC32XX_CLK_DEFINE(I2C2, "i2c2", 0x0, LPC32XX_CLK_HCLK),
- LPC32XX_CLK_DEFINE(TIMER0, "timer0", 0x0, LPC32XX_CLK_PERIPH),
- LPC32XX_CLK_DEFINE(TIMER1, "timer1", 0x0, LPC32XX_CLK_PERIPH),
- LPC32XX_CLK_DEFINE(TIMER2, "timer2", 0x0, LPC32XX_CLK_PERIPH),
- LPC32XX_CLK_DEFINE(TIMER3, "timer3", 0x0, LPC32XX_CLK_PERIPH),
- LPC32XX_CLK_DEFINE(TIMER4, "timer4", 0x0, LPC32XX_CLK_PERIPH),
- LPC32XX_CLK_DEFINE(TIMER5, "timer5", 0x0, LPC32XX_CLK_PERIPH),
- LPC32XX_CLK_DEFINE(WDOG, "watchdog", 0x0, LPC32XX_CLK_PERIPH),
- LPC32XX_CLK_DEFINE(I2S0, "i2s0", 0x0, LPC32XX_CLK_HCLK),
- LPC32XX_CLK_DEFINE(I2S1, "i2s1", 0x0, LPC32XX_CLK_HCLK),
- LPC32XX_CLK_DEFINE(SPI1, "spi1", 0x0, LPC32XX_CLK_HCLK),
- LPC32XX_CLK_DEFINE(SPI2, "spi2", 0x0, LPC32XX_CLK_HCLK),
- LPC32XX_CLK_DEFINE(MCPWM, "mcpwm", 0x0, LPC32XX_CLK_HCLK),
- LPC32XX_CLK_DEFINE(HSTIMER, "hstimer", 0x0, LPC32XX_CLK_PERIPH),
- LPC32XX_CLK_DEFINE(KEY, "key", 0x0, LPC32XX_CLK_RTC),
- LPC32XX_CLK_DEFINE(PWM1, "pwm1", 0x0,
- LPC32XX_CLK_RTC, LPC32XX_CLK_PERIPH),
- LPC32XX_CLK_DEFINE(PWM2, "pwm2", 0x0,
- LPC32XX_CLK_RTC, LPC32XX_CLK_PERIPH),
- LPC32XX_CLK_DEFINE(ADC, "adc", 0x0,
- LPC32XX_CLK_ADC_RTC, LPC32XX_CLK_ADC_DIV),
- LPC32XX_CLK_DEFINE(ADC_DIV, "adc_div", 0x0, LPC32XX_CLK_PERIPH),
- LPC32XX_CLK_DEFINE(ADC_RTC, "adc_rtc", 0x0, LPC32XX_CLK_RTC),
- LPC32XX_CLK_DEFINE(TEST1, "test1", 0x0,
- LPC32XX_CLK_PERIPH, LPC32XX_CLK_RTC, LPC32XX_CLK_OSC),
- LPC32XX_CLK_DEFINE(TEST2, "test2", 0x0,
- LPC32XX_CLK_HCLK, LPC32XX_CLK_PERIPH, LPC32XX_CLK_USB,
- LPC32XX_CLK_OSC, LPC32XX_CLK_PLL397X),
-
- /* USB controller clocks */
- LPC32XX_CLK_DEFINE(USB_AHB, "usb_ahb", 0x0, LPC32XX_CLK_USB),
- LPC32XX_CLK_DEFINE(USB_OTG, "usb_otg", 0x0, LPC32XX_CLK_USB_AHB),
- LPC32XX_CLK_DEFINE(USB_I2C, "usb_i2c", 0x0, LPC32XX_CLK_USB_AHB),
- LPC32XX_CLK_DEFINE(USB_DEV, "usb_dev", 0x0, LPC32XX_CLK_USB_OTG),
- LPC32XX_CLK_DEFINE(USB_HOST, "usb_host", 0x0, LPC32XX_CLK_USB_OTG),
-};
-
-struct lpc32xx_clk {
- struct clk_hw hw;
- u32 reg;
- u32 enable;
- u32 enable_mask;
- u32 disable;
- u32 disable_mask;
- u32 busy;
- u32 busy_mask;
-};
-
-enum clk_pll_mode {
- PLL_UNKNOWN,
- PLL_DIRECT,
- PLL_BYPASS,
- PLL_DIRECT_BYPASS,
- PLL_INTEGER,
- PLL_NON_INTEGER,
-};
-
-struct lpc32xx_pll_clk {
- struct clk_hw hw;
- u32 reg;
- u32 enable;
- unsigned long m_div;
- unsigned long n_div;
- unsigned long p_div;
- enum clk_pll_mode mode;
-};
-
-struct lpc32xx_usb_clk {
- struct clk_hw hw;
- u32 ctrl_enable;
- u32 ctrl_disable;
- u32 ctrl_mask;
- u32 enable;
- u32 busy;
-};
-
-struct lpc32xx_clk_mux {
- struct clk_hw hw;
- u32 reg;
- u32 mask;
- u8 shift;
- u32 *table;
- u8 flags;
-};
-
-struct lpc32xx_clk_div {
- struct clk_hw hw;
- u32 reg;
- u8 shift;
- u8 width;
- const struct clk_div_table *table;
- u8 flags;
-};
-
-struct lpc32xx_clk_gate {
- struct clk_hw hw;
- u32 reg;
- u8 bit_idx;
- u8 flags;
-};
-
-#define to_lpc32xx_clk(_hw) container_of(_hw, struct lpc32xx_clk, hw)
-#define to_lpc32xx_pll_clk(_hw) container_of(_hw, struct lpc32xx_pll_clk, hw)
-#define to_lpc32xx_usb_clk(_hw) container_of(_hw, struct lpc32xx_usb_clk, hw)
-#define to_lpc32xx_mux(_hw) container_of(_hw, struct lpc32xx_clk_mux, hw)
-#define to_lpc32xx_div(_hw) container_of(_hw, struct lpc32xx_clk_div, hw)
-#define to_lpc32xx_gate(_hw) container_of(_hw, struct lpc32xx_clk_gate, hw)
-
-static inline bool pll_is_valid(u64 val0, u64 val1, u64 min, u64 max)
-{
- return (val0 >= (val1 * min) && val0 <= (val1 * max));
-}
-
-static inline u32 lpc32xx_usb_clk_read(struct lpc32xx_usb_clk *clk)
-{
- return readl(usb_clk_vbase + LPC32XX_USB_CLK_STS);
-}
-
-static inline void lpc32xx_usb_clk_write(struct lpc32xx_usb_clk *clk, u32 val)
-{
- writel(val, usb_clk_vbase + LPC32XX_USB_CLK_CTRL);
-}
-
-static int clk_mask_enable(struct clk_hw *hw)
-{
- struct lpc32xx_clk *clk = to_lpc32xx_clk(hw);
- u32 val;
-
- regmap_read(clk_regmap, clk->reg, &val);
-
- if (clk->busy_mask && (val & clk->busy_mask) == clk->busy)
- return -EBUSY;
-
- return regmap_update_bits(clk_regmap, clk->reg,
- clk->enable_mask, clk->enable);
-}
-
-static void clk_mask_disable(struct clk_hw *hw)
-{
- struct lpc32xx_clk *clk = to_lpc32xx_clk(hw);
-
- regmap_update_bits(clk_regmap, clk->reg,
- clk->disable_mask, clk->disable);
-}
-
-static int clk_mask_is_enabled(struct clk_hw *hw)
-{
- struct lpc32xx_clk *clk = to_lpc32xx_clk(hw);
- u32 val;
-
- regmap_read(clk_regmap, clk->reg, &val);
-
- return ((val & clk->enable_mask) == clk->enable);
-}
-
-static const struct clk_ops clk_mask_ops = {
- .enable = clk_mask_enable,
- .disable = clk_mask_disable,
- .is_enabled = clk_mask_is_enabled,
-};
-
-static int clk_pll_enable(struct clk_hw *hw)
-{
- struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw);
- u32 val, count;
-
- regmap_update_bits(clk_regmap, clk->reg, clk->enable, clk->enable);
-
- for (count = 0; count < 1000; count++) {
- regmap_read(clk_regmap, clk->reg, &val);
- if (val & PLL_CTRL_LOCK)
- break;
- }
-
- if (val & PLL_CTRL_LOCK)
- return 0;
-
- return -ETIMEDOUT;
-}
-
-static void clk_pll_disable(struct clk_hw *hw)
-{
- struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw);
-
- regmap_update_bits(clk_regmap, clk->reg, clk->enable, 0x0);
-}
-
-static int clk_pll_is_enabled(struct clk_hw *hw)
-{
- struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw);
- u32 val;
-
- regmap_read(clk_regmap, clk->reg, &val);
-
- val &= clk->enable | PLL_CTRL_LOCK;
- if (val == (clk->enable | PLL_CTRL_LOCK))
- return 1;
-
- return 0;
-}
-
-static unsigned long clk_pll_397x_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
-{
- return parent_rate * 397;
-}
-
-static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
-{
- struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw);
- bool is_direct, is_bypass, is_feedback;
- unsigned long rate, cco_rate, ref_rate;
- u32 val;
-
- regmap_read(clk_regmap, clk->reg, &val);
- is_direct = val & PLL_CTRL_DIRECT;
- is_bypass = val & PLL_CTRL_BYPASS;
- is_feedback = val & PLL_CTRL_FEEDBACK;
-
- clk->m_div = ((val & PLL_CTRL_FEEDDIV) >> 1) + 1;
- clk->n_div = ((val & PLL_CTRL_PREDIV) >> 9) + 1;
- clk->p_div = ((val & PLL_CTRL_POSTDIV) >> 11) + 1;
-
- if (is_direct && is_bypass) {
- clk->p_div = 0;
- clk->mode = PLL_DIRECT_BYPASS;
- return parent_rate;
- }
- if (is_bypass) {
- clk->mode = PLL_BYPASS;
- return parent_rate / (1 << clk->p_div);
- }
- if (is_direct) {
- clk->p_div = 0;
- clk->mode = PLL_DIRECT;
- }
-
- ref_rate = parent_rate / clk->n_div;
- rate = cco_rate = ref_rate * clk->m_div;
-
- if (!is_direct) {
- if (is_feedback) {
- cco_rate *= (1 << clk->p_div);
- clk->mode = PLL_INTEGER;
- } else {
- rate /= (1 << clk->p_div);
- clk->mode = PLL_NON_INTEGER;
- }
- }
-
- pr_debug("%s: %lu: 0x%x: %d/%d/%d, %lu/%lu/%d => %lu\n",
- clk_hw_get_name(hw),
- parent_rate, val, is_direct, is_bypass, is_feedback,
- clk->n_div, clk->m_div, (1 << clk->p_div), rate);
-
- if (clk_pll_is_enabled(hw) &&
- !(pll_is_valid(parent_rate, 1, 1000000, 20000000)
- && pll_is_valid(cco_rate, 1, 156000000, 320000000)
- && pll_is_valid(ref_rate, 1, 1000000, 27000000)))
- pr_err("%s: PLL clocks are not in valid ranges: %lu/%lu/%lu\n",
- clk_hw_get_name(hw),
- parent_rate, cco_rate, ref_rate);
-
- return rate;
-}
-
-static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long parent_rate)
-{
- struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw);
- u32 val;
- unsigned long new_rate;
-
- /* Validate PLL clock parameters computed on round rate stage */
- switch (clk->mode) {
- case PLL_DIRECT:
- val = PLL_CTRL_DIRECT;
- val |= (clk->m_div - 1) << 1;
- val |= (clk->n_div - 1) << 9;
- new_rate = (parent_rate * clk->m_div) / clk->n_div;
- break;
- case PLL_BYPASS:
- val = PLL_CTRL_BYPASS;
- val |= (clk->p_div - 1) << 11;
- new_rate = parent_rate / (1 << (clk->p_div));
- break;
- case PLL_DIRECT_BYPASS:
- val = PLL_CTRL_DIRECT | PLL_CTRL_BYPASS;
- new_rate = parent_rate;
- break;
- case PLL_INTEGER:
- val = PLL_CTRL_FEEDBACK;
- val |= (clk->m_div - 1) << 1;
- val |= (clk->n_div - 1) << 9;
- val |= (clk->p_div - 1) << 11;
- new_rate = (parent_rate * clk->m_div) / clk->n_div;
- break;
- case PLL_NON_INTEGER:
- val = 0x0;
- val |= (clk->m_div - 1) << 1;
- val |= (clk->n_div - 1) << 9;
- val |= (clk->p_div - 1) << 11;
- new_rate = (parent_rate * clk->m_div) /
- (clk->n_div * (1 << clk->p_div));
- break;
- default:
- return -EINVAL;
- }
-
- /* Sanity check that round rate is equal to the requested one */
- if (new_rate != rate)
- return -EINVAL;
-
- return regmap_update_bits(clk_regmap, clk->reg, 0x1FFFF, val);
-}
-
-static int clk_hclk_pll_determine_rate(struct clk_hw *hw,
- struct clk_rate_request *req)
-{
- struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw);
- u64 m_i, o = req->rate, i = req->best_parent_rate, d = (u64)req->rate << 6;
- u64 m = 0, n = 0, p = 0;
- int p_i, n_i;
-
- pr_debug("%s: %lu/%lu\n", clk_hw_get_name(hw), req->best_parent_rate, req->rate);
-
- if (req->rate > 266500000)
- return -EINVAL;
-
- /* Have to check all 20 possibilities to find the minimal M */
- for (p_i = 4; p_i >= 0; p_i--) {
- for (n_i = 4; n_i > 0; n_i--) {
- m_i = div64_u64(o * n_i * (1 << p_i), i);
-
- /* Check for valid PLL parameter constraints */
- if (!(m_i && m_i <= 256
- && pll_is_valid(i, n_i, 1000000, 27000000)
- && pll_is_valid(i * m_i * (1 << p_i), n_i,
- 156000000, 320000000)))
- continue;
-
- /* Store some intermediate valid parameters */
- if (o * n_i * (1 << p_i) - i * m_i <= d) {
- m = m_i;
- n = n_i;
- p = p_i;
- d = o * n_i * (1 << p_i) - i * m_i;
- }
- }
- }
-
- if (d == (u64)req->rate << 6) {
- pr_err("%s: %lu: no valid PLL parameters are found\n",
- clk_hw_get_name(hw), req->rate);
- return -EINVAL;
- }
-
- clk->m_div = m;
- clk->n_div = n;
- clk->p_div = p;
-
- /* Set only direct or non-integer mode of PLL */
- if (!p)
- clk->mode = PLL_DIRECT;
- else
- clk->mode = PLL_NON_INTEGER;
-
- o = div64_u64(i * m, n * (1 << p));
-
- if (!d)
- pr_debug("%s: %lu: found exact match: %llu/%llu/%llu\n",
- clk_hw_get_name(hw), req->rate, m, n, p);
- else
- pr_debug("%s: %lu: found closest: %llu/%llu/%llu - %llu\n",
- clk_hw_get_name(hw), req->rate, m, n, p, o);
-
- req->rate = o;
-
- return 0;
-}
-
-static int clk_usb_pll_determine_rate(struct clk_hw *hw,
- struct clk_rate_request *req)
-{
- struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw);
- struct clk_hw *usb_div_hw, *osc_hw;
- u64 d_i, n_i, m, o;
-
- pr_debug("%s: %lu/%lu\n", clk_hw_get_name(hw), req->best_parent_rate,
- req->rate);
-
- /*
- * The only supported USB clock is 48MHz, with PLL internal constraints
- * on Fclkin, Fcco and Fref this implies that Fcco must be 192MHz
- * and post-divider must be 4, this slightly simplifies calculation of
- * USB divider, USB PLL N and M parameters.
- */
- if (req->rate != 48000000)
- return -EINVAL;
-
- /* USB divider clock */
- usb_div_hw = clk_hw_get_parent_by_index(hw, 0);
- if (!usb_div_hw)
- return -EINVAL;
-
- /* Main oscillator clock */
- osc_hw = clk_hw_get_parent_by_index(usb_div_hw, 0);
- if (!osc_hw)
- return -EINVAL;
- o = clk_hw_get_rate(osc_hw); /* must be in range 1..20 MHz */
-
- /* Check if valid USB divider and USB PLL parameters exists */
- for (d_i = 16; d_i >= 1; d_i--) {
- for (n_i = 1; n_i <= 4; n_i++) {
- m = div64_u64(192000000 * d_i * n_i, o);
- if (!(m && m <= 256
- && m * o == 192000000 * d_i * n_i
- && pll_is_valid(o, d_i, 1000000, 20000000)
- && pll_is_valid(o, d_i * n_i, 1000000, 27000000)))
- continue;
-
- clk->n_div = n_i;
- clk->m_div = m;
- clk->p_div = 2;
- clk->mode = PLL_NON_INTEGER;
- req->best_parent_rate = div64_u64(o, d_i);
-
- return 0;
- }
- }
-
- return -EINVAL;
-}
-
-#define LPC32XX_DEFINE_PLL_OPS(_name, _rc, _sr, _dr) \
- static const struct clk_ops clk_ ##_name ## _ops = { \
- .enable = clk_pll_enable, \
- .disable = clk_pll_disable, \
- .is_enabled = clk_pll_is_enabled, \
- .recalc_rate = _rc, \
- .set_rate = _sr, \
- .determine_rate = _dr, \
- }
-
-LPC32XX_DEFINE_PLL_OPS(pll_397x, clk_pll_397x_recalc_rate, NULL, NULL);
-LPC32XX_DEFINE_PLL_OPS(hclk_pll, clk_pll_recalc_rate,
- clk_pll_set_rate, clk_hclk_pll_determine_rate);
-LPC32XX_DEFINE_PLL_OPS(usb_pll, clk_pll_recalc_rate,
- clk_pll_set_rate, clk_usb_pll_determine_rate);
-
-static int clk_ddram_is_enabled(struct clk_hw *hw)
-{
- struct lpc32xx_clk *clk = to_lpc32xx_clk(hw);
- u32 val;
-
- regmap_read(clk_regmap, clk->reg, &val);
- val &= clk->enable_mask | clk->busy_mask;
-
- return (val == (BIT(7) | BIT(0)) ||
- val == (BIT(8) | BIT(1)));
-}
-
-static int clk_ddram_enable(struct clk_hw *hw)
-{
- struct lpc32xx_clk *clk = to_lpc32xx_clk(hw);
- u32 val, hclk_div;
-
- regmap_read(clk_regmap, clk->reg, &val);
- hclk_div = val & clk->busy_mask;
-
- /*
- * DDRAM clock must be 2 times higher than HCLK,
- * this implies DDRAM clock can not be enabled,
- * if HCLK clock rate is equal to ARM clock rate
- */
- if (hclk_div == 0x0 || hclk_div == (BIT(1) | BIT(0)))
- return -EINVAL;
-
- return regmap_update_bits(clk_regmap, clk->reg,
- clk->enable_mask, hclk_div << 7);
-}
-
-static unsigned long clk_ddram_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
-{
- struct lpc32xx_clk *clk = to_lpc32xx_clk(hw);
- u32 val;
-
- if (!clk_ddram_is_enabled(hw))
- return 0;
-
- regmap_read(clk_regmap, clk->reg, &val);
- val &= clk->enable_mask;
-
- return parent_rate / (val >> 7);
-}
-
-static const struct clk_ops clk_ddram_ops = {
- .enable = clk_ddram_enable,
- .disable = clk_mask_disable,
- .is_enabled = clk_ddram_is_enabled,
- .recalc_rate = clk_ddram_recalc_rate,
-};
-
-static unsigned long lpc32xx_clk_uart_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
-{
- struct lpc32xx_clk *clk = to_lpc32xx_clk(hw);
- u32 val, x, y;
-
- regmap_read(clk_regmap, clk->reg, &val);
- x = (val & 0xFF00) >> 8;
- y = val & 0xFF;
-
- if (x && y)
- return (parent_rate * x) / y;
- else
- return 0;
-}
-
-static const struct clk_ops lpc32xx_uart_div_ops = {
- .recalc_rate = lpc32xx_clk_uart_recalc_rate,
-};
-
-static const struct clk_div_table clk_hclk_div_table[] = {
- { .val = 0, .div = 1 },
- { .val = 1, .div = 2 },
- { .val = 2, .div = 4 },
- { },
-};
-
-static u32 test1_mux_table[] = { 0, 1, 2, };
-static u32 test2_mux_table[] = { 0, 1, 2, 5, 7, };
-
-static int clk_usb_enable(struct clk_hw *hw)
-{
- struct lpc32xx_usb_clk *clk = to_lpc32xx_usb_clk(hw);
- u32 val, ctrl_val, count;
-
- pr_debug("%s: 0x%x\n", clk_hw_get_name(hw), clk->enable);
-
- if (clk->ctrl_mask) {
- regmap_read(clk_regmap, LPC32XX_CLKPWR_USB_CTRL, &ctrl_val);
- regmap_update_bits(clk_regmap, LPC32XX_CLKPWR_USB_CTRL,
- clk->ctrl_mask, clk->ctrl_enable);
- }
-
- val = lpc32xx_usb_clk_read(clk);
- if (clk->busy && (val & clk->busy) == clk->busy) {
- if (clk->ctrl_mask)
- regmap_write(clk_regmap, LPC32XX_CLKPWR_USB_CTRL,
- ctrl_val);
- return -EBUSY;
- }
-
- val |= clk->enable;
- lpc32xx_usb_clk_write(clk, val);
-
- for (count = 0; count < 1000; count++) {
- val = lpc32xx_usb_clk_read(clk);
- if ((val & clk->enable) == clk->enable)
- break;
- }
-
- if ((val & clk->enable) == clk->enable)
- return 0;
-
- if (clk->ctrl_mask)
- regmap_write(clk_regmap, LPC32XX_CLKPWR_USB_CTRL, ctrl_val);
-
- return -ETIMEDOUT;
-}
-
-static void clk_usb_disable(struct clk_hw *hw)
-{
- struct lpc32xx_usb_clk *clk = to_lpc32xx_usb_clk(hw);
- u32 val = lpc32xx_usb_clk_read(clk);
-
- val &= ~clk->enable;
- lpc32xx_usb_clk_write(clk, val);
-
- if (clk->ctrl_mask)
- regmap_update_bits(clk_regmap, LPC32XX_CLKPWR_USB_CTRL,
- clk->ctrl_mask, clk->ctrl_disable);
-}
-
-static int clk_usb_is_enabled(struct clk_hw *hw)
-{
- struct lpc32xx_usb_clk *clk = to_lpc32xx_usb_clk(hw);
- u32 ctrl_val, val;
-
- if (clk->ctrl_mask) {
- regmap_read(clk_regmap, LPC32XX_CLKPWR_USB_CTRL, &ctrl_val);
- if ((ctrl_val & clk->ctrl_mask) != clk->ctrl_enable)
- return 0;
- }
-
- val = lpc32xx_usb_clk_read(clk);
-
- return ((val & clk->enable) == clk->enable);
-}
-
-static unsigned long clk_usb_i2c_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
-{
- return clk_get_rate(clk[LPC32XX_CLK_PERIPH]);
-}
-
-static const struct clk_ops clk_usb_ops = {
- .enable = clk_usb_enable,
- .disable = clk_usb_disable,
- .is_enabled = clk_usb_is_enabled,
-};
-
-static const struct clk_ops clk_usb_i2c_ops = {
- .enable = clk_usb_enable,
- .disable = clk_usb_disable,
- .is_enabled = clk_usb_is_enabled,
- .recalc_rate = clk_usb_i2c_recalc_rate,
-};
-
-static int lpc32xx_clk_gate_enable(struct clk_hw *hw)
-{
- struct lpc32xx_clk_gate *clk = to_lpc32xx_gate(hw);
- u32 mask = BIT(clk->bit_idx);
- u32 val = (clk->flags & CLK_GATE_SET_TO_DISABLE ? 0x0 : mask);
-
- return regmap_update_bits(clk_regmap, clk->reg, mask, val);
-}
-
-static void lpc32xx_clk_gate_disable(struct clk_hw *hw)
-{
- struct lpc32xx_clk_gate *clk = to_lpc32xx_gate(hw);
- u32 mask = BIT(clk->bit_idx);
- u32 val = (clk->flags & CLK_GATE_SET_TO_DISABLE ? mask : 0x0);
-
- regmap_update_bits(clk_regmap, clk->reg, mask, val);
-}
-
-static int lpc32xx_clk_gate_is_enabled(struct clk_hw *hw)
-{
- struct lpc32xx_clk_gate *clk = to_lpc32xx_gate(hw);
- u32 val;
- bool is_set;
-
- regmap_read(clk_regmap, clk->reg, &val);
- is_set = val & BIT(clk->bit_idx);
-
- return (clk->flags & CLK_GATE_SET_TO_DISABLE ? !is_set : is_set);
-}
-
-static const struct clk_ops lpc32xx_clk_gate_ops = {
- .enable = lpc32xx_clk_gate_enable,
- .disable = lpc32xx_clk_gate_disable,
- .is_enabled = lpc32xx_clk_gate_is_enabled,
-};
-
-#define div_mask(width) ((1 << (width)) - 1)
-
-static unsigned int _get_table_div(const struct clk_div_table *table,
- unsigned int val)
-{
- const struct clk_div_table *clkt;
-
- for (clkt = table; clkt->div; clkt++)
- if (clkt->val == val)
- return clkt->div;
- return 0;
-}
-
-static unsigned int _get_div(const struct clk_div_table *table,
- unsigned int val, unsigned long flags, u8 width)
-{
- if (flags & CLK_DIVIDER_ONE_BASED)
- return val;
- if (table)
- return _get_table_div(table, val);
- return val + 1;
-}
-
-static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
-{
- struct lpc32xx_clk_div *divider = to_lpc32xx_div(hw);
- unsigned int val;
-
- regmap_read(clk_regmap, divider->reg, &val);
-
- val >>= divider->shift;
- val &= div_mask(divider->width);
-
- return divider_recalc_rate(hw, parent_rate, val, divider->table,
- divider->flags, divider->width);
-}
-
-static int clk_divider_determine_rate(struct clk_hw *hw,
- struct clk_rate_request *req)
-{
- struct lpc32xx_clk_div *divider = to_lpc32xx_div(hw);
- unsigned int bestdiv;
-
- /* if read only, just return current value */
- if (divider->flags & CLK_DIVIDER_READ_ONLY) {
- regmap_read(clk_regmap, divider->reg, &bestdiv);
- bestdiv >>= divider->shift;
- bestdiv &= div_mask(divider->width);
- bestdiv = _get_div(divider->table, bestdiv, divider->flags,
- divider->width);
- req->rate = DIV_ROUND_UP(req->best_parent_rate, bestdiv);
-
- return 0;
- }
-
- return divider_determine_rate(hw, req, divider->table, divider->width,
- divider->flags);
-}
-
-static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long parent_rate)
-{
- struct lpc32xx_clk_div *divider = to_lpc32xx_div(hw);
- unsigned int value;
-
- value = divider_get_val(rate, parent_rate, divider->table,
- divider->width, divider->flags);
-
- return regmap_update_bits(clk_regmap, divider->reg,
- div_mask(divider->width) << divider->shift,
- value << divider->shift);
-}
-
-static const struct clk_ops lpc32xx_clk_divider_ops = {
- .recalc_rate = clk_divider_recalc_rate,
- .determine_rate = clk_divider_determine_rate,
- .set_rate = clk_divider_set_rate,
-};
-
-static u8 clk_mux_get_parent(struct clk_hw *hw)
-{
- struct lpc32xx_clk_mux *mux = to_lpc32xx_mux(hw);
- u32 num_parents = clk_hw_get_num_parents(hw);
- u32 val;
-
- regmap_read(clk_regmap, mux->reg, &val);
- val >>= mux->shift;
- val &= mux->mask;
-
- if (mux->table) {
- u32 i;
-
- for (i = 0; i < num_parents; i++)
- if (mux->table[i] == val)
- return i;
- return -EINVAL;
- }
-
- if (val >= num_parents)
- return -EINVAL;
-
- return val;
-}
-
-static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
-{
- struct lpc32xx_clk_mux *mux = to_lpc32xx_mux(hw);
-
- if (mux->table)
- index = mux->table[index];
-
- return regmap_update_bits(clk_regmap, mux->reg,
- mux->mask << mux->shift, index << mux->shift);
-}
-
-static const struct clk_ops lpc32xx_clk_mux_ro_ops = {
- .get_parent = clk_mux_get_parent,
-};
-
-static const struct clk_ops lpc32xx_clk_mux_ops = {
- .get_parent = clk_mux_get_parent,
- .set_parent = clk_mux_set_parent,
- .determine_rate = __clk_mux_determine_rate,
-};
-
-enum lpc32xx_clk_type {
- CLK_FIXED,
- CLK_MUX,
- CLK_DIV,
- CLK_GATE,
- CLK_COMPOSITE,
- CLK_LPC32XX,
- CLK_LPC32XX_PLL,
- CLK_LPC32XX_USB,
-};
-
-struct clk_hw_proto0 {
- const struct clk_ops *ops;
- union {
- struct lpc32xx_pll_clk pll;
- struct lpc32xx_clk clk;
- struct lpc32xx_usb_clk usb_clk;
- struct lpc32xx_clk_mux mux;
- struct lpc32xx_clk_div div;
- struct lpc32xx_clk_gate gate;
- };
-};
-
-struct clk_hw_proto1 {
- struct clk_hw_proto0 *mux;
- struct clk_hw_proto0 *div;
- struct clk_hw_proto0 *gate;
-};
-
-struct clk_hw_proto {
- enum lpc32xx_clk_type type;
-
- union {
- struct clk_fixed_rate f;
- struct clk_hw_proto0 hw0;
- struct clk_hw_proto1 hw1;
- };
-};
-
-#define LPC32XX_DEFINE_FIXED(_idx, _rate) \
-[CLK_PREFIX(_idx)] = { \
- .type = CLK_FIXED, \
- { \
- .f = { \
- .fixed_rate = (_rate), \
- }, \
- }, \
-}
-
-#define LPC32XX_DEFINE_PLL(_idx, _name, _reg, _enable) \
-[CLK_PREFIX(_idx)] = { \
- .type = CLK_LPC32XX_PLL, \
- { \
- .hw0 = { \
- .ops = &clk_ ##_name ## _ops, \
- { \
- .pll = { \
- .reg = LPC32XX_CLKPWR_ ## _reg, \
- .enable = (_enable), \
- }, \
- }, \
- }, \
- }, \
-}
-
-#define LPC32XX_DEFINE_MUX(_idx, _reg, _shift, _mask, _table, _flags) \
-[CLK_PREFIX(_idx)] = { \
- .type = CLK_MUX, \
- { \
- .hw0 = { \
- .ops = (_flags & CLK_MUX_READ_ONLY ? \
- &lpc32xx_clk_mux_ro_ops : \
- &lpc32xx_clk_mux_ops), \
- { \
- .mux = { \
- .reg = LPC32XX_CLKPWR_ ## _reg, \
- .mask = (_mask), \
- .shift = (_shift), \
- .table = (_table), \
- .flags = (_flags), \
- }, \
- }, \
- }, \
- }, \
-}
-
-#define LPC32XX_DEFINE_DIV(_idx, _reg, _shift, _width, _table, _flags) \
-[CLK_PREFIX(_idx)] = { \
- .type = CLK_DIV, \
- { \
- .hw0 = { \
- .ops = &lpc32xx_clk_divider_ops, \
- { \
- .div = { \
- .reg = LPC32XX_CLKPWR_ ## _reg, \
- .shift = (_shift), \
- .width = (_width), \
- .table = (_table), \
- .flags = (_flags), \
- }, \
- }, \
- }, \
- }, \
-}
-
-#define LPC32XX_DEFINE_GATE(_idx, _reg, _bit, _flags) \
-[CLK_PREFIX(_idx)] = { \
- .type = CLK_GATE, \
- { \
- .hw0 = { \
- .ops = &lpc32xx_clk_gate_ops, \
- { \
- .gate = { \
- .reg = LPC32XX_CLKPWR_ ## _reg, \
- .bit_idx = (_bit), \
- .flags = (_flags), \
- }, \
- }, \
- }, \
- }, \
-}
-
-#define LPC32XX_DEFINE_CLK(_idx, _reg, _e, _em, _d, _dm, _b, _bm, _ops) \
-[CLK_PREFIX(_idx)] = { \
- .type = CLK_LPC32XX, \
- { \
- .hw0 = { \
- .ops = &(_ops), \
- { \
- .clk = { \
- .reg = LPC32XX_CLKPWR_ ## _reg, \
- .enable = (_e), \
- .enable_mask = (_em), \
- .disable = (_d), \
- .disable_mask = (_dm), \
- .busy = (_b), \
- .busy_mask = (_bm), \
- }, \
- }, \
- }, \
- }, \
-}
-
-#define LPC32XX_DEFINE_USB(_idx, _ce, _cd, _cm, _e, _b, _ops) \
-[CLK_PREFIX(_idx)] = { \
- .type = CLK_LPC32XX_USB, \
- { \
- .hw0 = { \
- .ops = &(_ops), \
- { \
- .usb_clk = { \
- .ctrl_enable = (_ce), \
- .ctrl_disable = (_cd), \
- .ctrl_mask = (_cm), \
- .enable = (_e), \
- .busy = (_b), \
- } \
- }, \
- } \
- }, \
-}
-
-#define LPC32XX_DEFINE_COMPOSITE(_idx, _mux, _div, _gate) \
-[CLK_PREFIX(_idx)] = { \
- .type = CLK_COMPOSITE, \
- { \
- .hw1 = { \
- .mux = (CLK_PREFIX(_mux) == LPC32XX_CLK__NULL ? NULL : \
- &clk_hw_proto[CLK_PREFIX(_mux)].hw0), \
- .div = (CLK_PREFIX(_div) == LPC32XX_CLK__NULL ? NULL : \
- &clk_hw_proto[CLK_PREFIX(_div)].hw0), \
- .gate = (CLK_PREFIX(_gate) == LPC32XX_CLK__NULL ? NULL :\
- &clk_hw_proto[CLK_PREFIX(_gate)].hw0), \
- }, \
- }, \
-}
-
-static struct clk_hw_proto clk_hw_proto[LPC32XX_CLK_HW_MAX] = {
- LPC32XX_DEFINE_FIXED(RTC, 32768),
- LPC32XX_DEFINE_PLL(PLL397X, pll_397x, HCLKPLL_CTRL, BIT(1)),
- LPC32XX_DEFINE_PLL(HCLK_PLL, hclk_pll, HCLKPLL_CTRL, PLL_CTRL_ENABLE),
- LPC32XX_DEFINE_PLL(USB_PLL, usb_pll, USB_CTRL, PLL_CTRL_ENABLE),
- LPC32XX_DEFINE_GATE(OSC, OSC_CTRL, 0, CLK_GATE_SET_TO_DISABLE),
- LPC32XX_DEFINE_GATE(USB, USB_CTRL, 18, 0),
-
- LPC32XX_DEFINE_DIV(HCLK_DIV_PERIPH, HCLKDIV_CTRL, 2, 5, NULL,
- CLK_DIVIDER_READ_ONLY),
- LPC32XX_DEFINE_DIV(HCLK_DIV, HCLKDIV_CTRL, 0, 2, clk_hclk_div_table,
- CLK_DIVIDER_READ_ONLY),
-
- /* Register 3 read-only muxes with a single control PWR_CTRL[2] */
- LPC32XX_DEFINE_MUX(SYSCLK_PERIPH_MUX, PWR_CTRL, 2, 0x1, NULL,
- CLK_MUX_READ_ONLY),
- LPC32XX_DEFINE_MUX(SYSCLK_HCLK_MUX, PWR_CTRL, 2, 0x1, NULL,
- CLK_MUX_READ_ONLY),
- LPC32XX_DEFINE_MUX(SYSCLK_ARM_MUX, PWR_CTRL, 2, 0x1, NULL,
- CLK_MUX_READ_ONLY),
- /* Register 2 read-only muxes with a single control PWR_CTRL[10] */
- LPC32XX_DEFINE_MUX(PERIPH_HCLK_MUX, PWR_CTRL, 10, 0x1, NULL,
- CLK_MUX_READ_ONLY),
- LPC32XX_DEFINE_MUX(PERIPH_ARM_MUX, PWR_CTRL, 10, 0x1, NULL,
- CLK_MUX_READ_ONLY),
-
- /* 3 always on gates with a single control PWR_CTRL[0] same as OSC */
- LPC32XX_DEFINE_GATE(PERIPH, PWR_CTRL, 0, CLK_GATE_SET_TO_DISABLE),
- LPC32XX_DEFINE_GATE(HCLK, PWR_CTRL, 0, CLK_GATE_SET_TO_DISABLE),
- LPC32XX_DEFINE_GATE(ARM, PWR_CTRL, 0, CLK_GATE_SET_TO_DISABLE),
-
- LPC32XX_DEFINE_GATE(ARM_VFP, DEBUG_CTRL, 4, 0),
- LPC32XX_DEFINE_GATE(DMA, DMA_CLK_CTRL, 0, 0),
- LPC32XX_DEFINE_CLK(DDRAM, HCLKDIV_CTRL, 0x0, BIT(8) | BIT(7),
- 0x0, BIT(8) | BIT(7), 0x0, BIT(1) | BIT(0), clk_ddram_ops),
-
- LPC32XX_DEFINE_GATE(TIMER0, TIMCLK_CTRL1, 2, 0),
- LPC32XX_DEFINE_GATE(TIMER1, TIMCLK_CTRL1, 3, 0),
- LPC32XX_DEFINE_GATE(TIMER2, TIMCLK_CTRL1, 4, 0),
- LPC32XX_DEFINE_GATE(TIMER3, TIMCLK_CTRL1, 5, 0),
- LPC32XX_DEFINE_GATE(TIMER4, TIMCLK_CTRL1, 0, 0),
- LPC32XX_DEFINE_GATE(TIMER5, TIMCLK_CTRL1, 1, 0),
-
- LPC32XX_DEFINE_GATE(SSP0, SSP_CTRL, 0, 0),
- LPC32XX_DEFINE_GATE(SSP1, SSP_CTRL, 1, 0),
- LPC32XX_DEFINE_GATE(SPI1, SPI_CTRL, 0, 0),
- LPC32XX_DEFINE_GATE(SPI2, SPI_CTRL, 4, 0),
- LPC32XX_DEFINE_GATE(I2S0, I2S_CTRL, 0, 0),
- LPC32XX_DEFINE_GATE(I2S1, I2S_CTRL, 1, 0),
- LPC32XX_DEFINE_GATE(I2C1, I2CCLK_CTRL, 0, 0),
- LPC32XX_DEFINE_GATE(I2C2, I2CCLK_CTRL, 1, 0),
- LPC32XX_DEFINE_GATE(WDOG, TIMCLK_CTRL, 0, 0),
- LPC32XX_DEFINE_GATE(HSTIMER, TIMCLK_CTRL, 1, 0),
-
- LPC32XX_DEFINE_GATE(KEY, KEYCLK_CTRL, 0, 0),
- LPC32XX_DEFINE_GATE(MCPWM, TIMCLK_CTRL1, 6, 0),
-
- LPC32XX_DEFINE_MUX(PWM1_MUX, PWMCLK_CTRL, 1, 0x1, NULL, 0),
- LPC32XX_DEFINE_DIV(PWM1_DIV, PWMCLK_CTRL, 4, 4, NULL,
- CLK_DIVIDER_ONE_BASED),
- LPC32XX_DEFINE_GATE(PWM1_GATE, PWMCLK_CTRL, 0, 0),
- LPC32XX_DEFINE_COMPOSITE(PWM1, PWM1_MUX, PWM1_DIV, PWM1_GATE),
-
- LPC32XX_DEFINE_MUX(PWM2_MUX, PWMCLK_CTRL, 3, 0x1, NULL, 0),
- LPC32XX_DEFINE_DIV(PWM2_DIV, PWMCLK_CTRL, 8, 4, NULL,
- CLK_DIVIDER_ONE_BASED),
- LPC32XX_DEFINE_GATE(PWM2_GATE, PWMCLK_CTRL, 2, 0),
- LPC32XX_DEFINE_COMPOSITE(PWM2, PWM2_MUX, PWM2_DIV, PWM2_GATE),
-
- LPC32XX_DEFINE_MUX(UART3_MUX, UART3_CLK_CTRL, 16, 0x1, NULL, 0),
- LPC32XX_DEFINE_CLK(UART3_DIV, UART3_CLK_CTRL,
- 0, 0, 0, 0, 0, 0, lpc32xx_uart_div_ops),
- LPC32XX_DEFINE_GATE(UART3_GATE, UART_CLK_CTRL, 0, 0),
- LPC32XX_DEFINE_COMPOSITE(UART3, UART3_MUX, UART3_DIV, UART3_GATE),
-
- LPC32XX_DEFINE_MUX(UART4_MUX, UART4_CLK_CTRL, 16, 0x1, NULL, 0),
- LPC32XX_DEFINE_CLK(UART4_DIV, UART4_CLK_CTRL,
- 0, 0, 0, 0, 0, 0, lpc32xx_uart_div_ops),
- LPC32XX_DEFINE_GATE(UART4_GATE, UART_CLK_CTRL, 1, 0),
- LPC32XX_DEFINE_COMPOSITE(UART4, UART4_MUX, UART4_DIV, UART4_GATE),
-
- LPC32XX_DEFINE_MUX(UART5_MUX, UART5_CLK_CTRL, 16, 0x1, NULL, 0),
- LPC32XX_DEFINE_CLK(UART5_DIV, UART5_CLK_CTRL,
- 0, 0, 0, 0, 0, 0, lpc32xx_uart_div_ops),
- LPC32XX_DEFINE_GATE(UART5_GATE, UART_CLK_CTRL, 2, 0),
- LPC32XX_DEFINE_COMPOSITE(UART5, UART5_MUX, UART5_DIV, UART5_GATE),
-
- LPC32XX_DEFINE_MUX(UART6_MUX, UART6_CLK_CTRL, 16, 0x1, NULL, 0),
- LPC32XX_DEFINE_CLK(UART6_DIV, UART6_CLK_CTRL,
- 0, 0, 0, 0, 0, 0, lpc32xx_uart_div_ops),
- LPC32XX_DEFINE_GATE(UART6_GATE, UART_CLK_CTRL, 3, 0),
- LPC32XX_DEFINE_COMPOSITE(UART6, UART6_MUX, UART6_DIV, UART6_GATE),
-
- LPC32XX_DEFINE_CLK(IRDA, IRDA_CLK_CTRL,
- 0, 0, 0, 0, 0, 0, lpc32xx_uart_div_ops),
-
- LPC32XX_DEFINE_MUX(TEST1_MUX, TEST_CLK_CTRL, 5, 0x3,
- test1_mux_table, 0),
- LPC32XX_DEFINE_GATE(TEST1_GATE, TEST_CLK_CTRL, 4, 0),
- LPC32XX_DEFINE_COMPOSITE(TEST1, TEST1_MUX, _NULL, TEST1_GATE),
-
- LPC32XX_DEFINE_MUX(TEST2_MUX, TEST_CLK_CTRL, 1, 0x7,
- test2_mux_table, 0),
- LPC32XX_DEFINE_GATE(TEST2_GATE, TEST_CLK_CTRL, 0, 0),
- LPC32XX_DEFINE_COMPOSITE(TEST2, TEST2_MUX, _NULL, TEST2_GATE),
-
- LPC32XX_DEFINE_MUX(SYS, SYSCLK_CTRL, 0, 0x1, NULL, CLK_MUX_READ_ONLY),
-
- LPC32XX_DEFINE_DIV(USB_DIV_DIV, USB_DIV, 0, 4, NULL, 0),
- LPC32XX_DEFINE_GATE(USB_DIV_GATE, USB_CTRL, 17, 0),
- LPC32XX_DEFINE_COMPOSITE(USB_DIV, _NULL, USB_DIV_DIV, USB_DIV_GATE),
-
- LPC32XX_DEFINE_DIV(SD_DIV, MS_CTRL, 0, 4, NULL, CLK_DIVIDER_ONE_BASED),
- LPC32XX_DEFINE_CLK(SD_GATE, MS_CTRL, BIT(5) | BIT(9), BIT(5) | BIT(9),
- 0x0, BIT(5) | BIT(9), 0x0, 0x0, clk_mask_ops),
- LPC32XX_DEFINE_COMPOSITE(SD, _NULL, SD_DIV, SD_GATE),
-
- LPC32XX_DEFINE_DIV(LCD_DIV, LCDCLK_CTRL, 0, 5, NULL, 0),
- LPC32XX_DEFINE_GATE(LCD_GATE, LCDCLK_CTRL, 5, 0),
- LPC32XX_DEFINE_COMPOSITE(LCD, _NULL, LCD_DIV, LCD_GATE),
-
- LPC32XX_DEFINE_CLK(MAC, MACCLK_CTRL,
- BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(1) | BIT(0),
- BIT(2) | BIT(1) | BIT(0), BIT(2) | BIT(1) | BIT(0),
- 0x0, 0x0, clk_mask_ops),
- LPC32XX_DEFINE_CLK(SLC, FLASHCLK_CTRL,
- BIT(2) | BIT(0), BIT(2) | BIT(0), 0x0,
- BIT(0), BIT(1), BIT(2) | BIT(1), clk_mask_ops),
- LPC32XX_DEFINE_CLK(MLC, FLASHCLK_CTRL,
- BIT(1), BIT(2) | BIT(1), 0x0, BIT(1),
- BIT(2) | BIT(0), BIT(2) | BIT(0), clk_mask_ops),
- /*
- * ADC/TS clock unfortunately cannot be registered as a composite one
- * due to a different connection of gate, div and mux, e.g. gating it
- * won't mean that the clock is off, if peripheral clock is its parent:
- *
- * rtc-->[gate]-->| |
- * | mux |--> adc/ts
- * pclk-->[div]-->| |
- *
- * Constraints:
- * ADC --- resulting clock must be <= 4.5 MHz
- * TS --- resulting clock must be <= 400 KHz
- */
- LPC32XX_DEFINE_DIV(ADC_DIV, ADCCLK_CTRL1, 0, 8, NULL, 0),
- LPC32XX_DEFINE_GATE(ADC_RTC, ADCCLK_CTRL, 0, 0),
- LPC32XX_DEFINE_MUX(ADC, ADCCLK_CTRL1, 8, 0x1, NULL, 0),
-
- /* USB controller clocks */
- LPC32XX_DEFINE_USB(USB_AHB,
- BIT(24), 0x0, BIT(24), BIT(4), 0, clk_usb_ops),
- LPC32XX_DEFINE_USB(USB_OTG,
- 0x0, 0x0, 0x0, BIT(3), 0, clk_usb_ops),
- LPC32XX_DEFINE_USB(USB_I2C,
- 0x0, BIT(23), BIT(23), BIT(2), 0, clk_usb_i2c_ops),
- LPC32XX_DEFINE_USB(USB_DEV,
- BIT(22), 0x0, BIT(22), BIT(1), BIT(0), clk_usb_ops),
- LPC32XX_DEFINE_USB(USB_HOST,
- BIT(21), 0x0, BIT(21), BIT(0), BIT(1), clk_usb_ops),
-};
-
-static struct clk * __init lpc32xx_clk_register(u32 id)
-{
- const struct clk_proto_t *lpc32xx_clk = &clk_proto[id];
- struct clk_hw_proto *clk_hw = &clk_hw_proto[id];
- const char *parents[LPC32XX_CLK_PARENTS_MAX];
- struct clk *clk;
- unsigned int i;
-
- for (i = 0; i < lpc32xx_clk->num_parents; i++)
- parents[i] = clk_proto[lpc32xx_clk->parents[i]].name;
-
- pr_debug("%s: derived from '%s', clock type %d\n", lpc32xx_clk->name,
- parents[0], clk_hw->type);
-
- switch (clk_hw->type) {
- case CLK_LPC32XX:
- case CLK_LPC32XX_PLL:
- case CLK_LPC32XX_USB:
- case CLK_MUX:
- case CLK_DIV:
- case CLK_GATE:
- {
- struct clk_init_data clk_init = {
- .name = lpc32xx_clk->name,
- .parent_names = parents,
- .num_parents = lpc32xx_clk->num_parents,
- .flags = lpc32xx_clk->flags,
- .ops = clk_hw->hw0.ops,
- };
- struct clk_hw *hw;
-
- if (clk_hw->type == CLK_LPC32XX)
- hw = &clk_hw->hw0.clk.hw;
- else if (clk_hw->type == CLK_LPC32XX_PLL)
- hw = &clk_hw->hw0.pll.hw;
- else if (clk_hw->type == CLK_LPC32XX_USB)
- hw = &clk_hw->hw0.usb_clk.hw;
- else if (clk_hw->type == CLK_MUX)
- hw = &clk_hw->hw0.mux.hw;
- else if (clk_hw->type == CLK_DIV)
- hw = &clk_hw->hw0.div.hw;
- else if (clk_hw->type == CLK_GATE)
- hw = &clk_hw->hw0.gate.hw;
- else
- return ERR_PTR(-EINVAL);
-
- hw->init = &clk_init;
- clk = clk_register(NULL, hw);
- break;
- }
- case CLK_COMPOSITE:
- {
- struct clk_hw *mux_hw = NULL, *div_hw = NULL, *gate_hw = NULL;
- const struct clk_ops *mops = NULL, *dops = NULL, *gops = NULL;
- struct clk_hw_proto0 *mux0, *div0, *gate0;
-
- mux0 = clk_hw->hw1.mux;
- div0 = clk_hw->hw1.div;
- gate0 = clk_hw->hw1.gate;
- if (mux0) {
- mops = mux0->ops;
- mux_hw = &mux0->clk.hw;
- }
- if (div0) {
- dops = div0->ops;
- div_hw = &div0->clk.hw;
- }
- if (gate0) {
- gops = gate0->ops;
- gate_hw = &gate0->clk.hw;
- }
-
- clk = clk_register_composite(NULL, lpc32xx_clk->name,
- parents, lpc32xx_clk->num_parents,
- mux_hw, mops, div_hw, dops,
- gate_hw, gops, lpc32xx_clk->flags);
- break;
- }
- case CLK_FIXED:
- {
- struct clk_fixed_rate *fixed = &clk_hw->f;
-
- clk = clk_register_fixed_rate(NULL, lpc32xx_clk->name,
- parents[0], 0, fixed->fixed_rate);
- break;
- }
- default:
- clk = ERR_PTR(-EINVAL);
- }
-
- return clk;
-}
-
-static void __init lpc32xx_clk_div_quirk(u32 reg, u32 div_mask, u32 gate)
-{
- u32 val;
-
- regmap_read(clk_regmap, reg, &val);
-
- if (!(val & div_mask)) {
- val &= ~gate;
- val |= BIT(__ffs(div_mask));
- }
-
- regmap_update_bits(clk_regmap, reg, gate | div_mask, val);
-}
-
-static void __init lpc32xx_clk_init(struct device_node *np)
-{
- unsigned int i;
- struct clk *clk_osc, *clk_32k;
- void __iomem *base = NULL;
-
- /* Ensure that parent clocks are available and valid */
- clk_32k = of_clk_get_by_name(np, clk_proto[LPC32XX_CLK_XTAL_32K].name);
- if (IS_ERR(clk_32k)) {
- pr_err("failed to find external 32KHz clock: %ld\n",
- PTR_ERR(clk_32k));
- return;
- }
- if (clk_get_rate(clk_32k) != 32768) {
- pr_err("invalid clock rate of external 32KHz oscillator\n");
- return;
- }
-
- clk_osc = of_clk_get_by_name(np, clk_proto[LPC32XX_CLK_XTAL].name);
- if (IS_ERR(clk_osc)) {
- pr_err("failed to find external main oscillator clock: %ld\n",
- PTR_ERR(clk_osc));
- return;
- }
-
- base = of_iomap(np, 0);
- if (!base) {
- pr_err("failed to map system control block registers\n");
- return;
- }
-
- clk_regmap = regmap_init_mmio(NULL, base, &lpc32xx_scb_regmap_config);
- if (IS_ERR(clk_regmap)) {
- pr_err("failed to regmap system control block: %ld\n",
- PTR_ERR(clk_regmap));
- iounmap(base);
- return;
- }
-
- /*
- * Divider part of PWM and MS clocks requires a quirk to avoid
- * a misinterpretation of formally valid zero value in register
- * bitfield, which indicates another clock gate. Instead of
- * adding complexity to a gate clock ensure that zero value in
- * divider clock is never met in runtime.
- */
- lpc32xx_clk_div_quirk(LPC32XX_CLKPWR_PWMCLK_CTRL, 0xf0, BIT(0));
- lpc32xx_clk_div_quirk(LPC32XX_CLKPWR_PWMCLK_CTRL, 0xf00, BIT(2));
- lpc32xx_clk_div_quirk(LPC32XX_CLKPWR_MS_CTRL, 0xf, BIT(5) | BIT(9));
-
- for (i = 1; i < LPC32XX_CLK_MAX; i++) {
- clk[i] = lpc32xx_clk_register(i);
- if (IS_ERR(clk[i])) {
- pr_err("failed to register %s clock: %ld\n",
- clk_proto[i].name, PTR_ERR(clk[i]));
- clk[i] = NULL;
- }
- }
-
- of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
-
- /* Set 48MHz rate of USB PLL clock */
- clk_set_rate(clk[LPC32XX_CLK_USB_PLL], 48000000);
-
- /* These two clocks must be always on independently on consumers */
- clk_prepare_enable(clk[LPC32XX_CLK_ARM]);
- clk_prepare_enable(clk[LPC32XX_CLK_HCLK]);
-
- /* Enable ARM VFP by default */
- clk_prepare_enable(clk[LPC32XX_CLK_ARM_VFP]);
-
- /* Disable enabled by default clocks for NAND MLC and SLC */
- clk_mask_disable(&clk_hw_proto[LPC32XX_CLK_SLC].hw0.clk.hw);
- clk_mask_disable(&clk_hw_proto[LPC32XX_CLK_MLC].hw0.clk.hw);
-}
-CLK_OF_DECLARE(lpc32xx_clk, "nxp,lpc3220-clk", lpc32xx_clk_init);
-
-static void __init lpc32xx_usb_clk_init(struct device_node *np)
-{
- unsigned int i;
-
- usb_clk_vbase = of_iomap(np, 0);
- if (!usb_clk_vbase) {
- pr_err("failed to map address range\n");
- return;
- }
-
- for (i = 1; i < LPC32XX_USB_CLK_MAX; i++) {
- usb_clk[i] = lpc32xx_clk_register(i + LPC32XX_CLK_USB_OFFSET);
- if (IS_ERR(usb_clk[i])) {
- pr_err("failed to register %s clock: %ld\n",
- clk_proto[i].name, PTR_ERR(usb_clk[i]));
- usb_clk[i] = NULL;
- }
- }
-
- of_clk_add_provider(np, of_clk_src_onecell_get, &usb_clk_data);
-}
-CLK_OF_DECLARE(lpc32xx_usb_clk, "nxp,lpc3220-usb-clk", lpc32xx_usb_clk_init);
--
2.43.0
^ permalink raw reply related
* [PATCH 11/11] pinctrl: nxp: lpc: Remove NOMMU platform support
From: Frank.Li @ 2026-06-19 15:41 UTC (permalink / raw)
To: Arnd Bergmann, Sascha Hauer, Pengutronix Kernel Team,
Stefan Agner, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Russell King, Abel Vesa, Peng Fan,
Michael Turquette, Stephen Boyd, Brian Masney, Dong Aisheng,
Jacky Bai, NXP S32 Linux Team, Linus Walleij, Vladimir Zapolskiy,
Piotr Wojtaszczyk, Kees Cook, Gustavo A. R. Silva
Cc: linux-arm-kernel, imx, devicetree, linux-kernel, linux-clk,
linux-gpio, linux-hardening, Frank Li
In-Reply-To: <20260619-dts_cleanup_arm_mcore-v1-0-0101795a2662@nxp.com>
From: Frank Li <Frank.Li@nxp.com>
Commercial users and hardware vendors migrated to Zephyr or other RTOS
solutions years ago, leaving the NOMMU platform support effectively
unused and unmaintained.
Remove the obsolete support to reduce maintenance burden and simplify the
NXP/Freescale platform code.
The pinctrl driver is highly SoC-specific and provides little opportunity
for reuse on future hardware
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
drivers/pinctrl/Kconfig | 9 -
drivers/pinctrl/Makefile | 1 -
drivers/pinctrl/pinctrl-lpc18xx.c | 1382 -------------------------------------
3 files changed, 1392 deletions(-)
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index c2cdd7b2c49b0..35a379570becd 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -364,15 +364,6 @@ config PINCTRL_XWAY
depends on SOC_TYPE_XWAY
depends on PINCTRL_LANTIQ
-config PINCTRL_LPC18XX
- bool "NXP LPC18XX/43XX SCU pinctrl driver"
- depends on OF && (ARCH_LPC18XX || COMPILE_TEST)
- default ARCH_LPC18XX
- select PINMUX
- select GENERIC_PINCONF
- help
- Pinctrl driver for NXP LPC18xx/43xx System Control Unit (SCU).
-
config PINCTRL_MAX7360
tristate "MAX7360 Pincontrol support"
depends on MFD_MAX7360
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index a35d71135abfb..2176baf2ec3fc 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -38,7 +38,6 @@ obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o
obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o
obj-$(CONFIG_PINCTRL_LOONGSON2) += pinctrl-loongson2.o
obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o
-obj-$(CONFIG_PINCTRL_LPC18XX) += pinctrl-lpc18xx.o
obj-$(CONFIG_PINCTRL_MAX7360) += pinctrl-max7360.o
obj-$(CONFIG_PINCTRL_MAX77620) += pinctrl-max77620.o
obj-$(CONFIG_PINCTRL_MCP23S08_I2C) += pinctrl-mcp23s08_i2c.o
diff --git a/drivers/pinctrl/pinctrl-lpc18xx.c b/drivers/pinctrl/pinctrl-lpc18xx.c
deleted file mode 100644
index 5e02017683235..0000000000000
--- a/drivers/pinctrl/pinctrl-lpc18xx.c
+++ /dev/null
@@ -1,1382 +0,0 @@
-/*
- * Pinctrl driver for NXP LPC18xx/LPC43xx System Control Unit (SCU)
- *
- * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/bitops.h>
-#include <linux/clk.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/mod_devicetable.h>
-#include <linux/platform_device.h>
-
-#include <linux/pinctrl/pinconf-generic.h>
-#include <linux/pinctrl/pinconf.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/pinctrl/pinmux.h>
-
-#include "core.h"
-#include "pinctrl-utils.h"
-
-/* LPC18XX SCU analog function registers */
-#define LPC18XX_SCU_REG_ENAIO0 0xc88
-#define LPC18XX_SCU_REG_ENAIO1 0xc8c
-#define LPC18XX_SCU_REG_ENAIO2 0xc90
-#define LPC18XX_SCU_REG_ENAIO2_DAC BIT(0)
-
-/* LPC18XX SCU pin register definitions */
-#define LPC18XX_SCU_PIN_MODE_MASK 0x7
-#define LPC18XX_SCU_PIN_EPD BIT(3)
-#define LPC18XX_SCU_PIN_EPUN BIT(4)
-#define LPC18XX_SCU_PIN_EHS BIT(5)
-#define LPC18XX_SCU_PIN_EZI BIT(6)
-#define LPC18XX_SCU_PIN_ZIF BIT(7)
-#define LPC18XX_SCU_PIN_EHD_MASK 0x300
-#define LPC18XX_SCU_PIN_EHD_POS 8
-
-#define LPC18XX_SCU_USB1_EPD BIT(2)
-#define LPC18XX_SCU_USB1_EPWR BIT(4)
-
-#define LPC18XX_SCU_I2C0_EFP BIT(0)
-#define LPC18XX_SCU_I2C0_EHD BIT(2)
-#define LPC18XX_SCU_I2C0_EZI BIT(3)
-#define LPC18XX_SCU_I2C0_ZIF BIT(7)
-#define LPC18XX_SCU_I2C0_SCL_SHIFT 0
-#define LPC18XX_SCU_I2C0_SDA_SHIFT 8
-
-#define LPC18XX_SCU_FUNC_PER_PIN 8
-
-/* LPC18XX SCU pin interrupt select registers */
-#define LPC18XX_SCU_PINTSEL0 0xe00
-#define LPC18XX_SCU_PINTSEL1 0xe04
-#define LPC18XX_SCU_PINTSEL_VAL_MASK 0xff
-#define LPC18XX_SCU_PINTSEL_PORT_SHIFT 5
-#define LPC18XX_SCU_IRQ_PER_PINTSEL 4
-#define LPC18XX_GPIO_PINS_PER_PORT 32
-#define LPC18XX_GPIO_PIN_INT_MAX 8
-
-#define LPC18XX_SCU_PINTSEL_VAL(val, n) \
- ((val) << (((n) % LPC18XX_SCU_IRQ_PER_PINTSEL) * 8))
-
-/* LPC18xx pin types */
-enum {
- TYPE_ND, /* Normal-drive */
- TYPE_HD, /* High-drive */
- TYPE_HS, /* High-speed */
- TYPE_I2C0,
- TYPE_USB1,
-};
-
-/* LPC18xx pin functions */
-enum {
- FUNC_R, /* Reserved */
- FUNC_ADC,
- FUNC_ADCTRIG,
- FUNC_CAN0,
- FUNC_CAN1,
- FUNC_CGU_OUT,
- FUNC_CLKIN,
- FUNC_CLKOUT,
- FUNC_CTIN,
- FUNC_CTOUT,
- FUNC_DAC,
- FUNC_EMC,
- FUNC_EMC_ALT,
- FUNC_ENET,
- FUNC_ENET_ALT,
- FUNC_GPIO,
- FUNC_I2C0,
- FUNC_I2C1,
- FUNC_I2S0_RX_MCLK,
- FUNC_I2S0_RX_SCK,
- FUNC_I2S0_RX_SDA,
- FUNC_I2S0_RX_WS,
- FUNC_I2S0_TX_MCLK,
- FUNC_I2S0_TX_SCK,
- FUNC_I2S0_TX_SDA,
- FUNC_I2S0_TX_WS,
- FUNC_I2S1,
- FUNC_LCD,
- FUNC_LCD_ALT,
- FUNC_MCTRL,
- FUNC_NMI,
- FUNC_QEI,
- FUNC_SDMMC,
- FUNC_SGPIO,
- FUNC_SPI,
- FUNC_SPIFI,
- FUNC_SSP0,
- FUNC_SSP0_ALT,
- FUNC_SSP1,
- FUNC_TIMER0,
- FUNC_TIMER1,
- FUNC_TIMER2,
- FUNC_TIMER3,
- FUNC_TRACE,
- FUNC_UART0,
- FUNC_UART1,
- FUNC_UART2,
- FUNC_UART3,
- FUNC_USB0,
- FUNC_USB1,
- FUNC_MAX
-};
-
-static const char *const lpc18xx_function_names[] = {
- [FUNC_R] = "reserved",
- [FUNC_ADC] = "adc",
- [FUNC_ADCTRIG] = "adctrig",
- [FUNC_CAN0] = "can0",
- [FUNC_CAN1] = "can1",
- [FUNC_CGU_OUT] = "cgu_out",
- [FUNC_CLKIN] = "clkin",
- [FUNC_CLKOUT] = "clkout",
- [FUNC_CTIN] = "ctin",
- [FUNC_CTOUT] = "ctout",
- [FUNC_DAC] = "dac",
- [FUNC_EMC] = "emc",
- [FUNC_EMC_ALT] = "emc_alt",
- [FUNC_ENET] = "enet",
- [FUNC_ENET_ALT] = "enet_alt",
- [FUNC_GPIO] = "gpio",
- [FUNC_I2C0] = "i2c0",
- [FUNC_I2C1] = "i2c1",
- [FUNC_I2S0_RX_MCLK] = "i2s0_rx_mclk",
- [FUNC_I2S0_RX_SCK] = "i2s0_rx_sck",
- [FUNC_I2S0_RX_SDA] = "i2s0_rx_sda",
- [FUNC_I2S0_RX_WS] = "i2s0_rx_ws",
- [FUNC_I2S0_TX_MCLK] = "i2s0_tx_mclk",
- [FUNC_I2S0_TX_SCK] = "i2s0_tx_sck",
- [FUNC_I2S0_TX_SDA] = "i2s0_tx_sda",
- [FUNC_I2S0_TX_WS] = "i2s0_tx_ws",
- [FUNC_I2S1] = "i2s1",
- [FUNC_LCD] = "lcd",
- [FUNC_LCD_ALT] = "lcd_alt",
- [FUNC_MCTRL] = "mctrl",
- [FUNC_NMI] = "nmi",
- [FUNC_QEI] = "qei",
- [FUNC_SDMMC] = "sdmmc",
- [FUNC_SGPIO] = "sgpio",
- [FUNC_SPI] = "spi",
- [FUNC_SPIFI] = "spifi",
- [FUNC_SSP0] = "ssp0",
- [FUNC_SSP0_ALT] = "ssp0_alt",
- [FUNC_SSP1] = "ssp1",
- [FUNC_TIMER0] = "timer0",
- [FUNC_TIMER1] = "timer1",
- [FUNC_TIMER2] = "timer2",
- [FUNC_TIMER3] = "timer3",
- [FUNC_TRACE] = "trace",
- [FUNC_UART0] = "uart0",
- [FUNC_UART1] = "uart1",
- [FUNC_UART2] = "uart2",
- [FUNC_UART3] = "uart3",
- [FUNC_USB0] = "usb0",
- [FUNC_USB1] = "usb1",
-};
-
-struct lpc18xx_pmx_func {
- const char **groups;
- unsigned ngroups;
-};
-
-struct lpc18xx_scu_data {
- struct pinctrl_dev *pctl;
- void __iomem *base;
- struct clk *clk;
- struct lpc18xx_pmx_func func[FUNC_MAX];
-};
-
-struct lpc18xx_pin_caps {
- unsigned int offset;
- unsigned char functions[LPC18XX_SCU_FUNC_PER_PIN];
- unsigned char analog;
- unsigned char type;
-};
-
-/* Analog pins are required to have both bias and input disabled */
-#define LPC18XX_SCU_ANALOG_PIN_CFG 0x10
-
-/* Macros to maniupluate analog member in lpc18xx_pin_caps */
-#define LPC18XX_ANALOG_PIN BIT(7)
-#define LPC18XX_ANALOG_ADC(a) ((a >> 5) & 0x3)
-#define LPC18XX_ANALOG_BIT_MASK 0x1f
-#define ADC0 (LPC18XX_ANALOG_PIN | (0x00 << 5))
-#define ADC1 (LPC18XX_ANALOG_PIN | (0x01 << 5))
-#define DAC LPC18XX_ANALOG_PIN
-
-#define LPC_P(port, pin, f0, f1, f2, f3, f4, f5, f6, f7, a, t) \
-static struct lpc18xx_pin_caps lpc18xx_pin_p##port##_##pin = { \
- .offset = 0x##port * 32 * 4 + pin * 4, \
- .functions = { \
- FUNC_##f0, FUNC_##f1, FUNC_##f2, \
- FUNC_##f3, FUNC_##f4, FUNC_##f5, \
- FUNC_##f6, FUNC_##f7, \
- }, \
- .analog = a, \
- .type = TYPE_##t, \
-}
-
-#define LPC_N(pname, off, f0, f1, f2, f3, f4, f5, f6, f7, a, t) \
-static struct lpc18xx_pin_caps lpc18xx_pin_##pname = { \
- .offset = off, \
- .functions = { \
- FUNC_##f0, FUNC_##f1, FUNC_##f2, \
- FUNC_##f3, FUNC_##f4, FUNC_##f5, \
- FUNC_##f6, FUNC_##f7, \
- }, \
- .analog = a, \
- .type = TYPE_##t, \
-}
-
-
-/* Pinmuxing table taken from data sheet */
-/* Pin FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 ANALOG TYPE */
-LPC_P(0,0, GPIO, SSP1, ENET, SGPIO, R, R, I2S0_TX_WS,I2S1, 0, ND);
-LPC_P(0,1, GPIO, SSP1,ENET_ALT,SGPIO, R, R, ENET, I2S1, 0, ND);
-LPC_P(1,0, GPIO, CTIN, EMC, R, R, SSP0, SGPIO, R, 0, ND);
-LPC_P(1,1, GPIO, CTOUT, EMC, SGPIO, R, SSP0, R, R, 0, ND);
-LPC_P(1,2, GPIO, CTOUT, EMC, SGPIO, R, SSP0, R, R, 0, ND);
-LPC_P(1,3, GPIO, CTOUT, SGPIO, EMC, USB0, SSP1, R, SDMMC, 0, ND);
-LPC_P(1,4, GPIO, CTOUT, SGPIO, EMC, USB0, SSP1, R, SDMMC, 0, ND);
-LPC_P(1,5, GPIO, CTOUT, R, EMC, USB0, SSP1, SGPIO, SDMMC, 0, ND);
-LPC_P(1,6, GPIO, CTIN, R, EMC, R, R, SGPIO, SDMMC, 0, ND);
-LPC_P(1,7, GPIO, UART1, CTOUT, EMC, USB0, R, R, R, 0, ND);
-LPC_P(1,8, GPIO, UART1, CTOUT, EMC, R, R, R, SDMMC, 0, ND);
-LPC_P(1,9, GPIO, UART1, CTOUT, EMC, R, R, R, SDMMC, 0, ND);
-LPC_P(1,10, GPIO, UART1, CTOUT, EMC, R, R, R, SDMMC, 0, ND);
-LPC_P(1,11, GPIO, UART1, CTOUT, EMC, R, R, R, SDMMC, 0, ND);
-LPC_P(1,12, GPIO, UART1, R, EMC, TIMER0, R, SGPIO, SDMMC, 0, ND);
-LPC_P(1,13, GPIO, UART1, R, EMC, TIMER0, R, SGPIO, SDMMC, 0, ND);
-LPC_P(1,14, GPIO, UART1, R, EMC, TIMER0, R, SGPIO, R, 0, ND);
-LPC_P(1,15, GPIO, UART2, SGPIO, ENET, TIMER0, R, R, R, 0, ND);
-LPC_P(1,16, GPIO, UART2, SGPIO,ENET_ALT,TIMER0, R, R, ENET, 0, ND);
-LPC_P(1,17, GPIO, UART2, R, ENET, TIMER0, CAN1, SGPIO, R, 0, HD);
-LPC_P(1,18, GPIO, UART2, R, ENET, TIMER0, CAN1, SGPIO, R, 0, ND);
-LPC_P(1,19, ENET, SSP1, R, R, CLKOUT, R, I2S0_RX_MCLK,I2S1, 0, ND);
-LPC_P(1,20, GPIO, SSP1, R, ENET, TIMER0, R, SGPIO, R, 0, ND);
-LPC_P(2,0, SGPIO, UART0, EMC, USB0, GPIO, R, TIMER3, ENET, 0, ND);
-LPC_P(2,1, SGPIO, UART0, EMC, USB0, GPIO, R, TIMER3, R, 0, ND);
-LPC_P(2,2, SGPIO, UART0, EMC, USB0, GPIO, CTIN, TIMER3, R, 0, ND);
-LPC_P(2,3, SGPIO, I2C1, UART3, CTIN, GPIO, R, TIMER3, USB0, 0, HD);
-LPC_P(2,4, SGPIO, I2C1, UART3, CTIN, GPIO, R, TIMER3, USB0, 0, HD);
-LPC_P(2,5, SGPIO, CTIN, USB1, ADCTRIG, GPIO, R, TIMER3, USB0, 0, HD);
-LPC_P(2,6, SGPIO, UART0, EMC, USB0, GPIO, CTIN, TIMER3, R, 0, ND);
-LPC_P(2,7, GPIO, CTOUT, UART3, EMC, R, R, TIMER3, R, 0, ND);
-LPC_P(2,8, SGPIO, CTOUT, UART3, EMC, GPIO, R, R, R, 0, ND);
-LPC_P(2,9, GPIO, CTOUT, UART3, EMC, R, R, R, R, 0, ND);
-LPC_P(2,10, GPIO, CTOUT, UART2, EMC, R, R, R, R, 0, ND);
-LPC_P(2,11, GPIO, CTOUT, UART2, EMC, R, R, R, R, 0, ND);
-LPC_P(2,12, GPIO, CTOUT, R, EMC, R, R, R, UART2, 0, ND);
-LPC_P(2,13, GPIO, CTIN, R, EMC, R, R, R, UART2, 0, ND);
-LPC_P(3,0, I2S0_RX_SCK, I2S0_RX_MCLK, I2S0_TX_SCK, I2S0_TX_MCLK,SSP0,R,R,R, 0, ND);
-LPC_P(3,1, I2S0_TX_WS, I2S0_RX_WS,CAN0,USB1,GPIO, R, LCD, R, 0, ND);
-LPC_P(3,2, I2S0_TX_SDA, I2S0_RX_SDA,CAN0,USB1,GPIO, R, LCD, R, 0, ND);
-LPC_P(3,3, R, SPI, SSP0, SPIFI, CGU_OUT,R, I2S0_TX_MCLK, I2S1, 0, HS);
-LPC_P(3,4, GPIO, R, R, SPIFI, UART1, I2S0_TX_WS, I2S1, LCD, 0, ND);
-LPC_P(3,5, GPIO, R, R, SPIFI, UART1, I2S0_TX_SDA,I2S1, LCD, 0, ND);
-LPC_P(3,6, GPIO, SPI, SSP0, SPIFI, R, SSP0_ALT, R, R, 0, ND);
-LPC_P(3,7, R, SPI, SSP0, SPIFI, GPIO, SSP0_ALT, R, R, 0, ND);
-LPC_P(3,8, R, SPI, SSP0, SPIFI, GPIO, SSP0_ALT, R, R, 0, ND);
-LPC_P(4,0, GPIO, MCTRL, NMI, R, R, LCD, UART3, R, 0, ND);
-LPC_P(4,1, GPIO, CTOUT, LCD, R, R, LCD_ALT, UART3, ENET, ADC0|1, ND);
-LPC_P(4,2, GPIO, CTOUT, LCD, R, R, LCD_ALT, UART3, SGPIO, 0, ND);
-LPC_P(4,3, GPIO, CTOUT, LCD, R, R, LCD_ALT, UART3, SGPIO, ADC0|0, ND);
-LPC_P(4,4, GPIO, CTOUT, LCD, R, R, LCD_ALT, UART3, SGPIO, DAC, ND);
-LPC_P(4,5, GPIO, CTOUT, LCD, R, R, R, R, SGPIO, 0, ND);
-LPC_P(4,6, GPIO, CTOUT, LCD, R, R, R, R, SGPIO, 0, ND);
-LPC_P(4,7, LCD, CLKIN, R, R, R, R, I2S1,I2S0_TX_SCK, 0, ND);
-LPC_P(4,8, R, CTIN, LCD, R, GPIO, LCD_ALT, CAN1, SGPIO, 0, ND);
-LPC_P(4,9, R, CTIN, LCD, R, GPIO, LCD_ALT, CAN1, SGPIO, 0, ND);
-LPC_P(4,10, R, CTIN, LCD, R, GPIO, LCD_ALT, R, SGPIO, 0, ND);
-LPC_P(5,0, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
-LPC_P(5,1, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
-LPC_P(5,2, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
-LPC_P(5,3, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
-LPC_P(5,4, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
-LPC_P(5,5, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
-LPC_P(5,6, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
-LPC_P(5,7, GPIO, MCTRL, EMC, R, UART1, TIMER1, R, R, 0, ND);
-LPC_P(6,0, R, I2S0_RX_MCLK,R, R, I2S0_RX_SCK, R, R, R, 0, ND);
-LPC_P(6,1, GPIO, EMC, UART0, I2S0_RX_WS, R, TIMER2, R, R, 0, ND);
-LPC_P(6,2, GPIO, EMC, UART0, I2S0_RX_SDA, R, TIMER2, R, R, 0, ND);
-LPC_P(6,3, GPIO, USB0, SGPIO, EMC, R, TIMER2, R, R, 0, ND);
-LPC_P(6,4, GPIO, CTIN, UART0, EMC, R, R, R, R, 0, ND);
-LPC_P(6,5, GPIO, CTOUT, UART0, EMC, R, R, R, R, 0, ND);
-LPC_P(6,6, GPIO, EMC, SGPIO, USB0, R, TIMER2, R, R, 0, ND);
-LPC_P(6,7, R, EMC, SGPIO, USB0, GPIO, TIMER2, R, R, 0, ND);
-LPC_P(6,8, R, EMC, SGPIO, USB0, GPIO, TIMER2, R, R, 0, ND);
-LPC_P(6,9, GPIO, R, R, EMC, R, TIMER2, R, R, 0, ND);
-LPC_P(6,10, GPIO, MCTRL, R, EMC, R, R, R, R, 0, ND);
-LPC_P(6,11, GPIO, R, R, EMC, R, TIMER2, R, R, 0, ND);
-LPC_P(6,12, GPIO, CTOUT, R, EMC, R, R, R, R, 0, ND);
-LPC_P(7,0, GPIO, CTOUT, R, LCD, R, R, R, SGPIO, 0, ND);
-LPC_P(7,1, GPIO, CTOUT,I2S0_TX_WS,LCD,LCD_ALT, R, UART2, SGPIO, 0, ND);
-LPC_P(7,2, GPIO, CTIN,I2S0_TX_SDA,LCD,LCD_ALT, R, UART2, SGPIO, 0, ND);
-LPC_P(7,3, GPIO, CTIN, R, LCD,LCD_ALT, R, R, R, 0, ND);
-LPC_P(7,4, GPIO, CTOUT, R, LCD,LCD_ALT, TRACE, R, R, ADC0|4, ND);
-LPC_P(7,5, GPIO, CTOUT, R, LCD,LCD_ALT, TRACE, R, R, ADC0|3, ND);
-LPC_P(7,6, GPIO, CTOUT, R, LCD, R, TRACE, R, R, 0, ND);
-LPC_P(7,7, GPIO, CTOUT, R, LCD, R, TRACE, ENET, SGPIO, ADC1|6, ND);
-LPC_P(8,0, GPIO, USB0, R, MCTRL, SGPIO, R, R, TIMER0, 0, HD);
-LPC_P(8,1, GPIO, USB0, R, MCTRL, SGPIO, R, R, TIMER0, 0, HD);
-LPC_P(8,2, GPIO, USB0, R, MCTRL, SGPIO, R, R, TIMER0, 0, HD);
-LPC_P(8,3, GPIO, USB1, R, LCD, LCD_ALT, R, R, TIMER0, 0, ND);
-LPC_P(8,4, GPIO, USB1, R, LCD, LCD_ALT, R, R, TIMER0, 0, ND);
-LPC_P(8,5, GPIO, USB1, R, LCD, LCD_ALT, R, R, TIMER0, 0, ND);
-LPC_P(8,6, GPIO, USB1, R, LCD, LCD_ALT, R, R, TIMER0, 0, ND);
-LPC_P(8,7, GPIO, USB1, R, LCD, LCD_ALT, R, R, TIMER0, 0, ND);
-LPC_P(8,8, R, USB1, R, R, R, R,CGU_OUT, I2S1, 0, ND);
-LPC_P(9,0, GPIO, MCTRL, R, R, R, ENET, SGPIO, SSP0, 0, ND);
-LPC_P(9,1, GPIO, MCTRL, R, R, I2S0_TX_WS,ENET, SGPIO, SSP0, 0, ND);
-LPC_P(9,2, GPIO, MCTRL, R, R, I2S0_TX_SDA,ENET,SGPIO, SSP0, 0, ND);
-LPC_P(9,3, GPIO, MCTRL, USB1, R, R, ENET, SGPIO, UART3, 0, ND);
-LPC_P(9,4, R, MCTRL, USB1, R, GPIO, ENET, SGPIO, UART3, 0, ND);
-LPC_P(9,5, R, MCTRL, USB1, R, GPIO, ENET, SGPIO, UART0, 0, ND);
-LPC_P(9,6, GPIO, MCTRL, USB1, R, R, ENET, SGPIO, UART0, 0, ND);
-LPC_P(a,0, R, R, R, R, R, I2S1, CGU_OUT, R, 0, ND);
-LPC_P(a,1, GPIO, QEI, R, UART2, R, R, R, R, 0, HD);
-LPC_P(a,2, GPIO, QEI, R, UART2, R, R, R, R, 0, HD);
-LPC_P(a,3, GPIO, QEI, R, R, R, R, R, R, 0, HD);
-LPC_P(a,4, R, CTOUT, R, EMC, GPIO, R, R, R, 0, ND);
-LPC_P(b,0, R, CTOUT, LCD, R, GPIO, R, R, R, 0, ND);
-LPC_P(b,1, R, USB1, LCD, R, GPIO, CTOUT, R, R, 0, ND);
-LPC_P(b,2, R, USB1, LCD, R, GPIO, CTOUT, R, R, 0, ND);
-LPC_P(b,3, R, USB1, LCD, R, GPIO, CTOUT, R, R, 0, ND);
-LPC_P(b,4, R, USB1, LCD, R, GPIO, CTIN, R, R, 0, ND);
-LPC_P(b,5, R, USB1, LCD, R, GPIO, CTIN, LCD_ALT, R, 0, ND);
-LPC_P(b,6, R, USB1, LCD, R, GPIO, CTIN, LCD_ALT, R, ADC0|6, ND);
-LPC_P(c,0, R, USB1, R, ENET, LCD, R, R, SDMMC, ADC1|1, ND);
-LPC_P(c,1, USB1, R, UART1, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
-LPC_P(c,2, USB1, R, UART1, ENET, GPIO, R, R, SDMMC, 0, ND);
-LPC_P(c,3, USB1, R, UART1, ENET, GPIO, R, R, SDMMC, ADC1|0, ND);
-LPC_P(c,4, R, USB1, R, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
-LPC_P(c,5, R, USB1, R, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
-LPC_P(c,6, R, USB1, R, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
-LPC_P(c,7, R, USB1, R, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
-LPC_P(c,8, R, USB1, R, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
-LPC_P(c,9, R, USB1, R, ENET, GPIO, R, TIMER3, SDMMC, 0, ND);
-LPC_P(c,10, R, USB1, UART1, R, GPIO, R, TIMER3, SDMMC, 0, ND);
-LPC_P(c,11, R, USB1, UART1, R, GPIO, R, R, SDMMC, 0, ND);
-LPC_P(c,12, R, R, UART1, R, GPIO, SGPIO, I2S0_TX_SDA,SDMMC, 0, ND);
-LPC_P(c,13, R, R, UART1, R, GPIO, SGPIO, I2S0_TX_WS, SDMMC, 0, ND);
-LPC_P(c,14, R, R, UART1, R, GPIO, SGPIO, ENET, SDMMC, 0, ND);
-LPC_P(d,0, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
-LPC_P(d,1, R, R, EMC, R, GPIO, SDMMC, R, SGPIO, 0, ND);
-LPC_P(d,2, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
-LPC_P(d,3, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
-LPC_P(d,4, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
-LPC_P(d,5, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
-LPC_P(d,6, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
-LPC_P(d,7, R, CTIN, EMC, R, GPIO, R, R, SGPIO, 0, ND);
-LPC_P(d,8, R, CTIN, EMC, R, GPIO, R, R, SGPIO, 0, ND);
-LPC_P(d,9, R, CTOUT, EMC, R, GPIO, R, R, SGPIO, 0, ND);
-LPC_P(d,10, R, CTIN, EMC, R, GPIO, R, R, R, 0, ND);
-LPC_P(d,11, R, R, EMC, R, GPIO, USB1, CTOUT, R, 0, ND);
-LPC_P(d,12, R, R, EMC, R, GPIO, R, CTOUT, R, 0, ND);
-LPC_P(d,13, R, CTIN, EMC, R, GPIO, R, CTOUT, R, 0, ND);
-LPC_P(d,14, R, R, EMC, R, GPIO, R, CTOUT, R, 0, ND);
-LPC_P(d,15, R, R, EMC, R, GPIO, SDMMC, CTOUT, R, 0, ND);
-LPC_P(d,16, R, R, EMC, R, GPIO, SDMMC, CTOUT, R, 0, ND);
-LPC_P(e,0, R, R, R, EMC, GPIO, CAN1, R, R, 0, ND);
-LPC_P(e,1, R, R, R, EMC, GPIO, CAN1, R, R, 0, ND);
-LPC_P(e,2,ADCTRIG, CAN0, R, EMC, GPIO, R, R, R, 0, ND);
-LPC_P(e,3, R, CAN0,ADCTRIG, EMC, GPIO, R, R, R, 0, ND);
-LPC_P(e,4, R, NMI, R, EMC, GPIO, R, R, R, 0, ND);
-LPC_P(e,5, R, CTOUT, UART1, EMC, GPIO, R, R, R, 0, ND);
-LPC_P(e,6, R, CTOUT, UART1, EMC, GPIO, R, R, R, 0, ND);
-LPC_P(e,7, R, CTOUT, UART1, EMC, GPIO, R, R, R, 0, ND);
-LPC_P(e,8, R, CTOUT, UART1, EMC, GPIO, R, R, R, 0, ND);
-LPC_P(e,9, R, CTIN, UART1, EMC, GPIO, R, R, R, 0, ND);
-LPC_P(e,10, R, CTIN, UART1, EMC, GPIO, R, R, R, 0, ND);
-LPC_P(e,11, R, CTOUT, UART1, EMC, GPIO, R, R, R, 0, ND);
-LPC_P(e,12, R, CTOUT, UART1, EMC, GPIO, R, R, R, 0, ND);
-LPC_P(e,13, R, CTOUT, I2C1, EMC, GPIO, R, R, R, 0, ND);
-LPC_P(e,14, R, R, R, EMC, GPIO, R, R, R, 0, ND);
-LPC_P(e,15, R, CTOUT, I2C1, EMC, GPIO, R, R, R, 0, ND);
-LPC_P(f,0, SSP0, CLKIN, R, R, R, R, R, I2S1, 0, ND);
-LPC_P(f,1, R, R, SSP0, R, GPIO, R, SGPIO, R, 0, ND);
-LPC_P(f,2, R, UART3, SSP0, R, GPIO, R, SGPIO, R, 0, ND);
-LPC_P(f,3, R, UART3, SSP0, R, GPIO, R, SGPIO, R, 0, ND);
-LPC_P(f,4, SSP1, CLKIN, TRACE, R, R, R, I2S0_TX_MCLK,I2S0_RX_SCK, 0, ND);
-LPC_P(f,5, R, UART3, SSP1, TRACE, GPIO, R, SGPIO, R, ADC1|4, ND);
-LPC_P(f,6, R, UART3, SSP1, TRACE, GPIO, R, SGPIO, I2S1, ADC1|3, ND);
-LPC_P(f,7, R, UART3, SSP1, TRACE, GPIO, R, SGPIO, I2S1, ADC1|7, ND);
-LPC_P(f,8, R, UART0, CTIN, TRACE, GPIO, R, SGPIO, R, ADC0|2, ND);
-LPC_P(f,9, R, UART0, CTOUT, R, GPIO, R, SGPIO, R, ADC1|2, ND);
-LPC_P(f,10, R, UART0, R, R, GPIO, R, SDMMC, R, ADC0|5, ND);
-LPC_P(f,11, R, UART0, R, R, GPIO, R, SDMMC, R, ADC1|5, ND);
-
-/* Pin Offset FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 ANALOG TYPE */
-LPC_N(clk0, 0xc00, EMC, CLKOUT, R, R, SDMMC, EMC_ALT, SSP1, ENET, 0, HS);
-LPC_N(clk1, 0xc04, EMC, CLKOUT, R, R, R, CGU_OUT, R, I2S1, 0, HS);
-LPC_N(clk2, 0xc08, EMC, CLKOUT, R, R, SDMMC, EMC_ALT,I2S0_TX_MCLK,I2S1, 0, HS);
-LPC_N(clk3, 0xc0c, EMC, CLKOUT, R, R, R, CGU_OUT, R, I2S1, 0, HS);
-LPC_N(usb1_dm, 0xc80, R, R, R, R, R, R, R, R, 0, USB1);
-LPC_N(usb1_dp, 0xc80, R, R, R, R, R, R, R, R, 0, USB1);
-LPC_N(i2c0_scl, 0xc84, R, R, R, R, R, R, R, R, 0, I2C0);
-LPC_N(i2c0_sda, 0xc84, R, R, R, R, R, R, R, R, 0, I2C0);
-
-#define LPC18XX_PIN_P(port, pin) { \
- .number = 0x##port * 32 + pin, \
- .name = "p"#port"_"#pin, \
- .drv_data = &lpc18xx_pin_p##port##_##pin \
-}
-
-/* Pin numbers for special pins */
-enum {
- PIN_CLK0 = 600,
- PIN_CLK1,
- PIN_CLK2,
- PIN_CLK3,
- PIN_USB1_DM,
- PIN_USB1_DP,
- PIN_I2C0_SCL,
- PIN_I2C0_SDA,
-};
-
-#define LPC18XX_PIN(pname, n) { \
- .number = n, \
- .name = #pname, \
- .drv_data = &lpc18xx_pin_##pname \
-}
-
-static const struct pinctrl_pin_desc lpc18xx_pins[] = {
- LPC18XX_PIN_P(0,0),
- LPC18XX_PIN_P(0,1),
- LPC18XX_PIN_P(1,0),
- LPC18XX_PIN_P(1,1),
- LPC18XX_PIN_P(1,2),
- LPC18XX_PIN_P(1,3),
- LPC18XX_PIN_P(1,4),
- LPC18XX_PIN_P(1,5),
- LPC18XX_PIN_P(1,6),
- LPC18XX_PIN_P(1,7),
- LPC18XX_PIN_P(1,8),
- LPC18XX_PIN_P(1,9),
- LPC18XX_PIN_P(1,10),
- LPC18XX_PIN_P(1,11),
- LPC18XX_PIN_P(1,12),
- LPC18XX_PIN_P(1,13),
- LPC18XX_PIN_P(1,14),
- LPC18XX_PIN_P(1,15),
- LPC18XX_PIN_P(1,16),
- LPC18XX_PIN_P(1,17),
- LPC18XX_PIN_P(1,18),
- LPC18XX_PIN_P(1,19),
- LPC18XX_PIN_P(1,20),
- LPC18XX_PIN_P(2,0),
- LPC18XX_PIN_P(2,1),
- LPC18XX_PIN_P(2,2),
- LPC18XX_PIN_P(2,3),
- LPC18XX_PIN_P(2,4),
- LPC18XX_PIN_P(2,5),
- LPC18XX_PIN_P(2,6),
- LPC18XX_PIN_P(2,7),
- LPC18XX_PIN_P(2,8),
- LPC18XX_PIN_P(2,9),
- LPC18XX_PIN_P(2,10),
- LPC18XX_PIN_P(2,11),
- LPC18XX_PIN_P(2,12),
- LPC18XX_PIN_P(2,13),
- LPC18XX_PIN_P(3,0),
- LPC18XX_PIN_P(3,1),
- LPC18XX_PIN_P(3,2),
- LPC18XX_PIN_P(3,3),
- LPC18XX_PIN_P(3,4),
- LPC18XX_PIN_P(3,5),
- LPC18XX_PIN_P(3,6),
- LPC18XX_PIN_P(3,7),
- LPC18XX_PIN_P(3,8),
- LPC18XX_PIN_P(4,0),
- LPC18XX_PIN_P(4,1),
- LPC18XX_PIN_P(4,2),
- LPC18XX_PIN_P(4,3),
- LPC18XX_PIN_P(4,4),
- LPC18XX_PIN_P(4,5),
- LPC18XX_PIN_P(4,6),
- LPC18XX_PIN_P(4,7),
- LPC18XX_PIN_P(4,8),
- LPC18XX_PIN_P(4,9),
- LPC18XX_PIN_P(4,10),
- LPC18XX_PIN_P(5,0),
- LPC18XX_PIN_P(5,1),
- LPC18XX_PIN_P(5,2),
- LPC18XX_PIN_P(5,3),
- LPC18XX_PIN_P(5,4),
- LPC18XX_PIN_P(5,5),
- LPC18XX_PIN_P(5,6),
- LPC18XX_PIN_P(5,7),
- LPC18XX_PIN_P(6,0),
- LPC18XX_PIN_P(6,1),
- LPC18XX_PIN_P(6,2),
- LPC18XX_PIN_P(6,3),
- LPC18XX_PIN_P(6,4),
- LPC18XX_PIN_P(6,5),
- LPC18XX_PIN_P(6,6),
- LPC18XX_PIN_P(6,7),
- LPC18XX_PIN_P(6,8),
- LPC18XX_PIN_P(6,9),
- LPC18XX_PIN_P(6,10),
- LPC18XX_PIN_P(6,11),
- LPC18XX_PIN_P(6,12),
- LPC18XX_PIN_P(7,0),
- LPC18XX_PIN_P(7,1),
- LPC18XX_PIN_P(7,2),
- LPC18XX_PIN_P(7,3),
- LPC18XX_PIN_P(7,4),
- LPC18XX_PIN_P(7,5),
- LPC18XX_PIN_P(7,6),
- LPC18XX_PIN_P(7,7),
- LPC18XX_PIN_P(8,0),
- LPC18XX_PIN_P(8,1),
- LPC18XX_PIN_P(8,2),
- LPC18XX_PIN_P(8,3),
- LPC18XX_PIN_P(8,4),
- LPC18XX_PIN_P(8,5),
- LPC18XX_PIN_P(8,6),
- LPC18XX_PIN_P(8,7),
- LPC18XX_PIN_P(8,8),
- LPC18XX_PIN_P(9,0),
- LPC18XX_PIN_P(9,1),
- LPC18XX_PIN_P(9,2),
- LPC18XX_PIN_P(9,3),
- LPC18XX_PIN_P(9,4),
- LPC18XX_PIN_P(9,5),
- LPC18XX_PIN_P(9,6),
- LPC18XX_PIN_P(a,0),
- LPC18XX_PIN_P(a,1),
- LPC18XX_PIN_P(a,2),
- LPC18XX_PIN_P(a,3),
- LPC18XX_PIN_P(a,4),
- LPC18XX_PIN_P(b,0),
- LPC18XX_PIN_P(b,1),
- LPC18XX_PIN_P(b,2),
- LPC18XX_PIN_P(b,3),
- LPC18XX_PIN_P(b,4),
- LPC18XX_PIN_P(b,5),
- LPC18XX_PIN_P(b,6),
- LPC18XX_PIN_P(c,0),
- LPC18XX_PIN_P(c,1),
- LPC18XX_PIN_P(c,2),
- LPC18XX_PIN_P(c,3),
- LPC18XX_PIN_P(c,4),
- LPC18XX_PIN_P(c,5),
- LPC18XX_PIN_P(c,6),
- LPC18XX_PIN_P(c,7),
- LPC18XX_PIN_P(c,8),
- LPC18XX_PIN_P(c,9),
- LPC18XX_PIN_P(c,10),
- LPC18XX_PIN_P(c,11),
- LPC18XX_PIN_P(c,12),
- LPC18XX_PIN_P(c,13),
- LPC18XX_PIN_P(c,14),
- LPC18XX_PIN_P(d,0),
- LPC18XX_PIN_P(d,1),
- LPC18XX_PIN_P(d,2),
- LPC18XX_PIN_P(d,3),
- LPC18XX_PIN_P(d,4),
- LPC18XX_PIN_P(d,5),
- LPC18XX_PIN_P(d,6),
- LPC18XX_PIN_P(d,7),
- LPC18XX_PIN_P(d,8),
- LPC18XX_PIN_P(d,9),
- LPC18XX_PIN_P(d,10),
- LPC18XX_PIN_P(d,11),
- LPC18XX_PIN_P(d,12),
- LPC18XX_PIN_P(d,13),
- LPC18XX_PIN_P(d,14),
- LPC18XX_PIN_P(d,15),
- LPC18XX_PIN_P(d,16),
- LPC18XX_PIN_P(e,0),
- LPC18XX_PIN_P(e,1),
- LPC18XX_PIN_P(e,2),
- LPC18XX_PIN_P(e,3),
- LPC18XX_PIN_P(e,4),
- LPC18XX_PIN_P(e,5),
- LPC18XX_PIN_P(e,6),
- LPC18XX_PIN_P(e,7),
- LPC18XX_PIN_P(e,8),
- LPC18XX_PIN_P(e,9),
- LPC18XX_PIN_P(e,10),
- LPC18XX_PIN_P(e,11),
- LPC18XX_PIN_P(e,12),
- LPC18XX_PIN_P(e,13),
- LPC18XX_PIN_P(e,14),
- LPC18XX_PIN_P(e,15),
- LPC18XX_PIN_P(f,0),
- LPC18XX_PIN_P(f,1),
- LPC18XX_PIN_P(f,2),
- LPC18XX_PIN_P(f,3),
- LPC18XX_PIN_P(f,4),
- LPC18XX_PIN_P(f,5),
- LPC18XX_PIN_P(f,6),
- LPC18XX_PIN_P(f,7),
- LPC18XX_PIN_P(f,8),
- LPC18XX_PIN_P(f,9),
- LPC18XX_PIN_P(f,10),
- LPC18XX_PIN_P(f,11),
-
- LPC18XX_PIN(clk0, PIN_CLK0),
- LPC18XX_PIN(clk1, PIN_CLK1),
- LPC18XX_PIN(clk2, PIN_CLK2),
- LPC18XX_PIN(clk3, PIN_CLK3),
- LPC18XX_PIN(usb1_dm, PIN_USB1_DM),
- LPC18XX_PIN(usb1_dp, PIN_USB1_DP),
- LPC18XX_PIN(i2c0_scl, PIN_I2C0_SCL),
- LPC18XX_PIN(i2c0_sda, PIN_I2C0_SDA),
-};
-
-/* PIN_CONFIG_GPIO_PIN_INT: route gpio to the gpio pin interrupt controller */
-#define PIN_CONFIG_GPIO_PIN_INT (PIN_CONFIG_END + 1)
-
-static const struct pinconf_generic_params lpc18xx_params[] = {
- {"nxp,gpio-pin-interrupt", PIN_CONFIG_GPIO_PIN_INT, 0},
-};
-
-#ifdef CONFIG_DEBUG_FS
-static const struct pin_config_item lpc18xx_conf_items[ARRAY_SIZE(lpc18xx_params)] = {
- PCONFDUMP(PIN_CONFIG_GPIO_PIN_INT, "gpio pin int", NULL, true),
-};
-#endif
-
-static int lpc18xx_pconf_get_usb1(enum pin_config_param param, int *arg, u32 reg)
-{
- switch (param) {
- case PIN_CONFIG_MODE_LOW_POWER:
- if (reg & LPC18XX_SCU_USB1_EPWR)
- *arg = 0;
- else
- *arg = 1;
- break;
-
- case PIN_CONFIG_BIAS_DISABLE:
- if (reg & LPC18XX_SCU_USB1_EPD)
- return -EINVAL;
- break;
-
- case PIN_CONFIG_BIAS_PULL_DOWN:
- if (reg & LPC18XX_SCU_USB1_EPD)
- *arg = 1;
- else
- return -EINVAL;
- break;
-
- default:
- return -ENOTSUPP;
- }
-
- return 0;
-}
-
-static int lpc18xx_pconf_get_i2c0(enum pin_config_param param, int *arg, u32 reg,
- unsigned pin)
-{
- u8 shift;
-
- if (pin == PIN_I2C0_SCL)
- shift = LPC18XX_SCU_I2C0_SCL_SHIFT;
- else
- shift = LPC18XX_SCU_I2C0_SDA_SHIFT;
-
- switch (param) {
- case PIN_CONFIG_INPUT_ENABLE:
- if (reg & (LPC18XX_SCU_I2C0_EZI << shift))
- *arg = 1;
- else
- return -EINVAL;
- break;
-
- case PIN_CONFIG_SLEW_RATE:
- if (reg & (LPC18XX_SCU_I2C0_EHD << shift))
- *arg = 1;
- else
- *arg = 0;
- break;
-
- case PIN_CONFIG_INPUT_SCHMITT:
- if (reg & (LPC18XX_SCU_I2C0_EFP << shift))
- *arg = 3;
- else
- *arg = 50;
- break;
-
- case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
- if (reg & (LPC18XX_SCU_I2C0_ZIF << shift))
- return -EINVAL;
- else
- *arg = 1;
- break;
-
- default:
- return -ENOTSUPP;
- }
-
- return 0;
-}
-
-static int lpc18xx_pin_to_gpio(struct pinctrl_dev *pctldev, unsigned pin)
-{
- struct pinctrl_gpio_range *range;
-
- range = pinctrl_find_gpio_range_from_pin_nolock(pctldev, pin);
- if (!range)
- return -EINVAL;
-
- return pin - range->pin_base + range->base;
-}
-
-static int lpc18xx_get_pintsel(void __iomem *addr, u32 val, int *arg)
-{
- u32 reg_val;
- int i;
-
- reg_val = readl(addr);
- for (i = 0; i < LPC18XX_SCU_IRQ_PER_PINTSEL; i++) {
- if ((reg_val & LPC18XX_SCU_PINTSEL_VAL_MASK) == val)
- return 0;
-
- reg_val >>= BITS_PER_BYTE;
- *arg += 1;
- }
-
- return -EINVAL;
-}
-
-static u32 lpc18xx_gpio_to_pintsel_val(int gpio)
-{
- unsigned int gpio_port, gpio_pin;
-
- gpio_port = gpio / LPC18XX_GPIO_PINS_PER_PORT;
- gpio_pin = gpio % LPC18XX_GPIO_PINS_PER_PORT;
-
- return gpio_pin | (gpio_port << LPC18XX_SCU_PINTSEL_PORT_SHIFT);
-}
-
-static int lpc18xx_pconf_get_gpio_pin_int(struct pinctrl_dev *pctldev,
- int *arg, unsigned pin)
-{
- struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
- int gpio, ret;
- u32 val;
-
- gpio = lpc18xx_pin_to_gpio(pctldev, pin);
- if (gpio < 0)
- return -ENOTSUPP;
-
- val = lpc18xx_gpio_to_pintsel_val(gpio);
-
- /*
- * Check if this pin has been enabled as a interrupt in any of the two
- * PINTSEL registers. *arg indicates which interrupt number (0-7).
- */
- *arg = 0;
- ret = lpc18xx_get_pintsel(scu->base + LPC18XX_SCU_PINTSEL0, val, arg);
- if (ret == 0)
- return ret;
-
- return lpc18xx_get_pintsel(scu->base + LPC18XX_SCU_PINTSEL1, val, arg);
-}
-
-static int lpc18xx_pconf_get_pin(struct pinctrl_dev *pctldev, unsigned param,
- int *arg, u32 reg, unsigned pin,
- struct lpc18xx_pin_caps *pin_cap)
-{
- switch (param) {
- case PIN_CONFIG_BIAS_DISABLE:
- if ((!(reg & LPC18XX_SCU_PIN_EPD)) && (reg & LPC18XX_SCU_PIN_EPUN))
- ;
- else
- return -EINVAL;
- break;
-
- case PIN_CONFIG_BIAS_PULL_UP:
- if (reg & LPC18XX_SCU_PIN_EPUN)
- return -EINVAL;
- else
- *arg = 1;
- break;
-
- case PIN_CONFIG_BIAS_PULL_DOWN:
- if (reg & LPC18XX_SCU_PIN_EPD)
- *arg = 1;
- else
- return -EINVAL;
- break;
-
- case PIN_CONFIG_INPUT_ENABLE:
- if (reg & LPC18XX_SCU_PIN_EZI)
- *arg = 1;
- else
- return -EINVAL;
- break;
-
- case PIN_CONFIG_SLEW_RATE:
- if (pin_cap->type == TYPE_HD)
- return -ENOTSUPP;
-
- if (reg & LPC18XX_SCU_PIN_EHS)
- *arg = 1;
- else
- *arg = 0;
- break;
-
- case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
- if (reg & LPC18XX_SCU_PIN_ZIF)
- return -EINVAL;
- else
- *arg = 1;
- break;
-
- case PIN_CONFIG_DRIVE_STRENGTH:
- if (pin_cap->type != TYPE_HD)
- return -ENOTSUPP;
-
- *arg = (reg & LPC18XX_SCU_PIN_EHD_MASK) >> LPC18XX_SCU_PIN_EHD_POS;
- switch (*arg) {
- case 3: *arg += 5;
- fallthrough;
- case 2: *arg += 5;
- fallthrough;
- case 1: *arg += 3;
- fallthrough;
- case 0: *arg += 4;
- }
- break;
-
- case PIN_CONFIG_GPIO_PIN_INT:
- return lpc18xx_pconf_get_gpio_pin_int(pctldev, arg, pin);
-
- default:
- return -ENOTSUPP;
- }
-
- return 0;
-}
-
-static struct lpc18xx_pin_caps *lpc18xx_get_pin_caps(unsigned pin)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(lpc18xx_pins); i++) {
- if (lpc18xx_pins[i].number == pin)
- return lpc18xx_pins[i].drv_data;
- }
-
- return NULL;
-}
-
-static int lpc18xx_pconf_get(struct pinctrl_dev *pctldev, unsigned pin,
- unsigned long *config)
-{
- struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
- enum pin_config_param param = pinconf_to_config_param(*config);
- struct lpc18xx_pin_caps *pin_cap;
- int ret, arg = 0;
- u32 reg;
-
- pin_cap = lpc18xx_get_pin_caps(pin);
- if (!pin_cap)
- return -EINVAL;
-
- reg = readl(scu->base + pin_cap->offset);
-
- if (pin_cap->type == TYPE_I2C0)
- ret = lpc18xx_pconf_get_i2c0(param, &arg, reg, pin);
- else if (pin_cap->type == TYPE_USB1)
- ret = lpc18xx_pconf_get_usb1(param, &arg, reg);
- else
- ret = lpc18xx_pconf_get_pin(pctldev, param, &arg, reg, pin, pin_cap);
-
- if (ret < 0)
- return ret;
-
- *config = pinconf_to_config_packed(param, (u16)arg);
-
- return 0;
-}
-
-static int lpc18xx_pconf_set_usb1(struct pinctrl_dev *pctldev,
- enum pin_config_param param,
- u32 param_val, u32 *reg)
-{
- switch (param) {
- case PIN_CONFIG_MODE_LOW_POWER:
- if (param_val)
- *reg &= ~LPC18XX_SCU_USB1_EPWR;
- else
- *reg |= LPC18XX_SCU_USB1_EPWR;
- break;
-
- case PIN_CONFIG_BIAS_DISABLE:
- *reg &= ~LPC18XX_SCU_USB1_EPD;
- break;
-
- case PIN_CONFIG_BIAS_PULL_DOWN:
- *reg |= LPC18XX_SCU_USB1_EPD;
- break;
-
- default:
- dev_err(pctldev->dev, "Property not supported\n");
- return -ENOTSUPP;
- }
-
- return 0;
-}
-
-static int lpc18xx_pconf_set_i2c0(struct pinctrl_dev *pctldev,
- enum pin_config_param param,
- u32 param_val, u32 *reg,
- unsigned pin)
-{
- u8 shift;
-
- if (pin == PIN_I2C0_SCL)
- shift = LPC18XX_SCU_I2C0_SCL_SHIFT;
- else
- shift = LPC18XX_SCU_I2C0_SDA_SHIFT;
-
- switch (param) {
- case PIN_CONFIG_INPUT_ENABLE:
- if (param_val)
- *reg |= (LPC18XX_SCU_I2C0_EZI << shift);
- else
- *reg &= ~(LPC18XX_SCU_I2C0_EZI << shift);
- break;
-
- case PIN_CONFIG_SLEW_RATE:
- if (param_val)
- *reg |= (LPC18XX_SCU_I2C0_EHD << shift);
- else
- *reg &= ~(LPC18XX_SCU_I2C0_EHD << shift);
- break;
-
- case PIN_CONFIG_INPUT_SCHMITT:
- if (param_val == 3)
- *reg |= (LPC18XX_SCU_I2C0_EFP << shift);
- else if (param_val == 50)
- *reg &= ~(LPC18XX_SCU_I2C0_EFP << shift);
- else
- return -ENOTSUPP;
- break;
-
- case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
- if (param_val)
- *reg &= ~(LPC18XX_SCU_I2C0_ZIF << shift);
- else
- *reg |= (LPC18XX_SCU_I2C0_ZIF << shift);
- break;
-
- default:
- dev_err(pctldev->dev, "Property not supported\n");
- return -ENOTSUPP;
- }
-
- return 0;
-}
-
-static int lpc18xx_pconf_set_gpio_pin_int(struct pinctrl_dev *pctldev,
- u32 param_val, unsigned pin)
-{
- struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
- u32 val, reg_val, reg_offset = LPC18XX_SCU_PINTSEL0;
- int gpio;
-
- if (param_val >= LPC18XX_GPIO_PIN_INT_MAX)
- return -EINVAL;
-
- gpio = lpc18xx_pin_to_gpio(pctldev, pin);
- if (gpio < 0)
- return -ENOTSUPP;
-
- val = lpc18xx_gpio_to_pintsel_val(gpio);
-
- reg_offset += (param_val / LPC18XX_SCU_IRQ_PER_PINTSEL) * sizeof(u32);
-
- reg_val = readl(scu->base + reg_offset);
- reg_val &= ~LPC18XX_SCU_PINTSEL_VAL(LPC18XX_SCU_PINTSEL_VAL_MASK, param_val);
- reg_val |= LPC18XX_SCU_PINTSEL_VAL(val, param_val);
- writel(reg_val, scu->base + reg_offset);
-
- return 0;
-}
-
-static int lpc18xx_pconf_set_pin(struct pinctrl_dev *pctldev, unsigned param,
- u32 param_val, u32 *reg, unsigned pin,
- struct lpc18xx_pin_caps *pin_cap)
-{
- switch (param) {
- case PIN_CONFIG_BIAS_DISABLE:
- *reg &= ~LPC18XX_SCU_PIN_EPD;
- *reg |= LPC18XX_SCU_PIN_EPUN;
- break;
-
- case PIN_CONFIG_BIAS_PULL_UP:
- *reg &= ~LPC18XX_SCU_PIN_EPUN;
- break;
-
- case PIN_CONFIG_BIAS_PULL_DOWN:
- *reg |= LPC18XX_SCU_PIN_EPD;
- break;
-
- case PIN_CONFIG_INPUT_ENABLE:
- if (param_val)
- *reg |= LPC18XX_SCU_PIN_EZI;
- else
- *reg &= ~LPC18XX_SCU_PIN_EZI;
- break;
-
- case PIN_CONFIG_SLEW_RATE:
- if (pin_cap->type == TYPE_HD) {
- dev_err(pctldev->dev, "Slew rate unsupported on high-drive pins\n");
- return -ENOTSUPP;
- }
-
- if (param_val == 0)
- *reg &= ~LPC18XX_SCU_PIN_EHS;
- else
- *reg |= LPC18XX_SCU_PIN_EHS;
- break;
-
- case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
- if (param_val)
- *reg &= ~LPC18XX_SCU_PIN_ZIF;
- else
- *reg |= LPC18XX_SCU_PIN_ZIF;
- break;
-
- case PIN_CONFIG_DRIVE_STRENGTH:
- if (pin_cap->type != TYPE_HD) {
- dev_err(pctldev->dev, "Drive strength available only on high-drive pins\n");
- return -ENOTSUPP;
- }
- *reg &= ~LPC18XX_SCU_PIN_EHD_MASK;
-
- switch (param_val) {
- case 20: param_val -= 5;
- fallthrough;
- case 14: param_val -= 5;
- fallthrough;
- case 8: param_val -= 3;
- fallthrough;
- case 4: param_val -= 4;
- break;
- default:
- dev_err(pctldev->dev, "Drive strength %u unsupported\n", param_val);
- return -ENOTSUPP;
- }
- *reg |= param_val << LPC18XX_SCU_PIN_EHD_POS;
- break;
-
- case PIN_CONFIG_GPIO_PIN_INT:
- return lpc18xx_pconf_set_gpio_pin_int(pctldev, param_val, pin);
-
- default:
- dev_err(pctldev->dev, "Property not supported\n");
- return -ENOTSUPP;
- }
-
- return 0;
-}
-
-static int lpc18xx_pconf_set(struct pinctrl_dev *pctldev, unsigned pin,
- unsigned long *configs, unsigned num_configs)
-{
- struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
- struct lpc18xx_pin_caps *pin_cap;
- enum pin_config_param param;
- u32 param_val;
- u32 reg;
- int ret;
- int i;
-
- pin_cap = lpc18xx_get_pin_caps(pin);
- if (!pin_cap)
- return -EINVAL;
-
- reg = readl(scu->base + pin_cap->offset);
-
- for (i = 0; i < num_configs; i++) {
- param = pinconf_to_config_param(configs[i]);
- param_val = pinconf_to_config_argument(configs[i]);
-
- if (pin_cap->type == TYPE_I2C0)
- ret = lpc18xx_pconf_set_i2c0(pctldev, param, param_val, ®, pin);
- else if (pin_cap->type == TYPE_USB1)
- ret = lpc18xx_pconf_set_usb1(pctldev, param, param_val, ®);
- else
- ret = lpc18xx_pconf_set_pin(pctldev, param, param_val, ®, pin, pin_cap);
-
- if (ret)
- return ret;
- }
-
- writel(reg, scu->base + pin_cap->offset);
-
- return 0;
-}
-
-static const struct pinconf_ops lpc18xx_pconf_ops = {
- .is_generic = true,
- .pin_config_get = lpc18xx_pconf_get,
- .pin_config_set = lpc18xx_pconf_set,
-};
-
-static int lpc18xx_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
-{
- return ARRAY_SIZE(lpc18xx_function_names);
-}
-
-static const char *lpc18xx_pmx_get_func_name(struct pinctrl_dev *pctldev,
- unsigned function)
-{
- return lpc18xx_function_names[function];
-}
-
-static int lpc18xx_pmx_get_func_groups(struct pinctrl_dev *pctldev,
- unsigned function,
- const char *const **groups,
- unsigned *const num_groups)
-{
- struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
-
- *groups = scu->func[function].groups;
- *num_groups = scu->func[function].ngroups;
-
- return 0;
-}
-
-static int lpc18xx_pmx_set(struct pinctrl_dev *pctldev, unsigned function,
- unsigned group)
-{
- struct lpc18xx_scu_data *scu = pinctrl_dev_get_drvdata(pctldev);
- struct lpc18xx_pin_caps *pin = lpc18xx_pins[group].drv_data;
- int func;
- u32 reg;
-
- /* Dedicated USB1 and I2C0 pins doesn't support muxing */
- if (pin->type == TYPE_USB1) {
- if (function == FUNC_USB1)
- return 0;
-
- goto fail;
- }
-
- if (pin->type == TYPE_I2C0) {
- if (function == FUNC_I2C0)
- return 0;
-
- goto fail;
- }
-
- if (function == FUNC_ADC && (pin->analog & LPC18XX_ANALOG_PIN)) {
- u32 offset;
-
- writel(LPC18XX_SCU_ANALOG_PIN_CFG, scu->base + pin->offset);
-
- if (LPC18XX_ANALOG_ADC(pin->analog) == 0)
- offset = LPC18XX_SCU_REG_ENAIO0;
- else
- offset = LPC18XX_SCU_REG_ENAIO1;
-
- reg = readl(scu->base + offset);
- reg |= pin->analog & LPC18XX_ANALOG_BIT_MASK;
- writel(reg, scu->base + offset);
-
- return 0;
- }
-
- if (function == FUNC_DAC && (pin->analog & LPC18XX_ANALOG_PIN)) {
- writel(LPC18XX_SCU_ANALOG_PIN_CFG, scu->base + pin->offset);
-
- reg = readl(scu->base + LPC18XX_SCU_REG_ENAIO2);
- reg |= LPC18XX_SCU_REG_ENAIO2_DAC;
- writel(reg, scu->base + LPC18XX_SCU_REG_ENAIO2);
-
- return 0;
- }
-
- for (func = 0; func < LPC18XX_SCU_FUNC_PER_PIN; func++) {
- if (function == pin->functions[func])
- break;
- }
-
- if (func >= LPC18XX_SCU_FUNC_PER_PIN)
- goto fail;
-
- reg = readl(scu->base + pin->offset);
- reg &= ~LPC18XX_SCU_PIN_MODE_MASK;
- writel(reg | func, scu->base + pin->offset);
-
- return 0;
-fail:
- dev_err(pctldev->dev, "Pin %s can't be %s\n", lpc18xx_pins[group].name,
- lpc18xx_function_names[function]);
- return -EINVAL;
-}
-
-static const struct pinmux_ops lpc18xx_pmx_ops = {
- .get_functions_count = lpc18xx_pmx_get_funcs_count,
- .get_function_name = lpc18xx_pmx_get_func_name,
- .get_function_groups = lpc18xx_pmx_get_func_groups,
- .set_mux = lpc18xx_pmx_set,
-};
-
-static int lpc18xx_pctl_get_groups_count(struct pinctrl_dev *pctldev)
-{
- return ARRAY_SIZE(lpc18xx_pins);
-}
-
-static const char *lpc18xx_pctl_get_group_name(struct pinctrl_dev *pctldev,
- unsigned group)
-{
- return lpc18xx_pins[group].name;
-}
-
-static int lpc18xx_pctl_get_group_pins(struct pinctrl_dev *pctldev,
- unsigned group,
- const unsigned **pins,
- unsigned *num_pins)
-{
- *pins = &lpc18xx_pins[group].number;
- *num_pins = 1;
-
- return 0;
-}
-
-static const struct pinctrl_ops lpc18xx_pctl_ops = {
- .get_groups_count = lpc18xx_pctl_get_groups_count,
- .get_group_name = lpc18xx_pctl_get_group_name,
- .get_group_pins = lpc18xx_pctl_get_group_pins,
- .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
- .dt_free_map = pinctrl_utils_free_map,
-};
-
-static const struct pinctrl_desc lpc18xx_scu_desc = {
- .name = "lpc18xx/43xx-scu",
- .pins = lpc18xx_pins,
- .npins = ARRAY_SIZE(lpc18xx_pins),
- .pctlops = &lpc18xx_pctl_ops,
- .pmxops = &lpc18xx_pmx_ops,
- .confops = &lpc18xx_pconf_ops,
- .num_custom_params = ARRAY_SIZE(lpc18xx_params),
- .custom_params = lpc18xx_params,
-#ifdef CONFIG_DEBUG_FS
- .custom_conf_items = lpc18xx_conf_items,
-#endif
- .owner = THIS_MODULE,
-};
-
-static bool lpc18xx_valid_pin_function(unsigned pin, unsigned function)
-{
- struct lpc18xx_pin_caps *p = lpc18xx_pins[pin].drv_data;
- int i;
-
- if (function == FUNC_DAC && p->analog == DAC)
- return true;
-
- if (function == FUNC_ADC && p->analog)
- return true;
-
- if (function == FUNC_I2C0 && p->type == TYPE_I2C0)
- return true;
-
- if (function == FUNC_USB1 && p->type == TYPE_USB1)
- return true;
-
- for (i = 0; i < LPC18XX_SCU_FUNC_PER_PIN; i++) {
- if (function == p->functions[i])
- return true;
- }
-
- return false;
-}
-
-static int lpc18xx_create_group_func_map(struct device *dev,
- struct lpc18xx_scu_data *scu)
-{
- u16 pins[ARRAY_SIZE(lpc18xx_pins)];
- int func, ngroups, i;
-
- for (func = 0; func < FUNC_MAX; func++) {
- for (ngroups = 0, i = 0; i < ARRAY_SIZE(lpc18xx_pins); i++) {
- if (lpc18xx_valid_pin_function(i, func))
- pins[ngroups++] = i;
- }
-
- scu->func[func].ngroups = ngroups;
- scu->func[func].groups = devm_kcalloc(dev,
- ngroups, sizeof(char *),
- GFP_KERNEL);
- if (!scu->func[func].groups)
- return -ENOMEM;
-
- for (i = 0; i < ngroups; i++)
- scu->func[func].groups[i] = lpc18xx_pins[pins[i]].name;
- }
-
- return 0;
-}
-
-static int lpc18xx_scu_probe(struct platform_device *pdev)
-{
- struct lpc18xx_scu_data *scu;
- int ret;
-
- scu = devm_kzalloc(&pdev->dev, sizeof(*scu), GFP_KERNEL);
- if (!scu)
- return -ENOMEM;
-
- scu->base = devm_platform_ioremap_resource(pdev, 0);
- if (IS_ERR(scu->base))
- return PTR_ERR(scu->base);
-
- scu->clk = devm_clk_get(&pdev->dev, NULL);
- if (IS_ERR(scu->clk)) {
- dev_err(&pdev->dev, "Input clock not found.\n");
- return PTR_ERR(scu->clk);
- }
-
- ret = lpc18xx_create_group_func_map(&pdev->dev, scu);
- if (ret) {
- dev_err(&pdev->dev, "Unable to create group func map.\n");
- return ret;
- }
-
- ret = clk_prepare_enable(scu->clk);
- if (ret) {
- dev_err(&pdev->dev, "Unable to enable clock.\n");
- return ret;
- }
-
- platform_set_drvdata(pdev, scu);
-
- scu->pctl = devm_pinctrl_register(&pdev->dev, &lpc18xx_scu_desc, scu);
- if (IS_ERR(scu->pctl)) {
- dev_err(&pdev->dev, "Could not register pinctrl driver\n");
- clk_disable_unprepare(scu->clk);
- return PTR_ERR(scu->pctl);
- }
-
- return 0;
-}
-
-static const struct of_device_id lpc18xx_scu_match[] = {
- { .compatible = "nxp,lpc1850-scu" },
- {},
-};
-
-static struct platform_driver lpc18xx_scu_driver = {
- .probe = lpc18xx_scu_probe,
- .driver = {
- .name = "lpc18xx-scu",
- .of_match_table = lpc18xx_scu_match,
- .suppress_bind_attrs = true,
- },
-};
-builtin_platform_driver(lpc18xx_scu_driver);
--
2.43.0
^ permalink raw reply related
* [PATCH 09/11] ARM: configs: lpc*: Remove NOMMU platform support
From: Frank.Li @ 2026-06-19 15:41 UTC (permalink / raw)
To: Arnd Bergmann, Sascha Hauer, Pengutronix Kernel Team,
Stefan Agner, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Russell King, Abel Vesa, Peng Fan,
Michael Turquette, Stephen Boyd, Brian Masney, Dong Aisheng,
Jacky Bai, NXP S32 Linux Team, Linus Walleij, Vladimir Zapolskiy,
Piotr Wojtaszczyk, Kees Cook, Gustavo A. R. Silva
Cc: linux-arm-kernel, imx, devicetree, linux-kernel, linux-clk,
linux-gpio, linux-hardening, Frank Li
In-Reply-To: <20260619-dts_cleanup_arm_mcore-v1-0-0101795a2662@nxp.com>
From: Frank Li <Frank.Li@nxp.com>
Commercial users and hardware vendors migrated to Zephyr or other RTOS
solutions years ago, leaving the NOMMU platform support effectively
unused and unmaintained.
Remove the obsolete support to reduce maintenance burden and simplify the
NXP/Freescale platform code.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm/configs/lpc18xx_defconfig | 158 ------------------------------
arch/arm/configs/lpc32xx_defconfig | 192 -------------------------------------
2 files changed, 350 deletions(-)
diff --git a/arch/arm/configs/lpc18xx_defconfig b/arch/arm/configs/lpc18xx_defconfig
deleted file mode 100644
index f142a6637edee..0000000000000
--- a/arch/arm/configs/lpc18xx_defconfig
+++ /dev/null
@@ -1,158 +0,0 @@
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_BLK_DEV_INITRD=y
-# CONFIG_RD_BZIP2 is not set
-# CONFIG_RD_LZMA is not set
-# CONFIG_RD_XZ is not set
-# CONFIG_RD_LZO is not set
-# CONFIG_RD_LZ4 is not set
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-# CONFIG_UID16 is not set
-CONFIG_BASE_SMALL=y
-# CONFIG_FUTEX is not set
-# CONFIG_EPOLL is not set
-# CONFIG_SIGNALFD is not set
-# CONFIG_EVENTFD is not set
-# CONFIG_AIO is not set
-CONFIG_EXPERT=y
-# CONFIG_MMU is not set
-CONFIG_ARCH_LPC18XX=y
-CONFIG_SET_MEM_PARAM=y
-CONFIG_DRAM_BASE=0x28000000
-CONFIG_DRAM_SIZE=0x02000000
-CONFIG_FLASH_MEM_BASE=0x1b000000
-CONFIG_FLASH_SIZE=0x00080000
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_BINFMT_FLAT=y
-CONFIG_BINFMT_ZFLAT=y
-# CONFIG_COREDUMP is not set
-# CONFIG_VM_EVENT_COUNTERS is not set
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_IPV6 is not set
-# CONFIG_WIRELESS is not set
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_PHYSMAP_OF=y
-CONFIG_MTD_SPI_NOR=y
-# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
-CONFIG_SPI_NXP_SPIFI=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_SRAM=y
-CONFIG_EEPROM_AT24=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_NETDEVICES=y
-# CONFIG_NET_VENDOR_ARC is not set
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CIRRUS is not set
-# CONFIG_NET_VENDOR_FARADAY is not set
-# CONFIG_NET_VENDOR_HISILICON is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-# CONFIG_NET_VENDOR_QUALCOMM is not set
-# CONFIG_NET_VENDOR_ROCKER is not set
-# CONFIG_NET_VENDOR_SAMSUNG is not set
-# CONFIG_NET_VENDOR_SEEQ is not set
-# CONFIG_NET_VENDOR_SMSC is not set
-CONFIG_STMMAC_ETH=y
-# CONFIG_NET_VENDOR_VIA is not set
-# CONFIG_NET_VENDOR_WIZNET is not set
-CONFIG_SMSC_PHY=y
-# CONFIG_USB_NET_DRIVERS is not set
-# CONFIG_WLAN is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_GPIO=y
-CONFIG_KEYBOARD_GPIO_POLLED=y
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_UNIX98_PTYS is not set
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIAL_NONSTANDARD=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C_LPC2K=y
-CONFIG_SPI=y
-CONFIG_SPI_PL022=y
-CONFIG_GPIOLIB=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_74XX_MMIO=y
-CONFIG_GPIO_PCF857X=y
-CONFIG_SENSORS_JC42=y
-CONFIG_SENSORS_LM75=y
-CONFIG_WATCHDOG=y
-CONFIG_LPC18XX_WATCHDOG=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_DRM=y
-CONFIG_DRM_PL111=y
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_ROOT_HUB_TT=y
-CONFIG_USB_EHCI_HCD_PLATFORM=y
-CONFIG_USB_STORAGE=y
-CONFIG_MMC=y
-CONFIG_MMC_DW=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_PCA9532=y
-CONFIG_LEDS_PCA9532_GPIO=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_DRV_LPC24XX=y
-CONFIG_DMADEVICES=y
-CONFIG_AMBA_PL08X=y
-CONFIG_LPC18XX_DMAMUX=y
-CONFIG_MEMORY=y
-CONFIG_ARM_PL172_MPMC=y
-CONFIG_IIO=y
-CONFIG_MMA7455_I2C=y
-CONFIG_LPC18XX_ADC=y
-CONFIG_LPC18XX_DAC=y
-CONFIG_IIO_SYSFS_TRIGGER=y
-CONFIG_PWM=y
-CONFIG_PWM_LPC18XX_SCT=y
-CONFIG_PHY_LPC18XX_USB_OTG=y
-CONFIG_NVMEM_LPC18XX_EEPROM=y
-CONFIG_EXT2_FS=y
-# CONFIG_FILE_LOCKING is not set
-# CONFIG_DNOTIFY is not set
-# CONFIG_INOTIFY_USER is not set
-CONFIG_JFFS2_FS=y
-# CONFIG_NETWORK_FILESYSTEMS is not set
-CONFIG_PRINTK_TIME=y
-# CONFIG_ENABLE_MUST_CHECK is not set
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_FS=y
-# CONFIG_SLUB_DEBUG is not set
-# CONFIG_SCHED_DEBUG is not set
-CONFIG_DEBUG_LL=y
-CONFIG_EARLY_PRINTK=y
diff --git a/arch/arm/configs/lpc32xx_defconfig b/arch/arm/configs/lpc32xx_defconfig
deleted file mode 100644
index b9e2e603cd95e..0000000000000
--- a/arch/arm/configs/lpc32xx_defconfig
+++ /dev/null
@@ -1,192 +0,0 @@
-CONFIG_SYSVIPC=y
-CONFIG_NO_HZ_IDLE=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_LOG_BUF_SHIFT=16
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_CC_OPTIMIZE_FOR_SIZE=y
-CONFIG_EXPERT=y
-# CONFIG_ARCH_MULTI_V7 is not set
-CONFIG_ARCH_LPC32XX=y
-CONFIG_AEABI=y
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ATAG_DTB_COMPAT=y
-CONFIG_CMDLINE="console=ttyS0,115200n81 root=/dev/ram0"
-CONFIG_CPU_IDLE=y
-CONFIG_VFP=y
-CONFIG_JUMP_LABEL=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_DIAG is not set
-# CONFIG_WIRELESS is not set
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-# CONFIG_FW_LOADER is not set
-CONFIG_MTD=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_RAW_NAND=y
-CONFIG_MTD_NAND_SLC_LPC32XX=y
-CONFIG_MTD_NAND_MLC_LPC32XX=y
-CONFIG_MTD_UBI=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_CRYPTOLOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=1
-CONFIG_BLK_DEV_RAM_SIZE=16384
-CONFIG_SRAM=y
-CONFIG_EEPROM_AT24=y
-CONFIG_EEPROM_AT25=y
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_NETDEVICES=y
-# CONFIG_NET_VENDOR_BROADCOM is not set
-# CONFIG_NET_VENDOR_CIRRUS is not set
-# CONFIG_NET_VENDOR_FARADAY is not set
-# CONFIG_NET_VENDOR_INTEL is not set
-# CONFIG_NET_VENDOR_MARVELL is not set
-# CONFIG_NET_VENDOR_MICREL is not set
-# CONFIG_NET_VENDOR_MICROCHIP is not set
-# CONFIG_NET_VENDOR_NATSEMI is not set
-CONFIG_LPC_ENET=y
-# CONFIG_NET_VENDOR_SEEQ is not set
-# CONFIG_NET_VENDOR_SMSC is not set
-# CONFIG_NET_VENDOR_STMICRO is not set
-CONFIG_SMSC_PHY=y
-# CONFIG_WLAN is not set
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
-CONFIG_KEYBOARD_GPIO=y
-CONFIG_KEYBOARD_GPIO_POLLED=y
-CONFIG_KEYBOARD_LPC32XX=y
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_TOUCHSCREEN_LPC32XX=y
-CONFIG_SERIO_LIBPS2=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_OF_PLATFORM=y
-CONFIG_SERIAL_HS_LPC32XX=y
-CONFIG_SERIAL_HS_LPC32XX_CONSOLE=y
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_PNX=y
-CONFIG_SPI=y
-CONFIG_SPI_PL022=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_GENERIC_PLATFORM=y
-CONFIG_GPIO_LPC32XX=y
-CONFIG_GPIO_PCA953X=y
-CONFIG_GPIO_PCF857X=y
-CONFIG_SENSORS_DS620=y
-CONFIG_SENSORS_MAX6639=y
-CONFIG_WATCHDOG=y
-CONFIG_PNX4008_WATCHDOG=y
-CONFIG_REGULATOR=y
-CONFIG_REGULATOR_FIXED_VOLTAGE=y
-CONFIG_DRM=y
-CONFIG_DRM_PANEL_SIMPLE=y
-CONFIG_DRM_PANEL_EDP=y
-CONFIG_DRM_PL111=y
-CONFIG_FB_MODE_HELPERS=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-# CONFIG_LOGO_LINUX_MONO is not set
-# CONFIG_LOGO_LINUX_VGA16 is not set
-CONFIG_SOUND=y
-CONFIG_SND=y
-# CONFIG_SND_VERBOSE_PROCFS is not set
-CONFIG_SND_DEBUG=y
-CONFIG_SND_DEBUG_VERBOSE=y
-CONFIG_SND_SEQUENCER=y
-# CONFIG_SND_DRIVERS is not set
-# CONFIG_SND_ARM is not set
-# CONFIG_SND_SPI is not set
-CONFIG_SND_SOC=y
-CONFIG_USB=y
-CONFIG_USB_OHCI_HCD=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_LPC32XX=y
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_MMC=y
-CONFIG_MMC_ARMMMCI=y
-CONFIG_MMC_SPI=y
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=y
-CONFIG_LEDS_PCA9532=y
-CONFIG_LEDS_PCA9532_GPIO=y
-CONFIG_LEDS_GPIO=y
-CONFIG_LEDS_PWM=y
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=y
-CONFIG_LEDS_TRIGGER_HEARTBEAT=y
-CONFIG_LEDS_TRIGGER_BACKLIGHT=y
-CONFIG_LEDS_TRIGGER_GPIO=y
-CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
-CONFIG_RTC_CLASS=y
-CONFIG_RTC_INTF_DEV_UIE_EMUL=y
-CONFIG_RTC_DRV_DS1374=y
-CONFIG_RTC_DRV_PCF8563=y
-CONFIG_RTC_DRV_LPC32XX=y
-CONFIG_DMADEVICES=y
-CONFIG_AMBA_PL08X=y
-CONFIG_STAGING=y
-CONFIG_MEMORY=y
-CONFIG_ARM_PL172_MPMC=y
-CONFIG_IIO=y
-CONFIG_LPC32XX_ADC=y
-CONFIG_MAX517=y
-CONFIG_PWM=y
-CONFIG_PWM_LPC32XX=y
-CONFIG_EXT2_FS=y
-CONFIG_AUTOFS_FS=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_JFFS2_FS_WBUF_VERIFY=y
-CONFIG_UBIFS_FS=y
-CONFIG_CRAMFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V4=y
-CONFIG_NFS_V4_1=y
-CONFIG_NFS_V4_2=y
-CONFIG_ROOT_NFS=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_UTF8=y
-# CONFIG_CRYPTO_HW is not set
-CONFIG_PRINTK_TIME=y
-CONFIG_DYNAMIC_DEBUG=y
-CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
-CONFIG_GDB_SCRIPTS=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_FS=y
-CONFIG_PANIC_ON_OOPS=y
-CONFIG_PANIC_TIMEOUT=5
-# CONFIG_SCHED_DEBUG is not set
-# CONFIG_DEBUG_PREEMPT is not set
-# CONFIG_FTRACE is not set
-CONFIG_DEBUG_LL=y
-CONFIG_EARLY_PRINTK=y
--
2.43.0
^ permalink raw reply related
* [PATCH 06/11] ARM: imxrt_defconfig: Remove NOMMU platform support
From: Frank.Li @ 2026-06-19 15:41 UTC (permalink / raw)
To: Arnd Bergmann, Sascha Hauer, Pengutronix Kernel Team,
Stefan Agner, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Russell King, Abel Vesa, Peng Fan,
Michael Turquette, Stephen Boyd, Brian Masney, Dong Aisheng,
Jacky Bai, NXP S32 Linux Team, Linus Walleij, Vladimir Zapolskiy,
Piotr Wojtaszczyk, Kees Cook, Gustavo A. R. Silva
Cc: linux-arm-kernel, imx, devicetree, linux-kernel, linux-clk,
linux-gpio, linux-hardening, Frank Li
In-Reply-To: <20260619-dts_cleanup_arm_mcore-v1-0-0101795a2662@nxp.com>
From: Frank Li <Frank.Li@nxp.com>
Commercial users and hardware vendors migrated to Zephyr or other RTOS
solutions years ago, leaving the NOMMU platform support effectively
unused and unmaintained.
Remove the obsolete support to reduce maintenance burden and simplify the
i.MX platform code.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm/configs/imxrt_defconfig | 35 -----------------------------------
1 file changed, 35 deletions(-)
diff --git a/arch/arm/configs/imxrt_defconfig b/arch/arm/configs/imxrt_defconfig
deleted file mode 100644
index 52dba3762996c..0000000000000
--- a/arch/arm/configs/imxrt_defconfig
+++ /dev/null
@@ -1,35 +0,0 @@
-# CONFIG_LOCALVERSION_AUTO is not set
-CONFIG_BPF_SYSCALL=y
-CONFIG_SCHED_AUTOGROUP=y
-# CONFIG_MMU is not set
-CONFIG_ARCH_MXC=y
-CONFIG_SOC_IMXRT=y
-CONFIG_SET_MEM_PARAM=y
-CONFIG_DRAM_BASE=0x80000000
-CONFIG_DRAM_SIZE=0x02000000
-CONFIG_BINFMT_FLAT=y
-CONFIG_UEVENT_HELPER=y
-CONFIG_DEVTMPFS=y
-CONFIG_DEVTMPFS_MOUNT=y
-CONFIG_IMX_WEIM=y
-CONFIG_LEGACY_PTY_COUNT=2
-CONFIG_SERIAL_FSL_LPUART=y
-CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
-CONFIG_SERIAL_DEV_BUS=y
-CONFIG_PINCTRL_IMXRT1050=y
-CONFIG_GPIO_MXC=y
-CONFIG_MMC=y
-CONFIG_MMC_SDHCI=y
-CONFIG_MMC_SDHCI_PLTFM=y
-CONFIG_MMC_SDHCI_ESDHC_IMX=y
-CONFIG_DMADEVICES=y
-CONFIG_FSL_EDMA=y
-CONFIG_CLK_IMXRT1050=y
-CONFIG_EXT4_FS=y
-CONFIG_EXT4_FS_POSIX_ACL=y
-CONFIG_EXT4_FS_SECURITY=y
-CONFIG_VFAT_FS=y
-CONFIG_FAT_DEFAULT_UTF8=y
-CONFIG_EXFAT_FS=y
-CONFIG_NLS_ASCII=y
-CONFIG_NLS_UTF8=y
--
2.43.0
^ permalink raw reply related
* [PATCH 05/11] pinctrl: freescale: IMXRT: Remove NOMMU platform support
From: Frank.Li @ 2026-06-19 15:41 UTC (permalink / raw)
To: Arnd Bergmann, Sascha Hauer, Pengutronix Kernel Team,
Stefan Agner, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Russell King, Abel Vesa, Peng Fan,
Michael Turquette, Stephen Boyd, Brian Masney, Dong Aisheng,
Jacky Bai, NXP S32 Linux Team, Linus Walleij, Vladimir Zapolskiy,
Piotr Wojtaszczyk, Kees Cook, Gustavo A. R. Silva
Cc: linux-arm-kernel, imx, devicetree, linux-kernel, linux-clk,
linux-gpio, linux-hardening, Frank Li
In-Reply-To: <20260619-dts_cleanup_arm_mcore-v1-0-0101795a2662@nxp.com>
From: Frank Li <Frank.Li@nxp.com>
Commercial users and hardware vendors migrated to Zephyr or other RTOS
solutions years ago, leaving the NOMMU platform support effectively
unused and unmaintained.
Remove the obsolete support to reduce maintenance burden and simplify the
i.MX platform code.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
.../devicetree/bindings/pinctrl/fsl,imxrt1050.yaml | 79 -----
.../devicetree/bindings/pinctrl/fsl,imxrt1170.yaml | 77 -----
drivers/pinctrl/freescale/Kconfig | 16 -
drivers/pinctrl/freescale/Makefile | 2 -
drivers/pinctrl/freescale/pinctrl-imxrt1050.c | 309 ------------------
drivers/pinctrl/freescale/pinctrl-imxrt1170.c | 349 ---------------------
6 files changed, 832 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1050.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1050.yaml
deleted file mode 100644
index db5fe66ad8733..0000000000000
--- a/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1050.yaml
+++ /dev/null
@@ -1,79 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/pinctrl/fsl,imxrt1050.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Freescale IMXRT1050 IOMUX Controller
-
-maintainers:
- - Giulio Benetti <giulio.benetti@benettiengineering.com>
- - Jesse Taube <Mr.Bossman075@gmail.com>
-
-description:
- Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
- for common binding part and usage.
-
-properties:
- compatible:
- const: fsl,imxrt1050-iomuxc
-
- reg:
- maxItems: 1
-
-# Client device subnode's properties
-patternProperties:
- 'grp$':
- type: object
- description:
- Pinctrl node's client devices use subnodes for desired pin configuration.
- Client device subnodes use below standard properties.
-
- properties:
- fsl,pins:
- description:
- each entry consists of 6 integers and represents the mux and config
- setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
- mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
- be found in <arch/arm/boot/dts/imxrt1050-pinfunc.h>. The last
- integer CONFIG is the pad setting value like pull-up on this pin. Please
- refer to i.MXRT1050 Reference Manual for detailed CONFIG settings.
- $ref: /schemas/types.yaml#/definitions/uint32-matrix
- items:
- items:
- - description: |
- "mux_reg" indicates the offset of mux register.
- - description: |
- "conf_reg" indicates the offset of pad configuration register.
- - description: |
- "input_reg" indicates the offset of select input register.
- - description: |
- "mux_val" indicates the mux value to be applied.
- - description: |
- "input_val" indicates the select input value to be applied.
- - description: |
- "pad_setting" indicates the pad configuration value to be applied.
-
- required:
- - fsl,pins
-
- additionalProperties: false
-
-required:
- - compatible
- - reg
-
-additionalProperties: false
-
-examples:
- - |
- iomuxc: iomuxc@401f8000 {
- compatible = "fsl,imxrt1050-iomuxc";
- reg = <0x401f8000 0x4000>;
-
- pinctrl_lpuart1: lpuart1grp {
- fsl,pins =
- <0x0EC 0x2DC 0x000 0x2 0x0 0xf1>,
- <0x0F0 0x2E0 0x000 0x2 0x0 0xf1>;
- };
- };
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1170.yaml b/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1170.yaml
deleted file mode 100644
index 2e880b3e537c1..0000000000000
--- a/Documentation/devicetree/bindings/pinctrl/fsl,imxrt1170.yaml
+++ /dev/null
@@ -1,77 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/pinctrl/fsl,imxrt1170.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Freescale i.MXRT1170 IOMUX Controller
-
-maintainers:
- - Giulio Benetti <giulio.benetti@benettiengineering.com>
- - Jesse Taube <Mr.Bossman075@gmail.com>
-
-description:
- Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
- for common binding part and usage.
-
-properties:
- compatible:
- const: fsl,imxrt1170-iomuxc
-
- reg:
- maxItems: 1
-
-# Client device subnode's properties
-patternProperties:
- 'grp$':
- type: object
- description:
- Pinctrl node's client devices use subnodes for desired pin configuration.
- Client device subnodes use below standard properties.
-
- properties:
- fsl,pins:
- description:
- each entry consists of 6 integers and represents the mux and config
- setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
- mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
- be found in <arch/arm/boot/dts/imxrt1170-pinfunc.h>. The last
- integer CONFIG is the pad setting value like pull-up on this pin. Please
- refer to i.MXRT1170 Reference Manual for detailed CONFIG settings.
- $ref: /schemas/types.yaml#/definitions/uint32-matrix
- items:
- items:
- - description: |
- "mux_reg" indicates the offset of mux register.
- - description: |
- "conf_reg" indicates the offset of pad configuration register.
- - description: |
- "input_reg" indicates the offset of select input register.
- - description: |
- "mux_val" indicates the mux value to be applied.
- - description: |
- "input_val" indicates the select input value to be applied.
- - description: |
- "pad_setting" indicates the pad configuration value to be applied.
- required:
- - fsl,pins
-
- additionalProperties: false
-
-required:
- - compatible
- - reg
-
-additionalProperties: false
-
-examples:
- - |
- iomuxc: iomuxc@400e8000 {
- compatible = "fsl,imxrt1170-iomuxc";
- reg = <0x400e8000 0x4000>;
- pinctrl_lpuart1: lpuart1grp {
- fsl,pins =
- <0x16C 0x3B0 0x620 0x0 0x0 0xf1>,
- <0x170 0x3B4 0x61C 0x0 0x0 0xf1>;
- };
- };
diff --git a/drivers/pinctrl/freescale/Kconfig b/drivers/pinctrl/freescale/Kconfig
index fd53cf5bb843d..9baf222abdecf 100644
--- a/drivers/pinctrl/freescale/Kconfig
+++ b/drivers/pinctrl/freescale/Kconfig
@@ -229,15 +229,6 @@ config PINCTRL_IMX8ULP
help
Say Y here to enable the imx8ulp pinctrl driver
-config PINCTRL_IMXRT1050
- bool "IMXRT1050 pinctrl driver"
- depends on OF
- depends on SOC_IMXRT || COMPILE_TEST
- default SOC_IMXRT
- select PINCTRL_IMX
- help
- Say Y here to enable the imxrt1050 pinctrl driver
-
config PINCTRL_IMX91
tristate "IMX91 pinctrl driver"
depends on ARCH_MXC
@@ -276,10 +267,3 @@ config PINCTRL_IMX28
bool
select PINCTRL_MXS
-config PINCTRL_IMXRT1170
- bool "IMXRT1170 pinctrl driver"
- depends on OF
- depends on SOC_IMXRT || COMPILE_TEST
- select PINCTRL_IMX
- help
- Say Y here to enable the imxrt1170 pinctrl driver
diff --git a/drivers/pinctrl/freescale/Makefile b/drivers/pinctrl/freescale/Makefile
index d27085c2b4c45..72de53db68eb8 100644
--- a/drivers/pinctrl/freescale/Makefile
+++ b/drivers/pinctrl/freescale/Makefile
@@ -33,5 +33,3 @@ obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
obj-$(CONFIG_PINCTRL_IMX25) += pinctrl-imx25.o
obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o
-obj-$(CONFIG_PINCTRL_IMXRT1050) += pinctrl-imxrt1050.o
-obj-$(CONFIG_PINCTRL_IMXRT1170) += pinctrl-imxrt1170.o
diff --git a/drivers/pinctrl/freescale/pinctrl-imxrt1050.c b/drivers/pinctrl/freescale/pinctrl-imxrt1050.c
deleted file mode 100644
index f6435227d4fbb..0000000000000
--- a/drivers/pinctrl/freescale/pinctrl-imxrt1050.c
+++ /dev/null
@@ -1,309 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2020
- * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
- */
-
-#include <linux/err.h>
-#include <linux/init.h>
-#include <linux/of.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/platform_device.h>
-
-#include "pinctrl-imx.h"
-
-enum imxrt1050_pads {
- IMXRT1050_PAD_RESERVE0,
- IMXRT1050_PAD_RESERVE1,
- IMXRT1050_PAD_RESERVE2,
- IMXRT1050_PAD_RESERVE3,
- IMXRT1050_PAD_RESERVE4,
- IMXRT1050_PAD_EMC_00,
- IMXRT1050_PAD_EMC_01,
- IMXRT1050_PAD_EMC_02,
- IMXRT1050_PAD_EMC_03,
- IMXRT1050_PAD_EMC_04,
- IMXRT1050_PAD_EMC_05,
- IMXRT1050_PAD_EMC_06,
- IMXRT1050_PAD_EMC_07,
- IMXRT1050_PAD_EMC_08,
- IMXRT1050_PAD_EMC_09,
- IMXRT1050_PAD_EMC_10,
- IMXRT1050_PAD_EMC_11,
- IMXRT1050_PAD_EMC_12,
- IMXRT1050_PAD_EMC_13,
- IMXRT1050_PAD_EMC_14,
- IMXRT1050_PAD_EMC_15,
- IMXRT1050_PAD_EMC_16,
- IMXRT1050_PAD_EMC_17,
- IMXRT1050_PAD_EMC_18,
- IMXRT1050_PAD_EMC_19,
- IMXRT1050_PAD_EMC_20,
- IMXRT1050_PAD_EMC_21,
- IMXRT1050_PAD_EMC_22,
- IMXRT1050_PAD_EMC_23,
- IMXRT1050_PAD_EMC_24,
- IMXRT1050_PAD_EMC_25,
- IMXRT1050_PAD_EMC_26,
- IMXRT1050_PAD_EMC_27,
- IMXRT1050_PAD_EMC_28,
- IMXRT1050_PAD_EMC_29,
- IMXRT1050_PAD_EMC_30,
- IMXRT1050_PAD_EMC_31,
- IMXRT1050_PAD_EMC_32,
- IMXRT1050_PAD_EMC_33,
- IMXRT1050_PAD_EMC_34,
- IMXRT1050_PAD_EMC_35,
- IMXRT1050_PAD_EMC_36,
- IMXRT1050_PAD_EMC_37,
- IMXRT1050_PAD_EMC_38,
- IMXRT1050_PAD_EMC_39,
- IMXRT1050_PAD_EMC_40,
- IMXRT1050_PAD_EMC_41,
- IMXRT1050_PAD_AD_B0_00,
- IMXRT1050_PAD_AD_B0_01,
- IMXRT1050_PAD_AD_B0_02,
- IMXRT1050_PAD_AD_B0_03,
- IMXRT1050_PAD_AD_B0_04,
- IMXRT1050_PAD_AD_B0_05,
- IMXRT1050_PAD_AD_B0_06,
- IMXRT1050_PAD_AD_B0_07,
- IMXRT1050_PAD_AD_B0_08,
- IMXRT1050_PAD_AD_B0_09,
- IMXRT1050_PAD_AD_B0_10,
- IMXRT1050_PAD_AD_B0_11,
- IMXRT1050_PAD_AD_B0_12,
- IMXRT1050_PAD_AD_B0_13,
- IMXRT1050_PAD_AD_B0_14,
- IMXRT1050_PAD_AD_B0_15,
- IMXRT1050_PAD_AD_B1_00,
- IMXRT1050_PAD_AD_B1_01,
- IMXRT1050_PAD_AD_B1_02,
- IMXRT1050_PAD_AD_B1_03,
- IMXRT1050_PAD_AD_B1_04,
- IMXRT1050_PAD_AD_B1_05,
- IMXRT1050_PAD_AD_B1_06,
- IMXRT1050_PAD_AD_B1_07,
- IMXRT1050_PAD_AD_B1_08,
- IMXRT1050_PAD_AD_B1_09,
- IMXRT1050_PAD_AD_B1_10,
- IMXRT1050_PAD_AD_B1_11,
- IMXRT1050_PAD_AD_B1_12,
- IMXRT1050_PAD_AD_B1_13,
- IMXRT1050_PAD_AD_B1_14,
- IMXRT1050_PAD_AD_B1_15,
- IMXRT1050_PAD_B0_00,
- IMXRT1050_PAD_B0_01,
- IMXRT1050_PAD_B0_02,
- IMXRT1050_PAD_B0_03,
- IMXRT1050_PAD_B0_04,
- IMXRT1050_PAD_B0_05,
- IMXRT1050_PAD_B0_06,
- IMXRT1050_PAD_B0_07,
- IMXRT1050_PAD_B0_08,
- IMXRT1050_PAD_B0_09,
- IMXRT1050_PAD_B0_10,
- IMXRT1050_PAD_B0_11,
- IMXRT1050_PAD_B0_12,
- IMXRT1050_PAD_B0_13,
- IMXRT1050_PAD_B0_14,
- IMXRT1050_PAD_B0_15,
- IMXRT1050_PAD_B1_00,
- IMXRT1050_PAD_B1_01,
- IMXRT1050_PAD_B1_02,
- IMXRT1050_PAD_B1_03,
- IMXRT1050_PAD_B1_04,
- IMXRT1050_PAD_B1_05,
- IMXRT1050_PAD_B1_06,
- IMXRT1050_PAD_B1_07,
- IMXRT1050_PAD_B1_08,
- IMXRT1050_PAD_B1_09,
- IMXRT1050_PAD_B1_10,
- IMXRT1050_PAD_B1_11,
- IMXRT1050_PAD_B1_12,
- IMXRT1050_PAD_B1_13,
- IMXRT1050_PAD_B1_14,
- IMXRT1050_PAD_B1_15,
- IMXRT1050_PAD_SD_B0_00,
- IMXRT1050_PAD_SD_B0_01,
- IMXRT1050_PAD_SD_B0_02,
- IMXRT1050_PAD_SD_B0_03,
- IMXRT1050_PAD_SD_B0_04,
- IMXRT1050_PAD_SD_B0_05,
- IMXRT1050_PAD_SD_B1_00,
- IMXRT1050_PAD_SD_B1_01,
- IMXRT1050_PAD_SD_B1_02,
- IMXRT1050_PAD_SD_B1_03,
- IMXRT1050_PAD_SD_B1_04,
- IMXRT1050_PAD_SD_B1_05,
- IMXRT1050_PAD_SD_B1_06,
- IMXRT1050_PAD_SD_B1_07,
- IMXRT1050_PAD_SD_B1_08,
- IMXRT1050_PAD_SD_B1_09,
- IMXRT1050_PAD_SD_B1_10,
- IMXRT1050_PAD_SD_B1_11,
-};
-
-/* Pad names for the pinmux subsystem */
-static const struct pinctrl_pin_desc imxrt1050_pinctrl_pads[] = {
- IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE0),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE1),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE2),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE3),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_RESERVE4),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_00),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_01),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_02),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_03),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_04),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_05),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_06),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_07),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_08),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_09),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_10),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_11),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_12),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_13),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_14),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_15),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_16),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_17),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_18),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_19),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_20),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_21),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_22),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_23),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_24),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_25),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_26),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_27),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_28),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_29),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_30),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_31),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_32),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_33),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_34),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_35),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_36),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_37),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_38),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_39),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_40),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_EMC_41),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_00),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_01),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_02),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_03),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_04),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_05),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_06),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_07),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_08),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_09),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_10),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_11),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_12),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_13),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_14),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B0_15),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_00),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_01),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_02),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_03),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_04),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_05),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_06),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_07),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_08),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_09),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_10),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_11),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_12),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_13),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_14),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_AD_B1_15),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_00),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_01),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_02),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_03),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_04),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_05),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_06),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_07),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_08),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_09),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_10),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_11),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_12),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_13),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_14),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B0_15),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_00),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_01),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_02),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_03),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_04),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_05),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_06),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_07),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_08),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_09),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_10),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_11),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_12),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_13),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_14),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_B1_15),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B0_00),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B0_01),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B0_02),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B0_03),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B0_04),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B0_05),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_00),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_01),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_02),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_03),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_04),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_05),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_06),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_07),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_08),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_09),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_10),
- IMX_PINCTRL_PIN(IMXRT1050_PAD_SD_B1_11),
-};
-
-static const struct imx_pinctrl_soc_info imxrt1050_pinctrl_info = {
- .pins = imxrt1050_pinctrl_pads,
- .npins = ARRAY_SIZE(imxrt1050_pinctrl_pads),
- .gpr_compatible = "fsl,imxrt1050-iomuxc-gpr",
-};
-
-static const struct of_device_id imxrt1050_pinctrl_of_match[] = {
- { .compatible = "fsl,imxrt1050-iomuxc", .data = &imxrt1050_pinctrl_info, },
- { /* sentinel */ }
-};
-
-static int imxrt1050_pinctrl_probe(struct platform_device *pdev)
-{
- return imx_pinctrl_probe(pdev, &imxrt1050_pinctrl_info);
-}
-
-static struct platform_driver imxrt1050_pinctrl_driver = {
- .driver = {
- .name = "imxrt1050-pinctrl",
- .of_match_table = of_match_ptr(imxrt1050_pinctrl_of_match),
- .suppress_bind_attrs = true,
- },
- .probe = imxrt1050_pinctrl_probe,
-};
-
-static int __init imxrt1050_pinctrl_init(void)
-{
- return platform_driver_register(&imxrt1050_pinctrl_driver);
-}
-arch_initcall(imxrt1050_pinctrl_init);
diff --git a/drivers/pinctrl/freescale/pinctrl-imxrt1170.c b/drivers/pinctrl/freescale/pinctrl-imxrt1170.c
deleted file mode 100644
index d8857f329e253..0000000000000
--- a/drivers/pinctrl/freescale/pinctrl-imxrt1170.c
+++ /dev/null
@@ -1,349 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2022
- * Author(s): Jesse Taube <Mr.Bossman075@gmail.com>
- */
-
-#include <linux/err.h>
-#include <linux/init.h>
-#include <linux/of.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/platform_device.h>
-
-#include "pinctrl-imx.h"
-
-enum imxrt1170_pads {
- IMXRT1170_PAD_RESERVE0,
- IMXRT1170_PAD_RESERVE1,
- IMXRT1170_PAD_RESERVE2,
- IMXRT1170_PAD_RESERVE3,
- IMXRT1170_PAD_EMC_B1_00,
- IMXRT1170_PAD_EMC_B1_01,
- IMXRT1170_PAD_EMC_B1_02,
- IMXRT1170_PAD_EMC_B1_03,
- IMXRT1170_PAD_EMC_B1_04,
- IMXRT1170_PAD_EMC_B1_05,
- IMXRT1170_PAD_EMC_B1_06,
- IMXRT1170_PAD_EMC_B1_07,
- IMXRT1170_PAD_EMC_B1_08,
- IMXRT1170_PAD_EMC_B1_09,
- IMXRT1170_PAD_EMC_B1_10,
- IMXRT1170_PAD_EMC_B1_11,
- IMXRT1170_PAD_EMC_B1_12,
- IMXRT1170_PAD_EMC_B1_13,
- IMXRT1170_PAD_EMC_B1_14,
- IMXRT1170_PAD_EMC_B1_15,
- IMXRT1170_PAD_EMC_B1_16,
- IMXRT1170_PAD_EMC_B1_17,
- IMXRT1170_PAD_EMC_B1_18,
- IMXRT1170_PAD_EMC_B1_19,
- IMXRT1170_PAD_EMC_B1_20,
- IMXRT1170_PAD_EMC_B1_21,
- IMXRT1170_PAD_EMC_B1_22,
- IMXRT1170_PAD_EMC_B1_23,
- IMXRT1170_PAD_EMC_B1_24,
- IMXRT1170_PAD_EMC_B1_25,
- IMXRT1170_PAD_EMC_B1_26,
- IMXRT1170_PAD_EMC_B1_27,
- IMXRT1170_PAD_EMC_B1_28,
- IMXRT1170_PAD_EMC_B1_29,
- IMXRT1170_PAD_EMC_B1_30,
- IMXRT1170_PAD_EMC_B1_31,
- IMXRT1170_PAD_EMC_B1_32,
- IMXRT1170_PAD_EMC_B1_33,
- IMXRT1170_PAD_EMC_B1_34,
- IMXRT1170_PAD_EMC_B1_35,
- IMXRT1170_PAD_EMC_B1_36,
- IMXRT1170_PAD_EMC_B1_37,
- IMXRT1170_PAD_EMC_B1_38,
- IMXRT1170_PAD_EMC_B1_39,
- IMXRT1170_PAD_EMC_B1_40,
- IMXRT1170_PAD_EMC_B1_41,
- IMXRT1170_PAD_EMC_B2_00,
- IMXRT1170_PAD_EMC_B2_01,
- IMXRT1170_PAD_EMC_B2_02,
- IMXRT1170_PAD_EMC_B2_03,
- IMXRT1170_PAD_EMC_B2_04,
- IMXRT1170_PAD_EMC_B2_05,
- IMXRT1170_PAD_EMC_B2_06,
- IMXRT1170_PAD_EMC_B2_07,
- IMXRT1170_PAD_EMC_B2_08,
- IMXRT1170_PAD_EMC_B2_09,
- IMXRT1170_PAD_EMC_B2_10,
- IMXRT1170_PAD_EMC_B2_11,
- IMXRT1170_PAD_EMC_B2_12,
- IMXRT1170_PAD_EMC_B2_13,
- IMXRT1170_PAD_EMC_B2_14,
- IMXRT1170_PAD_EMC_B2_15,
- IMXRT1170_PAD_EMC_B2_16,
- IMXRT1170_PAD_EMC_B2_17,
- IMXRT1170_PAD_EMC_B2_18,
- IMXRT1170_PAD_EMC_B2_19,
- IMXRT1170_PAD_EMC_B2_20,
- IMXRT1170_PAD_AD_00,
- IMXRT1170_PAD_AD_01,
- IMXRT1170_PAD_AD_02,
- IMXRT1170_PAD_AD_03,
- IMXRT1170_PAD_AD_04,
- IMXRT1170_PAD_AD_05,
- IMXRT1170_PAD_AD_06,
- IMXRT1170_PAD_AD_07,
- IMXRT1170_PAD_AD_08,
- IMXRT1170_PAD_AD_09,
- IMXRT1170_PAD_AD_10,
- IMXRT1170_PAD_AD_11,
- IMXRT1170_PAD_AD_12,
- IMXRT1170_PAD_AD_13,
- IMXRT1170_PAD_AD_14,
- IMXRT1170_PAD_AD_15,
- IMXRT1170_PAD_AD_16,
- IMXRT1170_PAD_AD_17,
- IMXRT1170_PAD_AD_18,
- IMXRT1170_PAD_AD_19,
- IMXRT1170_PAD_AD_20,
- IMXRT1170_PAD_AD_21,
- IMXRT1170_PAD_AD_22,
- IMXRT1170_PAD_AD_23,
- IMXRT1170_PAD_AD_24,
- IMXRT1170_PAD_AD_25,
- IMXRT1170_PAD_AD_26,
- IMXRT1170_PAD_AD_27,
- IMXRT1170_PAD_AD_28,
- IMXRT1170_PAD_AD_29,
- IMXRT1170_PAD_AD_30,
- IMXRT1170_PAD_AD_31,
- IMXRT1170_PAD_AD_32,
- IMXRT1170_PAD_AD_33,
- IMXRT1170_PAD_AD_34,
- IMXRT1170_PAD_AD_35,
- IMXRT1170_PAD_SD_B1_00,
- IMXRT1170_PAD_SD_B1_01,
- IMXRT1170_PAD_SD_B1_02,
- IMXRT1170_PAD_SD_B1_03,
- IMXRT1170_PAD_SD_B1_04,
- IMXRT1170_PAD_SD_B1_05,
- IMXRT1170_PAD_SD_B2_00,
- IMXRT1170_PAD_SD_B2_01,
- IMXRT1170_PAD_SD_B2_02,
- IMXRT1170_PAD_SD_B2_03,
- IMXRT1170_PAD_SD_B2_04,
- IMXRT1170_PAD_SD_B2_05,
- IMXRT1170_PAD_SD_B2_06,
- IMXRT1170_PAD_SD_B2_07,
- IMXRT1170_PAD_SD_B2_08,
- IMXRT1170_PAD_SD_B2_09,
- IMXRT1170_PAD_SD_B2_10,
- IMXRT1170_PAD_SD_B2_11,
- IMXRT1170_PAD_DISP_B1_00,
- IMXRT1170_PAD_DISP_B1_01,
- IMXRT1170_PAD_DISP_B1_02,
- IMXRT1170_PAD_DISP_B1_03,
- IMXRT1170_PAD_DISP_B1_04,
- IMXRT1170_PAD_DISP_B1_05,
- IMXRT1170_PAD_DISP_B1_06,
- IMXRT1170_PAD_DISP_B1_07,
- IMXRT1170_PAD_DISP_B1_08,
- IMXRT1170_PAD_DISP_B1_09,
- IMXRT1170_PAD_DISP_B1_10,
- IMXRT1170_PAD_DISP_B1_11,
- IMXRT1170_PAD_DISP_B2_00,
- IMXRT1170_PAD_DISP_B2_01,
- IMXRT1170_PAD_DISP_B2_02,
- IMXRT1170_PAD_DISP_B2_03,
- IMXRT1170_PAD_DISP_B2_04,
- IMXRT1170_PAD_DISP_B2_05,
- IMXRT1170_PAD_DISP_B2_06,
- IMXRT1170_PAD_DISP_B2_07,
- IMXRT1170_PAD_DISP_B2_08,
- IMXRT1170_PAD_DISP_B2_09,
- IMXRT1170_PAD_DISP_B2_10,
- IMXRT1170_PAD_DISP_B2_11,
- IMXRT1170_PAD_DISP_B2_12,
- IMXRT1170_PAD_DISP_B2_13,
- IMXRT1170_PAD_DISP_B2_14,
- IMXRT1170_PAD_DISP_B2_15,
-};
-
-/* Pad names for the pinmux subsystem */
-static const struct pinctrl_pin_desc imxrt1170_pinctrl_pads[] = {
- IMX_PINCTRL_PIN(IMXRT1170_PAD_RESERVE0),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_RESERVE1),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_RESERVE2),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_RESERVE3),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_00),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_01),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_02),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_03),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_04),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_05),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_06),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_07),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_08),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_09),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_10),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_11),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_12),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_13),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_14),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_15),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_16),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_17),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_18),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_19),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_20),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_21),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_22),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_23),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_24),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_25),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_26),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_27),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_28),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_29),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_30),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_31),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_32),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_33),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_34),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_35),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_36),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_37),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_38),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_39),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_40),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B1_41),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_00),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_01),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_02),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_03),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_04),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_05),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_06),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_07),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_08),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_09),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_10),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_11),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_12),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_13),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_14),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_15),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_16),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_17),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_18),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_19),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_EMC_B2_20),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_00),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_01),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_02),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_03),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_04),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_05),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_06),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_07),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_08),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_09),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_10),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_11),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_12),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_13),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_14),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_15),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_16),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_17),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_18),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_19),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_20),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_21),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_22),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_23),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_24),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_25),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_26),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_27),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_28),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_29),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_30),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_31),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_32),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_33),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_34),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_AD_35),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B1_00),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B1_01),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B1_02),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B1_03),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B1_04),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B1_05),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_00),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_01),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_02),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_03),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_04),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_05),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_06),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_07),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_08),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_09),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_10),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_SD_B2_11),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_00),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_01),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_02),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_03),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_04),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_05),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_06),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_07),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_08),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_09),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_10),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B1_11),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_00),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_01),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_02),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_03),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_04),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_05),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_06),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_07),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_08),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_09),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_10),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_11),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_12),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_13),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_14),
- IMX_PINCTRL_PIN(IMXRT1170_PAD_DISP_B2_15),
-};
-
-static const struct imx_pinctrl_soc_info imxrt1170_pinctrl_info = {
- .pins = imxrt1170_pinctrl_pads,
- .npins = ARRAY_SIZE(imxrt1170_pinctrl_pads),
- .gpr_compatible = "fsl,imxrt1170-iomuxc-gpr",
-};
-
-static const struct of_device_id imxrt1170_pinctrl_of_match[] = {
- { .compatible = "fsl,imxrt1170-iomuxc", .data = &imxrt1170_pinctrl_info, },
- { /* sentinel */ }
-};
-
-static int imxrt1170_pinctrl_probe(struct platform_device *pdev)
-{
- return imx_pinctrl_probe(pdev, &imxrt1170_pinctrl_info);
-}
-
-static struct platform_driver imxrt1170_pinctrl_driver = {
- .driver = {
- .name = "imxrt1170-pinctrl",
- .of_match_table = of_match_ptr(imxrt1170_pinctrl_of_match),
- .suppress_bind_attrs = true,
- },
- .probe = imxrt1170_pinctrl_probe,
-};
-
-static int __init imxrt1170_pinctrl_init(void)
-{
- return platform_driver_register(&imxrt1170_pinctrl_driver);
-}
-arch_initcall(imxrt1170_pinctrl_init);
--
2.43.0
^ permalink raw reply related
* [PATCH 04/11] clk: imx: imxrt1050: Remove NOMMU platform support
From: Frank.Li @ 2026-06-19 15:41 UTC (permalink / raw)
To: Arnd Bergmann, Sascha Hauer, Pengutronix Kernel Team,
Stefan Agner, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Russell King, Abel Vesa, Peng Fan,
Michael Turquette, Stephen Boyd, Brian Masney, Dong Aisheng,
Jacky Bai, NXP S32 Linux Team, Linus Walleij, Vladimir Zapolskiy,
Piotr Wojtaszczyk, Kees Cook, Gustavo A. R. Silva
Cc: linux-arm-kernel, imx, devicetree, linux-kernel, linux-clk,
linux-gpio, linux-hardening, Frank Li
In-Reply-To: <20260619-dts_cleanup_arm_mcore-v1-0-0101795a2662@nxp.com>
From: Frank Li <Frank.Li@nxp.com>
Commercial users and hardware vendors migrated to Zephyr or other RTOS
solutions years ago, leaving the NOMMU platform support effectively
unused and unmaintained.
Remove the obsolete support to reduce maintenance burden and simplify the
i.MX platform code.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
drivers/clk/imx/Kconfig | 6 -
drivers/clk/imx/Makefile | 1 -
drivers/clk/imx/clk-imxrt1050.c | 182 ----------------------------
include/dt-bindings/clock/imxrt1050-clock.h | 72 -----------
4 files changed, 261 deletions(-)
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index b292e7ca5c248..92ae6e095fadb 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -123,9 +123,3 @@ config CLK_IMX95_BLK_CTL
help
Build the clock driver for i.MX95 BLK CTL
-config CLK_IMXRT1050
- tristate "IMXRT1050 CCM Clock Driver"
- depends on SOC_IMXRT || COMPILE_TEST
- select MXC_CLK
- help
- Build the driver for i.MXRT1050 CCM Clock Driver
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index 208b46873a18c..e71a6a8f8b04f 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -56,5 +56,4 @@ obj-$(CONFIG_CLK_IMX6SX) += clk-imx6sx.o
obj-$(CONFIG_CLK_IMX6UL) += clk-imx6ul.o
obj-$(CONFIG_CLK_IMX7D) += clk-imx7d.o
obj-$(CONFIG_CLK_IMX7ULP) += clk-imx7ulp.o
-obj-$(CONFIG_CLK_IMXRT1050) += clk-imxrt1050.o
obj-$(CONFIG_CLK_VF610) += clk-vf610.o
diff --git a/drivers/clk/imx/clk-imxrt1050.c b/drivers/clk/imx/clk-imxrt1050.c
deleted file mode 100644
index efd1ac9d8eeb7..0000000000000
--- a/drivers/clk/imx/clk-imxrt1050.c
+++ /dev/null
@@ -1,182 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * Copyright (C) 2021
- * Author(s):
- * Jesse Taube <Mr.Bossman075@gmail.com>
- * Giulio Benetti <giulio.benetti@benettiengineering.com>
- */
-#include <linux/clk.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-#include <linux/platform_device.h>
-#include <dt-bindings/clock/imxrt1050-clock.h>
-
-#include "clk.h"
-
-static const char * const pll_ref_sels[] = {"osc", "dummy", };
-static const char * const per_sels[] = {"ipg_pdof", "osc", };
-static const char * const pll1_bypass_sels[] = {"pll1_arm", "pll1_arm_ref_sel", };
-static const char * const pll2_bypass_sels[] = {"pll2_sys", "pll2_sys_ref_sel", };
-static const char * const pll3_bypass_sels[] = {"pll3_usb_otg", "pll3_usb_otg_ref_sel", };
-static const char * const pll5_bypass_sels[] = {"pll5_video", "pll5_video_ref_sel", };
-static const char *const pre_periph_sels[] = {
- "pll2_sys", "pll2_pfd2_396m", "pll2_pfd0_352m", "arm_podf", };
-static const char *const periph_sels[] = { "pre_periph_sel", "todo", };
-static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", };
-static const char *const lpuart_sels[] = { "pll3_80m", "osc", };
-static const char *const lcdif_sels[] = {
- "pll2_sys", "pll3_pfd3_454_74m", "pll5_video", "pll2_pfd0_352m",
- "pll2_pfd1_594m", "pll3_pfd1_664_62m", };
-static const char *const semc_alt_sels[] = { "pll2_pfd2_396m", "pll3_pfd1_664_62m", };
-static const char *const semc_sels[] = { "periph_sel", "semc_alt_sel", };
-
-static struct clk_hw **hws;
-static struct clk_hw_onecell_data *clk_hw_data;
-
-static int imxrt1050_clocks_probe(struct platform_device *pdev)
-{
- void __iomem *ccm_base;
- void __iomem *pll_base;
- struct device *dev = &pdev->dev;
- struct device_node *np = dev->of_node;
- struct device_node *anp;
- int ret;
-
- clk_hw_data = devm_kzalloc(dev, struct_size(clk_hw_data, hws,
- IMXRT1050_CLK_END), GFP_KERNEL);
- if (WARN_ON(!clk_hw_data))
- return -ENOMEM;
-
- clk_hw_data->num = IMXRT1050_CLK_END;
- hws = clk_hw_data->hws;
-
- hws[IMXRT1050_CLK_OSC] = imx_get_clk_hw_by_name(np, "osc");
-
- anp = of_find_compatible_node(NULL, NULL, "fsl,imxrt-anatop");
- pll_base = devm_of_iomap(dev, anp, 0, NULL);
- of_node_put(anp);
- if (WARN_ON(IS_ERR(pll_base))) {
- ret = PTR_ERR(pll_base);
- goto unregister_hws;
- }
-
- /* Anatop clocks */
- hws[IMXRT1050_CLK_DUMMY] = imx_clk_hw_fixed("dummy", 0UL);
-
- hws[IMXRT1050_CLK_PLL1_REF_SEL] = imx_clk_hw_mux("pll1_arm_ref_sel",
- pll_base + 0x0, 14, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
- hws[IMXRT1050_CLK_PLL2_REF_SEL] = imx_clk_hw_mux("pll2_sys_ref_sel",
- pll_base + 0x30, 14, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
- hws[IMXRT1050_CLK_PLL3_REF_SEL] = imx_clk_hw_mux("pll3_usb_otg_ref_sel",
- pll_base + 0x10, 14, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
- hws[IMXRT1050_CLK_PLL5_REF_SEL] = imx_clk_hw_mux("pll5_video_ref_sel",
- pll_base + 0xa0, 14, 2, pll_ref_sels, ARRAY_SIZE(pll_ref_sels));
-
- hws[IMXRT1050_CLK_PLL1_ARM] = imx_clk_hw_pllv3(IMX_PLLV3_SYS, "pll1_arm",
- "pll1_arm_ref_sel", pll_base + 0x0, 0x7f);
- hws[IMXRT1050_CLK_PLL2_SYS] = imx_clk_hw_pllv3(IMX_PLLV3_GENERIC, "pll2_sys",
- "pll2_sys_ref_sel", pll_base + 0x30, 0x1);
- hws[IMXRT1050_CLK_PLL3_USB_OTG] = imx_clk_hw_pllv3(IMX_PLLV3_USB, "pll3_usb_otg",
- "pll3_usb_otg_ref_sel", pll_base + 0x10, 0x1);
- hws[IMXRT1050_CLK_PLL5_VIDEO] = imx_clk_hw_pllv3(IMX_PLLV3_AV, "pll5_video",
- "pll5_video_ref_sel", pll_base + 0xa0, 0x7f);
-
- /* PLL bypass out */
- hws[IMXRT1050_CLK_PLL1_BYPASS] = imx_clk_hw_mux_flags("pll1_bypass", pll_base + 0x0, 16, 1,
- pll1_bypass_sels, ARRAY_SIZE(pll1_bypass_sels), CLK_SET_RATE_PARENT);
- hws[IMXRT1050_CLK_PLL2_BYPASS] = imx_clk_hw_mux_flags("pll2_bypass", pll_base + 0x30, 16, 1,
- pll2_bypass_sels, ARRAY_SIZE(pll2_bypass_sels), CLK_SET_RATE_PARENT);
- hws[IMXRT1050_CLK_PLL3_BYPASS] = imx_clk_hw_mux_flags("pll3_bypass", pll_base + 0x10, 16, 1,
- pll3_bypass_sels, ARRAY_SIZE(pll3_bypass_sels), CLK_SET_RATE_PARENT);
- hws[IMXRT1050_CLK_PLL5_BYPASS] = imx_clk_hw_mux_flags("pll5_bypass", pll_base + 0xa0, 16, 1,
- pll5_bypass_sels, ARRAY_SIZE(pll5_bypass_sels), CLK_SET_RATE_PARENT);
-
- hws[IMXRT1050_CLK_VIDEO_POST_DIV_SEL] = imx_clk_hw_divider("video_post_div_sel",
- "pll5_video", pll_base + 0xa0, 19, 2);
- hws[IMXRT1050_CLK_VIDEO_DIV] = imx_clk_hw_divider("video_div",
- "video_post_div_sel", pll_base + 0x170, 30, 2);
-
- hws[IMXRT1050_CLK_PLL3_80M] = imx_clk_hw_fixed_factor("pll3_80m", "pll3_usb_otg", 1, 6);
-
- hws[IMXRT1050_CLK_PLL2_PFD0_352M] = imx_clk_hw_pfd("pll2_pfd0_352m", "pll2_sys", pll_base + 0x100, 0);
- hws[IMXRT1050_CLK_PLL2_PFD1_594M] = imx_clk_hw_pfd("pll2_pfd1_594m", "pll2_sys", pll_base + 0x100, 1);
- hws[IMXRT1050_CLK_PLL2_PFD2_396M] = imx_clk_hw_pfd("pll2_pfd2_396m", "pll2_sys", pll_base + 0x100, 2);
- hws[IMXRT1050_CLK_PLL3_PFD1_664_62M] = imx_clk_hw_pfd("pll3_pfd1_664_62m", "pll3_usb_otg", pll_base + 0xf0, 1);
- hws[IMXRT1050_CLK_PLL3_PFD3_454_74M] = imx_clk_hw_pfd("pll3_pfd3_454_74m", "pll3_usb_otg", pll_base + 0xf0, 3);
-
- /* CCM clocks */
- ccm_base = devm_platform_ioremap_resource(pdev, 0);
- if (WARN_ON(IS_ERR(ccm_base))) {
- ret = PTR_ERR(ccm_base);
- goto unregister_hws;
- }
-
- hws[IMXRT1050_CLK_ARM_PODF] = imx_clk_hw_divider("arm_podf", "pll1_arm", ccm_base + 0x10, 0, 3);
- hws[IMXRT1050_CLK_PRE_PERIPH_SEL] = imx_clk_hw_mux("pre_periph_sel", ccm_base + 0x18, 18, 2,
- pre_periph_sels, ARRAY_SIZE(pre_periph_sels));
- hws[IMXRT1050_CLK_PERIPH_SEL] = imx_clk_hw_mux("periph_sel", ccm_base + 0x14, 25, 1,
- periph_sels, ARRAY_SIZE(periph_sels));
- hws[IMXRT1050_CLK_USDHC1_SEL] = imx_clk_hw_mux("usdhc1_sel", ccm_base + 0x1c, 16, 1,
- usdhc_sels, ARRAY_SIZE(usdhc_sels));
- hws[IMXRT1050_CLK_USDHC2_SEL] = imx_clk_hw_mux("usdhc2_sel", ccm_base + 0x1c, 17, 1,
- usdhc_sels, ARRAY_SIZE(usdhc_sels));
- hws[IMXRT1050_CLK_LPUART_SEL] = imx_clk_hw_mux("lpuart_sel", ccm_base + 0x24, 6, 1,
- lpuart_sels, ARRAY_SIZE(lpuart_sels));
- hws[IMXRT1050_CLK_LCDIF_SEL] = imx_clk_hw_mux("lcdif_sel", ccm_base + 0x38, 15, 3,
- lcdif_sels, ARRAY_SIZE(lcdif_sels));
- hws[IMXRT1050_CLK_PER_CLK_SEL] = imx_clk_hw_mux("per_sel", ccm_base + 0x1C, 6, 1,
- per_sels, ARRAY_SIZE(per_sels));
- hws[IMXRT1050_CLK_SEMC_ALT_SEL] = imx_clk_hw_mux("semc_alt_sel", ccm_base + 0x14, 7, 1,
- semc_alt_sels, ARRAY_SIZE(semc_alt_sels));
- hws[IMXRT1050_CLK_SEMC_SEL] = imx_clk_hw_mux_flags("semc_sel", ccm_base + 0x14, 6, 1,
- semc_sels, ARRAY_SIZE(semc_sels), CLK_IS_CRITICAL);
-
- hws[IMXRT1050_CLK_AHB_PODF] = imx_clk_hw_divider("ahb", "periph_sel", ccm_base + 0x14, 10, 3);
- hws[IMXRT1050_CLK_IPG_PDOF] = imx_clk_hw_divider("ipg", "ahb", ccm_base + 0x14, 8, 2);
- hws[IMXRT1050_CLK_PER_PDOF] = imx_clk_hw_divider("per", "per_sel", ccm_base + 0x1C, 0, 5);
-
- hws[IMXRT1050_CLK_USDHC1_PODF] = imx_clk_hw_divider("usdhc1_podf", "usdhc1_sel", ccm_base + 0x24, 11, 3);
- hws[IMXRT1050_CLK_USDHC2_PODF] = imx_clk_hw_divider("usdhc2_podf", "usdhc2_sel", ccm_base + 0x24, 16, 3);
- hws[IMXRT1050_CLK_LPUART_PODF] = imx_clk_hw_divider("lpuart_podf", "lpuart_sel", ccm_base + 0x24, 0, 6);
- hws[IMXRT1050_CLK_LCDIF_PRED] = imx_clk_hw_divider("lcdif_pred", "lcdif_sel", ccm_base + 0x38, 12, 3);
- hws[IMXRT1050_CLK_LCDIF_PODF] = imx_clk_hw_divider("lcdif_podf", "lcdif_pred", ccm_base + 0x18, 23, 3);
-
- hws[IMXRT1050_CLK_USDHC1] = imx_clk_hw_gate2("usdhc1", "usdhc1_podf", ccm_base + 0x80, 2);
- hws[IMXRT1050_CLK_USDHC2] = imx_clk_hw_gate2("usdhc2", "usdhc2_podf", ccm_base + 0x80, 4);
- hws[IMXRT1050_CLK_LPUART1] = imx_clk_hw_gate2("lpuart1", "lpuart_podf", ccm_base + 0x7c, 24);
- hws[IMXRT1050_CLK_LCDIF_APB] = imx_clk_hw_gate2("lcdif", "lcdif_podf", ccm_base + 0x70, 28);
- hws[IMXRT1050_CLK_LCDIF_PIX] = imx_clk_hw_gate2("lcdif_pix", "lcdif", ccm_base + 0x74, 10);
- hws[IMXRT1050_CLK_DMA] = imx_clk_hw_gate("dma", "ipg", ccm_base + 0x7C, 6);
- hws[IMXRT1050_CLK_DMA_MUX] = imx_clk_hw_gate("dmamux0", "ipg", ccm_base + 0x7C, 7);
- imx_check_clk_hws(hws, IMXRT1050_CLK_END);
-
- ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);
- if (ret < 0) {
- dev_err(dev, "Failed to register clks for i.MXRT1050.\n");
- goto unregister_hws;
- }
- return 0;
-
-unregister_hws:
- imx_unregister_hw_clocks(hws, IMXRT1050_CLK_END);
- return ret;
-}
-static const struct of_device_id imxrt1050_clk_of_match[] = {
- { .compatible = "fsl,imxrt1050-ccm" },
- { /* Sentinel */ }
-};
-MODULE_DEVICE_TABLE(of, imxrt1050_clk_of_match);
-
-static struct platform_driver imxrt1050_clk_driver = {
- .probe = imxrt1050_clocks_probe,
- .driver = {
- .name = "imxrt1050-ccm",
- .of_match_table = imxrt1050_clk_of_match,
- },
-};
-module_platform_driver(imxrt1050_clk_driver);
-
-MODULE_DESCRIPTION("NXP i.MX RT1050 clock driver");
-MODULE_LICENSE("Dual BSD/GPL");
-MODULE_AUTHOR("Jesse Taube <Mr.Bossman075@gmail.com>");
-MODULE_AUTHOR("Giulio Benetti <giulio.benetti@benettiengineering.com>");
diff --git a/include/dt-bindings/clock/imxrt1050-clock.h b/include/dt-bindings/clock/imxrt1050-clock.h
deleted file mode 100644
index 93bef0832d16d..0000000000000
--- a/include/dt-bindings/clock/imxrt1050-clock.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
-/*
- * Copyright(C) 2019
- * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
- */
-
-#ifndef __DT_BINDINGS_CLOCK_IMXRT1050_H
-#define __DT_BINDINGS_CLOCK_IMXRT1050_H
-
-#define IMXRT1050_CLK_DUMMY 0
-#define IMXRT1050_CLK_CKIL 1
-#define IMXRT1050_CLK_CKIH 2
-#define IMXRT1050_CLK_OSC 3
-#define IMXRT1050_CLK_PLL2_PFD0_352M 4
-#define IMXRT1050_CLK_PLL2_PFD1_594M 5
-#define IMXRT1050_CLK_PLL2_PFD2_396M 6
-#define IMXRT1050_CLK_PLL3_PFD0_720M 7
-#define IMXRT1050_CLK_PLL3_PFD1_664_62M 8
-#define IMXRT1050_CLK_PLL3_PFD2_508_24M 9
-#define IMXRT1050_CLK_PLL3_PFD3_454_74M 10
-#define IMXRT1050_CLK_PLL2_198M 11
-#define IMXRT1050_CLK_PLL3_120M 12
-#define IMXRT1050_CLK_PLL3_80M 13
-#define IMXRT1050_CLK_PLL3_60M 14
-#define IMXRT1050_CLK_PLL1_BYPASS 15
-#define IMXRT1050_CLK_PLL2_BYPASS 16
-#define IMXRT1050_CLK_PLL3_BYPASS 17
-#define IMXRT1050_CLK_PLL5_BYPASS 19
-#define IMXRT1050_CLK_PLL1_REF_SEL 20
-#define IMXRT1050_CLK_PLL2_REF_SEL 21
-#define IMXRT1050_CLK_PLL3_REF_SEL 22
-#define IMXRT1050_CLK_PLL5_REF_SEL 23
-#define IMXRT1050_CLK_PRE_PERIPH_SEL 24
-#define IMXRT1050_CLK_PERIPH_SEL 25
-#define IMXRT1050_CLK_SEMC_ALT_SEL 26
-#define IMXRT1050_CLK_SEMC_SEL 27
-#define IMXRT1050_CLK_USDHC1_SEL 28
-#define IMXRT1050_CLK_USDHC2_SEL 29
-#define IMXRT1050_CLK_LPUART_SEL 30
-#define IMXRT1050_CLK_LCDIF_SEL 31
-#define IMXRT1050_CLK_VIDEO_POST_DIV_SEL 32
-#define IMXRT1050_CLK_VIDEO_DIV 33
-#define IMXRT1050_CLK_ARM_PODF 34
-#define IMXRT1050_CLK_LPUART_PODF 35
-#define IMXRT1050_CLK_USDHC1_PODF 36
-#define IMXRT1050_CLK_USDHC2_PODF 37
-#define IMXRT1050_CLK_SEMC_PODF 38
-#define IMXRT1050_CLK_AHB_PODF 39
-#define IMXRT1050_CLK_LCDIF_PRED 40
-#define IMXRT1050_CLK_LCDIF_PODF 41
-#define IMXRT1050_CLK_USDHC1 42
-#define IMXRT1050_CLK_USDHC2 43
-#define IMXRT1050_CLK_LPUART1 44
-#define IMXRT1050_CLK_SEMC 45
-#define IMXRT1050_CLK_LCDIF_APB 46
-#define IMXRT1050_CLK_PLL1_ARM 47
-#define IMXRT1050_CLK_PLL2_SYS 48
-#define IMXRT1050_CLK_PLL3_USB_OTG 49
-#define IMXRT1050_CLK_PLL4_AUDIO 50
-#define IMXRT1050_CLK_PLL5_VIDEO 51
-#define IMXRT1050_CLK_PLL6_ENET 52
-#define IMXRT1050_CLK_PLL7_USB_HOST 53
-#define IMXRT1050_CLK_LCDIF_PIX 54
-#define IMXRT1050_CLK_USBOH3 55
-#define IMXRT1050_CLK_IPG_PDOF 56
-#define IMXRT1050_CLK_PER_CLK_SEL 57
-#define IMXRT1050_CLK_PER_PDOF 58
-#define IMXRT1050_CLK_DMA 59
-#define IMXRT1050_CLK_DMA_MUX 60
-#define IMXRT1050_CLK_END 61
-
-#endif /* __DT_BINDINGS_CLOCK_IMXRT1050_H */
--
2.43.0
^ permalink raw reply related
* [PATCH 03/11] ARM: imx: Remove NOMMU platform support
From: Frank.Li @ 2026-06-19 15:41 UTC (permalink / raw)
To: Arnd Bergmann, Sascha Hauer, Pengutronix Kernel Team,
Stefan Agner, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Russell King, Abel Vesa, Peng Fan,
Michael Turquette, Stephen Boyd, Brian Masney, Dong Aisheng,
Jacky Bai, NXP S32 Linux Team, Linus Walleij, Vladimir Zapolskiy,
Piotr Wojtaszczyk, Kees Cook, Gustavo A. R. Silva
Cc: linux-arm-kernel, imx, devicetree, linux-kernel, linux-clk,
linux-gpio, linux-hardening, Frank Li
In-Reply-To: <20260619-dts_cleanup_arm_mcore-v1-0-0101795a2662@nxp.com>
From: Frank Li <Frank.Li@nxp.com>
Commercial users and hardware vendors migrated to Zephyr or other RTOS
solutions years ago, leaving the NOMMU platform support effectively unused
and unmaintained.
Remove the obsolete support to reduce maintenance burden and simplify the
i.MX platform code.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm/mach-imx/Kconfig | 7 -------
arch/arm/mach-imx/Makefile | 2 --
arch/arm/mach-imx/mach-imxrt.c | 19 -------------------
3 files changed, 28 deletions(-)
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index a361840d7a047..081f08bb01ae1 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -213,13 +213,6 @@ config SOC_IMX7ULP
help
This enables support for Freescale i.MX7 Ultra Low Power processor.
-config SOC_IMXRT
- bool "i.MXRT support"
- depends on ARM_SINGLE_ARMV7M
- select ARMV7M_SYSTICK if ARM_SINGLE_ARMV7M
- help
- This enables support for Freescale i.MXRT Crossover processor.
-
config SOC_VF610
bool "Vybrid Family VF610 support"
select ARM_GIC if ARCH_MULTI_V7
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 5c650bf40e024..b14e9a0ec7501 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -60,8 +60,6 @@ obj-$(CONFIG_SOC_IMX50) += mach-imx50.o
obj-$(CONFIG_SOC_IMX51) += mach-imx51.o
obj-$(CONFIG_SOC_IMX53) += mach-imx53.o
-obj-$(CONFIG_SOC_IMXRT) += mach-imxrt.o
-
obj-$(CONFIG_SOC_VF610) += mach-vf610.o
obj-$(CONFIG_SOC_LS1021A) += mach-ls1021a.o
diff --git a/arch/arm/mach-imx/mach-imxrt.c b/arch/arm/mach-imx/mach-imxrt.c
deleted file mode 100644
index 2063a3059c849..0000000000000
--- a/arch/arm/mach-imx/mach-imxrt.c
+++ /dev/null
@@ -1,19 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2019
- * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com>
- */
-
-#include <linux/kernel.h>
-#include <asm/mach/arch.h>
-#include <asm/v7m.h>
-
-static const char *const imxrt_compat[] __initconst = {
- "fsl,imxrt1050",
- NULL
-};
-
-DT_MACHINE_START(IMXRTDT, "IMXRT (Device Tree Support)")
- .dt_compat = imxrt_compat,
- .restart = armv7m_restart,
-MACHINE_END
--
2.43.0
^ permalink raw reply related
* [PATCH 01/11] ARM: dts: vf610m4: Remove NOMMU platform support
From: Frank.Li @ 2026-06-19 15:40 UTC (permalink / raw)
To: Arnd Bergmann, Sascha Hauer, Pengutronix Kernel Team,
Stefan Agner, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Russell King, Abel Vesa, Peng Fan,
Michael Turquette, Stephen Boyd, Brian Masney, Dong Aisheng,
Jacky Bai, NXP S32 Linux Team, Linus Walleij, Vladimir Zapolskiy,
Piotr Wojtaszczyk, Kees Cook, Gustavo A. R. Silva
Cc: linux-arm-kernel, imx, devicetree, linux-kernel, linux-clk,
linux-gpio, linux-hardening, Frank Li
In-Reply-To: <20260619-dts_cleanup_arm_mcore-v1-0-0101795a2662@nxp.com>
From: Frank Li <Frank.Li@nxp.com>
The Vybrid M4 NOMMU platform support was added as a proof-of-concept and
has not seen practical use in production systems.
Commercial users and hardware vendors migrated to Zephyr or other RTOS
solutions years ago, leaving the NOMMU platform support effectively
unused and unmaintained.
Remove the obsolete support to reduce maintenance burden and simplify the
code.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
Cc: Stefan Agner <stefan@agner.ch>
---
arch/arm/boot/dts/nxp/vf/Makefile | 2 -
arch/arm/boot/dts/nxp/vf/vf610m4-colibri.dts | 61 -------------------
arch/arm/boot/dts/nxp/vf/vf610m4-cosmic.dts | 88 ----------------------------
arch/arm/boot/dts/nxp/vf/vf610m4.dtsi | 61 -------------------
4 files changed, 212 deletions(-)
diff --git a/arch/arm/boot/dts/nxp/vf/Makefile b/arch/arm/boot/dts/nxp/vf/Makefile
index 0a4a7f9dd43e4..1733506c0c725 100644
--- a/arch/arm/boot/dts/nxp/vf/Makefile
+++ b/arch/arm/boot/dts/nxp/vf/Makefile
@@ -3,9 +3,7 @@ dtb-$(CONFIG_SOC_VF610) += \
vf500-colibri-eval-v3.dtb \
vf610-bk4.dtb \
vf610-colibri-eval-v3.dtb \
- vf610m4-colibri.dtb \
vf610-cosmic.dtb \
- vf610m4-cosmic.dtb \
vf610-twr.dtb \
vf610-zii-cfu1.dtb \
vf610-zii-dev-rev-b.dtb \
diff --git a/arch/arm/boot/dts/nxp/vf/vf610m4-colibri.dts b/arch/arm/boot/dts/nxp/vf/vf610m4-colibri.dts
deleted file mode 100644
index 86d32f54c250f..0000000000000
--- a/arch/arm/boot/dts/nxp/vf/vf610m4-colibri.dts
+++ /dev/null
@@ -1,61 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
-/*
- * Device tree for Colibri VF61 Cortex-M4 support
- *
- * Copyright (C) 2015 Stefan Agner
- */
-
-/dts-v1/;
-#include "vf610m4.dtsi"
-
-/ {
- model = "VF610 Cortex-M4";
- compatible = "fsl,vf610m4";
-
- chosen {
- bootargs = "clk_ignore_unused init=/linuxrc rw";
- stdout-path = "serial2:115200";
- };
-
- memory@8c000000 {
- device_type = "memory";
- reg = <0x8c000000 0x3000000>;
- };
-};
-
-&gpio0 {
- status = "disabled";
-};
-
-&gpio1 {
- status = "disabled";
-};
-
-&gpio2 {
- status = "disabled";
-};
-
-&gpio3 {
- status = "disabled";
-};
-
-&gpio4 {
- status = "disabled";
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart2>;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl_uart2: uart2grp {
- fsl,pins = <
- VF610_PAD_PTD0__UART2_TX 0x21a2
- VF610_PAD_PTD1__UART2_RX 0x21a1
- VF610_PAD_PTD2__UART2_RTS 0x21a2
- VF610_PAD_PTD3__UART2_CTS 0x21a1
- >;
- };
-};
diff --git a/arch/arm/boot/dts/nxp/vf/vf610m4-cosmic.dts b/arch/arm/boot/dts/nxp/vf/vf610m4-cosmic.dts
deleted file mode 100644
index 454b484368cb7..0000000000000
--- a/arch/arm/boot/dts/nxp/vf/vf610m4-cosmic.dts
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * Device tree for Cosmic+ VF6xx Cortex-M4 support
- *
- * Copyright (C) 2015
- *
- * Based on vf610m4 Colibri
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-#include "vf610m4.dtsi"
-
-/ {
- model = "VF610 Cortex-M4";
- compatible = "fsl,vf610m4";
-};
-
-&gpio0 {
- status = "disabled";
-};
-
-&gpio1 {
- status = "disabled";
-};
-
-&gpio2 {
- status = "disabled";
-};
-
-&gpio3 {
- status = "disabled";
-};
-
-&gpio4 {
- status = "disabled";
-};
-
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_uart3>;
- status = "okay";
-};
-
-&iomuxc {
- pinctrl_uart3: uart3grp {
- fsl,pins = <
- VF610_PAD_PTA20__UART3_TX 0x21a2
- VF610_PAD_PTA21__UART3_RX 0x21a1
- >;
- };
-};
diff --git a/arch/arm/boot/dts/nxp/vf/vf610m4.dtsi b/arch/arm/boot/dts/nxp/vf/vf610m4.dtsi
deleted file mode 100644
index 648d219e1d0ed..0000000000000
--- a/arch/arm/boot/dts/nxp/vf/vf610m4.dtsi
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * Device tree for VF6xx Cortex-M4 support
- *
- * Copyright (C) 2015 Stefan Agner
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include "../../armv7-m.dtsi"
-#include "vfxxx.dtsi"
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
- chosen { };
- aliases { };
-};
-
-&mscm_ir {
- interrupt-parent = <&nvic>;
-};
-
-&nvic {
- arm,num-irq-priority-bits = <4>;
-};
--
2.43.0
^ permalink raw reply related
* [PATCH 00/11] ARM: NXP: Drop NOMMU platform support
From: Frank.Li @ 2026-06-19 15:40 UTC (permalink / raw)
To: Arnd Bergmann, Sascha Hauer, Pengutronix Kernel Team,
Stefan Agner, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Russell King, Abel Vesa, Peng Fan,
Michael Turquette, Stephen Boyd, Brian Masney, Dong Aisheng,
Jacky Bai, NXP S32 Linux Team, Linus Walleij, Vladimir Zapolskiy,
Piotr Wojtaszczyk, Kees Cook, Gustavo A. R. Silva
Cc: linux-arm-kernel, imx, devicetree, linux-kernel, linux-clk,
linux-gpio, linux-hardening, Frank Li
Commercial users and hardware vendors migrated to Zephyr or other RTOS
solutions years ago, leaving the NOMMU platform support effectively
unused and unmaintained.
Remove the obsolete support to reduce maintenance burden and simplify the
Freescale/nxp platform code.
Some driver code still be kept and may clean up later since it is possible
reused by other SoC.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
Frank Li (11):
ARM: dts: vf610m4: Remove NOMMU platform support
ARM: dts: imxrt1050: Remove NOMMU platform support
ARM: imx: Remove NOMMU platform support
clk: imx: imxrt1050: Remove NOMMU platform support
pinctrl: freescale: IMXRT: Remove NOMMU platform support
ARM: imxrt_defconfig: Remove NOMMU platform support
ARM: dts: lpc: Remove NOMMU platform support
ARM: mach-lpc: Remove NOMMU platform support
ARM: configs: lpc*: Remove NOMMU platform support
clk: nxp: lpc: Remove NOMMU platform support
pinctrl: nxp: lpc: Remove NOMMU platform support
.../devicetree/bindings/pinctrl/fsl,imxrt1050.yaml | 79 -
.../devicetree/bindings/pinctrl/fsl,imxrt1170.yaml | 77 -
arch/arm/Kconfig | 12 -
arch/arm/Makefile | 2 -
arch/arm/boot/dts/nxp/Makefile | 1 -
arch/arm/boot/dts/nxp/imx/Makefile | 2 -
arch/arm/boot/dts/nxp/imx/imxrt1050-evk.dts | 72 -
arch/arm/boot/dts/nxp/imx/imxrt1050-pinfunc.h | 993 ------------
arch/arm/boot/dts/nxp/imx/imxrt1050.dtsi | 160 --
arch/arm/boot/dts/nxp/imx/imxrt1170-pinfunc.h | 1561 -------------------
arch/arm/boot/dts/nxp/lpc/Makefile | 9 -
arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi | 543 -------
arch/arm/boot/dts/nxp/lpc/lpc3250-ea3250.dts | 273 ----
arch/arm/boot/dts/nxp/lpc/lpc3250-phy3250.dts | 236 ---
arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 540 -------
arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dts | 221 ---
arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts | 485 ------
arch/arm/boot/dts/nxp/lpc/lpc4350.dtsi | 48 -
.../arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts | 624 --------
arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts | 621 --------
arch/arm/boot/dts/nxp/lpc/lpc4357.dtsi | 52 -
arch/arm/boot/dts/nxp/vf/Makefile | 2 -
arch/arm/boot/dts/nxp/vf/vf610m4-colibri.dts | 61 -
arch/arm/boot/dts/nxp/vf/vf610m4-cosmic.dts | 88 --
arch/arm/boot/dts/nxp/vf/vf610m4.dtsi | 61 -
arch/arm/configs/imxrt_defconfig | 35 -
arch/arm/configs/lpc18xx_defconfig | 158 --
arch/arm/configs/lpc32xx_defconfig | 192 ---
arch/arm/mach-imx/Kconfig | 7 -
arch/arm/mach-imx/Makefile | 2 -
arch/arm/mach-imx/mach-imxrt.c | 19 -
arch/arm/mach-lpc18xx/Makefile | 2 -
arch/arm/mach-lpc18xx/board-dt.c | 19 -
arch/arm/mach-lpc32xx/Kconfig | 13 -
arch/arm/mach-lpc32xx/Makefile | 8 -
arch/arm/mach-lpc32xx/common.c | 125 --
arch/arm/mach-lpc32xx/common.h | 32 -
arch/arm/mach-lpc32xx/lpc32xx.h | 717 ---------
arch/arm/mach-lpc32xx/phy3250.c | 92 --
arch/arm/mach-lpc32xx/pm.c | 135 --
arch/arm/mach-lpc32xx/serial.c | 148 --
arch/arm/mach-lpc32xx/suspend.S | 148 --
drivers/clk/Kconfig | 7 -
drivers/clk/Makefile | 1 -
drivers/clk/imx/Kconfig | 6 -
drivers/clk/imx/Makefile | 1 -
drivers/clk/imx/clk-imxrt1050.c | 182 ---
drivers/clk/nxp/Makefile | 5 -
drivers/clk/nxp/clk-lpc18xx-ccu.c | 301 ----
drivers/clk/nxp/clk-lpc18xx-cgu.c | 668 --------
drivers/clk/nxp/clk-lpc18xx-creg.c | 225 ---
drivers/clk/nxp/clk-lpc32xx.c | 1591 --------------------
drivers/pinctrl/Kconfig | 9 -
drivers/pinctrl/Makefile | 1 -
drivers/pinctrl/freescale/Kconfig | 16 -
drivers/pinctrl/freescale/Makefile | 2 -
drivers/pinctrl/freescale/pinctrl-imxrt1050.c | 309 ----
drivers/pinctrl/freescale/pinctrl-imxrt1170.c | 349 -----
drivers/pinctrl/pinctrl-lpc18xx.c | 1382 -----------------
include/dt-bindings/clock/imxrt1050-clock.h | 72 -
60 files changed, 13802 deletions(-)
---
base-commit: 598c7067dd8b65b93f3ccada47e9014a13137f1b
change-id: 20260618-dts_cleanup_arm_mcore-e7e933da798a
Best regards,
--
Frank Li <Frank.Li@nxp.com>
^ permalink raw reply
* Re: [PATCH v4 4/6] arm64: dts: qcom: shikra: Add pin configuration for mclks
From: Konrad Dybcio @ 2026-06-19 15:36 UTC (permalink / raw)
To: Nihal Kumar Gupta, Bryan O'Donoghue, Vladimir Zapolskiy,
Loic Poulain, Mauro Carvalho Chehab, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Robert Foss, Andi Shyti,
Bryan O'Donoghue, Bjorn Andersson, Konrad Dybcio, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam
Cc: linux-arm-msm, linux-media, devicetree, linux-kernel, linux-i2c,
imx, linux-arm-kernel, Suresh Vankadara, Vikram Sharma
In-Reply-To: <20260615-shikra-camss-review-v4-4-bcb51081735b@oss.qualcomm.com>
On 6/15/26 10:33 AM, Nihal Kumar Gupta wrote:
> Add pinctrl configuration for the four available camera master clocks.
>
> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
> Signed-off-by: Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/shikra.dtsi | 28 ++++++++++++++++++++++++++++
> 1 file changed, 28 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
> index 57732804a6c6a114a407a4a541a1cc7af7635ea2..16b547131e8b14541abc68ff7cda126ba777ad80 100644
> --- a/arch/arm64/boot/dts/qcom/shikra.dtsi
> +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
> @@ -380,6 +380,34 @@ cci_i2c1_sleep: cci-i2c1-sleep-state {
> bias-pull-down;
> };
>
> + cam_mclk0_default: cam-mclk0-default-state {
> + pins = "gpio34";
> + function = "cam_mclk";
> + drive-strength = <2>;
> + bias-disable;
> + };
> +
> + cam_mclk1_default: cam-mclk1-default-state {
> + pins = "gpio35";
> + function = "cam_mclk";
> + drive-strength = <2>;
> + bias-disable;
> + };
> +
> + cam_mclk2_default: cam-mclk2-default-state {
> + pins = "gpio96";
> + function = "cam_mclk";
> + drive-strength = <2>;
> + bias-disable;
> + };
> +
> + cam_mclk3_default: cam-mclk3-default-state {
> + pins = "gpio98";
> + function = "cam_mclk";
> + drive-strength = <2>;
> + bias-disable;
> + };
Please try to keep the entries roughly sorted by the pin index
For the entries themselves:
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply
* Re: [PATCH v2] arm64: tlbflush: Don't broadcast if mm was only active on local cpu
From: Will Deacon @ 2026-06-19 15:34 UTC (permalink / raw)
To: Ryan Roberts
Cc: Linu Cherian, Catalin Marinas, Kevin Brodsky, Anshuman Khandual,
Yang Shi, Mark Rutland, Huang Ying, linux-arm-kernel,
linux-kernel, shameerali.kolothum.thodi
In-Reply-To: <4aa78619-5a79-4fd0-aaac-a990b8c3fd05@arm.com>
On Mon, Jun 15, 2026 at 04:41:04PM +0100, Ryan Roberts wrote:
> On 15/06/2026 15:43, Will Deacon wrote:
> > On Mon, Jun 15, 2026 at 12:21:19PM +0100, Ryan Roberts wrote:
> >>>> + self = smp_processor_id();
> >>>> +
> >>>> + /*
> >>>> + * The load of mm->context.active_cpu must not be reordered before the
> >>>> + * store to the pgtable that necessitated this flush. This ensures that
> >>>> + * if the value read is our cpu id, then no other cpu can have seen the
> >>>> + * old pgtable value and therefore does not need this old value to be
> >>>> + * flushed from its tlb. But we don't want to upgrade the dsb(ishst),
> >>>> + * needed to make the pgtable updates visible to the walker, to a
> >>>> + * dsb(ish) by default. So speculatively load without a barrier and if
> >>>> + * it indicates our cpu id, then upgrade the barrier and re-load.
> >>>> + */
> >>>> + active = READ_ONCE(mm->context.active_cpu);
> >>>> + if (active == self) {
> >>>> + dsb(ish);
> >>>> + active = READ_ONCE(mm->context.active_cpu);
> >>>> + } else {
> >>>> + dsb(ishst);
> >>>> + }
> >>>
> >>> Why can't you just do:
> >>>
> >>> dsb(ishst);
> >>> active = READ_ONCE(mm->context.active_cpu);
> >>>
> >>> ?
> >>
> >> Prior to this optimization, we always issued a dsb(ishst) here. Catalin
> >> suggested the same simplification against the RFC. I believe Linu tried it but
> >> saw regressions; Hopefully Linu can provide the details.
> >
> > I don't follow...
> >
> > The old code always did dsb(ishst). The proposed code here does either
> > dsb(ish) or dsb(ishst). How can that possibly be faster?
>
> Ugh, sorry - I read your suggestion as unconditionally issuing a dsb(ish).
>
> Ignore my previous answer, and now I'll demonstrate my total lack of
> understanding of barriers instead...
>
> As the comment says, "The load of mm->context.active_cpu must not be reordered
> before the store to the pgtable that necessitated this flush". I thought that a
> dsb(ishst) would only provide ordering between stores. Don't we need the
> dsb(ish) to prevent the load from being reordered before the store?
dsb(ishst) orders prior stores -> everything later. That's why it works
today for ordered a PTE write before a TLBI (which isn't a store).
Will
^ permalink raw reply
* [PATCH v6 18/23] phy: rockchip: usbdp: Re-init the PHY on orientation change
From: Sebastian Reichel @ 2026-06-19 15:29 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Heiko Stuebner, Frank Wang,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Andy Yan, Dmitry Baryshkov, Yubing Zhang, Alexey Charkov,
linux-phy, linux-arm-kernel, linux-rockchip, linux-kernel, kernel,
devicetree, Sebastian Reichel
In-Reply-To: <20260619-rockchip-usbdp-cleanup-v6-0-3bb1f54b3f35@collabora.com>
Changing the cable orientation reconfigures the lane muxing, which
requires re-initializing the PHY. Without this DP functionality
breaks, if the cable is re-plugged with swapped orientation.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/phy/rockchip/phy-rockchip-usbdp.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c
index c210aaeb283a..402f3cafcf0a 100644
--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
@@ -622,6 +622,7 @@ static int rk_udphy_orien_sw_set(struct typec_switch_dev *sw,
enum typec_orientation orien)
{
struct rk_udphy *udphy = typec_switch_get_drvdata(sw);
+ bool flipped = orien == TYPEC_ORIENTATION_REVERSE;
mutex_lock(&udphy->mutex);
@@ -633,7 +634,10 @@ static int rk_udphy_orien_sw_set(struct typec_switch_dev *sw,
goto unlock_ret;
}
- udphy->flip = orien == TYPEC_ORIENTATION_REVERSE;
+ if (udphy->flip != flipped)
+ udphy->phy_needs_reinit = true;
+
+ udphy->flip = flipped;
rk_udphy_set_typec_default_mapping(udphy);
rk_udphy_usb_bvalid_enable(udphy, true);
--
2.53.0
^ permalink raw reply related
* [PATCH v6 21/23] phy: rockchip: usbdp: Support going from DP-only mode to USB mode
From: Sebastian Reichel @ 2026-06-19 15:29 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Heiko Stuebner, Frank Wang,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Andy Yan, Dmitry Baryshkov, Yubing Zhang, Alexey Charkov,
linux-phy, linux-arm-kernel, linux-rockchip, linux-kernel, kernel,
devicetree, Sebastian Reichel
In-Reply-To: <20260619-rockchip-usbdp-cleanup-v6-0-3bb1f54b3f35@collabora.com>
When a USB-C adapter, which maps all Superspeed lanes to DP is plugged
in, the USB support is disabled in the PHY. When the adapter is
unplugged and a different adapter with USB functionality is plugged in
afterwards, USB functionality is not restored as the USB controller
keeps the PHY enabled for the entire time.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/phy/rockchip/phy-rockchip-usbdp.c | 29 ++++++++++++++++++++++++++++-
1 file changed, 28 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c
index 81aae3bc5747..7f26b74cb515 100644
--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
@@ -178,6 +178,7 @@ struct rk_udphy {
/* utilized for USB */
bool hs; /* flag for high-speed */
+ bool usb_in_use;
/* utilized for DP */
struct gpio_desc *sbu1_dc_gpio;
@@ -1015,6 +1016,10 @@ static int rk_udphy_power_on(struct rk_udphy *udphy, u8 mode)
ret = rk_udphy_init(udphy);
if (ret)
return ret;
+
+ if (udphy->mode & UDPHY_MODE_USB)
+ rk_udphy_u3_port_disable(udphy, false);
+
udphy->phy_needs_reinit = false;
}
@@ -1278,6 +1283,7 @@ static const struct phy_ops rk_udphy_dp_phy_ops = {
static int rk_udphy_usb3_phy_init(struct phy *phy)
{
struct rk_udphy *udphy = phy_get_drvdata(phy);
+ int ret;
guard(mutex)(&udphy->mutex);
@@ -1287,7 +1293,13 @@ static int rk_udphy_usb3_phy_init(struct phy *phy)
return 0;
}
- return rk_udphy_power_on(udphy, UDPHY_MODE_USB);
+ ret = rk_udphy_power_on(udphy, UDPHY_MODE_USB);
+ if (ret)
+ return ret;
+
+ udphy->usb_in_use = true;
+
+ return 0;
}
static int rk_udphy_usb3_phy_exit(struct phy *phy)
@@ -1296,6 +1308,8 @@ static int rk_udphy_usb3_phy_exit(struct phy *phy)
guard(mutex)(&udphy->mutex);
+ udphy->usb_in_use = false;
+
/* DP only or high-speed */
if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs)
return 0;
@@ -1315,6 +1329,7 @@ static int rk_udphy_typec_mux_set(struct typec_mux_dev *mux,
struct typec_mux_state *state)
{
struct rk_udphy *udphy = typec_mux_get_drvdata(mux);
+ u8 old_mode;
/*
* Ignore mux events not involving DP AltMode, because
@@ -1326,8 +1341,20 @@ static int rk_udphy_typec_mux_set(struct typec_mux_dev *mux,
guard(mutex)(&udphy->mutex);
+ old_mode = udphy->mode;
+
rk_udphy_set_typec_state(udphy, state->mode);
+ /*
+ * If the new mode includes USB but the old one didn't (e.g. leaving
+ * DP-only), and the USB PHY was already initialized by the USB
+ * controller, we need to power on the USB side now since no
+ * subsequent phy_init call will come from the controller.
+ */
+ if ((udphy->mode & UDPHY_MODE_USB) && !(old_mode & UDPHY_MODE_USB) &&
+ udphy->usb_in_use && !udphy->hs)
+ return rk_udphy_power_on(udphy, UDPHY_MODE_USB);
+
return 0;
}
--
2.53.0
^ permalink raw reply related
* [PATCH v6 16/23] phy: rockchip: usbdp: Drop DP HPD handling
From: Sebastian Reichel @ 2026-06-19 15:29 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Heiko Stuebner, Frank Wang,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Andy Yan, Dmitry Baryshkov, Yubing Zhang, Alexey Charkov,
linux-phy, linux-arm-kernel, linux-rockchip, linux-kernel, kernel,
devicetree, Sebastian Reichel
In-Reply-To: <20260619-rockchip-usbdp-cleanup-v6-0-3bb1f54b3f35@collabora.com>
Drop the HPD handling logic from the USBDP PHY. The registers involved
require the display controller power domain being enabled and thus the
HPD signal should be handled by the displayport controller itself.
Apart from that the HPD handling as it is done here is incorrect and
misses hotplug events happening after the USB-C connector (e.g. when
a USB-C to HDMI adapter is involved and the HDMI cable is replugged).
Proper USB-C DP HPD support requires some restructuring of the DP
controller driver, which will happen independent of this patch. The
mainline kernel does not yet support USB-C DP AltMode on RK3588 and
RK3576, so it is fine to drop this code without adding the counterpart
in the DRM in an atomic change.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/phy/rockchip/phy-rockchip-usbdp.c | 85 ++++---------------------------
1 file changed, 9 insertions(+), 76 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c
index b75c190a4311..383e68b24506 100644
--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
@@ -128,7 +128,6 @@ struct rk_udphy_grf_cfg {
struct rk_udphy_vogrf_cfg {
/* vo-grf */
- struct rk_udphy_grf_reg hpd_trigger;
u32 dp_lane_reg;
};
@@ -186,14 +185,11 @@ struct rk_udphy {
u32 dp_lane_sel[4];
u32 dp_aux_dout_sel;
u32 dp_aux_din_sel;
- bool dp_sink_hpd_sel;
- bool dp_sink_hpd_cfg;
unsigned int link_rate;
unsigned int lanes;
u8 bw;
int id;
- bool dp_in_use;
int dp_lanes;
/* PHY const config */
@@ -579,19 +575,6 @@ static void rk_udphy_dp_lane_enable(struct rk_udphy *udphy, int dp_lanes)
CMN_DP_CMN_RSTN, FIELD_PREP(CMN_DP_CMN_RSTN, 0x0));
}
-static void rk_udphy_dp_hpd_event_trigger(struct rk_udphy *udphy, bool hpd)
-{
- const struct rk_udphy_cfg *cfg = udphy->cfgs;
-
- udphy->dp_sink_hpd_sel = true;
- udphy->dp_sink_hpd_cfg = hpd;
-
- if (!udphy->dp_in_use)
- return;
-
- rk_udphy_grfreg_write(udphy->vogrf, &cfg->vogrfcfg[udphy->id].hpd_trigger, hpd);
-}
-
static void rk_udphy_mode_set(struct rk_udphy *udphy, u8 mode)
{
if (udphy->mode == mode)
@@ -1024,29 +1007,6 @@ static void rk_udphy_power_off(struct rk_udphy *udphy, u8 mode)
rk_udphy_disable(udphy);
}
-static int rk_udphy_dp_phy_init(struct phy *phy)
-{
- struct rk_udphy *udphy = phy_get_drvdata(phy);
-
- mutex_lock(&udphy->mutex);
-
- udphy->dp_in_use = true;
-
- mutex_unlock(&udphy->mutex);
-
- return 0;
-}
-
-static int rk_udphy_dp_phy_exit(struct phy *phy)
-{
- struct rk_udphy *udphy = phy_get_drvdata(phy);
-
- mutex_lock(&udphy->mutex);
- udphy->dp_in_use = false;
- mutex_unlock(&udphy->mutex);
- return 0;
-}
-
static int rk_udphy_dp_phy_power_on(struct phy *phy)
{
struct rk_udphy *udphy = phy_get_drvdata(phy);
@@ -1278,8 +1238,6 @@ static int rk_udphy_dp_phy_configure(struct phy *phy,
}
static const struct phy_ops rk_udphy_dp_phy_ops = {
- .init = rk_udphy_dp_phy_init,
- .exit = rk_udphy_dp_phy_exit,
.power_on = rk_udphy_dp_phy_power_on,
.power_off = rk_udphy_dp_phy_power_off,
.configure = rk_udphy_dp_phy_configure,
@@ -1333,6 +1291,14 @@ static int rk_udphy_typec_mux_set(struct typec_mux_dev *mux,
struct rk_udphy *udphy = typec_mux_get_drvdata(mux);
u8 mode;
+ /*
+ * Ignore mux events not involving DP AltMode, because
+ * the mode field is being reused, e.g. state->mode == 4
+ * could be either TYPEC_MODE_USB4 or TYPEC_DP_STATE_C.
+ */
+ if (!state->alt || state->alt->svid != USB_TYPEC_DP_SID)
+ return 0;
+
mutex_lock(&udphy->mutex);
switch (state->mode) {
@@ -1364,22 +1330,7 @@ static int rk_udphy_typec_mux_set(struct typec_mux_dev *mux,
break;
}
- if (state->alt && state->alt->svid == USB_TYPEC_DP_SID) {
- struct typec_displayport_data *data = state->data;
-
- if (!data) {
- rk_udphy_dp_hpd_event_trigger(udphy, false);
- } else if (data->status & DP_STATUS_IRQ_HPD) {
- rk_udphy_dp_hpd_event_trigger(udphy, false);
- usleep_range(750, 800);
- rk_udphy_dp_hpd_event_trigger(udphy, true);
- } else if (data->status & DP_STATUS_HPD_STATE) {
- rk_udphy_mode_set(udphy, mode);
- rk_udphy_dp_hpd_event_trigger(udphy, true);
- } else {
- rk_udphy_dp_hpd_event_trigger(udphy, false);
- }
- }
+ rk_udphy_mode_set(udphy, mode);
mutex_unlock(&udphy->mutex);
return 0;
@@ -1535,20 +1486,6 @@ static int rk_udphy_probe(struct platform_device *pdev)
return 0;
}
-static int __maybe_unused rk_udphy_resume(struct device *dev)
-{
- struct rk_udphy *udphy = dev_get_drvdata(dev);
-
- if (udphy->dp_sink_hpd_sel)
- rk_udphy_dp_hpd_event_trigger(udphy, udphy->dp_sink_hpd_cfg);
-
- return 0;
-}
-
-static const struct dev_pm_ops rk_udphy_pm_ops = {
- SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, rk_udphy_resume)
-};
-
static const char * const rk_udphy_rst_list[] = {
"init", "cmn", "lane", "pcs_apb", "pma_apb"
};
@@ -1572,7 +1509,6 @@ static const struct rk_udphy_cfg rk3576_udphy_cfgs = {
},
.vogrfcfg = {
{
- .hpd_trigger = RK_UDPHY_GEN_GRF_REG(0x0000, 11, 10, 1, 3),
.dp_lane_reg = 0x0000,
},
},
@@ -1613,11 +1549,9 @@ static const struct rk_udphy_cfg rk3588_udphy_cfgs = {
},
.vogrfcfg = {
{
- .hpd_trigger = RK_UDPHY_GEN_GRF_REG(0x0000, 11, 10, 1, 3),
.dp_lane_reg = 0x0000,
},
{
- .hpd_trigger = RK_UDPHY_GEN_GRF_REG(0x0008, 11, 10, 1, 3),
.dp_lane_reg = 0x0008,
},
},
@@ -1653,7 +1587,6 @@ static struct platform_driver rk_udphy_driver = {
.driver = {
.name = "rockchip-usbdp-phy",
.of_match_table = rk_udphy_dt_match,
- .pm = &rk_udphy_pm_ops,
},
};
module_platform_driver(rk_udphy_driver);
--
2.53.0
^ permalink raw reply related
* Re: [PATCH v2 0/3] arm64: perf: Skip device memory during user callchain unwinding
From: Will Deacon @ 2026-06-19 15:31 UTC (permalink / raw)
To: Fredrik Markstrom
Cc: Catalin Marinas, Shuah Khan, Peter Zijlstra, Ingo Molnar,
Arnaldo Carvalho de Melo, Namhyung Kim, Mark Rutland,
Alexander Shishkin, Jiri Olsa, Ian Rogers, Adrian Hunter,
James Clark, Santosh Shilimkar, Olof Johansson, Tony Lindgren,
linux-arm-kernel, linux-kernel, linux-kselftest, linux-perf-users,
Nicolas Pitre, Ivar Holmqvist, Malin Jonsson
In-Reply-To: <agweYAbxRWOs41BE@elx-5cg6022w5t>
On Tue, May 19, 2026 at 10:25:04AM +0200, Fredrik Markstrom wrote:
> On Mon, May 18, 2026 at 04:06:11PM +0100, Will Deacon wrote:
> > On Thu, Apr 30, 2026 at 12:55:12PM +0200, Fredrik Markstrom wrote:
> > > Perf callchain unwinding follows userspace frame pointers via
> > > copy_from_user. A corrupted or malicious frame pointer can point
> > > into device I/O memory mapped into the process (e.g. via UIO or
> > > /dev/mem), causing the kernel to read from MMIO regions in PMU
> > > interrupt context. Such reads can have side effects on hardware
> > > (clearing status registers, advancing FIFOs, triggering DMA) and
> > > on arm64 can produce a synchronous external abort that panics the
> > > kernel.
> >
> > Hmm, but why is unwinding special in this case? If userspace has access
> > to sensitive MMIO/device mappings, it can presumably pass them to
> > syscalls and trigger crashes all over the place?
>
> You’re totally right, a broken app with access to hardware like this can
> already cause chaos by passing bad pointers to syscalls etc. But the big
> difference here is who is to blame when things crash.
>
> If an app passes a bad pointer to a syscall, it’s self-inflicted.
So I was going to argue that building arm64 code without frame-pointers
is self-inflicted, but it looks like that's the default in GCC for some
bizarre reason.
> Unwinding here is asynchronous and unrelated to the application.
> Perf interrupts a perfectly healthy app at a random moment. If that app
> is using the frame pointer as a normal register (totally legal in
> optimized code), it might hold a junk value that points to MMIO memory.
>
> If the kernel blindly follows that junk pointer during an unwind, perf
> causes the crash. I think it's acceptable that an app (with hardware
> access) causes a crash if buggy, but I don't think it's acceptable that
> a profiling tool is causing a crash just by looking at it.
I can see your argument, but I'm also not hugely keen to add fastgup to
our stack unwinder for each frame record. It's also not clear to me how
you avoid the mapping changing between the check and the access, given
that you still appear to use the user mapping for the unwind. Do other
architectures have this issue and, if so, how do they solve it?
If we could guarantee that the fault is synchronous, then we could
presumably hook up the uaccess exception fixup handlers.
Will
^ permalink raw reply
* Re: [PATCH v7 0/2] PCI: Configure Root Port MPS during host probing
From: Hans Zhang @ 2026-06-19 15:29 UTC (permalink / raw)
To: bhelgaas, Manivannan Sadhasivam, Bjorn Helgaas
Cc: lpieralisi, kwilczynski, heiko, yue.wang, pali, neil.armstrong,
robh, jingoohan1, khilman, jbrunet, martin.blumenstingl, cassel,
linux-pci, linux-kernel, linux-arm-kernel, linux-amlogic,
linux-rockchip
In-Reply-To: <vpuzlzry7uulctur7kwtlogniuhogd5ybmrwjtos2v7yryf47v@yj2ocobbog6s>
On 5/6/26 22:00, Manivannan Sadhasivam wrote:
> On Fri, Nov 28, 2025 at 01:09:06AM +0800, Hans Zhang wrote:
>> Current PCIe initialization exhibits a key optimization gap: Root Ports
>> may operate with non-optimal Maximum Payload Size (MPS) settings. While
>> downstream device configuration is handled during bus enumeration, Root
>> Port MPS values inherited from firmware or hardware defaults often fail
>> to utilize the full capabilities supported by controller hardware. This
>> results in suboptimal data transfer efficiency throughout the PCIe
>> hierarchy.
>>
>> This patch series addresses this by:
>>
>> 1. Core PCI enhancement (Patch 1):
>> - Proactively configures Root Port MPS during host controller probing
>> - Sets initial MPS to hardware maximum (128 << dev->pcie_mpss)
>> - Conditional on PCIe bus tuning being enabled (PCIE_BUS_TUNE_OFF unset)
>> and not in PCIE_BUS_PEER2PEER mode (which requires default 128 bytes)
>> - Maintains backward compatibility via PCIE_BUS_TUNE_OFF check
>> - Preserves standard MPS negotiation during downstream enumeration
>>
>> 2. Driver cleanup (Patch 2):
>> - Removes redundant MPS configuration from Meson PCIe controller driver
>> - Functionality is now centralized in PCI core
>> - Simplifies driver maintenance long-term
>>
>
> For the series,
>
> Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
>
> Bjorn: Could you please take a look? This series has been floating for a
> while...
Hello Bjorn,
Any chance for this series to be applied?
Best regards,
Hans
>
> - Mani
>
>> ---
>> Changes in v7:
>> - Exclude PCIE_BUS_PEER2PEER mode from Root Port MPS configuration
>> - Remove redundant check for upstream bridge (Root Ports don't have one)
>> - Improve commit message and code comments as per Bjorn.
>>
>> Changes for v6:
>> https://patchwork.kernel.org/project/linux-pci/patch/20251104165125.174168-1-18255117159@163.com/
>>
>> - Modify the commit message and comments. (Bjorn)
>> - Patch 1/2 code logic: Add !bridge check to configure MPS only for Root Ports
>> without an upstream bridge (root bridges), avoiding incorrect handling of
>> non-root-bridge Root Ports (Niklas).
>>
>> Changes for v5:
>> https://patchwork.kernel.org/project/linux-pci/patch/20250620155507.1022099-1-18255117159@163.com/
>>
>> - Use pcie_set_mps directly instead of pcie_write_mps.
>> - The patch 1 commit message were modified.
>>
>> Changes for v4:
>> https://patchwork.kernel.org/project/linux-pci/patch/20250510155607.390687-1-18255117159@163.com/
>>
>> - The patch [v4 1/2] add a comment to explain why it was done this way.
>> - The patch [v4 2/2] have not been modified.
>> - Drop patch [v3 3/3]. The Maintainer of the pci-aardvark.c file suggests
>> that this patch cannot be submitted. In addition, Mani also suggests
>> dropping this patch until this series of issues is resolved.
>>
>> Changes for v3:
>> https://patchwork.kernel.org/project/linux-pci/patch/20250506173439.292460-1-18255117159@163.com/
>>
>> - The new split is patch 2/3 and 3/3.
>> - Modify the patch 1/3 according to Niklas' suggestion.
>>
>> Changes for v2:
>> https://patchwork.kernel.org/project/linux-pci/patch/20250425095708.32662-1-18255117159@163.com/
>>
>> - According to the Maintainer's suggestion, limit the setting of MPS
>> changes to platforms with controller drivers.
>> - Delete the MPS code set by the SOC manufacturer.
>> ---
>>
>> Hans Zhang (2):
>> PCI: Configure Root Port MPS during host probing
>> PCI: dwc: Remove redundant MPS configuration
>>
>> drivers/pci/controller/dwc/pci-meson.c | 17 -----------------
>> drivers/pci/probe.c | 12 ++++++++++++
>> 2 files changed, 12 insertions(+), 17 deletions(-)
>>
>>
>> base-commit: 765e56e41a5af2d456ddda6cbd617b9d3295ab4e
>> --
>> 2.34.1
>>
>
^ permalink raw reply
* [PATCH v6 20/23] phy: rockchip: usbdp: Use guard functions for mutex
From: Sebastian Reichel @ 2026-06-19 15:29 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Heiko Stuebner, Frank Wang,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Andy Yan, Dmitry Baryshkov, Yubing Zhang, Alexey Charkov,
linux-phy, linux-arm-kernel, linux-rockchip, linux-kernel, kernel,
devicetree, Sebastian Reichel
In-Reply-To: <20260619-rockchip-usbdp-cleanup-v6-0-3bb1f54b3f35@collabora.com>
Convert the driver to use guard functions for mutex handling as
a small cleanup. There is a small functional change in the DP PHY
power up function, which no longer sleeps if the internal powerup
code returns an error. This is not a problem as the sleep is only
relevant for successful power-up.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/phy/rockchip/phy-rockchip-usbdp.c | 54 +++++++++++++------------------
1 file changed, 23 insertions(+), 31 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c
index 46ab9fb45ca4..81aae3bc5747 100644
--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
@@ -10,6 +10,7 @@
#include <dt-bindings/phy/phy.h>
#include <linux/bitfield.h>
#include <linux/bits.h>
+#include <linux/cleanup.h>
#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/gpio.h>
@@ -652,14 +653,15 @@ static int rk_udphy_orien_sw_set(struct typec_switch_dev *sw,
struct rk_udphy *udphy = typec_switch_get_drvdata(sw);
bool flipped = orien == TYPEC_ORIENTATION_REVERSE;
- mutex_lock(&udphy->mutex);
+ guard(mutex)(&udphy->mutex);
if (orien == TYPEC_ORIENTATION_NONE) {
gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 0);
gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 0);
/* unattached */
rk_udphy_usb_bvalid_enable(udphy, false);
- goto unlock_ret;
+
+ return 0;
}
if (udphy->flip != flipped)
@@ -669,8 +671,6 @@ static int rk_udphy_orien_sw_set(struct typec_switch_dev *sw,
rk_udphy_set_typec_default_mapping(udphy);
rk_udphy_usb_bvalid_enable(udphy, true);
-unlock_ret:
- mutex_unlock(&udphy->mutex);
return 0;
}
@@ -1044,26 +1044,25 @@ static int rk_udphy_dp_phy_power_on(struct phy *phy)
struct rk_udphy *udphy = phy_get_drvdata(phy);
int ret;
- mutex_lock(&udphy->mutex);
+ scoped_guard(mutex, &udphy->mutex) {
+ phy_set_bus_width(phy, udphy->dp_lanes);
- phy_set_bus_width(phy, udphy->dp_lanes);
-
- ret = rk_udphy_power_on(udphy, UDPHY_MODE_DP);
- if (ret)
- goto unlock;
+ ret = rk_udphy_power_on(udphy, UDPHY_MODE_DP);
+ if (ret)
+ return ret;
- rk_udphy_dp_lane_enable(udphy, udphy->dp_lanes);
+ rk_udphy_dp_lane_enable(udphy, udphy->dp_lanes);
- rk_udphy_dp_lane_select(udphy);
+ rk_udphy_dp_lane_select(udphy);
+ }
-unlock:
- mutex_unlock(&udphy->mutex);
/*
* If data send by aux channel too fast after phy power on,
* the aux may be not ready which will cause aux error. Adding
* delay to avoid this issue.
*/
usleep_range(10000, 11000);
+
return ret;
}
@@ -1071,10 +1070,10 @@ static int rk_udphy_dp_phy_power_off(struct phy *phy)
{
struct rk_udphy *udphy = phy_get_drvdata(phy);
- mutex_lock(&udphy->mutex);
+ guard(mutex)(&udphy->mutex);
+
rk_udphy_dp_lane_enable(udphy, 0);
rk_udphy_power_off(udphy, UDPHY_MODE_DP);
- mutex_unlock(&udphy->mutex);
return 0;
}
@@ -1279,35 +1278,30 @@ static const struct phy_ops rk_udphy_dp_phy_ops = {
static int rk_udphy_usb3_phy_init(struct phy *phy)
{
struct rk_udphy *udphy = phy_get_drvdata(phy);
- int ret = 0;
- mutex_lock(&udphy->mutex);
+ guard(mutex)(&udphy->mutex);
+
/* DP only or high-speed, disable U3 port */
if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) {
rk_udphy_u3_port_disable(udphy, true);
- goto unlock;
+ return 0;
}
- ret = rk_udphy_power_on(udphy, UDPHY_MODE_USB);
-
-unlock:
- mutex_unlock(&udphy->mutex);
- return ret;
+ return rk_udphy_power_on(udphy, UDPHY_MODE_USB);
}
static int rk_udphy_usb3_phy_exit(struct phy *phy)
{
struct rk_udphy *udphy = phy_get_drvdata(phy);
- mutex_lock(&udphy->mutex);
+ guard(mutex)(&udphy->mutex);
+
/* DP only or high-speed */
if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs)
- goto unlock;
+ return 0;
rk_udphy_power_off(udphy, UDPHY_MODE_USB);
-unlock:
- mutex_unlock(&udphy->mutex);
return 0;
}
@@ -1330,12 +1324,10 @@ static int rk_udphy_typec_mux_set(struct typec_mux_dev *mux,
if (!state->alt || state->alt->svid != USB_TYPEC_DP_SID)
return 0;
- mutex_lock(&udphy->mutex);
+ guard(mutex)(&udphy->mutex);
rk_udphy_set_typec_state(udphy, state->mode);
- mutex_unlock(&udphy->mutex);
-
return 0;
}
--
2.53.0
^ permalink raw reply related
* [PATCH v6 23/23] phy: rockchip: usbdp: Add some extra debug messages
From: Sebastian Reichel @ 2026-06-19 15:29 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Heiko Stuebner, Frank Wang,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Andy Yan, Dmitry Baryshkov, Yubing Zhang, Alexey Charkov,
linux-phy, linux-arm-kernel, linux-rockchip, linux-kernel, kernel,
devicetree, Sebastian Reichel
In-Reply-To: <20260619-rockchip-usbdp-cleanup-v6-0-3bb1f54b3f35@collabora.com>
It's useful to log PHY reinit to ease debugging issues around
USB-C hotplugging.
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/phy/rockchip/phy-rockchip-usbdp.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c
index 8c59c50f207e..6e80dfeee0e5 100644
--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
@@ -24,6 +24,7 @@
#include <linux/property.h>
#include <linux/regmap.h>
#include <linux/reset.h>
+#include <linux/string_choices.h>
#include <linux/usb/ch9.h>
#include <linux/usb/typec_dp.h>
#include <linux/usb/typec_mux.h>
@@ -491,6 +492,8 @@ static void rk_udphy_u3_port_disable(struct rk_udphy *udphy, u8 disable)
const struct rk_udphy_cfg *cfg = udphy->cfgs;
const struct rk_udphy_grf_reg *preg;
+ dev_dbg(udphy->dev, "USB3 port %s\n", str_on_off(!disable));
+
preg = udphy->id ? &cfg->grfcfg.usb3otg1_cfg : &cfg->grfcfg.usb3otg0_cfg;
rk_udphy_grfreg_write(udphy->usbgrf, preg, disable);
}
@@ -784,6 +787,10 @@ static int rk_udphy_init(struct rk_udphy *udphy)
const struct rk_udphy_cfg *cfg = udphy->cfgs;
int ret;
+ dev_dbg(udphy->dev, "(re-)init PHY with USB=%s and DP=%s\n",
+ str_enabled_disabled(udphy->mode & UDPHY_MODE_USB),
+ str_enabled_disabled(udphy->mode & UDPHY_MODE_DP));
+
rk_udphy_reset_assert_all(udphy);
usleep_range(10000, 11000);
@@ -854,6 +861,8 @@ static int rk_udphy_setup(struct rk_udphy *udphy)
{
int ret;
+ dev_dbg(udphy->dev, "enable PHY\n");
+
ret = clk_bulk_prepare_enable(udphy->num_clks, udphy->clks);
if (ret) {
dev_err(udphy->dev, "failed to enable clk\n");
@@ -872,6 +881,7 @@ static int rk_udphy_setup(struct rk_udphy *udphy)
static void rk_udphy_disable(struct rk_udphy *udphy)
{
+ dev_dbg(udphy->dev, "disable PHY\n");
clk_bulk_disable_unprepare(udphy->num_clks, udphy->clks);
rk_udphy_reset_assert_all(udphy);
}
--
2.53.0
^ permalink raw reply related
* [PATCH v6 15/23] phy: rockchip: usbdp: Register DP aux bridge
From: Sebastian Reichel @ 2026-06-19 15:29 UTC (permalink / raw)
To: Vinod Koul, Neil Armstrong, Heiko Stuebner, Frank Wang,
Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Andy Yan, Dmitry Baryshkov, Yubing Zhang, Alexey Charkov,
linux-phy, linux-arm-kernel, linux-rockchip, linux-kernel, kernel,
devicetree, Sebastian Reichel
In-Reply-To: <20260619-rockchip-usbdp-cleanup-v6-0-3bb1f54b3f35@collabora.com>
Add support to use USB-C connectors with the DP altmode helper code on
devicetree based platforms. To get this working there must be a DRM
bridge chain from the DisplayPort controller to the USB-C connector.
E.g. on Rockchip RK3576:
root@rk3576 # cat /sys/kernel/debug/dri/0/encoder-0/bridges
bridge[0]: dw_dp_bridge_funcs
refcount: 7
type: [10] DP
OF: /soc/dp@27e40000:rockchip,rk3576-dp
ops: [0x47] detect edid hpd
bridge[1]: drm_aux_bridge_funcs
refcount: 4
type: [0] Unknown
OF: /soc/phy@2b010000:rockchip,rk3576-usbdp-phy
ops: [0x0]
bridge[2]: drm_aux_hpd_bridge_funcs
refcount: 5
type: [10] DP
OF: /soc/i2c@2ac50000/typec-portc@22/connector:usb-c-connector
ops: [0x4] hpd
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
---
drivers/phy/rockchip/Kconfig | 2 ++
drivers/phy/rockchip/phy-rockchip-usbdp.c | 14 ++++++++++++++
2 files changed, 16 insertions(+)
diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig
index 14698571b607..39759bb2fa1d 100644
--- a/drivers/phy/rockchip/Kconfig
+++ b/drivers/phy/rockchip/Kconfig
@@ -136,8 +136,10 @@ config PHY_ROCKCHIP_USBDP
tristate "Rockchip USBDP COMBO PHY Driver"
depends on ARCH_ROCKCHIP && OF
depends on TYPEC
+ depends on DRM || DRM=n
select GENERIC_PHY
select USB_COMMON
+ select DRM_AUX_BRIDGE if DRM_BRIDGE
help
Enable this to support the Rockchip USB3.0/DP combo PHY with
Samsung IP block. This is required for USB3 support on RK3588.
diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c b/drivers/phy/rockchip/phy-rockchip-usbdp.c
index da769790df98..b75c190a4311 100644
--- a/drivers/phy/rockchip/phy-rockchip-usbdp.c
+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
@@ -6,6 +6,7 @@
* Copyright (C) 2024 Collabora Ltd
*/
+#include <drm/bridge/aux-bridge.h>
#include <dt-bindings/phy/phy.h>
#include <linux/bitfield.h>
#include <linux/bits.h>
@@ -1438,6 +1439,7 @@ static int rk_udphy_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct phy_provider *phy_provider;
+ struct fwnode_handle *dp_aux_ep;
struct resource *res;
struct rk_udphy *udphy;
void __iomem *base;
@@ -1496,6 +1498,18 @@ static int rk_udphy_probe(struct platform_device *pdev)
return ret;
}
+ /*
+ * Only register the DRM bridge, if the DP aux channel is connected.
+ * Some boards use the USBDP PHY only for its USB3 capabilities.
+ */
+ dp_aux_ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), 3, 0, 0);
+ if (dp_aux_ep) {
+ ret = drm_aux_bridge_register(dev);
+ fwnode_handle_put(dp_aux_ep);
+ if (ret)
+ return ret;
+ }
+
udphy->phy_u3 = devm_phy_create(dev, dev->of_node, &rk_udphy_usb3_phy_ops);
if (IS_ERR(udphy->phy_u3)) {
ret = PTR_ERR(udphy->phy_u3);
--
2.53.0
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox