* [PATCH] mfd: db8500-prcmu: Fold dbx500 header into db8500
From: Linus Walleij @ 2026-06-19 20:27 UTC (permalink / raw)
To: Russell King, Ulf Hansson, Michael Turquette, Stephen Boyd,
Brian Masney, Rafael J. Wysocki, Daniel Lezcano, Christian Loehle,
Lee Jones, Liam Girdwood, Mark Brown, Zhang Rui, Lukasz Luba,
Wim Van Sebroeck, Guenter Roeck, Jaroslav Kysela, Takashi Iwai
Cc: linux-arm-kernel, linux-clk, linux-pm, linux-watchdog,
linux-sound, kernel test robot, Linus Walleij
Move the DBx500 PRCMU definitions into the DB8500 PRCMU
header and delete the wrapper header.
Convert users of simple PRCMU wrappers to call the DB8500 helpers
directly.
The dbx500-prcmu.h header was the result of an earlier attempt to
abstract several DBx5x SoC PRCMU units to use the same abstract
header. They are deleted from the kernel and this is not just
causing maintenance burden and build errors.
The stub code is using -ENOSYS in a way checkpatch complains about
so replace these with -EINVAL while we're at it.
Assisted-by: Codex:gpt-5-5
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202606180825.vUSQntkJ-lkp@intel.com/
Signed-off-by: Linus Walleij <linusw@kernel.org>
---
| 6 +-
| 20 +-
| 2 +-
| 6 +-
| 2 +-
| 6 +-
| 12 +-
| 10 +-
| 22 +-
| 252 ++++++++++++++++-
| 575 ---------------------------------------
| 2 +-
12 files changed, 294 insertions(+), 621 deletions(-)
--git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index b1a70f203372..0d7530fb6ad0 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -12,7 +12,7 @@
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/irqchip/arm-gic.h>
-#include <linux/mfd/dbx500-prcmu.h>
+#include <linux/mfd/db8500-prcmu.h>
#include <linux/platform_data/arm-ux500-pm.h>
#include <linux/platform_device.h>
#include <linux/io.h>
@@ -81,7 +81,7 @@ static void __init ux500_init_irq(void)
struct resource r;
irqchip_init();
- prcmu_early_init();
+ db8500_prcmu_early_init();
np = of_find_compatible_node(NULL, NULL, "stericsson,db8500-prcmu");
of_address_to_resource(np, 0, &r);
of_node_put(np);
@@ -101,7 +101,7 @@ static void ux500_restart(enum reboot_mode mode, const char *cmd)
local_irq_disable();
local_fiq_disable();
- prcmu_system_reset(0);
+ db8500_prcmu_system_reset(0);
}
static const struct of_device_id u8500_local_bus_nodes[] = {
--git a/drivers/clk/ux500/clk-prcmu.c b/drivers/clk/ux500/clk-prcmu.c
index ddc86551bf57..ac96c46bd1bb 100644
--- a/drivers/clk/ux500/clk-prcmu.c
+++ b/drivers/clk/ux500/clk-prcmu.c
@@ -7,7 +7,7 @@
*/
#include <linux/clk-provider.h>
-#include <linux/mfd/dbx500-prcmu.h>
+#include <linux/mfd/db8500-prcmu.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/err.h>
@@ -35,13 +35,13 @@ static int clk_prcmu_prepare(struct clk_hw *hw)
{
struct clk_prcmu *clk = to_clk_prcmu(hw);
- return prcmu_request_clock(clk->cg_sel, true);
+ return db8500_prcmu_request_clock(clk->cg_sel, true);
}
static void clk_prcmu_unprepare(struct clk_hw *hw)
{
struct clk_prcmu *clk = to_clk_prcmu(hw);
- if (prcmu_request_clock(clk->cg_sel, false))
+ if (db8500_prcmu_request_clock(clk->cg_sel, false))
pr_err("clk_prcmu: %s failed to disable %s.\n", __func__,
clk_hw_get_name(hw));
}
@@ -86,7 +86,7 @@ static int clk_prcmu_opp_prepare(struct clk_hw *hw)
clk->opp_requested = 1;
}
- err = prcmu_request_clock(clk->cg_sel, true);
+ err = db8500_prcmu_request_clock(clk->cg_sel, true);
if (err) {
prcmu_qos_remove_requirement(PRCMU_QOS_APE_OPP,
(char *)clk_hw_get_name(hw));
@@ -101,7 +101,7 @@ static void clk_prcmu_opp_unprepare(struct clk_hw *hw)
{
struct clk_prcmu *clk = to_clk_prcmu(hw);
- if (prcmu_request_clock(clk->cg_sel, false)) {
+ if (db8500_prcmu_request_clock(clk->cg_sel, false)) {
pr_err("clk_prcmu: %s failed to disable %s.\n", __func__,
clk_hw_get_name(hw));
return;
@@ -120,7 +120,7 @@ static int clk_prcmu_opp_volt_prepare(struct clk_hw *hw)
struct clk_prcmu *clk = to_clk_prcmu(hw);
if (!clk->opp_requested) {
- err = prcmu_request_ape_opp_100_voltage(true);
+ err = db8500_prcmu_request_ape_opp_100_voltage(true);
if (err) {
pr_err("clk_prcmu: %s fail req APE OPP VOLT for %s.\n",
__func__, clk_hw_get_name(hw));
@@ -129,9 +129,9 @@ static int clk_prcmu_opp_volt_prepare(struct clk_hw *hw)
clk->opp_requested = 1;
}
- err = prcmu_request_clock(clk->cg_sel, true);
+ err = db8500_prcmu_request_clock(clk->cg_sel, true);
if (err) {
- prcmu_request_ape_opp_100_voltage(false);
+ db8500_prcmu_request_ape_opp_100_voltage(false);
clk->opp_requested = 0;
return err;
}
@@ -143,14 +143,14 @@ static void clk_prcmu_opp_volt_unprepare(struct clk_hw *hw)
{
struct clk_prcmu *clk = to_clk_prcmu(hw);
- if (prcmu_request_clock(clk->cg_sel, false)) {
+ if (db8500_prcmu_request_clock(clk->cg_sel, false)) {
pr_err("clk_prcmu: %s failed to disable %s.\n", __func__,
clk_hw_get_name(hw));
return;
}
if (clk->opp_requested) {
- prcmu_request_ape_opp_100_voltage(false);
+ db8500_prcmu_request_ape_opp_100_voltage(false);
clk->opp_requested = 0;
}
}
--git a/drivers/clk/ux500/u8500_of_clk.c b/drivers/clk/ux500/u8500_of_clk.c
index 6f78808387b1..d2499815226f 100644
--- a/drivers/clk/ux500/u8500_of_clk.c
+++ b/drivers/clk/ux500/u8500_of_clk.c
@@ -9,7 +9,7 @@
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/clk-provider.h>
-#include <linux/mfd/dbx500-prcmu.h>
+#include <linux/mfd/db8500-prcmu.h>
#include "clk.h"
#include "prcc.h"
--git a/drivers/cpuidle/cpuidle-ux500.c b/drivers/cpuidle/cpuidle-ux500.c
index f7d778580e9b..6d6c52c0bcc2 100644
--- a/drivers/cpuidle/cpuidle-ux500.c
+++ b/drivers/cpuidle/cpuidle-ux500.c
@@ -11,7 +11,7 @@
#include <linux/spinlock.h>
#include <linux/atomic.h>
#include <linux/smp.h>
-#include <linux/mfd/dbx500-prcmu.h>
+#include <linux/mfd/db8500-prcmu.h>
#include <linux/platform_data/arm-ux500-pm.h>
#include <linux/platform_device.h>
@@ -66,7 +66,7 @@ static inline int ux500_enter_idle(struct cpuidle_device *dev,
/* Go to the retention state, the prcmu will wait for the
* cpu to go WFI and this is what happens after exiting this
* 'master' critical section */
- if (prcmu_set_power_state(PRCMU_AP_IDLE, true, true))
+ if (db8500_prcmu_set_power_state(PRCMU_AP_IDLE, true, true))
goto out;
/* When we switch to retention, the prcmu is in charge
@@ -109,7 +109,7 @@ static struct cpuidle_driver ux500_idle_driver = {
static int dbx500_cpuidle_probe(struct platform_device *pdev)
{
/* Configure wake up reasons */
- prcmu_enable_wakeups(PRCMU_WAKEUP(ARM) | PRCMU_WAKEUP(RTC) |
+ db8500_prcmu_enable_wakeups(PRCMU_WAKEUP(ARM) | PRCMU_WAKEUP(RTC) |
PRCMU_WAKEUP(ABB));
return cpuidle_register(&ux500_idle_driver, NULL);
--git a/drivers/mfd/ab8500-core.c b/drivers/mfd/ab8500-core.c
index f0bc0b5a6f4a..86fa99022cb3 100644
--- a/drivers/mfd/ab8500-core.c
+++ b/drivers/mfd/ab8500-core.c
@@ -19,7 +19,7 @@
#include <linux/mfd/core.h>
#include <linux/mfd/abx500.h>
#include <linux/mfd/abx500/ab8500.h>
-#include <linux/mfd/dbx500-prcmu.h>
+#include <linux/mfd/db8500-prcmu.h>
#include <linux/of.h>
/*
--git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c
index 21e68a382b11..6672c55f2ebc 100644
--- a/drivers/mfd/db8500-prcmu.c
+++ b/drivers/mfd/db8500-prcmu.c
@@ -32,7 +32,7 @@
#include <linux/platform_device.h>
#include <linux/uaccess.h>
#include <linux/mfd/core.h>
-#include <linux/mfd/dbx500-prcmu.h>
+#include <linux/mfd/db8500-prcmu.h>
#include <linux/mfd/abx500/ab8500.h>
#include <linux/regulator/db8500-prcmu.h>
#include <linux/regulator/machine.h>
@@ -2285,7 +2285,7 @@ void db8500_prcmu_system_reset(u16 reset_code)
/**
* db8500_prcmu_get_reset_code - Retrieve SW reset reason code
*
- * Retrieves the reset reason code stored by prcmu_system_reset() before
+ * Retrieves the reset reason code stored by db8500_prcmu_system_reset() before
* last restart.
*/
u16 db8500_prcmu_get_reset_code(void)
@@ -3041,7 +3041,7 @@ static int db8500_prcmu_probe(struct platform_device *pdev)
db8500_irq_init(np);
- prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET);
+ db8500_prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET);
err = mfd_add_devices(&pdev->dev, 0, common_prcmu_devs,
ARRAY_SIZE(common_prcmu_devs), NULL, 0, db8500_irq_domain);
--git a/drivers/regulator/db8500-prcmu.c b/drivers/regulator/db8500-prcmu.c
index 1ec2e1348891..751fe36580fa 100644
--- a/drivers/regulator/db8500-prcmu.c
+++ b/drivers/regulator/db8500-prcmu.c
@@ -13,7 +13,7 @@
#include <linux/err.h>
#include <linux/spinlock.h>
#include <linux/platform_device.h>
-#include <linux/mfd/dbx500-prcmu.h>
+#include <linux/mfd/db8500-prcmu.h>
#include <linux/regulator/driver.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/db8500-prcmu.h>
@@ -93,13 +93,13 @@ static int enable_epod(u16 epod_id, bool ramret)
if (ramret) {
if (!epod_on[epod_id]) {
- ret = prcmu_set_epod(epod_id, EPOD_STATE_RAMRET);
+ ret = db8500_prcmu_set_epod(epod_id, EPOD_STATE_RAMRET);
if (ret < 0)
return ret;
}
epod_ramret[epod_id] = true;
} else {
- ret = prcmu_set_epod(epod_id, EPOD_STATE_ON);
+ ret = db8500_prcmu_set_epod(epod_id, EPOD_STATE_ON);
if (ret < 0)
return ret;
epod_on[epod_id] = true;
@@ -114,18 +114,18 @@ static int disable_epod(u16 epod_id, bool ramret)
if (ramret) {
if (!epod_on[epod_id]) {
- ret = prcmu_set_epod(epod_id, EPOD_STATE_OFF);
+ ret = db8500_prcmu_set_epod(epod_id, EPOD_STATE_OFF);
if (ret < 0)
return ret;
}
epod_ramret[epod_id] = false;
} else {
if (epod_ramret[epod_id]) {
- ret = prcmu_set_epod(epod_id, EPOD_STATE_RAMRET);
+ ret = db8500_prcmu_set_epod(epod_id, EPOD_STATE_RAMRET);
if (ret < 0)
return ret;
} else {
- ret = prcmu_set_epod(epod_id, EPOD_STATE_OFF);
+ ret = db8500_prcmu_set_epod(epod_id, EPOD_STATE_OFF);
if (ret < 0)
return ret;
}
--git a/drivers/thermal/db8500_thermal.c b/drivers/thermal/db8500_thermal.c
index 576f88b6a1b3..cf1706569e6d 100644
--- a/drivers/thermal/db8500_thermal.c
+++ b/drivers/thermal/db8500_thermal.c
@@ -10,7 +10,7 @@
#include <linux/cpu_cooling.h>
#include <linux/interrupt.h>
-#include <linux/mfd/dbx500-prcmu.h>
+#include <linux/mfd/db8500-prcmu.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
@@ -82,7 +82,7 @@ static void db8500_thermal_update_config(struct db8500_thermal_zone *th,
unsigned long next_low,
unsigned long next_high)
{
- prcmu_stop_temp_sense();
+ db8500_prcmu_stop_temp_sense();
th->cur_index = idx;
th->interpolated_temp = (next_low + next_high)/2;
@@ -91,8 +91,8 @@ static void db8500_thermal_update_config(struct db8500_thermal_zone *th,
* The PRCMU accept absolute temperatures in celsius so divide
* down the millicelsius with 1000
*/
- prcmu_config_hotmon((u8)(next_low/1000), (u8)(next_high/1000));
- prcmu_start_temp_sense(PRCMU_DEFAULT_MEASURE_TIME);
+ db8500_prcmu_config_hotmon((u8)(next_low / 1000), (u8)(next_high / 1000));
+ db8500_prcmu_start_temp_sense(PRCMU_DEFAULT_MEASURE_TIME);
}
static irqreturn_t prcmu_low_irq_handler(int irq, void *irq_data)
@@ -204,7 +204,7 @@ static int db8500_thermal_probe(struct platform_device *pdev)
static int db8500_thermal_suspend(struct platform_device *pdev,
pm_message_t state)
{
- prcmu_stop_temp_sense();
+ db8500_prcmu_stop_temp_sense();
return 0;
}
--git a/drivers/watchdog/db8500_wdt.c b/drivers/watchdog/db8500_wdt.c
index 97148ac0aa54..70ccea13288d 100644
--- a/drivers/watchdog/db8500_wdt.c
+++ b/drivers/watchdog/db8500_wdt.c
@@ -16,7 +16,7 @@
#include <linux/watchdog.h>
#include <linux/platform_device.h>
-#include <linux/mfd/dbx500-prcmu.h>
+#include <linux/mfd/db8500-prcmu.h>
#define WATCHDOG_TIMEOUT 600 /* 10 minutes */
@@ -37,24 +37,24 @@ MODULE_PARM_DESC(nowayout,
static int db8500_wdt_start(struct watchdog_device *wdd)
{
- return prcmu_enable_a9wdog(PRCMU_WDOG_ALL);
+ return db8500_prcmu_enable_a9wdog(PRCMU_WDOG_ALL);
}
static int db8500_wdt_stop(struct watchdog_device *wdd)
{
- return prcmu_disable_a9wdog(PRCMU_WDOG_ALL);
+ return db8500_prcmu_disable_a9wdog(PRCMU_WDOG_ALL);
}
static int db8500_wdt_keepalive(struct watchdog_device *wdd)
{
- return prcmu_kick_a9wdog(PRCMU_WDOG_ALL);
+ return db8500_prcmu_kick_a9wdog(PRCMU_WDOG_ALL);
}
static int db8500_wdt_set_timeout(struct watchdog_device *wdd,
unsigned int timeout)
{
db8500_wdt_stop(wdd);
- prcmu_load_a9wdog(PRCMU_WDOG_ALL, timeout * 1000);
+ db8500_prcmu_load_a9wdog(PRCMU_WDOG_ALL, timeout * 1000);
db8500_wdt_start(wdd);
return 0;
@@ -91,10 +91,10 @@ static int db8500_wdt_probe(struct platform_device *pdev)
watchdog_set_nowayout(&db8500_wdt, nowayout);
/* disable auto off on sleep */
- prcmu_config_a9wdog(PRCMU_WDOG_CPU1, false);
+ db8500_prcmu_config_a9wdog(PRCMU_WDOG_CPU1, false);
/* set HW initial value */
- prcmu_load_a9wdog(PRCMU_WDOG_ALL, timeout * 1000);
+ db8500_prcmu_load_a9wdog(PRCMU_WDOG_ALL, timeout * 1000);
ret = devm_watchdog_register_device(dev, &db8500_wdt);
if (ret)
@@ -110,9 +110,9 @@ static int db8500_wdt_suspend(struct platform_device *pdev,
{
if (watchdog_active(&db8500_wdt)) {
db8500_wdt_stop(&db8500_wdt);
- prcmu_config_a9wdog(PRCMU_WDOG_CPU1, true);
+ db8500_prcmu_config_a9wdog(PRCMU_WDOG_CPU1, true);
- prcmu_load_a9wdog(PRCMU_WDOG_ALL, timeout * 1000);
+ db8500_prcmu_load_a9wdog(PRCMU_WDOG_ALL, timeout * 1000);
db8500_wdt_start(&db8500_wdt);
}
return 0;
@@ -122,9 +122,9 @@ static int db8500_wdt_resume(struct platform_device *pdev)
{
if (watchdog_active(&db8500_wdt)) {
db8500_wdt_stop(&db8500_wdt);
- prcmu_config_a9wdog(PRCMU_WDOG_CPU1, false);
+ db8500_prcmu_config_a9wdog(PRCMU_WDOG_CPU1, false);
- prcmu_load_a9wdog(PRCMU_WDOG_ALL, timeout * 1000);
+ db8500_prcmu_load_a9wdog(PRCMU_WDOG_ALL, timeout * 1000);
db8500_wdt_start(&db8500_wdt);
}
return 0;
--git a/include/linux/mfd/db8500-prcmu.h b/include/linux/mfd/db8500-prcmu.h
index a62de3d155ed..c939c9a1170a 100644
--- a/include/linux/mfd/db8500-prcmu.h
+++ b/include/linux/mfd/db8500-prcmu.h
@@ -12,6 +12,9 @@
#include <linux/interrupt.h>
#include <linux/bitops.h>
+#include <linux/err.h>
+
+#include <dt-bindings/mfd/dbx500-prcmu.h> /* For clock identifiers */
/*
* Registers
@@ -24,6 +27,38 @@
#define DB8500_PRCM_DSI_SW_RESET_DSI1_SW_RESETN BIT(1)
#define DB8500_PRCM_DSI_SW_RESET_DSI2_SW_RESETN BIT(2)
+/* Offset for the firmware version within the TCPM */
+#define DB8500_PRCMU_FW_VERSION_OFFSET 0xA4
+
+#define DB8500_PRCMU_LEGACY_OFFSET 0xDD4
+
+/*
+ * CLKOUT sources
+ */
+#define PRCMU_CLKSRC_CLK38M 0x00
+#define PRCMU_CLKSRC_ACLK 0x01
+#define PRCMU_CLKSRC_SYSCLK 0x02
+#define PRCMU_CLKSRC_LCDCLK 0x03
+#define PRCMU_CLKSRC_SDMMCCLK 0x04
+#define PRCMU_CLKSRC_TVCLK 0x05
+#define PRCMU_CLKSRC_TIMCLK 0x06
+#define PRCMU_CLKSRC_CLK009 0x07
+/* These are only valid for CLKOUT1: */
+#define PRCMU_CLKSRC_SIAMMDSPCLK 0x40
+#define PRCMU_CLKSRC_I2CCLK 0x41
+#define PRCMU_CLKSRC_MSP02CLK 0x42
+#define PRCMU_CLKSRC_ARMPLL_OBSCLK 0x43
+#define PRCMU_CLKSRC_HSIRXCLK 0x44
+#define PRCMU_CLKSRC_HSITXCLK 0x45
+#define PRCMU_CLKSRC_ARMCLKFIX 0x46
+#define PRCMU_CLKSRC_HDMICLK 0x47
+
+/*
+ * Definitions for controlling ESRAM0 in deep sleep.
+ */
+#define ESRAM0_DEEP_SLEEP_STATE_OFF 1
+#define ESRAM0_DEEP_SLEEP_STATE_RET 2
+
/* This portion previously known as <mach/prcmu-fw-defs_v1.h> */
/**
@@ -451,10 +486,173 @@ enum prcmu_power_status {
PRCMU_ARMPENDINGIT_ER = 0x93,
};
+/* PRCMU Wakeup defines */
+enum prcmu_wakeup_index {
+ PRCMU_WAKEUP_INDEX_RTC,
+ PRCMU_WAKEUP_INDEX_RTT0,
+ PRCMU_WAKEUP_INDEX_RTT1,
+ PRCMU_WAKEUP_INDEX_HSI0,
+ PRCMU_WAKEUP_INDEX_HSI1,
+ PRCMU_WAKEUP_INDEX_USB,
+ PRCMU_WAKEUP_INDEX_ABB,
+ PRCMU_WAKEUP_INDEX_ABB_FIFO,
+ PRCMU_WAKEUP_INDEX_ARM,
+ PRCMU_WAKEUP_INDEX_CD_IRQ,
+ NUM_PRCMU_WAKEUP_INDICES
+};
+
+#define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name))
+
+/**
+ * enum prcmu_wdog_id - PRCMU watchdog IDs
+ * @PRCMU_WDOG_ALL: use all timers
+ * @PRCMU_WDOG_CPU1: use first CPU timer only
+ * @PRCMU_WDOG_CPU2: use second CPU timer conly
+ */
+enum prcmu_wdog_id {
+ PRCMU_WDOG_ALL = 0x00,
+ PRCMU_WDOG_CPU1 = 0x01,
+ PRCMU_WDOG_CPU2 = 0x02,
+};
+
+/**
+ * enum ape_opp - APE OPP states definition
+ * @APE_OPP_INIT:
+ * @APE_NO_CHANGE: The APE operating point is unchanged
+ * @APE_100_OPP: The new APE operating point is ape100opp
+ * @APE_50_OPP: 50%
+ * @APE_50_PARTLY_25_OPP: 50%, except some clocks at 25%.
+ */
+enum ape_opp {
+ APE_OPP_INIT = 0x00,
+ APE_NO_CHANGE = 0x01,
+ APE_100_OPP = 0x02,
+ APE_50_OPP = 0x03,
+ APE_50_PARTLY_25_OPP = 0xFF,
+};
+
+/**
+ * enum arm_opp - ARM OPP states definition
+ * @ARM_OPP_INIT:
+ * @ARM_NO_CHANGE: The ARM operating point is unchanged
+ * @ARM_100_OPP: The new ARM operating point is arm100opp
+ * @ARM_50_OPP: The new ARM operating point is arm50opp
+ * @ARM_MAX_OPP: Operating point is "max" (more than 100)
+ * @ARM_MAX_FREQ100OPP: Set max opp if available, else 100
+ * @ARM_EXTCLK: The new ARM operating point is armExtClk
+ */
+enum arm_opp {
+ ARM_OPP_INIT = 0x00,
+ ARM_NO_CHANGE = 0x01,
+ ARM_100_OPP = 0x02,
+ ARM_50_OPP = 0x03,
+ ARM_MAX_OPP = 0x04,
+ ARM_MAX_FREQ100OPP = 0x05,
+ ARM_EXTCLK = 0x07
+};
+
+/**
+ * enum ddr_opp - DDR OPP states definition
+ * @DDR_100_OPP: The new DDR operating point is ddr100opp
+ * @DDR_50_OPP: The new DDR operating point is ddr50opp
+ * @DDR_25_OPP: The new DDR operating point is ddr25opp
+ */
+enum ddr_opp {
+ DDR_100_OPP = 0x00,
+ DDR_50_OPP = 0x01,
+ DDR_25_OPP = 0x02,
+};
+
+/**
+ * enum ddr_pwrst - DDR power states definition
+ * @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged
+ * @DDR_PWR_STATE_ON:
+ * @DDR_PWR_STATE_OFFLOWLAT:
+ * @DDR_PWR_STATE_OFFHIGHLAT:
+ */
+enum ddr_pwrst {
+ DDR_PWR_STATE_UNCHANGED = 0x00,
+ DDR_PWR_STATE_ON = 0x01,
+ DDR_PWR_STATE_OFFLOWLAT = 0x02,
+ DDR_PWR_STATE_OFFHIGHLAT = 0x03
+};
+
/*
* Definitions for autonomous power management configuration.
*/
+/* EPOD (power domain) IDs */
+
+/*
+ * DB8500 EPODs
+ * - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP
+ * - EPOD_ID_SVAPIPE: power domain for SVA pipe
+ * - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP
+ * - EPOD_ID_SIAPIPE: power domain for SIA pipe
+ * - EPOD_ID_SGA: power domain for SGA
+ * - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE
+ * - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2
+ * - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4
+ * - NUM_EPOD_ID: number of power domains
+ *
+ * TODO: These should be prefixed.
+ */
+#define EPOD_ID_SVAMMDSP 0
+#define EPOD_ID_SVAPIPE 1
+#define EPOD_ID_SIAMMDSP 2
+#define EPOD_ID_SIAPIPE 3
+#define EPOD_ID_SGA 4
+#define EPOD_ID_B2R2_MCDE 5
+#define EPOD_ID_ESRAM12 6
+#define EPOD_ID_ESRAM34 7
+#define NUM_EPOD_ID 8
+
+/*
+ * state definition for EPOD (power domain)
+ * - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged
+ * - EPOD_STATE_OFF: The EPOD is switched off
+ * - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in
+ * retention
+ * - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off
+ * - EPOD_STATE_ON: Same as above, but with clock enabled
+ */
+#define EPOD_STATE_NO_CHANGE 0x00
+#define EPOD_STATE_OFF 0x01
+#define EPOD_STATE_RAMRET 0x02
+#define EPOD_STATE_ON_CLK_OFF 0x03
+#define EPOD_STATE_ON 0x04
+
+#define PRCMU_FW_PROJECT_U8500 2
+#define PRCMU_FW_PROJECT_U8400 3
+#define PRCMU_FW_PROJECT_U9500 4 /* Customer specific */
+#define PRCMU_FW_PROJECT_U8500_MBB 5
+#define PRCMU_FW_PROJECT_U8500_C1 6
+#define PRCMU_FW_PROJECT_U8500_C2 7
+#define PRCMU_FW_PROJECT_U8500_C3 8
+#define PRCMU_FW_PROJECT_U8500_C4 9
+#define PRCMU_FW_PROJECT_U9500_MBL 10
+#define PRCMU_FW_PROJECT_U8500_SSG1 11 /* Samsung specific */
+#define PRCMU_FW_PROJECT_U8500_MBL2 12 /* Customer specific */
+#define PRCMU_FW_PROJECT_U8520 13
+#define PRCMU_FW_PROJECT_U8420 14
+#define PRCMU_FW_PROJECT_U8500_SSG2 15 /* Samsung specific */
+#define PRCMU_FW_PROJECT_U8420_SYSCLK 17
+#define PRCMU_FW_PROJECT_A9420 20
+/* [32..63] 9540 and derivatives */
+#define PRCMU_FW_PROJECT_U9540 32
+/* [64..95] 8540 and derivatives */
+#define PRCMU_FW_PROJECT_L8540 64
+/* [96..126] 8580 and derivatives */
+#define PRCMU_FW_PROJECT_L8580 96
+
+#define PRCMU_FW_PROJECT_NAME_LEN 20
+
+/* PRCMU QoS APE OPP class */
+#define PRCMU_QOS_APE_OPP 1
+#define PRCMU_QOS_DDR_OPP 2
+#define PRCMU_QOS_ARM_OPP 3
+#define PRCMU_QOS_DEFAULT_VALUE -1
+
#define PRCMU_AUTO_PM_OFF 0
#define PRCMU_AUTO_PM_ON 1
@@ -469,6 +667,14 @@ enum prcmu_auto_pm_policy {
PRCMU_AUTO_PM_POLICY_DSP_CLK_OFF_HWP_CLK_OFF,
};
+struct prcmu_fw_version {
+ u32 project; /* Notice, project shifted with 8 on ux540 */
+ u8 api_version;
+ u8 func_version;
+ u8 errata;
+ char project_name[PRCMU_FW_PROJECT_NAME_LEN];
+};
+
/**
* struct prcmu_auto_pm_config - Autonomous power management configuration.
* @sia_auto_pm_enable: SIA autonomous pm enable. (PRCMU_AUTO_PM_{OFF,ON})
@@ -501,6 +707,9 @@ void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
bool prcmu_is_auto_pm_enabled(void);
int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
+unsigned long prcmu_clock_rate(u8 clock);
+long prcmu_round_clock_rate(u8 clock, unsigned long rate);
+int prcmu_set_clock_rate(u8 clock, unsigned long rate);
int prcmu_set_clock_divider(u8 clock, u8 divider);
int db8500_prcmu_config_hotdog(u8 threshold);
int db8500_prcmu_config_hotmon(u8 low, u8 high);
@@ -508,6 +717,8 @@ int db8500_prcmu_start_temp_sense(u16 cycles32k);
int db8500_prcmu_stop_temp_sense(void);
int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
+int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value,
+ u8 *mask, u8 size);
int prcmu_ac_wake_req(void);
void prcmu_ac_sleep_req(void);
@@ -610,6 +821,21 @@ static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
return 0;
}
+static inline unsigned long prcmu_clock_rate(u8 clock)
+{
+ return 0;
+}
+
+static inline long prcmu_round_clock_rate(u8 clock, unsigned long rate)
+{
+ return 0;
+}
+
+static inline int prcmu_set_clock_rate(u8 clock, unsigned long rate)
+{
+ return 0;
+}
+
static inline int prcmu_set_clock_divider(u8 clock, u8 divider)
{
return 0;
@@ -637,12 +863,18 @@ static inline int db8500_prcmu_stop_temp_sense(void)
static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
{
- return -ENOSYS;
+ return -EINVAL;
}
static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
{
- return -ENOSYS;
+ return -EINVAL;
+}
+
+static inline int prcmu_abb_write_masked(u8 slave, u8 reg,
+ u8 *value, u8 *mask, u8 size)
+{
+ return -EINVAL;
}
static inline int prcmu_ac_wake_req(void)
@@ -745,4 +977,20 @@ static inline void db8500_prcmu_write_masked(unsigned int reg, u32 mask,
#endif /* !CONFIG_MFD_DB8500_PRCMU */
+static inline int prcmu_qos_add_requirement(int prcmu_qos_class,
+ char *name, s32 value)
+{
+ return 0;
+}
+
+static inline int prcmu_qos_update_requirement(int prcmu_qos_class,
+ char *name, s32 new_value)
+{
+ return 0;
+}
+
+static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name)
+{
+}
+
#endif /* __MFD_DB8500_PRCMU_H */
diff --git a/include/linux/mfd/dbx500-prcmu.h b/include/linux/mfd/dbx500-prcmu.h
deleted file mode 100644
index 828362b7860c..000000000000
--- a/include/linux/mfd/dbx500-prcmu.h
+++ /dev/null
@@ -1,575 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) ST Ericsson SA 2011
- *
- * STE Ux500 PRCMU API
- */
-#ifndef __MACH_PRCMU_H
-#define __MACH_PRCMU_H
-
-#include <linux/interrupt.h>
-#include <linux/notifier.h>
-#include <linux/err.h>
-
-#include <dt-bindings/mfd/dbx500-prcmu.h> /* For clock identifiers */
-
-/* Offset for the firmware version within the TCPM */
-#define DB8500_PRCMU_FW_VERSION_OFFSET 0xA4
-#define DBX540_PRCMU_FW_VERSION_OFFSET 0xA8
-
-/* PRCMU Wakeup defines */
-enum prcmu_wakeup_index {
- PRCMU_WAKEUP_INDEX_RTC,
- PRCMU_WAKEUP_INDEX_RTT0,
- PRCMU_WAKEUP_INDEX_RTT1,
- PRCMU_WAKEUP_INDEX_HSI0,
- PRCMU_WAKEUP_INDEX_HSI1,
- PRCMU_WAKEUP_INDEX_USB,
- PRCMU_WAKEUP_INDEX_ABB,
- PRCMU_WAKEUP_INDEX_ABB_FIFO,
- PRCMU_WAKEUP_INDEX_ARM,
- PRCMU_WAKEUP_INDEX_CD_IRQ,
- NUM_PRCMU_WAKEUP_INDICES
-};
-#define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name))
-
-/* EPOD (power domain) IDs */
-
-/*
- * DB8500 EPODs
- * - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP
- * - EPOD_ID_SVAPIPE: power domain for SVA pipe
- * - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP
- * - EPOD_ID_SIAPIPE: power domain for SIA pipe
- * - EPOD_ID_SGA: power domain for SGA
- * - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE
- * - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2
- * - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4
- * - NUM_EPOD_ID: number of power domains
- *
- * TODO: These should be prefixed.
- */
-#define EPOD_ID_SVAMMDSP 0
-#define EPOD_ID_SVAPIPE 1
-#define EPOD_ID_SIAMMDSP 2
-#define EPOD_ID_SIAPIPE 3
-#define EPOD_ID_SGA 4
-#define EPOD_ID_B2R2_MCDE 5
-#define EPOD_ID_ESRAM12 6
-#define EPOD_ID_ESRAM34 7
-#define NUM_EPOD_ID 8
-
-/*
- * state definition for EPOD (power domain)
- * - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged
- * - EPOD_STATE_OFF: The EPOD is switched off
- * - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in
- * retention
- * - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off
- * - EPOD_STATE_ON: Same as above, but with clock enabled
- */
-#define EPOD_STATE_NO_CHANGE 0x00
-#define EPOD_STATE_OFF 0x01
-#define EPOD_STATE_RAMRET 0x02
-#define EPOD_STATE_ON_CLK_OFF 0x03
-#define EPOD_STATE_ON 0x04
-
-/*
- * CLKOUT sources
- */
-#define PRCMU_CLKSRC_CLK38M 0x00
-#define PRCMU_CLKSRC_ACLK 0x01
-#define PRCMU_CLKSRC_SYSCLK 0x02
-#define PRCMU_CLKSRC_LCDCLK 0x03
-#define PRCMU_CLKSRC_SDMMCCLK 0x04
-#define PRCMU_CLKSRC_TVCLK 0x05
-#define PRCMU_CLKSRC_TIMCLK 0x06
-#define PRCMU_CLKSRC_CLK009 0x07
-/* These are only valid for CLKOUT1: */
-#define PRCMU_CLKSRC_SIAMMDSPCLK 0x40
-#define PRCMU_CLKSRC_I2CCLK 0x41
-#define PRCMU_CLKSRC_MSP02CLK 0x42
-#define PRCMU_CLKSRC_ARMPLL_OBSCLK 0x43
-#define PRCMU_CLKSRC_HSIRXCLK 0x44
-#define PRCMU_CLKSRC_HSITXCLK 0x45
-#define PRCMU_CLKSRC_ARMCLKFIX 0x46
-#define PRCMU_CLKSRC_HDMICLK 0x47
-
-/**
- * enum prcmu_wdog_id - PRCMU watchdog IDs
- * @PRCMU_WDOG_ALL: use all timers
- * @PRCMU_WDOG_CPU1: use first CPU timer only
- * @PRCMU_WDOG_CPU2: use second CPU timer conly
- */
-enum prcmu_wdog_id {
- PRCMU_WDOG_ALL = 0x00,
- PRCMU_WDOG_CPU1 = 0x01,
- PRCMU_WDOG_CPU2 = 0x02,
-};
-
-/**
- * enum ape_opp - APE OPP states definition
- * @APE_OPP_INIT:
- * @APE_NO_CHANGE: The APE operating point is unchanged
- * @APE_100_OPP: The new APE operating point is ape100opp
- * @APE_50_OPP: 50%
- * @APE_50_PARTLY_25_OPP: 50%, except some clocks at 25%.
- */
-enum ape_opp {
- APE_OPP_INIT = 0x00,
- APE_NO_CHANGE = 0x01,
- APE_100_OPP = 0x02,
- APE_50_OPP = 0x03,
- APE_50_PARTLY_25_OPP = 0xFF,
-};
-
-/**
- * enum arm_opp - ARM OPP states definition
- * @ARM_OPP_INIT:
- * @ARM_NO_CHANGE: The ARM operating point is unchanged
- * @ARM_100_OPP: The new ARM operating point is arm100opp
- * @ARM_50_OPP: The new ARM operating point is arm50opp
- * @ARM_MAX_OPP: Operating point is "max" (more than 100)
- * @ARM_MAX_FREQ100OPP: Set max opp if available, else 100
- * @ARM_EXTCLK: The new ARM operating point is armExtClk
- */
-enum arm_opp {
- ARM_OPP_INIT = 0x00,
- ARM_NO_CHANGE = 0x01,
- ARM_100_OPP = 0x02,
- ARM_50_OPP = 0x03,
- ARM_MAX_OPP = 0x04,
- ARM_MAX_FREQ100OPP = 0x05,
- ARM_EXTCLK = 0x07
-};
-
-/**
- * enum ddr_opp - DDR OPP states definition
- * @DDR_100_OPP: The new DDR operating point is ddr100opp
- * @DDR_50_OPP: The new DDR operating point is ddr50opp
- * @DDR_25_OPP: The new DDR operating point is ddr25opp
- */
-enum ddr_opp {
- DDR_100_OPP = 0x00,
- DDR_50_OPP = 0x01,
- DDR_25_OPP = 0x02,
-};
-
-/*
- * Definitions for controlling ESRAM0 in deep sleep.
- */
-#define ESRAM0_DEEP_SLEEP_STATE_OFF 1
-#define ESRAM0_DEEP_SLEEP_STATE_RET 2
-
-/**
- * enum ddr_pwrst - DDR power states definition
- * @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged
- * @DDR_PWR_STATE_ON:
- * @DDR_PWR_STATE_OFFLOWLAT:
- * @DDR_PWR_STATE_OFFHIGHLAT:
- */
-enum ddr_pwrst {
- DDR_PWR_STATE_UNCHANGED = 0x00,
- DDR_PWR_STATE_ON = 0x01,
- DDR_PWR_STATE_OFFLOWLAT = 0x02,
- DDR_PWR_STATE_OFFHIGHLAT = 0x03
-};
-
-#define DB8500_PRCMU_LEGACY_OFFSET 0xDD4
-
-#define PRCMU_FW_PROJECT_U8500 2
-#define PRCMU_FW_PROJECT_U8400 3
-#define PRCMU_FW_PROJECT_U9500 4 /* Customer specific */
-#define PRCMU_FW_PROJECT_U8500_MBB 5
-#define PRCMU_FW_PROJECT_U8500_C1 6
-#define PRCMU_FW_PROJECT_U8500_C2 7
-#define PRCMU_FW_PROJECT_U8500_C3 8
-#define PRCMU_FW_PROJECT_U8500_C4 9
-#define PRCMU_FW_PROJECT_U9500_MBL 10
-#define PRCMU_FW_PROJECT_U8500_SSG1 11 /* Samsung specific */
-#define PRCMU_FW_PROJECT_U8500_MBL2 12 /* Customer specific */
-#define PRCMU_FW_PROJECT_U8520 13
-#define PRCMU_FW_PROJECT_U8420 14
-#define PRCMU_FW_PROJECT_U8500_SSG2 15 /* Samsung specific */
-#define PRCMU_FW_PROJECT_U8420_SYSCLK 17
-#define PRCMU_FW_PROJECT_A9420 20
-/* [32..63] 9540 and derivatives */
-#define PRCMU_FW_PROJECT_U9540 32
-/* [64..95] 8540 and derivatives */
-#define PRCMU_FW_PROJECT_L8540 64
-/* [96..126] 8580 and derivatives */
-#define PRCMU_FW_PROJECT_L8580 96
-
-#define PRCMU_FW_PROJECT_NAME_LEN 20
-struct prcmu_fw_version {
- u32 project; /* Notice, project shifted with 8 on ux540 */
- u8 api_version;
- u8 func_version;
- u8 errata;
- char project_name[PRCMU_FW_PROJECT_NAME_LEN];
-};
-
-#include <linux/mfd/db8500-prcmu.h>
-
-#if defined(CONFIG_UX500_SOC_DB8500)
-
-static inline void __init prcmu_early_init(void)
-{
- db8500_prcmu_early_init();
-}
-
-static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
- bool keep_ap_pll)
-{
- return db8500_prcmu_set_power_state(state, keep_ulp_clk,
- keep_ap_pll);
-}
-
-static inline u8 prcmu_get_power_state_result(void)
-{
- return db8500_prcmu_get_power_state_result();
-}
-
-static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
-{
- return db8500_prcmu_set_epod(epod_id, epod_state);
-}
-
-static inline void prcmu_enable_wakeups(u32 wakeups)
-{
- db8500_prcmu_enable_wakeups(wakeups);
-}
-
-static inline void prcmu_disable_wakeups(void)
-{
- prcmu_enable_wakeups(0);
-}
-
-static inline void prcmu_config_abb_event_readout(u32 abb_events)
-{
- db8500_prcmu_config_abb_event_readout(abb_events);
-}
-
-static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
-{
- db8500_prcmu_get_abb_event_buffer(buf);
-}
-
-int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
-int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
-int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size);
-
-int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
-
-static inline int prcmu_request_clock(u8 clock, bool enable)
-{
- return db8500_prcmu_request_clock(clock, enable);
-}
-
-unsigned long prcmu_clock_rate(u8 clock);
-long prcmu_round_clock_rate(u8 clock, unsigned long rate);
-int prcmu_set_clock_rate(u8 clock, unsigned long rate);
-
-static inline int prcmu_get_ddr_opp(void)
-{
- return db8500_prcmu_get_ddr_opp();
-}
-
-static inline int prcmu_set_arm_opp(u8 opp)
-{
- return db8500_prcmu_set_arm_opp(opp);
-}
-
-static inline int prcmu_get_arm_opp(void)
-{
- return db8500_prcmu_get_arm_opp();
-}
-
-static inline int prcmu_set_ape_opp(u8 opp)
-{
- return db8500_prcmu_set_ape_opp(opp);
-}
-
-static inline int prcmu_get_ape_opp(void)
-{
- return db8500_prcmu_get_ape_opp();
-}
-
-static inline int prcmu_request_ape_opp_100_voltage(bool enable)
-{
- return db8500_prcmu_request_ape_opp_100_voltage(enable);
-}
-
-static inline void prcmu_system_reset(u16 reset_code)
-{
- db8500_prcmu_system_reset(reset_code);
-}
-
-static inline u16 prcmu_get_reset_code(void)
-{
- return db8500_prcmu_get_reset_code();
-}
-
-int prcmu_ac_wake_req(void);
-void prcmu_ac_sleep_req(void);
-static inline void prcmu_modem_reset(void)
-{
- db8500_prcmu_modem_reset();
-}
-
-static inline bool prcmu_is_ac_wake_requested(void)
-{
- return db8500_prcmu_is_ac_wake_requested();
-}
-
-static inline int prcmu_config_esram0_deep_sleep(u8 state)
-{
- return db8500_prcmu_config_esram0_deep_sleep(state);
-}
-
-static inline int prcmu_config_hotdog(u8 threshold)
-{
- return db8500_prcmu_config_hotdog(threshold);
-}
-
-static inline int prcmu_config_hotmon(u8 low, u8 high)
-{
- return db8500_prcmu_config_hotmon(low, high);
-}
-
-static inline int prcmu_start_temp_sense(u16 cycles32k)
-{
- return db8500_prcmu_start_temp_sense(cycles32k);
-}
-
-static inline int prcmu_stop_temp_sense(void)
-{
- return db8500_prcmu_stop_temp_sense();
-}
-
-static inline u32 prcmu_read(unsigned int reg)
-{
- return db8500_prcmu_read(reg);
-}
-
-static inline void prcmu_write(unsigned int reg, u32 value)
-{
- db8500_prcmu_write(reg, value);
-}
-
-static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
-{
- db8500_prcmu_write_masked(reg, mask, value);
-}
-
-static inline int prcmu_enable_a9wdog(u8 id)
-{
- return db8500_prcmu_enable_a9wdog(id);
-}
-
-static inline int prcmu_disable_a9wdog(u8 id)
-{
- return db8500_prcmu_disable_a9wdog(id);
-}
-
-static inline int prcmu_kick_a9wdog(u8 id)
-{
- return db8500_prcmu_kick_a9wdog(id);
-}
-
-static inline int prcmu_load_a9wdog(u8 id, u32 timeout)
-{
- return db8500_prcmu_load_a9wdog(id, timeout);
-}
-
-static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
-{
- return db8500_prcmu_config_a9wdog(num, sleep_auto_off);
-}
-#else
-
-static inline void prcmu_early_init(void) {}
-
-static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
- bool keep_ap_pll)
-{
- return 0;
-}
-
-static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
-{
- return 0;
-}
-
-static inline void prcmu_enable_wakeups(u32 wakeups) {}
-
-static inline void prcmu_disable_wakeups(void) {}
-
-static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
-{
- return -ENOSYS;
-}
-
-static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
-{
- return -ENOSYS;
-}
-
-static inline int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask,
- u8 size)
-{
- return -ENOSYS;
-}
-
-static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
-{
- return 0;
-}
-
-static inline int prcmu_request_clock(u8 clock, bool enable)
-{
- return 0;
-}
-
-static inline long prcmu_round_clock_rate(u8 clock, unsigned long rate)
-{
- return 0;
-}
-
-static inline int prcmu_set_clock_rate(u8 clock, unsigned long rate)
-{
- return 0;
-}
-
-static inline unsigned long prcmu_clock_rate(u8 clock)
-{
- return 0;
-}
-
-static inline int prcmu_set_ape_opp(u8 opp)
-{
- return 0;
-}
-
-static inline int prcmu_get_ape_opp(void)
-{
- return APE_100_OPP;
-}
-
-static inline int prcmu_request_ape_opp_100_voltage(bool enable)
-{
- return 0;
-}
-
-static inline int prcmu_set_arm_opp(u8 opp)
-{
- return 0;
-}
-
-static inline int prcmu_get_arm_opp(void)
-{
- return ARM_100_OPP;
-}
-
-static inline int prcmu_get_ddr_opp(void)
-{
- return DDR_100_OPP;
-}
-
-static inline void prcmu_system_reset(u16 reset_code) {}
-
-static inline u16 prcmu_get_reset_code(void)
-{
- return 0;
-}
-
-static inline int prcmu_ac_wake_req(void)
-{
- return 0;
-}
-
-static inline void prcmu_ac_sleep_req(void) {}
-
-static inline void prcmu_modem_reset(void) {}
-
-static inline bool prcmu_is_ac_wake_requested(void)
-{
- return false;
-}
-
-static inline int prcmu_config_esram0_deep_sleep(u8 state)
-{
- return 0;
-}
-
-static inline void prcmu_config_abb_event_readout(u32 abb_events) {}
-
-static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
-{
- *buf = NULL;
-}
-
-static inline int prcmu_config_hotdog(u8 threshold)
-{
- return 0;
-}
-
-static inline int prcmu_config_hotmon(u8 low, u8 high)
-{
- return 0;
-}
-
-static inline int prcmu_start_temp_sense(u16 cycles32k)
-{
- return 0;
-}
-
-static inline int prcmu_stop_temp_sense(void)
-{
- return 0;
-}
-
-static inline u32 prcmu_read(unsigned int reg)
-{
- return 0;
-}
-
-static inline void prcmu_write(unsigned int reg, u32 value) {}
-
-static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) {}
-
-#endif
-
-static inline void prcmu_set(unsigned int reg, u32 bits)
-{
- prcmu_write_masked(reg, bits, bits);
-}
-
-static inline void prcmu_clear(unsigned int reg, u32 bits)
-{
- prcmu_write_masked(reg, bits, 0);
-}
-
-/* PRCMU QoS APE OPP class */
-#define PRCMU_QOS_APE_OPP 1
-#define PRCMU_QOS_DDR_OPP 2
-#define PRCMU_QOS_ARM_OPP 3
-#define PRCMU_QOS_DEFAULT_VALUE -1
-
-static inline int prcmu_qos_add_requirement(int prcmu_qos_class,
- char *name, s32 value)
-{
- return 0;
-}
-
-static inline int prcmu_qos_update_requirement(int prcmu_qos_class,
- char *name, s32 new_value)
-{
- return 0;
-}
-
-static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name)
-{
-}
-
-#endif /* __MACH_PRCMU_H */
--git a/sound/soc/ux500/ux500_msp_dai.c b/sound/soc/ux500/ux500_msp_dai.c
index 7798957c6504..499e826d7120 100644
--- a/sound/soc/ux500/ux500_msp_dai.c
+++ b/sound/soc/ux500/ux500_msp_dai.c
@@ -14,7 +14,7 @@
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/regulator/consumer.h>
-#include <linux/mfd/dbx500-prcmu.h>
+#include <linux/mfd/db8500-prcmu.h>
#include <sound/soc.h>
#include <sound/soc-dai.h>
---
base-commit: 8cd9520d35a6c38db6567e97dd93b1f11f185dc6
change-id: 20260619-mfd-prcmu-merge-headers-bc84905195b4
Best regards,
--
Linus Walleij <linusw@kernel.org>
^ permalink raw reply related
* [PATCH v1] irqchip/gic-v3-its: Fix OF node reference leak
From: Yuho Choi @ 2026-06-19 18:58 UTC (permalink / raw)
To: Marc Zyngier, Thomas Gleixner; +Cc: linux-arm-kernel, linux-kernel, Yuho Choi
of_get_cpu_node() returns a referenced device node. In
its_cpu_init_collection(), the node is only used to get the CPU NUMA
node for the Cavium 23144 workaround, but the reference is never
dropped.
Store the NUMA node locally and call of_node_put() before either
continuing with collection setup or returning early for a NUMA mismatch.
Fixes: 920181ce8469 ("irqchip/gic-v3-its: Add ability to resend MAPC on resume")
Signed-off-by: Yuho Choi <dbgh9129@gmail.com>
---
drivers/irqchip/irq-gic-v3-its.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index b57d81ad33a0..f82035eb77e5 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -3291,10 +3291,14 @@ static void its_cpu_init_collection(struct its_node *its)
/* avoid cross node collections and its mapping */
if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) {
struct device_node *cpu_node;
+ int cpu_nid;
cpu_node = of_get_cpu_node(cpu, NULL);
+ cpu_nid = of_node_to_nid(cpu_node);
+ of_node_put(cpu_node);
+
if (its->numa_node != NUMA_NO_NODE &&
- its->numa_node != of_node_to_nid(cpu_node))
+ its->numa_node != cpu_nid)
return;
}
--
2.43.0
^ permalink raw reply related
* ❌ FAIL: Test report for for-kernelci (7.1.0-rc7, upstream-arm-next, 92e3f6ef)
From: cki-project @ 2026-06-19 19:52 UTC (permalink / raw)
To: will, catalin.marinas, linux-arm-kernel, fs-test
Hi, we tested your kernel and here are the results:
Overall result: FAILED
Merge: OK
Compile: OK
Test: FAILED
Kernel information:
Commit message: Merge branch 'for-next/core' into for-kernelci
You can find all the details about the test run at
https://datawarehouse.cki-project.org/kcidb/checkouts/redhat:2615019607
One or more kernel tests failed:
Unrecognized or new issues:
xfstests - btrfs
aarch64
Logs: https://datawarehouse.cki-project.org/kcidb/tests/redhat:2615019607_aarch64_kernel_kcidb_tool_21495614_9
Non-passing ran subtests:
❌ FAIL generic/301
We also see the following known issues which are not related to your changes:
Issue: [upstream] Hardware - Firmware test suite - auto-waive failures
URL: https://gitlab.com/cki-project/infrastructure/-/issues/779
Affected tests:
Hardware - Firmware test suite [aarch64]
If you find a failure unrelated to your changes, please ask the test maintainer to review it.
This will prevent the failures from being incorrectly reported in the future.
Please reply to this email if you have any questions about the tests that we
ran or if you have any suggestions on how to make future tests more effective.
,-. ,-.
( C ) ( K ) Continuous
`-',-.`-' Kernel
( I ) Integration
`-'
______________________________________________________________________________
^ permalink raw reply
* Re: [PATCH] iommu/io-pgtable-arm: Add support for contiguous hint bit
From: Daniel Mentz @ 2026-06-19 19:40 UTC (permalink / raw)
To: Vijayanand Jitta
Cc: Joerg Roedel (AMD), Will Deacon, Robin Murphy, linux-arm-msm,
iommu, linux-kernel, linux-arm-kernel, Prakash Gupta
In-Reply-To: <20260618-iommu_contig_hint-v1-1-4502a59e6388@oss.qualcomm.com>
On Thu, Jun 18, 2026 at 2:06 AM Vijayanand Jitta
<vijayanand.jitta@oss.qualcomm.com> wrote:
> Support is gated behind CONFIG_IOMMU_IO_PGTABLE_CONTIG_HINT, which
> provides a compile-time opt-out for hardware affected by SMMU errata
> related to the contiguous bit.
Have you considered making this a runtime option? Compare this with
arm_smmu_device_iidr_probe() where the smmuv3 driver disables certain
features based on the identified implementation and the errata
affecting that implementation.
> On the mapping side, __arm_lpae_map() detects when the requested size
> matches a contiguous range at the next level, sets the CONT bit on all
> PTEs in the group, then recurses with the base block size and an
> adjusted pgcount.
I would perform this check at the current level not the previous
level. See comments below.
>
> On the unmapping side, the CONT bit is cleared from all PTEs in the
> affected contiguous group before any individual entry is invalidated,
> following the Break-Before-Make requirement of the architecture.
My understanding is that for unmap operations, the following rule applies:
The IOVA range targeted by an unmap operation must exactly match the
IOVA range of a previous map operation. Partial unmap operations are
not allowed.
The iopgtable code previously had a function named
arm_lpae_split_blk_unmap() which allowed a block mapping to be split
up. However, that function has since been removed, which aligns with
prohibiting partial unmaps.
The other concern I have is a potential race condition: While one
thread clears the contiguous bit, another thread could try to unmap
the same descriptor.
Consider dropping support for partial unmap and just triggering a
WARN_ON() if you detect that a contiguous group is partially unmapped.
> +static inline int arm_lpae_cont_pmds(unsigned long size)
PMD is not a term that is used in this file. I advise against
introducing this term.
> +static u32 arm_lpae_find_num_cont(struct arm_lpae_io_pgtable *data, int lvl)
> +{
> + if (lvl == ARM_LPAE_MAX_LEVELS - 2)
> + return arm_lpae_cont_pmds(ARM_LPAE_BLOCK_SIZE(lvl, data));
> + else if (lvl == ARM_LPAE_MAX_LEVELS - 1)
> + return arm_lpae_cont_ptes(ARM_LPAE_BLOCK_SIZE(lvl, data));
Consider supporting the contiguous bit at lookup level 1.
> static int __arm_lpae_map(struct arm_lpae_io_pgtable *data, unsigned long iova,
> phys_addr_t paddr, size_t size, size_t pgcount,
> arm_lpae_iopte prot, int lvl, arm_lpae_iopte *ptep,
> @@ -463,6 +583,7 @@ static int __arm_lpae_map(struct arm_lpae_io_pgtable *data, unsigned long iova,
> size_t tblsz = ARM_LPAE_GRANULE(data);
> struct io_pgtable_cfg *cfg = &data->iop.cfg;
> int ret = 0, num_entries, max_entries, map_idx_start;
> + u32 num_cont = 1;
>
> /* Find our entry at the current level */
> map_idx_start = ARM_LPAE_LVL_IDX(iova, lvl, data);
> @@ -505,6 +626,24 @@ static int __arm_lpae_map(struct arm_lpae_io_pgtable *data, unsigned long iova,
> return -EEXIST;
> }
>
> + if (arm_lpae_pte_is_contiguous_range(data, size, lvl + 1, &num_cont)) {
I would recommend performing this check at the actual level not at the
previous lookup level i.e. not at the (lvl - 1) level. Imagine the
following situation: The granule size is 4KB, the initial lookup level
is 2, and size is 32MB. I'm wondering if in that case, it'll just keep
recursing until it hits (WARN_ON(lvl >= ARM_LPAE_MAX_LEVELS - 1)).
> +#ifdef CONFIG_IOMMU_IO_PGTABLE_CONTIG_HINT
> +static void arm_lpae_cont_clear(struct arm_lpae_io_pgtable *data,
> + unsigned long iova, int lvl,
> + arm_lpae_iopte *ptep, size_t num_entries)
> +{
> + struct io_pgtable_cfg *cfg = &data->iop.cfg;
> + u32 num_cont = arm_lpae_find_num_cont(data, lvl);
> + arm_lpae_iopte *cont_ptep;
> + arm_lpae_iopte *cont_ptep_start;
> + unsigned long cont_iova;
> + int offset, itr;
> +
> + cont_ptep = ptep - ARM_LPAE_LVL_IDX(iova, lvl, data);
> + cont_iova = round_down(iova,
> + ARM_LPAE_BLOCK_SIZE(lvl, data) * num_cont);
As a result of this round_down() function, you are accessing a
descriptor that describes an IOVA outside the range targeted by the
iommu_unmap call. Consequently, you might race against another thread
accessing the same descriptor.
> + cont_ptep += ARM_LPAE_LVL_IDX(cont_iova, lvl, data);
> + cont_ptep_start = cont_ptep;
> +
> + /*
> + * iova may not be aligned to the contiguous group boundary; include
> + * any leading entries so round_up() covers all overlapping groups.
> + */
> + offset = ARM_LPAE_LVL_IDX(iova, lvl, data) -
> + ARM_LPAE_LVL_IDX(cont_iova, lvl, data);
> + num_entries = round_up(offset + num_entries, num_cont);
> +
> + for (itr = 0; itr < num_entries; itr++) {
> + WRITE_ONCE(*cont_ptep, READ_ONCE(*cont_ptep) & ~ARM_LPAE_PTE_CONT);
This read-modify-write operation is not safe due to the potential race
described above.
> + cont_ptep++;
> + }
> +
> + if (!cfg->coherent_walk)
> + __arm_lpae_sync_pte(cont_ptep_start, num_entries, cfg);
> +}
> +#else
> +static void arm_lpae_cont_clear(struct arm_lpae_io_pgtable *data,
> + unsigned long iova, int lvl,
> + arm_lpae_iopte *ptep, size_t num_entries)
> +{
> +}
> +#endif
> +
> static size_t __arm_lpae_unmap(struct arm_lpae_io_pgtable *data,
> struct iommu_iotlb_gather *gather,
> unsigned long iova, size_t size, size_t pgcount,
> @@ -660,7 +841,7 @@ static size_t __arm_lpae_unmap(struct arm_lpae_io_pgtable *data,
> {
> arm_lpae_iopte pte;
> struct io_pgtable *iop = &data->iop;
> - int i = 0, num_entries, max_entries, unmap_idx_start;
> + int i = 0, num_cont = 1, num_entries, max_entries, unmap_idx_start;
>
> /* Something went horribly wrong and we ran out of page table */
> if (WARN_ON(lvl == ARM_LPAE_MAX_LEVELS))
> @@ -675,9 +856,15 @@ static size_t __arm_lpae_unmap(struct arm_lpae_io_pgtable *data,
> }
>
> /* If the size matches this level, we're in the right place */
> - if (size == ARM_LPAE_BLOCK_SIZE(lvl, data)) {
> + if (size == ARM_LPAE_BLOCK_SIZE(lvl, data) ||
> + (size == arm_lpae_find_num_cont(data, lvl) *
> + ARM_LPAE_BLOCK_SIZE(lvl, data))) {
> + size_t pte_size;
> +
> max_entries = arm_lpae_max_entries(unmap_idx_start, data);
> - num_entries = min_t(int, pgcount, max_entries);
> + num_cont = arm_lpae_check_num_cont(data, size, lvl);
> + num_entries = min_t(int, num_cont * pgcount, max_entries);
> + pte_size = size / num_cont;
>
> /* Find and handle non-leaf entries */
> for (i = 0; i < num_entries; i++) {
> @@ -687,11 +874,27 @@ static size_t __arm_lpae_unmap(struct arm_lpae_io_pgtable *data,
> break;
> }
>
> + /*
> + * Break-Before-Make: before invalidating any leaf
> + * entry, clear the CONT bit from every entry in the
> + * contiguous group(s) and flush the TLB, as required
> + * by the architecture. arm_lpae_cont_clear() covers
> + * the full [iova, iova + num_entries * pte_size) range
> + * via round_up(), so subsequent entries read back
> + * CONT=0 and skip this block.
> + */
> + if (pte & ARM_LPAE_PTE_CONT) {
> + arm_lpae_cont_clear(data, iova, lvl, ptep, num_entries);
> + io_pgtable_tlb_flush_walk(iop, iova,
> + num_entries * pte_size,
> + ARM_LPAE_GRANULE(data));
I believe this is inefficient. Consider the case where we unmap 2MB
worth of IOVA space mapped by 512 4KB page descriptors with the
contiguous bit set. If I'm not mistaken, you're running CMOs
(__arm_lpae_sync_pte) twice for every page descriptor. In addition,
io_pgtable_tlb_flush_walk() will submit an extra CMD_SYNC and wait for
it's completion.
Additionally, you perform rounding in arm_lpae_cont_clear(). However,
io_pgtable_tlb_flush_walk() is called on the original, potentially
unaligned range. Can this lead to under invalidation? Again, my
preference would be to drop support for partial unmaps which would
also remove the requirement for calling io_pgtable_tlb_flush_walk()
here.
> + }
> +
> if (!iopte_leaf(pte, lvl, iop->fmt)) {
> __arm_lpae_clear_pte(&ptep[i], &iop->cfg, 1);
>
> /* Also flush any partial walks */
> - io_pgtable_tlb_flush_walk(iop, iova + i * size, size,
> + io_pgtable_tlb_flush_walk(iop, iova + i * pte_size, pte_size,
> ARM_LPAE_GRANULE(data));
> __arm_lpae_free_pgtable(data, lvl + 1, iopte_deref(pte, data));
> }
^ permalink raw reply
* Re: [PATCH RFC 1/3] cpu/hotplug: Introduce CONFIG_PARALLEL_SMT_PRIMARY_FIRST
From: Thomas Gleixner @ 2026-06-19 19:27 UTC (permalink / raw)
To: Peter Zijlstra
Cc: Jinjie Ruan, catalin.marinas, will, tsbogend, pjw, palmer, aou,
alex, mingo, bp, dave.hansen, hpa, kees, nathan, linusw, ojeda,
david.kaplan, lukas.bulwahn, ryan.roberts, maz, timothy.hayes,
lpieralisi, thuth, oupton, yeoreum.yun, miko.lenczewski, broonie,
kevin.brodsky, james.clark, tabba, mrigendra.chaubey, arnd,
anshuman.khandual, x86, linux-kernel, linux-arm-kernel,
linux-mips, linux-riscv
In-Reply-To: <20260619094130.GU49951@noisy.programming.kicks-ass.net>
On Fri, Jun 19 2026 at 11:41, Peter Zijlstra wrote:
> On Thu, Jun 18, 2026 at 05:17:03PM +0200, Thomas Gleixner wrote:
>
>> Something simple like the uncompiled below should just work, no?
>>
>> ---
>> --- a/arch/Kconfig
>> +++ b/arch/Kconfig
>> @@ -102,6 +102,10 @@ config HOTPLUG_PARALLEL
>> bool
>> select HOTPLUG_SPLIT_STARTUP
>>
>> +config HOTPLUG_PARALLEL_SMT
>> + bool
>> + select HOTPLUG_PARALLEL
>
> depends on ARCH_SUPPORTS_SCHED_SMT ?
Probably. Did not think about that as this has to be anyway selected by
the architecture.
^ permalink raw reply
* Re: [PATCH 00/11] ARM: NXP: Drop NOMMU platform support
From: Arnd Bergmann @ 2026-06-19 19:17 UTC (permalink / raw)
To: Vladimir Zapolskiy, Frank Li, Sascha Hauer,
Pengutronix Kernel Team, Stefan Agner, Fabio Estevam, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Russell King, Abel Vesa,
Peng Fan, Michael Turquette, Stephen Boyd, Brian Masney,
Aisheng Dong, Jacky Bai, NXP S32 Linux Team, Linus Walleij,
Piotr Wojtaszczyk, Kees Cook, Gustavo A. R. Silva
Cc: linux-arm-kernel, imx, devicetree, linux-kernel, linux-clk,
open list:GPIO SUBSYSTEM, linux-hardening, Frank Li
In-Reply-To: <7d946861-c3cb-4512-9d5f-9f4cb9b7ee8a@kernel.org>
On Fri, Jun 19, 2026, at 18:07, Vladimir Zapolskiy wrote:
> On 6/19/26 18:40, Frank.Li@oss.nxp.com wrote:
>> Commercial users and hardware vendors migrated to Zephyr or other RTOS
>> solutions years ago, leaving the NOMMU platform support effectively
>> unused and unmaintained.
>>
>> Remove the obsolete support to reduce maintenance burden and simplify the
>> Freescale/nxp platform code.
>>
>> Some driver code still be kept and may clean up later since it is possible
>> reused by other SoC.
Thanks a lot for going through these already!
>> Signed-off-by: Frank Li <Frank.Li@nxp.com>
>
> This change is a bit too early to happen, I prefer to get it orchestrated
> by Arnd. So, as for today I NAK the change for its NXP LPC part.
I am planning to post a series of deprecation notices for platforms
that I would like to remove for one reason or another. Since it's only
one more merge before the next (S)LTS kernel, my idea was to post
the series once v7.2-rc1 is out, merge it into 7.3-LTS and remove
the deprecated code early next year once the LTS release is announced.
I have rebased uploaded my current draft to
https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git/log/?h=rfc-arm-deprecation-7.2
None of those are finalized of course, and we can do any part
of it earlier or later (or not at all) if there is a good reason.
If you to remove the vf610m4/imx7d-cm4/lpc43xx/lpc18xx portions
earlier, that is definitely fine with me. For imxrt1050, there a
slightly higher chance that this is still used, so I would
prefer to wait for the LTS kernel on that one.
>> Frank Li (11):
>> ARM: dts: vf610m4: Remove NOMMU platform support
>> ARM: dts: imxrt1050: Remove NOMMU platform support
>> ARM: imx: Remove NOMMU platform support
>> clk: imx: imxrt1050: Remove NOMMU platform support
>> pinctrl: freescale: IMXRT: Remove NOMMU platform support
>> ARM: imxrt_defconfig: Remove NOMMU platform support
>> ARM: dts: lpc: Remove NOMMU platform support
>> ARM: mach-lpc: Remove NOMMU platform support
>> ARM: configs: lpc*: Remove NOMMU platform support
>> clk: nxp: lpc: Remove NOMMU platform support
>> pinctrl: nxp: lpc: Remove NOMMU platform support
>
> NXP LPC32xx is ARMv5 and it has MMU, hence it's plainly out of scope of
> the proposed "dropping NOMMU platform support".
Agreed. There are a few more platforms with MMU that I would like
to drop because they were never converted to devicetree support,
but there is nothing wrong with lpc32xx.
Arnd
^ permalink raw reply
* Re: [PATCH v1] ARM: highbank: Fix OF node refcount leaks
From: 최유호 @ 2026-06-19 18:38 UTC (permalink / raw)
To: Andre Przywara, Russell King; +Cc: linux-arm-kernel, linux-kernel
In-Reply-To: <20260525031312.1341109-1-dbgh9129@gmail.com>
Hi,
Just a gentle ping on this patch.
I would appreciate any feedback when you have a chance to review this.
Thanks
^ permalink raw reply
* Re: [PATCH RFC v2 0/4] Add support for DisplayPort link training information report
From: Kory Maincent @ 2026-06-19 17:49 UTC (permalink / raw)
To: Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Jani Nikula, Rodrigo Vivi, Joonas Lahtinen,
Tvrtko Ursulin, Andrzej Hajda, Neil Armstrong, Robert Foss,
Laurent Pinchart, Jonas Karlman, Jernej Skrabec, Luca Ceresoli,
Chun-Kuang Hu, Philipp Zabel, Matthias Brugger,
AngeloGioacchino Del Regno, Dmitry Baryshkov, Daniel Stone
Cc: Thomas Petazzoni, Mark Yacoub, Sean Paul, Manasi Navare,
Drew Davenport, Louis Chauvet, dri-devel, linux-kernel, intel-gfx,
intel-xe, linux-mediatek, linux-arm-kernel
In-Reply-To: <20260619-feat_link_cap-v2-0-a3dec4c02ad9@bootlin.com>
Hello
On Fri, 19 Jun 2026 16:08:42 +0200
Kory Maincent <kory.maincent@bootlin.com> wrote:
> DisplayPort link training negotiates the physical-layer parameters needed
> for a reliable connection: lane count, link rate, and optionally Display
> Stream Compression (DSC). Currently, each driver exposes this state in
> its own way, often through driver-specific debugfs entries, with no
> standard interface for userspace diagnostic and monitoring tools.
>
> This series introduces generic, managed and unmanaged DisplayPort
> connector initialization helpers, for exposing DP link capabilities and
> state as standard sysfs entries, modeled after the existing HDMI helper
> drmm_connector_hdmi_init().
>
> The aim of such development is to guide users to select the most suitable
> DisplayPort connector for their needs. For example, if you have a USB-C
> hub with lesser capabilities than your computer’s native DisplayPort
> connector (such as HBR2 versus HBR3 support), the system could recommend
> connecting high-resolution displays directly to the computer’s port
> instead of through the hub to ensure optimal performance.
>
> These new drmm_connector_dp_init() and drm_connector_dp_init_with_ddc()
> helpers initialize a DP connector and expose link training capabilities
> and state to userspace via sysfs attributes under dp_link.
>
> Additional helpers are provided to manage link capabilities and parameters
> at runtime.
>
> Two drivers are updated as reference implementations: i915 (direct
> connector path) and MediaTek (via the bridge connector framework using a
> new DRM_BRIDGE_OP_DP flag).
>
> The changes updating the i915 driver to use DRM managed resources have been
> removed due to cleanup path issues. The core problem is that some functions
> do not consistently propagate errors through their call paths (whether this
> is intentional or not) making it difficult to properly handle cleanup of
> DRM objects (planes, encoders, connectors). A potential solution would be
> to implement something similar to devres_group for each DRM object type,
> but this represents a substantial undertaking that falls outside the scope
> of this patch series.
>
> The MST case in i915 driver is not supported yet.
I have seen and fixed the reviews from Sashiko.
I prefer to wait for human reviews about the core design before sending a v3, so
don't hesitate to look at the series. Mainly the first patch which tackle core
DRM changes.
Regards,
--
Köry Maincent, Bootlin
Embedded Linux and kernel engineering
https://bootlin.com
^ permalink raw reply
* [PATCH v3 2/2] regulator: Use named initializers for arrays of i2c_device_data
From: Uwe Kleine-König (The Capable Hub) @ 2026-06-19 17:17 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown
Cc: Michael Hennerich, Support Opensource, Laurent Pinchart,
Ivaylo Ivanov, Claudiu Beznea, Saravanan Sekar, Matthias Brugger,
AngeloGioacchino Del Regno, Woodrow Douglass, Jagan Teki,
Icenowy Zheng, linux-kernel, linux-arm-kernel, linux-mediatek
In-Reply-To: <cover.1781888370.git.u.kleine-koenig@baylibre.com>
While being less compact, using named initializers allows to more easily
see which members of the structs are assigned which value without having
to lookup the declaration of the struct. And it's also more robust
against changes to the struct definition.
The mentioned robustness is relevant for a planned change to struct
i2c_device_id that replaces .driver_data by an anonymous union.
While touching all these arrays, unify usage of whitespace and commas.
This patch doesn't modify the compiled arrays, only their representation
in source form benefits. The former was confirmed with x86 and arm64
builds.
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Uwe Kleine-König (The Capable Hub) <u.kleine-koenig@baylibre.com>
---
drivers/regulator/88pg86x.c | 4 ++--
drivers/regulator/ad5398.c | 4 ++--
drivers/regulator/da9121-regulator.c | 20 ++++++++++----------
drivers/regulator/da9210-regulator.c | 4 ++--
drivers/regulator/da9211-regulator.c | 18 +++++++++---------
drivers/regulator/fan53880.c | 4 ++--
drivers/regulator/isl9305.c | 4 ++--
drivers/regulator/lp3971.c | 2 +-
drivers/regulator/lp3972.c | 2 +-
drivers/regulator/lp872x.c | 4 ++--
drivers/regulator/lp8755.c | 4 ++--
drivers/regulator/ltc3589.c | 6 +++---
drivers/regulator/ltc3676.c | 2 +-
drivers/regulator/max1586.c | 2 +-
drivers/regulator/max20086-regulator.c | 8 ++++----
drivers/regulator/max20411-regulator.c | 2 +-
drivers/regulator/max77503-regulator.c | 2 +-
drivers/regulator/max77675-regulator.c | 2 +-
drivers/regulator/max77826-regulator.c | 2 +-
drivers/regulator/max77838-regulator.c | 2 +-
drivers/regulator/max77857-regulator.c | 8 ++++----
drivers/regulator/max8649.c | 2 +-
drivers/regulator/max8893.c | 2 +-
drivers/regulator/max8952.c | 2 +-
drivers/regulator/mcp16502.c | 2 +-
drivers/regulator/mp5416.c | 6 +++---
drivers/regulator/mp8859.c | 4 ++--
drivers/regulator/mp886x.c | 6 +++---
drivers/regulator/mpq7920.c | 4 ++--
drivers/regulator/mt6311-regulator.c | 4 ++--
drivers/regulator/pf530x-regulator.c | 6 +++---
drivers/regulator/pf8x00-regulator.c | 8 ++++----
drivers/regulator/pv88060-regulator.c | 4 ++--
drivers/regulator/pv88080-regulator.c | 8 ++++----
drivers/regulator/pv88090-regulator.c | 4 ++--
drivers/regulator/slg51000-regulator.c | 4 ++--
drivers/regulator/sy8106a-regulator.c | 2 +-
drivers/regulator/sy8824x.c | 8 ++++----
drivers/regulator/sy8827n.c | 4 ++--
drivers/regulator/tps6286x-regulator.c | 10 +++++-----
drivers/regulator/tps6287x-regulator.c | 10 +++++-----
41 files changed, 103 insertions(+), 103 deletions(-)
diff --git a/drivers/regulator/88pg86x.c b/drivers/regulator/88pg86x.c
index e6598e74ec94..8c25a1db412f 100644
--- a/drivers/regulator/88pg86x.c
+++ b/drivers/regulator/88pg86x.c
@@ -92,8 +92,8 @@ static const struct of_device_id __maybe_unused pg86x_dt_ids[] = {
MODULE_DEVICE_TABLE(of, pg86x_dt_ids);
static const struct i2c_device_id pg86x_i2c_id[] = {
- { "88pg867", },
- { "88pg868", },
+ { .name = "88pg867" },
+ { .name = "88pg868" },
{ }
};
MODULE_DEVICE_TABLE(i2c, pg86x_i2c_id);
diff --git a/drivers/regulator/ad5398.c b/drivers/regulator/ad5398.c
index eb2a666a45cb..0123ca8157a8 100644
--- a/drivers/regulator/ad5398.c
+++ b/drivers/regulator/ad5398.c
@@ -207,8 +207,8 @@ struct ad5398_current_data_format {
static const struct ad5398_current_data_format df_10_4_120 = {10, 4, 0, 120000};
static const struct i2c_device_id ad5398_id[] = {
- { "ad5398", (kernel_ulong_t)&df_10_4_120 },
- { "ad5821", (kernel_ulong_t)&df_10_4_120 },
+ { .name = "ad5398", .driver_data = (kernel_ulong_t)&df_10_4_120 },
+ { .name = "ad5821", .driver_data = (kernel_ulong_t)&df_10_4_120 },
{ }
};
MODULE_DEVICE_TABLE(i2c, ad5398_id);
diff --git a/drivers/regulator/da9121-regulator.c b/drivers/regulator/da9121-regulator.c
index 2b150bb4d471..8155f0974f7d 100644
--- a/drivers/regulator/da9121-regulator.c
+++ b/drivers/regulator/da9121-regulator.c
@@ -1195,16 +1195,16 @@ static void da9121_i2c_remove(struct i2c_client *i2c)
}
static const struct i2c_device_id da9121_i2c_id[] = {
- {"da9121", DA9121_TYPE_DA9121_DA9130},
- {"da9130", DA9121_TYPE_DA9121_DA9130},
- {"da9217", DA9121_TYPE_DA9217},
- {"da9122", DA9121_TYPE_DA9122_DA9131},
- {"da9131", DA9121_TYPE_DA9122_DA9131},
- {"da9220", DA9121_TYPE_DA9220_DA9132},
- {"da9132", DA9121_TYPE_DA9220_DA9132},
- {"da9141", DA9121_TYPE_DA9141},
- {"da9142", DA9121_TYPE_DA9142},
- {},
+ { .name = "da9121", .driver_data = DA9121_TYPE_DA9121_DA9130 },
+ { .name = "da9130", .driver_data = DA9121_TYPE_DA9121_DA9130 },
+ { .name = "da9217", .driver_data = DA9121_TYPE_DA9217 },
+ { .name = "da9122", .driver_data = DA9121_TYPE_DA9122_DA9131 },
+ { .name = "da9131", .driver_data = DA9121_TYPE_DA9122_DA9131 },
+ { .name = "da9220", .driver_data = DA9121_TYPE_DA9220_DA9132 },
+ { .name = "da9132", .driver_data = DA9121_TYPE_DA9220_DA9132 },
+ { .name = "da9141", .driver_data = DA9121_TYPE_DA9141 },
+ { .name = "da9142", .driver_data = DA9121_TYPE_DA9142 },
+ { }
};
MODULE_DEVICE_TABLE(i2c, da9121_i2c_id);
diff --git a/drivers/regulator/da9210-regulator.c b/drivers/regulator/da9210-regulator.c
index 39ade0dba40f..9154e32bd745 100644
--- a/drivers/regulator/da9210-regulator.c
+++ b/drivers/regulator/da9210-regulator.c
@@ -202,8 +202,8 @@ static int da9210_i2c_probe(struct i2c_client *i2c)
}
static const struct i2c_device_id da9210_i2c_id[] = {
- { "da9210" },
- {}
+ { .name = "da9210" },
+ { }
};
MODULE_DEVICE_TABLE(i2c, da9210_i2c_id);
diff --git a/drivers/regulator/da9211-regulator.c b/drivers/regulator/da9211-regulator.c
index d4f14d7ea8cf..9cf713755636 100644
--- a/drivers/regulator/da9211-regulator.c
+++ b/drivers/regulator/da9211-regulator.c
@@ -522,15 +522,15 @@ static int da9211_i2c_probe(struct i2c_client *i2c)
}
static const struct i2c_device_id da9211_i2c_id[] = {
- {"da9211", DA9211},
- {"da9212", DA9212},
- {"da9213", DA9213},
- {"da9223", DA9223},
- {"da9214", DA9214},
- {"da9224", DA9224},
- {"da9215", DA9215},
- {"da9225", DA9225},
- {},
+ { .name = "da9211", .driver_data = DA9211 },
+ { .name = "da9212", .driver_data = DA9212 },
+ { .name = "da9213", .driver_data = DA9213 },
+ { .name = "da9223", .driver_data = DA9223 },
+ { .name = "da9214", .driver_data = DA9214 },
+ { .name = "da9224", .driver_data = DA9224 },
+ { .name = "da9215", .driver_data = DA9215 },
+ { .name = "da9225", .driver_data = DA9225 },
+ { }
};
MODULE_DEVICE_TABLE(i2c, da9211_i2c_id);
diff --git a/drivers/regulator/fan53880.c b/drivers/regulator/fan53880.c
index 6cb5656845f9..79ba705ec324 100644
--- a/drivers/regulator/fan53880.c
+++ b/drivers/regulator/fan53880.c
@@ -164,8 +164,8 @@ static const struct of_device_id fan53880_dt_ids[] = {
MODULE_DEVICE_TABLE(of, fan53880_dt_ids);
static const struct i2c_device_id fan53880_i2c_id[] = {
- { "fan53880", },
- {}
+ { .name = "fan53880" },
+ { }
};
MODULE_DEVICE_TABLE(i2c, fan53880_i2c_id);
diff --git a/drivers/regulator/isl9305.c b/drivers/regulator/isl9305.c
index 5a234f25e6bb..ec6bd6bb9721 100644
--- a/drivers/regulator/isl9305.c
+++ b/drivers/regulator/isl9305.c
@@ -186,8 +186,8 @@ MODULE_DEVICE_TABLE(of, isl9305_dt_ids);
#endif
static const struct i2c_device_id isl9305_i2c_id[] = {
- { "isl9305", },
- { "isl9305h", },
+ { .name = "isl9305" },
+ { .name = "isl9305h" },
{ }
};
MODULE_DEVICE_TABLE(i2c, isl9305_i2c_id);
diff --git a/drivers/regulator/lp3971.c b/drivers/regulator/lp3971.c
index d4dab86fe385..6f830ae1bb61 100644
--- a/drivers/regulator/lp3971.c
+++ b/drivers/regulator/lp3971.c
@@ -439,7 +439,7 @@ static int lp3971_i2c_probe(struct i2c_client *i2c)
}
static const struct i2c_device_id lp3971_i2c_id[] = {
- { "lp3971" },
+ { .name = "lp3971" },
{ }
};
MODULE_DEVICE_TABLE(i2c, lp3971_i2c_id);
diff --git a/drivers/regulator/lp3972.c b/drivers/regulator/lp3972.c
index 1b918fb72134..235c640ba57f 100644
--- a/drivers/regulator/lp3972.c
+++ b/drivers/regulator/lp3972.c
@@ -537,7 +537,7 @@ static int lp3972_i2c_probe(struct i2c_client *i2c)
}
static const struct i2c_device_id lp3972_i2c_id[] = {
- { "lp3972" },
+ { .name = "lp3972" },
{ }
};
MODULE_DEVICE_TABLE(i2c, lp3972_i2c_id);
diff --git a/drivers/regulator/lp872x.c b/drivers/regulator/lp872x.c
index 942f37082cb1..5b2faddd8110 100644
--- a/drivers/regulator/lp872x.c
+++ b/drivers/regulator/lp872x.c
@@ -935,8 +935,8 @@ static const struct of_device_id lp872x_dt_ids[] __maybe_unused = {
MODULE_DEVICE_TABLE(of, lp872x_dt_ids);
static const struct i2c_device_id lp872x_ids[] = {
- {"lp8720", LP8720},
- {"lp8725", LP8725},
+ { .name = "lp8720", .driver_data = LP8720 },
+ { .name = "lp8725", .driver_data = LP8725 },
{ }
};
MODULE_DEVICE_TABLE(i2c, lp872x_ids);
diff --git a/drivers/regulator/lp8755.c b/drivers/regulator/lp8755.c
index 5509bee49bda..632320ba1800 100644
--- a/drivers/regulator/lp8755.c
+++ b/drivers/regulator/lp8755.c
@@ -430,8 +430,8 @@ static void lp8755_remove(struct i2c_client *client)
}
static const struct i2c_device_id lp8755_id[] = {
- { LP8755_NAME },
- {}
+ { .name = LP8755_NAME },
+ { }
};
MODULE_DEVICE_TABLE(i2c, lp8755_id);
diff --git a/drivers/regulator/ltc3589.c b/drivers/regulator/ltc3589.c
index 3f70c2225dba..8bae5d8aeaf4 100644
--- a/drivers/regulator/ltc3589.c
+++ b/drivers/regulator/ltc3589.c
@@ -445,9 +445,9 @@ static const struct ltc3589_info ltc3589_12_info = {
};
static const struct i2c_device_id ltc3589_i2c_id[] = {
- { "ltc3589", (kernel_ulong_t)<c3589_info },
- { "ltc3589-1", (kernel_ulong_t)<c3589_12_info },
- { "ltc3589-2", (kernel_ulong_t)<c3589_12_info },
+ { .name = "ltc3589", .driver_data = (kernel_ulong_t)<c3589_info },
+ { .name = "ltc3589-1", .driver_data = (kernel_ulong_t)<c3589_12_info },
+ { .name = "ltc3589-2", .driver_data = (kernel_ulong_t)<c3589_12_info },
{ }
};
MODULE_DEVICE_TABLE(i2c, ltc3589_i2c_id);
diff --git a/drivers/regulator/ltc3676.c b/drivers/regulator/ltc3676.c
index 73d511eb1c1d..597d20a200d7 100644
--- a/drivers/regulator/ltc3676.c
+++ b/drivers/regulator/ltc3676.c
@@ -357,7 +357,7 @@ static int ltc3676_regulator_probe(struct i2c_client *client)
}
static const struct i2c_device_id ltc3676_i2c_id[] = {
- { "ltc3676" },
+ { .name = "ltc3676" },
{ }
};
MODULE_DEVICE_TABLE(i2c, ltc3676_i2c_id);
diff --git a/drivers/regulator/max1586.c b/drivers/regulator/max1586.c
index 4242fbb7b147..e5cbc09c2d39 100644
--- a/drivers/regulator/max1586.c
+++ b/drivers/regulator/max1586.c
@@ -276,7 +276,7 @@ static int max1586_pmic_probe(struct i2c_client *client)
}
static const struct i2c_device_id max1586_id[] = {
- { "max1586" },
+ { .name = "max1586" },
{ }
};
MODULE_DEVICE_TABLE(i2c, max1586_id);
diff --git a/drivers/regulator/max20086-regulator.c b/drivers/regulator/max20086-regulator.c
index fcdd2d0317a5..92594b2915f3 100644
--- a/drivers/regulator/max20086-regulator.c
+++ b/drivers/regulator/max20086-regulator.c
@@ -301,10 +301,10 @@ static const struct max20086_chip_info max20089_chip_info = {
};
static const struct i2c_device_id max20086_i2c_id[] = {
- { "max20086", (kernel_ulong_t)&max20086_chip_info },
- { "max20087", (kernel_ulong_t)&max20087_chip_info },
- { "max20088", (kernel_ulong_t)&max20088_chip_info },
- { "max20089", (kernel_ulong_t)&max20089_chip_info },
+ { .name = "max20086", .driver_data = (kernel_ulong_t)&max20086_chip_info },
+ { .name = "max20087", .driver_data = (kernel_ulong_t)&max20087_chip_info },
+ { .name = "max20088", .driver_data = (kernel_ulong_t)&max20088_chip_info },
+ { .name = "max20089", .driver_data = (kernel_ulong_t)&max20089_chip_info },
{ /* Sentinel */ }
};
MODULE_DEVICE_TABLE(i2c, max20086_i2c_id);
diff --git a/drivers/regulator/max20411-regulator.c b/drivers/regulator/max20411-regulator.c
index 6c0ebb970e90..ac7a9aa014aa 100644
--- a/drivers/regulator/max20411-regulator.c
+++ b/drivers/regulator/max20411-regulator.c
@@ -145,7 +145,7 @@ static const struct of_device_id of_max20411_match_tbl[] = {
MODULE_DEVICE_TABLE(of, of_max20411_match_tbl);
static const struct i2c_device_id max20411_id[] = {
- { "max20411" },
+ { .name = "max20411" },
{ }
};
MODULE_DEVICE_TABLE(i2c, max20411_id);
diff --git a/drivers/regulator/max77503-regulator.c b/drivers/regulator/max77503-regulator.c
index c7c94e868fc1..1cae846f96d0 100644
--- a/drivers/regulator/max77503-regulator.c
+++ b/drivers/regulator/max77503-regulator.c
@@ -107,7 +107,7 @@ static const struct of_device_id of_max77503_match_tbl[] = {
MODULE_DEVICE_TABLE(of, of_max77503_match_tbl);
static const struct i2c_device_id max77503_regulator_id[] = {
- {"max77503"},
+ { .name = "max77503" },
{ }
};
diff --git a/drivers/regulator/max77675-regulator.c b/drivers/regulator/max77675-regulator.c
index 57350526afd7..ebea08ddf4b8 100644
--- a/drivers/regulator/max77675-regulator.c
+++ b/drivers/regulator/max77675-regulator.c
@@ -1029,7 +1029,7 @@ static int max77675_regulator_probe(struct i2c_client *client)
}
static const struct i2c_device_id max77675_i2c_id[] = {
- { "max77675" },
+ { .name = "max77675" },
{ }
};
MODULE_DEVICE_TABLE(i2c, max77675_i2c_id);
diff --git a/drivers/regulator/max77826-regulator.c b/drivers/regulator/max77826-regulator.c
index 310bc8ee7af8..8b60a9fcab44 100644
--- a/drivers/regulator/max77826-regulator.c
+++ b/drivers/regulator/max77826-regulator.c
@@ -278,7 +278,7 @@ static const struct of_device_id __maybe_unused max77826_of_match[] = {
MODULE_DEVICE_TABLE(of, max77826_of_match);
static const struct i2c_device_id max77826_id[] = {
- { "max77826-regulator" },
+ { .name = "max77826-regulator" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(i2c, max77826_id);
diff --git a/drivers/regulator/max77838-regulator.c b/drivers/regulator/max77838-regulator.c
index 9faddbfd25fd..765756fdcf6e 100644
--- a/drivers/regulator/max77838-regulator.c
+++ b/drivers/regulator/max77838-regulator.c
@@ -200,7 +200,7 @@ static const struct of_device_id __maybe_unused max77838_of_match[] = {
MODULE_DEVICE_TABLE(of, max77838_of_match);
static const struct i2c_device_id max77838_id[] = {
- { "max77838-regulator" },
+ { .name = "max77838-regulator" },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(i2c, max77838_id);
diff --git a/drivers/regulator/max77857-regulator.c b/drivers/regulator/max77857-regulator.c
index 1216cc3a6f72..f1410f845653 100644
--- a/drivers/regulator/max77857-regulator.c
+++ b/drivers/regulator/max77857-regulator.c
@@ -428,10 +428,10 @@ static int max77857_probe(struct i2c_client *client)
}
static const struct i2c_device_id max77857_id[] = {
- { "max77831", ID_MAX77831 },
- { "max77857", ID_MAX77857 },
- { "max77859", ID_MAX77859 },
- { "max77859a", ID_MAX77859A },
+ { .name = "max77831", .driver_data = ID_MAX77831 },
+ { .name = "max77857", .driver_data = ID_MAX77857 },
+ { .name = "max77859", .driver_data = ID_MAX77859 },
+ { .name = "max77859a", .driver_data = ID_MAX77859A },
{ }
};
MODULE_DEVICE_TABLE(i2c, max77857_id);
diff --git a/drivers/regulator/max8649.c b/drivers/regulator/max8649.c
index f57c588bcf28..2d17405242e7 100644
--- a/drivers/regulator/max8649.c
+++ b/drivers/regulator/max8649.c
@@ -240,7 +240,7 @@ static int max8649_regulator_probe(struct i2c_client *client)
}
static const struct i2c_device_id max8649_id[] = {
- { "max8649" },
+ { .name = "max8649" },
{ }
};
MODULE_DEVICE_TABLE(i2c, max8649_id);
diff --git a/drivers/regulator/max8893.c b/drivers/regulator/max8893.c
index 5a90633d8536..7a0e44a16d49 100644
--- a/drivers/regulator/max8893.c
+++ b/drivers/regulator/max8893.c
@@ -162,7 +162,7 @@ MODULE_DEVICE_TABLE(of, max8893_dt_match);
#endif
static const struct i2c_device_id max8893_ids[] = {
- { "max8893" },
+ { .name = "max8893" },
{ }
};
MODULE_DEVICE_TABLE(i2c, max8893_ids);
diff --git a/drivers/regulator/max8952.c b/drivers/regulator/max8952.c
index 1f94315bfb02..f8b91a5701f3 100644
--- a/drivers/regulator/max8952.c
+++ b/drivers/regulator/max8952.c
@@ -307,7 +307,7 @@ static int max8952_pmic_probe(struct i2c_client *client)
}
static const struct i2c_device_id max8952_ids[] = {
- { "max8952" },
+ { .name = "max8952" },
{ }
};
MODULE_DEVICE_TABLE(i2c, max8952_ids);
diff --git a/drivers/regulator/mcp16502.c b/drivers/regulator/mcp16502.c
index b34ae0bbba6f..89fd79d446f7 100644
--- a/drivers/regulator/mcp16502.c
+++ b/drivers/regulator/mcp16502.c
@@ -578,7 +578,7 @@ static const struct dev_pm_ops mcp16502_pm_ops = {
};
#endif
static const struct i2c_device_id mcp16502_i2c_id[] = {
- { "mcp16502" },
+ { .name = "mcp16502" },
{ }
};
MODULE_DEVICE_TABLE(i2c, mcp16502_i2c_id);
diff --git a/drivers/regulator/mp5416.c b/drivers/regulator/mp5416.c
index e6794190cb68..2948635b1b9f 100644
--- a/drivers/regulator/mp5416.c
+++ b/drivers/regulator/mp5416.c
@@ -228,9 +228,9 @@ static const struct of_device_id mp5416_of_match[] = {
MODULE_DEVICE_TABLE(of, mp5416_of_match);
static const struct i2c_device_id mp5416_id[] = {
- { "mp5416", (kernel_ulong_t)&mp5416_regulators_desc },
- { "mp5496", (kernel_ulong_t)&mp5496_regulators_desc },
- {}
+ { .name = "mp5416", .driver_data = (kernel_ulong_t)&mp5416_regulators_desc },
+ { .name = "mp5496", .driver_data = (kernel_ulong_t)&mp5496_regulators_desc },
+ { }
};
MODULE_DEVICE_TABLE(i2c, mp5416_id);
diff --git a/drivers/regulator/mp8859.c b/drivers/regulator/mp8859.c
index ab105ffd6a2e..9a708e826d93 100644
--- a/drivers/regulator/mp8859.c
+++ b/drivers/regulator/mp8859.c
@@ -386,8 +386,8 @@ static const struct of_device_id mp8859_dt_id[] __maybe_unused = {
MODULE_DEVICE_TABLE(of, mp8859_dt_id);
static const struct i2c_device_id mp8859_i2c_id[] = {
- { "mp8859", },
- { },
+ { .name = "mp8859" },
+ { }
};
MODULE_DEVICE_TABLE(i2c, mp8859_i2c_id);
diff --git a/drivers/regulator/mp886x.c b/drivers/regulator/mp886x.c
index 9ad16b04c913..e0b62bc02a1e 100644
--- a/drivers/regulator/mp886x.c
+++ b/drivers/regulator/mp886x.c
@@ -348,9 +348,9 @@ static const struct of_device_id mp886x_dt_ids[] = {
MODULE_DEVICE_TABLE(of, mp886x_dt_ids);
static const struct i2c_device_id mp886x_id[] = {
- { "mp8867", (kernel_ulong_t)&mp8867_ci },
- { "mp8869", (kernel_ulong_t)&mp8869_ci },
- { },
+ { .name = "mp8867", .driver_data = (kernel_ulong_t)&mp8867_ci },
+ { .name = "mp8869", .driver_data = (kernel_ulong_t)&mp8869_ci },
+ { }
};
MODULE_DEVICE_TABLE(i2c, mp886x_id);
diff --git a/drivers/regulator/mpq7920.c b/drivers/regulator/mpq7920.c
index a670e09891e7..0cbc17deb1d1 100644
--- a/drivers/regulator/mpq7920.c
+++ b/drivers/regulator/mpq7920.c
@@ -309,8 +309,8 @@ static const struct of_device_id mpq7920_of_match[] = {
MODULE_DEVICE_TABLE(of, mpq7920_of_match);
static const struct i2c_device_id mpq7920_id[] = {
- { "mpq7920", },
- { },
+ { .name = "mpq7920" },
+ { }
};
MODULE_DEVICE_TABLE(i2c, mpq7920_id);
diff --git a/drivers/regulator/mt6311-regulator.c b/drivers/regulator/mt6311-regulator.c
index 2ebc1c0b5e6f..1d457d1fdf23 100644
--- a/drivers/regulator/mt6311-regulator.c
+++ b/drivers/regulator/mt6311-regulator.c
@@ -133,8 +133,8 @@ static int mt6311_i2c_probe(struct i2c_client *i2c)
}
static const struct i2c_device_id mt6311_i2c_id[] = {
- { "mt6311" },
- {}
+ { .name = "mt6311" },
+ { }
};
MODULE_DEVICE_TABLE(i2c, mt6311_i2c_id);
diff --git a/drivers/regulator/pf530x-regulator.c b/drivers/regulator/pf530x-regulator.c
index ef3d5bb784cd..8ad1cbbd7a8c 100644
--- a/drivers/regulator/pf530x-regulator.c
+++ b/drivers/regulator/pf530x-regulator.c
@@ -353,9 +353,9 @@ static const struct of_device_id pf530x_dt_ids[] = {
MODULE_DEVICE_TABLE(of, pf530x_dt_ids);
static const struct i2c_device_id pf530x_i2c_id[] = {
- { "pf5300" },
- { "pf5301" },
- { "pf5302" },
+ { .name = "pf5300" },
+ { .name = "pf5301" },
+ { .name = "pf5302" },
{ }
};
MODULE_DEVICE_TABLE(i2c, pf530x_i2c_id);
diff --git a/drivers/regulator/pf8x00-regulator.c b/drivers/regulator/pf8x00-regulator.c
index ea3611de42b4..c938b4632ef1 100644
--- a/drivers/regulator/pf8x00-regulator.c
+++ b/drivers/regulator/pf8x00-regulator.c
@@ -596,10 +596,10 @@ static const struct of_device_id pf8x00_dt_ids[] = {
MODULE_DEVICE_TABLE(of, pf8x00_dt_ids);
static const struct i2c_device_id pf8x00_i2c_id[] = {
- { "pf8100" },
- { "pf8121a" },
- { "pf8200" },
- {}
+ { .name = "pf8100" },
+ { .name = "pf8121a" },
+ { .name = "pf8200" },
+ { }
};
MODULE_DEVICE_TABLE(i2c, pf8x00_i2c_id);
diff --git a/drivers/regulator/pv88060-regulator.c b/drivers/regulator/pv88060-regulator.c
index ae1c4b9daaa1..375d9e759c47 100644
--- a/drivers/regulator/pv88060-regulator.c
+++ b/drivers/regulator/pv88060-regulator.c
@@ -360,8 +360,8 @@ static int pv88060_i2c_probe(struct i2c_client *i2c)
}
static const struct i2c_device_id pv88060_i2c_id[] = {
- { "pv88060" },
- {}
+ { .name = "pv88060" },
+ { }
};
MODULE_DEVICE_TABLE(i2c, pv88060_i2c_id);
diff --git a/drivers/regulator/pv88080-regulator.c b/drivers/regulator/pv88080-regulator.c
index 9fe539a34786..3dc48d059791 100644
--- a/drivers/regulator/pv88080-regulator.c
+++ b/drivers/regulator/pv88080-regulator.c
@@ -523,10 +523,10 @@ static const struct of_device_id pv88080_dt_ids[] = {
MODULE_DEVICE_TABLE(of, pv88080_dt_ids);
static const struct i2c_device_id pv88080_i2c_id[] = {
- { "pv88080", (kernel_ulong_t)&pv88080_aa_regs },
- { "pv88080-aa", (kernel_ulong_t)&pv88080_aa_regs },
- { "pv88080-ba", (kernel_ulong_t)&pv88080_ba_regs },
- {}
+ { .name = "pv88080", .driver_data = (kernel_ulong_t)&pv88080_aa_regs },
+ { .name = "pv88080-aa", .driver_data = (kernel_ulong_t)&pv88080_aa_regs },
+ { .name = "pv88080-ba", .driver_data = (kernel_ulong_t)&pv88080_ba_regs },
+ { }
};
MODULE_DEVICE_TABLE(i2c, pv88080_i2c_id);
diff --git a/drivers/regulator/pv88090-regulator.c b/drivers/regulator/pv88090-regulator.c
index 3c48757bbbda..ca5eeb5dfe62 100644
--- a/drivers/regulator/pv88090-regulator.c
+++ b/drivers/regulator/pv88090-regulator.c
@@ -381,8 +381,8 @@ static int pv88090_i2c_probe(struct i2c_client *i2c)
}
static const struct i2c_device_id pv88090_i2c_id[] = {
- { "pv88090" },
- {}
+ { .name = "pv88090" },
+ { }
};
MODULE_DEVICE_TABLE(i2c, pv88090_i2c_id);
diff --git a/drivers/regulator/slg51000-regulator.c b/drivers/regulator/slg51000-regulator.c
index 3bbd4a29e6d3..d682764cdbf8 100644
--- a/drivers/regulator/slg51000-regulator.c
+++ b/drivers/regulator/slg51000-regulator.c
@@ -497,8 +497,8 @@ static int slg51000_i2c_probe(struct i2c_client *client)
}
static const struct i2c_device_id slg51000_i2c_id[] = {
- { "slg51000" },
- {}
+ { .name = "slg51000" },
+ { }
};
MODULE_DEVICE_TABLE(i2c, slg51000_i2c_id);
diff --git a/drivers/regulator/sy8106a-regulator.c b/drivers/regulator/sy8106a-regulator.c
index d79a4cc25a0d..b2b835c60262 100644
--- a/drivers/regulator/sy8106a-regulator.c
+++ b/drivers/regulator/sy8106a-regulator.c
@@ -130,7 +130,7 @@ static const struct of_device_id sy8106a_i2c_of_match[] = {
MODULE_DEVICE_TABLE(of, sy8106a_i2c_of_match);
static const struct i2c_device_id sy8106a_i2c_id[] = {
- { "sy8106a" },
+ { .name = "sy8106a" },
{ }
};
MODULE_DEVICE_TABLE(i2c, sy8106a_i2c_id);
diff --git a/drivers/regulator/sy8824x.c b/drivers/regulator/sy8824x.c
index 5bec84db25f1..3f07e7da90cb 100644
--- a/drivers/regulator/sy8824x.c
+++ b/drivers/regulator/sy8824x.c
@@ -213,10 +213,10 @@ static const struct of_device_id sy8824_dt_ids[] = {
MODULE_DEVICE_TABLE(of, sy8824_dt_ids);
static const struct i2c_device_id sy8824_id[] = {
- { "sy8824c", (kernel_ulong_t)&sy8824c_cfg },
- { "sy8824e", (kernel_ulong_t)&sy8824e_cfg },
- { "sy20276", (kernel_ulong_t)&sy20276_cfg },
- { "sy20278", (kernel_ulong_t)&sy20278_cfg },
+ { .name = "sy8824c", .driver_data = (kernel_ulong_t)&sy8824c_cfg },
+ { .name = "sy8824e", .driver_data = (kernel_ulong_t)&sy8824e_cfg },
+ { .name = "sy20276", .driver_data = (kernel_ulong_t)&sy20276_cfg },
+ { .name = "sy20278", .driver_data = (kernel_ulong_t)&sy20278_cfg },
{ }
};
MODULE_DEVICE_TABLE(i2c, sy8824_id);
diff --git a/drivers/regulator/sy8827n.c b/drivers/regulator/sy8827n.c
index 0b811514782f..a1cac8cc3d96 100644
--- a/drivers/regulator/sy8827n.c
+++ b/drivers/regulator/sy8827n.c
@@ -180,8 +180,8 @@ static const struct of_device_id sy8827n_dt_ids[] = {
MODULE_DEVICE_TABLE(of, sy8827n_dt_ids);
static const struct i2c_device_id sy8827n_id[] = {
- { "sy8827n", },
- { },
+ { .name = "sy8827n" },
+ { }
};
MODULE_DEVICE_TABLE(i2c, sy8827n_id);
diff --git a/drivers/regulator/tps6286x-regulator.c b/drivers/regulator/tps6286x-regulator.c
index e29aab06bf79..1ab53bee9f6e 100644
--- a/drivers/regulator/tps6286x-regulator.c
+++ b/drivers/regulator/tps6286x-regulator.c
@@ -145,11 +145,11 @@ static int tps6286x_i2c_probe(struct i2c_client *i2c)
}
static const struct i2c_device_id tps6286x_i2c_id[] = {
- { "tps62864" },
- { "tps62866" },
- { "tps62868" },
- { "tps62869" },
- {}
+ { .name = "tps62864" },
+ { .name = "tps62866" },
+ { .name = "tps62868" },
+ { .name = "tps62869" },
+ { }
};
MODULE_DEVICE_TABLE(i2c, tps6286x_i2c_id);
diff --git a/drivers/regulator/tps6287x-regulator.c b/drivers/regulator/tps6287x-regulator.c
index 7b7d3ae39206..c0bc4a6192c4 100644
--- a/drivers/regulator/tps6287x-regulator.c
+++ b/drivers/regulator/tps6287x-regulator.c
@@ -229,11 +229,11 @@ static const struct of_device_id tps6287x_dt_ids[] = {
MODULE_DEVICE_TABLE(of, tps6287x_dt_ids);
static const struct i2c_device_id tps6287x_i2c_id[] = {
- { "tps62870" },
- { "tps62871" },
- { "tps62872" },
- { "tps62873" },
- {}
+ { .name = "tps62870" },
+ { .name = "tps62871" },
+ { .name = "tps62872" },
+ { .name = "tps62873" },
+ { }
};
MODULE_DEVICE_TABLE(i2c, tps6287x_i2c_id);
--
2.47.3
^ permalink raw reply related
* [PATCH v3 0/2] regulator: Rework i2c_device_id initialisation
From: Uwe Kleine-König (The Capable Hub) @ 2026-06-19 17:17 UTC (permalink / raw)
To: Liam Girdwood, Mark Brown
Cc: Laurent Pinchart, Woodrow Douglass, linux-kernel,
Michael Hennerich, Support Opensource, Ivaylo Ivanov,
Claudiu Beznea, Saravanan Sekar, Matthias Brugger,
AngeloGioacchino Del Regno, Jagan Teki, Icenowy Zheng,
linux-arm-kernel, linux-mediatek
Hello,
v2 is available at https://lore.kernel.org/lkml/cover.1779184320.git.u.kleine-koenig@baylibre.com .
The only change is that I rebased to next-20260619 and dropped the
adaptions to the of_regulator_match arrays that Laurent pointed out to
not belong into this patch set.
Best regards
Uwe
Uwe Kleine-König (The Capable Hub) (2):
regulator: Drop unused i2c driver data
regulator: Use named initializers for arrays of i2c_device_data
drivers/regulator/88pg86x.c | 4 ++--
drivers/regulator/ad5398.c | 4 ++--
drivers/regulator/da9121-regulator.c | 20 ++++++++++----------
drivers/regulator/da9210-regulator.c | 4 ++--
drivers/regulator/da9211-regulator.c | 18 +++++++++---------
drivers/regulator/fan53880.c | 4 ++--
drivers/regulator/isl9305.c | 4 ++--
drivers/regulator/lp3971.c | 2 +-
drivers/regulator/lp3972.c | 2 +-
drivers/regulator/lp872x.c | 4 ++--
drivers/regulator/lp8755.c | 4 ++--
drivers/regulator/ltc3589.c | 6 +++---
drivers/regulator/ltc3676.c | 2 +-
drivers/regulator/max1586.c | 2 +-
drivers/regulator/max20086-regulator.c | 8 ++++----
drivers/regulator/max20411-regulator.c | 2 +-
drivers/regulator/max77503-regulator.c | 2 +-
drivers/regulator/max77675-regulator.c | 2 +-
drivers/regulator/max77826-regulator.c | 2 +-
drivers/regulator/max77838-regulator.c | 2 +-
drivers/regulator/max77857-regulator.c | 8 ++++----
drivers/regulator/max8649.c | 2 +-
drivers/regulator/max8893.c | 2 +-
drivers/regulator/max8952.c | 2 +-
drivers/regulator/mcp16502.c | 2 +-
drivers/regulator/mp5416.c | 6 +++---
drivers/regulator/mp8859.c | 4 ++--
drivers/regulator/mp886x.c | 6 +++---
drivers/regulator/mpq7920.c | 4 ++--
drivers/regulator/mt6311-regulator.c | 4 ++--
drivers/regulator/pf530x-regulator.c | 8 ++++----
drivers/regulator/pf8x00-regulator.c | 8 ++++----
drivers/regulator/pv88060-regulator.c | 4 ++--
drivers/regulator/pv88080-regulator.c | 8 ++++----
drivers/regulator/pv88090-regulator.c | 4 ++--
drivers/regulator/slg51000-regulator.c | 4 ++--
drivers/regulator/sy8106a-regulator.c | 2 +-
drivers/regulator/sy8824x.c | 8 ++++----
drivers/regulator/sy8827n.c | 4 ++--
drivers/regulator/tps6286x-regulator.c | 10 +++++-----
drivers/regulator/tps6287x-regulator.c | 10 +++++-----
41 files changed, 104 insertions(+), 104 deletions(-)
base-commit: 3ce97bd3c4f18608335e709c24d6a40e7036cab8
--
2.47.3
^ permalink raw reply
* [PATCH v2] mfd: mt6397-irq: Fix PM notifier and IRQ domain teardown
From: Yuho Choi @ 2026-06-19 16:56 UTC (permalink / raw)
To: Lee Jones, Matthias Brugger, AngeloGioacchino Del Regno
Cc: linux-kernel, linux-arm-kernel, linux-mediatek, Yuho Choi
mt6397_irq_init() registers a PM notifier and creates an irq_domain. Both
objects point back to the devm-managed mt6397_chip.
The notifier was not unregistered on probe failure or unbind, so a later PM
transition could dereference freed chip state. The irq_domain had the
opposite lifetime problem: it could be removed while the devm-managed
parent IRQ was still active, but it was leaked on successful unbind.
Manage both lifetimes with devm actions. Register the domain cleanup before
requesting the parent IRQ, so devres frees the parent IRQ before removing
child mappings and the irq_domain. This keeps the domain alive while the
parent IRQ handler can still run.
Also serialize PM notifier mask writes with irqlock. While suspend is in
progress, keep wake_mask programmed in hardware even if a concurrent IRQ
sync updates irq_masks_cur in software.
Fixes: a4872e80ce7d ("mfd: mt6397: Extract IRQ related code from core driver")
Fixes: 4e2e7cfec13a ("mfd: mt6397: Modify suspend/resume behavior")
Signed-off-by: Yuho Choi <dbgh9129@gmail.com>
---
Changes in v2:
- Use devm actions for PM notifier and irq_domain cleanup.
- Remove direct irq_domain_remove() calls from failure paths.
- Serialize PM notifier mask writes with irqlock.
---
drivers/mfd/mt6397-core.c | 4 +-
drivers/mfd/mt6397-irq.c | 85 +++++++++++++++++++++++----------
include/linux/mfd/mt6397/core.h | 1 +
3 files changed, 63 insertions(+), 27 deletions(-)
diff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c
index 1bdacda9a933..ff1e393202ee 100644
--- a/drivers/mfd/mt6397-core.c
+++ b/drivers/mfd/mt6397-core.c
@@ -389,10 +389,8 @@ static int mt6397_probe(struct platform_device *pdev)
ret = devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE,
pmic_core->cells, pmic_core->cell_size,
NULL, 0, pmic->irq_domain);
- if (ret) {
- irq_domain_remove(pmic->irq_domain);
+ if (ret)
dev_err(&pdev->dev, "failed to add child devices: %d\n", ret);
- }
return ret;
}
diff --git a/drivers/mfd/mt6397-irq.c b/drivers/mfd/mt6397-irq.c
index 5d2e5459f744..4be74d8325cd 100644
--- a/drivers/mfd/mt6397-irq.c
+++ b/drivers/mfd/mt6397-irq.c
@@ -25,17 +25,23 @@ static void mt6397_irq_lock(struct irq_data *data)
mutex_lock(&mt6397->irqlock);
}
+static void mt6397_irq_write_masks(struct mt6397_chip *mt6397,
+ const u16 *masks)
+{
+ regmap_write(mt6397->regmap, mt6397->int_con[0], masks[0]);
+ regmap_write(mt6397->regmap, mt6397->int_con[1], masks[1]);
+ if (mt6397->int_con[2])
+ regmap_write(mt6397->regmap, mt6397->int_con[2], masks[2]);
+}
+
static void mt6397_irq_sync_unlock(struct irq_data *data)
{
struct mt6397_chip *mt6397 = irq_data_get_irq_chip_data(data);
+ const u16 *masks;
- regmap_write(mt6397->regmap, mt6397->int_con[0],
- mt6397->irq_masks_cur[0]);
- regmap_write(mt6397->regmap, mt6397->int_con[1],
- mt6397->irq_masks_cur[1]);
- if (mt6397->int_con[2])
- regmap_write(mt6397->regmap, mt6397->int_con[2],
- mt6397->irq_masks_cur[2]);
+ masks = mt6397->irq_suspended ? mt6397->wake_mask :
+ mt6397->irq_masks_cur;
+ mt6397_irq_write_masks(mt6397, masks);
mutex_unlock(&mt6397->irqlock);
}
@@ -141,24 +147,20 @@ static int mt6397_irq_pm_notifier(struct notifier_block *notifier,
switch (pm_event) {
case PM_SUSPEND_PREPARE:
- regmap_write(chip->regmap,
- chip->int_con[0], chip->wake_mask[0]);
- regmap_write(chip->regmap,
- chip->int_con[1], chip->wake_mask[1]);
- if (chip->int_con[2])
- regmap_write(chip->regmap,
- chip->int_con[2], chip->wake_mask[2]);
+ mutex_lock(&chip->irqlock);
+ chip->irq_suspended = true;
+ mt6397_irq_write_masks(chip, chip->wake_mask);
+ mutex_unlock(&chip->irqlock);
+
enable_irq_wake(chip->irq);
break;
case PM_POST_SUSPEND:
- regmap_write(chip->regmap,
- chip->int_con[0], chip->irq_masks_cur[0]);
- regmap_write(chip->regmap,
- chip->int_con[1], chip->irq_masks_cur[1]);
- if (chip->int_con[2])
- regmap_write(chip->regmap,
- chip->int_con[2], chip->irq_masks_cur[2]);
+ mutex_lock(&chip->irqlock);
+ chip->irq_suspended = false;
+ mt6397_irq_write_masks(chip, chip->irq_masks_cur);
+ mutex_unlock(&chip->irqlock);
+
disable_irq_wake(chip->irq);
break;
@@ -169,6 +171,29 @@ static int mt6397_irq_pm_notifier(struct notifier_block *notifier,
return NOTIFY_DONE;
}
+static void mt6397_irq_pm_notifier_unregister(void *data)
+{
+ struct mt6397_chip *chip = data;
+
+ unregister_pm_notifier(&chip->pm_nb);
+}
+
+static void mt6397_irq_domain_remove(void *data)
+{
+ struct mt6397_chip *chip = data;
+ unsigned int hwirq;
+ unsigned int virq;
+
+ for (hwirq = 0; hwirq < MT6397_IRQ_NR; hwirq++) {
+ virq = irq_find_mapping(chip->irq_domain, hwirq);
+ if (virq)
+ irq_dispose_mapping(virq);
+ }
+
+ irq_domain_remove(chip->irq_domain);
+ chip->irq_domain = NULL;
+}
+
int mt6397_irq_init(struct mt6397_chip *chip)
{
int ret;
@@ -223,16 +248,28 @@ int mt6397_irq_init(struct mt6397_chip *chip)
return -ENOMEM;
}
+ ret = devm_add_action_or_reset(chip->dev, mt6397_irq_domain_remove,
+ chip);
+ if (ret)
+ return ret;
+
ret = devm_request_threaded_irq(chip->dev, chip->irq, NULL,
mt6397_irq_thread, IRQF_ONESHOT,
"mt6397-pmic", chip);
if (ret) {
dev_err(chip->dev, "failed to register irq=%d; err: %d\n",
chip->irq, ret);
- irq_domain_remove(chip->irq_domain);
return ret;
}
- register_pm_notifier(&chip->pm_nb);
- return 0;
+ ret = register_pm_notifier(&chip->pm_nb);
+ if (ret) {
+ dev_err(chip->dev, "failed to register PM notifier: %d\n", ret);
+ return ret;
+ }
+
+ ret = devm_add_action_or_reset(chip->dev,
+ mt6397_irq_pm_notifier_unregister, chip);
+
+ return ret;
}
diff --git a/include/linux/mfd/mt6397/core.h b/include/linux/mfd/mt6397/core.h
index 340fc72e22aa..f9c2cbd17c5c 100644
--- a/include/linux/mfd/mt6397/core.h
+++ b/include/linux/mfd/mt6397/core.h
@@ -66,6 +66,7 @@ struct mt6397_chip {
int irq;
struct irq_domain *irq_domain;
struct mutex irqlock;
+ bool irq_suspended;
u16 wake_mask[3];
u16 irq_masks_cur[3];
u16 irq_masks_cache[3];
--
2.43.0
^ permalink raw reply related
* Re: [PATCH v3] drm/bridge: imx93-mipi-dsi: Fix mode validation
From: Luca Ceresoli @ 2026-06-19 16:49 UTC (permalink / raw)
To: Liu Ying, Andrzej Hajda, Neil Armstrong, Robert Foss,
Laurent Pinchart, Jonas Karlman, Jernej Skrabec,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Frank Li, Sascha Hauer, Pengutronix Kernel Team,
Fabio Estevam, Luca Ceresoli
Cc: Dmitry Baryshkov, dri-devel, imx, linux-arm-kernel, linux-kernel
In-Reply-To: <20260515-imx93-mipi-dsi-fix-mode-validation-v3-1-91f7d22b2fe4@nxp.com>
Hello Liu,
On Fri May 15, 2026 at 8:54 AM CEST, Liu Ying wrote:
> i.MX93 MIPI DPHY PLL has limitation for matching with some pixel clock
> rates, e.g., the best DPHY PLL frequency is 445.333333MHz for a typical
> 1920x1080p@60Hz CEA/DMT display mode with a pixel clock rate running
> at 148.5MHz with 4 data lanes + RGB888 pixel in MIPI DSI sync pulse mode,
> while the expected PLL frequency is (148.5 * 24) / 4 / 2 MHz = 445.5MHz.
> Fortunately, VESA Display Monitor Timing Standard allows +/-0.5% pixel
> clock rate deviation for timings. So, for those display modes read
> from EDID through a bridge with DRM_BRIDGE_OP_DETECT and DRM_BRIDGE_OP_EDID
> operation bit masks set, pixel clock rate could be adjusted to match
> with the PLL frequency(for the above example, the pixel clock rate is
> adjusted to be 148.444444MHz with about -0.03% deviation from the 148.5MHz
> nominal rate so that the adjusted rate matches with the 445.333333MHz PLL
> frequency).
>
> Instead of checking the last bridge's operation bit masks against
> DRM_BRIDGE_OP_DETECT and DRM_BRIDGE_OP_EDID to determine if allowing
> +/-0.5% pixel clock rate deviation, check any bridge after this bridge,
> because the last bridge is usually a display connector bridge without
> any operation bit mask when the clock rate deviation is allowed.
>
> Fixes: ce62f8ea7e3f ("drm/bridge: imx: Add i.MX93 MIPI DSI support")
> Fixes: 5849eff7f067 ("drm/bridge: imx93-mipi-dsi: use drm_bridge_chain_get_last_bridge()")
> Reviewed-by: Frank Li <Frank.Li@nxp.com>
> Signed-off-by: Liu Ying <victor.liu@nxp.com>
I'm perhaps not the most qualified to review this change, but let me try.
> --- a/drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c
> +++ b/drivers/gpu/drm/bridge/imx/imx93-mipi-dsi.c
> @@ -489,25 +489,43 @@ static int imx93_dsi_get_phy_configure_opts(struct imx93_dsi *dsi,
> return 0;
> }
>
> +static inline struct drm_bridge *
> +imx93_dsi_get_next_bridge_in_chain(struct drm_bridge *bridge)
> +{
> + struct drm_bridge *next = drm_bridge_get_next_bridge(bridge);
> +
> + drm_bridge_put(bridge);
> +
> + return next;
> +}
> +
> static enum drm_mode_status
> imx93_dsi_validate_mode(struct imx93_dsi *dsi, const struct drm_display_mode *mode)
> {
> struct drm_bridge *dmd_bridge = dw_mipi_dsi_get_bridge(dsi->dmd);
> - struct drm_bridge *last_bridge __free(drm_bridge_put) =
> - drm_bridge_chain_get_last_bridge(dmd_bridge->encoder);
> + struct drm_bridge *bridge;
>
> - if ((last_bridge->ops & DRM_BRIDGE_OP_DETECT) &&
> - (last_bridge->ops & DRM_BRIDGE_OP_EDID)) {
> - unsigned long pixel_clock_rate = mode->clock * 1000;
> - unsigned long rounded_rate;
> + for (bridge = drm_bridge_get_next_bridge(dmd_bridge);
> + bridge;
> + bridge = imx93_dsi_get_next_bridge_in_chain(bridge)) {
> + if ((bridge->ops & DRM_BRIDGE_OP_DETECT) &&
> + (bridge->ops & DRM_BRIDGE_OP_EDID)) {
> + unsigned long pixel_clock_rate = mode->clock * 1000;
> + unsigned long rounded_rate;
>
> - /* Allow +/-0.5% pixel clock rate deviation */
> - rounded_rate = clk_round_rate(dsi->clk_pixel, pixel_clock_rate);
> - if (rounded_rate < pixel_clock_rate * 995 / 1000 ||
> - rounded_rate > pixel_clock_rate * 1005 / 1000) {
> - dev_dbg(dsi->dev, "failed to round clock for mode " DRM_MODE_FMT "\n",
> - DRM_MODE_ARG(mode));
> - return MODE_NOCLOCK;
> + /* Allow +/-0.5% pixel clock rate deviation */
> + rounded_rate = clk_round_rate(dsi->clk_pixel, pixel_clock_rate);
> + if (rounded_rate < pixel_clock_rate * 995 / 1000 ||
> + rounded_rate > pixel_clock_rate * 1005 / 1000) {
> + dev_dbg(dsi->dev,
> + "failed to round clock for mode " DRM_MODE_FMT "\n",
> + DRM_MODE_ARG(mode));
> + drm_bridge_put(bridge);
> + return MODE_NOCLOCK;
> + }
> +
> + drm_bridge_put(bridge);
> + break;
> }
> }
Is this logic specific to the imx93 MIPI DSI host only? Or should it be
made generic for all dw-hdmi users, or even every DSI host?
Also, iterating over the bridge chain is not very clean. I'm working on
bridge hotplug (not upstream yet) and bad things would happen if a bridge
were hot-unplugged during this loop. If the core did this sort of algorithm
it would be able to be more robust.
Finally, out of my utter ignorance on the subject, is the VESA +/-0.5%
margin generic enough that this driver can always rely on it?
Luca
--
Luca Ceresoli, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply
* Re: [PATCH v2 8/8] KVM: arm64: Implement lazy vCPU state sync for non-protected guests
From: Fuad Tabba @ 2026-06-19 16:41 UTC (permalink / raw)
To: Vincent Donnefort
Cc: Marc Zyngier, Oliver Upton, kvmarm, linux-arm-kernel,
linux-kernel, Catalin Marinas, Will Deacon, Joey Gouly,
Steffen Eiden, Suzuki K Poulose, Zenghui Yu, Quentin Perret,
Sebastian Ene, Hyunwoo Kim
In-Reply-To: <ajVAV5ct0xdLn1KX@google.com>
On Fri, 19 Jun 2026 at 14:13, Vincent Donnefort <vdonnefort@google.com> wrote:
>
> On Fri, Jun 19, 2026 at 08:07:19AM +0100, Fuad Tabba wrote:
> > pKVM copies a non-protected guest's register context between the host
> > and the hypervisor on every world switch, even when the host never
> > inspects it. Defer the copy: on entry, flush the host context into the
> > hyp vCPU only when the host marked it dirty (PKVM_HOST_STATE_DIRTY); on
> > exit, leave it in the hyp vCPU and copy it back only when the host needs
> > it, via a __pkvm_vcpu_sync_state hypercall on trap handling or at vcpu
> > put. A protected guest's context is copied as before, since lazy sync
> > only helps where the host is trusted to see the guest's registers.
> >
> > PC and PSTATE are the exception: they are copied back on every exit so
> > the kvm_exit tracepoint reports the guest's real exit PC, and the run
> > loop's vcpu_mode_is_bad_32bit() and SError-masking checks evaluate the
> > guest's current PSTATE rather than the value left by the previous sync.
> >
> > handle_exit_early() can also inject an SError, which writes the guest
> > context (ESR_EL1) outside the trap-handling path. For a non-protected
> > guest it therefore syncs the context from the hyp vCPU and marks it
> > dirty, as handle_trap_exceptions() does, so the injection reaches the
> > hyp vCPU on re-entry rather than being dropped.
> >
> > Signed-off-by: Fuad Tabba <tabba@google.com>
> > ---
> > arch/arm64/include/asm/kvm_asm.h | 1 +
> > arch/arm64/include/asm/kvm_host.h | 2 +
> > arch/arm64/kvm/arm.c | 7 +++
> > arch/arm64/kvm/handle_exit.c | 30 +++++++++++
> > arch/arm64/kvm/hyp/nvhe/hyp-main.c | 86 ++++++++++++++++++++++++++++--
> > 5 files changed, 121 insertions(+), 5 deletions(-)
> >
> > diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include/asm/kvm_asm.h
> > index 043495f7fc78..6e1135b3ded4 100644
> > --- a/arch/arm64/include/asm/kvm_asm.h
> > +++ b/arch/arm64/include/asm/kvm_asm.h
> > @@ -113,6 +113,7 @@ enum __kvm_host_smccc_func {
> > __KVM_HOST_SMCCC_FUNC___pkvm_finalize_teardown_vm,
> > __KVM_HOST_SMCCC_FUNC___pkvm_vcpu_load,
> > __KVM_HOST_SMCCC_FUNC___pkvm_vcpu_put,
> > + __KVM_HOST_SMCCC_FUNC___pkvm_vcpu_sync_state,
> > __KVM_HOST_SMCCC_FUNC___pkvm_tlb_flush_vmid,
> >
> > MARKER(__KVM_HOST_SMCCC_FUNC_MAX)
> > diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
> > index 2faa60df847d..caa39ee5125f 100644
> > --- a/arch/arm64/include/asm/kvm_host.h
> > +++ b/arch/arm64/include/asm/kvm_host.h
> > @@ -1068,6 +1068,8 @@ struct kvm_vcpu_arch {
> > #define INCREMENT_PC __vcpu_single_flag(iflags, BIT(1))
> > /* Target EL/MODE (not a single flag, but let's abuse the macro) */
> > #define EXCEPT_MASK __vcpu_single_flag(iflags, GENMASK(3, 1))
> > +/* Host-set: the hyp flushes the non-protected vCPU state in on entry */
> > +#define PKVM_HOST_STATE_DIRTY __vcpu_single_flag(iflags, BIT(4))
> >
> > /* Helpers to encode exceptions with minimum fuss */
> > #define __EXCEPT_MASK_VAL unpack_vcpu_flag(EXCEPT_MASK)
> > diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c
> > index 3732ee9eb0d4..4e89558d8027 100644
> > --- a/arch/arm64/kvm/arm.c
> > +++ b/arch/arm64/kvm/arm.c
> > @@ -733,6 +733,10 @@ void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
> > if (is_protected_kvm_enabled()) {
> > kvm_call_hyp(__vgic_v3_save_aprs, &vcpu->arch.vgic_cpu.vgic_v3);
> > kvm_call_hyp_nvhe(__pkvm_vcpu_put);
> > +
> > + /* __pkvm_vcpu_put implies a sync of the state */
> > + if (!kvm_vm_is_protected(vcpu->kvm))
> > + vcpu_set_flag(vcpu, PKVM_HOST_STATE_DIRTY);
> > }
> >
> > kvm_vcpu_put_debug(vcpu);
> > @@ -964,6 +968,9 @@ int kvm_arch_vcpu_run_pid_change(struct kvm_vcpu *vcpu)
> > return ret;
> >
> > if (is_protected_kvm_enabled()) {
> > + /* Start with the vcpu in a dirty state */
> > + if (!kvm_vm_is_protected(vcpu->kvm))
> > + vcpu_set_flag(vcpu, PKVM_HOST_STATE_DIRTY);
> > ret = pkvm_create_hyp_vm(kvm);
> > if (ret)
> > return ret;
> > diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c
> > index 54aedf93c78b..8963621bcdd1 100644
> > --- a/arch/arm64/kvm/handle_exit.c
> > +++ b/arch/arm64/kvm/handle_exit.c
> > @@ -422,6 +422,20 @@ static int handle_trap_exceptions(struct kvm_vcpu *vcpu)
> > {
> > int handled;
> >
> > + /*
> > + * If we run a non-protected VM when protection is enabled
> > + * system-wide, resync the state from the hypervisor and mark
> > + * it as dirty on the host side if it wasn't dirty already
> > + * (which could happen if preemption has taken place).
> > + */
> > + if (is_protected_kvm_enabled() && !kvm_vm_is_protected(vcpu->kvm)) {
> > + guard(preempt)();
> > + if (!(vcpu_get_flag(vcpu, PKVM_HOST_STATE_DIRTY))) {
> > + kvm_call_hyp_nvhe(__pkvm_vcpu_sync_state);
> > + vcpu_set_flag(vcpu, PKVM_HOST_STATE_DIRTY);
> > + }
> > + }
> > +
>
> Could we remove this update here and let handle_exit_early() do the sync
> regardless of the SError injection? One of the main point of handle_exit_early()
> is to do things under !prempt().
Agreed on the move: handle_exit_early() is already preempt-off, so the
guard() goes away. Not on every exit though. handle_exit_early() runs
on every exit, and sync_hyp_vcpu() only copies PC/PSTATE/fault back
for a non-protected guest; the GPRs and sysregs cross solely via
__pkvm_vcpu_sync_state. Syncing unconditionally would pull the full
context back on plain IRQ exits, which is the copy this patch avoids.
So I will gate it on trap-or-SError and drop the
handle_trap_exceptions() block.
>
>
> > /*
> > * See ARM ARM B1.14.1: "Hyp traps on instructions
> > * that fail their condition code check"
> > @@ -489,6 +503,22 @@ int handle_exit(struct kvm_vcpu *vcpu, int exception_index)
> > /* For exit types that need handling before we can be preempted */
> > void handle_exit_early(struct kvm_vcpu *vcpu, int exception_index)
> > {
> > + bool inject_serror = ARM_SERROR_PENDING(exception_index) ||
> > + ARM_EXCEPTION_CODE(exception_index) == ARM_EXCEPTION_EL1_SERROR;
> > +
> > + /*
> > + * An SError injected below writes the host ctxt; for a non-protected
> > + * guest, sync from the hyp vCPU and keep it dirty so it isn't dropped.
> > + */
> > + if (is_protected_kvm_enabled()) {
>
> Should we test !kvm_vm_is_protected(vcpu->kvm) here, as the
> PKVM_HOST_STATE_DIRTY is only updated for p-guests everywhere else?
Yes. The flag is only ever set for non-protected guests, so clearing it
for a protected one is a no-op, but gating it matches the invariant.
Both fold into one block in handle_exit_early():
if (is_protected_kvm_enabled() && !kvm_vm_is_protected(vcpu->kvm)) {
if (inject_serror ||
ARM_EXCEPTION_CODE(exception_index) == ARM_EXCEPTION_TRAP) {
kvm_call_hyp_nvhe(__pkvm_vcpu_sync_state);
vcpu_set_flag(vcpu, PKVM_HOST_STATE_DIRTY);
} else {
vcpu_clear_flag(vcpu, PKVM_HOST_STATE_DIRTY);
}
}
I will fold this into the next respin.
Thanks for the reviews!
/fuad
>
> > + vcpu_clear_flag(vcpu, PKVM_HOST_STATE_DIRTY);
> > +
> > + if (inject_serror && !kvm_vm_is_protected(vcpu->kvm)) {
> > + kvm_call_hyp_nvhe(__pkvm_vcpu_sync_state);
> > + vcpu_set_flag(vcpu, PKVM_HOST_STATE_DIRTY);
> > + }
> > + }
> > +
> > if (ARM_SERROR_PENDING(exception_index)) {
> > if (this_cpu_has_cap(ARM64_HAS_RAS_EXTN)) {
> > u64 disr = kvm_vcpu_get_disr(vcpu);
>
> [...]
^ permalink raw reply
* [PATCH] arm64: mm: Defer read-only remap of data/bss linear alias
From: Ard Biesheuvel @ 2026-06-19 16:39 UTC (permalink / raw)
To: linux-arm-kernel
Cc: linux-kernel, catalin.marinas, will, Ard Biesheuvel, Fuad Tabba
From: Ard Biesheuvel <ardb@kernel.org>
Fuad reports that in some cases, the KVM init code may apply relocations
to variables that reside in .data, and does so via the linear map. This
means that remapping .data read-only beforehand is a bad idea, and
results in an early boot crash.
These variables in .data are only present when CONFIG_NVHE_EL2_DEBUG or
CONFIG_NVHE_EL2_TRACING are enabled, which is why it was not spotted in
testing.
So move the remap to mark_rodata_ro(), which is a reasonable place to
put this, and ensures that it happens much later during the boot. It
also means that rodata=off is now taken into account, and so the linear
alias will remain writable in that case.
Cc: Fuad Tabba <fuad.tabba@linux.dev>
Fixes: f2ba877402e5 ("arm64: mm: Map the kernel data/bss read-only in the linear map")
Signed-off-by: Ard Biesheuvel <ardb@kernel.org>
---
arch/arm64/mm/mmu.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
index 9f354971b7e4..1f7eca86b5c1 100644
--- a/arch/arm64/mm/mmu.c
+++ b/arch/arm64/mm/mmu.c
@@ -1198,11 +1198,6 @@ static void __init map_mem(void)
__map_memblock(start, end, pgprot_tagged(PAGE_KERNEL),
flags);
}
-
- /* Map the kernel data/bss read-only in the linear map */
- __map_memblock(init_end, kernel_end, PAGE_KERNEL_RO, flags);
- flush_tlb_kernel_range((unsigned long)lm_alias(__init_end),
- (unsigned long)lm_alias(__bss_stop));
}
void mark_rodata_ro(void)
@@ -1221,6 +1216,12 @@ void mark_rodata_ro(void)
update_mapping_prot(__pa_symbol(_text), (unsigned long)_text,
(unsigned long)_stext - (unsigned long)_text,
PAGE_KERNEL_RO);
+
+ /* Map the kernel data/bss read-only in the linear map */
+ update_mapping_prot(__pa_symbol(__init_end),
+ (unsigned long)lm_alias(__init_end),
+ (unsigned long)__bss_stop - (unsigned long)__init_end,
+ PAGE_KERNEL_RO);
}
static void __init declare_vma(struct vm_struct *vma,
--
2.55.0.rc0.738.g0c8ab3ebcc-goog
^ permalink raw reply related
* [PATCH] remoteproc: xlnx: refactor start & stop ops
From: Tanmay Shah @ 2026-06-19 16:38 UTC (permalink / raw)
To: michal.simek, andersson, mathieu.poirier
Cc: linux-arm-kernel, linux-kernel, linux-remoteproc, Tanmay Shah
Current _start and _stop ops are implemented using various APIs from the
platform management firmware driver. Instead provide respective RPU
start and stop API in the firmware driver and move the logic to interact
with the PM firmware in the firmware driver. The remoteproc driver doesn't
need to know actual logic, but only the final result i.e. RPU start/stop
was success or not. This refactor keeps the remoteproc driver simple and
moves firmware interaction logic to the firmware driver.
Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
---
drivers/firmware/xilinx/zynqmp.c | 93 +++++++++++++++++++++++++
drivers/remoteproc/xlnx_r5_remoteproc.c | 68 ++----------------
include/linux/firmware/xlnx-zynqmp.h | 12 ++++
3 files changed, 110 insertions(+), 63 deletions(-)
diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c
index af838b2dc327..f9a3a95b0638 100644
--- a/drivers/firmware/xilinx/zynqmp.c
+++ b/drivers/firmware/xilinx/zynqmp.c
@@ -1513,6 +1513,99 @@ int zynqmp_pm_request_wake(const u32 node,
}
EXPORT_SYMBOL_GPL(zynqmp_pm_request_wake);
+/**
+ * zynqmp_pm_start_rpu - Boot Real-time Processing Unit (Cortex-R) on SoC
+ *
+ * @node: power-domains id of the core
+ * @bootaddr: Boot address of elf
+ *
+ * Return: status, either success or error+reason
+ */
+int zynqmp_pm_start_rpu(const u32 node, const u64 bootaddr)
+{
+ enum rpu_boot_mem bootmem;
+ int ret;
+
+ /*
+ * The exception vector pointers (EVP) refer to the base-address of
+ * exception vectors (for reset, IRQ, FIQ, etc). The reset-vector
+ * starts at the base-address and subsequent vectors are on 4-byte
+ * boundaries.
+ *
+ * Exception vectors can start either from 0x0000_0000 (LOVEC) or
+ * from 0xFFFF_0000 (HIVEC) which is mapped in the OCM (On-Chip Memory)
+ *
+ * Usually firmware will put Exception vectors at LOVEC.
+ *
+ * It is not recommend that you change the exception vector.
+ * Changing the EVP to HIVEC will result in increased interrupt latency
+ * and jitter. Also, if the OCM is secured and the Cortex-R5F processor
+ * is non-secured, then the Cortex-R5F processor cannot access the
+ * HIVEC exception vectors in the OCM.
+ */
+ bootmem = (bootaddr >= 0xFFFC0000) ?
+ PM_RPU_BOOTMEM_HIVEC : PM_RPU_BOOTMEM_LOVEC;
+
+ pr_debug("RPU boot addr 0x%llx from %s.", bootaddr,
+ bootmem == PM_RPU_BOOTMEM_HIVEC ? "OCM" : "TCM");
+
+ /* Request node before starting RPU core if new version of API is supported */
+ if (zynqmp_pm_feature(PM_REQUEST_NODE) > PM_API_VERSION_1) {
+ ret = zynqmp_pm_request_node(node,
+ ZYNQMP_PM_CAPABILITY_ACCESS, 0,
+ ZYNQMP_PM_REQUEST_ACK_BLOCKING);
+ if (ret < 0) {
+ pr_err("failed to request 0x%x", node);
+ return ret;
+ }
+ }
+
+ ret = zynqmp_pm_request_wake(node, true,
+ bootmem, ZYNQMP_PM_REQUEST_ACK_NO);
+ if (ret)
+ pr_err("failed to start RPU = 0x%x\n", node);
+ return ret;
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_start_rpu);
+
+/**
+ * zynqmp_pm_stop_rpu - Stop Real-time Processing Unit (Cortex-R) on SoC
+ *
+ * @node: power-domains id of the core
+ *
+ * Return: status, either success or error+reason
+ */
+int zynqmp_pm_stop_rpu(const u32 node)
+{
+ int ret;
+
+ /* Use release node API to stop core if new version of API is supported */
+ if (zynqmp_pm_feature(PM_RELEASE_NODE) > PM_API_VERSION_1) {
+ ret = zynqmp_pm_release_node(node);
+ if (ret)
+ pr_err("failed to stop remoteproc RPU %d\n", ret);
+ return ret;
+ }
+
+ /*
+ * Check expected version of EEMI call before calling it. This avoids
+ * any error or warning prints from firmware as it is expected that fw
+ * doesn't support it.
+ */
+ if (zynqmp_pm_feature(PM_FORCE_POWERDOWN) != PM_API_VERSION_1) {
+ pr_debug("EEMI interface %d ver 1 not supported\n",
+ PM_FORCE_POWERDOWN);
+ return -EOPNOTSUPP;
+ }
+
+ /* maintain force pwr down for backward compatibility */
+ ret = zynqmp_pm_force_pwrdwn(node, ZYNQMP_PM_REQUEST_ACK_BLOCKING);
+ if (ret)
+ pr_err("core force power down failed\n");
+ return ret;
+}
+EXPORT_SYMBOL_GPL(zynqmp_pm_stop_rpu);
+
/**
* zynqmp_pm_set_requirement() - PM call to set requirement for PM slaves
* @node: Node ID of the slave
diff --git a/drivers/remoteproc/xlnx_r5_remoteproc.c b/drivers/remoteproc/xlnx_r5_remoteproc.c
index 3349d1877751..dcd8a93f031c 100644
--- a/drivers/remoteproc/xlnx_r5_remoteproc.c
+++ b/drivers/remoteproc/xlnx_r5_remoteproc.c
@@ -364,49 +364,12 @@ static void zynqmp_r5_rproc_kick(struct rproc *rproc, int vqid)
static int zynqmp_r5_rproc_start(struct rproc *rproc)
{
struct zynqmp_r5_core *r5_core = rproc->priv;
- enum rpu_boot_mem bootmem;
int ret;
- /*
- * The exception vector pointers (EVP) refer to the base-address of
- * exception vectors (for reset, IRQ, FIQ, etc). The reset-vector
- * starts at the base-address and subsequent vectors are on 4-byte
- * boundaries.
- *
- * Exception vectors can start either from 0x0000_0000 (LOVEC) or
- * from 0xFFFF_0000 (HIVEC) which is mapped in the OCM (On-Chip Memory)
- *
- * Usually firmware will put Exception vectors at LOVEC.
- *
- * It is not recommend that you change the exception vector.
- * Changing the EVP to HIVEC will result in increased interrupt latency
- * and jitter. Also, if the OCM is secured and the Cortex-R5F processor
- * is non-secured, then the Cortex-R5F processor cannot access the
- * HIVEC exception vectors in the OCM.
- */
- bootmem = (rproc->bootaddr >= 0xFFFC0000) ?
- PM_RPU_BOOTMEM_HIVEC : PM_RPU_BOOTMEM_LOVEC;
-
- dev_dbg(r5_core->dev, "RPU boot addr 0x%llx from %s.", rproc->bootaddr,
- bootmem == PM_RPU_BOOTMEM_HIVEC ? "OCM" : "TCM");
-
- /* Request node before starting RPU core if new version of API is supported */
- if (zynqmp_pm_feature(PM_REQUEST_NODE) > 1) {
- ret = zynqmp_pm_request_node(r5_core->pm_domain_id,
- ZYNQMP_PM_CAPABILITY_ACCESS, 0,
- ZYNQMP_PM_REQUEST_ACK_BLOCKING);
- if (ret < 0) {
- dev_err(r5_core->dev, "failed to request 0x%x",
- r5_core->pm_domain_id);
- return ret;
- }
- }
-
- ret = zynqmp_pm_request_wake(r5_core->pm_domain_id, 1,
- bootmem, ZYNQMP_PM_REQUEST_ACK_NO);
+ ret = zynqmp_pm_start_rpu(r5_core->pm_domain_id, rproc->bootaddr);
if (ret)
- dev_err(r5_core->dev,
- "failed to start RPU = 0x%x\n", r5_core->pm_domain_id);
+ dev_err(&rproc->dev, "failed to start RPU\n");
+
return ret;
}
@@ -423,30 +386,9 @@ static int zynqmp_r5_rproc_stop(struct rproc *rproc)
struct zynqmp_r5_core *r5_core = rproc->priv;
int ret;
- /* Use release node API to stop core if new version of API is supported */
- if (zynqmp_pm_feature(PM_RELEASE_NODE) > 1) {
- ret = zynqmp_pm_release_node(r5_core->pm_domain_id);
- if (ret)
- dev_err(r5_core->dev, "failed to stop remoteproc RPU %d\n", ret);
- return ret;
- }
-
- /*
- * Check expected version of EEMI call before calling it. This avoids
- * any error or warning prints from firmware as it is expected that fw
- * doesn't support it.
- */
- if (zynqmp_pm_feature(PM_FORCE_POWERDOWN) != 1) {
- dev_dbg(r5_core->dev, "EEMI interface %d ver 1 not supported\n",
- PM_FORCE_POWERDOWN);
- return -EOPNOTSUPP;
- }
-
- /* maintain force pwr down for backward compatibility */
- ret = zynqmp_pm_force_pwrdwn(r5_core->pm_domain_id,
- ZYNQMP_PM_REQUEST_ACK_BLOCKING);
+ ret = zynqmp_pm_stop_rpu(r5_core->pm_domain_id);
if (ret)
- dev_err(r5_core->dev, "core force power down failed\n");
+ dev_err(&rproc->dev, "failed to stop RPU\n");
return ret;
}
diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h
index 7e27b0f7bf7e..347df66ee176 100644
--- a/include/linux/firmware/xlnx-zynqmp.h
+++ b/include/linux/firmware/xlnx-zynqmp.h
@@ -644,6 +644,8 @@ int zynqmp_pm_get_node_status(const u32 node, u32 *const status,
u32 *const requirements, u32 *const usage);
int zynqmp_pm_get_rpu_node_status(const u32 node, u32 *const status,
u32 *const requirements, u32 *const usage);
+int zynqmp_pm_start_rpu(const u32 node, const u64 bootaddr);
+int zynqmp_pm_stop_rpu(const u32 node);
int zynqmp_pm_set_sd_config(u32 node, enum pm_sd_config_type config, u32 value);
int zynqmp_pm_set_gem_config(u32 node, enum pm_gem_config_type config,
u32 value);
@@ -960,6 +962,16 @@ static inline int zynqmp_pm_get_rpu_node_status(const u32 node, u32 *const statu
return -ENODEV;
}
+static inline int zynqmp_pm_start_rpu(const u32 node, const u64 bootaddr)
+{
+ return -ENODEV;
+}
+
+static inline int zynqmp_pm_stop_rpu(const u32 node)
+{
+ return -ENODEV;
+}
+
static inline int zynqmp_pm_set_sd_config(u32 node,
enum pm_sd_config_type config,
u32 value)
base-commit: 721396afea31eac476d88f5db10ba111ba4b8382
--
2.34.1
^ permalink raw reply related
* Re: [PATCH v2] arm64/hw_breakpoint: reject unaligned watchpoints that would truncate BAS
From: Will Deacon @ 2026-06-19 16:36 UTC (permalink / raw)
To: Mark Rutland, Catalin Marinas, Pratyush Anand, Breno Leitao
Cc: kernel-team, Will Deacon, linux-arm-kernel, linux-perf-users,
linux-kernel, clm, leo.bras, kernel-team
In-Reply-To: <20260609-arm64_bas-v2-1-9f34dbbded88@debian.org>
On Tue, 09 Jun 2026 06:15:53 -0700, Breno Leitao wrote:
> hw_breakpoint_arch_parse() positions the BAS bit pattern in
> hw->ctrl.len with
>
> offset = hw->address & alignment_mask; /* 0..7 */
> hw->ctrl.len <<= offset;
>
> ctrl.len is an 8-bit bitfield (struct arch_hw_breakpoint_ctrl::len is
> u32 :8), so the shift silently drops any bits past bit 7. For
> non-compat AArch64 watchpoints the offset is unbounded relative to
> ctrl.len: a perf_event_open(PERF_TYPE_BREAKPOINT) caller asking for
> HW_BREAKPOINT_W with bp_addr=page+1 and bp_len=HW_BREAKPOINT_LEN_8
> ends up with 0xff << 1 = 0x1fe, stored as 0xfe. The kernel programs
> WCR.BAS=0xfe and the hardware watches bytes [1..7] instead of the
> requested [1..8] -- the eighth byte is silently dropped. The
> syscall still returns success, leaving userspace to discover the
> gap by empirical probing.
>
> [...]
Applied to arm64 (for-next/core), thanks!
[1/1] arm64/hw_breakpoint: reject unaligned watchpoints that would truncate BAS
https://git.kernel.org/arm64/c/4cc70f75853b
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev
^ permalink raw reply
* Re: [PATCH] arm64: static_call: include asm/insns.h
From: Will Deacon @ 2026-06-19 16:36 UTC (permalink / raw)
To: Peter Zijlstra, Josh Poimboeuf, Jason Baron, Alice Ryhl,
Catalin Marinas, Ard Biesheuvel, Arnd Bergmann
Cc: kernel-team, Will Deacon, Arnd Bergmann, Steven Rostedt,
linux-arm-kernel, linux-kernel
In-Reply-To: <20260611132149.40873-1-arnd@kernel.org>
On Thu, 11 Jun 2026 15:21:44 +0200, Arnd Bergmann wrote:
> I came a cross a missing declaration in a randconfig build:
>
> arch/arm64/kernel/static_call.c:16:5: error: call to undeclared function 'aarch64_insn_adrp_get_offset'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
> 16 | aarch64_insn_adrp_get_offset(le32_to_cpup(tramp + 4)) +
> | ^
>
> Include the header that contains this definition explicitly,
> rather than relying on it to come indirectly through another
> header.
>
> [...]
Applied to arm64 (for-next/core), thanks!
[1/1] arm64: static_call: include asm/insns.h
https://git.kernel.org/arm64/c/998d4d789d2d
Cheers,
--
Will
https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev
^ permalink raw reply
* Re: [PATCH v6 15/19] drm/connector: Add new atomic_create_state callback
From: Luca Ceresoli @ 2026-06-19 16:24 UTC (permalink / raw)
To: Maxime Ripard, Maarten Lankhorst, Thomas Zimmermann, David Airlie,
Simona Vetter, Jonathan Corbet, Shuah Khan, Dmitry Baryshkov,
Jyri Sarha, Tomi Valkeinen, Andrzej Hajda, Neil Armstrong,
Robert Foss, Laurent Pinchart, Jonas Karlman, Jernej Skrabec,
Simon Ser, Harry Wentland, Melissa Wen, Sebastian Wick, Alex Hung,
Jani Nikula, Rodrigo Vivi, Joonas Lahtinen, Tvrtko Ursulin,
Chen-Yu Tsai, Samuel Holland, Dave Stevenson, Maíra Canal,
Raspberry Pi Kernel Maintenance
Cc: dri-devel, linux-doc, linux-kernel, Daniel Stone, intel-gfx,
intel-xe, linux-arm-kernel, linux-sunxi, Laurent Pinchart
In-Reply-To: <20260526-drm-mode-config-init-v6-15-852346394200@kernel.org>
Hello Maxime, Dmitry, all,
On Tue May 26, 2026 at 6:46 PM CEST, Maxime Ripard wrote:
> Commit 47b5ac7daa46 ("drm/atomic: Add new atomic_create_state callback
> to drm_private_obj") introduced a new pattern for allocating drm object
> states.
>
> Instead of relying on the reset() callback, it created a new
> atomic_create_state hook. This is helpful because reset is a bit
> overloaded: it's used to create the initial software state, reset it,
> but also reset the hardware.
>
> It can also be used either at probe time, to create the initial state
> and possibly reset the hardware to an expected default, but also during
> suspend/resume.
>
> Both these cases come with different expectations too: during the
> initialization, we want to initialize all states, but during
> suspend/resume, drm_private_states for example are expected to be kept
> around.
>
> reset() also isn't fallible, which makes it harder to handle
> initialization errors properly. This is only really relevant for some
> drivers though, since all the helpers for reset only create a new
> state, and don't touch the hardware at all.
>
> It was thus decided to create a new hook that would allocate and
> initialize a pristine state without any side effect:
> atomic_create_state to untangle a bit some of it, and to separate the
> initialization with the actual reset one might need during a
> suspend/resume.
>
> Continue the transition to the new pattern with connectors.
>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Reviewed-by: Thomas Zimmermann <tzimmermann@suse.de>
> Signed-off-by: Maxime Ripard <mripard@kernel.org>
As I'm rebasing another series on current drm-misc-next, which now includes
this patch, I ran into troubles and I'm not sure what is the right thing to
do. I hope you can help me clarify this. See below for my question.
FTR the series I'm rebasing is "drm bridge hotplug", but the question is
not specific to that series.
> --- a/drivers/gpu/drm/drm_connector.c
> +++ b/drivers/gpu/drm/drm_connector.c
> @@ -616,11 +616,19 @@ int drmm_connector_hdmi_init(struct drm_device *dev,
>
> /*
> * drm_connector_attach_max_bpc_property() requires the
> * connector to have a state.
> */
> - if (connector->funcs->reset)
> + if (connector->funcs->atomic_create_state) {
> + struct drm_connector_state *state;
> +
> + state = connector->funcs->atomic_create_state(connector);
> + if (IS_ERR(state))
> + return PTR_ERR(state);
> +
> + connector->state = state;
> + } else if (connector->funcs->reset)
> connector->funcs->reset(connector);
Here a state is added to connector->state, and that's fine.
However non-HDMI connectors don't get a state created by default.
I was hit by this with the drm_bridge_connector which it can add either an
HDMI or a non-HDMI connector [0]. In the former case it calls
drmm_connector_hdmi_init(), which creates the state (in the hunk quoted
above). In the latter case, as I experienced at runtime and confirmed by
code inspection, it does not create a state: no one calls
connector->funcs->atomic_create_state.
I suspect this is related to patch 19/19 which converted the
drm_bridge_connector from drm_atomic_helper_connector_reset() to
drm_atomic_helper_connector_create_state(), and only the former sets
'connector->state = conn_state'.
Generally speaking, looks like a state is created only for HDMI
connectors.
The hardware I have uses the drm_bridge_connector in the non-HDMI case, so
the state is not created and this results in a NULL pointer deref later on,
in my case it's in in drm_atomic_connector_get_property().
Am I missing anything obvious?
For now I've come up with a quick workaround, adding (roughly after
connector init at [1]):
if (!connector->state)
connector->state = drm_bridge_connector_create_state(connector);
I'm not sure which would be the best solution. Maybe taking the whole
atomic_create_state/reset state creation calls [2] from
drmm_connector_hdmi_init() and hoist them up into
drmm_connector_init(), so all connectors benefit?
Let me know what you think.
[0] https://gitlab.freedesktop.org/drm/misc/kernel/-/blob/7a921d111810652672e02c392b35fdcefa4d5030/drivers/gpu/drm/display/drm_bridge_connector.c#L995-1029
[1] https://gitlab.freedesktop.org/drm/misc/kernel/-/blob/7a921d111810652672e02c392b35fdcefa4d5030/drivers/gpu/drm/display/drm_bridge_connector.c#L1030
[2] https://gitlab.freedesktop.org/drm/misc/kernel/-/blob/7a921d111810652672e02c392b35fdcefa4d5030/drivers/gpu/drm/drm_connector.c#L617-631
Kind regards,
Luca
--
Luca Ceresoli, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply
* [PATCH 07/11] ARM: dts: lpc: Remove NOMMU platform support
From: Frank.Li @ 2026-06-19 15:41 UTC (permalink / raw)
To: Arnd Bergmann, Sascha Hauer, Pengutronix Kernel Team,
Stefan Agner, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Russell King, Abel Vesa, Peng Fan,
Michael Turquette, Stephen Boyd, Brian Masney, Dong Aisheng,
Jacky Bai, NXP S32 Linux Team, Linus Walleij, Vladimir Zapolskiy,
Piotr Wojtaszczyk, Kees Cook, Gustavo A. R. Silva
Cc: linux-arm-kernel, imx, devicetree, linux-kernel, linux-clk,
linux-gpio, linux-hardening, Frank Li
In-Reply-To: <20260619-dts_cleanup_arm_mcore-v1-0-0101795a2662@nxp.com>
From: Frank Li <Frank.Li@nxp.com>
Commercial users and hardware vendors migrated to Zephyr or other RTOS
solutions years ago, leaving the NOMMU platform support effectively
unused and unmaintained.
Remove the obsolete support to reduce maintenance burden and simplify the
i.MX platform code.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm/boot/dts/nxp/Makefile | 1 -
arch/arm/boot/dts/nxp/lpc/Makefile | 9 -
arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi | 543 ------------------
arch/arm/boot/dts/nxp/lpc/lpc3250-ea3250.dts | 273 ---------
arch/arm/boot/dts/nxp/lpc/lpc3250-phy3250.dts | 236 --------
arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 540 ------------------
arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dts | 221 --------
arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts | 485 ----------------
arch/arm/boot/dts/nxp/lpc/lpc4350.dtsi | 48 --
.../arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts | 624 ---------------------
arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts | 621 --------------------
arch/arm/boot/dts/nxp/lpc/lpc4357.dtsi | 52 --
12 files changed, 3653 deletions(-)
diff --git a/arch/arm/boot/dts/nxp/Makefile b/arch/arm/boot/dts/nxp/Makefile
index db44e7a0a1983..3ca4c932f3a9c 100644
--- a/arch/arm/boot/dts/nxp/Makefile
+++ b/arch/arm/boot/dts/nxp/Makefile
@@ -1,6 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
subdir-y += imx
-subdir-y += lpc
subdir-y += ls
subdir-y += mxs
subdir-y += vf
diff --git a/arch/arm/boot/dts/nxp/lpc/Makefile b/arch/arm/boot/dts/nxp/lpc/Makefile
deleted file mode 100644
index 56b9a0ebb9179..0000000000000
--- a/arch/arm/boot/dts/nxp/lpc/Makefile
+++ /dev/null
@@ -1,9 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-dtb-$(CONFIG_ARCH_LPC18XX) += \
- lpc4337-ciaa.dtb \
- lpc4350-hitex-eval.dtb \
- lpc4357-ea4357-devkit.dtb \
- lpc4357-myd-lpc4357.dtb
-dtb-$(CONFIG_ARCH_LPC32XX) += \
- lpc3250-ea3250.dtb \
- lpc3250-phy3250.dtb
diff --git a/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi
deleted file mode 100644
index 152e98cf0c4e2..0000000000000
--- a/arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi
+++ /dev/null
@@ -1,543 +0,0 @@
-/*
- * Common base for NXP LPC18xx and LPC43xx devices.
- *
- * Copyright 2015 Joachim Eastwood <manabian@gmail.com>
- *
- * This code is released using a dual license strategy: BSD/GPL
- * You can choose the licence that better fits your requirements.
- *
- * Released under the terms of 3-clause BSD License
- * Released under the terms of GNU General Public License Version 2.0
- *
- */
-
-#include "../../armv7-m.dtsi"
-
-#include "dt-bindings/clock/lpc18xx-cgu.h"
-#include "dt-bindings/clock/lpc18xx-ccu.h"
-
-#define LPC_PIN(port, pin) (0x##port * 32 + pin)
-#define LPC_GPIO(port, pin) (port * 32 + pin)
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- compatible = "arm,cortex-m3";
- device_type = "cpu";
- reg = <0x0>;
- clocks = <&ccu1 CLK_CPU_CORE>;
- };
- };
-
- clocks {
- xtal: xtal {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <12000000>;
- };
-
- xtal32: xtal32 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- };
-
- enet_rx_clk: enet_rx_clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- clock-output-names = "enet_rx_clk";
- };
-
- enet_tx_clk: enet_tx_clk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- clock-output-names = "enet_tx_clk";
- };
-
- gp_clkin: gp_clkin {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- clock-output-names = "gp_clkin";
- };
- };
-
- soc {
- sct_pwm: pwm@40000000 {
- compatible = "nxp,lpc1850-sct-pwm";
- reg = <0x40000000 0x1000>;
- clocks = <&ccu1 CLK_CPU_SCT>;
- clock-names = "pwm";
- resets = <&rgu 37>;
- #pwm-cells = <3>;
- status = "disabled";
- };
-
- dmac: dma-controller@40002000 {
- compatible = "arm,pl080", "arm,primecell";
- arm,primecell-periphid = <0x00041080>;
- reg = <0x40002000 0x1000>;
- interrupts = <2>;
- clocks = <&ccu1 CLK_CPU_DMA>;
- clock-names = "apb_pclk";
- resets = <&rgu 19>;
- #dma-cells = <2>;
- dma-channels = <8>;
- dma-requests = <16>;
- lli-bus-interface-ahb1;
- lli-bus-interface-ahb2;
- mem-bus-interface-ahb1;
- mem-bus-interface-ahb2;
- memcpy-burst-size = <256>;
- memcpy-bus-width = <32>;
- };
-
- spifi: spi@40003000 {
- compatible = "nxp,lpc1773-spifi";
- reg = <0x40003000 0x1000>, <0x14000000 0x4000000>;
- reg-names = "spifi", "flash";
- interrupts = <30>;
- clocks = <&ccu1 CLK_SPIFI>, <&ccu1 CLK_CPU_SPIFI>;
- clock-names = "spifi", "reg";
- #address-cells = <1>;
- #size-cells = <0>;
- resets = <&rgu 53>;
- status = "disabled";
- };
-
- mmcsd: mmc@40004000 {
- compatible = "snps,dw-mshc";
- reg = <0x40004000 0x1000>;
- interrupts = <6>;
- clocks = <&ccu1 CLK_CPU_SDIO>, <&ccu2 CLK_SDIO>;
- clock-names = "biu", "ciu";
- resets = <&rgu 20>;
- status = "disabled";
- };
-
- usb0: usb@40006100 {
- compatible = "nxp,lpc1850-ehci", "generic-ehci";
- reg = <0x40006100 0x100>;
- interrupts = <8>;
- clocks = <&ccu1 CLK_CPU_USB0>;
- resets = <&rgu 17>;
- phys = <&usb0_otg_phy>;
- phy-names = "usb";
- has-transaction-translator;
- status = "disabled";
- };
-
- usb1: usb@40007100 {
- compatible = "nxp,lpc1850-ehci", "generic-ehci";
- reg = <0x40007100 0x100>;
- interrupts = <9>;
- clocks = <&ccu1 CLK_CPU_USB1>;
- resets = <&rgu 18>;
- status = "disabled";
- };
-
- emc: memory-controller@40005000 {
- compatible = "arm,pl172", "arm,primecell";
- reg = <0x40005000 0x1000>;
- clocks = <&ccu1 CLK_CPU_EMCDIV>, <&ccu1 CLK_CPU_EMC>;
- clock-names = "mpmcclk", "apb_pclk";
- resets = <&rgu 21>;
- #address-cells = <2>;
- #size-cells = <1>;
- ranges = <0 0 0x1c000000 0x1000000
- 1 0 0x1d000000 0x1000000
- 2 0 0x1e000000 0x1000000
- 3 0 0x1f000000 0x1000000>;
- status = "disabled";
- };
-
- lcdc: lcd-controller@40008000 {
- compatible = "arm,pl111", "arm,primecell";
- reg = <0x40008000 0x1000>;
- interrupts = <7>;
- interrupt-names = "combined";
- clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>;
- clock-names = "clcdclk", "apb_pclk";
- resets = <&rgu 16>;
- status = "disabled";
- };
-
- eeprom: eeprom@4000e000 {
- compatible = "nxp,lpc1857-eeprom";
- reg = <0x4000e000 0x1000>, <0x20040000 0x4000>;
- reg-names = "reg", "mem";
- clocks = <&ccu1 CLK_CPU_EEPROM>;
- clock-names = "eeprom";
- resets = <&rgu 27>;
- interrupts = <4>;
- status = "disabled";
- };
-
- mac: ethernet@40010000 {
- compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac";
- reg = <0x40010000 0x2000>;
- interrupts = <5>;
- interrupt-names = "macirq";
- clocks = <&ccu1 CLK_CPU_ETHERNET>;
- clock-names = "stmmaceth";
- resets = <&rgu 22>;
- reset-names = "stmmaceth";
- rx-fifo-depth = <256>;
- tx-fifo-depth = <256>;
- snps,pbl = <4>; /* 32 (8x mode) */
- snps,force_thresh_dma_mode;
- status = "disabled";
- };
-
- creg: syscon@40043000 {
- compatible = "nxp,lpc1850-creg", "syscon", "simple-mfd";
- reg = <0x40043000 0x1000>;
- clocks = <&ccu1 CLK_CPU_CREG>;
- resets = <&rgu 5>;
-
- creg_clk: clock-controller {
- compatible = "nxp,lpc1850-creg-clk";
- clocks = <&xtal32>;
- #clock-cells = <1>;
- };
-
- usb0_otg_phy: phy {
- compatible = "nxp,lpc1850-usb-otg-phy";
- clocks = <&ccu1 CLK_USB0>;
- #phy-cells = <0>;
- };
-
- dmamux: dma-mux {
- compatible = "nxp,lpc1850-dmamux";
- #dma-cells = <3>;
- dma-requests = <64>;
- dma-masters = <&dmac>;
- };
- };
-
- rtc: rtc@40046000 {
- compatible = "nxp,lpc1850-rtc", "nxp,lpc1788-rtc";
- reg = <0x40046000 0x1000>;
- interrupts = <47>;
- clocks = <&creg_clk 0>, <&ccu1 CLK_CPU_BUS>;
- clock-names = "rtc", "reg";
- };
-
- cgu: clock-controller@40050000 {
- compatible = "nxp,lpc1850-cgu";
- reg = <0x40050000 0x1000>;
- #clock-cells = <1>;
- clocks = <&xtal>, <&creg_clk 1>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>;
- };
-
- ccu1: clock-controller@40051000 {
- compatible = "nxp,lpc1850-ccu";
- reg = <0x40051000 0x1000>;
- #clock-cells = <1>;
- clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>,
- <&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>,
- <&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>,
- <&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>;
- clock-names = "base_apb3_clk", "base_apb1_clk",
- "base_spifi_clk", "base_cpu_clk",
- "base_periph_clk", "base_usb0_clk",
- "base_usb1_clk", "base_spi_clk";
- };
-
- ccu2: clock-controller@40052000 {
- compatible = "nxp,lpc1850-ccu";
- reg = <0x40052000 0x1000>;
- #clock-cells = <1>;
- clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,
- <&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>,
- <&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>,
- <&cgu BASE_SSP0_CLK>, <&cgu BASE_SDIO_CLK>;
- clock-names = "base_audio_clk", "base_uart3_clk",
- "base_uart2_clk", "base_uart1_clk",
- "base_uart0_clk", "base_ssp1_clk",
- "base_ssp0_clk", "base_sdio_clk";
- };
-
- rgu: reset-controller@40053000 {
- compatible = "nxp,lpc1850-rgu";
- reg = <0x40053000 0x1000>;
- clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_BUS>;
- clock-names = "delay", "reg";
- #reset-cells = <1>;
- };
-
- watchdog@40080000 {
- compatible = "nxp,lpc1850-wwdt";
- reg = <0x40080000 0x24>;
- interrupts = <49>;
- clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_WWDT>;
- clock-names = "wdtclk", "reg";
- };
-
- uart0: serial@40081000 {
- compatible = "nxp,lpc1850-uart", "ns16550a";
- reg = <0x40081000 0x1000>;
- reg-shift = <2>;
- interrupts = <24>;
- clocks = <&ccu2 CLK_APB0_UART0>, <&ccu1 CLK_CPU_UART0>;
- clock-names = "uartclk", "reg";
- resets = <&rgu 44>;
- dmas = <&dmamux 1 1 2
- &dmamux 2 1 2
- &dmamux 11 2 2
- &dmamux 12 2 2>;
- dma-names = "tx", "rx", "tx", "rx";
- status = "disabled";
- };
-
- uart1: serial@40082000 {
- compatible = "nxp,lpc1850-uart", "ns16550a";
- reg = <0x40082000 0x1000>;
- reg-shift = <2>;
- interrupts = <25>;
- clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>;
- clock-names = "uartclk", "reg";
- resets = <&rgu 45>;
- dmas = <&dmamux 3 1 2
- &dmamux 4 1 2>;
- dma-names = "tx", "rx";
- status = "disabled";
- };
-
- ssp0: spi@40083000 {
- compatible = "arm,pl022", "arm,primecell";
- reg = <0x40083000 0x1000>;
- interrupts = <22>;
- clocks = <&ccu2 CLK_APB0_SSP0>, <&ccu1 CLK_CPU_SSP0>;
- clock-names = "sspclk", "apb_pclk";
- resets = <&rgu 50>;
- dmas = <&dmamux 9 0 2
- &dmamux 10 0 2>;
- dma-names = "rx", "tx";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- timer0: timer@40084000 {
- compatible = "nxp,lpc3220-timer";
- reg = <0x40084000 0x1000>;
- interrupts = <12>;
- clocks = <&ccu1 CLK_CPU_TIMER0>;
- clock-names = "timerclk";
- resets = <&rgu 32>;
- };
-
- timer1: timer@40085000 {
- compatible = "nxp,lpc3220-timer";
- reg = <0x40085000 0x1000>;
- interrupts = <13>;
- clocks = <&ccu1 CLK_CPU_TIMER1>;
- clock-names = "timerclk";
- resets = <&rgu 33>;
- };
-
- pinctrl: pinctrl@40086000 {
- compatible = "nxp,lpc1850-scu";
- reg = <0x40086000 0x1000>;
- clocks = <&ccu1 CLK_CPU_SCU>;
- };
-
- i2c0: i2c@400a1000 {
- compatible = "nxp,lpc1788-i2c";
- reg = <0x400a1000 0x1000>;
- interrupts = <18>;
- clocks = <&ccu1 CLK_APB1_I2C0>;
- resets = <&rgu 48>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- can1: can@400a4000 {
- compatible = "bosch,c_can";
- reg = <0x400a4000 0x1000>;
- interrupts = <43>;
- clocks = <&ccu1 CLK_APB1_CAN1>;
- resets = <&rgu 54>;
- status = "disabled";
- };
-
- uart2: serial@400c1000 {
- compatible = "nxp,lpc1850-uart", "ns16550a";
- reg = <0x400c1000 0x1000>;
- reg-shift = <2>;
- interrupts = <26>;
- clocks = <&ccu2 CLK_APB2_UART2>, <&ccu1 CLK_CPU_UART2>;
- clock-names = "uartclk", "reg";
- resets = <&rgu 46>;
- dmas = <&dmamux 5 1 2
- &dmamux 6 1 2>;
- dma-names = "tx", "rx";
- status = "disabled";
- };
-
- uart3: serial@400c2000 {
- compatible = "nxp,lpc1850-uart", "ns16550a";
- reg = <0x400c2000 0x1000>;
- reg-shift = <2>;
- interrupts = <27>;
- clocks = <&ccu2 CLK_APB2_UART3>, <&ccu1 CLK_CPU_UART3>;
- clock-names = "uartclk", "reg";
- resets = <&rgu 47>;
- dmas = <&dmamux 7 1 2
- &dmamux 8 1 2
- &dmamux 13 3 2
- &dmamux 14 3 2>;
- dma-names = "tx", "rx", "rx", "tx";
- status = "disabled";
- };
-
- timer2: timer@400c3000 {
- compatible = "nxp,lpc3220-timer";
- reg = <0x400c3000 0x1000>;
- interrupts = <14>;
- clocks = <&ccu1 CLK_CPU_TIMER2>;
- clock-names = "timerclk";
- resets = <&rgu 34>;
- };
-
- timer3: timer@400c4000 {
- compatible = "nxp,lpc3220-timer";
- reg = <0x400c4000 0x1000>;
- interrupts = <15>;
- clocks = <&ccu1 CLK_CPU_TIMER3>;
- clock-names = "timerclk";
- resets = <&rgu 35>;
- };
-
- ssp1: spi@400c5000 {
- compatible = "arm,pl022", "arm,primecell";
- reg = <0x400c5000 0x1000>;
- interrupts = <23>;
- clocks = <&ccu2 CLK_APB2_SSP1>, <&ccu1 CLK_CPU_SSP1>;
- clock-names = "sspclk", "apb_pclk";
- resets = <&rgu 51>;
- dmas = <&dmamux 11 2 2
- &dmamux 12 2 2
- &dmamux 3 3 2
- &dmamux 4 3 2
- &dmamux 5 2 2
- &dmamux 6 2 2
- &dmamux 13 2 2
- &dmamux 14 2 2>;
- dma-names = "rx", "tx", "tx", "rx",
- "tx", "rx", "rx", "tx";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c1: i2c@400e0000 {
- compatible = "nxp,lpc1788-i2c";
- reg = <0x400e0000 0x1000>;
- interrupts = <19>;
- clocks = <&ccu1 CLK_APB3_I2C1>;
- resets = <&rgu 49>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- dac: dac@400e1000 {
- compatible = "nxp,lpc1850-dac";
- reg = <0x400e1000 0x1000>;
- interrupts = <0>;
- clocks = <&ccu1 CLK_APB3_DAC>;
- resets = <&rgu 42>;
- status = "disabled";
- };
-
- can0: can@400e2000 {
- compatible = "bosch,c_can";
- reg = <0x400e2000 0x1000>;
- interrupts = <51>;
- clocks = <&ccu1 CLK_APB3_CAN0>;
- resets = <&rgu 55>;
- status = "disabled";
- };
-
- adc0: adc@400e3000 {
- compatible = "nxp,lpc1850-adc";
- reg = <0x400e3000 0x1000>;
- interrupts = <17>;
- clocks = <&ccu1 CLK_APB3_ADC0>;
- resets = <&rgu 40>;
- status = "disabled";
- };
-
- adc1: adc@400e4000 {
- compatible = "nxp,lpc1850-adc";
- reg = <0x400e4000 0x1000>;
- interrupts = <21>;
- clocks = <&ccu1 CLK_APB3_ADC1>;
- resets = <&rgu 41>;
- status = "disabled";
- };
-
- gpio: gpio@400f4000 {
- compatible = "nxp,lpc1850-gpio";
- reg = <0x400f4000 0x4000>;
- clocks = <&ccu1 CLK_CPU_GPIO>;
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pinctrl LPC_GPIO(0,0) LPC_PIN(0,0) 2>,
- <&pinctrl LPC_GPIO(0,4) LPC_PIN(1,0) 1>,
- <&pinctrl LPC_GPIO(0,8) LPC_PIN(1,1) 4>,
- <&pinctrl LPC_GPIO(1,8) LPC_PIN(1,5) 2>,
- <&pinctrl LPC_GPIO(1,0) LPC_PIN(1,7) 8>,
- <&pinctrl LPC_GPIO(0,2) LPC_PIN(1,15) 2>,
- <&pinctrl LPC_GPIO(0,12) LPC_PIN(1,17) 2>,
- <&pinctrl LPC_GPIO(0,15) LPC_PIN(1,20) 1>,
- <&pinctrl LPC_GPIO(5,0) LPC_PIN(2,0) 7>,
- <&pinctrl LPC_GPIO(0,7) LPC_PIN(2,7) 1>,
- <&pinctrl LPC_GPIO(5,7) LPC_PIN(2,8) 1>,
- <&pinctrl LPC_GPIO(1,10) LPC_PIN(2,9) 1>,
- <&pinctrl LPC_GPIO(0,14) LPC_PIN(2,10) 1>,
- <&pinctrl LPC_GPIO(1,11) LPC_PIN(2,11) 3>,
- <&pinctrl LPC_GPIO(5,8) LPC_PIN(3,1) 2>,
- <&pinctrl LPC_GPIO(1,14) LPC_PIN(3,4) 2>,
- <&pinctrl LPC_GPIO(0,6) LPC_PIN(3,6) 1>,
- <&pinctrl LPC_GPIO(5,10) LPC_PIN(3,7) 2>,
- <&pinctrl LPC_GPIO(2,0) LPC_PIN(4,0) 7>,
- <&pinctrl LPC_GPIO(5,12) LPC_PIN(4,8) 3>,
- <&pinctrl LPC_GPIO(2,9) LPC_PIN(5,0) 7>,
- <&pinctrl LPC_GPIO(2,7) LPC_PIN(5,7) 1>,
- <&pinctrl LPC_GPIO(3,0) LPC_PIN(6,1) 5>,
- <&pinctrl LPC_GPIO(0,5) LPC_PIN(6,6) 1>,
- <&pinctrl LPC_GPIO(5,15) LPC_PIN(6,7) 2>,
- <&pinctrl LPC_GPIO(3,5) LPC_PIN(6,9) 3>,
- <&pinctrl LPC_GPIO(2,8) LPC_PIN(6,12) 1>,
- <&pinctrl LPC_GPIO(3,8) LPC_PIN(7,0) 8>,
- <&pinctrl LPC_GPIO(4,0) LPC_PIN(8,0) 8>,
- <&pinctrl LPC_GPIO(4,12) LPC_PIN(9,0) 4>,
- <&pinctrl LPC_GPIO(5,17) LPC_PIN(9,4) 2>,
- <&pinctrl LPC_GPIO(4,11) LPC_PIN(9,6) 1>,
- <&pinctrl LPC_GPIO(4,8) LPC_PIN(a,1) 3>,
- <&pinctrl LPC_GPIO(5,19) LPC_PIN(a,4) 1>,
- <&pinctrl LPC_GPIO(5,20) LPC_PIN(b,0) 7>,
- <&pinctrl LPC_GPIO(6,0) LPC_PIN(c,1) 14>,
- <&pinctrl LPC_GPIO(6,14) LPC_PIN(d,0) 17>,
- <&pinctrl LPC_GPIO(7,0) LPC_PIN(e,0) 16>,
- <&pinctrl LPC_GPIO(7,16) LPC_PIN(f,1) 3>,
- <&pinctrl LPC_GPIO(7,19) LPC_PIN(f,5) 7>;
- };
- };
-};
-
-&nvic {
- arm,num-irq-priority-bits = <3>;
-};
diff --git a/arch/arm/boot/dts/nxp/lpc/lpc3250-ea3250.dts b/arch/arm/boot/dts/nxp/lpc/lpc3250-ea3250.dts
deleted file mode 100644
index 837a3cfa8e7c8..0000000000000
--- a/arch/arm/boot/dts/nxp/lpc/lpc3250-ea3250.dts
+++ /dev/null
@@ -1,273 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * Embedded Artists LPC3250 board
- *
- * Copyright 2012 Roland Stigge <stigge@antcom.de>
- */
-
-/dts-v1/;
-#include "lpc32xx.dtsi"
-
-/ {
- model = "Embedded Artists LPC3250 board based on NXP LPC3250";
- compatible = "ea,ea3250", "nxp,lpc3250";
-
- memory@80000000 {
- device_type = "memory";
- reg = <0x80000000 0x4000000>;
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- autorepeat;
-
- button {
- label = "Interrupt Key";
- linux,code = <103>;
- gpios = <&gpio 4 1 0>; /* GPI_P3 1 */
- };
-
- key-1 {
- label = "KEY1";
- linux,code = <1>;
- gpios = <&pca9532 0 0>;
- };
-
- key-2 {
- label = "KEY2";
- linux,code = <2>;
- gpios = <&pca9532 1 0>;
- };
-
- key-3 {
- label = "KEY3";
- linux,code = <3>;
- gpios = <&pca9532 2 0>;
- };
-
- key-4 {
- label = "KEY4";
- linux,code = <4>;
- gpios = <&pca9532 3 0>;
- };
-
- key-joy0 {
- label = "Joystick Key 0";
- linux,code = <10>;
- gpios = <&gpio 2 0 0>; /* P2.0 */
- };
-
- key-joy1 {
- label = "Joystick Key 1";
- linux,code = <11>;
- gpios = <&gpio 2 1 0>; /* P2.1 */
- };
-
- key-joy2 {
- label = "Joystick Key 2";
- linux,code = <12>;
- gpios = <&gpio 2 2 0>; /* P2.2 */
- };
-
- key-joy3 {
- label = "Joystick Key 3";
- linux,code = <13>;
- gpios = <&gpio 2 3 0>; /* P2.3 */
- };
-
- key-joy4 {
- label = "Joystick Key 4";
- linux,code = <14>;
- gpios = <&gpio 2 4 0>; /* P2.4 */
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- /* LEDs on OEM Board */
-
- led1 {
- gpios = <&gpio 5 14 1>; /* GPO_P3 14, GPIO 93, active low */
- linux,default-trigger = "timer";
- default-state = "off";
- };
-
- led2 {
- gpios = <&gpio 2 10 1>; /* P2.10, active low */
- default-state = "off";
- };
-
- led3 {
- gpios = <&gpio 2 11 1>; /* P2.11, active low */
- default-state = "off";
- };
-
- led4 {
- gpios = <&gpio 2 12 1>; /* P2.12, active low */
- default-state = "off";
- };
-
- /* LEDs on Base Board */
-
- lede1 {
- gpios = <&pca9532 8 0>;
- default-state = "off";
- };
- lede2 {
- gpios = <&pca9532 9 0>;
- default-state = "off";
- };
- lede3 {
- gpios = <&pca9532 10 0>;
- default-state = "off";
- };
- lede4 {
- gpios = <&pca9532 11 0>;
- default-state = "off";
- };
- lede5 {
- gpios = <&pca9532 12 0>;
- default-state = "off";
- };
- lede6 {
- gpios = <&pca9532 13 0>;
- default-state = "off";
- };
- lede7 {
- gpios = <&pca9532 14 0>;
- default-state = "off";
- };
- lede8 {
- gpios = <&pca9532 15 0>;
- default-state = "off";
- };
- };
-};
-
-/* 3-axis accelerometer X,Y,Z (or AD-IN instead of Z) */
-&adc {
- status = "okay";
-};
-
-&i2c1 {
- clock-frequency = <100000>;
-
- uda1380: uda1380@18 {
- compatible = "nxp,uda1380";
- reg = <0x18>;
- power-gpio = <&gpio 3 10 0>;
- reset-gpio = <&gpio 3 2 0>;
- dac-clk = "wspll";
- };
-
- eeprom@50 {
- compatible = "atmel,24c256";
- reg = <0x50>;
- };
-
- eeprom@57 {
- compatible = "atmel,24c64";
- reg = <0x57>;
- };
-
- pca9532: pca9532@60 {
- compatible = "nxp,pca9532";
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x60>;
- };
-};
-
-&i2c2 {
- clock-frequency = <100000>;
-};
-
-&i2cusb {
- clock-frequency = <100000>;
-
- isp1301: usb-transceiver@2d {
- compatible = "nxp,isp1301";
- reg = <0x2d>;
- };
-};
-
-&mac {
- phy-mode = "rmii";
- use-iram;
- status = "okay";
-};
-
-/* Here, choose exactly one from: ohci, usbd */
-&ohci /* &usbd */ {
- transceiver = <&isp1301>;
- status = "okay";
-};
-
-&sd {
- wp-gpios = <&pca9532 5 0>;
- cd-gpios = <&pca9532 4 0>;
- cd-inverted;
- bus-width = <4>;
- status = "okay";
-};
-
-/* 128MB Flash via SLC NAND controller */
-&slc {
- status = "okay";
-
- nxp,wdr-clks = <14>;
- nxp,wwidth = <260000000>;
- nxp,whold = <104000000>;
- nxp,wsetup = <200000000>;
- nxp,rdr-clks = <14>;
- nxp,rwidth = <34666666>;
- nxp,rhold = <104000000>;
- nxp,rsetup = <200000000>;
- nand-on-flash-bbt;
- gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- mtd0@0 {
- label = "ea3250-boot";
- reg = <0x00000000 0x00080000>;
- read-only;
- };
-
- mtd1@80000 {
- label = "ea3250-uboot";
- reg = <0x00080000 0x000c0000>;
- read-only;
- };
-
- mtd2@140000 {
- label = "ea3250-kernel";
- reg = <0x00140000 0x00400000>;
- };
-
- mtd3@540000 {
- label = "ea3250-rootfs";
- reg = <0x00540000 0x07ac0000>;
- };
- };
-};
-
-&uart1 {
- status = "okay";
-};
-
-&uart3 {
- status = "okay";
-};
-
-&uart5 {
- status = "okay";
-};
-
-&uart6 {
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/nxp/lpc/lpc3250-phy3250.dts b/arch/arm/boot/dts/nxp/lpc/lpc3250-phy3250.dts
deleted file mode 100644
index 0f96ea0337a1f..0000000000000
--- a/arch/arm/boot/dts/nxp/lpc/lpc3250-phy3250.dts
+++ /dev/null
@@ -1,236 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * PHYTEC phyCORE-LPC3250 board
- *
- * Copyright (C) 2015-2019 Vladimir Zapolskiy <vz@mleia.com>
- * Copyright 2012 Roland Stigge <stigge@antcom.de>
- */
-
-/dts-v1/;
-#include "lpc32xx.dtsi"
-
-/ {
- model = "PHYTEC phyCORE-LPC3250 board based on NXP LPC3250";
- compatible = "phytec,phy3250", "nxp,lpc3250";
-
- memory@80000000 {
- device_type = "memory";
- reg = <0x80000000 0x4000000>;
- };
-
- leds {
- compatible = "gpio-leds";
-
- led0 { /* red */
- gpios = <&gpio 5 1 0>; /* GPO_P3 1, GPIO 80, active high */
- default-state = "off";
- };
-
- led1 { /* green */
- gpios = <&gpio 5 14 0>; /* GPO_P3 14, GPIO 93, active high */
- linux,default-trigger = "heartbeat";
- };
- };
-
- panel: panel {
- compatible = "sharp,lq035q7db03";
- power-supply = <®_lcd>;
-
- port {
- panel_input: endpoint {
- remote-endpoint = <&cldc_output>;
- };
- };
- };
-
- reg_backlight: regulator-backlight {
- compatible = "regulator-fixed";
- regulator-name = "backlight";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- gpio = <&gpio 5 4 0>;
- enable-active-high;
- regulator-boot-on;
- };
-
- reg_lcd: regulator-lcd {
- compatible = "regulator-fixed";
- regulator-name = "lcd";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- gpio = <&gpio 5 0 0>;
- enable-active-high;
- regulator-boot-on;
- };
-
- reg_sd: regulator-sd {
- compatible = "regulator-fixed";
- regulator-name = "sd";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio 5 5 0>;
- enable-active-high;
- regulator-boot-on;
- };
-};
-
-&clcd {
- max-memory-bandwidth = <18710000>;
- status = "okay";
-
- port {
- cldc_output: endpoint {
- remote-endpoint = <&panel_input>;
- arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
- };
- };
-};
-
-&i2c1 {
- clock-frequency = <100000>;
-
- uda1380: uda1380@18 {
- compatible = "nxp,uda1380";
- reg = <0x18>;
- power-gpio = <&gpio 3 10 0>;
- reset-gpio = <&gpio 3 2 0>;
- dac-clk = "wspll";
- };
-
- pcf8563: rtc@51 {
- compatible = "nxp,pcf8563";
- reg = <0x51>;
- };
-};
-
-&i2c2 {
- clock-frequency = <100000>;
-};
-
-&i2cusb {
- clock-frequency = <100000>;
-
- isp1301: usb-transceiver@2c {
- compatible = "nxp,isp1301";
- reg = <0x2c>;
- };
-};
-
-&key {
- keypad,num-rows = <1>;
- keypad,num-columns = <1>;
- nxp,debounce-delay-ms = <3>;
- nxp,scan-delay-ms = <34>;
- linux,keymap = <0x00000002>;
- status = "okay";
-};
-
-&mac {
- phy-mode = "rmii";
- use-iram;
- status = "okay";
-};
-
-/* Here, choose exactly one from: ohci, usbd */
-&ohci /* &usbd */ {
- transceiver = <&isp1301>;
- status = "okay";
-};
-
-&sd {
- wp-gpios = <&gpio 3 0 0>;
- cd-gpios = <&gpio 3 1 0>;
- cd-inverted;
- bus-width = <4>;
- vmmc-supply = <®_sd>;
- status = "okay";
-};
-
-/* 64MB Flash via SLC NAND controller */
-&slc {
- status = "okay";
-
- nxp,wdr-clks = <14>;
- nxp,wwidth = <40000000>;
- nxp,whold = <100000000>;
- nxp,wsetup = <100000000>;
- nxp,rdr-clks = <14>;
- nxp,rwidth = <40000000>;
- nxp,rhold = <66666666>;
- nxp,rsetup = <100000000>;
- nand-on-flash-bbt;
- gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- mtd0@0 {
- label = "phy3250-boot";
- reg = <0x00000000 0x00064000>;
- read-only;
- };
-
- mtd1@64000 {
- label = "phy3250-uboot";
- reg = <0x00064000 0x00190000>;
- read-only;
- };
-
- mtd2@1f4000 {
- label = "phy3250-ubt-prms";
- reg = <0x001f4000 0x00010000>;
- };
-
- mtd3@204000 {
- label = "phy3250-kernel";
- reg = <0x00204000 0x00400000>;
- };
-
- mtd4@604000 {
- label = "phy3250-rootfs";
- reg = <0x00604000 0x039fc000>;
- };
- };
-};
-
-&ssp0 {
- num-cs = <1>;
- cs-gpios = <&gpio 3 5 0>;
- status = "okay";
-
- eeprom: eeprom@0 {
- compatible = "atmel,at25";
- reg = <0>;
- spi-max-frequency = <5000000>;
-
- pl022,interface = <0>;
- pl022,com-mode = <0>;
- pl022,rx-level-trig = <1>;
- pl022,tx-level-trig = <1>;
- pl022,ctrl-len = <11>;
- pl022,wait-state = <0>;
- pl022,duplex = <0>;
-
- size = <0x8000>;
- address-width = <16>;
- pagesize = <64>;
- };
-};
-
-&tsc {
- status = "okay";
-};
-
-&uart2 {
- status = "okay";
-};
-
-&uart3 {
- status = "okay";
-};
-
-&uart5 {
- status = "okay";
-};
diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi
deleted file mode 100644
index e94df78def18a..0000000000000
--- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi
+++ /dev/null
@@ -1,540 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * NXP LPC32xx SoC
- *
- * Copyright (C) 2015-2019 Vladimir Zapolskiy <vz@mleia.com>
- * Copyright 2012 Roland Stigge <stigge@antcom.de>
- */
-
-#include <dt-bindings/clock/lpc32xx-clock.h>
-#include <dt-bindings/interrupt-controller/irq.h>
-
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "nxp,lpc3220";
- interrupt-parent = <&mic>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- compatible = "arm,arm926ej-s";
- device_type = "cpu";
- reg = <0x0>;
- };
- };
-
- clocks {
- xtal_32k: xtal_32k {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- clock-output-names = "xtal_32k";
- };
-
- xtal: xtal {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <13000000>;
- clock-output-names = "xtal";
- };
- };
-
- ahb {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- ranges = <0x00000000 0x00000000 0x10000000>,
- <0x20000000 0x20000000 0x30000000>,
- <0xe0000000 0xe0000000 0x04000000>;
-
- iram: sram@8000000 {
- compatible = "mmio-sram";
- reg = <0x08000000 0x20000>;
-
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00000000 0x08000000 0x20000>;
- };
-
- /*
- * Enable either SLC or MLC
- */
- slc: nand-controller@20020000 {
- compatible = "nxp,lpc3220-slc";
- reg = <0x20020000 0x1000>;
- interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk LPC32XX_CLK_SLC>;
- dmas = <&dma 1 1>;
- dma-names = "rx-tx";
- status = "disabled";
- };
-
- mlc: nand-controller@200a8000 {
- compatible = "nxp,lpc3220-mlc";
- reg = <0x200a8000 0x11000>;
- interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk LPC32XX_CLK_MLC>;
- dmas = <&dma 12 1>;
- dma-names = "rx-tx";
- status = "disabled";
- };
-
- dma: dma-controller@31000000 {
- compatible = "arm,pl080", "arm,primecell";
- reg = <0x31000000 0x1000>;
- interrupts = <28 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk LPC32XX_CLK_DMA>;
- clock-names = "apb_pclk";
- dma-channels = <8>;
- dma-requests = <16>;
- lli-bus-interface-ahb1;
- lli-bus-interface-ahb2;
- mem-bus-interface-ahb1;
- mem-bus-interface-ahb2;
- memcpy-burst-size = <256>;
- memcpy-bus-width = <32>;
- #dma-cells = <2>;
- };
-
- /*
- * Enable either ohci or usbd (gadget)!
- */
- ohci: usb@31020000 {
- compatible = "nxp,ohci-nxp", "usb-ohci";
- reg = <0x31020000 0x300>;
- interrupt-parent = <&sic1>;
- interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&usbclk LPC32XX_USB_CLK_HOST>;
- status = "disabled";
- };
-
- usbd: usbd@31020000 {
- compatible = "nxp,lpc3220-udc";
- reg = <0x31020000 0x300>;
- interrupt-parent = <&sic1>;
- interrupts = <29 IRQ_TYPE_LEVEL_HIGH>,
- <30 IRQ_TYPE_LEVEL_HIGH>,
- <28 IRQ_TYPE_LEVEL_HIGH>,
- <26 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&usbclk LPC32XX_USB_CLK_DEVICE>;
- status = "disabled";
- };
-
- i2cusb: i2c@31020300 {
- compatible = "nxp,pnx-i2c";
- reg = <0x31020300 0x100>;
- interrupt-parent = <&sic1>;
- interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&usbclk LPC32XX_USB_CLK_I2C>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- usbclk: clock-controller@31020f00 {
- compatible = "nxp,lpc3220-usb-clk";
- reg = <0x31020f00 0x100>;
- #clock-cells = <1>;
- };
-
- clcd: clcd@31040000 {
- compatible = "arm,pl111", "arm,primecell";
- reg = <0x31040000 0x1000>;
- interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk LPC32XX_CLK_LCD>, <&clk LPC32XX_CLK_LCD>;
- clock-names = "clcdclk", "apb_pclk";
- status = "disabled";
- };
-
- mac: ethernet@31060000 {
- compatible = "nxp,lpc-eth";
- reg = <0x31060000 0x1000>;
- interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk LPC32XX_CLK_MAC>;
- status = "disabled";
- };
-
- emc: memory-controller@31080000 {
- compatible = "arm,pl175", "arm,primecell";
- reg = <0x31080000 0x1000>;
- clocks = <&clk LPC32XX_CLK_DDRAM>, <&clk LPC32XX_CLK_DDRAM>;
- clock-names = "mpmcclk", "apb_pclk";
- #address-cells = <1>;
- #size-cells = <1>;
-
- ranges = <0 0xe0000000 0x01000000>,
- <1 0xe1000000 0x01000000>,
- <2 0xe2000000 0x01000000>,
- <3 0xe3000000 0x01000000>;
- status = "disabled";
- };
-
- apb {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- ranges = <0x20000000 0x20000000 0x30000000>;
-
- /*
- * ssp0 and spi1 are shared pins;
- * enable one in your board dts, as needed.
- */
- ssp0: spi@20084000 {
- compatible = "arm,pl022", "arm,primecell";
- reg = <0x20084000 0x1000>;
- interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk LPC32XX_CLK_SSP0>, <&clk LPC32XX_CLK_SSP0>;
- clock-names = "sspclk", "apb_pclk";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- spi1: spi@20088000 {
- compatible = "nxp,lpc3220-spi";
- reg = <0x20088000 0x1000>;
- clocks = <&clk LPC32XX_CLK_SPI1>;
- dmas = <&dmamux 11 1 0>;
- dma-names = "rx-tx";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- /*
- * ssp1 and spi2 are shared pins;
- * enable one in your board dts, as needed.
- */
- ssp1: spi@2008c000 {
- compatible = "arm,pl022", "arm,primecell";
- reg = <0x2008c000 0x1000>;
- interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk LPC32XX_CLK_SSP1>, <&clk LPC32XX_CLK_SSP1>;
- clock-names = "sspclk", "apb_pclk";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- spi2: spi@20090000 {
- compatible = "nxp,lpc3220-spi";
- reg = <0x20090000 0x1000>;
- clocks = <&clk LPC32XX_CLK_SPI2>;
- dmas = <&dmamux 3 1 0>;
- dma-names = "rx-tx";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2s0: i2s@20094000 {
- compatible = "nxp,lpc3220-i2s";
- reg = <0x20094000 0x1000>;
- interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk LPC32XX_CLK_I2S0>;
- dmas = <&dma 0 1>, <&dma 13 1>;
- dma-names = "rx", "tx";
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- sd: mmc@20098000 {
- compatible = "arm,pl180", "arm,primecell";
- reg = <0x20098000 0x1000>;
- interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
- <13 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk LPC32XX_CLK_SD>;
- clock-names = "apb_pclk";
- status = "disabled";
- };
-
- i2s1: i2s@2009c000 {
- compatible = "nxp,lpc3220-i2s";
- reg = <0x2009c000 0x1000>;
- interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk LPC32XX_CLK_I2S1>;
- dmas = <&dma 2 1>, <&dmamux 10 1 1>;
- dma-names = "rx", "tx";
- #sound-dai-cells = <0>;
- status = "disabled";
- };
-
- /* UART5 first since it is the default console, ttyS0 */
- uart5: serial@40090000 {
- /* actually, ns16550a w/ 64 byte fifos! */
- compatible = "nxp,lpc3220-uart";
- reg = <0x40090000 0x1000>;
- interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- clocks = <&clk LPC32XX_CLK_UART5>;
- status = "disabled";
- };
-
- uart3: serial@40080000 {
- compatible = "nxp,lpc3220-uart";
- reg = <0x40080000 0x1000>;
- interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- clocks = <&clk LPC32XX_CLK_UART3>;
- status = "disabled";
- };
-
- uart4: serial@40088000 {
- compatible = "nxp,lpc3220-uart";
- reg = <0x40088000 0x1000>;
- interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- clocks = <&clk LPC32XX_CLK_UART4>;
- status = "disabled";
- };
-
- uart6: serial@40098000 {
- compatible = "nxp,lpc3220-uart";
- reg = <0x40098000 0x1000>;
- interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- clocks = <&clk LPC32XX_CLK_UART6>;
- status = "disabled";
- };
-
- i2c1: i2c@400a0000 {
- compatible = "nxp,pnx-i2c";
- reg = <0x400a0000 0x100>;
- interrupt-parent = <&sic1>;
- interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clk LPC32XX_CLK_I2C1>;
- };
-
- i2c2: i2c@400a8000 {
- compatible = "nxp,pnx-i2c";
- reg = <0x400a8000 0x100>;
- interrupt-parent = <&sic1>;
- interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clk LPC32XX_CLK_I2C2>;
- };
-
- mpwm: pwm@400e8000 {
- compatible = "nxp,lpc3220-motor-pwm";
- reg = <0x400e8000 0x78>;
- interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&clk LPC32XX_CLK_MCPWM>;
- #pwm-cells = <3>;
- status = "disabled";
- };
- };
-
- fab {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "simple-bus";
- ranges = <0x20000000 0x20000000 0x30000000>;
-
- /* System Control Block */
- syscon@40004000 {
- compatible = "nxp,lpc3220-scb", "syscon", "simple-mfd";
- reg = <0x40004000 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x40004000 0x1000>;
-
- clk: clock-controller@0 {
- compatible = "nxp,lpc3220-clk";
- reg = <0x00 0x114>;
- #clock-cells = <1>;
- clocks = <&xtal_32k>, <&xtal>;
- clock-names = "xtal_32k", "xtal";
- };
-
- dmamux: dma-router@78 {
- compatible = "nxp,lpc3220-dmamux";
- reg = <0x78 0x8>;
- dma-masters = <&dma>;
- #dma-cells = <3>;
- };
- };
-
- mic: interrupt-controller@40008000 {
- compatible = "nxp,lpc3220-mic";
- reg = <0x40008000 0x4000>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
-
- sic1: interrupt-controller@4000c000 {
- compatible = "nxp,lpc3220-sic";
- reg = <0x4000c000 0x4000>;
- interrupt-controller;
- #interrupt-cells = <2>;
-
- interrupt-parent = <&mic>;
- interrupts = <0 IRQ_TYPE_LEVEL_LOW>,
- <30 IRQ_TYPE_LEVEL_LOW>;
- };
-
- sic2: interrupt-controller@40010000 {
- compatible = "nxp,lpc3220-sic";
- reg = <0x40010000 0x4000>;
- interrupt-controller;
- #interrupt-cells = <2>;
-
- interrupt-parent = <&mic>;
- interrupts = <1 IRQ_TYPE_LEVEL_LOW>,
- <31 IRQ_TYPE_LEVEL_LOW>;
- };
-
- uart1: serial@40014000 {
- compatible = "nxp,lpc3220-hsuart";
- reg = <0x40014000 0x1000>;
- interrupts = <26 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- uart2: serial@40018000 {
- compatible = "nxp,lpc3220-hsuart";
- reg = <0x40018000 0x1000>;
- interrupts = <25 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- uart7: serial@4001c000 {
- compatible = "nxp,lpc3220-hsuart";
- reg = <0x4001c000 0x1000>;
- interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- rtc: rtc@40024000 {
- compatible = "nxp,lpc3220-rtc";
- reg = <0x40024000 0x1000>;
- interrupt-parent = <&sic1>;
- interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk LPC32XX_CLK_RTC>;
- };
-
- gpio: gpio@40028000 {
- compatible = "nxp,lpc3220-gpio";
- reg = <0x40028000 0x1000>;
- gpio-controller;
- #gpio-cells = <3>; /* bank, pin, flags */
- };
-
- timer4: timer@4002c000 {
- compatible = "nxp,lpc3220-timer";
- reg = <0x4002c000 0x1000>;
- interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&clk LPC32XX_CLK_TIMER4>;
- clock-names = "timerclk";
- status = "disabled";
- };
-
- timer5: timer@40030000 {
- compatible = "nxp,lpc3220-timer";
- reg = <0x40030000 0x1000>;
- interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&clk LPC32XX_CLK_TIMER5>;
- clock-names = "timerclk";
- status = "disabled";
- };
-
- watchdog: watchdog@4003c000 {
- compatible = "nxp,pnx4008-wdt";
- reg = <0x4003c000 0x1000>;
- clocks = <&clk LPC32XX_CLK_WDOG>;
- };
-
- timer0: timer@40044000 {
- compatible = "nxp,lpc3220-timer";
- reg = <0x40044000 0x1000>;
- clocks = <&clk LPC32XX_CLK_TIMER0>;
- clock-names = "timerclk";
- interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
- };
-
- /*
- * TSC vs. ADC: Since those two share the same
- * hardware, you need to choose from one of the
- * following two and do 'status = "okay";' for one of
- * them
- */
-
- adc: adc@40048000 {
- compatible = "nxp,lpc3220-adc";
- reg = <0x40048000 0x1000>;
- interrupt-parent = <&sic1>;
- interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk LPC32XX_CLK_ADC>;
- status = "disabled";
- };
-
- tsc: tsc@40048000 {
- compatible = "nxp,lpc3220-tsc";
- reg = <0x40048000 0x1000>;
- interrupt-parent = <&sic1>;
- interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk LPC32XX_CLK_ADC>;
- status = "disabled";
- };
-
- timer1: timer@4004c000 {
- compatible = "nxp,lpc3220-timer";
- reg = <0x4004c000 0x1000>;
- interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&clk LPC32XX_CLK_TIMER1>;
- clock-names = "timerclk";
- };
-
- key: key@40050000 {
- compatible = "nxp,lpc3220-key";
- reg = <0x40050000 0x1000>;
- clocks = <&clk LPC32XX_CLK_KEY>;
- interrupt-parent = <&sic1>;
- interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- timer2: timer@40058000 {
- compatible = "nxp,lpc3220-timer";
- reg = <0x40058000 0x1000>;
- interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&clk LPC32XX_CLK_TIMER2>;
- clock-names = "timerclk";
- status = "disabled";
- };
-
- pwm1: pwm@4005c000 {
- compatible = "nxp,lpc3220-pwm";
- reg = <0x4005c000 0x4>;
- clocks = <&clk LPC32XX_CLK_PWM1>;
- #pwm-cells = <3>;
- assigned-clocks = <&clk LPC32XX_CLK_PWM1>;
- assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>;
- status = "disabled";
- };
-
- pwm2: pwm@4005c004 {
- compatible = "nxp,lpc3220-pwm";
- reg = <0x4005c004 0x4>;
- clocks = <&clk LPC32XX_CLK_PWM2>;
- #pwm-cells = <3>;
- assigned-clocks = <&clk LPC32XX_CLK_PWM2>;
- assigned-clock-parents = <&clk LPC32XX_CLK_PERIPH>;
- status = "disabled";
- };
-
- timer3: timer@40060000 {
- compatible = "nxp,lpc3220-timer";
- reg = <0x40060000 0x1000>;
- interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&clk LPC32XX_CLK_TIMER3>;
- clock-names = "timerclk";
- status = "disabled";
- };
- };
- };
-};
diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dts b/arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dts
deleted file mode 100644
index 5ff43c825944d..0000000000000
--- a/arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dts
+++ /dev/null
@@ -1,221 +0,0 @@
-/*
- * CIAA NXP LPC4337 (http://www.proyecto-ciaa.com.ar)
- *
- * Copyright (C) 2015 VanguardiaSur - www.vanguardiasur.com.ar
- *
- * This code is released using a dual license strategy: BSD/GPL
- * You can choose the licence that better fits your requirements.
- *
- * Released under the terms of 3-clause BSD License
- * Released under the terms of GNU General Public License Version 2.0
- */
-/dts-v1/;
-
-#include "lpc18xx.dtsi"
-#include "lpc4357.dtsi"
-
-#include "dt-bindings/gpio/gpio.h"
-
-/ {
- model = "CIAA NXP LPC4337";
- compatible = "ciaa,lpc4337", "nxp,lpc4337", "nxp,lpc4350";
-
- aliases {
- serial0 = &uart2;
- serial1 = &uart3;
- };
-
- chosen {
- bootargs = "console=ttyS0,115200 earlyprintk";
- stdout-path = &uart2;
- };
-
- memory@28000000 {
- device_type = "memory";
- reg = <0x28000000 0x0800000>; /* 8 MB */
- };
-};
-
-&pinctrl {
- enet_rmii_pins: enet-rmii-pins {
- enet_rmii_rxd_cfg {
- pins = "p1_15", "p0_0";
- function = "enet";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- enet_rmii_txd_cfg {
- pins = "p1_18", "p1_20";
- function = "enet";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- enet_rmii_rx_dv_cfg {
- pins = "p1_16";
- function = "enet";
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- enet_rmii_tx_en_cfg {
- pins = "p0_1";
- function = "enet";
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- enet_ref_clk_cfg {
- pins = "p1_19";
- function = "enet";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- enet_mdio_cfg {
- pins = "p1_17";
- function = "enet";
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- enet_mdc_cfg {
- pins = "p7_7";
- function = "enet";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
- };
-
- i2c0_pins: i2c0-pins {
- i2c0_pins_cfg {
- pins = "i2c0_scl", "i2c0_sda";
- function = "i2c0";
- input-enable;
- };
- };
-
- ssp_pins: ssp-pins {
- ssp1_cs_cfg {
- pins = "p6_7";
- function = "gpio";
- bias-pull-up;
- bias-disable;
- };
-
- ssp1_miso_mosi_cfg {
- pins = "p1_3", "p1_4";
- function = "ssp1";
- slew-rate = <1>;
- bias-pull-down;
- input-enable;
- input-schmitt-disable;
- };
-
- ssp1_sck_cfg {
- pins = "pf_4";
- function = "ssp1";
- slew-rate = <1>;
- bias-disable;
- };
- };
-
- uart2_pins: uart2-pins {
- uart2_rx_cfg {
- pins = "p7_2";
- function = "uart2";
- bias-disable;
- input-enable;
- };
-
- uart2_tx_cfg {
- pins = "p7_1";
- function = "uart2";
- bias-disable;
- };
- };
-
- uart3_pins: uart3-pins {
- uart3_rx_cfg {
- pins = "p2_4";
- function = "uart3";
- bias-disable;
- input-enable;
- };
-
- uart3_tx_cfg {
- pins = "p2_3";
- function = "uart3";
- bias-disable;
- };
- };
-};
-
-&enet_tx_clk {
- clock-frequency = <50000000>;
-};
-
-&i2c0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins>;
- clock-frequency = <400000>;
-
- eeprom@50 {
- compatible = "microchip,24c512", "atmel,24c512";
- reg = <0x50>;
- };
-
- eeprom@51 {
- compatible = "microchip,24c02", "atmel,24c02";
- reg = <0x51>;
- };
-
- eeprom@54 {
- compatible = "microchip,24c512", "atmel,24c512";
- reg = <0x54>;
- };
-};
-
-&mac {
- status = "okay";
- phy-mode = "rmii";
- pinctrl-names = "default";
- pinctrl-0 = <&enet_rmii_pins>;
-};
-
-&sct_pwm {
- status = "okay";
-};
-
-&ssp1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&ssp_pins>;
- cs-gpios = <&gpio LPC_GPIO(5,15) GPIO_ACTIVE_HIGH>;
- num-cs = <1>;
-};
-
-&uart2 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins>;
-};
-
-&uart3 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&uart3_pins>;
-};
diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts b/arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts
deleted file mode 100644
index 18f757c569057..0000000000000
--- a/arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts
+++ /dev/null
@@ -1,485 +0,0 @@
-/*
- * Hitex LPC4350 Evaluation Board
- *
- * Copyright 2015 Ariel D'Alessandro <ariel.dalessandro@gmail.com>
- *
- * This code is released using a dual license strategy: BSD/GPL
- * You can choose the licence that better fits your requirements.
- *
- * Released under the terms of 3-clause BSD License
- * Released under the terms of GNU General Public License Version 2.0
- *
- */
-/dts-v1/;
-
-#include "lpc18xx.dtsi"
-#include "lpc4350.dtsi"
-
-#include "dt-bindings/input/input.h"
-#include "dt-bindings/gpio/gpio.h"
-
-/ {
- model = "Hitex LPC4350 Evaluation Board";
- compatible = "hitex,lpc4350-eval-board", "nxp,lpc4350";
-
- aliases {
- serial0 = &uart0;
- serial1 = &uart1;
- serial2 = &uart2;
- serial3 = &uart3;
- };
-
- chosen {
- stdout-path = &uart0;
- };
-
- memory@28000000 {
- device_type = "memory";
- reg = <0x28000000 0x800000>; /* 8 MB */
- };
-
- pca_buttons {
- compatible = "gpio-keys-polled";
- poll-interval = <100>;
- autorepeat;
-
- button-0 {
- label = "joy:right";
- linux,code = <KEY_RIGHT>;
- gpios = <&pca_gpio 8 GPIO_ACTIVE_LOW>;
- };
-
- button-1 {
- label = "joy:up";
- linux,code = <KEY_UP>;
- gpios = <&pca_gpio 9 GPIO_ACTIVE_LOW>;
- };
-
-
- button-2 {
- label = "joy:enter";
- linux,code = <KEY_ENTER>;
- gpios = <&pca_gpio 10 GPIO_ACTIVE_LOW>;
- };
-
- button-3 {
- label = "joy:left";
- linux,code = <KEY_LEFT>;
- gpios = <&pca_gpio 11 GPIO_ACTIVE_LOW>;
- };
-
- button-4 {
- label = "joy:down";
- linux,code = <KEY_DOWN>;
- gpios = <&pca_gpio 12 GPIO_ACTIVE_LOW>;
- };
-
- button-5 {
- label = "user:sw3";
- linux,code = <KEY_F1>;
- gpios = <&pca_gpio 13 GPIO_ACTIVE_LOW>;
- };
-
- button-6 {
- label = "user:sw4";
- linux,code = <KEY_F2>;
- gpios = <&pca_gpio 14 GPIO_ACTIVE_LOW>;
- };
-
- button-7 {
- label = "user:sw5";
- linux,code = <KEY_F3>;
- gpios = <&pca_gpio 15 GPIO_ACTIVE_LOW>;
- };
- };
-
- pca_leds {
- compatible = "gpio-leds";
-
- led0 {
- label = "ext:led0";
- gpios = <&pca_gpio 0 GPIO_ACTIVE_LOW>;
- linux,default-trigger = "heartbeat";
- };
-
- led1 {
- label = "ext:led1";
- gpios = <&pca_gpio 1 GPIO_ACTIVE_LOW>;
- };
-
- led2 {
- label = "ext:led2";
- gpios = <&pca_gpio 2 GPIO_ACTIVE_LOW>;
- };
-
- led3 {
- label = "ext:led3";
- gpios = <&pca_gpio 3 GPIO_ACTIVE_LOW>;
- };
- };
-
- vcc: vcc_fixed {
- compatible = "regulator-fixed";
- regulator-name = "3v3io";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-};
-
-&pinctrl {
- adc1_pins: adc1-pins {
- adc1_pins_cfg {
- pins = "pf_9";
- function = "adc";
- input-disable;
- bias-disable;
- };
- };
-
- emc_pins: emc-pins {
- emc_addr0_23_cfg {
- pins = "p2_9", "p2_10", "p2_11", "p2_12",
- "p2_13", "p1_0", "p1_1", "p1_2",
- "p2_8", "p2_7", "p2_6", "p2_2",
- "p2_1", "p2_0", "p6_8", "p6_7",
- "pd_16", "pd_15", "pe_0", "pe_1",
- "pe_2", "pe_3", "pe_4", "pa_4";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_data0_15_cfg {
- pins = "p1_7", "p1_8", "p1_9", "p1_10",
- "p1_11", "p1_12", "p1_13", "p1_14",
- "p5_4", "p5_5", "p5_6", "p5_7",
- "p5_0", "p5_1", "p5_2", "p5_3";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_we_oe_cfg {
- pins = "p1_6", "p1_3";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_bls0_3_cfg {
- pins = "p1_4", "p6_6", "pd_13", "pd_10";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_cs0_cs2_cfg {
- pins = "p1_5", "pd_12";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_sdram_dqm0_3_cfg {
- pins = "p6_12", "p6_10", "pd_0", "pe_13";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_sdram_ras_cas_cfg {
- pins = "p6_5", "p6_4";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_sdram_dycs0_cfg {
- pins = "p6_9";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_sdram_cke_cfg {
- pins = "p6_11";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_sdram_clock_cfg {
- pins = "clk0", "clk1", "clk2", "clk3";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
- };
-
- enet_mii_pins: enet-mii-pins {
- enet_mii_rxd0_3_cfg {
- pins = "p1_15", "p0_0", "p9_3", "p9_2";
- function = "enet";
- bias-disable;
- input-enable;
- };
-
- enet_mii_txd0_3_cfg {
- pins = "p1_18", "p1_20", "p9_4", "p9_5";
- function = "enet";
- bias-disable;
- };
-
- enet_mii_crs_col_cfg {
- pins = "p9_0", "p9_6";
- function = "enet";
- bias-disable;
- input-enable;
- };
-
- enet_mii_rx_clk_dv_er_cfg {
- pins = "pc_0", "p1_16", "p9_1";
- function = "enet";
- bias-disable;
- input-enable;
- };
-
- enet_mii_tx_clk_en_cfg {
- pins = "p1_19", "p0_1";
- function = "enet";
- bias-disable;
- input-enable;
- };
-
- enet_mdio_cfg {
- pins = "p1_17";
- function = "enet";
- bias-disable;
- input-enable;
- };
-
- enet_mdc_cfg {
- pins = "pc_1";
- function = "enet";
- bias-disable;
- };
- };
-
- i2c0_pins: i2c0-pins {
- i2c0_pins_cfg {
- pins = "i2c0_scl", "i2c0_sda";
- function = "i2c0";
- input-enable;
- };
- };
-
- spifi_pins: spifi-pins {
- spifi_clk_cfg {
- pins = "p3_3";
- function = "spifi";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- spifi_mosi_miso_sio2_3_cfg {
- pins = "p3_7", "p3_6", "p3_5", "p3_4";
- function = "spifi";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- spifi_cs_cfg {
- pins = "p3_8";
- function = "spifi";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
- };
-
- uart0_pins: uart0-pins {
- uart0_rx_cfg {
- pins = "pf_11";
- function = "uart0";
- input-schmitt-disable;
- bias-disable;
- input-enable;
- };
-
- uart0_tx_cfg {
- pins = "pf_10";
- function = "uart0";
- bias-pull-down;
- };
- };
-};
-
-&adc1 {
- status = "okay";
- vref-supply = <&vcc>;
- pinctrl-names = "default";
- pinctrl-0 = <&adc1_pins>;
-};
-
-&emc {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&emc_pins>;
-
- cs0 {
- #address-cells = <2>;
- #size-cells = <1>;
- ranges;
-
- mpmc,cs = <0>;
- mpmc,memory-width = <16>;
- mpmc,byte-lane-low;
- mpmc,write-enable-delay = <0>;
- mpmc,output-enable-delay = <0>;
- mpmc,read-access-delay = <70>;
- mpmc,page-mode-read-delay = <70>;
-
- flash@0,0 {
- compatible = "sst,sst39vf320", "cfi-flash";
- reg = <0 0 0x400000>;
- bank-width = <2>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "bootloader";
- reg = <0x000000 0x040000>; /* 256 KiB */
- };
-
- partition@1 {
- label = "kernel";
- reg = <0x040000 0x2C0000>; /* 2.75 MiB */
- };
-
- partition@2 {
- label = "rootfs";
- reg = <0x300000 0x100000>; /* 1 MiB */
- };
- };
- };
-
- cs2 {
- #address-cells = <2>;
- #size-cells = <1>;
- ranges;
-
- mpmc,cs = <2>;
- mpmc,memory-width = <16>;
- mpmc,byte-lane-low;
- mpmc,write-enable-delay = <0>;
- mpmc,output-enable-delay = <30>;
- mpmc,read-access-delay = <90>;
- mpmc,page-mode-read-delay = <55>;
- mpmc,write-access-delay = <55>;
- mpmc,turn-round-delay = <55>;
-
- ext_sram: sram@2,0 {
- compatible = "mmio-sram";
- reg = <2 0 0x80000>; /* 512 KiB SRAM on IS62WV25616 */
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 2 0 0x80000>;
- };
- };
-};
-
-&enet_tx_clk {
- clock-frequency = <25000000>;
-};
-
-&i2c0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins>;
- clock-frequency = <400000>;
-
- /* NXP SE97BTP with temperature sensor + eeprom */
- sensor@18 {
- compatible = "nxp,se97", "jedec,jc-42.4-temp";
- reg = <0x18>;
- };
-
- eeprom@50 {
- compatible = "nxp,24c02", "atmel,24c02";
- reg = <0x50>;
- };
-
- pca_gpio: gpio@24 {
- compatible = "nxp,pca9673";
- reg = <0x24>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-};
-
-&mac {
- status = "okay";
- phy-mode = "mii";
- pinctrl-names = "default";
- pinctrl-0 = <&enet_mii_pins>;
-};
-
-&spifi {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&spifi_pins>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-rx-bus-width = <4>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "bootloader";
- reg = <0x000000 0x040000>; /* 256 KiB */
- };
-
- partition@1 {
- label = "kernel";
- reg = <0x040000 0x2c0000>; /* 2.75 MiB */
- };
-
- partition@2 {
- label = "rootfs";
- reg = <0x300000 0x500000>; /* 5 MiB */
- };
- };
-};
-
-&uart0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins>;
-};
diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4350.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc4350.dtsi
deleted file mode 100644
index 707d22a219d83..0000000000000
--- a/arch/arm/boot/dts/nxp/lpc/lpc4350.dtsi
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * NXP LPC4350 and LPC4330 SoC
- *
- * Copyright 2015 Ariel D'Alessandro <ariel.dalessandro@gmail.com>
- *
- * This code is released using a dual license strategy: BSD/GPL
- * You can choose the licence that better fits your requirements.
- *
- * Released under the terms of 3-clause BSD License
- * Released under the terms of GNU General Public License Version 2.0
- *
- */
-
-/ {
- compatible = "nxp,lpc4350", "nxp,lpc4330";
-
- cpus {
- cpu@0 {
- compatible = "arm,cortex-m4";
- };
- };
-
- soc {
- sram0: sram@10000000 {
- compatible = "mmio-sram";
- reg = <0x10000000 0x20000>; /* 96 + 32 KiB local SRAM */
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- };
-
- sram1: sram@10080000 {
- compatible = "mmio-sram";
- reg = <0x10080000 0x12000>; /* 64 + 8 KiB local SRAM */
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- };
-
- sram2: sram@20000000 {
- compatible = "mmio-sram";
- reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- };
- };
-};
diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts b/arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts
deleted file mode 100644
index 7ccb4c2ca5710..0000000000000
--- a/arch/arm/boot/dts/nxp/lpc/lpc4357-ea4357-devkit.dts
+++ /dev/null
@@ -1,624 +0,0 @@
-/*
- * Embedded Artist LPC4357 Developer's Kit
- *
- * Copyright 2015 Joachim Eastwood <manabian@gmail.com>
- *
- * This code is released using a dual license strategy: BSD/GPL
- * You can choose the licence that better fits your requirements.
- *
- * Released under the terms of 3-clause BSD License
- * Released under the terms of GNU General Public License Version 2.0
- *
- */
-/dts-v1/;
-
-#include "lpc18xx.dtsi"
-#include "lpc4357.dtsi"
-
-#include "dt-bindings/input/input.h"
-#include "dt-bindings/gpio/gpio.h"
-
-/ {
- model = "Embedded Artists' LPC4357 Developer's Kit";
- compatible = "ea,lpc4357-developers-kit", "nxp,lpc4357", "nxp,lpc4350";
-
- aliases {
- serial0 = &uart0;
- serial1 = &uart1;
- serial2 = &uart2;
- serial3 = &uart3;
- };
-
- chosen {
- stdout-path = &uart0;
- };
-
- memory@28000000 {
- device_type = "memory";
- reg = <0x28000000 0x2000000>; /* 32 MB */
- };
-
- vcc: vcc_fixed {
- compatible = "regulator-fixed";
- regulator-name = "3v3-supply";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- /* vmmc is controlled by sdmmc host internally */
- vmmc: vmmc_fixed {
- compatible = "regulator-fixed";
- regulator-name = "vmmc-supply";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- gpio_joystick {
- compatible = "gpio-keys-polled";
- pinctrl-names = "default";
- pinctrl-0 = <&gpio_joystick_pins>;
- poll-interval = <100>;
- autorepeat;
-
- button-0 {
- label = "joy_enter";
- linux,code = <KEY_ENTER>;
- gpios = <&gpio LPC_GPIO(4,8) GPIO_ACTIVE_LOW>;
- };
-
- button-1 {
- label = "joy_left";
- linux,code = <KEY_LEFT>;
- gpios = <&gpio LPC_GPIO(4,9) GPIO_ACTIVE_LOW>;
- };
-
- button-2 {
- label = "joy_up";
- linux,code = <KEY_UP>;
- gpios = <&gpio LPC_GPIO(4,10) GPIO_ACTIVE_LOW>;
- };
-
- button-3 {
- label = "joy_right";
- linux,code = <KEY_RIGHT>;
- gpios = <&gpio LPC_GPIO(4,12) GPIO_ACTIVE_LOW>;
- };
-
- button-4 {
- label = "joy_down";
- linux,code = <KEY_DOWN>;
- gpios = <&gpio LPC_GPIO(4,13) GPIO_ACTIVE_LOW>;
- };
- };
-
- leds_mmio {
- compatible = "gpio-leds";
-
- led1 {
- gpios = <&mmio_leds 15 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- };
-
- led2 {
- gpios = <&mmio_leds 14 GPIO_ACTIVE_HIGH>;
- };
-
- led3 {
- gpios = <&mmio_leds 13 GPIO_ACTIVE_HIGH>;
- };
-
- led4 {
- gpios = <&mmio_leds 12 GPIO_ACTIVE_HIGH>;
- };
-
- led5 {
- gpios = <&mmio_leds 11 GPIO_ACTIVE_HIGH>;
- };
-
- led6 {
- gpios = <&mmio_leds 10 GPIO_ACTIVE_HIGH>;
- };
-
- led7 {
- gpios = <&mmio_leds 9 GPIO_ACTIVE_HIGH>;
- };
-
- led8 {
- gpios = <&mmio_leds 8 GPIO_ACTIVE_HIGH>;
- };
-
- led9 {
- gpios = <&mmio_leds 7 GPIO_ACTIVE_HIGH>;
- };
-
- led10 {
- gpios = <&mmio_leds 6 GPIO_ACTIVE_HIGH>;
- };
-
- led11 {
- gpios = <&mmio_leds 5 GPIO_ACTIVE_HIGH>;
- };
-
- led12 {
- gpios = <&mmio_leds 4 GPIO_ACTIVE_HIGH>;
- };
-
- led13 {
- gpios = <&mmio_leds 3 GPIO_ACTIVE_HIGH>;
- };
-
- led14 {
- gpios = <&mmio_leds 2 GPIO_ACTIVE_HIGH>;
- };
-
- led15 {
- gpios = <&mmio_leds 1 GPIO_ACTIVE_HIGH>;
- };
-
- led16 {
- gpios = <&mmio_leds 0 GPIO_ACTIVE_HIGH>;
- };
- };
-};
-
-&pinctrl {
- emc_pins: emc-pins {
- emc_addr0_23_cfg {
- pins = "p2_9", "p2_10", "p2_11", "p2_12",
- "p2_13", "p1_0", "p1_1", "p1_2",
- "p2_8", "p2_7", "p2_6", "p2_2",
- "p2_1", "p2_0", "p6_8", "p6_7",
- "pd_16", "pd_15", "pe_0", "pe_1",
- "pe_2", "pe_3", "pe_4", "pa_4";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_data0_31_cfg {
- pins = "p1_7", "p1_8", "p1_9", "p1_10",
- "p1_11", "p1_12", "p1_13", "p1_14",
- "p5_4", "p5_5", "p5_6", "p5_7",
- "p5_0", "p5_1", "p5_2", "p5_3",
- "pd_2", "pd_3", "pd_4", "pd_5",
- "pd_6", "pd_7", "pd_8", "pd_9",
- "pe_5", "pe_6", "pe_7", "pe_8",
- "pe_9", "pe_10", "pe_11", "pe_12";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_we_oe_cfg {
- pins = "p1_6", "p1_3";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_bls0_3_cfg {
- pins = "p1_4", "p6_6", "pd_13", "pd_10";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_cs0_3_cfg {
- pins = "p1_5", "p6_3", "pd_12", "pd_11";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_sdram_dqm0_3_cfg {
- pins = "p6_12", "p6_10", "pd_0", "pe_13";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_sdram_ras_cas_cfg {
- pins = "p6_5", "p6_4";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_sdram_dycs0_cfg {
- pins = "p6_9";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_sdram_cke_cfg {
- pins = "p6_11";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- emc_sdram_clock_cfg {
- pins = "clk0", "clk1", "clk2", "clk3";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
- };
-
- enet_rmii_pins: enet-rmii-pins {
- enet_rmii_rxd_cfg {
- pins = "p1_15", "p0_0";
- function = "enet";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- enet_rmii_txd_cfg {
- pins = "p1_18", "p1_20";
- function = "enet";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- enet_rmii_rx_dv_cfg {
- pins = "p1_16";
- function = "enet";
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- enet_rmii_tx_en_cfg {
- pins = "p0_1";
- function = "enet";
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- enet_ref_clk_cfg {
- pins = "p1_19";
- function = "enet";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- enet_mdio_cfg {
- pins = "p1_17";
- function = "enet";
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- enet_mdc_cfg {
- pins = "pc_1";
- function = "enet";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
- };
-
- gpio_joystick_pins: gpio-joystick-pins {
- gpio_joystick_cfg {
- pins = "p9_0", "p9_1", "pa_1", "pa_2", "pa_3";
- function = "gpio";
- input-enable;
- bias-disable;
- };
- };
-
- i2c0_pins: i2c0-pins {
- i2c0_pins_cfg {
- pins = "i2c0_scl", "i2c0_sda";
- function = "i2c0";
- input-enable;
- };
- };
-
- sdmmc_pins: sdmmc-pins {
- sdmmc_clk_cfg {
- pins = "pc_0";
- function = "sdmmc";
- slew-rate = <1>;
- bias-pull-down;
- };
-
- sdmmc_cmd_dat0_3_cfg {
- pins = "pc_4", "pc_5", "pc_6", "pc_7", "pc_10";
- function = "sdmmc";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- sdmmc_cd_cfg {
- pins = "pc_8";
- function = "sdmmc";
- bias-pull-down;
- input-enable;
- };
-
- sdmmc_pow_cfg {
- pins = "pc_9";
- function = "sdmmc";
- bias-pull-down;
- };
- };
-
- spifi_pins: spifi-pins {
- spifi_clk_cfg {
- pins = "p3_3";
- function = "spifi";
- slew-rate = <1>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- spifi_mosi_miso_sio2_3_cfg {
- pins = "p3_7", "p3_6", "p3_5", "p3_4";
- function = "spifi";
- slew-rate = <0>;
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- spifi_cs_cfg {
- pins = "p3_8";
- function = "spifi";
- bias-disable;
- };
- };
-
- ssp0_pins: ssp0-pins {
- ssp0_sck_miso_mosi_cfg {
- pins = "pf_0", "pf_2", "pf_3";
- function = "ssp0";
- slew-rate = <1>;
- bias-pull-down;
- input-enable;
- input-schmitt-disable;
- };
-
- ssp0_ssel_cfg {
- pins = "pf_1";
- function = "ssp0";
- bias-pull-up;
- };
- };
-
- uart0_pins: uart0-pins {
- uart0_rx_cfg {
- pins = "pf_11";
- function = "uart0";
- input-schmitt-disable;
- bias-disable;
- input-enable;
- };
-
- uart0_tx_cfg {
- pins = "pf_10";
- function = "uart0";
- bias-pull-down;
- };
- };
-
- uart3_pins: uart3-pins {
- uart3_rx_cfg {
- pins = "p2_4";
- function = "uart3";
- input-schmitt-disable;
- bias-disable;
- input-enable;
- };
-
- uart3_tx_cfg {
- pins = "p9_3";
- function = "uart3";
- bias-pull-down;
- };
- };
-
- usb0_pins: usb0-pins {
- usb0_pwr_enable_cfg {
- pins = "p2_3";
- function = "usb0";
- };
-
- usb0_pwr_fault_cfg {
- pins = "p8_0";
- function = "usb0";
- bias-disable;
- input-enable;
- };
- };
-};
-
-&adc0 {
- status = "okay";
- vref-supply = <&vcc>;
-};
-
-&i2c0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins>;
- clock-frequency = <400000>;
-
- mma7455@1d {
- compatible = "fsl,mma7455";
- reg = <0x1d>;
- };
-
- temperature-sensor@48 {
- compatible = "national,lm75b";
- reg = <0x48>;
- };
-
- eeprom@57 {
- compatible = "microchip,24c64", "atmel,24c64";
- reg = <0x57>;
- };
-};
-
-&dac {
- status = "okay";
- vref-supply = <&vcc>;
-};
-
-&emc {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&emc_pins>;
-
- cs0 {
- #address-cells = <2>;
- #size-cells = <1>;
- ranges;
-
- mpmc,cs = <0>;
- mpmc,memory-width = <16>;
- mpmc,byte-lane-low;
- mpmc,write-enable-delay = <0>;
- mpmc,output-enable-delay = <0>;
- mpmc,read-access-delay = <70>;
- mpmc,page-mode-read-delay = <70>;
-
- flash@0,0 {
- compatible = "sst,sst39vf320", "cfi-flash";
- reg = <0 0 0x400000>;
- bank-width = <2>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "bootloader";
- reg = <0x000000 0x040000>; /* 256 KiB */
- };
-
- partition@1 {
- label = "kernel";
- reg = <0x040000 0x2c0000>; /* 2.75 MiB */
- };
-
- partition@2 {
- label = "rootfs";
- reg = <0x300000 0x100000>; /* 1 MiB */
- };
- };
- };
-
- cs2 {
- #address-cells = <2>;
- #size-cells = <1>;
- ranges;
-
- mpmc,cs = <2>;
- mpmc,memory-width = <16>;
-
- mmio_leds: gpio@2,0 {
- compatible = "ti,7416374";
- reg = <2 0 0x2>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- };
-};
-
-&enet_tx_clk {
- clock-frequency = <50000000>;
-};
-
-&mac {
- status = "okay";
- phy-mode = "rmii";
- pinctrl-names = "default";
- pinctrl-0 = <&enet_rmii_pins>;
-};
-
-&mmcsd {
- status = "okay";
- bus-width = <4>;
- vmmc-supply = <&vmmc>;
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_pins>;
-};
-
-&spifi {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&spifi_pins>;
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-cpol;
- spi-cpha;
- spi-rx-bus-width = <4>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "data";
- reg = <0 0x200000>;
- };
- };
-};
-
-&ssp0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&ssp0_pins>;
- num-cs = <1>;
-};
-
-&uart0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins>;
-};
-
-&uart3 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&uart3_pins>;
-};
-
-&usb0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_pins>;
-};
diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts b/arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts
deleted file mode 100644
index d18f2b2caf687..0000000000000
--- a/arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dts
+++ /dev/null
@@ -1,621 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
-/*
- * MYIR Tech MYD-LPC4357 Development Board with 800x480 7" TFT panel
- *
- * Copyright (C) 2016-2018 Vladimir Zapolskiy <vz@mleia.com>
- */
-
-/dts-v1/;
-
-#include "lpc18xx.dtsi"
-#include "lpc4357.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-
-/ {
- model = "MYIR Tech LPC4357 Development Board";
- compatible = "myir,myd-lpc4357", "nxp,lpc4357";
-
- chosen {
- stdout-path = "serial3:115200n8";
- };
-
- memory@28000000 {
- device_type = "memory";
- reg = <0x28000000 0x2000000>;
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&led_pins>;
-
- led1 {
- gpios = <&gpio LPC_GPIO(6,15) GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led2 {
- gpios = <&gpio LPC_GPIO(6,16) GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led3 {
- gpios = <&gpio LPC_GPIO(6,17) GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led4 {
- gpios = <&gpio LPC_GPIO(6,10) GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led5 {
- gpios = <&gpio LPC_GPIO(7,14) GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
-
- led6 {
- gpios = <&gpio LPC_GPIO(6,14) GPIO_ACTIVE_LOW>;
- default-state = "off";
- };
- };
-
- panel: panel {
- compatible = "innolux,at070tn92";
- power-supply = <&vcc>;
-
- port {
- panel_input: endpoint {
- remote-endpoint = <&lcdc_output>;
- };
- };
- };
-
- vcc: vcc_fixed {
- compatible = "regulator-fixed";
- regulator-name = "vcc-supply";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- vmmc: vmmc_fixed {
- compatible = "regulator-fixed";
- regulator-name = "vmmc-supply";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-};
-
-&pinctrl {
- can0_pins: can0-pins {
- can_rd_cfg {
- pins = "p3_1";
- function = "can0";
- input-enable;
- };
-
- can_td_cfg {
- pins = "p3_2";
- function = "can0";
- };
- };
-
- can1_pins: can1-pins {
- can_rd_cfg {
- pins = "pe_1";
- function = "can1";
- input-enable;
- };
-
- can_td_cfg {
- pins = "pe_0";
- function = "can1";
- };
- };
-
- emc_pins: emc-pins {
- emc_addr0_22_cfg {
- pins = "p2_9", "p2_10", "p2_11", "p2_12",
- "p2_13", "p1_0", "p1_1", "p1_2",
- "p2_8", "p2_7", "p2_6", "p2_2",
- "p2_1", "p2_0", "p6_8", "p6_7",
- "pd_16", "pd_15", "pe_0", "pe_1",
- "pe_2", "pe_3", "pe_4";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- };
-
- emc_data0_15_cfg {
- pins = "p1_7", "p1_8", "p1_9", "p1_10",
- "p1_11", "p1_12", "p1_13", "p1_14",
- "p5_4", "p5_5", "p5_6", "p5_7",
- "p5_0", "p5_1", "p5_2", "p5_3";
- function = "emc";
- input-enable;
- input-schmitt-disable;
- slew-rate = <1>;
- bias-disable;
- };
-
- emc_we_oe_cfg {
- pins = "p1_6", "p1_3";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- };
-
- emc_cs0_cfg {
- pins = "p1_5";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- };
-
- emc_sdram_dqm0_1_cfg {
- pins = "p6_12", "p6_10";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- };
-
- emc_sdram_ras_cas_cfg {
- pins = "p6_5", "p6_4";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- };
-
- emc_sdram_dycs0_cfg {
- pins = "p6_9";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- };
-
- emc_sdram_cke_cfg {
- pins = "p6_11";
- function = "emc";
- slew-rate = <1>;
- bias-disable;
- };
-
- emc_sdram_clock_cfg {
- pins = "clk0";
- function = "emc";
- input-enable;
- input-schmitt-disable;
- slew-rate = <1>;
- bias-disable;
- };
- };
-
- enet_rmii_pins: enet-rmii-pins {
- enet_rmii_rxd_cfg {
- pins = "p1_15", "p0_0";
- function = "enet";
- input-enable;
- input-schmitt-disable;
- slew-rate = <1>;
- bias-disable;
- };
-
- enet_rmii_txd_cfg {
- pins = "p1_18", "p1_20";
- function = "enet";
- slew-rate = <1>;
- bias-disable;
- };
-
- enet_rmii_rx_dv_cfg {
- pins = "p1_16";
- function = "enet";
- input-enable;
- input-schmitt-disable;
- bias-disable;
- };
-
- enet_mdio_cfg {
- pins = "p1_17";
- function = "enet";
- input-enable;
- input-schmitt-disable;
- bias-disable;
- };
-
- enet_mdc_cfg {
- pins = "pc_1";
- function = "enet";
- slew-rate = <1>;
- bias-disable;
- };
-
- enet_rmii_tx_en_cfg {
- pins = "p0_1";
- function = "enet";
- bias-disable;
- };
-
- enet_ref_clk_cfg {
- pins = "p1_19";
- function = "enet";
- slew-rate = <1>;
- input-enable;
- input-schmitt-disable;
- bias-disable;
- };
- };
-
- i2c0_pins: i2c0-pins {
- i2c0_pins_cfg {
- pins = "i2c0_scl", "i2c0_sda";
- function = "i2c0";
- input-enable;
- };
- };
-
- i2c1_pins: i2c1-pins {
- i2c1_pins_cfg {
- pins = "pe_15", "pe_13";
- function = "i2c1";
- input-enable;
- };
- };
-
- lcd_pins: lcd-pins {
- lcd_vd0_23_cfg {
- pins = "p4_1", "p4_4", "p4_3", "p4_2",
- "p8_7", "p8_6", "p8_5", "p8_4",
- "p7_5", "p4_8", "p4_10", "p4_9",
- "p8_3", "pb_6", "pb_5", "pb_4",
- "p7_4", "p7_3", "p7_2", "p7_1",
- "pb_3", "pb_2", "pb_1", "pb_0";
- function = "lcd";
- };
-
- lcd_vsync_en_dclk_lp_pwr_cfg {
- pins = "p4_5", "p4_6", "p4_7", "p7_6", "p7_7";
- function = "lcd";
- };
- };
-
- led_pins: led-pins {
- led_1_6_cfg {
- pins = "pd_1", "pd_2", "pd_3", "pc_11", "pe_14", "pd_0";
- function = "gpio";
- bias-pull-down;
- };
- };
-
- sdmmc_pins: sdmmc-pins {
- sdmmc_clk_cfg {
- pins = "pc_0";
- function = "sdmmc";
- slew-rate = <1>;
- bias-pull-down;
- };
-
- sdmmc_cmd_dat0_3_cfg {
- pins = "pc_4", "pc_5", "pc_6", "pc_7", "pc_10";
- function = "sdmmc";
- input-enable;
- input-schmitt-disable;
- slew-rate = <1>;
- bias-disable;
- };
-
- sdmmc_cd_cfg {
- pins = "pc_8";
- function = "sdmmc";
- input-enable;
- bias-pull-down;
- };
- };
-
- spifi_pins: spifi-pins {
- spifi_sck_cfg {
- pins = "p3_3";
- function = "spifi";
- input-enable;
- input-schmitt-disable;
- slew-rate = <1>;
- bias-disable;
- };
-
- spifi_mosi_miso_sio2_sio3_cfg {
- pins = "p3_7", "p3_6", "p3_5", "p3_4";
- function = "spifi";
- input-enable;
- input-schmitt-disable;
- slew-rate = <1>;
- bias-disable;
- };
-
- spifi_cs_cfg {
- pins = "p3_8";
- function = "spifi";
- bias-disable;
- };
- };
-
- ssp1_pins: ssp1-pins {
- ssp1_sck_cfg {
- pins = "pf_4";
- function = "ssp1";
- slew-rate = <1>;
- bias-pull-down;
- };
-
- ssp1_miso_cfg {
- pins = "pf_6";
- function = "ssp1";
- input-enable;
- input-schmitt-disable;
- slew-rate = <1>;
- bias-pull-down;
- };
-
- ssp1_mosi_cfg {
- pins = "pf_7";
- function = "ssp1";
- slew-rate = <1>;
- bias-pull-down;
- };
-
- ssp1_ssel_cfg {
- pins = "pf_5";
- function = "gpio";
- bias-disable;
- };
- };
-
- uart0_pins: uart0-pins {
- uart0_rxd_cfg {
- pins = "pf_11";
- function = "uart0";
- input-enable;
- input-schmitt-disable;
- bias-disable;
- };
-
- uart0_clk_dir_txd_cfg {
- pins = "pf_8", "pf_9", "pf_10";
- function = "uart0";
- bias-pull-down;
- };
- };
-
- uart1_pins: uart1-pins {
- uart1_rxd_cfg {
- pins = "pc_14";
- function = "uart1";
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- uart1_dtr_txd_cfg {
- pins = "pc_12", "pc_13";
- function = "uart1";
- bias-pull-down;
- };
- };
-
- uart2_pins: uart2-pins {
- uart2_rxd_cfg {
- pins = "pa_2";
- function = "uart2";
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- uart2_txd_cfg {
- pins = "pa_1";
- function = "uart2";
- bias-pull-down;
- };
- };
-
- uart3_pins: uart3-pins {
- uart3_rx_cfg {
- pins = "p2_4";
- function = "uart3";
- bias-disable;
- input-enable;
- input-schmitt-disable;
- };
-
- uart3_tx_cfg {
- pins = "p2_3";
- function = "uart3";
- bias-pull-down;
- };
- };
-
- usb0_pins: usb0-pins {
- usb0_pwr_enable_cfg {
- pins = "p6_3";
- function = "usb0";
- };
-
- usb0_pwr_fault_cfg {
- pins = "p8_0";
- function = "usb0";
- bias-disable;
- input-enable;
- };
- };
-};
-
-&adc1 {
- status = "okay";
- vref-supply = <&vcc>;
-};
-
-&can0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&can0_pins>;
-};
-
-/* Pin conflict with EMC, muxed by JP5 and JP6 */
-&can1 {
- status = "disabled";
- pinctrl-names = "default";
- pinctrl-0 = <&can1_pins>;
-};
-
-&emc {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&emc_pins>;
-
- cs0 {
- #address-cells = <2>;
- #size-cells = <1>;
- ranges;
-
- mpmc,cs = <0>;
- mpmc,memory-width = <16>;
- mpmc,byte-lane-low;
- mpmc,write-enable-delay = <0>;
- mpmc,output-enable-delay = <0>;
- mpmc,read-access-delay = <70>;
- mpmc,page-mode-read-delay = <70>;
-
- /* SST/Microchip SST39VF1601 */
- flash@0,0 {
- compatible = "cfi-flash";
- reg = <0 0 0x400000>;
- bank-width = <2>;
- };
- };
-};
-
-&enet_tx_clk {
- clock-frequency = <50000000>;
-};
-
-&i2c0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins>;
- clock-frequency = <400000>;
-};
-
-&i2c1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins>;
- clock-frequency = <400000>;
-
- sensor@49 {
- compatible = "national,lm75";
- reg = <0x49>;
- };
-
- eeprom@50 {
- compatible = "atmel,24c512";
- reg = <0x50>;
- };
-};
-
-&lcdc {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&lcd_pins>;
-
- max-memory-bandwidth = <92240000>;
-
- port {
- lcdc_output: endpoint {
- remote-endpoint = <&panel_input>;
- arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
- };
- };
-};
-
-&mac {
- status = "okay";
- phy-mode = "rmii";
- pinctrl-names = "default";
- pinctrl-0 = <&enet_rmii_pins>;
- phy-handle = <&phy1>;
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,dwmac-mdio";
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
- };
-};
-
-&mmcsd {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&sdmmc_pins>;
- bus-width = <4>;
- vmmc-supply = <&vmmc>;
-};
-
-/* Pin conflict with SSP0, the latter is routed to J17 pin header */
-&spifi {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&spifi_pins>;
-
- /* Atmel AT25DF321A */
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- spi-max-frequency = <51000000>;
- spi-cpol;
- spi-cpha;
- };
-};
-
-&ssp1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&ssp1_pins>;
- num-cs = <1>;
- cs-gpios = <&gpio LPC_GPIO(7,19) GPIO_ACTIVE_LOW>;
-};
-
-/* Routed to J17 pin header */
-&uart0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins>;
-};
-
-/* RS485 */
-&uart1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins>;
-};
-
-/* Routed to J17 pin header */
-&uart2 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins>;
-};
-
-&uart3 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&uart3_pins>;
-};
-
-&usb0 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&usb0_pins>;
-};
diff --git a/arch/arm/boot/dts/nxp/lpc/lpc4357.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc4357.dtsi
deleted file mode 100644
index d138ee7869ff3..0000000000000
--- a/arch/arm/boot/dts/nxp/lpc/lpc4357.dtsi
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * NXP LPC435x, LPC433x, LPC4327, LPC4325, LPC4317 and LPC4315 SoC
- *
- * Copyright 2015 Joachim Eastwood <manabian@gmail.com>
- *
- * This code is released using a dual license strategy: BSD/GPL
- * You can choose the licence that better fits your requirements.
- *
- * Released under the terms of 3-clause BSD License
- * Released under the terms of GNU General Public License Version 2.0
- *
- */
-
-/ {
- compatible = "nxp,lpc4357";
-
- cpus {
- cpu@0 {
- compatible = "arm,cortex-m4";
- };
- };
-
- soc {
- sram0: sram@10000000 {
- compatible = "mmio-sram";
- reg = <0x10000000 0x8000>; /* 32 KiB local SRAM */
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- };
-
- sram1: sram@10080000 {
- compatible = "mmio-sram";
- reg = <0x10080000 0xa000>; /* 32 + 8 KiB local SRAM */
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- };
-
- sram2: sram@20000000 {
- compatible = "mmio-sram";
- reg = <0x20000000 0x10000>; /* 4 x 16 KiB AHB SRAM */
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- };
- };
-};
-
-&eeprom {
- status = "okay";
-};
--
2.43.0
^ permalink raw reply related
* Re: [PATCH 00/11] ARM: NXP: Drop NOMMU platform support
From: Vladimir Zapolskiy @ 2026-06-19 16:07 UTC (permalink / raw)
To: Frank.Li, Arnd Bergmann, Sascha Hauer, Pengutronix Kernel Team,
Stefan Agner, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Russell King, Abel Vesa, Peng Fan,
Michael Turquette, Stephen Boyd, Brian Masney, Dong Aisheng,
Jacky Bai, NXP S32 Linux Team, Linus Walleij, Piotr Wojtaszczyk,
Kees Cook, Gustavo A. R. Silva
Cc: linux-arm-kernel, imx, devicetree, linux-kernel, linux-clk,
linux-gpio, linux-hardening, Frank Li
In-Reply-To: <20260619-dts_cleanup_arm_mcore-v1-0-0101795a2662@nxp.com>
Hello Frank.
On 6/19/26 18:40, Frank.Li@oss.nxp.com wrote:
> Commercial users and hardware vendors migrated to Zephyr or other RTOS
> solutions years ago, leaving the NOMMU platform support effectively
> unused and unmaintained.
>
> Remove the obsolete support to reduce maintenance burden and simplify the
> Freescale/nxp platform code.
>
> Some driver code still be kept and may clean up later since it is possible
> reused by other SoC.
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
This change is a bit too early to happen, I prefer to get it orchestrated
by Arnd. So, as for today I NAK the change for its NXP LPC part.
> ---
> Frank Li (11):
> ARM: dts: vf610m4: Remove NOMMU platform support
> ARM: dts: imxrt1050: Remove NOMMU platform support
> ARM: imx: Remove NOMMU platform support
> clk: imx: imxrt1050: Remove NOMMU platform support
> pinctrl: freescale: IMXRT: Remove NOMMU platform support
> ARM: imxrt_defconfig: Remove NOMMU platform support
> ARM: dts: lpc: Remove NOMMU platform support
> ARM: mach-lpc: Remove NOMMU platform support
> ARM: configs: lpc*: Remove NOMMU platform support
> clk: nxp: lpc: Remove NOMMU platform support
> pinctrl: nxp: lpc: Remove NOMMU platform support
>
> .../devicetree/bindings/pinctrl/fsl,imxrt1050.yaml | 79 -
> .../devicetree/bindings/pinctrl/fsl,imxrt1170.yaml | 77 -
> arch/arm/Kconfig | 12 -
> arch/arm/Makefile | 2 -
> arch/arm/boot/dts/nxp/Makefile | 1 -
> arch/arm/boot/dts/nxp/imx/Makefile | 2 -
> arch/arm/boot/dts/nxp/imx/imxrt1050-evk.dts | 72 -
> arch/arm/boot/dts/nxp/imx/imxrt1050-pinfunc.h | 993 ------------
> arch/arm/boot/dts/nxp/imx/imxrt1050.dtsi | 160 --
> arch/arm/boot/dts/nxp/imx/imxrt1170-pinfunc.h | 1561 -------------------
> arch/arm/boot/dts/nxp/lpc/Makefile | 9 -
> arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi | 543 -------
> arch/arm/boot/dts/nxp/lpc/lpc3250-ea3250.dts | 273 ----
> arch/arm/boot/dts/nxp/lpc/lpc3250-phy3250.dts | 236 ---
> arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 540 -------
NXP LPC32xx is ARMv5 and it has MMU, hence it's plainly out of scope of
the proposed "dropping NOMMU platform support".
--
Best wishes,
Vladimir
^ permalink raw reply
* Re: Re: [PATCH] fix: arm64: syscall: use live x0 for syscall_get_arguments() arg0
From: Will Deacon @ 2026-06-19 16:05 UTC (permalink / raw)
To: Yiqi Sun
Cc: catalin.marinas, kees, keno, linux-arm-kernel, linux-kernel,
luis.machado, mark.rutland, rmk+kernel, ruanjinjie
In-Reply-To: <20260603090730.16960-1-sunyiqixm@gmail.com>
On Wed, Jun 03, 2026 at 05:07:30PM +0800, Yiqi Sun wrote:
> On Mon, 1 Jun 2026 13:43:42 +0100, Well wrote:
> > On Fri, May 29, 2026 at 02:54:44PM +0800, Yiqi Sun wrote:
> > > On arm64, seccomp obtains syscall arguments via syscall_get_arguments(),
> > > where arg0 is currently read from regs->orig_x0. However, the syscall
> > > wrapper consumes live arguments from regs->regs[0..5].
> > >
> > > A ptracer can modify x0 on syscall-enter stop before seccomp runs,
> > > but cannot update orig_x0 through that interface. This can
> > > leave seccomp checking stale arg0 while the syscall executes with updated
> > > live x0, allowing seccomp bypass when filters depend on arg0.
> > >
> > > Make syscall_get_arguments() read arg0 from regs->regs[0], matching the
> > > actual dispatch arguments and removing this desynchronization.
> > >
> > > Fixes: f27bb139c387 ("arm64: Miscellaneous library functions")
> > > Signed-off-by: Yiqi Sun <sunyiqixm@gmail.com>
> > > ---
> > > arch/arm64/include/asm/syscall.h | 2 +-
> > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/arch/arm64/include/asm/syscall.h b/arch/arm64/include/asm/syscall.h
> > > index 5e4c7fc44f73..4bdb4d3ce2b4 100644
> > > --- a/arch/arm64/include/asm/syscall.h
> > > +++ b/arch/arm64/include/asm/syscall.h
> > > @@ -81,7 +81,7 @@ static inline void syscall_get_arguments(struct task_struct *task,
> > > struct pt_regs *regs,
> > > unsigned long *args)
> > > {
> > > - args[0] = regs->orig_x0;
> > > + args[0] = regs->regs[0];
> > > args[1] = regs->regs[1];
> > > args[2] = regs->regs[2];
> > > args[3] = regs->regs[3];
> > > --
> > > 2.34.1
> >
> > Hrm, this looks like a long-standing issue and I'm pretty nervous about
> > changing it :/
> >
> > How did you spot it?
>
> I share your concern here, and I’m trying to be very careful with any
> behavior change.
>
> I spotted this while comparing seccomp+ptrace ordering across arches.
> I had previously looked at x86/x86_64 (including the seccomp/ptrace
> ordering fix from more than 10 years ago), and then checked whether
> other arches like arm64 had the same issue.
>
> > A quick look at the code suggests we have a similar issue with
> > audit_syscall_entry(), so if we take your patch here then it will silently
> > introduce a behavioural change to this guy:
> >
> > https://lore.kernel.org/all/20260320102620.1336796-5-ruanjinjie@huawei.com/
> >
> > I also notice that the compat ptrace interface allows 'orig_x0' to be
> > set -- could that cause issues with things like syscall_rollback()?
> > Will
>
> You are right that on arm64, audit_syscall_entry() still takes arg0
> from orig_x0, so taking only this seccomp fix would diverge seccomp
> and audit semantics.
>
> I also checked syscall_rollback(): on arm64 it restores regs[0] from
> orig_x0, and orig_x0 is captured at syscall entry before the ptrace
> syscall-stop hook. So rollback normally returns to the syscall-entry
> state (i.e. pre-ptrace argument value), which does not look like a new
> security issue by itself. compat ptrace can explicitly write orig_x0,
> but that is existing tracer-controlled behavior and does not, by itself,
> cross a new security boundary introduced by this patch.
>
> If you agree, I can send a follow-up later so seccomp/audit stay consistent.
Yes, please send a v2 that fixes audit at the same time.
Will
^ permalink raw reply
* Re: [PATCH 2/5] dmaengine: sun6i-dma: Add set_addr function pointer for variable address widths
From: Frank Li @ 2026-06-19 16:02 UTC (permalink / raw)
To: Yuanshen Cao
Cc: Vinod Koul, Frank Li, Chen-Yu Tsai, Jernej Skrabec,
Samuel Holland, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Maxime Ripard, dmaengine, linux-arm-kernel, linux-sunxi,
linux-kernel, devicetree
In-Reply-To: <20260619-sun60i-a733-dma-v1-2-da4b649fc72a@gmail.com>
On Fri, Jun 19, 2026 at 04:53:31AM +0000, Yuanshen Cao wrote:
>
> The A733 DMA controller supports higher address (up to 32G) compared to
> previous generations. The existing `sun6i_dma_set_addr` function uses a
> hardcoded logic for setting the high-address bits in the LLI parameters.
>
> By moving `set_addr` into the `sun6i_dma_config` structure, we can
> provide specialized implementations for different hardware. This allows
> the A733 to use a version of `set_addr` that correctly handles its
> specific `SRC_HIGH_ADDR_32G` and `DST_HIGH_ADDR_32G` in the `set_addr`
> register later in the series.
>
> Changes:
> - Added `set_addr` function pointer to `struct sun6i_dma_config`.
> - Refactored `sun6i_dma_set_addr` and introduced
> `sun6i_dma_set_addr_a100` (keeping the logic for high address
> support).
> - Updated all existing configuration structs to include the new
> `set_addr` pointer.
> - Removed `has_high_addr` since the logic is replaced by
> `sun6i_dma_set_addr_a100`.
>
> Signed-off-by: Yuanshen Cao <alex.caoys@gmail.com>
> ---
> drivers/dma/sun6i-dma.c | 36 ++++++++++++++++++++++++++----------
> 1 file changed, 26 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c
> index d92e702320d9..059455425e19 100644
> --- a/drivers/dma/sun6i-dma.c
> +++ b/drivers/dma/sun6i-dma.c
> @@ -112,6 +112,7 @@
>
> /* forward declaration */
> struct sun6i_dma_dev;
> +struct sun6i_dma_lli;
>
> /*
> * Hardware channels / ports representation
> @@ -138,6 +139,8 @@ struct sun6i_dma_config {
> void (*set_burst_length)(u32 *p_cfg, s8 src_burst, s8 dst_burst);
> void (*set_drq)(u32 *p_cfg, s8 src_drq, s8 dst_drq);
> void (*set_mode)(u32 *p_cfg, s8 src_mode, s8 dst_mode);
> + void (*set_addr)(struct sun6i_dma_dev *sdev, struct sun6i_dma_lli *v_lli,
> + dma_addr_t src, dma_addr_t dst);
> void (*dump_com_regs)(struct sun6i_dma_dev *sdev);
> u32 (*read_irq_en)(struct sun6i_dma_dev *sdev, u32 chan_num);
> void (*write_irq_en)(struct sun6i_dma_dev *sdev, u32 chan_num, u32 irq_val);
> @@ -147,7 +150,6 @@ struct sun6i_dma_config {
> u32 dst_burst_lengths;
> u32 src_addr_widths;
> u32 dst_addr_widths;
> - bool has_high_addr;
> bool has_mbus_clk;
> };
>
> @@ -675,13 +677,20 @@ static int set_config(struct sun6i_dma_dev *sdev,
> static inline void sun6i_dma_set_addr(struct sun6i_dma_dev *sdev,
> struct sun6i_dma_lli *v_lli,
> dma_addr_t src, dma_addr_t dst)
> +{
> + v_lli->src = lower_32_bits(src);
> + v_lli->dst = lower_32_bits(dst);
> +}
> +
> +static inline void sun6i_dma_set_addr_a100(struct sun6i_dma_dev *sdev,
> + struct sun6i_dma_lli *v_lli,
> + dma_addr_t src, dma_addr_t dst)
> {
> v_lli->src = lower_32_bits(src);
> v_lli->dst = lower_32_bits(dst);
>
> - if (sdev->cfg->has_high_addr)
> - v_lli->para |= SRC_HIGH_ADDR(upper_32_bits(src)) |
> - DST_HIGH_ADDR(upper_32_bits(dst));
> + v_lli->para |= SRC_HIGH_ADDR(upper_32_bits(src)) |
> + DST_HIGH_ADDR(upper_32_bits(dst));
> }
>
> static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_memcpy(
> @@ -714,7 +723,7 @@ static struct dma_async_tx_descriptor *sun6i_dma_prep_dma_memcpy(
>
> v_lli->len = len;
> v_lli->para = NORMAL_WAIT;
> - sun6i_dma_set_addr(sdev, v_lli, src, dest);
> + sdev->cfg->set_addr(sdev, v_lli, src, dest);
can you move sdev->cfg->set_addr into helper function sun6i_dma_set_addr())
so need't change other place.
Old sun6i_dma_set_addr() rename sun6i_dma_set_addr_<name>()
sun6i_dma_set_addr()
{
sdev->cfg->set_addr(sdev, v_lli, src, dest)
}
Frank
^ permalink raw reply
* [PATCH v3 0/1] coresight: fix issue with insufficient claim tags
From: Mike Leach @ 2026-06-19 16:01 UTC (permalink / raw)
To: coresight, linux-arm-kernel, linux-kernel
Cc: suzuki.poulose, leo.yan, james.clark, Mike Leach
All CoreSight compliant components have an implementation defined number
of 0 to 8 claim tag bits in the claim tag registers.
These are used to claim the CoreSight resources by system agents.
ARM recommends implementions have 4 claim tag bits, though a valid
implementation can have 0 claim tags bits.
The CoreSight drivers implement a 2 claim tag bit protocol to allow
self hosted and external debug agents to manage access to the hardware.
However, if there are less than 2 claim tags available the protocol
incorrectly returns an error on device claim, as no checks are made.
If insufficient claim tags are present in a component then the protocol
must return success on claim / disclaim to allow components to be used
normally.
Add initialisation to read the CLAIMSET bits to establish the number of
available claim tag bits, and adjust the claim returns accordingly.
Cache the claimtag protocol availablity in the coresight_device to reduce
reads for the main claim/disclaim api.
changes since v2:
1) consolidated API to remove the API calls using just cs_access, which were
used purely to clear down stale self claim tags, replace with a normal
coresight_device API for initialisation, to match the claim/disclaim API.
This does both the check on availability and the stale tag clearance.
Updated all drivers to use the new init functionality
2) Added option for drivers to skip claim tag checking completely for devices
with no-compliant hardware, that do not implement registers at the claim tag
location, or do not operate correctly to indicate the correct number of
claim tags for the device.
changes since v1:
1) Added claim tag availability cache into coresight_device when using the
main coresight_claim_device() / coresight_disclaim_device() API.
Applies to coresight/next
Mike Leach (1):
coresight: fix issue where coresight component has no claimtags
drivers/hwtracing/coresight/coresight-catu.c | 6 +-
drivers/hwtracing/coresight/coresight-core.c | 139 ++++++++++++++++--
.../hwtracing/coresight/coresight-cti-core.c | 7 +-
drivers/hwtracing/coresight/coresight-etb10.c | 9 +-
.../coresight/coresight-etm3x-core.c | 8 +-
.../coresight/coresight-etm4x-core.c | 8 +-
.../hwtracing/coresight/coresight-funnel.c | 7 +-
drivers/hwtracing/coresight/coresight-priv.h | 7 +
.../coresight/coresight-replicator.c | 9 +-
.../hwtracing/coresight/coresight-tmc-core.c | 7 +-
include/linux/coresight.h | 23 ++-
11 files changed, 205 insertions(+), 25 deletions(-)
--
2.43.0
^ permalink raw reply
* [PATCH v3 1/1] coresight: fix issue where coresight component has no claimtags
From: Mike Leach @ 2026-06-19 16:01 UTC (permalink / raw)
To: coresight, linux-arm-kernel, linux-kernel
Cc: suzuki.poulose, leo.yan, james.clark, Mike Leach
In-Reply-To: <20260619160148.499223-1-mike.leach@arm.com>
Coresight components have 0 to 8 claim tag bits. ARM recommends 4 and
the implemented claim tag protocol uses two of these.
If a component has insufficient claim tags then the protocol incorrectly
returns an error when attempting to claim a component.
Fix by introducing a claim tag init function that will read CLAIMSET
to establish then actual number of claim tags and save a claim tag info
flag to indicate the level of support in the device.
Additionally this init routine will also clear down any stale self claim
tag bits that are present in the hardware - removing the need for the
additional interface that was added to accomplish this during device probe.
Any device which is not verified to support claim tags, will now get a
success return from the claim/disclaim calls.
Device drivers can also force skipping of claim tag support checks where
hardware does not support any readable registers at the claim tag
location.
Signed-off-by: Mike Leach <mike.leach@arm.com>
---
drivers/hwtracing/coresight/coresight-catu.c | 6 +-
drivers/hwtracing/coresight/coresight-core.c | 139 ++++++++++++++++--
.../hwtracing/coresight/coresight-cti-core.c | 7 +-
drivers/hwtracing/coresight/coresight-etb10.c | 9 +-
.../coresight/coresight-etm3x-core.c | 8 +-
.../coresight/coresight-etm4x-core.c | 8 +-
.../hwtracing/coresight/coresight-funnel.c | 7 +-
drivers/hwtracing/coresight/coresight-priv.h | 7 +
.../coresight/coresight-replicator.c | 9 +-
.../hwtracing/coresight/coresight-tmc-core.c | 7 +-
include/linux/coresight.h | 23 ++-
11 files changed, 205 insertions(+), 25 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-catu.c b/drivers/hwtracing/coresight/coresight-catu.c
index 43abe13995cf..d8a0ecc502af 100644
--- a/drivers/hwtracing/coresight/coresight-catu.c
+++ b/drivers/hwtracing/coresight/coresight-catu.c
@@ -574,10 +574,14 @@ static int __catu_probe(struct device *dev, struct resource *res)
catu_desc.subtype.helper_subtype = CORESIGHT_DEV_SUBTYPE_HELPER_CATU;
catu_desc.ops = &catu_ops;
- coresight_clear_self_claim_tag(&catu_desc.access);
drvdata->csdev = coresight_register(&catu_desc);
if (IS_ERR(drvdata->csdev))
ret = PTR_ERR(drvdata->csdev);
+
+ ret = coresight_init_claim_tags(drvdata->csdev);
+ if (ret)
+ coresight_unregister(drvdata->csdev);
+
out:
return ret;
}
diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c
index f7b1308a759c..b110d1b977d1 100644
--- a/drivers/hwtracing/coresight/coresight-core.c
+++ b/drivers/hwtracing/coresight/coresight-core.c
@@ -232,6 +232,34 @@ coresight_find_out_connection(struct coresight_device *csdev,
return ERR_PTR(-ENODEV);
}
+/*
+ * Reading CLAIMSET returns a bitfield representing the number of claim tags
+ * implemented from bit 0 to bit nTag-1, valid bits set to 1.
+ *
+ * Claim protocol requires 2 bits so test for MS bit required,
+ * bit 1 - CORESIGHT_CLAIM_SELF_HOSTED
+ *
+ * return true if sufficient claim tags implemented for protocol
+ */
+static bool coresight_claim_tags_implemented_unlocked(struct csdev_access *csa)
+{
+ u32 claim_bits_impl = FIELD_GET(CORESIGHT_CLAIM_BITS_MAX_MASK,
+ csdev_access_relaxed_read32(csa, CORESIGHT_CLAIMSET));
+ return ((claim_bits_impl & CORESIGHT_CLAIM_SELF_HOSTED) != 0);
+}
+
+/* helper for checking if claim tag protocol in use */
+static bool coresight_using_claim_tag_protocol(struct coresight_device *csdev)
+{
+ return (bool)(csdev->claim_tag_info == CS_CLAIM_TAG_STD_PROTOCOL);
+}
+
+/* helper to check initialised */
+static bool coresight_claim_tag_noinit(struct coresight_device *csdev)
+{
+ return (bool)(csdev->claim_tag_info == CS_CLAIM_TAG_UNKNOWN);
+}
+
static u32 coresight_read_claim_tags_unlocked(struct coresight_device *csdev)
{
return FIELD_GET(CORESIGHT_CLAIM_MASK,
@@ -245,23 +273,97 @@ static void coresight_set_self_claim_tag_unlocked(struct coresight_device *csdev
isb();
}
-void coresight_clear_self_claim_tag(struct csdev_access *csa)
+static void coresight_clear_self_claim_tag_unlocked(struct csdev_access *csa)
+{
+ csdev_access_relaxed_write32(csa, CORESIGHT_CLAIM_SELF_HOSTED,
+ CORESIGHT_CLAIMCLR);
+ isb();
+}
+
+/*
+ * Initialise claim tag protocol.
+ *
+ * Check for existence of claim tags and clear down any stale
+ * existing self claim tag.
+ *
+ * Set claim tag protocol usage flag.
+ *
+ * Automatically unlocks/relocks memory mapped devices.
+ *
+ * Call during device probe.
+ */
+int coresight_init_claim_tags(struct coresight_device *csdev)
{
+ struct csdev_access *csa;
+
+ if (WARN_ON(!csdev))
+ return -EINVAL;
+
+ /* if previous init or forced ignore claim tag, no checks needed */
+ if (csdev->claim_tag_info != CS_CLAIM_TAG_UNKNOWN) {
+ if (csdev->claim_tag_info == CS_CLAIM_TAG_IGNORE)
+ dev_dbg(&csdev->dev,
+ "Device set to ignore claim tag protocols\n");
+ return 0;
+ }
+
+ /* get the access method */
+ csa = &csdev->access;
+
+ /* unlock if memory access */
if (csa->io_mem)
CS_UNLOCK(csa->base);
- coresight_clear_self_claim_tag_unlocked(csa);
+
+ /* check claim tag validity */
+ if (coresight_claim_tags_implemented_unlocked(csa)) {
+ csdev->claim_tag_info = CS_CLAIM_TAG_STD_PROTOCOL;
+ dev_dbg(&csdev->dev, "Device using standard claim tag protocol\n");
+
+ /* using claim tags so clear down any stale self claim tag */
+ coresight_clear_self_claim_tag_unlocked(csa);
+ } else {
+ csdev->claim_tag_info = CS_CLAIM_TAG_NOT_IMPL;
+ dev_dbg(&csdev->dev, "Device claim tag hardware not implemented\n");
+ }
+
+ /* relock if memory access */
if (csa->io_mem)
CS_LOCK(csa->base);
+
+ /* return success - caller can check claim_tag_info for state */
+ return 0;
}
-EXPORT_SYMBOL_GPL(coresight_clear_self_claim_tag);
+EXPORT_SYMBOL_GPL(coresight_init_claim_tags);
+
+struct cs_claim_tag_init_arg {
+ struct coresight_device *csdev;
+ int rc;
+};
-void coresight_clear_self_claim_tag_unlocked(struct csdev_access *csa)
+static void coresight_init_claim_tags_smp_call(void *info)
{
- csdev_access_relaxed_write32(csa, CORESIGHT_CLAIM_SELF_HOSTED,
- CORESIGHT_CLAIMCLR);
- isb();
+ struct cs_claim_tag_init_arg *arg = info;
+
+ arg->rc = coresight_init_claim_tags(arg->csdev);
}
-EXPORT_SYMBOL_GPL(coresight_clear_self_claim_tag_unlocked);
+
+/* cpu bound devices (etms) may need to run on bound cpu */
+int coresight_init_claim_tags_cpu_smp(struct coresight_device *csdev, int cpu)
+{
+ int ret = 0;
+ struct cs_claim_tag_init_arg arg = { };
+
+ arg.csdev = csdev;
+ ret = smp_call_function_single(cpu,
+ coresight_init_claim_tags_smp_call,
+ &arg, 1);
+
+ if (!ret)
+ ret = arg.rc;
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(coresight_init_claim_tags_cpu_smp);
/*
* coresight_claim_device_unlocked : Claim the device for self-hosted usage
@@ -276,12 +378,18 @@ EXPORT_SYMBOL_GPL(coresight_clear_self_claim_tag_unlocked);
int coresight_claim_device_unlocked(struct coresight_device *csdev)
{
int tag;
- struct csdev_access *csa;
if (WARN_ON(!csdev))
return -EINVAL;
- csa = &csdev->access;
+ /* check init complete */
+ if (WARN_ON(coresight_claim_tag_noinit(csdev)))
+ return -EPERM;
+
+ /* check if we are using claim tags on this device */
+ if (!coresight_using_claim_tag_protocol(csdev))
+ return 0;
+
tag = coresight_read_claim_tags_unlocked(csdev);
switch (tag) {
@@ -291,7 +399,7 @@ int coresight_claim_device_unlocked(struct coresight_device *csdev)
return 0;
/* There was a race setting the tag, clean up and fail */
- coresight_clear_self_claim_tag_unlocked(csa);
+ coresight_clear_self_claim_tag_unlocked(&csdev->access);
dev_dbg(&csdev->dev, "Busy: Couldn't set self claim tag");
return -EBUSY;
@@ -338,6 +446,14 @@ void coresight_disclaim_device_unlocked(struct coresight_device *csdev)
if (WARN_ON(!csdev))
return;
+ /* check init complete */
+ if (WARN_ON(coresight_claim_tag_noinit(csdev)))
+ return;
+
+ /* check if we are using claim tags on this device */
+ if (!coresight_using_claim_tag_protocol(csdev))
+ return;
+
if (coresight_read_claim_tags_unlocked(csdev) == CORESIGHT_CLAIM_SELF_HOSTED)
coresight_clear_self_claim_tag_unlocked(&csdev->access);
else
@@ -1543,6 +1659,7 @@ coresight_init_device(struct coresight_desc *desc)
csdev->ops = desc->ops;
csdev->access = desc->access;
csdev->orphan = true;
+ csdev->claim_tag_info = CS_CLAIM_TAG_UNKNOWN;
if (desc->flags & CORESIGHT_DESC_CPU_BOUND) {
csdev->cpu = desc->cpu;
diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwtracing/coresight/coresight-cti-core.c
index b2c9a4db13b4..436ae2d8a7b9 100644
--- a/drivers/hwtracing/coresight/coresight-cti-core.c
+++ b/drivers/hwtracing/coresight/coresight-cti-core.c
@@ -729,11 +729,16 @@ static int cti_probe(struct amba_device *adev, const struct amba_id *id)
cti_desc.groups = drvdata->ctidev.con_groups;
cti_desc.dev = dev;
- coresight_clear_self_claim_tag(&cti_desc.access);
drvdata->csdev = coresight_register(&cti_desc);
if (IS_ERR(drvdata->csdev))
return PTR_ERR(drvdata->csdev);
+ ret = coresight_init_claim_tags(drvdata->csdev);
+ if (ret) {
+ coresight_unregister(drvdata->csdev);
+ return ret;
+ }
+
/* add to list of CTI devices */
mutex_lock(&ect_mutex);
list_add(&drvdata->node, &ect_net);
diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c
index a827f76b8144..339d902ce88a 100644
--- a/drivers/hwtracing/coresight/coresight-etb10.c
+++ b/drivers/hwtracing/coresight/coresight-etb10.c
@@ -769,22 +769,25 @@ static int etb_probe(struct amba_device *adev, const struct amba_id *id)
desc.dev = dev;
desc.groups = coresight_etb_groups;
- coresight_clear_self_claim_tag(&desc.access);
drvdata->csdev = coresight_register(&desc);
if (IS_ERR(drvdata->csdev))
return PTR_ERR(drvdata->csdev);
+ ret = coresight_init_claim_tags(drvdata->csdev);
+ if (ret)
+ goto err_unregister_csdev;
+
drvdata->miscdev.name = desc.name;
drvdata->miscdev.minor = MISC_DYNAMIC_MINOR;
drvdata->miscdev.fops = &etb_fops;
ret = misc_register(&drvdata->miscdev);
if (ret)
- goto err_misc_register;
+ goto err_unregister_csdev;
pm_runtime_put(&adev->dev);
return 0;
-err_misc_register:
+err_unregister_csdev:
coresight_unregister(drvdata->csdev);
return ret;
}
diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/hwtracing/coresight/coresight-etm3x-core.c
index 862ad0786699..3d24bcac14ec 100644
--- a/drivers/hwtracing/coresight/coresight-etm3x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c
@@ -756,7 +756,6 @@ static void etm_init_arch_data(void *info)
drvdata->nr_ext_out = BMVAL(etmccr, 20, 22);
drvdata->nr_ctxid_cmp = BMVAL(etmccr, 24, 25);
- coresight_clear_self_claim_tag_unlocked(&drvdata->csa);
etm_set_pwrdwn(drvdata);
etm_clr_pwrup(drvdata);
CS_LOCK(drvdata->csa.base);
@@ -852,6 +851,13 @@ static int etm_probe(struct amba_device *adev, const struct amba_id *id)
if (IS_ERR(drvdata->csdev))
return PTR_ERR(drvdata->csdev);
+ /* init the claim tag protocol - ensure run on correct cpu */
+ ret = coresight_init_claim_tags_cpu_smp(drvdata->csdev, drvdata->cpu);
+ if (ret) {
+ coresight_unregister(drvdata->csdev);
+ return ret;
+ }
+
ret = etm_perf_symlink(drvdata->csdev, true);
if (ret) {
coresight_unregister(drvdata->csdev);
diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index 14bb31bd6a0b..b053ba7cf021 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -1511,7 +1511,6 @@ static void etm4_init_arch_data(void *info)
/* NUMCNTR, bits[30:28] number of counters available for tracing */
drvdata->nr_cntr = FIELD_GET(TRCIDR5_NUMCNTR_MASK, etmidr5);
- coresight_clear_self_claim_tag_unlocked(csa);
etm4_cs_lock(drvdata, csa);
cpu_detect_trace_filtering(drvdata);
}
@@ -2195,6 +2194,13 @@ static int etm4_add_coresight_dev(struct etm4_init_arg *init_arg)
if (IS_ERR(drvdata->csdev))
return PTR_ERR(drvdata->csdev);
+ /* init the claim tag protocol - ensure run on correct cpu */
+ ret = coresight_init_claim_tags_cpu_smp(drvdata->csdev, drvdata->cpu);
+ if (ret) {
+ coresight_unregister(drvdata->csdev);
+ return ret;
+ }
+
ret = etm_perf_symlink(drvdata->csdev, true);
if (ret) {
coresight_unregister(drvdata->csdev);
diff --git a/drivers/hwtracing/coresight/coresight-funnel.c b/drivers/hwtracing/coresight/coresight-funnel.c
index 3f56ceccd8c9..72f87284219a 100644
--- a/drivers/hwtracing/coresight/coresight-funnel.c
+++ b/drivers/hwtracing/coresight/coresight-funnel.c
@@ -244,7 +244,6 @@ static int funnel_probe(struct device *dev, struct resource *res)
drvdata->base = base;
desc.groups = coresight_funnel_groups;
desc.access = CSDEV_ACCESS_IOMEM(base);
- coresight_clear_self_claim_tag(&desc.access);
}
dev_set_drvdata(dev, drvdata);
@@ -265,6 +264,12 @@ static int funnel_probe(struct device *dev, struct resource *res)
if (IS_ERR(drvdata->csdev))
return PTR_ERR(drvdata->csdev);
+ if (res) {
+ ret = coresight_init_claim_tags(drvdata->csdev);
+ if (ret)
+ coresight_unregister(drvdata->csdev);
+ }
+
return 0;
}
diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h
index dddac946659f..fada0e49ed28 100644
--- a/drivers/hwtracing/coresight/coresight-priv.h
+++ b/drivers/hwtracing/coresight/coresight-priv.h
@@ -41,6 +41,13 @@ extern const struct device_type coresight_dev_type[];
#define CORESIGHT_CLAIM_SELF_HOSTED 2
#define CORESIGHT_CLAIM_INVALID 3
+/*
+ * Coresight specification defines a maximum of 8 claim tag bits.
+ * The precise number is implementation defined, and may be obtained by
+ * reading the CLAIMSET register.
+ */
+#define CORESIGHT_CLAIM_BITS_MAX_MASK GENMASK(7, 0)
+
#define TIMEOUT_US 100
#define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb)
diff --git a/drivers/hwtracing/coresight/coresight-replicator.c b/drivers/hwtracing/coresight/coresight-replicator.c
index 07fc04f53b88..0ef87715fa2a 100644
--- a/drivers/hwtracing/coresight/coresight-replicator.c
+++ b/drivers/hwtracing/coresight/coresight-replicator.c
@@ -251,7 +251,6 @@ static int replicator_probe(struct device *dev, struct resource *res)
drvdata->base = base;
desc.groups = replicator_groups;
desc.access = CSDEV_ACCESS_IOMEM(base);
- coresight_clear_self_claim_tag(&desc.access);
}
if (fwnode_property_present(dev_fwnode(dev),
@@ -276,6 +275,14 @@ static int replicator_probe(struct device *dev, struct resource *res)
if (IS_ERR(drvdata->csdev))
return PTR_ERR(drvdata->csdev);
+ if (res) {
+ ret = coresight_init_claim_tags(drvdata->csdev);
+ if (ret) {
+ coresight_unregister(drvdata->csdev);
+ return ret;
+ }
+ }
+
replicator_reset(drvdata);
return 0;
}
diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c
index c89fe996af23..45241c934ee6 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-core.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-core.c
@@ -864,13 +864,18 @@ static int __tmc_probe(struct device *dev, struct resource *res)
dev->platform_data = pdata;
desc.pdata = pdata;
- coresight_clear_self_claim_tag(&desc.access);
drvdata->csdev = coresight_register(&desc);
if (IS_ERR(drvdata->csdev)) {
ret = PTR_ERR(drvdata->csdev);
goto out;
}
+ ret = coresight_init_claim_tags(drvdata->csdev);
+ if (ret) {
+ coresight_unregister(drvdata->csdev);
+ goto out;
+ }
+
drvdata->miscdev.name = desc.name;
drvdata->miscdev.minor = MISC_DYNAMIC_MINOR;
drvdata->miscdev.fops = &tmc_fops;
diff --git a/include/linux/coresight.h b/include/linux/coresight.h
index add0579cad88..126e0e867e16 100644
--- a/include/linux/coresight.h
+++ b/include/linux/coresight.h
@@ -248,6 +248,20 @@ struct coresight_trace_id_map {
raw_spinlock_t lock;
};
+/*
+ * Coresight claim tag info:
+ * CS_CLAIM_TAG_UNKNOWN - not yet checked.
+ * CS_CLAIM_TAG_STD_PROTOCOL - using standard claim/release protocol.
+ * CS_CLAIM_TAG_NOT_IMPL - no claim tags available.
+ * CS_CLAIM_TAG_IGNORE - force skip of claim tags protocol
+ */
+enum coresight_claim_tag_info {
+ CS_CLAIM_TAG_UNKNOWN,
+ CS_CLAIM_TAG_STD_PROTOCOL,
+ CS_CLAIM_TAG_NOT_IMPL,
+ CS_CLAIM_TAG_IGNORE,
+};
+
/**
* struct coresight_device - representation of a device as used by the framework
* @pdata: Platform data with device connections associated to this device.
@@ -269,6 +283,7 @@ struct coresight_trace_id_map {
* spinlock.
* @cpu: The CPU this component is affined to (-1 for not CPU bound).
* @orphan: true if the component has connections that haven't been linked.
+ * @claim_tag_info: how the device is using claim tags.
* @sysfs_sink_activated: 'true' when a sink has been selected for use via sysfs
* by writing a 1 to the 'enable_sink' file. A sink can be
* activated but not yet enabled. Enabling for a _sink_ happens
@@ -297,6 +312,7 @@ struct coresight_device {
int refcnt;
int cpu;
bool orphan;
+ enum coresight_claim_tag_info claim_tag_info;
/* sink specific fields */
bool sysfs_sink_activated;
struct dev_ext_attribute *ea;
@@ -664,15 +680,14 @@ int coresight_timeout(struct csdev_access *csa, u32 offset, int position, int va
typedef void (*coresight_timeout_cb_t) (struct csdev_access *, u32, int, int);
int coresight_timeout_action(struct csdev_access *csa, u32 offset, int position, int value,
coresight_timeout_cb_t cb);
-int coresight_claim_device(struct coresight_device *csdev);
-int coresight_claim_device_unlocked(struct coresight_device *csdev);
int coresight_claim_device(struct coresight_device *csdev);
int coresight_claim_device_unlocked(struct coresight_device *csdev);
-void coresight_clear_self_claim_tag(struct csdev_access *csa);
-void coresight_clear_self_claim_tag_unlocked(struct csdev_access *csa);
void coresight_disclaim_device(struct coresight_device *csdev);
void coresight_disclaim_device_unlocked(struct coresight_device *csdev);
+int coresight_init_claim_tags(struct coresight_device *csdev);
+int coresight_init_claim_tags_cpu_smp(struct coresight_device *csdev, int cpu);
+
char *coresight_alloc_device_name(const char *prefix, struct device *dev);
bool coresight_loses_context_with_cpu(struct device *dev);
--
2.43.0
^ permalink raw reply related
* [PATCH 08/11] ARM: mach-lpc: Remove NOMMU platform support
From: Frank.Li @ 2026-06-19 15:41 UTC (permalink / raw)
To: Arnd Bergmann, Sascha Hauer, Pengutronix Kernel Team,
Stefan Agner, Fabio Estevam, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Russell King, Abel Vesa, Peng Fan,
Michael Turquette, Stephen Boyd, Brian Masney, Dong Aisheng,
Jacky Bai, NXP S32 Linux Team, Linus Walleij, Vladimir Zapolskiy,
Piotr Wojtaszczyk, Kees Cook, Gustavo A. R. Silva
Cc: linux-arm-kernel, imx, devicetree, linux-kernel, linux-clk,
linux-gpio, linux-hardening, Frank Li
In-Reply-To: <20260619-dts_cleanup_arm_mcore-v1-0-0101795a2662@nxp.com>
From: Frank Li <Frank.Li@nxp.com>
Commercial users and hardware vendors migrated to Zephyr or other RTOS
solutions years ago, leaving the NOMMU platform support effectively
unused and unmaintained.
Remove the obsolete support to reduce maintenance burden and simplify the
NXP/Freescale platform code.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm/Kconfig | 12 -
arch/arm/Makefile | 2 -
arch/arm/mach-lpc18xx/Makefile | 2 -
arch/arm/mach-lpc18xx/board-dt.c | 19 --
arch/arm/mach-lpc32xx/Kconfig | 13 -
arch/arm/mach-lpc32xx/Makefile | 8 -
arch/arm/mach-lpc32xx/common.c | 125 -------
arch/arm/mach-lpc32xx/common.h | 32 --
arch/arm/mach-lpc32xx/lpc32xx.h | 717 ---------------------------------------
arch/arm/mach-lpc32xx/phy3250.c | 92 -----
arch/arm/mach-lpc32xx/pm.c | 135 --------
arch/arm/mach-lpc32xx/serial.c | 148 --------
arch/arm/mach-lpc32xx/suspend.S | 148 --------
13 files changed, 1453 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9187240a02db5..fe67d41f4a107 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -401,8 +401,6 @@ source "arch/arm/mach-ixp4xx/Kconfig"
source "arch/arm/mach-keystone/Kconfig"
-source "arch/arm/mach-lpc32xx/Kconfig"
-
source "arch/arm/mach-mediatek/Kconfig"
source "arch/arm/mach-meson/Kconfig"
@@ -470,16 +468,6 @@ source "arch/arm/mach-zte/Kconfig"
source "arch/arm/mach-zynq/Kconfig"
# ARMv7-M architecture
-config ARCH_LPC18XX
- bool "NXP LPC18xx/LPC43xx"
- depends on ARM_SINGLE_ARMV7M
- select ARCH_HAS_RESET_CONTROLLER
- select ARM_AMBA
- select CLKSRC_LPC32XX
- select PINCTRL
- help
- Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
- high performance microcontrollers.
config ARCH_MPS2
bool "ARM MPS2 platform"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 573813ef5e77a..dd30c256780d9 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -191,8 +191,6 @@ machine-$(CONFIG_ARCH_HIGHBANK) += highbank
machine-$(CONFIG_ARCH_HISI) += hisi
machine-$(CONFIG_ARCH_IXP4XX) += ixp4xx
machine-$(CONFIG_ARCH_KEYSTONE) += keystone
-machine-$(CONFIG_ARCH_LPC18XX) += lpc18xx
-machine-$(CONFIG_ARCH_LPC32XX) += lpc32xx
machine-$(CONFIG_ARCH_MESON) += meson
machine-$(CONFIG_ARCH_MMP) += mmp
machine-$(CONFIG_ARCH_MV78XX0) += mv78xx0
diff --git a/arch/arm/mach-lpc18xx/Makefile b/arch/arm/mach-lpc18xx/Makefile
deleted file mode 100644
index c80d80c199d37..0000000000000
--- a/arch/arm/mach-lpc18xx/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-obj-y += board-dt.o
diff --git a/arch/arm/mach-lpc18xx/board-dt.c b/arch/arm/mach-lpc18xx/board-dt.c
deleted file mode 100644
index 4729eb83401ae..0000000000000
--- a/arch/arm/mach-lpc18xx/board-dt.c
+++ /dev/null
@@ -1,19 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Device Tree board file for NXP LPC18xx/43xx
- *
- * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
- */
-
-#include <asm/mach/arch.h>
-
-static const char *const lpc18xx_43xx_compat[] __initconst = {
- "nxp,lpc1850",
- "nxp,lpc4350",
- "nxp,lpc4370",
- NULL
-};
-
-DT_MACHINE_START(LPC18XXDT, "NXP LPC18xx/43xx (Device Tree)")
- .dt_compat = lpc18xx_43xx_compat,
-MACHINE_END
diff --git a/arch/arm/mach-lpc32xx/Kconfig b/arch/arm/mach-lpc32xx/Kconfig
deleted file mode 100644
index 138599545c24c..0000000000000
--- a/arch/arm/mach-lpc32xx/Kconfig
+++ /dev/null
@@ -1,13 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-
-config ARCH_LPC32XX
- bool "NXP LPC32XX"
- depends on ARCH_MULTI_V5
- depends on CPU_LITTLE_ENDIAN
- select ARM_AMBA
- select CLKSRC_LPC32XX
- select CPU_ARM926T
- select GPIOLIB
- select LPC32XX_DMAMUX if AMBA_PL08X
- help
- Support for the NXP LPC32XX family of processors
diff --git a/arch/arm/mach-lpc32xx/Makefile b/arch/arm/mach-lpc32xx/Makefile
deleted file mode 100644
index 3bac1d17a207b..0000000000000
--- a/arch/arm/mach-lpc32xx/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-#
-# Makefile for the linux kernel.
-#
-
-obj-y := common.o serial.o
-obj-y += pm.o suspend.o
-obj-y += phy3250.o
diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c
deleted file mode 100644
index 304ea61a07160..0000000000000
--- a/arch/arm/mach-lpc32xx/common.c
+++ /dev/null
@@ -1,125 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * arch/arm/mach-lpc32xx/common.c
- *
- * Author: Kevin Wells <kevin.wells@nxp.com>
- *
- * Copyright (C) 2010 NXP Semiconductors
- */
-
-#include <linux/init.h>
-#include <linux/soc/nxp/lpc32xx-misc.h>
-
-#include <asm/mach/map.h>
-#include <asm/system_info.h>
-
-#include "lpc32xx.h"
-#include "common.h"
-
-/*
- * Returns the unique ID for the device
- */
-void lpc32xx_get_uid(u32 devid[4])
-{
- int i;
-
- for (i = 0; i < 4; i++)
- devid[i] = __raw_readl(LPC32XX_CLKPWR_DEVID(i << 2));
-}
-
-/*
- * Detects and returns IRAM size for the device variation
- */
-#define LPC32XX_IRAM_BANK_SIZE SZ_128K
-static u32 iram_size;
-u32 lpc32xx_return_iram(void __iomem **mapbase, dma_addr_t *dmaaddr)
-{
- if (iram_size == 0) {
- u32 savedval1, savedval2;
- void __iomem *iramptr1, *iramptr2;
-
- iramptr1 = io_p2v(LPC32XX_IRAM_BASE);
- iramptr2 = io_p2v(LPC32XX_IRAM_BASE + LPC32XX_IRAM_BANK_SIZE);
- savedval1 = __raw_readl(iramptr1);
- savedval2 = __raw_readl(iramptr2);
-
- if (savedval1 == savedval2) {
- __raw_writel(savedval2 + 1, iramptr2);
- if (__raw_readl(iramptr1) == savedval2 + 1)
- iram_size = LPC32XX_IRAM_BANK_SIZE;
- else
- iram_size = LPC32XX_IRAM_BANK_SIZE * 2;
- __raw_writel(savedval2, iramptr2);
- } else
- iram_size = LPC32XX_IRAM_BANK_SIZE * 2;
- }
- if (dmaaddr)
- *dmaaddr = LPC32XX_IRAM_BASE;
- if (mapbase)
- *mapbase = io_p2v(LPC32XX_IRAM_BASE);
-
- return iram_size;
-}
-EXPORT_SYMBOL_GPL(lpc32xx_return_iram);
-
-void lpc32xx_set_phy_interface_mode(phy_interface_t mode)
-{
- u32 tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL);
- tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK;
- if (mode == PHY_INTERFACE_MODE_MII)
- tmp |= LPC32XX_CLKPWR_MACCTRL_USE_MII_PINS;
- else
- tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS;
- __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL);
-}
-EXPORT_SYMBOL_GPL(lpc32xx_set_phy_interface_mode);
-
-static struct map_desc lpc32xx_io_desc[] __initdata = {
- {
- .virtual = (unsigned long)IO_ADDRESS(LPC32XX_AHB0_START),
- .pfn = __phys_to_pfn(LPC32XX_AHB0_START),
- .length = LPC32XX_AHB0_SIZE,
- .type = MT_DEVICE
- },
- {
- .virtual = (unsigned long)IO_ADDRESS(LPC32XX_AHB1_START),
- .pfn = __phys_to_pfn(LPC32XX_AHB1_START),
- .length = LPC32XX_AHB1_SIZE,
- .type = MT_DEVICE
- },
- {
- .virtual = (unsigned long)IO_ADDRESS(LPC32XX_FABAPB_START),
- .pfn = __phys_to_pfn(LPC32XX_FABAPB_START),
- .length = LPC32XX_FABAPB_SIZE,
- .type = MT_DEVICE
- },
- {
- .virtual = (unsigned long)IO_ADDRESS(LPC32XX_IRAM_BASE),
- .pfn = __phys_to_pfn(LPC32XX_IRAM_BASE),
- .length = (LPC32XX_IRAM_BANK_SIZE * 2),
- .type = MT_DEVICE
- },
-};
-
-void __init lpc32xx_map_io(void)
-{
- iotable_init(lpc32xx_io_desc, ARRAY_SIZE(lpc32xx_io_desc));
-}
-
-static int __init lpc32xx_check_uid(void)
-{
- u32 uid[4];
-
- lpc32xx_get_uid(uid);
-
- printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n",
- uid[3], uid[2], uid[1], uid[0]);
-
- if (!system_serial_low && !system_serial_high) {
- system_serial_low = uid[0];
- system_serial_high = uid[1];
- }
-
- return 1;
-}
-arch_initcall(lpc32xx_check_uid);
diff --git a/arch/arm/mach-lpc32xx/common.h b/arch/arm/mach-lpc32xx/common.h
deleted file mode 100644
index 32f0ad2178077..0000000000000
--- a/arch/arm/mach-lpc32xx/common.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * arch/arm/mach-lpc32xx/common.h
- *
- * Author: Kevin Wells <kevin.wells@nxp.com>
- *
- * Copyright (C) 2009-2010 NXP Semiconductors
- */
-
-#ifndef __LPC32XX_COMMON_H
-#define __LPC32XX_COMMON_H
-
-#include <linux/init.h>
-
-/*
- * Other arch specific structures and functions
- */
-extern void __init lpc32xx_map_io(void);
-extern void __init lpc32xx_serial_init(void);
-
-/*
- * Returns the LPC32xx unique 128-bit chip ID
- */
-extern void lpc32xx_get_uid(u32 devid[4]);
-
-/*
- * Pointers used for sizing and copying suspend function data
- */
-extern int lpc32xx_sys_suspend(void);
-extern int lpc32xx_sys_suspend_sz;
-
-#endif
diff --git a/arch/arm/mach-lpc32xx/lpc32xx.h b/arch/arm/mach-lpc32xx/lpc32xx.h
deleted file mode 100644
index 5eeb884a19939..0000000000000
--- a/arch/arm/mach-lpc32xx/lpc32xx.h
+++ /dev/null
@@ -1,717 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * arch/arm/mach-lpc32xx/include/mach/platform.h
- *
- * Author: Kevin Wells <kevin.wells@nxp.com>
- *
- * Copyright (C) 2010 NXP Semiconductors
- */
-
-#ifndef __ARM_LPC32XX_H
-#define __ARM_LPC32XX_H
-
-#define _SBF(f, v) ((v) << (f))
-#define _BIT(n) _SBF(n, 1)
-
-/*
- * AHB 0 physical base addresses
- */
-#define LPC32XX_SLC_BASE 0x20020000
-#define LPC32XX_SSP0_BASE 0x20084000
-#define LPC32XX_SPI1_BASE 0x20088000
-#define LPC32XX_SSP1_BASE 0x2008C000
-#define LPC32XX_SPI2_BASE 0x20090000
-#define LPC32XX_I2S0_BASE 0x20094000
-#define LPC32XX_SD_BASE 0x20098000
-#define LPC32XX_I2S1_BASE 0x2009C000
-#define LPC32XX_MLC_BASE 0x200A8000
-#define LPC32XX_AHB0_START LPC32XX_SLC_BASE
-#define LPC32XX_AHB0_SIZE 0x00089000
-
-/*
- * AHB 1 physical base addresses
- */
-#define LPC32XX_DMA_BASE 0x31000000
-#define LPC32XX_USB_BASE 0x31020000
-#define LPC32XX_USBH_BASE 0x31020000
-#define LPC32XX_USB_OTG_BASE 0x31020000
-#define LPC32XX_OTG_I2C_BASE 0x31020300
-#define LPC32XX_LCD_BASE 0x31040000
-#define LPC32XX_ETHERNET_BASE 0x31060000
-#define LPC32XX_EMC_BASE 0x31080000
-#define LPC32XX_ETB_CFG_BASE 0x310C0000
-#define LPC32XX_ETB_DATA_BASE 0x310E0000
-#define LPC32XX_AHB1_START LPC32XX_DMA_BASE
-#define LPC32XX_AHB1_SIZE 0x000E1000
-
-/*
- * FAB physical base addresses
- */
-#define LPC32XX_CLK_PM_BASE 0x40004000
-#define LPC32XX_MIC_BASE 0x40008000
-#define LPC32XX_SIC1_BASE 0x4000C000
-#define LPC32XX_SIC2_BASE 0x40010000
-#define LPC32XX_HS_UART1_BASE 0x40014000
-#define LPC32XX_HS_UART2_BASE 0x40018000
-#define LPC32XX_HS_UART7_BASE 0x4001C000
-#define LPC32XX_RTC_BASE 0x40024000
-#define LPC32XX_RTC_RAM_BASE 0x40024080
-#define LPC32XX_GPIO_BASE 0x40028000
-#define LPC32XX_PWM3_BASE 0x4002C000
-#define LPC32XX_PWM4_BASE 0x40030000
-#define LPC32XX_MSTIM_BASE 0x40034000
-#define LPC32XX_HSTIM_BASE 0x40038000
-#define LPC32XX_WDTIM_BASE 0x4003C000
-#define LPC32XX_DEBUG_CTRL_BASE 0x40040000
-#define LPC32XX_TIMER0_BASE 0x40044000
-#define LPC32XX_ADC_BASE 0x40048000
-#define LPC32XX_TIMER1_BASE 0x4004C000
-#define LPC32XX_KSCAN_BASE 0x40050000
-#define LPC32XX_UART_CTRL_BASE 0x40054000
-#define LPC32XX_TIMER2_BASE 0x40058000
-#define LPC32XX_PWM1_BASE 0x4005C000
-#define LPC32XX_PWM2_BASE 0x4005C004
-#define LPC32XX_TIMER3_BASE 0x40060000
-
-/*
- * APB physical base addresses
- */
-#define LPC32XX_UART3_BASE 0x40080000
-#define LPC32XX_UART4_BASE 0x40088000
-#define LPC32XX_UART5_BASE 0x40090000
-#define LPC32XX_UART6_BASE 0x40098000
-#define LPC32XX_I2C1_BASE 0x400A0000
-#define LPC32XX_I2C2_BASE 0x400A8000
-
-/*
- * FAB and APB base and sizing
- */
-#define LPC32XX_FABAPB_START LPC32XX_CLK_PM_BASE
-#define LPC32XX_FABAPB_SIZE 0x000A5000
-
-/*
- * Internal memory bases and sizes
- */
-#define LPC32XX_IRAM_BASE 0x08000000
-#define LPC32XX_IROM_BASE 0x0C000000
-
-/*
- * External Static Memory Bank Address Space Bases
- */
-#define LPC32XX_EMC_CS0_BASE 0xE0000000
-#define LPC32XX_EMC_CS1_BASE 0xE1000000
-#define LPC32XX_EMC_CS2_BASE 0xE2000000
-#define LPC32XX_EMC_CS3_BASE 0xE3000000
-
-/*
- * External SDRAM Memory Bank Address Space Bases
- */
-#define LPC32XX_EMC_DYCS0_BASE 0x80000000
-#define LPC32XX_EMC_DYCS1_BASE 0xA0000000
-
-/*
- * Clock and crystal information
- */
-#define LPC32XX_MAIN_OSC_FREQ 13000000
-#define LPC32XX_CLOCK_OSC_FREQ 32768
-
-/*
- * Clock and Power control register offsets
- */
-#define _PMREG(x) io_p2v(LPC32XX_CLK_PM_BASE +\
- (x))
-#define LPC32XX_CLKPWR_DEBUG_CTRL _PMREG(0x000)
-#define LPC32XX_CLKPWR_BOOTMAP _PMREG(0x014)
-#define LPC32XX_CLKPWR_P01_ER _PMREG(0x018)
-#define LPC32XX_CLKPWR_USBCLK_PDIV _PMREG(0x01C)
-#define LPC32XX_CLKPWR_INT_ER _PMREG(0x020)
-#define LPC32XX_CLKPWR_INT_RS _PMREG(0x024)
-#define LPC32XX_CLKPWR_INT_SR _PMREG(0x028)
-#define LPC32XX_CLKPWR_INT_AP _PMREG(0x02C)
-#define LPC32XX_CLKPWR_PIN_ER _PMREG(0x030)
-#define LPC32XX_CLKPWR_PIN_RS _PMREG(0x034)
-#define LPC32XX_CLKPWR_PIN_SR _PMREG(0x038)
-#define LPC32XX_CLKPWR_PIN_AP _PMREG(0x03C)
-#define LPC32XX_CLKPWR_HCLK_DIV _PMREG(0x040)
-#define LPC32XX_CLKPWR_PWR_CTRL _PMREG(0x044)
-#define LPC32XX_CLKPWR_PLL397_CTRL _PMREG(0x048)
-#define LPC32XX_CLKPWR_MAIN_OSC_CTRL _PMREG(0x04C)
-#define LPC32XX_CLKPWR_SYSCLK_CTRL _PMREG(0x050)
-#define LPC32XX_CLKPWR_LCDCLK_CTRL _PMREG(0x054)
-#define LPC32XX_CLKPWR_HCLKPLL_CTRL _PMREG(0x058)
-#define LPC32XX_CLKPWR_ADC_CLK_CTRL_1 _PMREG(0x060)
-#define LPC32XX_CLKPWR_USB_CTRL _PMREG(0x064)
-#define LPC32XX_CLKPWR_SDRAMCLK_CTRL _PMREG(0x068)
-#define LPC32XX_CLKPWR_DDR_LAP_NOM _PMREG(0x06C)
-#define LPC32XX_CLKPWR_DDR_LAP_COUNT _PMREG(0x070)
-#define LPC32XX_CLKPWR_DDR_LAP_DELAY _PMREG(0x074)
-#define LPC32XX_CLKPWR_SSP_CLK_CTRL _PMREG(0x078)
-#define LPC32XX_CLKPWR_I2S_CLK_CTRL _PMREG(0x07C)
-#define LPC32XX_CLKPWR_MS_CTRL _PMREG(0x080)
-#define LPC32XX_CLKPWR_MACCLK_CTRL _PMREG(0x090)
-#define LPC32XX_CLKPWR_TEST_CLK_SEL _PMREG(0x0A4)
-#define LPC32XX_CLKPWR_SFW_INT _PMREG(0x0A8)
-#define LPC32XX_CLKPWR_I2C_CLK_CTRL _PMREG(0x0AC)
-#define LPC32XX_CLKPWR_KEY_CLK_CTRL _PMREG(0x0B0)
-#define LPC32XX_CLKPWR_ADC_CLK_CTRL _PMREG(0x0B4)
-#define LPC32XX_CLKPWR_PWM_CLK_CTRL _PMREG(0x0B8)
-#define LPC32XX_CLKPWR_TIMER_CLK_CTRL _PMREG(0x0BC)
-#define LPC32XX_CLKPWR_TIMERS_PWMS_CLK_CTRL_1 _PMREG(0x0C0)
-#define LPC32XX_CLKPWR_SPI_CLK_CTRL _PMREG(0x0C4)
-#define LPC32XX_CLKPWR_NAND_CLK_CTRL _PMREG(0x0C8)
-#define LPC32XX_CLKPWR_UART3_CLK_CTRL _PMREG(0x0D0)
-#define LPC32XX_CLKPWR_UART4_CLK_CTRL _PMREG(0x0D4)
-#define LPC32XX_CLKPWR_UART5_CLK_CTRL _PMREG(0x0D8)
-#define LPC32XX_CLKPWR_UART6_CLK_CTRL _PMREG(0x0DC)
-#define LPC32XX_CLKPWR_IRDA_CLK_CTRL _PMREG(0x0E0)
-#define LPC32XX_CLKPWR_UART_CLK_CTRL _PMREG(0x0E4)
-#define LPC32XX_CLKPWR_DMA_CLK_CTRL _PMREG(0x0E8)
-#define LPC32XX_CLKPWR_AUTOCLOCK _PMREG(0x0EC)
-#define LPC32XX_CLKPWR_DEVID(x) _PMREG(0x130 + (x))
-
-/*
- * clkpwr_debug_ctrl register definitions
-*/
-#define LPC32XX_CLKPWR_VFP_CLOCK_ENABLE_BIT _BIT(4)
-
-/*
- * clkpwr_bootmap register definitions
- */
-#define LPC32XX_CLKPWR_BOOTMAP_SEL_BIT _BIT(1)
-
-/*
- * clkpwr_start_gpio register bit definitions
- */
-#define LPC32XX_CLKPWR_GPIOSRC_P1IO23_BIT _BIT(31)
-#define LPC32XX_CLKPWR_GPIOSRC_P1IO22_BIT _BIT(30)
-#define LPC32XX_CLKPWR_GPIOSRC_P1IO21_BIT _BIT(29)
-#define LPC32XX_CLKPWR_GPIOSRC_P1IO20_BIT _BIT(28)
-#define LPC32XX_CLKPWR_GPIOSRC_P1IO19_BIT _BIT(27)
-#define LPC32XX_CLKPWR_GPIOSRC_P1IO18_BIT _BIT(26)
-#define LPC32XX_CLKPWR_GPIOSRC_P1IO17_BIT _BIT(25)
-#define LPC32XX_CLKPWR_GPIOSRC_P1IO16_BIT _BIT(24)
-#define LPC32XX_CLKPWR_GPIOSRC_P1IO15_BIT _BIT(23)
-#define LPC32XX_CLKPWR_GPIOSRC_P1IO14_BIT _BIT(22)
-#define LPC32XX_CLKPWR_GPIOSRC_P1IO13_BIT _BIT(21)
-#define LPC32XX_CLKPWR_GPIOSRC_P1IO12_BIT _BIT(20)
-#define LPC32XX_CLKPWR_GPIOSRC_P1IO11_BIT _BIT(19)
-#define LPC32XX_CLKPWR_GPIOSRC_P1IO10_BIT _BIT(18)
-#define LPC32XX_CLKPWR_GPIOSRC_P1IO9_BIT _BIT(17)
-#define LPC32XX_CLKPWR_GPIOSRC_P1IO8_BIT _BIT(16)
-#define LPC32XX_CLKPWR_GPIOSRC_P1IO7_BIT _BIT(15)
-#define LPC32XX_CLKPWR_GPIOSRC_P1IO6_BIT _BIT(14)
-#define LPC32XX_CLKPWR_GPIOSRC_P1IO5_BIT _BIT(13)
-#define LPC32XX_CLKPWR_GPIOSRC_P1IO4_BIT _BIT(12)
-#define LPC32XX_CLKPWR_GPIOSRC_P1IO3_BIT _BIT(11)
-#define LPC32XX_CLKPWR_GPIOSRC_P1IO2_BIT _BIT(10)
-#define LPC32XX_CLKPWR_GPIOSRC_P1IO1_BIT _BIT(9)
-#define LPC32XX_CLKPWR_GPIOSRC_P1IO0_BIT _BIT(8)
-#define LPC32XX_CLKPWR_GPIOSRC_P0IO7_BIT _BIT(7)
-#define LPC32XX_CLKPWR_GPIOSRC_P0IO6_BIT _BIT(6)
-#define LPC32XX_CLKPWR_GPIOSRC_P0IO5_BIT _BIT(5)
-#define LPC32XX_CLKPWR_GPIOSRC_P0IO4_BIT _BIT(4)
-#define LPC32XX_CLKPWR_GPIOSRC_P0IO3_BIT _BIT(3)
-#define LPC32XX_CLKPWR_GPIOSRC_P0IO2_BIT _BIT(2)
-#define LPC32XX_CLKPWR_GPIOSRC_P0IO1_BIT _BIT(1)
-#define LPC32XX_CLKPWR_GPIOSRC_P0IO0_BIT _BIT(0)
-
-/*
- * clkpwr_usbclk_pdiv register definitions
- */
-#define LPC32XX_CLKPWR_USBPDIV_PLL_MASK 0xF
-
-/*
- * clkpwr_start_int, clkpwr_start_raw_sts_int, clkpwr_start_sts_int,
- * clkpwr_start_pol_int, register bit definitions
- */
-#define LPC32XX_CLKPWR_INTSRC_ADC_BIT _BIT(31)
-#define LPC32XX_CLKPWR_INTSRC_TS_P_BIT _BIT(30)
-#define LPC32XX_CLKPWR_INTSRC_TS_AUX_BIT _BIT(29)
-#define LPC32XX_CLKPWR_INTSRC_USBAHNEEDCLK_BIT _BIT(26)
-#define LPC32XX_CLKPWR_INTSRC_MSTIMER_BIT _BIT(25)
-#define LPC32XX_CLKPWR_INTSRC_RTC_BIT _BIT(24)
-#define LPC32XX_CLKPWR_INTSRC_USBNEEDCLK_BIT _BIT(23)
-#define LPC32XX_CLKPWR_INTSRC_USB_BIT _BIT(22)
-#define LPC32XX_CLKPWR_INTSRC_I2C_BIT _BIT(21)
-#define LPC32XX_CLKPWR_INTSRC_USBOTGTIMER_BIT _BIT(20)
-#define LPC32XX_CLKPWR_INTSRC_USBATXINT_BIT _BIT(19)
-#define LPC32XX_CLKPWR_INTSRC_KEY_BIT _BIT(16)
-#define LPC32XX_CLKPWR_INTSRC_MAC_BIT _BIT(7)
-#define LPC32XX_CLKPWR_INTSRC_P0P1_BIT _BIT(6)
-#define LPC32XX_CLKPWR_INTSRC_GPIO_05_BIT _BIT(5)
-#define LPC32XX_CLKPWR_INTSRC_GPIO_04_BIT _BIT(4)
-#define LPC32XX_CLKPWR_INTSRC_GPIO_03_BIT _BIT(3)
-#define LPC32XX_CLKPWR_INTSRC_GPIO_02_BIT _BIT(2)
-#define LPC32XX_CLKPWR_INTSRC_GPIO_01_BIT _BIT(1)
-#define LPC32XX_CLKPWR_INTSRC_GPIO_00_BIT _BIT(0)
-
-/*
- * clkpwr_start_pin, clkpwr_start_raw_sts_pin, clkpwr_start_sts_pin,
- * clkpwr_start_pol_pin register bit definitions
- */
-#define LPC32XX_CLKPWR_EXTSRC_U7_RX_BIT _BIT(31)
-#define LPC32XX_CLKPWR_EXTSRC_U7_HCTS_BIT _BIT(30)
-#define LPC32XX_CLKPWR_EXTSRC_U6_IRRX_BIT _BIT(28)
-#define LPC32XX_CLKPWR_EXTSRC_U5_RX_BIT _BIT(26)
-#define LPC32XX_CLKPWR_EXTSRC_GPI_28_BIT _BIT(25)
-#define LPC32XX_CLKPWR_EXTSRC_U3_RX_BIT _BIT(24)
-#define LPC32XX_CLKPWR_EXTSRC_U2_HCTS_BIT _BIT(23)
-#define LPC32XX_CLKPWR_EXTSRC_U2_RX_BIT _BIT(22)
-#define LPC32XX_CLKPWR_EXTSRC_U1_RX_BIT _BIT(21)
-#define LPC32XX_CLKPWR_EXTSRC_MSDIO_INT_BIT _BIT(18)
-#define LPC32XX_CLKPWR_EXTSRC_MSDIO_SRT_BIT _BIT(17)
-#define LPC32XX_CLKPWR_EXTSRC_GPI_06_BIT _BIT(16)
-#define LPC32XX_CLKPWR_EXTSRC_GPI_05_BIT _BIT(15)
-#define LPC32XX_CLKPWR_EXTSRC_GPI_04_BIT _BIT(14)
-#define LPC32XX_CLKPWR_EXTSRC_GPI_03_BIT _BIT(13)
-#define LPC32XX_CLKPWR_EXTSRC_GPI_02_BIT _BIT(12)
-#define LPC32XX_CLKPWR_EXTSRC_GPI_01_BIT _BIT(11)
-#define LPC32XX_CLKPWR_EXTSRC_GPI_00_BIT _BIT(10)
-#define LPC32XX_CLKPWR_EXTSRC_SYSCLKEN_BIT _BIT(9)
-#define LPC32XX_CLKPWR_EXTSRC_SPI1_DATIN_BIT _BIT(8)
-#define LPC32XX_CLKPWR_EXTSRC_GPI_07_BIT _BIT(7)
-#define LPC32XX_CLKPWR_EXTSRC_SPI2_DATIN_BIT _BIT(6)
-#define LPC32XX_CLKPWR_EXTSRC_GPI_19_BIT _BIT(5)
-#define LPC32XX_CLKPWR_EXTSRC_GPI_09_BIT _BIT(4)
-#define LPC32XX_CLKPWR_EXTSRC_GPI_08_BIT _BIT(3)
-
-/*
- * clkpwr_hclk_div register definitions
- */
-#define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_STOP (0x0 << 7)
-#define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_NORM (0x1 << 7)
-#define LPC32XX_CLKPWR_HCLKDIV_DDRCLK_HALF (0x2 << 7)
-#define LPC32XX_CLKPWR_HCLKDIV_PCLK_DIV(n) (((n) & 0x1F) << 2)
-#define LPC32XX_CLKPWR_HCLKDIV_DIV_2POW(n) ((n) & 0x3)
-
-/*
- * clkpwr_pwr_ctrl register definitions
- */
-#define LPC32XX_CLKPWR_CTRL_FORCE_PCLK _BIT(10)
-#define LPC32XX_CLKPWR_SDRAM_SELF_RFSH _BIT(9)
-#define LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH _BIT(8)
-#define LPC32XX_CLKPWR_AUTO_SDRAM_SELF_RFSH _BIT(7)
-#define LPC32XX_CLKPWR_HIGHCORE_STATE_BIT _BIT(5)
-#define LPC32XX_CLKPWR_SYSCLKEN_STATE_BIT _BIT(4)
-#define LPC32XX_CLKPWR_SYSCLKEN_GPIO_EN _BIT(3)
-#define LPC32XX_CLKPWR_SELECT_RUN_MODE _BIT(2)
-#define LPC32XX_CLKPWR_HIGHCORE_GPIO_EN _BIT(1)
-#define LPC32XX_CLKPWR_STOP_MODE_CTRL _BIT(0)
-
-/*
- * clkpwr_pll397_ctrl register definitions
- */
-#define LPC32XX_CLKPWR_PLL397_MSLOCK_STS _BIT(10)
-#define LPC32XX_CLKPWR_PLL397_BYPASS _BIT(9)
-#define LPC32XX_CLKPWR_PLL397_BIAS_NORM 0x000
-#define LPC32XX_CLKPWR_PLL397_BIAS_N12_5 0x040
-#define LPC32XX_CLKPWR_PLL397_BIAS_N25 0x080
-#define LPC32XX_CLKPWR_PLL397_BIAS_N37_5 0x0C0
-#define LPC32XX_CLKPWR_PLL397_BIAS_P12_5 0x100
-#define LPC32XX_CLKPWR_PLL397_BIAS_P25 0x140
-#define LPC32XX_CLKPWR_PLL397_BIAS_P37_5 0x180
-#define LPC32XX_CLKPWR_PLL397_BIAS_P50 0x1C0
-#define LPC32XX_CLKPWR_PLL397_BIAS_MASK 0x1C0
-#define LPC32XX_CLKPWR_SYSCTRL_PLL397_DIS _BIT(1)
-#define LPC32XX_CLKPWR_SYSCTRL_PLL397_STS _BIT(0)
-
-/*
- * clkpwr_main_osc_ctrl register definitions
- */
-#define LPC32XX_CLKPWR_MOSC_ADD_CAP(n) (((n) & 0x7F) << 2)
-#define LPC32XX_CLKPWR_MOSC_CAP_MASK (0x7F << 2)
-#define LPC32XX_CLKPWR_TEST_MODE _BIT(1)
-#define LPC32XX_CLKPWR_MOSC_DISABLE _BIT(0)
-
-/*
- * clkpwr_sysclk_ctrl register definitions
- */
-#define LPC32XX_CLKPWR_SYSCTRL_BP_TRIG(n) (((n) & 0x3FF) << 2)
-#define LPC32XX_CLKPWR_SYSCTRL_BP_MASK (0x3FF << 2)
-#define LPC32XX_CLKPWR_SYSCTRL_USEPLL397 _BIT(1)
-#define LPC32XX_CLKPWR_SYSCTRL_SYSCLKMUX _BIT(0)
-
-/*
- * clkpwr_lcdclk_ctrl register definitions
- */
-#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT12 0x000
-#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16 0x040
-#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT15 0x080
-#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT24 0x0C0
-#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_STN4M 0x100
-#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_STN8C 0x140
-#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_DSTN4M 0x180
-#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_DSTN8C 0x1C0
-#define LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK 0x01C0
-#define LPC32XX_CLKPWR_LCDCTRL_CLK_EN 0x020
-#define LPC32XX_CLKPWR_LCDCTRL_SET_PSCALE(n) ((n - 1) & 0x1F)
-#define LPC32XX_CLKPWR_LCDCTRL_PSCALE_MSK 0x001F
-
-/*
- * clkpwr_hclkpll_ctrl register definitions
- */
-#define LPC32XX_CLKPWR_HCLKPLL_POWER_UP _BIT(16)
-#define LPC32XX_CLKPWR_HCLKPLL_CCO_BYPASS _BIT(15)
-#define LPC32XX_CLKPWR_HCLKPLL_POSTDIV_BYPASS _BIT(14)
-#define LPC32XX_CLKPWR_HCLKPLL_FDBK_SEL_FCLK _BIT(13)
-#define LPC32XX_CLKPWR_HCLKPLL_POSTDIV_2POW(n) (((n) & 0x3) << 11)
-#define LPC32XX_CLKPWR_HCLKPLL_PREDIV_PLUS1(n) (((n) & 0x3) << 9)
-#define LPC32XX_CLKPWR_HCLKPLL_PLLM(n) (((n) & 0xFF) << 1)
-#define LPC32XX_CLKPWR_HCLKPLL_PLL_STS _BIT(0)
-
-/*
- * clkpwr_adc_clk_ctrl_1 register definitions
- */
-#define LPC32XX_CLKPWR_ADCCTRL1_RTDIV(n) (((n) & 0xFF) << 0)
-#define LPC32XX_CLKPWR_ADCCTRL1_PCLK_SEL _BIT(8)
-
-/*
- * clkpwr_usb_ctrl register definitions
- */
-#define LPC32XX_CLKPWR_USBCTRL_HCLK_EN _BIT(24)
-#define LPC32XX_CLKPWR_USBCTRL_USBI2C_EN _BIT(23)
-#define LPC32XX_CLKPWR_USBCTRL_USBDVND_EN _BIT(22)
-#define LPC32XX_CLKPWR_USBCTRL_USBHSTND_EN _BIT(21)
-#define LPC32XX_CLKPWR_USBCTRL_PU_ADD (0x0 << 19)
-#define LPC32XX_CLKPWR_USBCTRL_BUS_KEEPER (0x1 << 19)
-#define LPC32XX_CLKPWR_USBCTRL_PD_ADD (0x3 << 19)
-#define LPC32XX_CLKPWR_USBCTRL_CLK_EN2 _BIT(18)
-#define LPC32XX_CLKPWR_USBCTRL_CLK_EN1 _BIT(17)
-#define LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP _BIT(16)
-#define LPC32XX_CLKPWR_USBCTRL_CCO_BYPASS _BIT(15)
-#define LPC32XX_CLKPWR_USBCTRL_POSTDIV_BYPASS _BIT(14)
-#define LPC32XX_CLKPWR_USBCTRL_FDBK_SEL_FCLK _BIT(13)
-#define LPC32XX_CLKPWR_USBCTRL_POSTDIV_2POW(n) (((n) & 0x3) << 11)
-#define LPC32XX_CLKPWR_USBCTRL_PREDIV_PLUS1(n) (((n) & 0x3) << 9)
-#define LPC32XX_CLKPWR_USBCTRL_FDBK_PLUS1(n) (((n) & 0xFF) << 1)
-#define LPC32XX_CLKPWR_USBCTRL_PLL_STS _BIT(0)
-
-/*
- * clkpwr_sdramclk_ctrl register definitions
- */
-#define LPC32XX_CLKPWR_SDRCLK_FASTSLEW_CLK _BIT(22)
-#define LPC32XX_CLKPWR_SDRCLK_FASTSLEW _BIT(21)
-#define LPC32XX_CLKPWR_SDRCLK_FASTSLEW_DAT _BIT(20)
-#define LPC32XX_CLKPWR_SDRCLK_SW_DDR_RESET _BIT(19)
-#define LPC32XX_CLKPWR_SDRCLK_HCLK_DLY(n) (((n) & 0x1F) << 14)
-#define LPC32XX_CLKPWR_SDRCLK_DLY_ADDR_STS _BIT(13)
-#define LPC32XX_CLKPWR_SDRCLK_SENS_FACT(n) (((n) & 0x7) << 10)
-#define LPC32XX_CLKPWR_SDRCLK_USE_CAL _BIT(9)
-#define LPC32XX_CLKPWR_SDRCLK_DO_CAL _BIT(8)
-#define LPC32XX_CLKPWR_SDRCLK_CAL_ON_RTC _BIT(7)
-#define LPC32XX_CLKPWR_SDRCLK_DQS_DLY(n) (((n) & 0x1F) << 2)
-#define LPC32XX_CLKPWR_SDRCLK_USE_DDR _BIT(1)
-#define LPC32XX_CLKPWR_SDRCLK_CLK_DIS _BIT(0)
-
-/*
- * clkpwr_ssp_blk_ctrl register definitions
- */
-#define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP1RX _BIT(5)
-#define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP1TX _BIT(4)
-#define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP0RX _BIT(3)
-#define LPC32XX_CLKPWR_SSPCTRL_DMA_SSP0TX _BIT(2)
-#define LPC32XX_CLKPWR_SSPCTRL_SSPCLK1_EN _BIT(1)
-#define LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN _BIT(0)
-
-/*
- * clkpwr_i2s_clk_ctrl register definitions
- */
-#define LPC32XX_CLKPWR_I2SCTRL_I2S1_RX_FOR_TX _BIT(6)
-#define LPC32XX_CLKPWR_I2SCTRL_I2S1_TX_FOR_RX _BIT(5)
-#define LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA _BIT(4)
-#define LPC32XX_CLKPWR_I2SCTRL_I2S0_RX_FOR_TX _BIT(3)
-#define LPC32XX_CLKPWR_I2SCTRL_I2S0_TX_FOR_RX _BIT(2)
-#define LPC32XX_CLKPWR_I2SCTRL_I2SCLK1_EN _BIT(1)
-#define LPC32XX_CLKPWR_I2SCTRL_I2SCLK0_EN _BIT(0)
-
-/*
- * clkpwr_ms_ctrl register definitions
- */
-#define LPC32XX_CLKPWR_MSCARD_MSDIO_PIN_DIS _BIT(10)
-#define LPC32XX_CLKPWR_MSCARD_MSDIO_PU_EN _BIT(9)
-#define LPC32XX_CLKPWR_MSCARD_MSDIO23_DIS _BIT(8)
-#define LPC32XX_CLKPWR_MSCARD_MSDIO1_DIS _BIT(7)
-#define LPC32XX_CLKPWR_MSCARD_MSDIO0_DIS _BIT(6)
-#define LPC32XX_CLKPWR_MSCARD_SDCARD_EN _BIT(5)
-#define LPC32XX_CLKPWR_MSCARD_SDCARD_DIV(n) ((n) & 0xF)
-
-/*
- * clkpwr_macclk_ctrl register definitions
- */
-#define LPC32XX_CLKPWR_MACCTRL_NO_ENET_PIS 0x00
-#define LPC32XX_CLKPWR_MACCTRL_USE_MII_PINS 0x08
-#define LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS 0x18
-#define LPC32XX_CLKPWR_MACCTRL_PINS_MSK 0x18
-#define LPC32XX_CLKPWR_MACCTRL_DMACLK_EN _BIT(2)
-#define LPC32XX_CLKPWR_MACCTRL_MMIOCLK_EN _BIT(1)
-#define LPC32XX_CLKPWR_MACCTRL_HRCCLK_EN _BIT(0)
-
-/*
- * clkpwr_test_clk_sel register definitions
- */
-#define LPC32XX_CLKPWR_TESTCLK1_SEL_PERCLK (0x0 << 5)
-#define LPC32XX_CLKPWR_TESTCLK1_SEL_RTC (0x1 << 5)
-#define LPC32XX_CLKPWR_TESTCLK1_SEL_MOSC (0x2 << 5)
-#define LPC32XX_CLKPWR_TESTCLK1_SEL_MASK (0x3 << 5)
-#define LPC32XX_CLKPWR_TESTCLK_TESTCLK1_EN _BIT(4)
-#define LPC32XX_CLKPWR_TESTCLK2_SEL_HCLK (0x0 << 1)
-#define LPC32XX_CLKPWR_TESTCLK2_SEL_PERCLK (0x1 << 1)
-#define LPC32XX_CLKPWR_TESTCLK2_SEL_USBCLK (0x2 << 1)
-#define LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC (0x5 << 1)
-#define LPC32XX_CLKPWR_TESTCLK2_SEL_PLL397 (0x7 << 1)
-#define LPC32XX_CLKPWR_TESTCLK2_SEL_MASK (0x7 << 1)
-#define LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN _BIT(0)
-
-/*
- * clkpwr_sw_int register definitions
- */
-#define LPC32XX_CLKPWR_SW_INT(n) (_BIT(0) | (((n) & 0x7F) << 1))
-#define LPC32XX_CLKPWR_SW_GET_ARG(n) (((n) & 0xFE) >> 1)
-
-/*
- * clkpwr_i2c_clk_ctrl register definitions
- */
-#define LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE _BIT(4)
-#define LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE _BIT(3)
-#define LPC32XX_CLKPWR_I2CCLK_I2C1HI_DRIVE _BIT(2)
-#define LPC32XX_CLKPWR_I2CCLK_I2C2CLK_EN _BIT(1)
-#define LPC32XX_CLKPWR_I2CCLK_I2C1CLK_EN _BIT(0)
-
-/*
- * clkpwr_key_clk_ctrl register definitions
- */
-#define LPC32XX_CLKPWR_KEYCLKCTRL_CLK_EN 0x1
-
-/*
- * clkpwr_adc_clk_ctrl register definitions
- */
-#define LPC32XX_CLKPWR_ADC32CLKCTRL_CLK_EN 0x1
-
-/*
- * clkpwr_pwm_clk_ctrl register definitions
- */
-#define LPC32XX_CLKPWR_PWMCLK_PWM2_DIV(n) (((n) & 0xF) << 8)
-#define LPC32XX_CLKPWR_PWMCLK_PWM1_DIV(n) (((n) & 0xF) << 4)
-#define LPC32XX_CLKPWR_PWMCLK_PWM2SEL_PCLK 0x8
-#define LPC32XX_CLKPWR_PWMCLK_PWM2CLK_EN 0x4
-#define LPC32XX_CLKPWR_PWMCLK_PWM1SEL_PCLK 0x2
-#define LPC32XX_CLKPWR_PWMCLK_PWM1CLK_EN 0x1
-
-/*
- * clkpwr_timer_clk_ctrl register definitions
- */
-#define LPC32XX_CLKPWR_PWMCLK_HSTIMER_EN 0x2
-#define LPC32XX_CLKPWR_PWMCLK_WDOG_EN 0x1
-
-/*
- * clkpwr_timers_pwms_clk_ctrl_1 register definitions
- */
-#define LPC32XX_CLKPWR_TMRPWMCLK_MPWM_EN 0x40
-#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER3_EN 0x20
-#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER2_EN 0x10
-#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER1_EN 0x08
-#define LPC32XX_CLKPWR_TMRPWMCLK_TIMER0_EN 0x04
-#define LPC32XX_CLKPWR_TMRPWMCLK_PWM4_EN 0x02
-#define LPC32XX_CLKPWR_TMRPWMCLK_PWM3_EN 0x01
-
-/*
- * clkpwr_spi_clk_ctrl register definitions
- */
-#define LPC32XX_CLKPWR_SPICLK_SET_SPI2DATIO 0x80
-#define LPC32XX_CLKPWR_SPICLK_SET_SPI2CLK 0x40
-#define LPC32XX_CLKPWR_SPICLK_USE_SPI2 0x20
-#define LPC32XX_CLKPWR_SPICLK_SPI2CLK_EN 0x10
-#define LPC32XX_CLKPWR_SPICLK_SET_SPI1DATIO 0x08
-#define LPC32XX_CLKPWR_SPICLK_SET_SPI1CLK 0x04
-#define LPC32XX_CLKPWR_SPICLK_USE_SPI1 0x02
-#define LPC32XX_CLKPWR_SPICLK_SPI1CLK_EN 0x01
-
-/*
- * clkpwr_nand_clk_ctrl register definitions
- */
-#define LPC32XX_CLKPWR_NANDCLK_INTSEL_MLC 0x20
-#define LPC32XX_CLKPWR_NANDCLK_DMA_RNB 0x10
-#define LPC32XX_CLKPWR_NANDCLK_DMA_INT 0x08
-#define LPC32XX_CLKPWR_NANDCLK_SEL_SLC 0x04
-#define LPC32XX_CLKPWR_NANDCLK_MLCCLK_EN 0x02
-#define LPC32XX_CLKPWR_NANDCLK_SLCCLK_EN 0x01
-
-/*
- * clkpwr_uart3_clk_ctrl, clkpwr_uart4_clk_ctrl, clkpwr_uart5_clk_ctrl
- * and clkpwr_uart6_clk_ctrl register definitions
- */
-#define LPC32XX_CLKPWR_UART_Y_DIV(y) ((y) & 0xFF)
-#define LPC32XX_CLKPWR_UART_X_DIV(x) (((x) & 0xFF) << 8)
-#define LPC32XX_CLKPWR_UART_USE_HCLK _BIT(16)
-
-/*
- * clkpwr_irda_clk_ctrl register definitions
- */
-#define LPC32XX_CLKPWR_IRDA_Y_DIV(y) ((y) & 0xFF)
-#define LPC32XX_CLKPWR_IRDA_X_DIV(x) (((x) & 0xFF) << 8)
-
-/*
- * clkpwr_uart_clk_ctrl register definitions
- */
-#define LPC32XX_CLKPWR_UARTCLKCTRL_UART6_EN _BIT(3)
-#define LPC32XX_CLKPWR_UARTCLKCTRL_UART5_EN _BIT(2)
-#define LPC32XX_CLKPWR_UARTCLKCTRL_UART4_EN _BIT(1)
-#define LPC32XX_CLKPWR_UARTCLKCTRL_UART3_EN _BIT(0)
-
-/*
- * clkpwr_dmaclk_ctrl register definitions
- */
-#define LPC32XX_CLKPWR_DMACLKCTRL_CLK_EN 0x1
-
-/*
- * clkpwr_autoclock register definitions
- */
-#define LPC32XX_CLKPWR_AUTOCLK_USB_EN 0x40
-#define LPC32XX_CLKPWR_AUTOCLK_IRAM_EN 0x02
-#define LPC32XX_CLKPWR_AUTOCLK_IROM_EN 0x01
-
-/*
- * Interrupt controller register offsets
- */
-#define LPC32XX_INTC_MASK(x) io_p2v((x) + 0x00)
-#define LPC32XX_INTC_RAW_STAT(x) io_p2v((x) + 0x04)
-#define LPC32XX_INTC_STAT(x) io_p2v((x) + 0x08)
-#define LPC32XX_INTC_POLAR(x) io_p2v((x) + 0x0C)
-#define LPC32XX_INTC_ACT_TYPE(x) io_p2v((x) + 0x10)
-#define LPC32XX_INTC_TYPE(x) io_p2v((x) + 0x14)
-
-/*
- * Timer/counter register offsets
- */
-#define LPC32XX_TIMER_IR(x) io_p2v((x) + 0x00)
-#define LPC32XX_TIMER_TCR(x) io_p2v((x) + 0x04)
-#define LPC32XX_TIMER_TC(x) io_p2v((x) + 0x08)
-#define LPC32XX_TIMER_PR(x) io_p2v((x) + 0x0C)
-#define LPC32XX_TIMER_PC(x) io_p2v((x) + 0x10)
-#define LPC32XX_TIMER_MCR(x) io_p2v((x) + 0x14)
-#define LPC32XX_TIMER_MR0(x) io_p2v((x) + 0x18)
-#define LPC32XX_TIMER_MR1(x) io_p2v((x) + 0x1C)
-#define LPC32XX_TIMER_MR2(x) io_p2v((x) + 0x20)
-#define LPC32XX_TIMER_MR3(x) io_p2v((x) + 0x24)
-#define LPC32XX_TIMER_CCR(x) io_p2v((x) + 0x28)
-#define LPC32XX_TIMER_CR0(x) io_p2v((x) + 0x2C)
-#define LPC32XX_TIMER_CR1(x) io_p2v((x) + 0x30)
-#define LPC32XX_TIMER_CR2(x) io_p2v((x) + 0x34)
-#define LPC32XX_TIMER_CR3(x) io_p2v((x) + 0x38)
-#define LPC32XX_TIMER_EMR(x) io_p2v((x) + 0x3C)
-#define LPC32XX_TIMER_CTCR(x) io_p2v((x) + 0x70)
-
-/*
- * ir register definitions
- */
-#define LPC32XX_TIMER_CNTR_MTCH_BIT(n) (1 << ((n) & 0x3))
-#define LPC32XX_TIMER_CNTR_CAPT_BIT(n) (1 << (4 + ((n) & 0x3)))
-
-/*
- * tcr register definitions
- */
-#define LPC32XX_TIMER_CNTR_TCR_EN 0x1
-#define LPC32XX_TIMER_CNTR_TCR_RESET 0x2
-
-/*
- * mcr register definitions
- */
-#define LPC32XX_TIMER_CNTR_MCR_MTCH(n) (0x1 << ((n) * 3))
-#define LPC32XX_TIMER_CNTR_MCR_RESET(n) (0x1 << (((n) * 3) + 1))
-#define LPC32XX_TIMER_CNTR_MCR_STOP(n) (0x1 << (((n) * 3) + 2))
-
-/*
- * Standard UART register offsets
- */
-#define LPC32XX_UART_DLL_FIFO(x) io_p2v((x) + 0x00)
-#define LPC32XX_UART_DLM_IER(x) io_p2v((x) + 0x04)
-#define LPC32XX_UART_IIR_FCR(x) io_p2v((x) + 0x08)
-#define LPC32XX_UART_LCR(x) io_p2v((x) + 0x0C)
-#define LPC32XX_UART_MODEM_CTRL(x) io_p2v((x) + 0x10)
-#define LPC32XX_UART_LSR(x) io_p2v((x) + 0x14)
-#define LPC32XX_UART_MODEM_STATUS(x) io_p2v((x) + 0x18)
-#define LPC32XX_UART_RXLEV(x) io_p2v((x) + 0x1C)
-
-/*
- * UART control structure offsets
- */
-#define _UCREG(x) io_p2v(\
- LPC32XX_UART_CTRL_BASE + (x))
-#define LPC32XX_UARTCTL_CTRL _UCREG(0x00)
-#define LPC32XX_UARTCTL_CLKMODE _UCREG(0x04)
-#define LPC32XX_UARTCTL_CLOOP _UCREG(0x08)
-
-/*
- * ctrl register definitions
- */
-#define LPC32XX_UART_U3_MD_CTRL_EN _BIT(11)
-#define LPC32XX_UART_IRRX6_INV_EN _BIT(10)
-#define LPC32XX_UART_HDPX_EN _BIT(9)
-#define LPC32XX_UART_UART6_IRDAMOD_BYPASS _BIT(5)
-#define LPC32XX_RT_IRTX6_INV_EN _BIT(4)
-#define LPC32XX_RT_IRTX6_INV_MIR_EN _BIT(3)
-#define LPC32XX_RT_RX_IRPULSE_3_16_115K _BIT(2)
-#define LPC32XX_RT_TX_IRPULSE_3_16_115K _BIT(1)
-#define LPC32XX_UART_U5_ROUTE_TO_USB _BIT(0)
-
-/*
- * clkmode register definitions
- */
-#define LPC32XX_UART_ENABLED_CLOCKS(n) (((n) >> 16) & 0x7F)
-#define LPC32XX_UART_ENABLED_CLOCK(n, u) (((n) >> (16 + (u))) & 0x1)
-#define LPC32XX_UART_ENABLED_CLKS_ANY _BIT(14)
-#define LPC32XX_UART_CLKMODE_OFF 0x0
-#define LPC32XX_UART_CLKMODE_ON 0x1
-#define LPC32XX_UART_CLKMODE_AUTO 0x2
-#define LPC32XX_UART_CLKMODE_MASK(u) (0x3 << ((((u) - 3) * 2) + 4))
-#define LPC32XX_UART_CLKMODE_LOAD(m, u) ((m) << ((((u) - 3) * 2) + 4))
-
-/*
- * GPIO Module Register offsets
- */
-#define _GPREG(x) io_p2v(LPC32XX_GPIO_BASE + (x))
-#define LPC32XX_GPIO_P_MUX_SET _GPREG(0x100)
-#define LPC32XX_GPIO_P_MUX_CLR _GPREG(0x104)
-#define LPC32XX_GPIO_P_MUX_STATE _GPREG(0x108)
-#define LPC32XX_GPIO_P3_MUX_SET _GPREG(0x110)
-#define LPC32XX_GPIO_P3_MUX_CLR _GPREG(0x114)
-#define LPC32XX_GPIO_P3_MUX_STATE _GPREG(0x118)
-#define LPC32XX_GPIO_P0_MUX_SET _GPREG(0x120)
-#define LPC32XX_GPIO_P0_MUX_CLR _GPREG(0x124)
-#define LPC32XX_GPIO_P0_MUX_STATE _GPREG(0x128)
-#define LPC32XX_GPIO_P1_MUX_SET _GPREG(0x130)
-#define LPC32XX_GPIO_P1_MUX_CLR _GPREG(0x134)
-#define LPC32XX_GPIO_P1_MUX_STATE _GPREG(0x138)
-#define LPC32XX_GPIO_P2_MUX_SET _GPREG(0x028)
-#define LPC32XX_GPIO_P2_MUX_CLR _GPREG(0x02C)
-#define LPC32XX_GPIO_P2_MUX_STATE _GPREG(0x030)
-
-/*
- * USB Otg Registers
- */
-#define _OTGREG(x) io_p2v(LPC32XX_USB_OTG_BASE + (x))
-#define LPC32XX_USB_OTG_CLK_CTRL _OTGREG(0xFF4)
-#define LPC32XX_USB_OTG_CLK_STAT _OTGREG(0xFF8)
-
-/* USB OTG CLK CTRL bit defines */
-#define LPC32XX_USB_OTG_AHB_M_CLOCK_ON _BIT(4)
-#define LPC32XX_USB_OTG_OTG_CLOCK_ON _BIT(3)
-#define LPC32XX_USB_OTG_I2C_CLOCK_ON _BIT(2)
-#define LPC32XX_USB_OTG_DEV_CLOCK_ON _BIT(1)
-#define LPC32XX_USB_OTG_HOST_CLOCK_ON _BIT(0)
-
-/*
- * Start of virtual addresses for IO devices
- */
-#define IO_BASE 0xF0000000
-
-/*
- * This macro relies on fact that for all HW i/o addresses bits 20-23 are 0
- */
-#define IO_ADDRESS(x) IOMEM(((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) |\
- IO_BASE)
-
-#define io_p2v(x) ((void __iomem *) (unsigned long) IO_ADDRESS(x))
-#define io_v2p(x) ((((x) & 0x0ff00000) << 4) | ((x) & 0x000fffff))
-
-#endif
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
deleted file mode 100644
index 66701bf432488..0000000000000
--- a/arch/arm/mach-lpc32xx/phy3250.c
+++ /dev/null
@@ -1,92 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Platform support for LPC32xx SoC
- *
- * Author: Kevin Wells <kevin.wells@nxp.com>
- *
- * Copyright (C) 2012 Roland Stigge <stigge@antcom.de>
- * Copyright (C) 2010 NXP Semiconductors
- */
-
-#include <linux/amba/pl08x.h>
-#include <linux/mtd/lpc32xx_mlc.h>
-#include <linux/mtd/lpc32xx_slc.h>
-#include <linux/of_platform.h>
-
-#include <asm/mach/arch.h>
-#include "common.h"
-
-static struct pl08x_channel_data pl08x_slave_channels[] = {
- {
- .bus_id = "nand-slc",
- .min_signal = 1, /* SLC NAND Flash */
- .max_signal = 1,
- .periph_buses = PL08X_AHB1,
- },
- {
- .bus_id = "nand-mlc",
- .min_signal = 12, /* MLC NAND Flash */
- .max_signal = 12,
- .periph_buses = PL08X_AHB1,
- },
-};
-
-static int pl08x_get_signal(const struct pl08x_channel_data *cd)
-{
- return cd->min_signal;
-}
-
-static void pl08x_put_signal(const struct pl08x_channel_data *cd, int ch)
-{
-}
-
-static struct pl08x_platform_data pl08x_pd = {
- /* Some reasonable memcpy defaults */
- .memcpy_burst_size = PL08X_BURST_SZ_256,
- .memcpy_bus_width = PL08X_BUS_WIDTH_32_BITS,
- .slave_channels = &pl08x_slave_channels[0],
- .num_slave_channels = ARRAY_SIZE(pl08x_slave_channels),
- .get_xfer_signal = pl08x_get_signal,
- .put_xfer_signal = pl08x_put_signal,
- .lli_buses = PL08X_AHB1,
- .mem_buses = PL08X_AHB1,
-};
-
-static struct lpc32xx_slc_platform_data lpc32xx_slc_data = {
- .dma_filter = pl08x_filter_id,
-};
-
-static struct lpc32xx_mlc_platform_data lpc32xx_mlc_data = {
- .dma_filter = pl08x_filter_id,
-};
-
-static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = {
- OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd),
- OF_DEV_AUXDATA("nxp,lpc3220-slc", 0x20020000, "20020000.flash",
- &lpc32xx_slc_data),
- OF_DEV_AUXDATA("nxp,lpc3220-mlc", 0x200a8000, "200a8000.flash",
- &lpc32xx_mlc_data),
- { }
-};
-
-static void __init lpc3250_machine_init(void)
-{
- lpc32xx_serial_init();
-
- of_platform_default_populate(NULL, lpc32xx_auxdata_lookup, NULL);
-}
-
-static const char *const lpc32xx_dt_compat[] __initconst = {
- "nxp,lpc3220",
- "nxp,lpc3230",
- "nxp,lpc3240",
- "nxp,lpc3250",
- NULL
-};
-
-DT_MACHINE_START(LPC32XX_DT, "LPC32XX SoC (Flattened Device Tree)")
- .atag_offset = 0x100,
- .map_io = lpc32xx_map_io,
- .init_machine = lpc3250_machine_init,
- .dt_compat = lpc32xx_dt_compat,
-MACHINE_END
diff --git a/arch/arm/mach-lpc32xx/pm.c b/arch/arm/mach-lpc32xx/pm.c
deleted file mode 100644
index 2572bd89a5e8d..0000000000000
--- a/arch/arm/mach-lpc32xx/pm.c
+++ /dev/null
@@ -1,135 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * arch/arm/mach-lpc32xx/pm.c
- *
- * Original authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
- * Modified by Kevin Wells <kevin.wells@nxp.com>
- *
- * 2005 (c) MontaVista Software, Inc.
- */
-
-/*
- * LPC32XX CPU and system power management
- *
- * The LPC32XX has three CPU modes for controlling system power: run,
- * direct-run, and halt modes. When switching between halt and run modes,
- * the CPU transistions through direct-run mode. For Linux, direct-run
- * mode is not used in normal operation. Halt mode is used when the
- * system is fully suspended.
- *
- * Run mode:
- * The ARM CPU clock (HCLK_PLL), HCLK bus clock, and PCLK bus clocks are
- * derived from the HCLK PLL. The HCLK and PCLK bus rates are divided from
- * the HCLK_PLL rate. Linux runs in this mode.
- *
- * Direct-run mode:
- * The ARM CPU clock, HCLK bus clock, and PCLK bus clocks are driven from
- * SYSCLK. SYSCLK is usually around 13MHz, but may vary based on SYSCLK
- * source or the frequency of the main oscillator. In this mode, the
- * HCLK_PLL can be safely enabled, changed, or disabled.
- *
- * Halt mode:
- * SYSCLK is gated off and the CPU and system clocks are halted.
- * Peripherals based on the 32KHz oscillator clock (ie, RTC, touch,
- * key scanner, etc.) still operate if enabled. In this state, an enabled
- * system event (ie, GPIO state change, RTC match, key press, etc.) will
- * wake the system up back into direct-run mode.
- *
- * DRAM refresh
- * DRAM clocking and refresh are slightly different for systems with DDR
- * DRAM or regular SDRAM devices. If SDRAM is used in the system, the
- * SDRAM will still be accessible in direct-run mode. In DDR based systems,
- * a transition to direct-run mode will stop all DDR accesses (no clocks).
- * Because of this, the code to switch power modes and the code to enter
- * and exit DRAM self-refresh modes must not be executed in DRAM. A small
- * section of IRAM is used instead for this.
- *
- * Suspend is handled with the following logic:
- * Backup a small area of IRAM used for the suspend code
- * Copy suspend code to IRAM
- * Transfer control to code in IRAM
- * Places DRAMs in self-refresh mode
- * Enter direct-run mode
- * Save state of HCLK_PLL PLL
- * Disable HCLK_PLL PLL
- * Enter halt mode - CPU and buses will stop
- * System enters direct-run mode when an enabled event occurs
- * HCLK PLL state is restored
- * Run mode is entered
- * DRAMS are placed back into normal mode
- * Code execution returns from IRAM
- * IRAM code are used for suspend is restored
- * Suspend mode is exited
- */
-
-#include <linux/suspend.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-
-#include <asm/cacheflush.h>
-
-#include "lpc32xx.h"
-#include "common.h"
-
-#define TEMP_IRAM_AREA IO_ADDRESS(LPC32XX_IRAM_BASE)
-
-/*
- * Both STANDBY and MEM suspend states are handled the same with no
- * loss of CPU or memory state
- */
-static int lpc32xx_pm_enter(suspend_state_t state)
-{
- int (*lpc32xx_suspend_ptr) (void);
- void *iram_swap_area;
-
- /* Allocate some space for temporary IRAM storage */
- iram_swap_area = kmemdup((void *)TEMP_IRAM_AREA,
- lpc32xx_sys_suspend_sz, GFP_KERNEL);
- if (!iram_swap_area)
- return -ENOMEM;
-
- /*
- * Copy code to suspend system into IRAM. The suspend code
- * needs to run from IRAM as DRAM may no longer be available
- * when the PLL is stopped.
- */
- memcpy((void *) TEMP_IRAM_AREA, &lpc32xx_sys_suspend,
- lpc32xx_sys_suspend_sz);
- flush_icache_range((unsigned long)TEMP_IRAM_AREA,
- (unsigned long)(TEMP_IRAM_AREA) + lpc32xx_sys_suspend_sz);
-
- /* Transfer to suspend code in IRAM */
- lpc32xx_suspend_ptr = (void *) TEMP_IRAM_AREA;
- flush_cache_all();
- (void) lpc32xx_suspend_ptr();
-
- /* Restore original IRAM contents */
- memcpy((void *) TEMP_IRAM_AREA, iram_swap_area,
- lpc32xx_sys_suspend_sz);
-
- kfree(iram_swap_area);
-
- return 0;
-}
-
-static const struct platform_suspend_ops lpc32xx_pm_ops = {
- .valid = suspend_valid_only_mem,
- .enter = lpc32xx_pm_enter,
-};
-
-#define EMC_DYN_MEM_CTRL_OFS 0x20
-#define EMC_SRMMC (1 << 3)
-#define EMC_CTRL_REG io_p2v(LPC32XX_EMC_BASE + EMC_DYN_MEM_CTRL_OFS)
-static int __init lpc32xx_pm_init(void)
-{
- /*
- * Setup SDRAM self-refresh clock to automatically disable o
- * start of self-refresh. This only needs to be done once.
- */
- __raw_writel(__raw_readl(EMC_CTRL_REG) | EMC_SRMMC, EMC_CTRL_REG);
-
- suspend_set_ops(&lpc32xx_pm_ops);
-
- return 0;
-}
-arch_initcall(lpc32xx_pm_init);
diff --git a/arch/arm/mach-lpc32xx/serial.c b/arch/arm/mach-lpc32xx/serial.c
deleted file mode 100644
index 3b1203db81b2c..0000000000000
--- a/arch/arm/mach-lpc32xx/serial.c
+++ /dev/null
@@ -1,148 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * arch/arm/mach-lpc32xx/serial.c
- *
- * Author: Kevin Wells <kevin.wells@nxp.com>
- *
- * Copyright (C) 2010 NXP Semiconductors
- */
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/serial.h>
-#include <linux/serial_core.h>
-#include <linux/serial_reg.h>
-#include <linux/serial_8250.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/soc/nxp/lpc32xx-misc.h>
-
-#include "lpc32xx.h"
-#include "common.h"
-
-#define LPC32XX_SUART_FIFO_SIZE 64
-
-struct uartinit {
- char *uart_ck_name;
- u32 ck_mode_mask;
- void __iomem *pdiv_clk_reg;
- resource_size_t mapbase;
-};
-
-static struct uartinit uartinit_data[] __initdata = {
- {
- .uart_ck_name = "uart5_ck",
- .ck_mode_mask =
- LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 5),
- .pdiv_clk_reg = LPC32XX_CLKPWR_UART5_CLK_CTRL,
- .mapbase = LPC32XX_UART5_BASE,
- },
- {
- .uart_ck_name = "uart3_ck",
- .ck_mode_mask =
- LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 3),
- .pdiv_clk_reg = LPC32XX_CLKPWR_UART3_CLK_CTRL,
- .mapbase = LPC32XX_UART3_BASE,
- },
- {
- .uart_ck_name = "uart4_ck",
- .ck_mode_mask =
- LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 4),
- .pdiv_clk_reg = LPC32XX_CLKPWR_UART4_CLK_CTRL,
- .mapbase = LPC32XX_UART4_BASE,
- },
- {
- .uart_ck_name = "uart6_ck",
- .ck_mode_mask =
- LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 6),
- .pdiv_clk_reg = LPC32XX_CLKPWR_UART6_CLK_CTRL,
- .mapbase = LPC32XX_UART6_BASE,
- },
-};
-
-/* LPC3250 Errata HSUART.1: Hang workaround via loopback mode on inactivity */
-void lpc32xx_loopback_set(resource_size_t mapbase, int state)
-{
- int bit;
- u32 tmp;
-
- switch (mapbase) {
- case LPC32XX_HS_UART1_BASE:
- bit = 0;
- break;
- case LPC32XX_HS_UART2_BASE:
- bit = 1;
- break;
- case LPC32XX_HS_UART7_BASE:
- bit = 6;
- break;
- default:
- WARN(1, "lpc32xx_hs: Warning: Unknown port at %08x\n", mapbase);
- return;
- }
-
- tmp = readl(LPC32XX_UARTCTL_CLOOP);
- if (state)
- tmp |= (1 << bit);
- else
- tmp &= ~(1 << bit);
- writel(tmp, LPC32XX_UARTCTL_CLOOP);
-}
-EXPORT_SYMBOL_GPL(lpc32xx_loopback_set);
-
-void __init lpc32xx_serial_init(void)
-{
- u32 tmp, clkmodes = 0;
- struct clk *clk;
- unsigned int puart;
- int i, j;
-
- for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) {
- clk = clk_get(NULL, uartinit_data[i].uart_ck_name);
- if (!IS_ERR(clk)) {
- clk_enable(clk);
- }
-
- /* Setup UART clock modes for all UARTs, disable autoclock */
- clkmodes |= uartinit_data[i].ck_mode_mask;
-
- /* pre-UART clock divider set to 1 */
- __raw_writel(0x0101, uartinit_data[i].pdiv_clk_reg);
-
- /*
- * Force a flush of the RX FIFOs to work around a
- * HW bug
- */
- puart = uartinit_data[i].mapbase;
- __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart));
- __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart));
- j = LPC32XX_SUART_FIFO_SIZE;
- while (j--)
- tmp = __raw_readl(
- LPC32XX_UART_DLL_FIFO(puart));
- __raw_writel(0, LPC32XX_UART_IIR_FCR(puart));
- }
-
- /* This needs to be done after all UART clocks are setup */
- __raw_writel(clkmodes, LPC32XX_UARTCTL_CLKMODE);
- for (i = 0; i < ARRAY_SIZE(uartinit_data); i++) {
- /* Force a flush of the RX FIFOs to work around a HW bug */
- puart = uartinit_data[i].mapbase;
- __raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart));
- __raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart));
- j = LPC32XX_SUART_FIFO_SIZE;
- while (j--)
- tmp = __raw_readl(LPC32XX_UART_DLL_FIFO(puart));
- __raw_writel(0, LPC32XX_UART_IIR_FCR(puart));
- }
-
- /* Disable IrDA pulsing support on UART6 */
- tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
- tmp |= LPC32XX_UART_UART6_IRDAMOD_BYPASS;
- __raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
-
- /* Disable UART5->USB transparent mode or USB won't work */
- tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
- tmp &= ~LPC32XX_UART_U5_ROUTE_TO_USB;
- __raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
-}
diff --git a/arch/arm/mach-lpc32xx/suspend.S b/arch/arm/mach-lpc32xx/suspend.S
deleted file mode 100644
index a95c5e0e40384..0000000000000
--- a/arch/arm/mach-lpc32xx/suspend.S
+++ /dev/null
@@ -1,148 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * arch/arm/mach-lpc32xx/suspend.S
- *
- * Original authors: Dmitry Chigirev, Vitaly Wool <source@mvista.com>
- * Modified by Kevin Wells <kevin.wells@nxp.com>
- *
- * 2005 (c) MontaVista Software, Inc.
- */
-#include <linux/linkage.h>
-#include <asm/assembler.h>
-#include "lpc32xx.h"
-
-/* Using named register defines makes the code easier to follow */
-#define WORK1_REG r0
-#define WORK2_REG r1
-#define SAVED_HCLK_DIV_REG r2
-#define SAVED_HCLK_PLL_REG r3
-#define SAVED_DRAM_CLKCTRL_REG r4
-#define SAVED_PWR_CTRL_REG r5
-#define CLKPWRBASE_REG r6
-#define EMCBASE_REG r7
-
-#define LPC32XX_EMC_STATUS_OFFS 0x04
-#define LPC32XX_EMC_STATUS_BUSY 0x1
-#define LPC32XX_EMC_STATUS_SELF_RFSH 0x4
-
-#define LPC32XX_CLKPWR_PWR_CTRL_OFFS 0x44
-#define LPC32XX_CLKPWR_HCLK_DIV_OFFS 0x40
-#define LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS 0x58
-
-#define CLKPWR_PCLK_DIV_MASK 0xFFFFFE7F
-
- .text
-
-ENTRY(lpc32xx_sys_suspend)
- @ Save a copy of the used registers in IRAM, r0 is corrupted
- adr r0, tmp_stack_end
- stmfd r0!, {r3 - r7, sp, lr}
-
- @ Load a few common register addresses
- adr WORK1_REG, reg_bases
- ldr CLKPWRBASE_REG, [WORK1_REG, #0]
- ldr EMCBASE_REG, [WORK1_REG, #4]
-
- ldr SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
- #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
- orr WORK1_REG, SAVED_PWR_CTRL_REG, #LPC32XX_CLKPWR_SDRAM_SELF_RFSH
-
- @ Wait for SDRAM busy status to go busy and then idle
- @ This guarantees a small windows where DRAM isn't busy
-1:
- ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
- and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
- cmp WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
- bne 1b @ Branch while idle
-2:
- ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
- and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
- cmp WORK2_REG, #LPC32XX_EMC_STATUS_BUSY
- beq 2b @ Branch until idle
-
- @ Setup self-refresh with support for manual exit of
- @ self-refresh mode
- str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
- orr WORK2_REG, WORK1_REG, #LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH
- str WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
- str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
-
- @ Wait for self-refresh acknowledge, clocks to the DRAM device
- @ will automatically stop on start of self-refresh
-3:
- ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
- and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH
- cmp WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH
- bne 3b @ Branch until self-refresh mode starts
-
- @ Enter direct-run mode from run mode
- bic WORK1_REG, WORK1_REG, #LPC32XX_CLKPWR_SELECT_RUN_MODE
- str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
-
- @ Safe disable of DRAM clock in EMC block, prevents DDR sync
- @ issues on restart
- ldr SAVED_HCLK_DIV_REG, [CLKPWRBASE_REG,\
- #LPC32XX_CLKPWR_HCLK_DIV_OFFS]
- and WORK2_REG, SAVED_HCLK_DIV_REG, #CLKPWR_PCLK_DIV_MASK
- str WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLK_DIV_OFFS]
-
- @ Save HCLK PLL state and disable HCLK PLL
- ldr SAVED_HCLK_PLL_REG, [CLKPWRBASE_REG,\
- #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
- bic WORK2_REG, SAVED_HCLK_PLL_REG, #LPC32XX_CLKPWR_HCLKPLL_POWER_UP
- str WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
-
- @ Enter stop mode until an enabled event occurs
- orr WORK1_REG, WORK1_REG, #LPC32XX_CLKPWR_STOP_MODE_CTRL
- str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
- .rept 9
- nop
- .endr
-
- @ Clear stop status
- bic WORK1_REG, WORK1_REG, #LPC32XX_CLKPWR_STOP_MODE_CTRL
-
- @ Restore original HCLK PLL value and wait for PLL lock
- str SAVED_HCLK_PLL_REG, [CLKPWRBASE_REG,\
- #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
-4:
- ldr WORK2_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_HCLKPLL_CTRL_OFFS]
- and WORK2_REG, WORK2_REG, #LPC32XX_CLKPWR_HCLKPLL_PLL_STS
- bne 4b
-
- @ Re-enter run mode with self-refresh flag cleared, but no DRAM
- @ update yet. DRAM is still in self-refresh
- str SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
- #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
-
- @ Restore original DRAM clock mode to restore DRAM clocks
- str SAVED_HCLK_DIV_REG, [CLKPWRBASE_REG,\
- #LPC32XX_CLKPWR_HCLK_DIV_OFFS]
-
- @ Clear self-refresh mode
- orr WORK1_REG, SAVED_PWR_CTRL_REG,\
- #LPC32XX_CLKPWR_UPD_SDRAM_SELF_RFSH
- str WORK1_REG, [CLKPWRBASE_REG, #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
- str SAVED_PWR_CTRL_REG, [CLKPWRBASE_REG,\
- #LPC32XX_CLKPWR_PWR_CTRL_OFFS]
-
- @ Wait for EMC to clear self-refresh mode
-5:
- ldr WORK2_REG, [EMCBASE_REG, #LPC32XX_EMC_STATUS_OFFS]
- and WORK2_REG, WORK2_REG, #LPC32XX_EMC_STATUS_SELF_RFSH
- bne 5b @ Branch until self-refresh has exited
-
- @ restore regs and return
- adr r0, tmp_stack
- ldmfd r0!, {r3 - r7, sp, pc}
-
-reg_bases:
- .long IO_ADDRESS(LPC32XX_CLK_PM_BASE)
- .long IO_ADDRESS(LPC32XX_EMC_BASE)
-
-tmp_stack:
- .long 0, 0, 0, 0, 0, 0, 0
-tmp_stack_end:
-
-ENTRY(lpc32xx_sys_suspend_sz)
- .word . - lpc32xx_sys_suspend
--
2.43.0
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