* [PATCH v1 2/4] arm64: dts: ti: var-som-am62p: update audio codec configuration
From: Stefano Radaelli @ 2026-06-28 17:06 UTC (permalink / raw)
To: linux-kernel, devicetree, linux-arm-kernel
Cc: pierluigi.p, matthias.p, Stefano Radaelli, Nishanth Menon,
Vignesh Raghavendra, Tero Kristo, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
In-Reply-To: <cover.1782665899.git.stefano.r@variscite.com>
Update the WM8904 audio codec configuration on the VAR-SOM-AM62P.
Set the audio reference clock rate to 12 MHz and add the codec DRC, GPIO
and DMIC configuration required by the board.
Signed-off-by: Stefano Radaelli <stefano.r@variscite.com>
---
arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi | 21 ++++++++++++++++++-
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi b/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
index be19cbaffc4b..9440891339b3 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi
@@ -152,7 +152,7 @@ simple-audio-card,cpu {
};
&audio_refclk1 {
- assigned-clock-rates = <100000000>;
+ assigned-clock-rates = <12000000>;
};
&cpsw3g {
@@ -204,6 +204,25 @@ wm8904: audio-codec@1a {
DBVDD-supply = <®_3v3>;
DCVDD-supply = <®_1v8>;
MICVDD-supply = <®_1v8>;
+ wlf,drc-cfg-names = "default", "peaklimiter", "tradition",
+ "soft", "music";
+ /*
+ * Config registers per name, respectively:
+ * KNEE_IP = 0, KNEE_OP = 0, HI_COMP = 1, LO_COMP = 1
+ * KNEE_IP = -24, KNEE_OP = -6, HI_COMP = 1/4, LO_COMP = 1
+ * KNEE_IP = -42, KNEE_OP = -3, HI_COMP = 0, LO_COMP = 1
+ * KNEE_IP = -45, KNEE_OP = -9, HI_COMP = 1/8, LO_COMP = 1
+ * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1
+ */
+ wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>,
+ /bits/ 16 <0x04af 0x324b 0x0010 0x0408>,
+ /bits/ 16 <0x04af 0x324b 0x0028 0x0704>,
+ /bits/ 16 <0x04af 0x324b 0x0018 0x078c>,
+ /bits/ 16 <0x04af 0x324b 0x0010 0x050e>;
+ /* GPIO1 = DMIC_CLK, don't touch others */
+ wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>;
+ /* DMIC is connected to IN1L */
+ wlf,in1l-as-dmicdat1;
};
};
--
2.47.3
^ permalink raw reply related
* Re: [PATCH v4 0/4] AUXADC driver for the MediaTek mt6323 PMIC
From: David Lechner @ 2026-06-28 17:34 UTC (permalink / raw)
To: rva333, Jonathan Cameron, Nuno Sá, Andy Shevchenko,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Lee Jones
Cc: linux-iio, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Ben Grisdale, Conor Dooley, Andy Shevchenko
In-Reply-To: <20260623-mt6323-adc-v4-0-299680ad3194@protonmail.com>
On 6/23/26 3:16 AM, Roman Vivchar via B4 Relay wrote:
> This series adds support for the 15-bit AUXADC hardware block found on
> the MediaTek mt6323 PMIC.
>
> The previous version of the series for all AUXADC, EFUSE and thermal
> drivers was split after Krzysztof's comment [1].
>
> Tested on the MediaTek mt6572 and mt8163 SoCs (Ben), both paired with a
> mt6323.
>
> [1]: https://lore.kernel.org/linux-mediatek/20260504-mt6323-v1-0-799b58b355ff@protonmail.com/T/#med30fad67a090be35f549231336b2dec295233f6
>
> Tested-by: Ben Grisdale <bengris32@protonmail.ch> # Amazon Echo Dot (2nd Generation)
> Signed-off-by: Roman Vivchar <rva333@protonmail.com>
> ---
Reviewed-by: David Lechner <dlechner@baylibre.com>
^ permalink raw reply
* [PATCH v3 0/8] drm/msm: Add support for Shikra GPU (A704)
From: Akhil P Oommen @ 2026-06-28 18:23 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Konrad Dybcio, Dmitry Baryshkov,
Abhinav Kumar, Jessica Zhang, Marijn Suijten, David Airlie,
Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Will Deacon, Robin Murphy, Joerg Roedel (AMD), Bjorn Andersson
Cc: Bibek Kumar Patro, linux-arm-msm, dri-devel, freedreno,
devicetree, linux-kernel, linux-arm-kernel, iommu, Akhil P Oommen,
Aditya Sherawat, Krzysztof Kozlowski, Konrad Dybcio,
Dmitry Baryshkov, Imran Shaik, Komal Bajaj
Adreno A704 GPU found in Shikra is an IP reuse of A702 GPU with very
minimal changes. The only KMD facing difference is the chipid and the
zap firmware which is specified via devicetree.
Mesa side support is already merged:
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41762
Included the DT bits in the v3 revision.
-Akhil.
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
Changes in v3:
- Rebase on top of next-20260626
- Included GPU related DT patches
- Link to v2: https://lore.kernel.org/r/20260615-shikra-gpu-v2-0-2f2d1347c3fb@oss.qualcomm.com
Changes in v2:
- Add a new patch to document the GPU SMMU bindings
- Capture trailers
- Link to v1: https://lore.kernel.org/r/20260609-shikra-gpu-v1-0-9d0e09cab115@oss.qualcomm.com
---
Aditya Sherawat (6):
dt-bindings: display/msm/gpu: Add support for A704 GPU
drm/msm/adreno: Add support for A704 GPU
arm64: dts: qcom: shikra: Add A704 GPU support
arm64: dts: qcom: shikra-cqm-evk: Enable A704 GPU
arm64: dts: qcom: shikra-cqs-evk: Enable A704 GPU
arm64: dts: qcom: shikra-iqs-evk: Enable A704 GPU
Bibek Kumar Patro (2):
dt-bindings: arm-smmu: Document GPU SMMU for Shikra SoC
arm64: dts: qcom: shikra: Add Adreno SMMU node
.../devicetree/bindings/display/msm/gpu.yaml | 1 +
.../devicetree/bindings/iommu/arm,smmu.yaml | 2 +
arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 8 ++
arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 8 ++
arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 8 ++
arch/arm64/boot/dts/qcom/shikra.dtsi | 127 +++++++++++++++++++++
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 2 +-
7 files changed, 155 insertions(+), 1 deletion(-)
---
base-commit: 10a31245d8ba950c7fe87face7d0c190009cb572
change-id: 20260609-shikra-gpu-5432bdeaf0f7
prerequisite-message-id: <20260608-shikra-gcc-rpmcc-clks-v5-0-94cefe092ee3@oss.qualcomm.com>
prerequisite-patch-id: 59bb0a7828e41f546f734f127d81da83c0adcda9
prerequisite-patch-id: 197da6bcb15cadc47869dba88c8020987b25c335
prerequisite-patch-id: 8ec9c1eb03f052ae232ed54117abed38672c23f6
prerequisite-patch-id: 350db4f4bcdfc0fad9ed57cd5b1723f85ad44f5d
prerequisite-message-id: <20260612-shikra-dt-v6-0-6b6cb58db477@oss.qualcomm.com>
prerequisite-patch-id: 3a689e8dda5fd2755b689d94d095806b3f2e6eed
prerequisite-patch-id: ac83151a889855498d36288ddd36216d451340c8
prerequisite-patch-id: 2357cac636e019eaf14d6a493a1c72bca56fe405
prerequisite-patch-id: 2885f299e711582da312ca9d13983d296a3dd5dc
prerequisite-patch-id: 91af5f3c01e766a53ce8de69aa21847a2d6bbbf8
prerequisite-message-id: <20260604-shikra-dispcc-gpucc-v4-0-8204f1029311@oss.qualcomm.com>
prerequisite-patch-id: 67fa5f31ee5109470da23db3b513721580f4c86f
prerequisite-patch-id: 0e79e46bc5a88849a2f0a410b39c08f3244dfed3
prerequisite-patch-id: 0396ac157aba73a5afd7ba4a8a744847f5a7b433
prerequisite-patch-id: 2b1aecd97b9c073a1b323138cd7a98cb34e3715f
prerequisite-patch-id: 823bc7bc713f6fce1b9de47a266307f1829636b9
prerequisite-patch-id: 8a8a9df61f7c7c51d7ea9cdacc52b7bdd917f12c
prerequisite-patch-id: 5b89b41d7c729c23b3b1fff9b5f572f4baa915ca
prerequisite-patch-id: acd08e91e5e2c6f4799879e48481b07167c0a400
prerequisite-patch-id: c9f2942207341ad4f450b20f049199f35188c02a
prerequisite-patch-id: dd62ebff6be6a2e2d32743812d35ec54daf91d00
prerequisite-patch-id: 3a6e9752793f2d7b084008b47daed10ea572064a
prerequisite-patch-id: 3338cdc5915c1e6b991067d3a7afb734c182663e
prerequisite-patch-id: a3026c858ffdfd3bfafc837e72c67fffe46021eb
Best regards,
--
Akhil P Oommen <akhilpo@oss.qualcomm.com>
^ permalink raw reply
* [PATCH v3 3/8] dt-bindings: arm-smmu: Document GPU SMMU for Shikra SoC
From: Akhil P Oommen @ 2026-06-28 18:23 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Konrad Dybcio, Dmitry Baryshkov,
Abhinav Kumar, Jessica Zhang, Marijn Suijten, David Airlie,
Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Will Deacon, Robin Murphy, Joerg Roedel (AMD), Bjorn Andersson
Cc: Bibek Kumar Patro, linux-arm-msm, dri-devel, freedreno,
devicetree, linux-kernel, linux-arm-kernel, iommu, Akhil P Oommen,
Krzysztof Kozlowski
In-Reply-To: <20260628-shikra-gpu-v3-0-9b28a3b167e1@oss.qualcomm.com>
From: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
Add specific compatible strings to document the GPU SMMU present
in the Shikra SoC.
Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
index a701dec2fa0a..ad15fda5c25e 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
@@ -108,6 +108,7 @@ properties:
- qcom,sc7280-smmu-500
- qcom,sc8180x-smmu-500
- qcom,sc8280xp-smmu-500
+ - qcom,shikra-smmu-500
- qcom,sm6115-smmu-500
- qcom,sm6125-smmu-500
- qcom,sm8150-smmu-500
@@ -543,6 +544,7 @@ allOf:
- enum:
- qcom,milos-smmu-500
- qcom,sar2130p-smmu-500
+ - qcom,shikra-smmu-500
- qcom,sm8550-smmu-500
- qcom,sm8650-smmu-500
- qcom,x1e80100-smmu-500
--
2.51.0
^ permalink raw reply related
* [PATCH v3 4/8] arm64: dts: qcom: shikra: Add Adreno SMMU node
From: Akhil P Oommen @ 2026-06-28 18:23 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Konrad Dybcio, Dmitry Baryshkov,
Abhinav Kumar, Jessica Zhang, Marijn Suijten, David Airlie,
Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Will Deacon, Robin Murphy, Joerg Roedel (AMD), Bjorn Andersson
Cc: Bibek Kumar Patro, linux-arm-msm, dri-devel, freedreno,
devicetree, linux-kernel, linux-arm-kernel, iommu, Akhil P Oommen,
Imran Shaik, Komal Bajaj
In-Reply-To: <20260628-shikra-gpu-v3-0-9b28a3b167e1@oss.qualcomm.com>
From: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
Add the Adreno GPU IOMMU (adreno_smmu) node for the Shikra SoC.
Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index 1ccb0f1419aa..398cb1a4dc86 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -655,6 +655,35 @@ gpucc: clock-controller@5990000 {
#power-domain-cells = <1>;
};
+ adreno_smmu: iommu@59a0000 {
+ compatible = "qcom,shikra-smmu-500", "qcom,adreno-smmu",
+ "qcom,smmu-500", "arm,mmu-500";
+ reg = <0x0 0x059a0000 0x0 0x10000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <1>;
+
+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
+ <&gpucc GPU_CC_AHB_CLK>;
+ clock-names = "hlos",
+ "bus",
+ "iface",
+ "ahb";
+
+ power-domains = <&gpucc GPU_CX_GDSC>;
+ };
+
dispcc: clock-controller@5f00000 {
compatible = "qcom,shikra-dispcc", "qcom,qcm2290-dispcc";
reg = <0x0 0x05f00000 0x0 0x20000>;
--
2.51.0
^ permalink raw reply related
* [PATCH v3 5/8] arm64: dts: qcom: shikra: Add A704 GPU support
From: Akhil P Oommen @ 2026-06-28 18:23 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Konrad Dybcio, Dmitry Baryshkov,
Abhinav Kumar, Jessica Zhang, Marijn Suijten, David Airlie,
Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Will Deacon, Robin Murphy, Joerg Roedel (AMD), Bjorn Andersson
Cc: Bibek Kumar Patro, linux-arm-msm, dri-devel, freedreno,
devicetree, linux-kernel, linux-arm-kernel, iommu, Akhil P Oommen,
Aditya Sherawat
In-Reply-To: <20260628-shikra-gpu-v3-0-9b28a3b167e1@oss.qualcomm.com>
From: Aditya Sherawat <asherawa@qti.qualcomm.com>
Add the A704 GPU and GMU wrapper nodes with register maps, clocks,
interconnects, IOMMU, OPP table and the zap-shader region.
Signed-off-by: Aditya Sherawat <asherawa@qti.qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 98 ++++++++++++++++++++++++++++++++++++
1 file changed, 98 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index 398cb1a4dc86..89cc5dc767e2 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -642,6 +642,104 @@ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
};
};
+ gpu: gpu@5900000 {
+ compatible = "qcom,adreno-07000400", "qcom,adreno";
+ reg = <0x0 0x05900000 0x0 0x40000>,
+ <0x0 0x0599e000 0x0 0x1000>,
+ <0x0 0x05961000 0x0 0x800>;
+ reg-names = "kgsl_3d0_reg_memory",
+ "cx_mem",
+ "cx_dbgc";
+
+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>,
+ <&gpucc GPU_CC_AHB_CLK>,
+ <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+ <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+ <&gpucc GPU_CC_CX_GMU_CLK>,
+ <&gpucc GPU_CC_CXO_CLK>;
+ clock-names = "core",
+ "iface",
+ "mem_iface",
+ "alt_mem_iface",
+ "gmu",
+ "xo";
+
+ interconnects = <&mem_noc MASTER_GRAPHICS_3D RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "gfx-mem";
+
+ iommus = <&adreno_smmu 0 1>;
+ operating-points-v2 = <&gpu_opp_table>;
+ power-domains = <&rpmpd RPMPD_VDDCX>;
+ qcom,gmu = <&gmu_wrapper>;
+
+ #cooling-cells = <2>;
+
+ status = "disabled";
+
+ gpu_zap_shader: zap-shader {
+ memory-region = <&gpu_micro_code_mem>;
+ };
+
+ gpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-1142400000 {
+ opp-hz = /bits/ 64 <1142400000>;
+ required-opps = <&rpmpd_opp_turbo_plus>;
+ opp-peak-kBps = <8171875>;
+ };
+
+ opp-1017600000 {
+ opp-hz = /bits/ 64 <1017600000>;
+ required-opps = <&rpmpd_opp_turbo>;
+ opp-peak-kBps = <8171875>;
+ };
+
+ opp-921600000 {
+ opp-hz = /bits/ 64 <921600000>;
+ required-opps = <&rpmpd_opp_nom_plus>;
+ opp-peak-kBps = <7046875>;
+ };
+
+ opp-844800000 {
+ opp-hz = /bits/ 64 <844800000>;
+ required-opps = <&rpmpd_opp_nom>;
+ opp-peak-kBps = <6074218>;
+ };
+
+ opp-672000000 {
+ opp-hz = /bits/ 64 <672000000>;
+ required-opps = <&rpmpd_opp_svs_plus>;
+ opp-peak-kBps = <5285156>;
+ };
+
+ opp-537600000 {
+ opp-hz = /bits/ 64 <537600000>;
+ required-opps = <&rpmpd_opp_svs>;
+ opp-peak-kBps = <3972656>;
+ };
+
+ opp-355200000 {
+ opp-hz = /bits/ 64 <355200000>;
+ required-opps = <&rpmpd_opp_low_svs>;
+ opp-peak-kBps = <2136718>;
+ };
+ };
+ };
+
+ gmu_wrapper: gmu@596a000 {
+ compatible = "qcom,adreno-gmu-wrapper";
+ reg = <0x0 0x0596a000 0x0 0x30000>;
+ reg-names = "gmu";
+ power-domains = <&gpucc GPU_CX_GDSC>,
+ <&gpucc GPU_GX_GDSC>;
+ power-domain-names = "cx",
+ "gx";
+ };
+
gpucc: clock-controller@5990000 {
compatible = "qcom,shikra-gpucc";
reg = <0x0 0x05990000 0x0 0x9000>;
--
2.51.0
^ permalink raw reply related
* [PATCH v3 7/8] arm64: dts: qcom: shikra-cqs-evk: Enable A704 GPU
From: Akhil P Oommen @ 2026-06-28 18:24 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Konrad Dybcio, Dmitry Baryshkov,
Abhinav Kumar, Jessica Zhang, Marijn Suijten, David Airlie,
Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Will Deacon, Robin Murphy, Joerg Roedel (AMD), Bjorn Andersson
Cc: Bibek Kumar Patro, linux-arm-msm, dri-devel, freedreno,
devicetree, linux-kernel, linux-arm-kernel, iommu, Akhil P Oommen,
Aditya Sherawat
In-Reply-To: <20260628-shikra-gpu-v3-0-9b28a3b167e1@oss.qualcomm.com>
From: Aditya Sherawat <asherawa@qti.qualcomm.com>
Enable the A704 GPU and configure its zap-shader firmware on the
Shikra CQS EVK board.
Signed-off-by: Aditya Sherawat <asherawa@qti.qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
index b3f19a64d7ae..94ef498a2467 100644
--- a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
+++ b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
@@ -23,6 +23,14 @@ chosen {
};
};
+&gpu {
+ status = "okay";
+};
+
+&gpu_zap_shader {
+ firmware-name = "qcom/shikra/a704_zap.mbn";
+};
+
&sdhc_1 {
vmmc-supply = <&pm4125_l20>;
vqmmc-supply = <&pm4125_l14>;
--
2.51.0
^ permalink raw reply related
* [PATCH v3 8/8] arm64: dts: qcom: shikra-iqs-evk: Enable A704 GPU
From: Akhil P Oommen @ 2026-06-28 18:24 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Konrad Dybcio, Dmitry Baryshkov,
Abhinav Kumar, Jessica Zhang, Marijn Suijten, David Airlie,
Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Will Deacon, Robin Murphy, Joerg Roedel (AMD), Bjorn Andersson
Cc: Bibek Kumar Patro, linux-arm-msm, dri-devel, freedreno,
devicetree, linux-kernel, linux-arm-kernel, iommu, Akhil P Oommen,
Aditya Sherawat
In-Reply-To: <20260628-shikra-gpu-v3-0-9b28a3b167e1@oss.qualcomm.com>
From: Aditya Sherawat <asherawa@qti.qualcomm.com>
Enable the A704 GPU and configure its zap-shader firmware on the
Shikra IQS EVK board.
Signed-off-by: Aditya Sherawat <asherawa@qti.qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
index 3003a47bd759..0918bcb4b1ea 100644
--- a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
+++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
@@ -23,6 +23,14 @@ chosen {
};
};
+&gpu {
+ status = "okay";
+};
+
+&gpu_zap_shader {
+ firmware-name = "qcom/shikra/a704_zap.mbn";
+};
+
&sdhc_1 {
vmmc-supply = <&pm8150_l17>;
vqmmc-supply = <&pm8150_s4>;
--
2.51.0
^ permalink raw reply related
* [PATCH v3 6/8] arm64: dts: qcom: shikra-cqm-evk: Enable A704 GPU
From: Akhil P Oommen @ 2026-06-28 18:23 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Konrad Dybcio, Dmitry Baryshkov,
Abhinav Kumar, Jessica Zhang, Marijn Suijten, David Airlie,
Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Will Deacon, Robin Murphy, Joerg Roedel (AMD), Bjorn Andersson
Cc: Bibek Kumar Patro, linux-arm-msm, dri-devel, freedreno,
devicetree, linux-kernel, linux-arm-kernel, iommu, Akhil P Oommen,
Aditya Sherawat
In-Reply-To: <20260628-shikra-gpu-v3-0-9b28a3b167e1@oss.qualcomm.com>
From: Aditya Sherawat <asherawa@qti.qualcomm.com>
Enable the A704 GPU and configure its zap-shader firmware on the
Shikra CQM EVK board.
Signed-off-by: Aditya Sherawat <asherawa@qti.qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
index 0a52ab9b7a4c..d46132e97c69 100644
--- a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
+++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
@@ -23,6 +23,14 @@ chosen {
};
};
+&gpu {
+ status = "okay";
+};
+
+&gpu_zap_shader {
+ firmware-name = "qcom/shikra/a704_zap.mbn";
+};
+
&sdhc_1 {
vmmc-supply = <&pm4125_l20>;
vqmmc-supply = <&pm4125_l14>;
--
2.51.0
^ permalink raw reply related
* [PATCH v3 1/8] dt-bindings: display/msm/gpu: Add support for A704 GPU
From: Akhil P Oommen @ 2026-06-28 18:23 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Konrad Dybcio, Dmitry Baryshkov,
Abhinav Kumar, Jessica Zhang, Marijn Suijten, David Airlie,
Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Will Deacon, Robin Murphy, Joerg Roedel (AMD), Bjorn Andersson
Cc: Bibek Kumar Patro, linux-arm-msm, dri-devel, freedreno,
devicetree, linux-kernel, linux-arm-kernel, iommu, Akhil P Oommen,
Aditya Sherawat, Krzysztof Kozlowski
In-Reply-To: <20260628-shikra-gpu-v3-0-9b28a3b167e1@oss.qualcomm.com>
From: Aditya Sherawat <asherawa@qti.qualcomm.com>
Adreno A704 GPU found Shikra SoC is an IP reuse of A702 GPU with very
minimal changes.
Signed-off-by: Aditya Sherawat <asherawa@qti.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
Documentation/devicetree/bindings/display/msm/gpu.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml
index dbbd8b814189..8e648bfb3b23 100644
--- a/Documentation/devicetree/bindings/display/msm/gpu.yaml
+++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml
@@ -353,6 +353,7 @@ allOf:
- qcom,adreno-610.0
- qcom,adreno-619.1
- qcom,adreno-07000200
+ - qcom,adreno-07000400
then:
properties:
clocks:
--
2.51.0
^ permalink raw reply related
* [PATCH v3 2/8] drm/msm/adreno: Add support for A704 GPU
From: Akhil P Oommen @ 2026-06-28 18:23 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Konrad Dybcio, Dmitry Baryshkov,
Abhinav Kumar, Jessica Zhang, Marijn Suijten, David Airlie,
Simona Vetter, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Will Deacon, Robin Murphy, Joerg Roedel (AMD), Bjorn Andersson
Cc: Bibek Kumar Patro, linux-arm-msm, dri-devel, freedreno,
devicetree, linux-kernel, linux-arm-kernel, iommu, Akhil P Oommen,
Aditya Sherawat, Konrad Dybcio, Dmitry Baryshkov
In-Reply-To: <20260628-shikra-gpu-v3-0-9b28a3b167e1@oss.qualcomm.com>
From: Aditya Sherawat <asherawa@qti.qualcomm.com>
Adreno A704 GPU found in Shikra is an IP reuse of A702 GPU with very
minimal changes. The only KMD facing difference is the chipid and the
zap firmware which is specified via devicetree.
Just add the new chipid to enable support for A704 GPU in Shikra.
Signed-off-by: Aditya Sherawat <asherawa@qti.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
index 3e6f409d13a2..2de3ab010135 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
@@ -1454,7 +1454,7 @@ DECLARE_ADRENO_REGLIST_PIPE_LIST(a7xx_dyn_pwrup_reglist);
static const struct adreno_info a7xx_gpus[] = {
{
- .chip_ids = ADRENO_CHIP_IDS(0x07000200),
+ .chip_ids = ADRENO_CHIP_IDS(0x07000200, 0x07000400),
.family = ADRENO_6XX_GEN1, /* NOT a mistake! */
.fw = {
[ADRENO_FW_SQE] = "a702_sqe.fw",
--
2.51.0
^ permalink raw reply related
* Re: [PATCH] arm64: dts: rockchip: fix eMMC reset polarity on PP-1516
From: Heiko Stuebner @ 2026-06-28 19:13 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Quentin Schulz
Cc: Heiko Stuebner, Heiko Stuebner, devicetree, linux-arm-kernel,
linux-rockchip, linux-kernel, Quentin Schulz, stable
In-Reply-To: <20260612-pp1516-emmc-polarity-v1-1-4816c1c909f7@cherry.de>
On Fri, 12 Jun 2026 18:47:34 +0200, Quentin Schulz wrote:
> According to the Jedec 5.1 specification, the device is held in reset
> when RST_n is low, therefore the polarity of the line must be that, as
> specified in the Device Tree binding (mmc/mmc-pwrseq-emmc.yaml).
>
> Due to the wrong polarity, eMMC devices with RST_n_FUNCTION[162]
> bitfield [1:0] set to 0x1 (the default is 0x0) will be held in reset
> forever.
>
> [...]
Applied, thanks!
[1/1] arm64: dts: rockchip: fix eMMC reset polarity on PP-1516
commit: 2a08921edcab6a462fa6ddb02c91b90b5ac92429
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
^ permalink raw reply
* Re: [PATCH v2] arm64: dts: rockchip: fix emmc reset polarity on px30-cobra
From: Heiko Stuebner @ 2026-06-28 19:13 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Jakob Unterwurzacher, Quentin Schulz, Jakob Unterwurzacher
Cc: Heiko Stuebner, stable, Heiko Stuebner, devicetree,
linux-arm-kernel, linux-rockchip, linux-kernel
In-Reply-To: <20260609081728.30616-2-jakobunt@gmail.com>
On Tue, 09 Jun 2026 10:17:25 +0200, Jakob Unterwurzacher wrote:
> Technically, the reset signal is active low - it's called RST_n after all.
>
> But it is ignored completely unless RST_n_FUNCTION=1 (byte 162 in extcsd)
> is set in the emmc. It is 0 per default.
>
> For emmcs that have RST_n_FUNCTION=1 we failed like this:
>
> [...]
Applied, thanks!
[1/1] arm64: dts: rockchip: fix emmc reset polarity on px30-cobra
commit: 85babf47515e2adf266dcc3be9804e31f752083e
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
^ permalink raw reply
* Re: [PATCH] clk: rockchip: rk3588: don't disable unused I2S MCLK output gates
From: Heiko Stuebner @ 2026-06-28 19:13 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Daniele Briguglio
Cc: Heiko Stuebner, linux-clk, linux-arm-kernel, linux-rockchip,
linux-kernel, Diederik de Haas, Nicolas Frattaroli,
Ricardo Pardini
In-Reply-To: <20260624123914.1767374-1-hello@superkali.me>
On Wed, 24 Jun 2026 14:39:14 +0200, Daniele Briguglio wrote:
> No in-tree board references these gates yet. Boards drive the codec
> MCLK through the parent I2S*_8CH_MCLKOUT, and now that the gates are
> managed clocks, clk_disable_unused() turns them off at boot. On a board
> that relied on firmware leaving the output enabled, that cuts the MCLK
> and analog audio stops working.
>
> Mark the four gates CLK_IGNORE_UNUSED so an unreferenced gate keeps the
> state firmware left. A board that wants the kernel to own the gate can
> reference I2S*_8CH_MCLKOUT_TO_IO from DT instead.
>
> [...]
Applied, thanks!
[1/1] clk: rockchip: rk3588: don't disable unused I2S MCLK output gates
commit: 946352b2f88fd2378f0341312e47dff1e8dc2fac
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
^ permalink raw reply
* Re: [PATCH v2 1/2] dt-bindings: arm: rockchip: Add Vicharak Vaaman2
From: Conor Dooley @ 2026-06-28 19:19 UTC (permalink / raw)
To: Hrushiraj Gandhi
Cc: linux-rockchip, devicetree, linux-arm-kernel, linux-kernel, heiko,
robh, krzk+dt, conor+dt
In-Reply-To: <20260627102633.86222-2-hrushirajg23@gmail.com>
[-- Attachment #1: Type: text/plain, Size: 75 bytes --]
Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply
* [PATCH RFC v5 00/12] ZTE zx297520v3 clock bindings and driver
From: Stefan Dösinger @ 2026-06-28 19:58 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Brian Masney
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
Stefan Dösinger
Hi,
I am sending version 5 of my zx297520v3 clock patch. The major change is
using regmaps rather than raw mmio to access the clocks and moving reset
handling into its own mfd/aux bus driver.
I think the list of clocks in my driver is fairly complete; It is
certainly a lot better than what the downstream ZTE drivers have. I
deduced a lot of it by trial and error. I am sure there are some clocks
missing that will need to be added to the binding later. Afaiu adding
clocks is not an issue, but removing or reordering them is an ABI break.
Signed-off-by: Stefan Dösinger <stefandoesinger@gmail.com>
---
Changes in v5:
*) Use MFD instead of aux bus for top and matrix clocks
*) Move top and matrix bindings to soc/zte
*) Give USB PHY its own resets
*) Other localized changes are noted in the individual patches
- Link to v4: https://lore.kernel.org/r/20260616-zx29clk-v4-0-ca994bd22e9d@gmail.com
Changes in v4:
*) Use syscon and regmap instead of raw IO
*) Move reset to its own driver on the aux bus, but keep reset and clk
in the same binding as it matches the way the hardware works
*) Go back to having matrixclk in its own device because syscon deals
poorly with multi io reg devices. List all PLL outputs from topclk as
inputs to matrixclk
*) Some more hardware research: Figure out the parents of the 4 possible
GPIO clock outputs and declare them in the driver. They are unused on
the hardware I have, but they show that all PLLs can be used.
- Link to v3: https://lore.kernel.org/r/20260529-zx29clk-v3-0-c7fe54ea388f@gmail.com
Changes in v3:
Model top and matrix clocks as one device
Add PLL driver
Fixed a few issues found by Sashiko: register lock, some missing devm_,
error handling
v2: Fix build issues introduced by checkpatch.pl fixes that I didn't
spot earlier.
---
Stefan Dösinger (12):
dt-bindings: soc: zte: Add zx297520v3 top clock and reset bindings
dt-bindings: soc: zte: Add zx297520v3 matrix clock and reset bindings
dt-bindings: clk: zte: Add zx297520v3 LSP clock and reset bindings
mfd: zx297520v3: Add a clock and reset MFD driver.
clk: zte: Add Clock registration infrastructure.
clk: zte: Add zx PLL support infrastructure
clk: zte: Add regmap based clocks
clk: zte: Introduce a driver for zx297520v3 top clocks
clk: zte: Introduce a driver for zx297520v3 matrix clocks
clk: zte: Introduce a driver for zx297520v3 LSP clocks and resets
reset: zte: Add a zx297520v3 reset driver
ARM: dts: zte: Declare zx297520v3 CRM device nodes
.../bindings/clock/zte,zx297520v3-lspcrm.yaml | 96 +++
.../bindings/soc/zte/zte,zx297520v3-matrixcrm.yaml | 177 +++++
.../bindings/soc/zte/zte,zx297520v3-topcrm.yaml | 85 +++
MAINTAINERS | 7 +
arch/arm/boot/dts/zte/zx297520v3.dtsi | 97 ++-
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 1 +
drivers/clk/zte/Kconfig | 28 +
drivers/clk/zte/Makefile | 6 +
drivers/clk/zte/clk-regmap.c | 245 ++++++
drivers/clk/zte/clk-zx.c | 192 +++++
drivers/clk/zte/clk-zx.h | 81 ++
drivers/clk/zte/clk-zx297520v3.c | 848 +++++++++++++++++++++
drivers/clk/zte/pll-zx.c | 485 ++++++++++++
drivers/reset/Kconfig | 11 +
drivers/reset/Makefile | 1 +
drivers/reset/reset-zte-zx297520v3.c | 274 +++++++
drivers/soc/Kconfig | 1 +
drivers/soc/Makefile | 1 +
drivers/soc/zte/Kconfig | 20 +
drivers/soc/zte/Makefile | 3 +
drivers/soc/zte/zx297520v3-crm.c | 76 ++
include/dt-bindings/clock/zte,zx297520v3-clk.h | 171 +++++
include/dt-bindings/reset/zte,zx297520v3-reset.h | 61 ++
24 files changed, 2960 insertions(+), 8 deletions(-)
---
base-commit: c1ecb239fa3456529a32255359fc78b69eb9d847
change-id: 20260510-zx29clk-2e4d39e3128c
Best regards,
--
Stefan Dösinger <stefandoesinger@gmail.com>
^ permalink raw reply
* [PATCH RFC v5 02/12] dt-bindings: soc: zte: Add zx297520v3 matrix clock and reset bindings
From: Stefan Dösinger @ 2026-06-28 19:58 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Brian Masney
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
Stefan Dösinger
In-Reply-To: <20260628-zx29clk-v5-0-79ff044e4192@gmail.com>
This controller contains clocks and resets for high speed devices on the
zx297520v3 board and hardware spinlocks that I expect will be necessary
to communicate correctly with the LTE DSP firmware blob.
A simple MFD driver will instantiate independent clock, reset and hwlock
drivers.
Signed-off-by: Stefan Dösinger <stefandoesinger@gmail.com>
---
Changes
v4->v5:
Move binding to soc/zte
Remove topclk from the example
Add #hwlock-cells for hw spinlock registers
Add more clocks I stumbled into: sram0 and another LTE related device
v3->v4:
Split matrixclk into its own controller again because syscon/regmap
deals poorly with device nodes that have more than one memory region. As
a consequence I am passing all PLL outputs generated on Topclk down to
Matrixclk.
---
.../bindings/soc/zte/zte,zx297520v3-matrixcrm.yaml | 177 +++++++++++++++++++++
include/dt-bindings/clock/zte,zx297520v3-clk.h | 37 +++++
include/dt-bindings/reset/zte,zx297520v3-reset.h | 10 ++
3 files changed, 224 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/zte/zte,zx297520v3-matrixcrm.yaml b/Documentation/devicetree/bindings/soc/zte/zte,zx297520v3-matrixcrm.yaml
new file mode 100644
index 000000000000..bbec0eb837da
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/zte/zte,zx297520v3-matrixcrm.yaml
@@ -0,0 +1,177 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/zte/zte,zx297520v3-matrixcrm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ZTE zx297520v3 SoC matrix clock and reset controller
+
+maintainers:
+ - Stefan Dösinger <stefandoesinger@gmail.com>
+
+description: |
+ This controller contains clock and reset controls for high speed devices on
+ the zx297520v3 board: The CPU, RAM, SDIO and Ethernet clocks and resets are
+ found here. This controller requires PLL-generated clocks from Topcrm as well
+ as the fixed 26 MHz and 32 KHz oscillators found on this board.
+
+ This controller also contains hardware mutex registers for synchronization
+ with different processors on this board.
+
+ All available clocks are defined as preprocessor macros in the
+ 'dt-bindings/clock/zte,zx297520v3-clk.h' header. Resets are defined in the
+ 'dt-bindings/reset/zte,zx297520v3-reset.h' header.
+
+properties:
+ compatible:
+ items:
+ - const: zte,zx297520v3-matrixcrm
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: 26 MHz external oscillator
+ - description: 32 KHz external oscillator
+ - description: Main PLL output from topcrm (usually 624 MHz)
+ - description: Main PLL subdivision factor 2
+ - description: Main PLL subdivision factor 3
+ - description: Main PLL subdivision factor 4
+ - description: Main PLL subdivision factor 5
+ - description: Main PLL subdivision factor 6
+ - description: Main PLL subdivision factor 8
+ - description: Main PLL subdivision factor 12
+ - description: Main PLL subdivision factor 16
+ - description: Main PLL subdivision factor 26
+ - description: Upll output from topcrm (Usually 480 MHz)
+ - description: Upll subdivision factor 2
+ - description: Upll subdivision factor 3
+ - description: Upll subdivision factor 4
+ - description: Upll subdivision factor 5
+ - description: Upll subdivision factor 6
+ - description: Upll subdivision factor 8
+ - description: Upll subdivision factor 12
+ - description: Upll subdivision factor 16
+ - description: Dpll output from topcrm (usually 492.88 MHz)
+ - description: Dpll subdivision factor 2
+ - description: Dpll subdivision factor 3
+ - description: Dpll subdivision factor 4
+ - description: Dpll subdivision factor 5
+ - description: Dpll subdivision factor 6
+ - description: Dpll subdivision factor 8
+ - description: Dpll subdivision factor 12
+ - description: Dpll subdivision factor 16
+ - description: Gpll output from topcrm (usually 200 MHz)
+ - description: Gpll subdivision factor 2
+ - description: Gpll subdivision factor 3
+ - description: Gpll subdivision factor 4
+ - description: Gpll subdivision factor 5
+ - description: Gpll subdivision factor 6
+ - description: Gpll subdivision factor 8
+ - description: Gpll subdivision factor 12
+ - description: Gpll subdivision factor 16
+
+ clock-names:
+ items:
+ - const: osc26m
+ - const: osc32k
+ - const: mpll
+ - const: mpll_d2
+ - const: mpll_d3
+ - const: mpll_d4
+ - const: mpll_d5
+ - const: mpll_d6
+ - const: mpll_d8
+ - const: mpll_d12
+ - const: mpll_d16
+ - const: mpll_d26
+ - const: upll
+ - const: upll_d2
+ - const: upll_d3
+ - const: upll_d4
+ - const: upll_d5
+ - const: upll_d6
+ - const: upll_d8
+ - const: upll_d12
+ - const: upll_d16
+ - const: dpll
+ - const: dpll_d2
+ - const: dpll_d3
+ - const: dpll_d4
+ - const: dpll_d5
+ - const: dpll_d6
+ - const: dpll_d8
+ - const: dpll_d12
+ - const: dpll_d16
+ - const: gpll
+ - const: gpll_d2
+ - const: gpll_d3
+ - const: gpll_d4
+ - const: gpll_d5
+ - const: gpll_d6
+ - const: gpll_d8
+ - const: gpll_d12
+ - const: gpll_d16
+
+ "#clock-cells":
+ const: 1
+
+ "#hwlock-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - "#hwlock-cells"
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/zte,zx297520v3-clk.h>
+ #include <dt-bindings/reset/zte,zx297520v3-reset.h>
+
+ clock-controller@1306000 {
+ compatible = "zte,zx297520v3-matrixcrm";
+ reg = <0x01306000 0x400>;
+ clocks = <&osc26m>, <&osc32k>,
+ <&topcrm ZX297520V3_MPLL>, <&topcrm ZX297520V3_MPLL_D2>,
+ <&topcrm ZX297520V3_MPLL_D3>, <&topcrm ZX297520V3_MPLL_D4>,
+ <&topcrm ZX297520V3_MPLL_D5>, <&topcrm ZX297520V3_MPLL_D6>,
+ <&topcrm ZX297520V3_MPLL_D8>, <&topcrm ZX297520V3_MPLL_D12>,
+ <&topcrm ZX297520V3_MPLL_D16>, <&topcrm ZX297520V3_MPLL_D26>,
+ <&topcrm ZX297520V3_UPLL>, <&topcrm ZX297520V3_UPLL_D2>,
+ <&topcrm ZX297520V3_UPLL_D3>, <&topcrm ZX297520V3_UPLL_D4>,
+ <&topcrm ZX297520V3_UPLL_D5>, <&topcrm ZX297520V3_UPLL_D6>,
+ <&topcrm ZX297520V3_UPLL_D8>, <&topcrm ZX297520V3_UPLL_D12>,
+ <&topcrm ZX297520V3_UPLL_D16>,
+ <&topcrm ZX297520V3_DPLL>, <&topcrm ZX297520V3_DPLL_D2>,
+ <&topcrm ZX297520V3_DPLL_D3>, <&topcrm ZX297520V3_DPLL_D4>,
+ <&topcrm ZX297520V3_DPLL_D5>, <&topcrm ZX297520V3_DPLL_D6>,
+ <&topcrm ZX297520V3_DPLL_D8>, <&topcrm ZX297520V3_DPLL_D12>,
+ <&topcrm ZX297520V3_DPLL_D16>,
+ <&topcrm ZX297520V3_GPLL>, <&topcrm ZX297520V3_GPLL_D2>,
+ <&topcrm ZX297520V3_GPLL_D3>, <&topcrm ZX297520V3_GPLL_D4>,
+ <&topcrm ZX297520V3_GPLL_D5>, <&topcrm ZX297520V3_GPLL_D6>,
+ <&topcrm ZX297520V3_GPLL_D8>, <&topcrm ZX297520V3_GPLL_D12>,
+ <&topcrm ZX297520V3_GPLL_D16>;
+ clock-names = "osc26m", "osc32k", "mpll", "mpll_d2", "mpll_d3",
+ "mpll_d4", "mpll_d5", "mpll_d6", "mpll_d8", "mpll_d12",
+ "mpll_d16", "mpll_d26", "upll", "upll_d2", "upll_d3",
+ "upll_d4", "upll_d5", "upll_d6", "upll_d8", "upll_d12",
+ "upll_d16", "dpll", "dpll_d2", "dpll_d3", "dpll_d4",
+ "dpll_d5", "dpll_d6", "dpll_d8", "dpll_d12", "dpll_d16",
+ "gpll", "gpll_d2", "gpll_d3", "gpll_d4", "gpll_d5",
+ "gpll_d6", "gpll_d8", "gpll_d12", "gpll_d16";
+ #clock-cells = <1>;
+ #hwlock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/include/dt-bindings/clock/zte,zx297520v3-clk.h b/include/dt-bindings/clock/zte,zx297520v3-clk.h
index de1c08b6a5a9..8a6aa456a708 100644
--- a/include/dt-bindings/clock/zte,zx297520v3-clk.h
+++ b/include/dt-bindings/clock/zte,zx297520v3-clk.h
@@ -94,4 +94,41 @@
#define ZX297520V3_HSIC_WCLK 86
#define ZX297520V3_HSIC_PCLK 87
+#define ZX297520V3_CPU_WCLK 1
+#define ZX297520V3_CPU_PCLK 2
+#define ZX297520V3_ZSP_WCLK 3
+#define ZX297520V3_EDCP_WCLK 4
+#define ZX297520V3_EDCP_PCLK 5
+#define ZX297520V3_SD0_WCLK 6
+#define ZX297520V3_SD0_PCLK 7
+#define ZX297520V3_SD0_CDET 8
+#define ZX297520V3_SD1_WCLK 9
+#define ZX297520V3_SD1_PCLK 10
+#define ZX297520V3_SD1_CDET 11
+#define ZX297520V3_NAND_WCLK 12
+#define ZX297520V3_NAND_PCLK 13
+#define ZX297520V3_DMA_PCLK 14
+#define ZX297520V3_MBOX_PCLK 15
+#define ZX297520V3_PDCFG_WCLK 16
+#define ZX297520V3_PDCFG_PCLK 17
+#define ZX297520V3_SSC_WCLK 18
+#define ZX297520V3_SSC_PCLK 19
+#define ZX297520V3_GMAC_WCLK 20
+#define ZX297520V3_GMAC_PCLK 21
+#define ZX297520V3_GMAC_AHB 22
+#define ZX297520V3_VOU_WCLK 23
+#define ZX297520V3_VOU_PCLK 24
+#define ZX297520V3_LSP_MPLL_D5_WCLK 25
+#define ZX297520V3_LSP_MPLL_D4_WCLK 26
+#define ZX297520V3_LSP_MPLL_D6_WCLK 27
+#define ZX297520V3_LSP_MPLL_D8_WCLK 28
+#define ZX297520V3_LSP_MPLL_D12_WCLK 29
+#define ZX297520V3_LSP_OSC26M_WCLK 30
+#define ZX297520V3_LSP_OSC32K_WCLK 31
+#define ZX297520V3_LSP_PCLK 32
+#define ZX297520V3_LSP_TDM_WCLK 33
+#define ZX297520V3_LSP_DPLL_D4_WCLK 34
+#define ZX297520V3_SRAM0_PCLK 35
+#define ZX297520V3_GSM_CFG_PCLK 36
+
#endif /* __DT_BINDINGS_CLOCK_ZX297520V3_H */
diff --git a/include/dt-bindings/reset/zte,zx297520v3-reset.h b/include/dt-bindings/reset/zte,zx297520v3-reset.h
index 43db72bb59de..81ffc8bc34c5 100644
--- a/include/dt-bindings/reset/zte,zx297520v3-reset.h
+++ b/include/dt-bindings/reset/zte,zx297520v3-reset.h
@@ -29,4 +29,14 @@
#define ZX297520V3_HSIC_PHY_RESET 20
#define ZX297520V3_HSIC_RESET 21
+#define ZX297520V3_CPU_RESET 0
+#define ZX297520V3_EDCP_RESET 1
+#define ZX297520V3_SD0_RESET 2
+#define ZX297520V3_SD1_RESET 3
+#define ZX297520V3_NAND_RESET 4
+#define ZX297520V3_PDCFG_RESET 5
+#define ZX297520V3_SSC_RESET 6
+#define ZX297520V3_GMAC_RESET 7
+#define ZX297520V3_VOU_RESET 8
+
#endif /* __DT_BINDINGS_RESET_ZX297520V3_H */
--
2.53.0
^ permalink raw reply related
* [PATCH RFC v5 01/12] dt-bindings: soc: zte: Add zx297520v3 top clock and reset bindings
From: Stefan Dösinger @ 2026-06-28 19:58 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Brian Masney
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
Stefan Dösinger
In-Reply-To: <20260628-zx29clk-v5-0-79ff044e4192@gmail.com>
These SoCs have 3 clock and reset controllers: Top, Matrix and LSP. The
separation of concerns between Top and Matrix and the interface between
them is poorly defined in the hardware, so the bindings list all
potential PLL clocks that might be passed between them.
Generally every device has two clocks (one work clock, and one that
connects it to the bus, I call it PCLK), two reset bits (I don't know
what the difference is - sometimes asserting one is enough to reset the
device, sometimes both need to be asserted). PCLK and WCLK are
controlled by individual gates. Some devices have a mux and/or a
divider for their work clock. Some devices, like the GPIO controller,
only have reset bits and no clocks.
The top clock controller is fed by a 26mhz external oscillator and has 4
PLLs to generate other clock rates. ZTE's kernel mostly relies on the
boot ROM to set up PLLs, but one LTE-Related PLL is not configured
on some boards. Therefore my driver contains code to program PLLs. It
produces identical settings as the boot ROM for the pre-programmed
frequencies.
Not all clocks will have an explicit user in the end. I am defining a
lot of them simply to shut them off. The boot loader sets up a few of
the proprietary timers, which will send regular IRQs (although the
kernel of course doesn't need to listen to them). I don't plan to add a
driver for the proprietary timer as I see no use for them - the ARM arch
timer works just fine. I will add a driver for the very similar
proprietary watchdog though.
The clock list in this patch is pretty complete but not exhaustive.
There are other bits that are enabled, but I couldn't deduce what they
are controlling by trial and error. Some of them seem to do nothing.
Others cause an instant hang of the board when disabled. It is quite
likely that a handful more clocks will be added in the future, but not a
large number.
Signed-off-by: Stefan Dösinger <stefandoesinger@gmail.com>
---
Changes v4->v5:
Rename from zte,zx297520v3-topclk to zte,zx297520v3-topcrm and move to
soc/zte
Fix path in MAINTAINERS
Add syscon-reboot node to the binding
Give the USB and HSIC PHY resets their own reset control
---
.../bindings/soc/zte/zte,zx297520v3-topcrm.yaml | 85 +++++++++++++++++++
MAINTAINERS | 3 +
include/dt-bindings/clock/zte,zx297520v3-clk.h | 97 ++++++++++++++++++++++
include/dt-bindings/reset/zte,zx297520v3-reset.h | 32 +++++++
4 files changed, 217 insertions(+)
diff --git a/Documentation/devicetree/bindings/soc/zte/zte,zx297520v3-topcrm.yaml b/Documentation/devicetree/bindings/soc/zte/zte,zx297520v3-topcrm.yaml
new file mode 100644
index 000000000000..6baab5c98d25
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/zte/zte,zx297520v3-topcrm.yaml
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/zte/zte,zx297520v3-topcrm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ZTE zx297520v3 SoC top clock and reset controller
+
+maintainers:
+ - Stefan Dösinger <stefandoesinger@gmail.com>
+
+description: |
+ The zx297520v3's top clock and reset controller generates clocks for core
+ devices on the board like the main bus, USB and timers. In addition to clocks
+ it has reset controls for peripherals, a global board reset, watchdog reset
+ controls and a USB status register.
+
+ The controller has two clock inputs: a 26 MHz and a 32 KHz external
+ oscillator. They need to be provided as input clocks. The controller provides
+ clocks to the downstream Matrix clock controller.
+
+ All available clocks are defined as preprocessor macros in the
+ 'dt-bindings/clock/zte,zx297520v3-clk.h' header. The resets are defined in the
+ 'dt-bindings/reset/zte,zx297520v3-reset.h' header.
+
+properties:
+ compatible:
+ items:
+ - const: zte,zx297520v3-topcrm
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: 26 MHz external oscillator
+ - description: 32 KHz external oscillator
+
+ clock-names:
+ items:
+ - const: osc26m
+ - const: osc32k
+
+ "#clock-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+ syscon-reboot:
+ type: object
+ $ref: /schemas/power/reset/syscon-reboot.yaml#
+ description:
+ Reboot method for the SoC.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/zte,zx297520v3-clk.h>
+ #include <dt-bindings/reset/zte,zx297520v3-reset.h>
+
+ clock-controller@13b000 {
+ compatible = "zte,zx297520v3-topcrm", "syscon";
+ reg = <0x0013b000 0x400>;
+ clocks = <&osc26m>, <&osc32k>;
+ clock-names = "osc26m", "osc32k";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+
+ syscon-reboot {
+ compatible = "syscon-reboot";
+ offset = <0x0>;
+ mask = <0x1>;
+ };
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 8629ed2aa82f..0f9e588e4839 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3867,8 +3867,11 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Odd fixes
F: Documentation/arch/arm/zte/
F: Documentation/devicetree/bindings/arm/zte.yaml
+F: Documentation/devicetree/bindings/soc/zte/
F: arch/arm/boot/dts/zte/
F: arch/arm/mach-zte/
+F: include/dt-bindings/clock/zte,zx297520v3-clk.h
+F: include/dt-bindings/reset/zte,zx297520v3-reset.h
ARM/ZYNQ ARCHITECTURE
M: Michal Simek <michal.simek@amd.com>
diff --git a/include/dt-bindings/clock/zte,zx297520v3-clk.h b/include/dt-bindings/clock/zte,zx297520v3-clk.h
new file mode 100644
index 000000000000..de1c08b6a5a9
--- /dev/null
+++ b/include/dt-bindings/clock/zte,zx297520v3-clk.h
@@ -0,0 +1,97 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) Stefan Dösinger.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_ZX297520V3_H
+#define __DT_BINDINGS_CLOCK_ZX297520V3_H
+
+#define ZX297520V3_M0_WCLK 1
+#define ZX297520V3_SRAM1_PCLK 2
+#define ZX297520V3_SRAM2_PCLK 3
+#define ZX297520V3_UART0_WCLK 4
+#define ZX297520V3_UART0_PCLK 5
+#define ZX297520V3_I2C0_WCLK 6
+#define ZX297520V3_I2C0_PCLK 7
+#define ZX297520V3_RTC_WCLK 8
+#define ZX297520V3_RTC_PCLK 9
+#define ZX297520V3_LPM_GSM_WCLK 10
+#define ZX297520V3_LPM_GSM_PCLK 11
+#define ZX297520V3_LPM_LTE_WCLK 12
+#define ZX297520V3_LPM_LTE_PCLK 13
+#define ZX297520V3_LPM_TD_WCLK 14
+#define ZX297520V3_LPM_TD_PCLK 15
+#define ZX297520V3_LPM_W_WCLK 16
+#define ZX297520V3_LPM_W_PCLK 17
+#define ZX297520V3_TIMER_T08_WCLK 18
+#define ZX297520V3_TIMER_T08_PCLK 19
+#define ZX297520V3_TIMER_T09_WCLK 20
+#define ZX297520V3_TIMER_T09_PCLK 21
+#define ZX297520V3_MPLL 22
+#define ZX297520V3_MPLL_D2 23
+#define ZX297520V3_MPLL_D3 24
+#define ZX297520V3_MPLL_D4 25
+#define ZX297520V3_MPLL_D5 26
+#define ZX297520V3_MPLL_D6 27
+#define ZX297520V3_MPLL_D8 28
+#define ZX297520V3_MPLL_D12 29
+#define ZX297520V3_MPLL_D16 30
+#define ZX297520V3_MPLL_D26 31
+#define ZX297520V3_UPLL 32
+#define ZX297520V3_UPLL_D2 33
+#define ZX297520V3_UPLL_D3 34
+#define ZX297520V3_UPLL_D4 35
+#define ZX297520V3_UPLL_D5 36
+#define ZX297520V3_UPLL_D6 37
+#define ZX297520V3_UPLL_D8 38
+#define ZX297520V3_UPLL_D12 39
+#define ZX297520V3_UPLL_D16 40
+#define ZX297520V3_DPLL 41
+#define ZX297520V3_DPLL_D2 42
+#define ZX297520V3_DPLL_D3 43
+#define ZX297520V3_DPLL_D4 44
+#define ZX297520V3_DPLL_D5 45
+#define ZX297520V3_DPLL_D6 46
+#define ZX297520V3_DPLL_D8 47
+#define ZX297520V3_DPLL_D12 48
+#define ZX297520V3_DPLL_D16 49
+#define ZX297520V3_GPLL 50
+#define ZX297520V3_GPLL_D2 51
+#define ZX297520V3_GPLL_D3 52
+#define ZX297520V3_GPLL_D4 53
+#define ZX297520V3_GPLL_D5 54
+#define ZX297520V3_GPLL_D6 55
+#define ZX297520V3_GPLL_D8 56
+#define ZX297520V3_GPLL_D12 57
+#define ZX297520V3_GPLL_D16 58
+#define ZX297520V3_PMM_WCLK 59
+#define ZX297520V3_PMM_PCLK 60
+#define ZX297520V3_OUT0_WCLK 61
+#define ZX297520V3_OUT1_WCLK 62
+#define ZX297520V3_OUT2_WCLK 63
+#define ZX297520V3_OUT32K_WCLK 64
+#define ZX297520V3_RMIIPHY_WCLK 65
+#define ZX297520V3_TIMER_T12_WCLK 66
+#define ZX297520V3_TIMER_T12_PCLK 67
+#define ZX297520V3_TIMER_T13_WCLK 68
+#define ZX297520V3_TIMER_T13_PCLK 69
+#define ZX297520V3_TIMER_T14_WCLK 70
+#define ZX297520V3_TIMER_T14_PCLK 71
+#define ZX297520V3_TIMER_T15_WCLK 72
+#define ZX297520V3_TIMER_T15_PCLK 73
+#define ZX297520V3_TIMER_T16_WCLK 74
+#define ZX297520V3_TIMER_T16_PCLK 75
+#define ZX297520V3_TIMER_T17_WCLK 76
+#define ZX297520V3_TIMER_T17_PCLK 77
+#define ZX297520V3_WDT_T18_WCLK 78
+#define ZX297520V3_WDT_T18_PCLK 79
+#define ZX297520V3_USIM1_WCLK 80
+#define ZX297520V3_USIM1_PCLK 81
+#define ZX297520V3_AHB_WCLK 82
+#define ZX297520V3_AHB_PCLK 83
+#define ZX297520V3_USB_WCLK 84
+#define ZX297520V3_USB_PCLK 85
+#define ZX297520V3_HSIC_WCLK 86
+#define ZX297520V3_HSIC_PCLK 87
+
+#endif /* __DT_BINDINGS_CLOCK_ZX297520V3_H */
diff --git a/include/dt-bindings/reset/zte,zx297520v3-reset.h b/include/dt-bindings/reset/zte,zx297520v3-reset.h
new file mode 100644
index 000000000000..43db72bb59de
--- /dev/null
+++ b/include/dt-bindings/reset/zte,zx297520v3-reset.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) Stefan Dösinger.
+ */
+
+#ifndef __DT_BINDINGS_RESET_ZX297520V3_H
+#define __DT_BINDINGS_RESET_ZX297520V3_H
+
+#define ZX297520V3_ZSP_RESET 0
+#define ZX297520V3_UART0_RESET 1
+#define ZX297520V3_I2C0_RESET 2
+#define ZX297520V3_RTC_RESET 3
+#define ZX297520V3_TIMER_T08_RESET 4
+#define ZX297520V3_TIMER_T09_RESET 5
+#define ZX297520V3_PMM_RESET 6
+#define ZX297520V3_GPIO_RESET 7
+#define ZX297520V3_GPIO8_RESET 8
+#define ZX297520V3_TIMER_T12_RESET 9
+#define ZX297520V3_TIMER_T13_RESET 10
+#define ZX297520V3_TIMER_T14_RESET 11
+#define ZX297520V3_TIMER_T15_RESET 12
+#define ZX297520V3_TIMER_T16_RESET 13
+#define ZX297520V3_TIMER_T17_RESET 14
+#define ZX297520V3_WDT_T18_RESET 15
+#define ZX297520V3_USIM1_RESET 16
+#define ZX297520V3_AHB_RESET 17
+#define ZX297520V3_USB_PHY_RESET 18
+#define ZX297520V3_USB_RESET 19
+#define ZX297520V3_HSIC_PHY_RESET 20
+#define ZX297520V3_HSIC_RESET 21
+
+#endif /* __DT_BINDINGS_RESET_ZX297520V3_H */
--
2.53.0
^ permalink raw reply related
* [PATCH RFC v5 04/12] mfd: zx297520v3: Add a clock and reset MFD driver.
From: Stefan Dösinger @ 2026-06-28 19:58 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Brian Masney
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
Stefan Dösinger
In-Reply-To: <20260628-zx29clk-v5-0-79ff044e4192@gmail.com>
This driver registers child devices for the zx297520v3 clock and reset
controllers. The clk-zx297520v3 and reset-zte-zx297520v3 submitted in
the next patches will drive the respective functionalities.
Signed-off-by: Stefan Dösinger <stefandoesinger@gmail.com>
---
Changes v5: Use MFD instead of Aux bus for top and matrix crm because of
extra functionality: Reboot in top, hwlock in Matrix.
LSP clocks stay with the aux bus and are thus not handled in this
driver. The clk driver will bind directly to the lspcrm node.
---
MAINTAINERS | 1 +
drivers/soc/Kconfig | 1 +
drivers/soc/Makefile | 1 +
drivers/soc/zte/Kconfig | 20 +++++++++++
drivers/soc/zte/Makefile | 3 ++
drivers/soc/zte/zx297520v3-crm.c | 76 ++++++++++++++++++++++++++++++++++++++++
6 files changed, 102 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index ee585982b859..57af566030db 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3871,6 +3871,7 @@ F: Documentation/devicetree/bindings/clock/zte,zx297520v3-lspcrm.yaml
F: Documentation/devicetree/bindings/soc/zte/
F: arch/arm/boot/dts/zte/
F: arch/arm/mach-zte/
+F: drivers/soc/zte/
F: include/dt-bindings/clock/zte,zx297520v3-clk.h
F: include/dt-bindings/reset/zte,zx297520v3-reset.h
diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
index a2d65adffb80..5cc1ade4ce52 100644
--- a/drivers/soc/Kconfig
+++ b/drivers/soc/Kconfig
@@ -31,5 +31,6 @@ source "drivers/soc/ux500/Kconfig"
source "drivers/soc/versatile/Kconfig"
source "drivers/soc/vt8500/Kconfig"
source "drivers/soc/xilinx/Kconfig"
+source "drivers/soc/zte/Kconfig"
endmenu
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index c9e689080ceb..63b3f340256c 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -37,3 +37,4 @@ obj-$(CONFIG_ARCH_U8500) += ux500/
obj-y += versatile/
obj-y += vt8500/
obj-y += xilinx/
+obj-y += zte/
diff --git a/drivers/soc/zte/Kconfig b/drivers/soc/zte/Kconfig
new file mode 100644
index 000000000000..1016fb99cf73
--- /dev/null
+++ b/drivers/soc/zte/Kconfig
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+if ARCH_ZTE || COMPILE_TEST
+
+menu "ZTE SoC drivers"
+
+config ZTE_ZX297520V3_CRM
+ tristate "ZTE zx297520v3 Clock and Reset Manager"
+ select MFD_CORE
+ default SOC_ZX297520V3
+ help
+ Say yes here to enable the driver for the ZTE zx297520v3 clock and
+ reset manager MFD driver. This driver provides the host device for
+ the clock and reset drivers and is required to boot the SoC. You
+ will also need to enable CLK_ZTE_ZX297520V3 and RESET_ZTE_ZX297520V3
+ to build the actual clock and reset submodule drivers.
+
+endmenu
+
+endif
diff --git a/drivers/soc/zte/Makefile b/drivers/soc/zte/Makefile
new file mode 100644
index 000000000000..090ba8aa06c1
--- /dev/null
+++ b/drivers/soc/zte/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+obj-$(CONFIG_ZTE_ZX297520V3_CRM) += zx297520v3-crm.o
diff --git a/drivers/soc/zte/zx297520v3-crm.c b/drivers/soc/zte/zx297520v3-crm.c
new file mode 100644
index 000000000000..bf5a71bc7706
--- /dev/null
+++ b/drivers/soc/zte/zx297520v3-crm.c
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2026 Stefan Dösinger
+ */
+
+#include <linux/platform_device.h>
+#include <linux/mfd/core.h>
+#include <linux/module.h>
+#include <linux/of.h>
+
+struct zx297520v3_crm_data {
+ const struct mfd_cell *cells;
+ unsigned int num_cells;
+};
+
+static const struct mfd_cell zx297520v3_topcrm_devs[] = {
+ {
+ .name = "zx297520v3-topclk",
+ },
+ {
+ .name = "zx297520v3-toprst",
+ },
+ {
+ .name = "zx297520v3-reboot",
+ .of_compatible = "syscon-reboot",
+ },
+};
+
+static const struct zx297520v3_crm_data zx297520v3_topcrm_data = {
+ zx297520v3_topcrm_devs,
+ ARRAY_SIZE(zx297520v3_topcrm_devs),
+};
+
+static const struct mfd_cell zx297520v3_matrixcrm_devs[] = {
+ {
+ .name = "zx297520v3-matrixclk",
+ },
+ {
+ .name = "zx297520v3-matrixrst",
+ },
+};
+
+static const struct zx297520v3_crm_data zx297520v3_matrixcrm_data = {
+ zx297520v3_matrixcrm_devs,
+ ARRAY_SIZE(zx297520v3_matrixcrm_devs),
+};
+
+static int zx297520v3_crm_probe(struct platform_device *pdev)
+{
+ const struct zx297520v3_crm_data *data;
+
+ data = of_device_get_match_data(&pdev->dev);
+ return devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_NONE, data->cells,
+ data->num_cells, NULL, 0, NULL);
+}
+
+static const struct of_device_id of_match_zx297520v3_crm[] = {
+ { .compatible = "zte,zx297520v3-topcrm", .data = &zx297520v3_topcrm_data },
+ { .compatible = "zte,zx297520v3-matrixcrm", .data = &zx297520v3_matrixcrm_data },
+ { }
+};
+MODULE_DEVICE_TABLE(of, of_match_zx297520v3_crm);
+
+static struct platform_driver zx297520v3_crm = {
+ .probe = zx297520v3_crm_probe,
+ .driver = {
+ .name = "zx297520v3-crm",
+ .of_match_table = of_match_zx297520v3_crm,
+ },
+};
+
+module_platform_driver(zx297520v3_crm);
+
+MODULE_AUTHOR("Stefan Dösinger <stefandoesinger@gmail.com>");
+MODULE_DESCRIPTION("ZTE zx297520v3 CRM MFD host driver");
+MODULE_LICENSE("GPL");
--
2.53.0
^ permalink raw reply related
* [PATCH RFC v5 03/12] dt-bindings: clk: zte: Add zx297520v3 LSP clock and reset bindings
From: Stefan Dösinger @ 2026-06-28 19:58 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Brian Masney
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
Stefan Dösinger
In-Reply-To: <20260628-zx29clk-v5-0-79ff044e4192@gmail.com>
The clock controller of the zx297520v3 Low Speed Peripherals is
relatively clean. One register per device with gates, muxes and resets
and for some devices a divider. There are even bits in the matrix
controller to control propagation of clock lines down to LSP.
The clocks are sorted by register address and I am convinced that the
device list is complete. There are however a few more registers that are
likely extra dividers for TDM and I2S devices
Signed-off-by: Stefan Dösinger <stefandoesinger@gmail.com>
---
Patch changelog:
v5:
Rename from lspclk to lspcrm
Remove matrixcrm from example
v4: Order properties compatible->reg->clocks->clock->names->#cells
---
.../bindings/clock/zte,zx297520v3-lspcrm.yaml | 96 ++++++++++++++++++++++
MAINTAINERS | 1 +
include/dt-bindings/clock/zte,zx297520v3-clk.h | 37 +++++++++
include/dt-bindings/reset/zte,zx297520v3-reset.h | 19 +++++
4 files changed, 153 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/zte,zx297520v3-lspcrm.yaml b/Documentation/devicetree/bindings/clock/zte,zx297520v3-lspcrm.yaml
new file mode 100644
index 000000000000..c510129068de
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/zte,zx297520v3-lspcrm.yaml
@@ -0,0 +1,96 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/zte,zx297520v3-lspcrm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ZTE zx297520v3 SoC LSP clock and reset controller
+
+maintainers:
+ - Stefan Dösinger <stefandoesinger@gmail.com>
+
+description: |
+ This clock and reset controller controls low speed peripherals on the board.
+ This is a relatively isolated subsystem containing UART, I2C, I2S and SPI
+ devices. The controller is responsible for bringing the devices out of reset
+ and enabling their clocks as needed.
+
+ The controller receives its clock signal from the matrix controller and need
+ to be declared as clock inputs.
+
+ All available clocks are defined as preprocessor macros in the
+ 'dt-bindings/clock/zte,zx297520v3-clk.h' header. Resets are defined in the
+ 'dt-bindings/reset/zte,zx297520v3-reset.h' header.
+
+properties:
+ compatible:
+ const: zte,zx297520v3-lspcrm
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Main PLL divided by 5 output from matrixcrm (124.8 MHz)
+ - description: Main PLL divided by 4 output from matrixcrm (156 MHz)
+ - description: Main PLL divided by 6 output from matrixcrm (104 MHz)
+ - description: Main PLL divided by 8 output from matrixcrm (78 MHz)
+ - description: Main PLL divided by 12 output from matrixcrm (52 MHz)
+ - description: Main oscillator output from matrixcrm (26 MHz)
+ - description: Timer oscillator output from matrixcrm (32 KHz)
+ - description: LSP pclk output from matrixcrm (26 MHz)
+ - description: TDM wclk mux output from matrixcrm
+ - description: DPLL divided by 4 output from matrixcrm (122.88 MHz)
+
+ clock-names:
+ items:
+ - const: mpll_d5
+ - const: mpll_d4
+ - const: mpll_d6
+ - const: mpll_d8
+ - const: mpll_d12
+ - const: osc26m
+ - const: osc32k
+ - const: pclk
+ - const: tdm_wclk
+ - const: dpll_d4
+
+ "#clock-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/zte,zx297520v3-clk.h>
+ #include <dt-bindings/reset/zte,zx297520v3-reset.h>
+
+ clock-controller@1400000 {
+ compatible = "zte,zx297520v3-lspcrm";
+ reg = <0x01400000 0x100>;
+ clocks = <&matrixcrm ZX297520V3_LSP_MPLL_D5_WCLK>,
+ <&matrixcrm ZX297520V3_LSP_MPLL_D4_WCLK>,
+ <&matrixcrm ZX297520V3_LSP_MPLL_D6_WCLK>,
+ <&matrixcrm ZX297520V3_LSP_MPLL_D8_WCLK>,
+ <&matrixcrm ZX297520V3_LSP_MPLL_D12_WCLK>,
+ <&matrixcrm ZX297520V3_LSP_OSC26M_WCLK>,
+ <&matrixcrm ZX297520V3_LSP_OSC32K_WCLK>,
+ <&matrixcrm ZX297520V3_LSP_PCLK>,
+ <&matrixcrm ZX297520V3_LSP_TDM_WCLK>,
+ <&matrixcrm ZX297520V3_LSP_DPLL_D4_WCLK>;
+ clock-names = "mpll_d5", "mpll_d4", "mpll_d6", "mpll_d8", "mpll_d12",
+ "osc26m", "osc32k", "pclk", "tdm_wclk", "dpll_d4";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 0f9e588e4839..ee585982b859 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3867,6 +3867,7 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Odd fixes
F: Documentation/arch/arm/zte/
F: Documentation/devicetree/bindings/arm/zte.yaml
+F: Documentation/devicetree/bindings/clock/zte,zx297520v3-lspcrm.yaml
F: Documentation/devicetree/bindings/soc/zte/
F: arch/arm/boot/dts/zte/
F: arch/arm/mach-zte/
diff --git a/include/dt-bindings/clock/zte,zx297520v3-clk.h b/include/dt-bindings/clock/zte,zx297520v3-clk.h
index 8a6aa456a708..3c390211f897 100644
--- a/include/dt-bindings/clock/zte,zx297520v3-clk.h
+++ b/include/dt-bindings/clock/zte,zx297520v3-clk.h
@@ -131,4 +131,41 @@
#define ZX297520V3_SRAM0_PCLK 35
#define ZX297520V3_GSM_CFG_PCLK 36
+#define ZX297520V3_TIMER_L1_WCLK 1
+#define ZX297520V3_TIMER_L1_PCLK 2
+#define ZX297520V3_WDT_L2_WCLK 3
+#define ZX297520V3_WDT_L2_PCLK 4
+#define ZX297520V3_WDT_L3_WCLK 5
+#define ZX297520V3_WDT_L3_PCLK 6
+#define ZX297520V3_PWM_WCLK 7
+#define ZX297520V3_PWM_PCLK 8
+#define ZX297520V3_I2S0_WCLK 9
+#define ZX297520V3_I2S0_PCLK 10
+#define ZX297520V3_I2S1_WCLK 11
+#define ZX297520V3_I2S1_PCLK 12
+#define ZX297520V3_QSPI_WCLK 13
+#define ZX297520V3_QSPI_PCLK 14
+#define ZX297520V3_UART1_WCLK 15
+#define ZX297520V3_UART1_PCLK 16
+#define ZX297520V3_I2C1_WCLK 17
+#define ZX297520V3_I2C1_PCLK 18
+#define ZX297520V3_SPI0_WCLK 19
+#define ZX297520V3_SPI0_PCLK 20
+#define ZX297520V3_TIMER_LB_WCLK 21
+#define ZX297520V3_TIMER_LB_PCLK 22
+#define ZX297520V3_TIMER_LC_WCLK 23
+#define ZX297520V3_TIMER_LC_PCLK 24
+#define ZX297520V3_UART2_WCLK 25
+#define ZX297520V3_UART2_PCLK 26
+#define ZX297520V3_WDT_LE_WCLK 27
+#define ZX297520V3_WDT_LE_PCLK 28
+#define ZX297520V3_TIMER_LF_WCLK 29
+#define ZX297520V3_TIMER_LF_PCLK 30
+#define ZX297520V3_SPI1_WCLK 31
+#define ZX297520V3_SPI1_PCLK 32
+#define ZX297520V3_TIMER_L11_WCLK 33
+#define ZX297520V3_TIMER_L11_PCLK 34
+#define ZX297520V3_TDM_WCLK 35
+#define ZX297520V3_TDM_PCLK 36
+
#endif /* __DT_BINDINGS_CLOCK_ZX297520V3_H */
diff --git a/include/dt-bindings/reset/zte,zx297520v3-reset.h b/include/dt-bindings/reset/zte,zx297520v3-reset.h
index 81ffc8bc34c5..85a2f0707cdc 100644
--- a/include/dt-bindings/reset/zte,zx297520v3-reset.h
+++ b/include/dt-bindings/reset/zte,zx297520v3-reset.h
@@ -39,4 +39,23 @@
#define ZX297520V3_GMAC_RESET 7
#define ZX297520V3_VOU_RESET 8
+#define ZX297520V3_TIMER_L1_RESET 0
+#define ZX297520V3_WDT_L2_RESET 1
+#define ZX297520V3_WDT_L3_RESET 2
+#define ZX297520V3_PWM_RESET 3
+#define ZX297520V3_I2S0_RESET 4
+#define ZX297520V3_I2S1_RESET 5
+#define ZX297520V3_QSPI_RESET 6
+#define ZX297520V3_UART1_RESET 7
+#define ZX297520V3_I2C1_RESET 8
+#define ZX297520V3_SPI0_RESET 9
+#define ZX297520V3_TIMER_LB_RESET 10
+#define ZX297520V3_TIMER_LC_RESET 11
+#define ZX297520V3_UART2_RESET 12
+#define ZX297520V3_WDT_LE_RESET 13
+#define ZX297520V3_TIMER_LF_RESET 14
+#define ZX297520V3_SPI1_RESET 15
+#define ZX297520V3_TIMER_L11_RESET 16
+#define ZX297520V3_TDM_RESET 17
+
#endif /* __DT_BINDINGS_RESET_ZX297520V3_H */
--
2.53.0
^ permalink raw reply related
* [PATCH RFC v5 10/12] clk: zte: Introduce a driver for zx297520v3 LSP clocks and resets
From: Stefan Dösinger @ 2026-06-28 19:59 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Brian Masney
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
Stefan Dösinger
In-Reply-To: <20260628-zx29clk-v5-0-79ff044e4192@gmail.com>
"LSP" is ZTE's term for this part of the SoC, I suspect it stands for
"low speed peripherals". The main UART is here, together with the flash
controller and more surplus proprietary timers.
It also has one more I2C controller that supposedly connects to a
battery charger, SPI for displays and I2S for analog telephones. The
boards I have don't have any of these components though.
Signed-off-by: Stefan Dösinger <stefandoesinger@gmail.com>
---
Version 5:
Removed unused tdm_lsp_sel. Fix zx297529 vs zx297520 typo.
Adjusted .compatible to zte,zx297520v3-lspcrm
---
drivers/clk/zte/clk-zx297520v3.c | 208 +++++++++++++++++++++++++++++++++++++++
1 file changed, 208 insertions(+)
diff --git a/drivers/clk/zte/clk-zx297520v3.c b/drivers/clk/zte/clk-zx297520v3.c
index 17e1f741b48c..f4ab065ee496 100644
--- a/drivers/clk/zte/clk-zx297520v3.c
+++ b/drivers/clk/zte/clk-zx297520v3.c
@@ -616,9 +616,217 @@ static struct platform_driver clk_zx297520v3_matrix = {
},
};
+/* LSP clock entries have a common pattern: Bit 0 for WCLK, Bit 1 for PCLK. Bit 4 (and sometimes
+ * more) for WCLK mux.
+ *
+ * Bit 8 and 9 are resets handled by the reset-zte-zx297520v3 driver.
+ *
+ * Bits 15:12 can be a divisor, but not all clocks have it. Some clocks have a divisor in 19:16.
+ *
+ * The ID given in this table is the first register in the device's MMIO space. ZTE's drivers
+ * usually call this a version register, but it looks more like a device identifier.
+ *
+ * It looks like the registers map to devices like this:
+ *
+ * Timer reg function div dev offset(lsp + xxxx) ID
+ * 0x0: Read-only, probably device identifier 0x00752100
+ * 0x4: timer_l1 Y 0x1000 0x02020000
+ * 0x8: watchdog_l2 Y 0x2000 0x02020000
+ * 0xc: watchdog_l3 Y 0x3000 0x02020000
+ * 0x10: pwm N 0x4000 0x01020000
+ * 0x14: i2s0 Yh 0x5000 0x01030000
+ * 0x18: always 0 - - -
+ * 0x1c: i2s1 Yh 0x6000 0x01030000
+ * 0x20: always 0 - - -
+ * 0x24: qspi N 0x7000 0x01040000
+ * 0x28: uart1 N 0x8000 0x01060000
+ * 0x2c: i2c1 N 0x9000 0x01020000
+ * 0x30: spi0 Y 0xa000 0x01040000
+ * 0x34: timer_lb Y 0xb000 0x02020000
+ * 0x38: timer_lc Y 0xc000 0x02020000
+ * 0x3c: uart2 N 0xd000 0x01060000
+ * 0x40: watchdog_le Y 0xe000 0x02020000
+ * 0x44: timer_lf Y 0xf000 0x02020000
+ * 0x48: spi1 Y 0x10000 0x01040000
+ * 0x4c: timer_l11 Y 0x11000 0x02020000
+ * 0x50: tdm Yh 0x12000 0x01040000
+ *
+ * Registers 0x58, 0x5c, 0x60, 0x64, 0x68 seem to contain more controls for i2s and tdm.
+ *
+ * I am not sure about the device at offset 0x4000 (clk reg 0x10). The ID matches that of i2c, but
+ * it has a larger register set. I suspect it is a PWM device, but I have not seen any ZTE kernel
+ * operate it - even devices with displays only use a GPIO to control the backlight.
+ */
+
+static const char * const timer_lsp_sel[] = {
+ "lsp_osc32k",
+ "lsp_osc26m",
+};
+
+static const char * const uart_lsp_sel[] = {
+ "lsp_osc26m",
+ "lsp_mpll_d6",
+};
+
+static const char * const i2s_lsp_sel[] = {
+ "lsp_osc26m",
+ "lsp_dpll_d4",
+ "lsp_mpll_d6",
+ /* Unknown */
+};
+
+static const char * const spi_lsp_sel[] = {
+ "lsp_osc26m",
+ "lsp_mpll_d4",
+ "lsp_mpll_d6",
+ /* Unknown */
+};
+
+static const char * const qspi_lsp_sel[] = {
+ "lsp_osc26m",
+ "lsp_mpll_d4",
+ "lsp_mpll_d5",
+ "lsp_mpll_d6",
+ "lsp_mpll_d8",
+ "lsp_mpll_d12",
+ "lsp_osc26m",
+ "lsp_osc26m",
+};
+
+static const struct zx_mux_desc zx297520v3_lsp_muxes[] = {
+ MUX(0, "timer_l1_mux", timer_lsp_sel, 0x04, 4, 1),
+ MUX(0, "wdt_l2_mux", timer_lsp_sel, 0x08, 4, 1),
+ MUX(0, "wdt_l3_mux", timer_lsp_sel, 0x0c, 4, 1),
+ /* PWM: No mux bit can be set */
+ MUX(0, "i2s0_mux", i2s_lsp_sel, 0x14, 4, 2),
+ /* 0x18: Always 0 */
+ MUX(0, "i2s1_mux", i2s_lsp_sel, 0x1c, 4, 2),
+ /* 0x20: Always 0 */
+ MUX(0, "qspi_mux", qspi_lsp_sel, 0x24, 4, 3),
+ MUX(0, "uart1_mux", uart_lsp_sel, 0x28, 4, 1),
+ MUX(0, "i2c1_mux", uart_lsp_sel, 0x2c, 4, 1),
+ MUX(0, "spi0_mux", spi_lsp_sel, 0x30, 4, 2),
+ MUX(0, "timer_lb_mux", timer_lsp_sel, 0x34, 4, 1),
+ MUX(0, "timer_lc_mux", timer_lsp_sel, 0x38, 4, 1),
+ MUX(0, "uart2_mux", uart_lsp_sel, 0x3c, 4, 1),
+ MUX(0, "wdt_le_mux", timer_lsp_sel, 0x40, 4, 1),
+ MUX(0, "timer_lf_mux", timer_lsp_sel, 0x44, 4, 1),
+ MUX(0, "spi1_mux", spi_lsp_sel, 0x48, 4, 2),
+ MUX(0, "timer_l11_mux", timer_lsp_sel, 0x4c, 4, 1),
+ /* TDM: No mux in LSP. Instead, it is in matrix with a separate clk line to LSP */
+};
+
+static const struct zx_div_desc zx297520v3_lsp_dividers[] = {
+ DIV(0, "timer_l1_div", "timer_l1_mux", 0x04, 12, 4),
+ DIV(0, "wdt_l2_div", "wdt_l2_mux", 0x08, 12, 4),
+ DIV(0, "wdt_l3_div", "wdt_l3_mux", 0x0c, 12, 4),
+ /* PWM: No div */
+ DIV(0, "i2s0_div", "i2s0_mux", 0x14, 16, 4),
+ /* 0x18: Always 0 */
+ DIV(0, "i2s1_div", "i2s1_mux", 0x1c, 16, 4),
+ /* 0x20: Always 0 */
+ /* qspi, uart1, i2c1: No div */
+ DIV(0, "spi0_div", "spi0_mux", 0x30, 12, 4),
+ DIV(0, "timer_lb_div", "timer_lb_mux", 0x34, 12, 4),
+ DIV(0, "timer_lc_div", "timer_lc_mux", 0x38, 12, 4),
+ /* uart2: No div */
+ DIV(0, "wdt_le_div", "wdt_le_mux", 0x40, 12, 4),
+ DIV(0, "timer_lf_div", "timer_lf_mux", 0x44, 12, 4),
+ DIV(0, "spi1_div", "spi1_mux", 0x48, 12, 4),
+ DIV(0, "timer_l11_div", "timer_l11_mux", 0x4c, 12, 4),
+ DIV(0, "tdm_div", "lsp_tdm_wclk", 0x50, 16, 4),
+};
+
+static const struct zx_gate_desc zx297520v3_lsp_gates[] = {
+ GATE(ZX297520V3_TIMER_L1_WCLK, "timer_l1_wclk", "timer_l1_div", 0x04, 0, 0),
+ GATE(ZX297520V3_TIMER_L1_PCLK, "timer_l1_pclk", "lsp_pclk", 0x04, 1, 0),
+ GATE(ZX297520V3_WDT_L2_WCLK, "wdt_l2_wclk", "wdt_l2_div", 0x08, 0, 0),
+ GATE(ZX297520V3_WDT_L2_PCLK, "wdt_l2_pclk", "lsp_pclk", 0x08, 1, 0),
+ GATE(ZX297520V3_WDT_L3_WCLK, "wdt_l3_wclk", "wdt_l3_div", 0x0c, 0, 0),
+ GATE(ZX297520V3_WDT_L3_PCLK, "wdt_l3_pclk", "lsp_pclk", 0x0c, 1, 0),
+ /* I don't know the LSP parent. It must be one of the LSP inputs though. */
+ GATE(ZX297520V3_PWM_WCLK, "pwm_wclk", "lsp_osc26m", 0x10, 0, 0),
+ GATE(ZX297520V3_PWM_PCLK, "pwm_pclk", "lsp_pclk", 0x10, 1, 0),
+ GATE(ZX297520V3_I2S0_WCLK, "i2s0_wclk", "i2s0_div", 0x14, 0, 0),
+ GATE(ZX297520V3_I2S0_PCLK, "i2s0_pclk", "lsp_pclk", 0x14, 1, 0),
+ /* 0x1c: Always 0 */
+ GATE(ZX297520V3_I2S1_WCLK, "i2s1_wclk", "i2s1_div", 0x1c, 0, 0),
+ GATE(ZX297520V3_I2S1_PCLK, "i2s1_pclk", "lsp_pclk", 0x1c, 1, 0),
+ /* 0x20: Always 0 */
+ GATE(ZX297520V3_QSPI_WCLK, "qspi_wclk", "qspi_mux", 0x24, 0, 0),
+ GATE(ZX297520V3_QSPI_PCLK, "qspi_pclk", "lsp_pclk", 0x24, 1, 0),
+ GATE(ZX297520V3_UART1_WCLK, "uart1_wclk", "uart1_mux", 0x28, 0, 0),
+ GATE(ZX297520V3_UART1_PCLK, "uart1_pclk", "lsp_pclk", 0x28, 1, 0),
+ GATE(ZX297520V3_I2C1_WCLK, "i2c1_wclk", "i2c1_mux", 0x2c, 0, 0),
+ GATE(ZX297520V3_I2C1_PCLK, "i2c1_pclk", "lsp_pclk", 0x2c, 1, 0),
+ GATE(ZX297520V3_SPI0_WCLK, "spi0_wclk", "spi0_div", 0x30, 0, 0),
+ GATE(ZX297520V3_SPI0_PCLK, "spi0_pclk", "lsp_pclk", 0x30, 1, 0),
+ GATE(ZX297520V3_TIMER_LB_WCLK, "timer_lb_wclk", "timer_lb_div", 0x34, 0, 0),
+ GATE(ZX297520V3_TIMER_LB_PCLK, "timer_lb_pclk", "lsp_pclk", 0x34, 1, 0),
+ GATE(ZX297520V3_TIMER_LC_WCLK, "timer_lc_wclk", "timer_lc_div", 0x38, 0, 0),
+ GATE(ZX297520V3_TIMER_LC_PCLK, "timer_lc_pclk", "lsp_pclk", 0x38, 1, 0),
+ GATE(ZX297520V3_UART2_WCLK, "uart2_wclk", "uart2_mux", 0x3c, 0, 0),
+ GATE(ZX297520V3_UART2_PCLK, "uart2_pclk", "lsp_pclk", 0x3c, 1, 0),
+ GATE(ZX297520V3_WDT_LE_WCLK, "wdt_le_wclk", "wdt_le_div", 0x40, 0, 0),
+ GATE(ZX297520V3_WDT_LE_PCLK, "wdt_le_pclk", "lsp_pclk", 0x40, 1, 0),
+ GATE(ZX297520V3_TIMER_LF_WCLK, "timer_lf_wclk", "timer_lf_div", 0x44, 0, 0),
+ GATE(ZX297520V3_TIMER_LF_PCLK, "timer_lf_pclk", "lsp_pclk", 0x44, 1, 0),
+ GATE(ZX297520V3_SPI1_WCLK, "spi1_wclk", "spi1_div", 0x48, 0, 0),
+ GATE(ZX297520V3_SPI1_PCLK, "spi1_pclk", "lsp_pclk", 0x48, 1, 0),
+ GATE(ZX297520V3_TIMER_L11_WCLK, "timer_l11_wclk", "timer_l11_div", 0x4c, 0, 0),
+ GATE(ZX297520V3_TIMER_L11_PCLK, "timer_l11_pclk", "lsp_pclk", 0x4c, 1, 0),
+ GATE(ZX297520V3_TDM_WCLK, "tdm_wclk", "tdm_div", 0x50, 0, 0),
+ GATE(ZX297520V3_TDM_PCLK, "tdm_pclk", "lsp_pclk", 0x50, 1, 0),
+};
+
+static const char * const zx297520v3_lsp_inputs[] = {
+ "mpll_d5", "mpll_d4", "mpll_d6", "mpll_d8", "mpll_d12",
+ "osc26m", "osc32k", "tdm_wclk", "dpll_d4"
+};
+
+static const char * const zx297520v3_lsp_inputs_enable[] = {
+ "pclk"
+};
+
+static const struct zx_clk_data zx297520v3_lsprm_data = {
+ .inputs_enable = zx297520v3_lsp_inputs_enable,
+ .num_inputs_enable = ARRAY_SIZE(zx297520v3_lsp_inputs_enable),
+ .inputs = zx297520v3_lsp_inputs,
+ .num_inputs = ARRAY_SIZE(zx297520v3_lsp_inputs),
+ .muxes = zx297520v3_lsp_muxes,
+ .num_muxes = ARRAY_SIZE(zx297520v3_lsp_muxes),
+ .divs = zx297520v3_lsp_dividers,
+ .num_divs = ARRAY_SIZE(zx297520v3_lsp_dividers),
+ .gates = zx297520v3_lsp_gates,
+ .num_gates = ARRAY_SIZE(zx297520v3_lsp_gates),
+ .reset_auxdev_name = "zx297520v3_lsprst"
+};
+
+static const struct of_device_id of_match_zx297520v3[] = {
+ { .compatible = "zte,zx297520v3-lspcrm", .data = &zx297520v3_lsprm_data },
+ { }
+};
+MODULE_DEVICE_TABLE(of, of_match_zx297520v3);
+
+static int zx297520v3_lspclk_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+
+ return zx_clk_common_probe(dev, dev->of_node, device_get_match_data(dev));
+}
+
+static struct platform_driver clk_zx297520v3_lsp = {
+ .probe = zx297520v3_lspclk_probe,
+ .driver = {
+ .name = "clk-zx297520v3",
+ .of_match_table = of_match_zx297520v3,
+ },
+};
+
static struct platform_driver * const clk_zx297520v3_drivers[] = {
&clk_zx297520v3_top,
&clk_zx297520v3_matrix,
+ &clk_zx297520v3_lsp,
};
static int __init clk_zx297520v3_init(void)
--
2.53.0
^ permalink raw reply related
* [PATCH RFC v5 12/12] ARM: dts: zte: Declare zx297520v3 CRM device nodes
From: Stefan Dösinger @ 2026-06-28 19:59 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Brian Masney
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
Stefan Dösinger
In-Reply-To: <20260628-zx29clk-v5-0-79ff044e4192@gmail.com>
This makes use of the driver added in the previous patches. It wires up
the uart clocks and resets and allows getting rid of the placeholder
uartclk node.
Signed-off-by: Stefan Dösinger <stefandoesinger@gmail.com>
---
Version 5:
Re-name from *clk to *crm
Add the syscon-reboot node here because the binding requires it
Re-add accidentally dropped uart2 IRQ
---
arch/arm/boot/dts/zte/zx297520v3.dtsi | 97 ++++++++++++++++++++++++++++++++---
1 file changed, 89 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/zte/zx297520v3.dtsi b/arch/arm/boot/dts/zte/zx297520v3.dtsi
index a16c30a164bb..2ae6b78bc034 100644
--- a/arch/arm/boot/dts/zte/zx297520v3.dtsi
+++ b/arch/arm/boot/dts/zte/zx297520v3.dtsi
@@ -4,6 +4,8 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/zte,zx297520v3-reset.h>
+#include <dt-bindings/clock/zte,zx297520v3-clk.h>
/ {
#address-cells = <1>;
@@ -20,13 +22,16 @@ cpu@0 {
};
};
- /* Base bus clock and default for the UART. It will be replaced once a clock driver has
- * been added.
- */
- uartclk: uartclk-26000000 {
- #clock-cells = <0>;
+ osc26m: osc26m {
compatible = "fixed-clock";
clock-frequency = <26000000>;
+ #clock-cells = <0>;
+ };
+
+ osc32k: osc32k {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
};
timer {
@@ -70,13 +75,87 @@ gic: interrupt-controller@f2000000 {
<0xf2040000 0x20000>;
};
+ topcrm: syscon@13b000 {
+ compatible = "zte,zx297520v3-topcrm", "syscon";
+ reg = <0x0013b000 0x400>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ clocks = <&osc26m>, <&osc32k>;
+ clock-names = "osc26m", "osc32k";
+
+ syscon-reboot {
+ compatible = "syscon-reboot";
+ offset = <0x0>;
+ mask = <0x1>;
+ };
+ };
+
+ matrixcrm: syscon@1306000 {
+ compatible = "zte,zx297520v3-matrixcrm";
+ reg = <0x01306000 0x400>;
+ clocks = <&osc26m>, <&osc32k>,
+ <&topcrm ZX297520V3_MPLL>, <&topcrm ZX297520V3_MPLL_D2>,
+ <&topcrm ZX297520V3_MPLL_D3>, <&topcrm ZX297520V3_MPLL_D4>,
+ <&topcrm ZX297520V3_MPLL_D5>, <&topcrm ZX297520V3_MPLL_D6>,
+ <&topcrm ZX297520V3_MPLL_D8>, <&topcrm ZX297520V3_MPLL_D12>,
+ <&topcrm ZX297520V3_MPLL_D16>, <&topcrm ZX297520V3_MPLL_D26>,
+ <&topcrm ZX297520V3_UPLL>, <&topcrm ZX297520V3_UPLL_D2>,
+ <&topcrm ZX297520V3_UPLL_D3>, <&topcrm ZX297520V3_UPLL_D4>,
+ <&topcrm ZX297520V3_UPLL_D5>, <&topcrm ZX297520V3_UPLL_D6>,
+ <&topcrm ZX297520V3_UPLL_D8>, <&topcrm ZX297520V3_UPLL_D12>,
+ <&topcrm ZX297520V3_UPLL_D16>,
+ <&topcrm ZX297520V3_DPLL>, <&topcrm ZX297520V3_DPLL_D2>,
+ <&topcrm ZX297520V3_DPLL_D3>, <&topcrm ZX297520V3_DPLL_D4>,
+ <&topcrm ZX297520V3_DPLL_D5>, <&topcrm ZX297520V3_DPLL_D6>,
+ <&topcrm ZX297520V3_DPLL_D8>, <&topcrm ZX297520V3_DPLL_D12>,
+ <&topcrm ZX297520V3_DPLL_D16>,
+ <&topcrm ZX297520V3_GPLL>, <&topcrm ZX297520V3_GPLL_D2>,
+ <&topcrm ZX297520V3_GPLL_D3>, <&topcrm ZX297520V3_GPLL_D4>,
+ <&topcrm ZX297520V3_GPLL_D5>, <&topcrm ZX297520V3_GPLL_D6>,
+ <&topcrm ZX297520V3_GPLL_D8>, <&topcrm ZX297520V3_GPLL_D12>,
+ <&topcrm ZX297520V3_GPLL_D16>;
+ clock-names = "osc26m", "osc32k", "mpll", "mpll_d2", "mpll_d3", "mpll_d4",
+ "mpll_d5", "mpll_d6", "mpll_d8", "mpll_d12", "mpll_d16",
+ "mpll_d26", "upll", "upll_d2", "upll_d3", "upll_d4",
+ "upll_d5", "upll_d6", "upll_d8", "upll_d12", "upll_d16",
+ "dpll", "dpll_d2", "dpll_d3", "dpll_d4", "dpll_d5", "dpll_d6",
+ "dpll_d8", "dpll_d12", "dpll_d16", "gpll", "gpll_d2",
+ "gpll_d3", "gpll_d4", "gpll_d5", "gpll_d6", "gpll_d8",
+ "gpll_d12", "gpll_d16";
+ #clock-cells = <1>;
+ #hwlock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ lspcrm: clock-controller@1400000 {
+ compatible = "zte,zx297520v3-lspcrm";
+ reg = <0x01400000 0x100>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+
+ clocks = <&matrixcrm ZX297520V3_LSP_MPLL_D5_WCLK>,
+ <&matrixcrm ZX297520V3_LSP_MPLL_D4_WCLK>,
+ <&matrixcrm ZX297520V3_LSP_MPLL_D6_WCLK>,
+ <&matrixcrm ZX297520V3_LSP_MPLL_D8_WCLK>,
+ <&matrixcrm ZX297520V3_LSP_MPLL_D12_WCLK>,
+ <&matrixcrm ZX297520V3_LSP_OSC26M_WCLK>,
+ <&matrixcrm ZX297520V3_LSP_OSC32K_WCLK>,
+ <&matrixcrm ZX297520V3_LSP_PCLK>,
+ <&matrixcrm ZX297520V3_LSP_TDM_WCLK>,
+ <&matrixcrm ZX297520V3_LSP_DPLL_D4_WCLK>;
+ clock-names = "mpll_d5", "mpll_d4", "mpll_d6", "mpll_d8", "mpll_d12",
+ "osc26m", "osc32k", "pclk", "tdm_wclk", "dpll_d4";
+ };
+
+
uart0: serial@131000 {
compatible = "arm,pl011", "arm,primecell";
arm,primecell-periphid = <0x0018c011>;
reg = <0x00131000 0x1000>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&uartclk>, <&uartclk>;
+ clocks = <&topcrm ZX297520V3_UART0_WCLK>, <&topcrm ZX297520V3_UART0_PCLK>;
clock-names = "uartclk", "apb_pclk";
+ resets = <&topcrm ZX297520V3_UART0_RESET>;
status = "disabled";
};
@@ -85,8 +164,9 @@ uart1: serial@1408000 {
arm,primecell-periphid = <0x0018c011>;
reg = <0x01408000 0x1000>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&uartclk>, <&uartclk>;
+ clocks = <&lspcrm ZX297520V3_UART1_WCLK>, <&lspcrm ZX297520V3_UART1_PCLK>;
clock-names = "uartclk", "apb_pclk";
+ resets = <&lspcrm ZX297520V3_UART1_RESET>;
status = "disabled";
};
@@ -95,8 +175,9 @@ uart2: serial@140d000 {
arm,primecell-periphid = <0x0018c011>;
reg = <0x0140d000 0x1000>;
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&uartclk>, <&uartclk>;
+ clocks = <&lspcrm ZX297520V3_UART2_WCLK>, <&lspcrm ZX297520V3_UART2_PCLK>;
clock-names = "uartclk", "apb_pclk";
+ resets = <&lspcrm ZX297520V3_UART2_RESET>;
status = "disabled";
};
};
--
2.53.0
^ permalink raw reply related
* [PATCH RFC v5 11/12] reset: zte: Add a zx297520v3 reset driver
From: Stefan Dösinger @ 2026-06-28 19:59 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Brian Masney
Cc: linux-clk, devicetree, linux-kernel, linux-arm-kernel,
Stefan Dösinger
In-Reply-To: <20260628-zx29clk-v5-0-79ff044e4192@gmail.com>
This drives the MFD child devices created by the zx297520v3-crm driver
as well as the aux device created by the zx297520v3-lspclk driver.
Signed-off-by: Stefan Dösinger <stefandoesinger@gmail.com>
---
v5:
Make top and matrix MFD children instead of aux devices
Split USB PHY reset into its own reset ID
Remove USB reset wait code - this will be handled via syscon from a
future minimal phy-zx29-usb driver
---
MAINTAINERS | 1 +
drivers/reset/Kconfig | 11 ++
drivers/reset/Makefile | 1 +
drivers/reset/reset-zte-zx297520v3.c | 274 +++++++++++++++++++++++++++++++++++
4 files changed, 287 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 297c15a2c860..d96bfb51c90e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3872,6 +3872,7 @@ F: Documentation/devicetree/bindings/soc/zte/
F: arch/arm/boot/dts/zte/
F: arch/arm/mach-zte/
F: drivers/clk/zte/
+F: drivers/reset/reset-zte-zx297520v3.c
F: drivers/soc/zte/
F: include/dt-bindings/clock/zte,zx297520v3-clk.h
F: include/dt-bindings/reset/zte,zx297520v3-reset.h
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index d009eb0849a3..116dd23f1b8e 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -404,6 +404,17 @@ config RESET_UNIPHIER_GLUE
on UniPhier SoCs. Say Y if you want to control reset signals
provided by the glue layer.
+config RESET_ZTE_ZX297520V3
+ tristate "ZTE zx297520v3 Reset Driver"
+ depends on (ARCH_ZTE || COMPILE_TEST)
+ default CLK_ZTE_ZX297520V3
+ select AUXILIARY_BUS
+ help
+ This enables the reset controller for ZTE zx297520v3 SoCs. The reset
+ controller is part of the clock controller on this SoC. This driver
+ operates on an auxiliary device exposed by the clock driver. Enable
+ this driver if you plan to boot the kernel on a zx297520v3 based SoC.
+
config RESET_ZYNQ
bool "ZYNQ Reset Driver" if COMPILE_TEST
default ARCH_ZYNQ
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 3e52569bd276..9a8a48d44dc4 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -50,5 +50,6 @@ obj-$(CONFIG_RESET_TI_TPS380X) += reset-tps380x.o
obj-$(CONFIG_RESET_TN48M_CPLD) += reset-tn48m.o
obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
obj-$(CONFIG_RESET_UNIPHIER_GLUE) += reset-uniphier-glue.o
+obj-$(CONFIG_RESET_ZTE_ZX297520V3) += reset-zte-zx297520v3.o
obj-$(CONFIG_RESET_ZYNQ) += reset-zynq.o
obj-$(CONFIG_RESET_ZYNQMP) += reset-zynqmp.o
diff --git a/drivers/reset/reset-zte-zx297520v3.c b/drivers/reset/reset-zte-zx297520v3.c
new file mode 100644
index 000000000000..8ef434904230
--- /dev/null
+++ b/drivers/reset/reset-zte-zx297520v3.c
@@ -0,0 +1,274 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2026 Stefan Dösinger
+ */
+#include <dt-bindings/reset/zte,zx297520v3-reset.h>
+#include <linux/reset-controller.h>
+#include <linux/platform_device.h>
+#include <linux/auxiliary_bus.h>
+#include <linux/mfd/syscon.h>
+#include <linux/regmap.h>
+#include <linux/iopoll.h>
+
+/* Most devices on the zx297520v3 SoC have one reset bit per clock line. As a rule of thumb, the
+ * lower bit disconnects the device from the bus, similarly to turning off PCLK - registers read 0
+ * or hang indefinitely. Unlike PCLK, this reset may have a lingering effect after deasserting.
+ * E.g. timers will be disabled, but retain their counter value.
+ *
+ * The other bit resets the actual device registers.
+ *
+ * For some devices, e.g. GMAC, the reset bits behave in the same way: They disconnect the device
+ * and registers will have their default state after deasserting. For devices that have both reset
+ * bits, both need to be deasserted for the device to function.
+ */
+struct zte_reset_reg {
+ u32 mask;
+ u16 reg;
+};
+
+struct zte_reset_info {
+ const struct zte_reset_reg *resets;
+ unsigned int num;
+};
+
+struct zte_reset {
+ struct reset_controller_dev rcdev;
+ struct regmap *map;
+ const struct zte_reset_reg *resets;
+};
+
+static inline struct zte_reset *to_zte_reset(struct reset_controller_dev *rcdev)
+{
+ return container_of(rcdev, struct zte_reset, rcdev);
+}
+
+static int zx29_rst_assert(struct reset_controller_dev *rcdev, unsigned long id)
+{
+ struct zte_reset *rst = to_zte_reset(rcdev);
+
+ return regmap_clear_bits(rst->map, rst->resets[id].reg, rst->resets[id].mask);
+}
+
+static int zx29_rst_deassert(struct reset_controller_dev *rcdev, unsigned long id)
+{
+ struct zte_reset *rst = to_zte_reset(rcdev);
+
+ return regmap_set_bits(rst->map, rst->resets[id].reg, rst->resets[id].mask);
+}
+
+static int zx29_rst_status(struct reset_controller_dev *rcdev, unsigned long id)
+{
+ struct zte_reset *rst = to_zte_reset(rcdev);
+ int res;
+
+ res = regmap_test_bits(rst->map, rst->resets[id].reg, rst->resets[id].mask);
+ if (res < 0)
+ return res;
+
+ return !res;
+}
+
+static const struct reset_control_ops zx29_rst_ops = {
+ .assert = zx29_rst_assert,
+ .deassert = zx29_rst_deassert,
+ .status = zx29_rst_status,
+};
+
+static const struct zte_reset_reg zx297520v3_top_resets[] = {
+ /* This bit is set by ZTE's cpko.ko blob, it looks like a reset bit for the LTE DSP
+ * coprocessor. Clocks for it are in matrixcrm.
+ */
+ [ZX297520V3_ZSP_RESET] = { .reg = 0x13c, .mask = BIT(0) },
+
+ [ZX297520V3_UART0_RESET] = { .reg = 0x78, .mask = BIT(6) | BIT(7) },
+ [ZX297520V3_I2C0_RESET] = { .reg = 0x74, .mask = BIT(8) | BIT(9) },
+ /* Only one reset. Bit 5 is settable but does not do anything observable */
+ [ZX297520V3_RTC_RESET] = { .reg = 0x74, .mask = BIT(4) },
+ [ZX297520V3_TIMER_T08_RESET] = { .reg = 0x78, .mask = BIT(4) | BIT(5) },
+ [ZX297520V3_TIMER_T09_RESET] = { .reg = 0x78, .mask = BIT(2) | BIT(3) },
+ /* Only one reset. Bit 0 is settable but does not do anything observable */
+ [ZX297520V3_PMM_RESET] = { .reg = 0x74, .mask = BIT(1) },
+
+ /* I haven't found any clocks for GPIO. It probably wouldn't make much
+ * sense anyway. Only one reset bit per controller.
+ */
+ [ZX297520V3_GPIO_RESET] = { .reg = 0x74, .mask = BIT(3) },
+ [ZX297520V3_GPIO8_RESET] = { .reg = 0x74, .mask = BIT(2) },
+
+ [ZX297520V3_TIMER_T12_RESET] = { .reg = 0x74, .mask = BIT(6) | BIT(7) },
+ [ZX297520V3_TIMER_T13_RESET] = { .reg = 0x7c, .mask = BIT(0) | BIT(1) },
+ [ZX297520V3_TIMER_T14_RESET] = { .reg = 0x7c, .mask = BIT(2) | BIT(3) },
+ [ZX297520V3_TIMER_T15_RESET] = { .reg = 0x74, .mask = BIT(10) | BIT(11) },
+ [ZX297520V3_TIMER_T16_RESET] = { .reg = 0x7c, .mask = BIT(4) | BIT(5) },
+ [ZX297520V3_TIMER_T17_RESET] = { .reg = 0x12c, .mask = BIT(0) | BIT(1) },
+ [ZX297520V3_WDT_T18_RESET] = { .reg = 0x74, .mask = BIT(12) | BIT(13) },
+ [ZX297520V3_USIM1_RESET] = { .reg = 0x74, .mask = BIT(14) | BIT(15) },
+ [ZX297520V3_AHB_RESET] = { .reg = 0x70, .mask = BIT(0) | BIT(1) },
+
+ /* USB reset. 0x84 returns the USB device status (0x1 for HSIC up, 0x2 for USB up, but
+ * all 3 bits (PCLK, WCLK, PHY) need to be deasserted for the device to report ready.
+ * Thus polling the status is the responsibility of the USB PHY driver.
+ */
+ [ZX297520V3_USB_PHY_RESET] = { .reg = 0x80, .mask = BIT(3) },
+ [ZX297520V3_USB_RESET] = { .reg = 0x80, .mask = BIT(4) | BIT(5) },
+ [ZX297520V3_HSIC_PHY_RESET] = { .reg = 0x80, .mask = BIT(0) },
+ [ZX297520V3_HSIC_RESET] = { .reg = 0x80, .mask = BIT(1) | BIT(2) },
+};
+
+static const struct zte_reset_info zx297520v3_top_info = {
+ .resets = zx297520v3_top_resets,
+ .num = ARRAY_SIZE(zx297520v3_top_resets),
+};
+
+static const struct zte_reset_reg zx297520v3_matrix_resets[] = {
+ [ZX297520V3_CPU_RESET] = { .reg = 0x28, .mask = BIT(1) },
+ [ZX297520V3_EDCP_RESET] = { .reg = 0x68, .mask = BIT(0) },
+ [ZX297520V3_SD0_RESET] = { .reg = 0x58, .mask = BIT(1) },
+ [ZX297520V3_SD1_RESET] = { .reg = 0x58, .mask = BIT(0) },
+ [ZX297520V3_NAND_RESET] = { .reg = 0x58, .mask = BIT(4) },
+ [ZX297520V3_PDCFG_RESET] = { .reg = 0x94, .mask = BIT(20) },
+ [ZX297520V3_SSC_RESET] = { .reg = 0x94, .mask = BIT(24) },
+ [ZX297520V3_GMAC_RESET] = { .reg = 0x114, .mask = BIT(0) | BIT(1) },
+ [ZX297520V3_VOU_RESET] = { .reg = 0x16c, .mask = BIT(0) },
+};
+
+static const struct zte_reset_info zx297520v3_matrix_info = {
+ .resets = zx297520v3_matrix_resets,
+ .num = ARRAY_SIZE(zx297520v3_matrix_resets),
+};
+
+static const struct zte_reset_reg zx297520v3_lsp_resets[] = {
+ [ZX297520V3_TIMER_L1_RESET] = { .reg = 0x04, .mask = BIT(8) | BIT(9) },
+ [ZX297520V3_WDT_L2_RESET] = { .reg = 0x08, .mask = BIT(8) | BIT(9) },
+ [ZX297520V3_WDT_L3_RESET] = { .reg = 0x0c, .mask = BIT(8) | BIT(9) },
+ [ZX297520V3_PWM_RESET] = { .reg = 0x10, .mask = BIT(8) | BIT(9) },
+ [ZX297520V3_I2S0_RESET] = { .reg = 0x14, .mask = BIT(8) | BIT(9) },
+ /* 0x18: Not writeable */
+ [ZX297520V3_I2S1_RESET] = { .reg = 0x1c, .mask = BIT(8) | BIT(9) },
+ /* 0x20: Not writeable */
+ [ZX297520V3_QSPI_RESET] = { .reg = 0x24, .mask = BIT(8) | BIT(9) },
+ [ZX297520V3_UART1_RESET] = { .reg = 0x28, .mask = BIT(8) | BIT(9) },
+ [ZX297520V3_I2C1_RESET] = { .reg = 0x2c, .mask = BIT(8) | BIT(9) },
+ [ZX297520V3_SPI0_RESET] = { .reg = 0x30, .mask = BIT(8) | BIT(9) },
+ [ZX297520V3_TIMER_LB_RESET] = { .reg = 0x34, .mask = BIT(8) | BIT(9) },
+ [ZX297520V3_TIMER_LC_RESET] = { .reg = 0x38, .mask = BIT(8) | BIT(9) },
+ [ZX297520V3_UART2_RESET] = { .reg = 0x3c, .mask = BIT(8) | BIT(9) },
+ [ZX297520V3_WDT_LE_RESET] = { .reg = 0x40, .mask = BIT(8) | BIT(9) },
+ [ZX297520V3_TIMER_LF_RESET] = { .reg = 0x44, .mask = BIT(8) | BIT(9) },
+ [ZX297520V3_SPI1_RESET] = { .reg = 0x48, .mask = BIT(8) | BIT(9) },
+ [ZX297520V3_TIMER_L11_RESET] = { .reg = 0x4c, .mask = BIT(8) | BIT(9) },
+ [ZX297520V3_TDM_RESET] = { .reg = 0x50, .mask = BIT(8) | BIT(9) },
+};
+
+static const struct zte_reset_info zx297520v3_lsp_info = {
+ .resets = zx297520v3_lsp_resets,
+ .num = ARRAY_SIZE(zx297520v3_lsp_resets),
+};
+
+static int reset_zx297520v3_common_probe(struct device *dev,
+ struct device_node *of_node,
+ const struct zte_reset_info *drv_info)
+{
+ struct zte_reset *rst;
+
+ rst = devm_kzalloc(dev, sizeof(*rst), GFP_KERNEL);
+ if (!rst)
+ return -ENOMEM;
+
+ rst->resets = drv_info->resets;
+ rst->rcdev.owner = THIS_MODULE;
+ rst->rcdev.nr_resets = drv_info->num;
+ rst->rcdev.ops = &zx29_rst_ops;
+ rst->rcdev.of_node = of_node;
+ rst->rcdev.dev = dev;
+
+ rst->map = device_node_to_regmap(of_node);
+ if (IS_ERR(rst->map))
+ return dev_err_probe(dev, PTR_ERR(rst->map), "Cannot get parent syscon regmap\n");
+
+ return devm_reset_controller_register(dev, &rst->rcdev);
+
+}
+
+static int reset_zx297520v3_aux_probe(struct auxiliary_device *adev,
+ const struct auxiliary_device_id *id)
+{
+ return reset_zx297520v3_common_probe(&adev->dev, adev->dev.of_node,
+ (const struct zte_reset_info *)id->driver_data);
+}
+
+static int reset_zx297520v3_top_probe(struct platform_device *pdev)
+{
+ return reset_zx297520v3_common_probe(&pdev->dev, pdev->dev.parent->of_node,
+ &zx297520v3_top_info);
+}
+
+static struct platform_driver reset_zx297520v3_top = {
+ .probe = reset_zx297520v3_top_probe,
+ .driver = {
+ .name = "zx297520v3-toprst",
+ },
+};
+
+static int reset_zx297520v3_matrix_probe(struct platform_device *pdev)
+{
+ return reset_zx297520v3_common_probe(&pdev->dev, pdev->dev.parent->of_node,
+ &zx297520v3_matrix_info);
+}
+
+static struct platform_driver reset_zx297520v3_matrix = {
+ .probe = reset_zx297520v3_matrix_probe,
+ .driver = {
+ .name = "zx297520v3-matrixrst",
+ },
+};
+
+static const struct auxiliary_device_id reset_zx297520v3_ids[] = {
+ {
+ .name = "clk_zte.zx297520v3_lsprst",
+ .driver_data = (kernel_ulong_t)&zx297520v3_lsp_info,
+ },
+ { },
+};
+MODULE_DEVICE_TABLE(auxiliary, reset_zx297520v3_ids);
+
+static struct auxiliary_driver reset_zx297520v3_auxdrv = {
+ .name = "zx297520v3_lsp_reset",
+ .id_table = reset_zx297520v3_ids,
+ .probe = reset_zx297520v3_aux_probe,
+};
+
+static struct platform_driver * const reset_zx297520v3_mfddrv[] = {
+ &reset_zx297520v3_top,
+ &reset_zx297520v3_matrix,
+};
+
+static int __init reset_zx297520v3_init(void)
+{
+ int res;
+
+ res = auxiliary_driver_register(&reset_zx297520v3_auxdrv);
+ if (res)
+ return res;
+
+ res = platform_register_drivers(reset_zx297520v3_mfddrv,
+ ARRAY_SIZE(reset_zx297520v3_mfddrv));
+ if (res)
+ auxiliary_driver_unregister(&reset_zx297520v3_auxdrv);
+
+ return res;
+}
+
+static void __exit reset_zx297520v3_exit(void)
+{
+ platform_unregister_drivers(reset_zx297520v3_mfddrv,
+ ARRAY_SIZE(reset_zx297520v3_mfddrv));
+ auxiliary_driver_unregister(&reset_zx297520v3_auxdrv);
+}
+
+module_init(reset_zx297520v3_init);
+module_exit(reset_zx297520v3_exit);
+
+MODULE_AUTHOR("Stefan Dösinger <stefandoesinger@gmail.com>");
+MODULE_DESCRIPTION("ZTE zx297520v3 reset driver");
+MODULE_LICENSE("GPL");
--
2.53.0
^ permalink raw reply related
* Re: [PATCH v6 1/9] media: mc-entity: Store parsed V4L2 fwnode endpoint in media_pad
From: Sakari Ailus @ 2026-06-28 20:28 UTC (permalink / raw)
To: Frank Li, Laurent Pinchart, Hans Verkuil
Cc: Mauro Carvalho Chehab, Michael Riesch, Frank Li,
Martin Kepplinger-Novakovic, Rui Miguel Silva, Purism Kernel Team,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, linux-media, linux-kernel,
imx, Guoniu Zhou, devicetree, linux-arm-kernel
In-Reply-To: <20260624-imx8qxp_pcam-v6-1-4b3f45920d2f@nxp.com>
Hi Frank,
Thanks for the patch.
On Wed, Jun 24, 2026 at 04:37:48PM -0400, Frank.Li@oss.nxp.com wrote:
> From: Frank Li <Frank.Li@nxp.com>
>
> Each media pad is associated with a firmware node endpoint. Capture the
> parsed V4L2 fwnode endpoint information in struct media_pad so it can be
> reused by consumers.
>
> This avoids reparsing firmware node endpoint data every time the endpoint
> configuration is needed, reduces duplicate code, and provides a common
> place to store endpoint properties associated with a pad.
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> Assume 1 to 1 map between dt's endpoint to medie pad.
> Change in v6
> - new patch
> ---
> include/media/media-entity.h | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/include/media/media-entity.h b/include/media/media-entity.h
> index d9b72cd87d524..4a3785cd9f370 100644
> --- a/include/media/media-entity.h
> +++ b/include/media/media-entity.h
> @@ -20,6 +20,8 @@
> #include <linux/minmax.h>
> #include <linux/types.h>
>
> +#include <media/v4l2-fwnode.h>
We have dependencies from V4L2 to MC but not the other way around as MC is
(or was?) intended for wider use then just V4L2. I'm thus more than a bit
hesitant adding any references to V4L2 in MC.
I wonder what Hans and Laurent think.
> +
> /* Enums used internally at the media controller to represent graphs */
>
> /**
> @@ -230,6 +232,7 @@ enum media_pad_signal_type {
> * @flags: Pad flags, as defined in
> * :ref:`include/uapi/linux/media.h <media_header>`
> * (seek for ``MEDIA_PAD_FL_*``)
> + * @vep: associated fwnode endpoint information
> * @pipe: Pipeline this pad belongs to. Use media_entity_pipeline() to
> * access this field.
> */
> @@ -240,7 +243,7 @@ struct media_pad {
> u16 num_links;
> enum media_pad_signal_type sig_type;
> unsigned long flags;
> -
> + struct v4l2_fwnode_endpoint vep;
> /*
> * The fields below are private, and should only be accessed via
> * appropriate functions.
>
--
Regards,
Sakari Ailus
^ permalink raw reply
* [PATCH v2 0/4] arm64: dts: am62p5-var-som-symphony: align DTS with hardware revision
From: Stefano Radaelli @ 2026-06-28 20:56 UTC (permalink / raw)
To: linux-kernel, devicetree, linux-arm-kernel
Cc: pierluigi.p, matthias.p, Stefano Radaelli, Nishanth Menon,
Vignesh Raghavendra, Tero Kristo, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
This series updates the device tree description for the Variscite
VAR-SOM-AM62P and Symphony carrier board to better reflect the current
board configuration.
It aligns the Ethernet PHY description, updates the audio codec
configuration, and adds the touchscreen and TPM devices together with
their required board-level resources.
v1->v2:
- Remove unused eth property
- Remove wrong dmic property
- Fix commit message
Stefano Radaelli (4):
arm64: dts: ti: var-som-am62p: fix Ethernet PHY configuration
arm64: dts: ti: var-som-am62p: update audio codec configuration
arm64: dts: am62p5-var-som-symphony: add touchscreen support
arm64: dts: am62p5-var-som-symphony: add TPM support
.../dts/ti/k3-am62p5-var-som-symphony.dts | 43 +++++++++++++++++++
arch/arm64/boot/dts/ti/k3-am62p5-var-som.dtsi | 35 +++++++++++++--
2 files changed, 74 insertions(+), 4 deletions(-)
base-commit: 3d5670d672ae08b8c534b7beed6f57c8b44e7b43
--
2.47.3
^ permalink raw reply
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