* [PATCH 01/15] dt-bindings: clock: mediatek: reorder MT8186 compatibles
From: Louis-Alexis Eyraud @ 2026-07-01 13:11 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Brian Masney, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chun-Jie Chen, Philipp Zabel,
Edward-JW Yang, Richard Cochran
Cc: kernel, linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Louis-Alexis Eyraud
In-Reply-To: <20260701-mt8189-clocks-system-base-v1-0-2b048feea50a@collabora.com>
In order to prepare regrouping several Mediatek SoC clock controller
dt-bindings files into the MT8186 ones, reorder the MT8186 clock
controller compatibles so they are sorted alphanumerically.
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
.../bindings/clock/mediatek,mt8186-clock.yaml | 17 +++++++++--------
.../bindings/clock/mediatek,mt8186-sys-clock.yaml | 4 ++--
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml
index f4e58bfa504f..37e1d7487ab4 100644
--- a/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml
@@ -23,18 +23,19 @@ properties:
compatible:
items:
- enum:
- - mediatek,mt8186-imp_iic_wrap
- - mediatek,mt8186-mfgsys
- - mediatek,mt8186-wpesys
- - mediatek,mt8186-imgsys1
- - mediatek,mt8186-imgsys2
- - mediatek,mt8186-vdecsys
- - mediatek,mt8186-vencsys
- mediatek,mt8186-camsys
- mediatek,mt8186-camsys_rawa
- mediatek,mt8186-camsys_rawb
- - mediatek,mt8186-mdpsys
+ - mediatek,mt8186-imgsys1
+ - mediatek,mt8186-imgsys2
+ - mediatek,mt8186-imp_iic_wrap
- mediatek,mt8186-ipesys
+ - mediatek,mt8186-mdpsys
+ - mediatek,mt8186-mfgsys
+ - mediatek,mt8186-vdecsys
+ - mediatek,mt8186-vencsys
+ - mediatek,mt8186-wpesys
+
reg:
maxItems: 1
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml
index 1c446fbc5108..c857a40ca2f0 100644
--- a/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml
@@ -27,10 +27,10 @@ properties:
compatible:
items:
- enum:
+ - mediatek,mt8186-apmixedsys
+ - mediatek,mt8186-infracfg_ao
- mediatek,mt8186-mcusys
- mediatek,mt8186-topckgen
- - mediatek,mt8186-infracfg_ao
- - mediatek,mt8186-apmixedsys
- const: syscon
reg:
--
2.54.0
^ permalink raw reply related
* [PATCH 02/15] dt-bindings: clock: mediatek: regroup MT8188 dt-bindings into MT8186
From: Louis-Alexis Eyraud @ 2026-07-01 13:11 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Brian Masney, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chun-Jie Chen, Philipp Zabel,
Edward-JW Yang, Richard Cochran
Cc: kernel, linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Louis-Alexis Eyraud
In-Reply-To: <20260701-mt8189-clocks-system-base-v1-0-2b048feea50a@collabora.com>
Regroup the MT8188 clock and system clock dt-bindings into MT8186 ones
to ease maintainability and have common files for several currently
supported SoC or new future ones, that have the same kind of clock
controller design.
Note:
The `#clock-cells` property is a required property for all compatibles
declared in MT8188 clock and system clock dt-bindings but not in MT8186
ones.
To avoid ABI breakage, conditional blocks to check this requirement
for MT8188 compatibles are added, rather than enforcing it for MT8186
compatibles.
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
.../bindings/clock/mediatek,mt8186-clock.yaml | 82 ++++++++++++++++++-
.../bindings/clock/mediatek,mt8186-sys-clock.yaml | 20 ++++-
.../bindings/clock/mediatek,mt8188-clock.yaml | 93 ----------------------
.../bindings/clock/mediatek,mt8188-sys-clock.yaml | 58 --------------
4 files changed, 100 insertions(+), 153 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml
index 37e1d7487ab4..28e05b5fb23b 100644
--- a/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/clock/mediatek,mt8186-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: MediaTek Functional Clock Controller for MT8186
+title: MediaTek Functional Clock Controller for Mediatek SoCs
maintainers:
- Chun-Jie Chen <chun-jie.chen@mediatek.com>
@@ -35,6 +35,30 @@ properties:
- mediatek,mt8186-vdecsys
- mediatek,mt8186-vencsys
- mediatek,mt8186-wpesys
+ - mediatek,mt8188-adsp-audio26m
+ - mediatek,mt8188-camsys
+ - mediatek,mt8188-camsys-rawa
+ - mediatek,mt8188-camsys-rawb
+ - mediatek,mt8188-camsys-yuva
+ - mediatek,mt8188-camsys-yuvb
+ - mediatek,mt8188-ccusys
+ - mediatek,mt8188-imgsys
+ - mediatek,mt8188-imgsys-wpe1
+ - mediatek,mt8188-imgsys-wpe2
+ - mediatek,mt8188-imgsys-wpe3
+ - mediatek,mt8188-imgsys1-dip-nr
+ - mediatek,mt8188-imgsys1-dip-top
+ - mediatek,mt8188-imp-iic-wrap-c
+ - mediatek,mt8188-imp-iic-wrap-en
+ - mediatek,mt8188-imp-iic-wrap-w
+ - mediatek,mt8188-ipesys
+ - mediatek,mt8188-mfgcfg
+ - mediatek,mt8188-vdecsys
+ - mediatek,mt8188-vdecsys-soc
+ - mediatek,mt8188-vencsys
+ - mediatek,mt8188-wpesys
+ - mediatek,mt8188-wpesys-vpp0
+
reg:
maxItems: 1
@@ -42,10 +66,66 @@ properties:
'#clock-cells':
const: 1
+ '#reset-cells':
+ const: 1
+
required:
- compatible
- reg
+allOf:
+ - if:
+ properties:
+ compatible:
+ enum:
+ - mediatek,mt8188-adsp-audio26m
+ - mediatek,mt8188-camsys
+ - mediatek,mt8188-camsys-rawa
+ - mediatek,mt8188-camsys-rawb
+ - mediatek,mt8188-camsys-yuva
+ - mediatek,mt8188-camsys-yuvb
+ - mediatek,mt8188-ccusys
+ - mediatek,mt8188-imgsys
+ - mediatek,mt8188-imgsys-wpe1
+ - mediatek,mt8188-imgsys-wpe2
+ - mediatek,mt8188-imgsys-wpe3
+ - mediatek,mt8188-imgsys1-dip-nr
+ - mediatek,mt8188-imgsys1-dip-top
+ - mediatek,mt8188-imp-iic-wrap-c
+ - mediatek,mt8188-imp-iic-wrap-en
+ - mediatek,mt8188-imp-iic-wrap-w
+ - mediatek,mt8188-ipesys
+ - mediatek,mt8188-mfgcfg
+ - mediatek,mt8188-vdecsys
+ - mediatek,mt8188-vdecsys-soc
+ - mediatek,mt8188-vencsys
+ - mediatek,mt8188-wpesys
+ - mediatek,mt8188-wpesys-vpp0
+ then:
+ required:
+ - '#clock-cells'
+
+ - if:
+ properties:
+ compatible:
+ enum:
+ - mediatek,mt8188-camsys-rawa
+ - mediatek,mt8188-camsys-rawb
+ - mediatek,mt8188-camsys-yuva
+ - mediatek,mt8188-camsys-yuvb
+ - mediatek,mt8188-imgsys-wpe1
+ - mediatek,mt8188-imgsys-wpe2
+ - mediatek,mt8188-imgsys-wpe3
+ - mediatek,mt8188-imgsys1-dip-nr
+ - mediatek,mt8188-imgsys1-dip-top
+ - mediatek,mt8188-ipesys
+ then:
+ required:
+ - '#reset-cells'
+ else:
+ properties:
+ reset-cells: false
+
additionalProperties: false
examples:
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml
index c857a40ca2f0..edf9562ca8b9 100644
--- a/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/clock/mediatek,mt8186-sys-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: MediaTek System Clock Controller for MT8186
+title: MediaTek System Clock Controller for Mediatek SoCs
maintainers:
- Chun-Jie Chen <chun-jie.chen@mediatek.com>
@@ -31,6 +31,10 @@ properties:
- mediatek,mt8186-infracfg_ao
- mediatek,mt8186-mcusys
- mediatek,mt8186-topckgen
+ - mediatek,mt8188-apmixedsys
+ - mediatek,mt8188-infracfg-ao
+ - mediatek,mt8188-pericfg-ao
+ - mediatek,mt8188-topckgen
- const: syscon
reg:
@@ -46,6 +50,20 @@ required:
- compatible
- reg
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - mediatek,mt8188-apmixedsys
+ - mediatek,mt8188-infracfg-ao
+ - mediatek,mt8188-pericfg-ao
+ - mediatek,mt8188-topckgen
+ then:
+ required:
+ - '#clock-cells'
+
additionalProperties: false
examples:
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml
deleted file mode 100644
index 5403242545ab..000000000000
--- a/Documentation/devicetree/bindings/clock/mediatek,mt8188-clock.yaml
+++ /dev/null
@@ -1,93 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/clock/mediatek,mt8188-clock.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: MediaTek Functional Clock Controller for MT8188
-
-maintainers:
- - Garmin Chang <garmin.chang@mediatek.com>
-
-description: |
- The clock architecture in MediaTek like below
- PLLs -->
- dividers -->
- muxes
- -->
- clock gate
-
- The devices provide clock gate control in different IP blocks.
-
-properties:
- compatible:
- enum:
- - mediatek,mt8188-adsp-audio26m
- - mediatek,mt8188-camsys
- - mediatek,mt8188-camsys-rawa
- - mediatek,mt8188-camsys-rawb
- - mediatek,mt8188-camsys-yuva
- - mediatek,mt8188-camsys-yuvb
- - mediatek,mt8188-ccusys
- - mediatek,mt8188-imgsys
- - mediatek,mt8188-imgsys-wpe1
- - mediatek,mt8188-imgsys-wpe2
- - mediatek,mt8188-imgsys-wpe3
- - mediatek,mt8188-imgsys1-dip-nr
- - mediatek,mt8188-imgsys1-dip-top
- - mediatek,mt8188-imp-iic-wrap-c
- - mediatek,mt8188-imp-iic-wrap-en
- - mediatek,mt8188-imp-iic-wrap-w
- - mediatek,mt8188-ipesys
- - mediatek,mt8188-mfgcfg
- - mediatek,mt8188-vdecsys
- - mediatek,mt8188-vdecsys-soc
- - mediatek,mt8188-vencsys
- - mediatek,mt8188-wpesys
- - mediatek,mt8188-wpesys-vpp0
-
- reg:
- maxItems: 1
-
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
-required:
- - compatible
- - reg
- - '#clock-cells'
-
-allOf:
- - if:
- properties:
- compatible:
- contains:
- enum:
- - mediatek,mt8188-camsys-rawa
- - mediatek,mt8188-camsys-rawb
- - mediatek,mt8188-camsys-yuva
- - mediatek,mt8188-camsys-yuvb
- - mediatek,mt8188-imgsys-wpe1
- - mediatek,mt8188-imgsys-wpe2
- - mediatek,mt8188-imgsys-wpe3
- - mediatek,mt8188-imgsys1-dip-nr
- - mediatek,mt8188-imgsys1-dip-top
- - mediatek,mt8188-ipesys
-
- then:
- required:
- - '#reset-cells'
-
-additionalProperties: false
-
-examples:
- - |
- clock-controller@11283000 {
- compatible = "mediatek,mt8188-imp-iic-wrap-c";
- reg = <0x11283000 0x1000>;
- #clock-cells = <1>;
- };
-
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8188-sys-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8188-sys-clock.yaml
deleted file mode 100644
index db13d51a4903..000000000000
--- a/Documentation/devicetree/bindings/clock/mediatek,mt8188-sys-clock.yaml
+++ /dev/null
@@ -1,58 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/clock/mediatek,mt8188-sys-clock.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: MediaTek System Clock Controller for MT8188
-
-maintainers:
- - Garmin Chang <garmin.chang@mediatek.com>
-
-description: |
- The clock architecture in MediaTek like below
- PLLs -->
- dividers -->
- muxes
- -->
- clock gate
-
- The apmixedsys provides most of PLLs which generated from SoC 26m.
- The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
- The infracfg_ao provides clock gate in peripheral and infrastructure IP blocks.
- The mcusys provides mux control to select the clock source in AP MCU.
- The device nodes also provide the system control capacity for configuration.
-
-properties:
- compatible:
- items:
- - enum:
- - mediatek,mt8188-apmixedsys
- - mediatek,mt8188-infracfg-ao
- - mediatek,mt8188-pericfg-ao
- - mediatek,mt8188-topckgen
- - const: syscon
-
- reg:
- maxItems: 1
-
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
-required:
- - compatible
- - reg
- - '#clock-cells'
-
-additionalProperties: false
-
-examples:
- - |
- clock-controller@10000000 {
- compatible = "mediatek,mt8188-topckgen", "syscon";
- reg = <0x10000000 0x1000>;
- #clock-cells = <1>;
- };
--
2.54.0
^ permalink raw reply related
* [PATCH 03/15] dt-bindings: clock: mediatek: regroup MT8192 dt-bindings into MT8186
From: Louis-Alexis Eyraud @ 2026-07-01 13:11 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Brian Masney, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chun-Jie Chen, Philipp Zabel,
Edward-JW Yang, Richard Cochran
Cc: kernel, linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Louis-Alexis Eyraud
In-Reply-To: <20260701-mt8189-clocks-system-base-v1-0-2b048feea50a@collabora.com>
Regroup the MT8192 clock and system clock dt-bindings into MT8186 ones
to ease maintainability and have common files for several currently
supported SoC or new future ones, that have the same kind of clock
controller design.
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
.../bindings/clock/mediatek,mt8186-clock.yaml | 21 ++-
.../bindings/clock/mediatek,mt8186-sys-clock.yaml | 4 +
.../bindings/clock/mediatek,mt8192-clock.yaml | 191 ---------------------
.../bindings/clock/mediatek,mt8192-sys-clock.yaml | 68 --------
4 files changed, 24 insertions(+), 260 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml
index 28e05b5fb23b..3b543c810f18 100644
--- a/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml
@@ -58,7 +58,26 @@ properties:
- mediatek,mt8188-vencsys
- mediatek,mt8188-wpesys
- mediatek,mt8188-wpesys-vpp0
-
+ - mediatek,mt8192-camsys
+ - mediatek,mt8192-camsys_rawa
+ - mediatek,mt8192-camsys_rawb
+ - mediatek,mt8192-camsys_rawc
+ - mediatek,mt8192-imgsys
+ - mediatek,mt8192-imgsys2
+ - mediatek,mt8192-imp_iic_wrap_c
+ - mediatek,mt8192-imp_iic_wrap_e
+ - mediatek,mt8192-imp_iic_wrap_s
+ - mediatek,mt8192-imp_iic_wrap_ws
+ - mediatek,mt8192-imp_iic_wrap_w
+ - mediatek,mt8192-imp_iic_wrap_n
+ - mediatek,mt8192-ipesys
+ - mediatek,mt8192-mdpsys
+ - mediatek,mt8192-mfgcfg
+ - mediatek,mt8192-msdc_top
+ - mediatek,mt8192-scp_adsp
+ - mediatek,mt8192-vdecsys_soc
+ - mediatek,mt8192-vdecsys
+ - mediatek,mt8192-vencsys
reg:
maxItems: 1
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml
index edf9562ca8b9..4500842b20de 100644
--- a/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml
@@ -35,6 +35,10 @@ properties:
- mediatek,mt8188-infracfg-ao
- mediatek,mt8188-pericfg-ao
- mediatek,mt8188-topckgen
+ - mediatek,mt8192-apmixedsys
+ - mediatek,mt8192-infracfg
+ - mediatek,mt8192-pericfg
+ - mediatek,mt8192-topckgen
- const: syscon
reg:
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8192-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8192-clock.yaml
deleted file mode 100644
index b8d690e28bdc..000000000000
--- a/Documentation/devicetree/bindings/clock/mediatek,mt8192-clock.yaml
+++ /dev/null
@@ -1,191 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/clock/mediatek,mt8192-clock.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: MediaTek Functional Clock Controller for MT8192
-
-maintainers:
- - Chun-Jie Chen <chun-jie.chen@mediatek.com>
-
-description:
- The Mediatek functional clock controller provides various clocks on MT8192.
-
-properties:
- compatible:
- items:
- - enum:
- - mediatek,mt8192-scp_adsp
- - mediatek,mt8192-imp_iic_wrap_c
- - mediatek,mt8192-imp_iic_wrap_e
- - mediatek,mt8192-imp_iic_wrap_s
- - mediatek,mt8192-imp_iic_wrap_ws
- - mediatek,mt8192-imp_iic_wrap_w
- - mediatek,mt8192-imp_iic_wrap_n
- - mediatek,mt8192-msdc_top
- - mediatek,mt8192-mfgcfg
- - mediatek,mt8192-imgsys
- - mediatek,mt8192-imgsys2
- - mediatek,mt8192-vdecsys_soc
- - mediatek,mt8192-vdecsys
- - mediatek,mt8192-vencsys
- - mediatek,mt8192-camsys
- - mediatek,mt8192-camsys_rawa
- - mediatek,mt8192-camsys_rawb
- - mediatek,mt8192-camsys_rawc
- - mediatek,mt8192-ipesys
- - mediatek,mt8192-mdpsys
-
- reg:
- maxItems: 1
-
- '#clock-cells':
- const: 1
-
-required:
- - compatible
- - reg
-
-additionalProperties: false
-
-examples:
- - |
- scp_adsp: clock-controller@10720000 {
- compatible = "mediatek,mt8192-scp_adsp";
- reg = <0x10720000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- imp_iic_wrap_c: clock-controller@11007000 {
- compatible = "mediatek,mt8192-imp_iic_wrap_c";
- reg = <0x11007000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- imp_iic_wrap_e: clock-controller@11cb1000 {
- compatible = "mediatek,mt8192-imp_iic_wrap_e";
- reg = <0x11cb1000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- imp_iic_wrap_s: clock-controller@11d03000 {
- compatible = "mediatek,mt8192-imp_iic_wrap_s";
- reg = <0x11d03000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- imp_iic_wrap_ws: clock-controller@11d23000 {
- compatible = "mediatek,mt8192-imp_iic_wrap_ws";
- reg = <0x11d23000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- imp_iic_wrap_w: clock-controller@11e01000 {
- compatible = "mediatek,mt8192-imp_iic_wrap_w";
- reg = <0x11e01000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- imp_iic_wrap_n: clock-controller@11f02000 {
- compatible = "mediatek,mt8192-imp_iic_wrap_n";
- reg = <0x11f02000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- msdc_top: clock-controller@11f10000 {
- compatible = "mediatek,mt8192-msdc_top";
- reg = <0x11f10000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- mfgcfg: clock-controller@13fbf000 {
- compatible = "mediatek,mt8192-mfgcfg";
- reg = <0x13fbf000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- imgsys: clock-controller@15020000 {
- compatible = "mediatek,mt8192-imgsys";
- reg = <0x15020000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- imgsys2: clock-controller@15820000 {
- compatible = "mediatek,mt8192-imgsys2";
- reg = <0x15820000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- vdecsys_soc: clock-controller@1600f000 {
- compatible = "mediatek,mt8192-vdecsys_soc";
- reg = <0x1600f000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- vdecsys: clock-controller@1602f000 {
- compatible = "mediatek,mt8192-vdecsys";
- reg = <0x1602f000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- vencsys: clock-controller@17000000 {
- compatible = "mediatek,mt8192-vencsys";
- reg = <0x17000000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- camsys: clock-controller@1a000000 {
- compatible = "mediatek,mt8192-camsys";
- reg = <0x1a000000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- camsys_rawa: clock-controller@1a04f000 {
- compatible = "mediatek,mt8192-camsys_rawa";
- reg = <0x1a04f000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- camsys_rawb: clock-controller@1a06f000 {
- compatible = "mediatek,mt8192-camsys_rawb";
- reg = <0x1a06f000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- camsys_rawc: clock-controller@1a08f000 {
- compatible = "mediatek,mt8192-camsys_rawc";
- reg = <0x1a08f000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- ipesys: clock-controller@1b000000 {
- compatible = "mediatek,mt8192-ipesys";
- reg = <0x1b000000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- mdpsys: clock-controller@1f000000 {
- compatible = "mediatek,mt8192-mdpsys";
- reg = <0x1f000000 0x1000>;
- #clock-cells = <1>;
- };
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8192-sys-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8192-sys-clock.yaml
deleted file mode 100644
index bf8c9aacdf1e..000000000000
--- a/Documentation/devicetree/bindings/clock/mediatek,mt8192-sys-clock.yaml
+++ /dev/null
@@ -1,68 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/clock/mediatek,mt8192-sys-clock.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: MediaTek System Clock Controller for MT8192
-
-maintainers:
- - Chun-Jie Chen <chun-jie.chen@mediatek.com>
-
-description:
- The Mediatek system clock controller provides various clocks and system configuration
- like reset and bus protection on MT8192.
-
-properties:
- compatible:
- items:
- - enum:
- - mediatek,mt8192-topckgen
- - mediatek,mt8192-infracfg
- - mediatek,mt8192-pericfg
- - mediatek,mt8192-apmixedsys
- - const: syscon
-
- reg:
- maxItems: 1
-
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
-required:
- - compatible
- - reg
-
-additionalProperties: false
-
-examples:
- - |
- topckgen: syscon@10000000 {
- compatible = "mediatek,mt8192-topckgen", "syscon";
- reg = <0x10000000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- infracfg: syscon@10001000 {
- compatible = "mediatek,mt8192-infracfg", "syscon";
- reg = <0x10001000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- pericfg: syscon@10003000 {
- compatible = "mediatek,mt8192-pericfg", "syscon";
- reg = <0x10003000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- apmixedsys: syscon@1000c000 {
- compatible = "mediatek,mt8192-apmixedsys", "syscon";
- reg = <0x1000c000 0x1000>;
- #clock-cells = <1>;
- };
--
2.54.0
^ permalink raw reply related
* [PATCH 04/15] dt-bindings: clock: mediatek: regroup MT8195 dt-bindings into MT8186
From: Louis-Alexis Eyraud @ 2026-07-01 13:11 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Brian Masney, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chun-Jie Chen, Philipp Zabel,
Edward-JW Yang, Richard Cochran
Cc: kernel, linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Louis-Alexis Eyraud
In-Reply-To: <20260701-mt8189-clocks-system-base-v1-0-2b048feea50a@collabora.com>
Regroup the MT8195 clock and system clock dt-bindings into MT8186 ones
to ease maintainability and have common files for several currently
supported SoC or new future ones, that have the same kind of clock
controller design.
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
.../bindings/clock/mediatek,mt8186-clock.yaml | 25 +++
.../bindings/clock/mediatek,mt8186-sys-clock.yaml | 4 +
.../bindings/clock/mediatek,mt8195-clock.yaml | 238 ---------------------
.../bindings/clock/mediatek,mt8195-sys-clock.yaml | 76 -------
4 files changed, 29 insertions(+), 314 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml
index 3b543c810f18..84e602c7d326 100644
--- a/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml
@@ -78,6 +78,31 @@ properties:
- mediatek,mt8192-vdecsys_soc
- mediatek,mt8192-vdecsys
- mediatek,mt8192-vencsys
+ - mediatek,mt8195-apusys_pll
+ - mediatek,mt8195-camsys
+ - mediatek,mt8195-camsys_rawa
+ - mediatek,mt8195-camsys_yuva
+ - mediatek,mt8195-camsys_rawb
+ - mediatek,mt8195-camsys_yuvb
+ - mediatek,mt8195-camsys_mraw
+ - mediatek,mt8195-ccusys
+ - mediatek,mt8195-imgsys
+ - mediatek,mt8195-imgsys1_dip_top
+ - mediatek,mt8195-imgsys1_dip_nr
+ - mediatek,mt8195-imgsys1_wpe
+ - mediatek,mt8195-imp_iic_wrap_s
+ - mediatek,mt8195-imp_iic_wrap_w
+ - mediatek,mt8195-ipesys
+ - mediatek,mt8195-mfgcfg
+ - mediatek,mt8195-scp_adsp
+ - mediatek,mt8195-vdecsys_soc
+ - mediatek,mt8195-vdecsys
+ - mediatek,mt8195-vdecsys_core1
+ - mediatek,mt8195-vencsys
+ - mediatek,mt8195-vencsys_core1
+ - mediatek,mt8195-wpesys
+ - mediatek,mt8195-wpesys_vpp0
+ - mediatek,mt8195-wpesys_vpp1
reg:
maxItems: 1
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml
index 4500842b20de..c4288b91e6b6 100644
--- a/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml
@@ -39,6 +39,10 @@ properties:
- mediatek,mt8192-infracfg
- mediatek,mt8192-pericfg
- mediatek,mt8192-topckgen
+ - mediatek,mt8195-apmixedsys
+ - mediatek,mt8195-infracfg_ao
+ - mediatek,mt8195-pericfg_ao
+ - mediatek,mt8195-topckgen
- const: syscon
reg:
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8195-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8195-clock.yaml
deleted file mode 100644
index fcc963aff087..000000000000
--- a/Documentation/devicetree/bindings/clock/mediatek,mt8195-clock.yaml
+++ /dev/null
@@ -1,238 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/clock/mediatek,mt8195-clock.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: MediaTek Functional Clock Controller for MT8195
-
-maintainers:
- - Chun-Jie Chen <chun-jie.chen@mediatek.com>
-
-description:
- The clock architecture in Mediatek like below
- PLLs -->
- dividers -->
- muxes
- -->
- clock gate
-
- The devices except apusys_pll provide clock gate control in different IP blocks.
- The apusys_pll provides Plls which generated from SoC 26m for AI Processing Unit.
-
-properties:
- compatible:
- items:
- - enum:
- - mediatek,mt8195-scp_adsp
- - mediatek,mt8195-imp_iic_wrap_s
- - mediatek,mt8195-imp_iic_wrap_w
- - mediatek,mt8195-mfgcfg
- - mediatek,mt8195-wpesys
- - mediatek,mt8195-wpesys_vpp0
- - mediatek,mt8195-wpesys_vpp1
- - mediatek,mt8195-imgsys
- - mediatek,mt8195-imgsys1_dip_top
- - mediatek,mt8195-imgsys1_dip_nr
- - mediatek,mt8195-imgsys1_wpe
- - mediatek,mt8195-ipesys
- - mediatek,mt8195-camsys
- - mediatek,mt8195-camsys_rawa
- - mediatek,mt8195-camsys_yuva
- - mediatek,mt8195-camsys_rawb
- - mediatek,mt8195-camsys_yuvb
- - mediatek,mt8195-camsys_mraw
- - mediatek,mt8195-ccusys
- - mediatek,mt8195-vdecsys_soc
- - mediatek,mt8195-vdecsys
- - mediatek,mt8195-vdecsys_core1
- - mediatek,mt8195-vencsys
- - mediatek,mt8195-vencsys_core1
- - mediatek,mt8195-apusys_pll
- reg:
- maxItems: 1
-
- '#clock-cells':
- const: 1
-
-required:
- - compatible
- - reg
-
-additionalProperties: false
-
-examples:
- - |
- scp_adsp: clock-controller@10720000 {
- compatible = "mediatek,mt8195-scp_adsp";
- reg = <0x10720000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- imp_iic_wrap_s: clock-controller@11d03000 {
- compatible = "mediatek,mt8195-imp_iic_wrap_s";
- reg = <0x11d03000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- imp_iic_wrap_w: clock-controller@11e05000 {
- compatible = "mediatek,mt8195-imp_iic_wrap_w";
- reg = <0x11e05000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- mfgcfg: clock-controller@13fbf000 {
- compatible = "mediatek,mt8195-mfgcfg";
- reg = <0x13fbf000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- wpesys: clock-controller@14e00000 {
- compatible = "mediatek,mt8195-wpesys";
- reg = <0x14e00000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- wpesys_vpp0: clock-controller@14e02000 {
- compatible = "mediatek,mt8195-wpesys_vpp0";
- reg = <0x14e02000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- wpesys_vpp1: clock-controller@14e03000 {
- compatible = "mediatek,mt8195-wpesys_vpp1";
- reg = <0x14e03000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- imgsys: clock-controller@15000000 {
- compatible = "mediatek,mt8195-imgsys";
- reg = <0x15000000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- imgsys1_dip_top: clock-controller@15110000 {
- compatible = "mediatek,mt8195-imgsys1_dip_top";
- reg = <0x15110000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- imgsys1_dip_nr: clock-controller@15130000 {
- compatible = "mediatek,mt8195-imgsys1_dip_nr";
- reg = <0x15130000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- imgsys1_wpe: clock-controller@15220000 {
- compatible = "mediatek,mt8195-imgsys1_wpe";
- reg = <0x15220000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- ipesys: clock-controller@15330000 {
- compatible = "mediatek,mt8195-ipesys";
- reg = <0x15330000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- camsys: clock-controller@16000000 {
- compatible = "mediatek,mt8195-camsys";
- reg = <0x16000000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- camsys_rawa: clock-controller@1604f000 {
- compatible = "mediatek,mt8195-camsys_rawa";
- reg = <0x1604f000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- camsys_yuva: clock-controller@1606f000 {
- compatible = "mediatek,mt8195-camsys_yuva";
- reg = <0x1606f000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- camsys_rawb: clock-controller@1608f000 {
- compatible = "mediatek,mt8195-camsys_rawb";
- reg = <0x1608f000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- camsys_yuvb: clock-controller@160af000 {
- compatible = "mediatek,mt8195-camsys_yuvb";
- reg = <0x160af000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- camsys_mraw: clock-controller@16140000 {
- compatible = "mediatek,mt8195-camsys_mraw";
- reg = <0x16140000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- ccusys: clock-controller@17200000 {
- compatible = "mediatek,mt8195-ccusys";
- reg = <0x17200000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- vdecsys_soc: clock-controller@1800f000 {
- compatible = "mediatek,mt8195-vdecsys_soc";
- reg = <0x1800f000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- vdecsys: clock-controller@1802f000 {
- compatible = "mediatek,mt8195-vdecsys";
- reg = <0x1802f000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- vdecsys_core1: clock-controller@1803f000 {
- compatible = "mediatek,mt8195-vdecsys_core1";
- reg = <0x1803f000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- vencsys: clock-controller@1a000000 {
- compatible = "mediatek,mt8195-vencsys";
- reg = <0x1a000000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- vencsys_core1: clock-controller@1b000000 {
- compatible = "mediatek,mt8195-vencsys_core1";
- reg = <0x1b000000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- apusys_pll: clock-controller@190f3000 {
- compatible = "mediatek,mt8195-apusys_pll";
- reg = <0x190f3000 0x1000>;
- #clock-cells = <1>;
- };
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8195-sys-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8195-sys-clock.yaml
deleted file mode 100644
index 69f096eb168d..000000000000
--- a/Documentation/devicetree/bindings/clock/mediatek,mt8195-sys-clock.yaml
+++ /dev/null
@@ -1,76 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/clock/mediatek,mt8195-sys-clock.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: MediaTek System Clock Controller for MT8195
-
-maintainers:
- - Chun-Jie Chen <chun-jie.chen@mediatek.com>
-
-description:
- The clock architecture in Mediatek like below
- PLLs -->
- dividers -->
- muxes
- -->
- clock gate
-
- The apmixedsys provides most of PLLs which generated from SoC 26m.
- The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
- The infracfg_ao and pericfg_ao provides clock gate in peripheral and infrastructure IP blocks.
-
-properties:
- compatible:
- items:
- - enum:
- - mediatek,mt8195-topckgen
- - mediatek,mt8195-infracfg_ao
- - mediatek,mt8195-apmixedsys
- - mediatek,mt8195-pericfg_ao
- - const: syscon
-
- reg:
- maxItems: 1
-
- '#clock-cells':
- const: 1
-
- '#reset-cells':
- const: 1
-
-required:
- - compatible
- - reg
-
-additionalProperties: false
-
-examples:
- - |
- topckgen: syscon@10000000 {
- compatible = "mediatek,mt8195-topckgen", "syscon";
- reg = <0x10000000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- infracfg_ao: syscon@10001000 {
- compatible = "mediatek,mt8195-infracfg_ao", "syscon";
- reg = <0x10001000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- apmixedsys: syscon@1000c000 {
- compatible = "mediatek,mt8195-apmixedsys", "syscon";
- reg = <0x1000c000 0x1000>;
- #clock-cells = <1>;
- };
-
- - |
- pericfg_ao: syscon@11003000 {
- compatible = "mediatek,mt8195-pericfg_ao", "syscon";
- reg = <0x11003000 0x1000>;
- #clock-cells = <1>;
- };
--
2.54.0
^ permalink raw reply related
* [PATCH 05/15] dt-bindings: clock: mediatek: Add MT8189 clocks
From: Louis-Alexis Eyraud @ 2026-07-01 13:11 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Brian Masney, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chun-Jie Chen, Philipp Zabel,
Edward-JW Yang, Richard Cochran
Cc: kernel, linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Irving-CH Lin, Louis-Alexis Eyraud
In-Reply-To: <20260701-mt8189-clocks-system-base-v1-0-2b048feea50a@collabora.com>
Add dt schema and IDs for the clocks of MediaTek MT8189 SoC.
The MT8189 clock IP provide clock control for main system
(apmixedsys, topcksys and vlpcksys) and subsys (eg. peri, scp,
ufs...).
Also, add compatible for frequency hopping and spread spectrum clock
functionality and reset controller header file for MT8189 UFS reset
controller support.
Co-developed-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
Signed-off-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
.../bindings/clock/mediatek,mt8186-clock.yaml | 28 ++
.../bindings/clock/mediatek,mt8186-fhctl.yaml | 1 +
.../bindings/clock/mediatek,mt8186-sys-clock.yaml | 10 +
include/dt-bindings/clock/mediatek,mt8189-clk.h | 433 +++++++++++++++++++++
include/dt-bindings/reset/mediatek,mt8189-resets.h | 17 +
5 files changed, 489 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml
index 84e602c7d326..e30ed16f321d 100644
--- a/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-clock.yaml
@@ -58,6 +58,19 @@ properties:
- mediatek,mt8188-vencsys
- mediatek,mt8188-wpesys
- mediatek,mt8188-wpesys-vpp0
+ - mediatek,mt8189-dbg-ao
+ - mediatek,mt8189-dem
+ - mediatek,mt8189-dvfsrc-top
+ - mediatek,mt8189-iic-wrap-e
+ - mediatek,mt8189-iic-wrap-en
+ - mediatek,mt8189-iic-wrap-s
+ - mediatek,mt8189-iic-wrap-ws
+ - mediatek,mt8189-scp-clk
+ - mediatek,mt8189-scp-i2c-clk
+ - mediatek,mt8189-ufscfg-ao
+ - mediatek,mt8189-ufscfg-pdn
+ - mediatek,mt8189-vlpcfg
+ - mediatek,mt8189-vlpcfg-ao
- mediatek,mt8192-camsys
- mediatek,mt8192-camsys_rawa
- mediatek,mt8192-camsys_rawb
@@ -145,6 +158,19 @@ allOf:
- mediatek,mt8188-vencsys
- mediatek,mt8188-wpesys
- mediatek,mt8188-wpesys-vpp0
+ - mediatek,mt8189-dbg-ao
+ - mediatek,mt8189-dem
+ - mediatek,mt8189-dvfsrc-top
+ - mediatek,mt8189-iic-wrap-e
+ - mediatek,mt8189-iic-wrap-en
+ - mediatek,mt8189-iic-wrap-s
+ - mediatek,mt8189-iic-wrap-ws
+ - mediatek,mt8189-scp-clk
+ - mediatek,mt8189-scp-i2c-clk
+ - mediatek,mt8189-ufscfg-ao
+ - mediatek,mt8189-ufscfg-pdn
+ - mediatek,mt8189-vlpcfg
+ - mediatek,mt8189-vlpcfg-ao
then:
required:
- '#clock-cells'
@@ -163,6 +189,8 @@ allOf:
- mediatek,mt8188-imgsys1-dip-nr
- mediatek,mt8188-imgsys1-dip-top
- mediatek,mt8188-ipesys
+ - mediatek,mt8189-ufscfg-ao
+ - mediatek,mt8189-ufscfg-pdn
then:
required:
- '#reset-cells'
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-fhctl.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-fhctl.yaml
index d00327d12e1e..824e3b2bd6c0 100644
--- a/Documentation/devicetree/bindings/clock/mediatek,mt8186-fhctl.yaml
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-fhctl.yaml
@@ -20,6 +20,7 @@ properties:
- mediatek,mt6795-fhctl
- mediatek,mt8173-fhctl
- mediatek,mt8186-fhctl
+ - mediatek,mt8189-fhctl
- mediatek,mt8192-fhctl
- mediatek,mt8195-fhctl
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml
index c4288b91e6b6..35094ed68548 100644
--- a/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt8186-sys-clock.yaml
@@ -35,6 +35,11 @@ properties:
- mediatek,mt8188-infracfg-ao
- mediatek,mt8188-pericfg-ao
- mediatek,mt8188-topckgen
+ - mediatek,mt8189-apmixedsys
+ - mediatek,mt8189-infra-ao
+ - mediatek,mt8189-peri-ao
+ - mediatek,mt8189-topckgen
+ - mediatek,mt8189-vlpckgen
- mediatek,mt8192-apmixedsys
- mediatek,mt8192-infracfg
- mediatek,mt8192-pericfg
@@ -68,6 +73,11 @@ allOf:
- mediatek,mt8188-infracfg-ao
- mediatek,mt8188-pericfg-ao
- mediatek,mt8188-topckgen
+ - mediatek,mt8189-apmixedsys
+ - mediatek,mt8189-infra-ao
+ - mediatek,mt8189-peri-ao
+ - mediatek,mt8189-topckgen
+ - mediatek,mt8189-vlpckgen
then:
required:
- '#clock-cells'
diff --git a/include/dt-bindings/clock/mediatek,mt8189-clk.h b/include/dt-bindings/clock/mediatek,mt8189-clk.h
new file mode 100644
index 000000000000..ca433f969698
--- /dev/null
+++ b/include/dt-bindings/clock/mediatek,mt8189-clk.h
@@ -0,0 +1,433 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2025-2026 MediaTek Inc.
+ * Qiqi Wang <qiqi.wang@mediatek.com>
+ * Irving-CH Lin <irving-ch.lin@mediatek.com>
+ * Copyright (C) 2026 Collabora Ltd.
+ * Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
+ */
+
+#ifndef _DT_BINDINGS_CLK_MT8189_H
+#define _DT_BINDINGS_CLK_MT8189_H
+
+/* TOPCKGEN */
+#define CLK_TOP_AXI_SEL 0
+#define CLK_TOP_AXI_PERI_SEL 1
+#define CLK_TOP_AXI_U_SEL 2
+#define CLK_TOP_BUS_AXIMEM_SEL 3
+#define CLK_TOP_DISP0_SEL 4
+#define CLK_TOP_MMINFRA_SEL 5
+#define CLK_TOP_UART_SEL 6
+#define CLK_TOP_SPI0_SEL 7
+#define CLK_TOP_SPI1_SEL 8
+#define CLK_TOP_SPI2_SEL 9
+#define CLK_TOP_SPI3_SEL 10
+#define CLK_TOP_SPI4_SEL 11
+#define CLK_TOP_SPI5_SEL 12
+#define CLK_TOP_MSDC_MACRO_0P_SEL 13
+#define CLK_TOP_MSDC50_0_HCLK_SEL 14
+#define CLK_TOP_MSDC50_0_SEL 15
+#define CLK_TOP_AES_MSDCFDE_SEL 16
+#define CLK_TOP_MSDC_MACRO_1P_SEL 17
+#define CLK_TOP_MSDC30_1_SEL 18
+#define CLK_TOP_MSDC30_1_HCLK_SEL 19
+#define CLK_TOP_MSDC_MACRO_2P_SEL 20
+#define CLK_TOP_MSDC30_2_SEL 21
+#define CLK_TOP_MSDC30_2_HCLK_SEL 22
+#define CLK_TOP_AUD_INTBUS_SEL 23
+#define CLK_TOP_ATB_SEL 24
+#define CLK_TOP_DISP_PWM_SEL 25
+#define CLK_TOP_USB_TOP_P0_SEL 26
+#define CLK_TOP_USB_XHCI_P0_SEL 27
+#define CLK_TOP_USB_TOP_P1_SEL 28
+#define CLK_TOP_USB_XHCI_P1_SEL 29
+#define CLK_TOP_USB_TOP_P2_SEL 30
+#define CLK_TOP_USB_XHCI_P2_SEL 31
+#define CLK_TOP_USB_TOP_P3_SEL 32
+#define CLK_TOP_USB_XHCI_P3_SEL 33
+#define CLK_TOP_USB_TOP_P4_SEL 34
+#define CLK_TOP_USB_XHCI_P4_SEL 35
+#define CLK_TOP_I2C_SEL 36
+#define CLK_TOP_SENINF_SEL 37
+#define CLK_TOP_SENINF1_SEL 38
+#define CLK_TOP_AUD_ENGEN1_SEL 39
+#define CLK_TOP_AUD_ENGEN2_SEL 40
+#define CLK_TOP_AES_UFSFDE_SEL 41
+#define CLK_TOP_U_SEL 42
+#define CLK_TOP_U_MBIST_SEL 43
+#define CLK_TOP_AUD_1_SEL 44
+#define CLK_TOP_AUD_2_SEL 45
+#define CLK_TOP_VENC_SEL 46
+#define CLK_TOP_VDEC_SEL 47
+#define CLK_TOP_PWM_SEL 48
+#define CLK_TOP_AUDIO_H_SEL 49
+#define CLK_TOP_MCUPM_SEL 50
+#define CLK_TOP_MEM_SUB_SEL 51
+#define CLK_TOP_MEM_SUB_PERI_SEL 52
+#define CLK_TOP_MEM_SUB_U_SEL 53
+#define CLK_TOP_EMI_N_SEL 54
+#define CLK_TOP_DSI_OCC_SEL 55
+#define CLK_TOP_AP2CONN_HOST_SEL 56
+#define CLK_TOP_IMG1_SEL 57
+#define CLK_TOP_IPE_SEL 58
+#define CLK_TOP_CAM_SEL 59
+#define CLK_TOP_CAMTM_SEL 60
+#define CLK_TOP_DSP_SEL 61
+#define CLK_TOP_SR_PKA_SEL 62
+#define CLK_TOP_DXCC_SEL 63
+#define CLK_TOP_MFG_REF_SEL 64
+#define CLK_TOP_MDP0_SEL 65
+#define CLK_TOP_DP_SEL 66
+#define CLK_TOP_EDP_SEL 67
+#define CLK_TOP_EDP_FAVT_SEL 68
+#define CLK_TOP_ETH_250M_SEL 69
+#define CLK_TOP_ETH_62P4M_PTP_SEL 70
+#define CLK_TOP_ETH_50M_RMII_SEL 71
+#define CLK_TOP_SFLASH_SEL 72
+#define CLK_TOP_GCPU_SEL 73
+#define CLK_TOP_MAC_TL_SEL 74
+#define CLK_TOP_VDSTX_DG_CTS_SEL 75
+#define CLK_TOP_PLL_DPIX_SEL 76
+#define CLK_TOP_ECC_SEL 77
+#define CLK_TOP_APLL_I2SIN0_MCK_SEL 78
+#define CLK_TOP_APLL_I2SIN1_MCK_SEL 79
+#define CLK_TOP_APLL_I2SIN2_MCK_SEL 80
+#define CLK_TOP_APLL_I2SIN3_MCK_SEL 81
+#define CLK_TOP_APLL_I2SIN4_MCK_SEL 82
+#define CLK_TOP_APLL_I2SIN6_MCK_SEL 83
+#define CLK_TOP_APLL_I2SOUT0_MCK_SEL 84
+#define CLK_TOP_APLL_I2SOUT1_MCK_SEL 85
+#define CLK_TOP_APLL_I2SOUT2_MCK_SEL 86
+#define CLK_TOP_APLL_I2SOUT3_MCK_SEL 87
+#define CLK_TOP_APLL_I2SOUT4_MCK_SEL 88
+#define CLK_TOP_APLL_I2SOUT6_MCK_SEL 89
+#define CLK_TOP_APLL_FMI2S_MCK_SEL 90
+#define CLK_TOP_APLL_TDMOUT_MCK_SEL 91
+#define CLK_TOP_MFG_SEL_MFGPLL 92
+#define CLK_TOP_APLL12_CK_DIV_I2SIN0 93
+#define CLK_TOP_APLL12_CK_DIV_I2SIN1 94
+#define CLK_TOP_APLL12_CK_DIV_I2SOUT0 95
+#define CLK_TOP_APLL12_CK_DIV_I2SOUT1 96
+#define CLK_TOP_APLL12_CK_DIV_FMI2S 97
+#define CLK_TOP_APLL12_CK_DIV_TDMOUT_M 98
+#define CLK_TOP_APLL12_CK_DIV_TDMOUT_B 99
+#define CLK_TOP_MAINPLL_D3 100
+#define CLK_TOP_MAINPLL_D4 101
+#define CLK_TOP_MAINPLL_D4_D2 102
+#define CLK_TOP_MAINPLL_D4_D4 103
+#define CLK_TOP_MAINPLL_D4_D8 104
+#define CLK_TOP_MAINPLL_D5 105
+#define CLK_TOP_MAINPLL_D5_D2 106
+#define CLK_TOP_MAINPLL_D5_D4 107
+#define CLK_TOP_MAINPLL_D5_D8 108
+#define CLK_TOP_MAINPLL_D6 109
+#define CLK_TOP_MAINPLL_D6_D2 110
+#define CLK_TOP_MAINPLL_D6_D4 111
+#define CLK_TOP_MAINPLL_D6_D8 112
+#define CLK_TOP_MAINPLL_D7 113
+#define CLK_TOP_MAINPLL_D7_D2 114
+#define CLK_TOP_MAINPLL_D7_D4 115
+#define CLK_TOP_MAINPLL_D7_D8 116
+#define CLK_TOP_MAINPLL_D9 117
+#define CLK_TOP_UNIVPLL_D2 118
+#define CLK_TOP_UNIVPLL_D3 119
+#define CLK_TOP_UNIVPLL_D4 120
+#define CLK_TOP_UNIVPLL_D4_D2 121
+#define CLK_TOP_UNIVPLL_D4_D4 122
+#define CLK_TOP_UNIVPLL_D4_D8 123
+#define CLK_TOP_UNIVPLL_D5 124
+#define CLK_TOP_UNIVPLL_D5_D2 125
+#define CLK_TOP_UNIVPLL_D5_D4 126
+#define CLK_TOP_UNIVPLL_D6 127
+#define CLK_TOP_UNIVPLL_D6_D2 128
+#define CLK_TOP_UNIVPLL_D6_D4 129
+#define CLK_TOP_UNIVPLL_D6_D8 130
+#define CLK_TOP_UNIVPLL_D6_D16 131
+#define CLK_TOP_UNIVPLL_D7 132
+#define CLK_TOP_UNIVPLL_D7_D2 133
+#define CLK_TOP_UNIVPLL_D7_D3 134
+#define CLK_TOP_LVDSTX_DG_CTS 135
+#define CLK_TOP_UNIVPLL_192M 136
+#define CLK_TOP_UNIVPLL_192M_D2 137
+#define CLK_TOP_UNIVPLL_192M_D4 138
+#define CLK_TOP_UNIVPLL_192M_D8 139
+#define CLK_TOP_UNIVPLL_192M_D10 140
+#define CLK_TOP_UNIVPLL_192M_D16 141
+#define CLK_TOP_UNIVPLL_192M_D32 142
+#define CLK_TOP_APLL1_D2 143
+#define CLK_TOP_APLL1_D4 144
+#define CLK_TOP_APLL1_D8 145
+#define CLK_TOP_APLL1_D3 146
+#define CLK_TOP_APLL2_D2 147
+#define CLK_TOP_APLL2_D4 148
+#define CLK_TOP_APLL2_D8 149
+#define CLK_TOP_APLL2_D3 150
+#define CLK_TOP_MMPLL_D4 151
+#define CLK_TOP_MMPLL_D4_D2 152
+#define CLK_TOP_MMPLL_D4_D4 153
+#define CLK_TOP_VPLL_DPIX 154
+#define CLK_TOP_MMPLL_D5 155
+#define CLK_TOP_MMPLL_D5_D2 156
+#define CLK_TOP_MMPLL_D5_D4 157
+#define CLK_TOP_MMPLL_D6 158
+#define CLK_TOP_MMPLL_D6_D2 159
+#define CLK_TOP_MMPLL_D7 160
+#define CLK_TOP_MMPLL_D9 161
+#define CLK_TOP_TVDPLL1_D2 162
+#define CLK_TOP_TVDPLL1_D4 163
+#define CLK_TOP_TVDPLL1_D8 164
+#define CLK_TOP_TVDPLL1_D16 165
+#define CLK_TOP_TVDPLL2_D2 166
+#define CLK_TOP_TVDPLL2_D4 167
+#define CLK_TOP_TVDPLL2_D8 168
+#define CLK_TOP_TVDPLL2_D16 169
+#define CLK_TOP_ETHPLL_D2 170
+#define CLK_TOP_ETHPLL_D8 171
+#define CLK_TOP_ETHPLL_D10 172
+#define CLK_TOP_MSDCPLL_D2 173
+#define CLK_TOP_UFSPLL_D2 174
+#define CLK_TOP_F26M_CK_D2 175
+#define CLK_TOP_OSC_D2 176
+#define CLK_TOP_OSC_D4 177
+#define CLK_TOP_OSC_D8 178
+#define CLK_TOP_OSC_D16 179
+#define CLK_TOP_OSC_D3 180
+#define CLK_TOP_OSC_D7 181
+#define CLK_TOP_OSC_D10 182
+#define CLK_TOP_OSC_D20 183
+#define CLK_TOP_FMCNT_P0_EN 184
+#define CLK_TOP_FMCNT_P1_EN 185
+#define CLK_TOP_FMCNT_P2_EN 186
+#define CLK_TOP_FMCNT_P3_EN 187
+#define CLK_TOP_FMCNT_P4_EN 188
+#define CLK_TOP_USB_F26M_CK_EN 189
+#define CLK_TOP_SSPXTP_F26M_CK_EN 190
+#define CLK_TOP_USB2_PHY_RF_P0_EN 191
+#define CLK_TOP_USB2_PHY_RF_P1_EN 192
+#define CLK_TOP_USB2_PHY_RF_P2_EN 193
+#define CLK_TOP_USB2_PHY_RF_P3_EN 194
+#define CLK_TOP_USB2_PHY_RF_P4_EN 195
+#define CLK_TOP_USB2_26M_CK_P0_EN 196
+#define CLK_TOP_USB2_26M_CK_P1_EN 197
+#define CLK_TOP_USB2_26M_CK_P2_EN 198
+#define CLK_TOP_USB2_26M_CK_P3_EN 199
+#define CLK_TOP_USB2_26M_CK_P4_EN 200
+#define CLK_TOP_F26M_CK_EN 201
+#define CLK_TOP_AP2CON_EN 202
+#define CLK_TOP_EINT_N_EN 203
+#define CLK_TOP_TOPCKGEN_FMIPI_CSI_UP26M_CK_EN 204
+#define CLK_TOP_EINT_E_EN 205
+#define CLK_TOP_EINT_W_EN 206
+#define CLK_TOP_EINT_S_EN 207
+
+/* INFRACFG_AO */
+#define CLK_IFRAO_CQ_DMA_FPC 0
+#define CLK_IFRAO_DEBUGSYS 1
+#define CLK_IFRAO_DBG_TRACE 2
+#define CLK_IFRAO_CQ_DMA 3
+
+/* APMIXEDSYS */
+#define CLK_APMIXED_ARMPLL_LL 0
+#define CLK_APMIXED_ARMPLL_BL 1
+#define CLK_APMIXED_CCIPLL 2
+#define CLK_APMIXED_MAINPLL 3
+#define CLK_APMIXED_UNIVPLL 4
+#define CLK_APMIXED_MMPLL 5
+#define CLK_APMIXED_MFGPLL 6
+#define CLK_APMIXED_APLL1 7
+#define CLK_APMIXED_APLL2 8
+#define CLK_APMIXED_EMIPLL 9
+#define CLK_APMIXED_APUPLL2 10
+#define CLK_APMIXED_APUPLL 11
+#define CLK_APMIXED_TVDPLL1 12
+#define CLK_APMIXED_TVDPLL2 13
+#define CLK_APMIXED_ETHPLL 14
+#define CLK_APMIXED_MSDCPLL 15
+#define CLK_APMIXED_UFSPLL 16
+
+/* PERICFG_AO */
+#define CLK_PERAO_UART0 0
+#define CLK_PERAO_UART1 1
+#define CLK_PERAO_UART2 2
+#define CLK_PERAO_UART3 3
+#define CLK_PERAO_PWM_H 4
+#define CLK_PERAO_PWM_B 5
+#define CLK_PERAO_PWM_FB1 6
+#define CLK_PERAO_PWM_FB2 7
+#define CLK_PERAO_PWM_FB3 8
+#define CLK_PERAO_PWM_FB4 9
+#define CLK_PERAO_DISP_PWM0 10
+#define CLK_PERAO_DISP_PWM1 11
+#define CLK_PERAO_SPI0_B 12
+#define CLK_PERAO_SPI1_B 13
+#define CLK_PERAO_SPI2_B 14
+#define CLK_PERAO_SPI3_B 15
+#define CLK_PERAO_SPI4_B 16
+#define CLK_PERAO_SPI5_B 17
+#define CLK_PERAO_SPI0_H 18
+#define CLK_PERAO_SPI1_H 19
+#define CLK_PERAO_SPI2_H 20
+#define CLK_PERAO_SPI3_H 21
+#define CLK_PERAO_SPI4_H 22
+#define CLK_PERAO_SPI5_H 23
+#define CLK_PERAO_AXI 24
+#define CLK_PERAO_AHB_APB 25
+#define CLK_PERAO_TL 26
+#define CLK_PERAO_REF 27
+#define CLK_PERAO_I2C 28
+#define CLK_PERAO_DMA_B 29
+#define CLK_PERAO_SSUSB0_REF 30
+#define CLK_PERAO_SSUSB0_FRMCNT 31
+#define CLK_PERAO_SSUSB0_SYS 32
+#define CLK_PERAO_SSUSB0_XHCI 33
+#define CLK_PERAO_SSUSB0_F 34
+#define CLK_PERAO_SSUSB0_H 35
+#define CLK_PERAO_SSUSB1_REF 36
+#define CLK_PERAO_SSUSB1_FRMCNT 37
+#define CLK_PERAO_SSUSB1_SYS 38
+#define CLK_PERAO_SSUSB1_XHCI 39
+#define CLK_PERAO_SSUSB1_F 40
+#define CLK_PERAO_SSUSB1_H 41
+#define CLK_PERAO_SSUSB2_REF 42
+#define CLK_PERAO_SSUSB2_FRMCNT 43
+#define CLK_PERAO_SSUSB2_SYS 44
+#define CLK_PERAO_SSUSB2_XHCI 45
+#define CLK_PERAO_SSUSB2_F 46
+#define CLK_PERAO_SSUSB2_H 47
+#define CLK_PERAO_SSUSB3_REF 48
+#define CLK_PERAO_SSUSB3_FRMCNT 49
+#define CLK_PERAO_SSUSB3_SYS 50
+#define CLK_PERAO_SSUSB3_XHCI 51
+#define CLK_PERAO_SSUSB3_F 52
+#define CLK_PERAO_SSUSB3_H 53
+#define CLK_PERAO_SSUSB4_REF 54
+#define CLK_PERAO_SSUSB4_FRMCNT 55
+#define CLK_PERAO_SSUSB4_SYS 56
+#define CLK_PERAO_SSUSB4_XHCI 57
+#define CLK_PERAO_SSUSB4_F 58
+#define CLK_PERAO_SSUSB4_H 59
+#define CLK_PERAO_MSDC0 60
+#define CLK_PERAO_MSDC0_H 61
+#define CLK_PERAO_MSDC0_FAES 62
+#define CLK_PERAO_MSDC0_MST_F 63
+#define CLK_PERAO_MSDC0_SLV_H 64
+#define CLK_PERAO_MSDC1 65
+#define CLK_PERAO_MSDC1_H 66
+#define CLK_PERAO_MSDC1_MST_F 67
+#define CLK_PERAO_MSDC1_SLV_H 68
+#define CLK_PERAO_MSDC2 69
+#define CLK_PERAO_MSDC2_H 70
+#define CLK_PERAO_MSDC2_MST_F 71
+#define CLK_PERAO_MSDC2_SLV_H 72
+#define CLK_PERAO_SFLASH 73
+#define CLK_PERAO_SFLASH_F 74
+#define CLK_PERAO_SFLASH_H 75
+#define CLK_PERAO_SFLASH_P 76
+#define CLK_PERAO_AUDIO0 77
+#define CLK_PERAO_AUDIO1 78
+#define CLK_PERAO_AUDIO2 79
+#define CLK_PERAO_AUXADC_26M 80
+
+/* UFSCFG_AO_REG */
+#define CLK_UFSCFG_AO_REG_UNIPRO_TX_SYM 0
+#define CLK_UFSCFG_AO_REG_UNIPRO_RX_SYM0 1
+#define CLK_UFSCFG_AO_REG_UNIPRO_RX_SYM1 2
+#define CLK_UFSCFG_AO_REG_UNIPRO_SYS 3
+#define CLK_UFSCFG_AO_REG_U_SAP_CFG 4
+#define CLK_UFSCFG_AO_REG_U_PHY_TOP_AHB_S_BUS 5
+
+/* UFSCFG_PDN_REG */
+#define CLK_UFSCFG_REG_UFSHCI_UFS 0
+#define CLK_UFSCFG_REG_UFSHCI_AES 1
+#define CLK_UFSCFG_REG_UFSHCI_U_AHB 2
+#define CLK_UFSCFG_REG_UFSHCI_U_AXI 3
+
+/* IMP_IIC_WRAP_WS */
+#define CLK_IMPWS_I2C2 0
+
+/* IMP_IIC_WRAP_E */
+#define CLK_IMPE_I2C0 0
+#define CLK_IMPE_I2C1 1
+
+/* IMP_IIC_WRAP_S */
+#define CLK_IMPS_I2C3 0
+#define CLK_IMPS_I2C4 1
+#define CLK_IMPS_I2C5 2
+#define CLK_IMPS_I2C6 3
+
+/* IMP_IIC_WRAP_EN */
+#define CLK_IMPEN_I2C7 0
+#define CLK_IMPEN_I2C8 1
+
+/* VLPCFG_REG */
+#define CLK_VLPCFG_REG_SCP 0
+#define CLK_VLPCFG_REG_RG_R_APXGPT_26M 1
+#define CLK_VLPCFG_REG_DPMSRCK_TEST 2
+#define CLK_VLPCFG_REG_RG_DPMSRRTC_TEST 3
+#define CLK_VLPCFG_REG_DPMSRULP_TEST 4
+#define CLK_VLPCFG_REG_SPMI_P_MST 5
+#define CLK_VLPCFG_REG_SPMI_P_MST_32K 6
+#define CLK_VLPCFG_REG_PMIF_SPMI_P_SYS 7
+#define CLK_VLPCFG_REG_PMIF_SPMI_P_TMR 8
+#define CLK_VLPCFG_REG_PMIF_SPMI_M_SYS 9
+#define CLK_VLPCFG_REG_PMIF_SPMI_M_TMR 10
+#define CLK_VLPCFG_REG_DVFSRC 11
+#define CLK_VLPCFG_REG_PWM_VLP 12
+#define CLK_VLPCFG_REG_SRCK 13
+#define CLK_VLPCFG_REG_SSPM_F26M 14
+#define CLK_VLPCFG_REG_SSPM_F32K 15
+#define CLK_VLPCFG_REG_SSPM_ULPOSC 16
+#define CLK_VLPCFG_REG_VLP_32K_COM 17
+#define CLK_VLPCFG_REG_VLP_26M_COM 18
+
+/* VLP_CKSYS */
+#define CLK_VLP_CK_SCP_SEL 0
+#define CLK_VLP_CK_PWRAP_ULPOSC_SEL 1
+#define CLK_VLP_CK_SPMI_P_MST_SEL 2
+#define CLK_VLP_CK_DVFSRC_SEL 3
+#define CLK_VLP_CK_PWM_VLP_SEL 4
+#define CLK_VLP_CK_AXI_VLP_SEL 5
+#define CLK_VLP_CK_SYSTIMER_26M_SEL 6
+#define CLK_VLP_CK_SSPM_SEL 7
+#define CLK_VLP_CK_SSPM_F26M_SEL 8
+#define CLK_VLP_CK_SRCK_SEL 9
+#define CLK_VLP_CK_SCP_SPI_SEL 10
+#define CLK_VLP_CK_SCP_IIC_SEL 11
+#define CLK_VLP_CK_SCP_SPI_HIGH_SPD_SEL 12
+#define CLK_VLP_CK_SCP_IIC_HIGH_SPD_SEL 13
+#define CLK_VLP_CK_SSPM_ULPOSC_SEL 14
+#define CLK_VLP_CK_APXGPT_26M_SEL 15
+#define CLK_VLP_CK_VADSP_SEL 16
+#define CLK_VLP_CK_VADSP_VOWPLL_SEL 17
+#define CLK_VLP_CK_VADSP_UARTHUB_BCLK_SEL 18
+#define CLK_VLP_CK_CAMTG0_SEL 19
+#define CLK_VLP_CK_CAMTG1_SEL 20
+#define CLK_VLP_CK_CAMTG2_SEL 21
+#define CLK_VLP_CK_AUD_ADC_SEL 22
+#define CLK_VLP_CK_KP_IRQ_GEN_SEL 23
+#define CLK_VLP_CK_VADSYS_VLP_26M_EN 24
+#define CLK_VLP_CK_FMIPI_CSI_UP26M_CK_EN 25
+
+/* SCP_IIC */
+#define CLK_SCP_IIC_I2C0_W1S 0
+#define CLK_SCP_IIC_I2C1_W1S 1
+
+/* SCP */
+#define CLK_SCP_SET_SPI0 0
+#define CLK_SCP_SET_SPI1 1
+
+/* VLPCFG_AO_REG */
+#define CLK_VLPCFG_AO_APEINT_RX 0
+
+/* DVFSRC_TOP */
+#define CLK_DVFSRC_TOP_DVFSRC_EN 0
+
+/* DBGAO */
+#define CLK_DBGAO_ATB_EN 0
+
+/* DEM */
+#define CLK_DEM_ATB_EN 0
+#define CLK_DEM_BUSCLK_EN 1
+#define CLK_DEM_SYSCLK_EN 2
+
+#endif /* _DT_BINDINGS_CLK_MT8189_H */
diff --git a/include/dt-bindings/reset/mediatek,mt8189-resets.h b/include/dt-bindings/reset/mediatek,mt8189-resets.h
new file mode 100644
index 000000000000..0f31984374be
--- /dev/null
+++ b/include/dt-bindings/reset/mediatek,mt8189-resets.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2026 Collabora Ltd.
+ * Author: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
+ */
+
+#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT8189
+#define _DT_BINDINGS_RESET_CONTROLLER_MT8189
+
+/* UFS resets */
+#define MT8189_UFSAO_RST_UFS_MPHY 0
+
+#define MT8189_UFSPDN_RST_UFS_UNIPRO 0
+#define MT8189_UFSPDN_RST_UFS_CRYPTO 1
+#define MT8189_UFSPDN_RST_UFS_HCI 2
+
+#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8189 */
--
2.54.0
^ permalink raw reply related
* [PATCH 06/15] clk: mediatek: Add MT8189 apmixedsys clock support
From: Louis-Alexis Eyraud @ 2026-07-01 13:11 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Brian Masney, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chun-Jie Chen, Philipp Zabel,
Edward-JW Yang, Richard Cochran
Cc: kernel, linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Irving-CH Lin, Louis-Alexis Eyraud
In-Reply-To: <20260701-mt8189-clocks-system-base-v1-0-2b048feea50a@collabora.com>
Add support for the MT8189 apmixedsys clock controller, which provides
PLLs generated from SoC 26m.
Co-developed-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
Signed-off-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
Co-developed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
drivers/clk/mediatek/Kconfig | 13 ++
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8189-apmixedsys.c | 196 +++++++++++++++++++++++++++
3 files changed, 210 insertions(+)
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 2c09fd729bab..f67dfb6cd019 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -815,6 +815,19 @@ config COMMON_CLK_MT8188_WPESYS
help
This driver supports MediaTek MT8188 Warp Engine clocks.
+config COMMON_CLK_MT8189
+ tristate "Clock driver for MediaTek MT8189"
+ depends on ARM64 || COMPILE_TEST
+ select COMMON_CLK_MEDIATEK
+ select COMMON_CLK_MEDIATEK_FHCTL
+ default ARCH_MEDIATEK
+ help
+ Enable this option to support the clock management for MediaTek MT8189 SoC. This
+ includes handling of all primary clock functions and features specific to the MT8189
+ platform. Enabling this driver ensures that the system's clock functionality aligns
+ with the MediaTek MT8189 hardware capabilities, providing efficient management of
+ clock speeds and power consumption.
+
config COMMON_CLK_MT8192
tristate "Clock driver for MediaTek MT8192"
depends on ARM64 || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index d8736a060dbd..66577ccb9b93 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -123,6 +123,7 @@ obj-$(CONFIG_COMMON_CLK_MT8188_VDOSYS) += clk-mt8188-vdo0.o clk-mt8188-vdo1.o
obj-$(CONFIG_COMMON_CLK_MT8188_VENCSYS) += clk-mt8188-venc.o
obj-$(CONFIG_COMMON_CLK_MT8188_VPPSYS) += clk-mt8188-vpp0.o clk-mt8188-vpp1.o
obj-$(CONFIG_COMMON_CLK_MT8188_WPESYS) += clk-mt8188-wpe.o
+obj-$(CONFIG_COMMON_CLK_MT8189) += clk-mt8189-apmixedsys.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192-apmixedsys.o clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8189-apmixedsys.c b/drivers/clk/mediatek/clk-mt8189-apmixedsys.c
new file mode 100644
index 000000000000..0657a50c30d9
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8189-apmixedsys.c
@@ -0,0 +1,196 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025-2026 MediaTek Inc.
+ * Qiqi Wang <qiqi.wang@mediatek.com>
+ * Irving-CH Lin <irving-ch.lin@mediatek.com>
+ * Copyright (C) 2026 Collabora Ltd.
+ * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ * Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include "clk-fhctl.h"
+#include "clk-mtk.h"
+#include "clk-pll.h"
+
+#include <dt-bindings/clock/mediatek,mt8189-clk.h>
+
+#define MT8189_PLL_FMAX (3800UL * MHZ)
+#define MT8189_PLL_FMIN (1500UL * MHZ)
+#define MT8189_PLLEN_OFS 0x70
+#define MT8189_INTEGER_BITS 8
+
+#define PLL_SETCLR(_id, _name, _reg, _en_setclr_bit, \
+ _rstb_setclr_bit, _flags, _pd_reg, \
+ _pd_shift, _tuner_reg, _tuner_en_reg, \
+ _tuner_en_bit, _pcw_reg, _pcw_shift, \
+ _pcwbits) { \
+ .id = _id, \
+ .name = _name, \
+ .en_reg = MT8189_PLLEN_OFS, \
+ .reg = _reg, \
+ .pll_en_bit = _en_setclr_bit, \
+ .rst_bar_mask = BIT(_rstb_setclr_bit), \
+ .flags = _flags, \
+ .fmax = MT8189_PLL_FMAX, \
+ .fmin = MT8189_PLL_FMIN, \
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .tuner_reg = _tuner_reg, \
+ .tuner_en_reg = _tuner_en_reg, \
+ .tuner_en_bit = _tuner_en_bit, \
+ .pcw_reg = _pcw_reg, \
+ .pcw_shift = _pcw_shift, \
+ .pcwbits = _pcwbits, \
+ .pcwibits = MT8189_INTEGER_BITS, \
+ }
+
+static const struct mtk_pll_data apmixed_plls[] = {
+ PLL_SETCLR(CLK_APMIXED_ARMPLL_LL, "armpll-ll", 0x204, 18,
+ 0, PLL_AO, 0x208, 24, 0, 0, 0, 0x208, 0, 22),
+ PLL_SETCLR(CLK_APMIXED_ARMPLL_BL, "armpll-bl", 0x214, 17,
+ 0, PLL_AO, 0x218, 24, 0, 0, 0, 0x218, 0, 22),
+ PLL_SETCLR(CLK_APMIXED_CCIPLL, "ccipll", 0x224, 16,
+ 0, PLL_AO, 0x228, 24, 0, 0, 0, 0x228, 0, 22),
+ PLL_SETCLR(CLK_APMIXED_MAINPLL, "mainpll", 0x304, 15,
+ 23, HAVE_RST_BAR | PLL_AO,
+ 0x308, 24, 0, 0, 0, 0x308, 0, 22),
+ PLL_SETCLR(CLK_APMIXED_UNIVPLL, "univpll", 0x314, 14,
+ 23, HAVE_RST_BAR, 0x318, 24, 0, 0, 0, 0x318, 0, 22),
+ PLL_SETCLR(CLK_APMIXED_MMPLL, "mmpll", 0x324, 13,
+ 23, HAVE_RST_BAR, 0x328, 24, 0, 0, 0, 0x328, 0, 22),
+ PLL_SETCLR(CLK_APMIXED_MFGPLL, "mfgpll", 0x504, 7,
+ 0, 0, 0x508, 24, 0, 0, 0, 0x508, 0, 22),
+ PLL_SETCLR(CLK_APMIXED_APLL1, "apll1", 0x404, 11,
+ 0, 0, 0x408, 24, 0x040, 0x00c, 0, 0x40c, 0, 32),
+ PLL_SETCLR(CLK_APMIXED_APLL2, "apll2", 0x418, 10,
+ 0, 0, 0x41c, 24, 0x044, 0x00c, 1, 0x420, 0, 32),
+ PLL_SETCLR(CLK_APMIXED_EMIPLL, "emipll", 0x334, 12,
+ 0, PLL_AO, 0x338, 24, 0, 0, 0, 0x338, 0, 22),
+ PLL_SETCLR(CLK_APMIXED_APUPLL2, "apupll2", 0x614, 2,
+ 0, 0, 0x618, 24, 0, 0, 0, 0x618, 0, 22),
+ PLL_SETCLR(CLK_APMIXED_APUPLL, "apupll", 0x604, 3,
+ 0, 0, 0x608, 24, 0, 0, 0, 0x608, 0, 22),
+ PLL_SETCLR(CLK_APMIXED_TVDPLL1, "tvdpll1", 0x42c, 9,
+ 0, 0, 0x430, 24, 0, 0, 0, 0x430, 0, 22),
+ PLL_SETCLR(CLK_APMIXED_TVDPLL2, "tvdpll2", 0x43c, 8,
+ 0, 0, 0x440, 24, 0, 0, 0, 0x440, 0, 22),
+ PLL_SETCLR(CLK_APMIXED_ETHPLL, "ethpll", 0x514, 6,
+ 0, 0, 0x518, 24, 0, 0, 0, 0x518, 0, 22),
+ PLL_SETCLR(CLK_APMIXED_MSDCPLL, "msdcpll", 0x524, 5,
+ 0, 0, 0x528, 24, 0, 0, 0, 0x528, 0, 22),
+ PLL_SETCLR(CLK_APMIXED_UFSPLL, "ufspll", 0x534, 4,
+ 0, 0, 0x538, 24, 0, 0, 0, 0x538, 0, 22),
+};
+
+#define FH(_pllid, _fhid, _offset) { \
+ .data = { \
+ .pll_id = _pllid, \
+ .fh_id = _fhid, \
+ .fh_ver = FHCTL_PLLFH_V2, \
+ .fhx_offset = _offset, \
+ .dds_mask = GENMASK(21, 0), \
+ .slope0_value = 0x6003c97, \
+ .slope1_value = 0x6003c97, \
+ .sfstrx_en = BIT(2), \
+ .frddsx_en = BIT(1), \
+ .fhctlx_en = BIT(0), \
+ .tgl_org = BIT(31), \
+ .dvfs_tri = BIT(31), \
+ .pcwchg = BIT(31), \
+ .dt_val = 0x0, \
+ .df_val = 0x9, \
+ .updnlmt_shft = 16, \
+ .msk_frddsx_dys = GENMASK(23, 20), \
+ .msk_frddsx_dts = GENMASK(19, 16), \
+ }, \
+ }
+
+static struct mtk_pllfh_data pllfhs[] = {
+ FH(CLK_APMIXED_ARMPLL_LL, 0, 0x003C),
+ FH(CLK_APMIXED_ARMPLL_BL, 1, 0x0050),
+ FH(CLK_APMIXED_CCIPLL, 2, 0x0064),
+ FH(CLK_APMIXED_MAINPLL, 3, 0x0078),
+ FH(CLK_APMIXED_MMPLL, 4, 0x008C),
+ FH(CLK_APMIXED_MFGPLL, 5, 0x00A0),
+ FH(CLK_APMIXED_EMIPLL, 6, 0x00B4),
+ FH(CLK_APMIXED_TVDPLL1, 7, 0x00C8),
+ FH(CLK_APMIXED_TVDPLL2, 8, 0x00DC),
+ FH(CLK_APMIXED_MSDCPLL, 9, 0x00F0),
+ FH(CLK_APMIXED_UFSPLL, 10, 0x0104),
+ FH(CLK_APMIXED_APUPLL, 11, 0x0118),
+ FH(CLK_APMIXED_APUPLL2, 12, 0x012c),
+};
+
+static const struct of_device_id of_match_clk_mt8189_apmixed[] = {
+ { .compatible = "mediatek,mt8189-apmixedsys" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, of_match_clk_mt8189_apmixed);
+
+static int clk_mt8189_apmixed_probe(struct platform_device *pdev)
+{
+ int r;
+ struct clk_hw_onecell_data *clk_data;
+ struct device_node *node = pdev->dev.of_node;
+ const u8 *fhctl_node = "mediatek,mt8189-fhctl";
+
+ clk_data = mtk_alloc_clk_data(ARRAY_SIZE(apmixed_plls));
+ if (!clk_data)
+ return -ENOMEM;
+
+ fhctl_parse_dt(fhctl_node, pllfhs, ARRAY_SIZE(pllfhs));
+
+ r = mtk_clk_register_pllfhs(&pdev->dev, apmixed_plls, ARRAY_SIZE(apmixed_plls),
+ pllfhs, ARRAY_SIZE(pllfhs), clk_data);
+ if (r)
+ goto free_apmixed_data;
+
+ r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
+ if (r)
+ goto unregister_plls;
+
+ platform_set_drvdata(pdev, clk_data);
+
+ return 0;
+
+unregister_plls:
+ mtk_clk_unregister_pllfhs(apmixed_plls, ARRAY_SIZE(apmixed_plls), pllfhs,
+ ARRAY_SIZE(pllfhs), clk_data);
+free_apmixed_data:
+ mtk_free_clk_data(clk_data);
+ return r;
+}
+
+static void clk_mt8189_apmixed_remove(struct platform_device *pdev)
+{
+ struct device_node *node = pdev->dev.of_node;
+ struct clk_hw_onecell_data *clk_data = platform_get_drvdata(pdev);
+
+ of_clk_del_provider(node);
+ mtk_clk_unregister_pllfhs(apmixed_plls, ARRAY_SIZE(apmixed_plls), pllfhs,
+ ARRAY_SIZE(pllfhs), clk_data);
+ mtk_free_clk_data(clk_data);
+}
+
+static struct platform_driver clk_mt8189_apmixed_drv = {
+ .probe = clk_mt8189_apmixed_probe,
+ .remove = clk_mt8189_apmixed_remove,
+ .driver = {
+ .name = "clk-mt8189-apmixed",
+ .of_match_table = of_match_clk_mt8189_apmixed,
+ },
+};
+module_platform_driver(clk_mt8189_apmixed_drv);
+
+MODULE_DESCRIPTION("MediaTek MT8189 apmixed clocks driver");
+MODULE_LICENSE("GPL");
--
2.54.0
^ permalink raw reply related
* [PATCH 10/15] clk: mediatek: Add MT8189 bus clock support
From: Louis-Alexis Eyraud @ 2026-07-01 13:11 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Brian Masney, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chun-Jie Chen, Philipp Zabel,
Edward-JW Yang, Richard Cochran
Cc: kernel, linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Irving-CH Lin, Louis-Alexis Eyraud
In-Reply-To: <20260701-mt8189-clocks-system-base-v1-0-2b048feea50a@collabora.com>
Add support for the MT8189 bus clock controller,
which provides clock gate control for infra/peri IPs
(such as spi, uart, msdc, flashif ...).
Co-developed-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
Signed-off-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
Co-developed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
drivers/clk/mediatek/Kconfig | 11 ++
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8189-bus.c | 200 ++++++++++++++++++++++++++++++++++
3 files changed, 212 insertions(+)
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index f67dfb6cd019..8eba45f05968 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -828,6 +828,17 @@ config COMMON_CLK_MT8189
with the MediaTek MT8189 hardware capabilities, providing efficient management of
clock speeds and power consumption.
+config COMMON_CLK_MT8189_BUS
+ tristate "Clock driver for MediaTek MT8189 bus"
+ depends on COMMON_CLK_MT8189
+ default COMMON_CLK_MT8189
+ help
+ Enable this configuration option to support the clock framework for
+ MediaTek MT8189 SoC bus clocks. It includes the necessary clock
+ management for bus-related peripherals and interconnects within the
+ MT8189 chipset, ensuring that all bus-related components receive the
+ correct clock signals for optimal performance.
+
config COMMON_CLK_MT8192
tristate "Clock driver for MediaTek MT8192"
depends on ARM64 || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index d9279b237b7b..aabfb42cb1b2 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -125,6 +125,7 @@ obj-$(CONFIG_COMMON_CLK_MT8188_VPPSYS) += clk-mt8188-vpp0.o clk-mt8188-vpp1.o
obj-$(CONFIG_COMMON_CLK_MT8188_WPESYS) += clk-mt8188-wpe.o
obj-$(CONFIG_COMMON_CLK_MT8189) += clk-mt8189-apmixedsys.o clk-mt8189-topckgen.o \
clk-mt8189-vlpckgen.o clk-mt8189-vlpcfg.o
+obj-$(CONFIG_COMMON_CLK_MT8189_BUS) += clk-mt8189-bus.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192-apmixedsys.o clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8189-bus.c b/drivers/clk/mediatek/clk-mt8189-bus.c
new file mode 100644
index 000000000000..494f25e85d11
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8189-bus.c
@@ -0,0 +1,200 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025-2026 MediaTek Inc.
+ * Qiqi Wang <qiqi.wang@mediatek.com>
+ * Irving-CH Lin <irving-ch.lin@mediatek.com>
+ * Copyright (C) 2026 Collabora Ltd.
+ * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ * Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mediatek,mt8189-clk.h>
+
+static const struct mtk_gate_regs ifrao0_cg_regs = {
+ .set_ofs = 0x80,
+ .clr_ofs = 0x84,
+ .sta_ofs = 0x90,
+};
+
+static const struct mtk_gate_regs ifrao1_cg_regs = {
+ .set_ofs = 0x88,
+ .clr_ofs = 0x8c,
+ .sta_ofs = 0x94,
+};
+
+static const struct mtk_gate_regs ifrao2_cg_regs = {
+ .set_ofs = 0xa4,
+ .clr_ofs = 0xa8,
+ .sta_ofs = 0xac,
+};
+
+#define GATE_IFRAO0(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &ifrao0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+#define GATE_IFRAO1(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &ifrao1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+#define GATE_IFRAO2(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &ifrao2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+static const struct mtk_gate ifrao_clks[] = {
+ /* IFRAO0 */
+ GATE_IFRAO0(CLK_IFRAO_CQ_DMA_FPC, "ifrao_dma", "ap2con", 28),
+ /* IFRAO1 */
+ GATE_IFRAO1(CLK_IFRAO_DEBUGSYS, "ifrao_debugsys", "axi_sel", 24),
+ GATE_IFRAO1(CLK_IFRAO_DBG_TRACE, "ifrao_dbg_trace", "axi_sel", 29),
+ /* IFRAO2 */
+ GATE_IFRAO2(CLK_IFRAO_CQ_DMA, "ifrao_cq_dma", "axi_sel", 27),
+};
+
+static const struct mtk_clk_desc ifrao_mcd = {
+ .clks = ifrao_clks,
+ .num_clks = ARRAY_SIZE(ifrao_clks),
+};
+
+static const struct mtk_gate_regs perao0_cg_regs = {
+ .set_ofs = 0x24,
+ .clr_ofs = 0x28,
+ .sta_ofs = 0x10,
+};
+
+static const struct mtk_gate_regs perao1_cg_regs = {
+ .set_ofs = 0x2c,
+ .clr_ofs = 0x30,
+ .sta_ofs = 0x14,
+};
+
+static const struct mtk_gate_regs perao2_cg_regs = {
+ .set_ofs = 0x34,
+ .clr_ofs = 0x38,
+ .sta_ofs = 0x18,
+};
+
+#define GATE_PERAO0(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &perao0_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+#define GATE_PERAO1(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &perao1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+#define GATE_PERAO2(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &perao2_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+static const struct mtk_gate perao_clks[] = {
+ /* PERAO0 */
+ GATE_PERAO0(CLK_PERAO_UART0, "perao_uart0", "uart_sel", 0),
+ GATE_PERAO0(CLK_PERAO_UART1, "perao_uart1", "uart_sel", 1),
+ GATE_PERAO0(CLK_PERAO_UART2, "perao_uart2", "uart_sel", 2),
+ GATE_PERAO0(CLK_PERAO_UART3, "perao_uart3", "uart_sel", 3),
+ GATE_PERAO0(CLK_PERAO_PWM_H, "perao_pwm_h", "axi_peri_sel", 4),
+ GATE_PERAO0(CLK_PERAO_PWM_B, "perao_pwm_b", "pwm_sel", 5),
+ GATE_PERAO0(CLK_PERAO_PWM_FB1, "perao_pwm_fb1", "pwm_sel", 6),
+ GATE_PERAO0(CLK_PERAO_PWM_FB2, "perao_pwm_fb2", "pwm_sel", 7),
+ GATE_PERAO0(CLK_PERAO_PWM_FB3, "perao_pwm_fb3", "pwm_sel", 8),
+ GATE_PERAO0(CLK_PERAO_PWM_FB4, "perao_pwm_fb4", "pwm_sel", 9),
+ GATE_PERAO0(CLK_PERAO_DISP_PWM0, "perao_disp_pwm0", "disp_pwm_sel", 10),
+ GATE_PERAO0(CLK_PERAO_DISP_PWM1, "perao_disp_pwm1", "disp_pwm_sel", 11),
+ GATE_PERAO0(CLK_PERAO_SPI0_B, "perao_spi0_b", "spi0_sel", 12),
+ GATE_PERAO0(CLK_PERAO_SPI1_B, "perao_spi1_b", "spi1_sel", 13),
+ GATE_PERAO0(CLK_PERAO_SPI2_B, "perao_spi2_b", "spi2_sel", 14),
+ GATE_PERAO0(CLK_PERAO_SPI3_B, "perao_spi3_b", "spi3_sel", 15),
+ GATE_PERAO0(CLK_PERAO_SPI4_B, "perao_spi4_b", "spi4_sel", 16),
+ GATE_PERAO0(CLK_PERAO_SPI5_B, "perao_spi5_b", "spi5_sel", 17),
+ GATE_PERAO0(CLK_PERAO_SPI0_H, "perao_spi0_h", "axi_peri_sel", 18),
+ GATE_PERAO0(CLK_PERAO_SPI1_H, "perao_spi1_h", "axi_peri_sel", 19),
+ GATE_PERAO0(CLK_PERAO_SPI2_H, "perao_spi2_h", "axi_peri_sel", 20),
+ GATE_PERAO0(CLK_PERAO_SPI3_H, "perao_spi3_h", "axi_peri_sel", 21),
+ GATE_PERAO0(CLK_PERAO_SPI4_H, "perao_spi4_h", "axi_peri_sel", 22),
+ GATE_PERAO0(CLK_PERAO_SPI5_H, "perao_spi5_h", "axi_peri_sel", 23),
+ GATE_PERAO0(CLK_PERAO_AXI, "perao_axi", "mem_sub_peri_sel", 24),
+ GATE_PERAO0(CLK_PERAO_AHB_APB, "perao_ahb_apb", "axi_peri_sel", 25),
+ GATE_PERAO0(CLK_PERAO_TL, "perao_tl", "pcie_mac_tl_sel", 26),
+ GATE_PERAO0(CLK_PERAO_REF, "perao_ref", "pcie_f26m", 27),
+ GATE_PERAO0(CLK_PERAO_I2C, "perao_i2c", "axi_peri_sel", 28),
+ GATE_PERAO0(CLK_PERAO_DMA_B, "perao_dma_b", "axi_peri_sel", 29),
+ /* PERAO1 */
+ GATE_PERAO1(CLK_PERAO_SSUSB0_REF, "perao_ssusb0_ref", "usb2_26m_p0_en", 1),
+ GATE_PERAO1(CLK_PERAO_SSUSB0_FRMCNT, "perao_ssusb0_frmcnt", "fmcnt_p0_en", 2),
+ GATE_PERAO1(CLK_PERAO_SSUSB0_SYS, "perao_ssusb0_sys", "usb_p0_sel", 4),
+ GATE_PERAO1(CLK_PERAO_SSUSB0_XHCI, "perao_ssusb0_xhci", "ssusb_xhci_p0_sel", 5),
+ GATE_PERAO1(CLK_PERAO_SSUSB0_F, "perao_ssusb0_f", "axi_peri_sel", 6),
+ GATE_PERAO1(CLK_PERAO_SSUSB0_H, "perao_ssusb0_h", "axi_peri_sel", 7),
+ GATE_PERAO1(CLK_PERAO_SSUSB1_REF, "perao_ssusb1_ref", "usb2_26m_p1_en", 8),
+ GATE_PERAO1(CLK_PERAO_SSUSB1_FRMCNT, "perao_ssusb1_frmcnt", "fmcnt_p1_en", 9),
+ GATE_PERAO1(CLK_PERAO_SSUSB1_SYS, "perao_ssusb1_sys", "usb_p1_sel", 11),
+ GATE_PERAO1(CLK_PERAO_SSUSB1_XHCI, "perao_ssusb1_xhci", "ssusb_xhci_p1_sel", 12),
+ GATE_PERAO1(CLK_PERAO_SSUSB1_F, "perao_ssusb1_f", "axi_peri_sel", 13),
+ GATE_PERAO1(CLK_PERAO_SSUSB1_H, "perao_ssusb1_h", "axi_peri_sel", 14),
+ GATE_PERAO1(CLK_PERAO_SSUSB2_REF, "perao_ssusb2_ref", "usb2_26m_p2_en", 15),
+ GATE_PERAO1(CLK_PERAO_SSUSB2_FRMCNT, "perao_ssusb2_frmcnt", "fmcnt_p2_en", 16),
+ GATE_PERAO1(CLK_PERAO_SSUSB2_SYS, "perao_ssusb2_sys", "usb_p2_sel", 18),
+ GATE_PERAO1(CLK_PERAO_SSUSB2_XHCI, "perao_ssusb2_xhci", "ssusb_xhci_p2_sel", 19),
+ GATE_PERAO1(CLK_PERAO_SSUSB2_F, "perao_ssusb2_f", "axi_peri_sel", 20),
+ GATE_PERAO1(CLK_PERAO_SSUSB2_H, "perao_ssusb2_h", "axi_peri_sel", 21),
+ GATE_PERAO1(CLK_PERAO_SSUSB3_REF, "perao_ssusb3_ref", "usb2_26m_p3_en", 23),
+ GATE_PERAO1(CLK_PERAO_SSUSB3_FRMCNT, "perao_ssusb3_frmcnt", "fmcnt_p3_en", 24),
+ GATE_PERAO1(CLK_PERAO_SSUSB3_SYS, "perao_ssusb3_sys", "usb_p3_sel", 26),
+ GATE_PERAO1(CLK_PERAO_SSUSB3_XHCI, "perao_ssusb3_xhci", "ssusb_xhci_p3_sel", 27),
+ GATE_PERAO1(CLK_PERAO_SSUSB3_F, "perao_ssusb3_f", "axi_peri_sel", 28),
+ GATE_PERAO1(CLK_PERAO_SSUSB3_H, "perao_ssusb3_h", "axi_peri_sel", 29),
+ /* PERAO2 */
+ GATE_PERAO2(CLK_PERAO_SSUSB4_REF, "perao_ssusb4_ref", "usb2_26m_p4_en", 0),
+ GATE_PERAO2(CLK_PERAO_SSUSB4_FRMCNT, "perao_ssusb4_frmcnt", "fmcnt_p4_en", 1),
+ GATE_PERAO2(CLK_PERAO_SSUSB4_SYS, "perao_ssusb4_sys", "usb_p4_sel", 3),
+ GATE_PERAO2(CLK_PERAO_SSUSB4_XHCI, "perao_ssusb4_xhci", "ssusb_xhci_p4_sel", 4),
+ GATE_PERAO2(CLK_PERAO_SSUSB4_F, "perao_ssusb4_f", "axi_peri_sel", 5),
+ GATE_PERAO2(CLK_PERAO_SSUSB4_H, "perao_ssusb4_h", "axi_peri_sel", 6),
+ GATE_PERAO2(CLK_PERAO_MSDC0, "perao_msdc0", "msdc50_0_sel", 7),
+ GATE_PERAO2(CLK_PERAO_MSDC0_H, "perao_msdc0_h", "msdc5hclk_sel", 8),
+ GATE_PERAO2(CLK_PERAO_MSDC0_FAES, "perao_msdc0_faes", "aes_msdcfde_sel", 9),
+ GATE_PERAO2(CLK_PERAO_MSDC0_MST_F, "perao_msdc0_mst_f", "axi_peri_sel", 10),
+ GATE_PERAO2(CLK_PERAO_MSDC0_SLV_H, "perao_msdc0_slv_h", "axi_peri_sel", 11),
+ GATE_PERAO2(CLK_PERAO_MSDC1, "perao_msdc1", "msdc30_1_sel", 12),
+ GATE_PERAO2(CLK_PERAO_MSDC1_H, "perao_msdc1_h", "msdc30_1_h_sel", 13),
+ GATE_PERAO2(CLK_PERAO_MSDC1_MST_F, "perao_msdc1_mst_f", "axi_peri_sel", 14),
+ GATE_PERAO2(CLK_PERAO_MSDC1_SLV_H, "perao_msdc1_slv_h", "axi_peri_sel", 15),
+ GATE_PERAO2(CLK_PERAO_MSDC2, "perao_msdc2", "msdc30_2_sel", 16),
+ GATE_PERAO2(CLK_PERAO_MSDC2_H, "perao_msdc2_h", "msdc30_2_h_sel", 17),
+ GATE_PERAO2(CLK_PERAO_MSDC2_MST_F, "perao_msdc2_mst_f", "axi_peri_sel", 18),
+ GATE_PERAO2(CLK_PERAO_MSDC2_SLV_H, "perao_msdc2_slv_h", "axi_peri_sel", 19),
+ GATE_PERAO2(CLK_PERAO_SFLASH, "perao_sflash", "sflash_sel", 20),
+ GATE_PERAO2(CLK_PERAO_SFLASH_F, "perao_sflash_f", "axi_peri_sel", 21),
+ GATE_PERAO2(CLK_PERAO_SFLASH_H, "perao_sflash_h", "axi_peri_sel", 22),
+ GATE_PERAO2(CLK_PERAO_SFLASH_P, "perao_sflash_p", "axi_peri_sel", 23),
+ GATE_PERAO2(CLK_PERAO_AUDIO0, "perao_audio0", "axi_peri_sel", 24),
+ GATE_PERAO2(CLK_PERAO_AUDIO1, "perao_audio1", "axi_peri_sel", 25),
+ GATE_PERAO2(CLK_PERAO_AUDIO2, "perao_audio2", "aud_intbus_sel", 26),
+ GATE_PERAO2(CLK_PERAO_AUXADC_26M, "perao_auxadc_26m", "clk26m", 27),
+};
+
+static const struct mtk_clk_desc perao_mcd = {
+ .clks = perao_clks,
+ .num_clks = ARRAY_SIZE(perao_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8189_bus[] = {
+ { .compatible = "mediatek,mt8189-infra-ao", .data = &ifrao_mcd },
+ { .compatible = "mediatek,mt8189-peri-ao", .data = &perao_mcd },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, of_match_clk_mt8189_bus);
+
+static struct platform_driver clk_mt8189_bus_drv = {
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
+ .driver = {
+ .name = "clk-mt8189-bus",
+ .of_match_table = of_match_clk_mt8189_bus,
+ },
+};
+module_platform_driver(clk_mt8189_bus_drv);
+
+MODULE_DESCRIPTION("MediaTek MT8189 bus/peripheral clocks driver");
+MODULE_LICENSE("GPL");
--
2.54.0
^ permalink raw reply related
* [PATCH 12/15] clk: mediatek: Add MT8189 dvfsrc clock support
From: Louis-Alexis Eyraud @ 2026-07-01 13:11 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Brian Masney, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chun-Jie Chen, Philipp Zabel,
Edward-JW Yang, Richard Cochran
Cc: kernel, linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Irving-CH Lin, Louis-Alexis Eyraud
In-Reply-To: <20260701-mt8189-clocks-system-base-v1-0-2b048feea50a@collabora.com>
Add support for the MT8189 dvfsrc clock controller,
which provides clock gate control for dram dvfs.
Co-developed-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
Signed-off-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
Co-developed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
drivers/clk/mediatek/Kconfig | 10 ++++++
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8189-dvfsrc.c | 58 ++++++++++++++++++++++++++++++++
3 files changed, 69 insertions(+)
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 635b0109ec07..245d3b83b5d3 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -849,6 +849,16 @@ config COMMON_CLK_MT8189_DBGAO
vcore debug system clocks. If you want to control its clocks, say Y or M
to include this driver in your kernel build.
+config COMMON_CLK_MT8189_DVFSRC
+ tristate "Clock driver for MediaTek MT8189 dvfsrc"
+ depends on COMMON_CLK_MT8189
+ default COMMON_CLK_MT8189
+ help
+ Enable this to support the clock management for the dvfsrc
+ on MediaTek MT8189 SoCs. This includes enabling and disabling
+ vcore dvfs clocks. If you want to control its clocks, say Y or M
+ to include this driver in your kernel build.
+
config COMMON_CLK_MT8192
tristate "Clock driver for MediaTek MT8192"
depends on ARM64 || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 6ab6df7ebf2a..4dbfc9ac83ba 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -127,6 +127,7 @@ obj-$(CONFIG_COMMON_CLK_MT8189) += clk-mt8189-apmixedsys.o clk-mt8189-topckgen.o
clk-mt8189-vlpckgen.o clk-mt8189-vlpcfg.o
obj-$(CONFIG_COMMON_CLK_MT8189_BUS) += clk-mt8189-bus.o
obj-$(CONFIG_COMMON_CLK_MT8189_DBGAO) += clk-mt8189-dbgao.o
+obj-$(CONFIG_COMMON_CLK_MT8189_DVFSRC) += clk-mt8189-dvfsrc.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192-apmixedsys.o clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8189-dvfsrc.c b/drivers/clk/mediatek/clk-mt8189-dvfsrc.c
new file mode 100644
index 000000000000..37b81dc0b882
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8189-dvfsrc.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025-2026 MediaTek Inc.
+ * Qiqi Wang <qiqi.wang@mediatek.com>
+ * Irving-CH Lin <irving-ch.lin@mediatek.com>
+ * Copyright (C) 2026 Collabora Ltd.
+ * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ * Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mediatek,mt8189-clk.h>
+
+static const struct mtk_gate_regs dvfsrc_top_cg_regs = {
+ .set_ofs = 0x0,
+ .clr_ofs = 0x0,
+ .sta_ofs = 0x0,
+};
+
+#define GATE_DVFSRC_TOP_FLAGS(_id, _name, _parent, _shift, _flags) \
+ GATE_MTK_FLAGS(_id, _name, _parent, &dvfsrc_top_cg_regs, _shift, \
+ &mtk_clk_gate_ops_no_setclr_inv, _flags)
+
+static const struct mtk_gate dvfsrc_top_clks[] = {
+ GATE_DVFSRC_TOP_FLAGS(CLK_DVFSRC_TOP_DVFSRC_EN, "dvfsrc_dvfsrc_en",
+ "clk26m", 0, CLK_IS_CRITICAL),
+};
+
+static const struct mtk_clk_desc dvfsrc_top_mcd = {
+ .clks = dvfsrc_top_clks,
+ .num_clks = ARRAY_SIZE(dvfsrc_top_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8189_dvfsrc[] = {
+ { .compatible = "mediatek,mt8189-dvfsrc-top", .data = &dvfsrc_top_mcd },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, of_match_clk_mt8189_dvfsrc);
+
+static struct platform_driver clk_mt8189_dvfsrc_drv = {
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
+ .driver = {
+ .name = "clk-mt8189-dvfsrc",
+ .of_match_table = of_match_clk_mt8189_dvfsrc,
+ },
+};
+module_platform_driver(clk_mt8189_dvfsrc_drv);
+
+MODULE_DESCRIPTION("MediaTek MT8189 dvfsrc clocks driver");
+MODULE_LICENSE("GPL");
--
2.54.0
^ permalink raw reply related
* [PATCH 11/15] clk: mediatek: Add MT8189 dbgao clock support
From: Louis-Alexis Eyraud @ 2026-07-01 13:11 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Brian Masney, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chun-Jie Chen, Philipp Zabel,
Edward-JW Yang, Richard Cochran
Cc: kernel, linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Irving-CH Lin, Louis-Alexis Eyraud
In-Reply-To: <20260701-mt8189-clocks-system-base-v1-0-2b048feea50a@collabora.com>
Add support for the MT8189 dbgao clock controller,
which provides clock gate control for debug-system.
Co-developed-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
Signed-off-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
Co-developed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
drivers/clk/mediatek/Kconfig | 10 ++++
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8189-dbgao.c | 98 +++++++++++++++++++++++++++++++++
3 files changed, 109 insertions(+)
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 8eba45f05968..635b0109ec07 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -839,6 +839,16 @@ config COMMON_CLK_MT8189_BUS
MT8189 chipset, ensuring that all bus-related components receive the
correct clock signals for optimal performance.
+config COMMON_CLK_MT8189_DBGAO
+ tristate "Clock driver for MediaTek MT8189 debug ao"
+ depends on COMMON_CLK_MT8189
+ default COMMON_CLK_MT8189
+ help
+ Enable this to support the clock management for the debug function
+ on MediaTek MT8189 SoCs. This includes enabling and disabling
+ vcore debug system clocks. If you want to control its clocks, say Y or M
+ to include this driver in your kernel build.
+
config COMMON_CLK_MT8192
tristate "Clock driver for MediaTek MT8192"
depends on ARM64 || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index aabfb42cb1b2..6ab6df7ebf2a 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -126,6 +126,7 @@ obj-$(CONFIG_COMMON_CLK_MT8188_WPESYS) += clk-mt8188-wpe.o
obj-$(CONFIG_COMMON_CLK_MT8189) += clk-mt8189-apmixedsys.o clk-mt8189-topckgen.o \
clk-mt8189-vlpckgen.o clk-mt8189-vlpcfg.o
obj-$(CONFIG_COMMON_CLK_MT8189_BUS) += clk-mt8189-bus.o
+obj-$(CONFIG_COMMON_CLK_MT8189_DBGAO) += clk-mt8189-dbgao.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192-apmixedsys.o clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8189-dbgao.c b/drivers/clk/mediatek/clk-mt8189-dbgao.c
new file mode 100644
index 000000000000..40307bdc93eb
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8189-dbgao.c
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025-2026 MediaTek Inc.
+ * Qiqi Wang <qiqi.wang@mediatek.com>
+ * Irving-CH Lin <irving-ch.lin@mediatek.com>
+ * Copyright (C) 2026 Collabora Ltd.
+ * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ * Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mediatek,mt8189-clk.h>
+
+static const struct mtk_gate_regs dbgao_cg_regs = {
+ .set_ofs = 0x70,
+ .clr_ofs = 0x70,
+ .sta_ofs = 0x70,
+};
+
+#define GATE_DBGAO(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &dbgao_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
+
+static const struct mtk_gate dbgao_clks[] = {
+ GATE_DBGAO(CLK_DBGAO_ATB_EN, "dbgao_atb_en", "atb_sel", 0),
+};
+
+static const struct mtk_clk_desc dbgao_mcd = {
+ .clks = dbgao_clks,
+ .num_clks = ARRAY_SIZE(dbgao_clks),
+};
+
+static const struct mtk_gate_regs dem0_cg_regs = {
+ .set_ofs = 0x2c,
+ .clr_ofs = 0x2c,
+ .sta_ofs = 0x2c,
+};
+
+static const struct mtk_gate_regs dem1_cg_regs = {
+ .set_ofs = 0x30,
+ .clr_ofs = 0x30,
+ .sta_ofs = 0x30,
+};
+
+static const struct mtk_gate_regs dem2_cg_regs = {
+ .set_ofs = 0x70,
+ .clr_ofs = 0x70,
+ .sta_ofs = 0x70,
+};
+
+#define GATE_DEM0(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &dem0_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
+
+#define GATE_DEM1(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &dem1_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
+
+#define GATE_DEM2(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &dem2_cg_regs, _shift, &mtk_clk_gate_ops_no_setclr_inv)
+
+static const struct mtk_gate dem_clks[] = {
+ /* DEM0 */
+ GATE_DEM0(CLK_DEM_BUSCLK_EN, "dem_busclk_en", "axi_sel", 0),
+ /* DEM1 */
+ GATE_DEM1(CLK_DEM_SYSCLK_EN, "dem_sysclk_en", "axi_sel", 0),
+ /* DEM2 */
+ GATE_DEM2(CLK_DEM_ATB_EN, "dem_atb_en", "atb_sel", 0),
+};
+
+static const struct mtk_clk_desc dem_mcd = {
+ .clks = dem_clks,
+ .num_clks = ARRAY_SIZE(dem_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8189_dbgao[] = {
+ { .compatible = "mediatek,mt8189-dbg-ao", .data = &dbgao_mcd },
+ { .compatible = "mediatek,mt8189-dem", .data = &dem_mcd },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, of_match_clk_mt8189_dbgao);
+
+static struct platform_driver clk_mt8189_dbgao_drv = {
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
+ .driver = {
+ .name = "clk-mt8189-dbgao",
+ .of_match_table = of_match_clk_mt8189_dbgao,
+ },
+};
+module_platform_driver(clk_mt8189_dbgao_drv);
+
+MODULE_DESCRIPTION("MediaTek MT8189 dbgao system clocks driver");
+MODULE_LICENSE("GPL");
--
2.54.0
^ permalink raw reply related
* [PATCH 14/15] clk: mediatek: Add MT8189 scp clock support
From: Louis-Alexis Eyraud @ 2026-07-01 13:11 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Brian Masney, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chun-Jie Chen, Philipp Zabel,
Edward-JW Yang, Richard Cochran
Cc: kernel, linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Irving-CH Lin, Louis-Alexis Eyraud
In-Reply-To: <20260701-mt8189-clocks-system-base-v1-0-2b048feea50a@collabora.com>
Add support for the MT8189 scp clock controller,
which provides clock gate control for System Control Processor.
Co-developed-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
Signed-off-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
Co-developed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
drivers/clk/mediatek/Kconfig | 10 +++++
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8189-scp.c | 77 +++++++++++++++++++++++++++++++++++
3 files changed, 88 insertions(+)
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index bba631138b07..919a916f1f4f 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -872,6 +872,16 @@ config COMMON_CLK_MT8189_IIC
the MT8189 chipset, improving the overall performance and power
efficiency of the device.
+config COMMON_CLK_MT8189_SCP
+ tristate "Clock driver for MediaTek MT8189 scp"
+ depends on COMMON_CLK_MT8189
+ default COMMON_CLK_MT8189
+ help
+ Enable this to support the clock framework for the System Control
+ Processor (SCP) in the MediaTek MT8189 SoC. This includes clock
+ management for SCP-related features, ensuring proper clock
+ distribution and gating for power efficiency and functionality.
+
config COMMON_CLK_MT8192
tristate "Clock driver for MediaTek MT8192"
depends on ARM64 || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index bfc075023d9b..a3a93a16b369 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -129,6 +129,7 @@ obj-$(CONFIG_COMMON_CLK_MT8189_BUS) += clk-mt8189-bus.o
obj-$(CONFIG_COMMON_CLK_MT8189_DBGAO) += clk-mt8189-dbgao.o
obj-$(CONFIG_COMMON_CLK_MT8189_DVFSRC) += clk-mt8189-dvfsrc.o
obj-$(CONFIG_COMMON_CLK_MT8189_IIC) += clk-mt8189-iic.o
+obj-$(CONFIG_COMMON_CLK_MT8189_SCP) += clk-mt8189-scp.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192-apmixedsys.o clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8189-scp.c b/drivers/clk/mediatek/clk-mt8189-scp.c
new file mode 100644
index 000000000000..75197cd98b52
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8189-scp.c
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025-2026 MediaTek Inc.
+ * Qiqi Wang <qiqi.wang@mediatek.com>
+ * Irving-CH Lin <irving-ch.lin@mediatek.com>
+ * Copyright (C) 2026 Collabora Ltd.
+ * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ * Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mediatek,mt8189-clk.h>
+
+static const struct mtk_gate_regs scp_cg_regs = {
+ .set_ofs = 0x4,
+ .clr_ofs = 0x8,
+ .sta_ofs = 0x4,
+};
+
+#define GATE_SCP(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &scp_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
+
+static const struct mtk_gate scp_clks[] = {
+ GATE_SCP(CLK_SCP_SET_SPI0, "scp_set_spi0", "clk26m", 0),
+ GATE_SCP(CLK_SCP_SET_SPI1, "scp_set_spi1", "clk26m", 1),
+};
+
+static const struct mtk_clk_desc scp_mcd = {
+ .clks = scp_clks,
+ .num_clks = ARRAY_SIZE(scp_clks),
+};
+
+static const struct mtk_gate_regs scp_iic_cg_regs = {
+ .set_ofs = 0x8,
+ .clr_ofs = 0x4,
+ .sta_ofs = 0x0,
+};
+
+#define GATE_SCP_IIC(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &scp_iic_cg_regs, _shift, &mtk_clk_gate_ops_setclr_inv)
+
+static const struct mtk_gate scp_iic_clks[] = {
+ GATE_SCP_IIC(CLK_SCP_IIC_I2C0_W1S, "scp_iic_i2c0_w1s", "vlp_scp_iic_sel", 0),
+ GATE_SCP_IIC(CLK_SCP_IIC_I2C1_W1S, "scp_iic_i2c1_w1s", "vlp_scp_iic_sel", 1),
+};
+
+static const struct mtk_clk_desc scp_iic_mcd = {
+ .clks = scp_iic_clks,
+ .num_clks = ARRAY_SIZE(scp_iic_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8189_scp[] = {
+ { .compatible = "mediatek,mt8189-scp-clk", .data = &scp_mcd },
+ { .compatible = "mediatek,mt8189-scp-i2c-clk", .data = &scp_iic_mcd },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, of_match_clk_mt8189_scp);
+
+static struct platform_driver clk_mt8189_scp_drv = {
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
+ .driver = {
+ .name = "clk-mt8189-scp",
+ .of_match_table = of_match_clk_mt8189_scp,
+ },
+};
+module_platform_driver(clk_mt8189_scp_drv);
+
+MODULE_DESCRIPTION("MediaTek MT8189 scp clocks driver");
+MODULE_LICENSE("GPL");
--
2.54.0
^ permalink raw reply related
* [PATCH 13/15] clk: mediatek: Add MT8189 i2c clock support
From: Louis-Alexis Eyraud @ 2026-07-01 13:11 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Brian Masney, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chun-Jie Chen, Philipp Zabel,
Edward-JW Yang, Richard Cochran
Cc: kernel, linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Irving-CH Lin, Louis-Alexis Eyraud
In-Reply-To: <20260701-mt8189-clocks-system-base-v1-0-2b048feea50a@collabora.com>
Add support for the MT8189 i2c clock controller,
which provides clock gate control for i2c.
Co-developed-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
Signed-off-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
Co-developed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
drivers/clk/mediatek/Kconfig | 13 ++++
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8189-iic.c | 122 ++++++++++++++++++++++++++++++++++
3 files changed, 136 insertions(+)
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 245d3b83b5d3..bba631138b07 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -859,6 +859,19 @@ config COMMON_CLK_MT8189_DVFSRC
vcore dvfs clocks. If you want to control its clocks, say Y or M
to include this driver in your kernel build.
+config COMMON_CLK_MT8189_IIC
+ tristate "Clock driver for MediaTek MT8189 iic"
+ depends on COMMON_CLK_MT8189
+ default COMMON_CLK_MT8189
+ help
+ Enable this option to support the clock framework for MediaTek MT8189
+ integrated circuits (iic). This driver is responsible for managing
+ clock sources, dividers, and gates specifically designed for MT8189
+ SoCs. Enabling this driver ensures that the system can correctly
+ manage clock frequencies and power for various components within
+ the MT8189 chipset, improving the overall performance and power
+ efficiency of the device.
+
config COMMON_CLK_MT8192
tristate "Clock driver for MediaTek MT8192"
depends on ARM64 || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 4dbfc9ac83ba..bfc075023d9b 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -128,6 +128,7 @@ obj-$(CONFIG_COMMON_CLK_MT8189) += clk-mt8189-apmixedsys.o clk-mt8189-topckgen.o
obj-$(CONFIG_COMMON_CLK_MT8189_BUS) += clk-mt8189-bus.o
obj-$(CONFIG_COMMON_CLK_MT8189_DBGAO) += clk-mt8189-dbgao.o
obj-$(CONFIG_COMMON_CLK_MT8189_DVFSRC) += clk-mt8189-dvfsrc.o
+obj-$(CONFIG_COMMON_CLK_MT8189_IIC) += clk-mt8189-iic.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192-apmixedsys.o clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8189-iic.c b/drivers/clk/mediatek/clk-mt8189-iic.c
new file mode 100644
index 000000000000..80a01706791a
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8189-iic.c
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025-2026 MediaTek Inc.
+ * Qiqi Wang <qiqi.wang@mediatek.com>
+ * Irving-CH Lin <irving-ch.lin@mediatek.com>
+ * Copyright (C) 2026 Collabora Ltd.
+ * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ * Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mediatek,mt8189-clk.h>
+
+static const struct mtk_gate_regs impe_cg_regs = {
+ .set_ofs = 0x8,
+ .clr_ofs = 0x4,
+ .sta_ofs = 0x0,
+};
+
+#define GATE_IMPE(_id, _name, _parent, _shift) \
+ GATE_MTK_FLAGS(_id, _name, _parent, &impe_cg_regs, _shift, \
+ &mtk_clk_gate_ops_setclr, CLK_OPS_PARENT_ENABLE)
+
+static const struct mtk_gate impe_clks[] = {
+ GATE_IMPE(CLK_IMPE_I2C0, "impe_i2c0", "i2c_sel", 0),
+ GATE_IMPE(CLK_IMPE_I2C1, "impe_i2c1", "i2c_sel", 1),
+};
+
+static const struct mtk_clk_desc impe_mcd = {
+ .clks = impe_clks,
+ .num_clks = ARRAY_SIZE(impe_clks),
+};
+
+static const struct mtk_gate_regs impen_cg_regs = {
+ .set_ofs = 0x8,
+ .clr_ofs = 0x4,
+ .sta_ofs = 0x0,
+};
+
+#define GATE_IMPEN(_id, _name, _parent, _shift) \
+ GATE_MTK_FLAGS(_id, _name, _parent, &impen_cg_regs, _shift, \
+ &mtk_clk_gate_ops_setclr, CLK_OPS_PARENT_ENABLE)
+
+static const struct mtk_gate impen_clks[] = {
+ GATE_IMPEN(CLK_IMPEN_I2C7, "impen_i2c7", "i2c_sel", 0),
+ GATE_IMPEN(CLK_IMPEN_I2C8, "impen_i2c8", "i2c_sel", 1),
+};
+
+static const struct mtk_clk_desc impen_mcd = {
+ .clks = impen_clks,
+ .num_clks = ARRAY_SIZE(impen_clks),
+};
+
+static const struct mtk_gate_regs imps_cg_regs = {
+ .set_ofs = 0x8,
+ .clr_ofs = 0x4,
+ .sta_ofs = 0x0,
+};
+
+#define GATE_IMPS(_id, _name, _parent, _shift) \
+ GATE_MTK_FLAGS(_id, _name, _parent, &imps_cg_regs, _shift, \
+ &mtk_clk_gate_ops_setclr, CLK_OPS_PARENT_ENABLE)
+
+static const struct mtk_gate imps_clks[] = {
+ GATE_IMPS(CLK_IMPS_I2C3, "imps_i2c3", "i2c_sel", 0),
+ GATE_IMPS(CLK_IMPS_I2C4, "imps_i2c4", "i2c_sel", 1),
+ GATE_IMPS(CLK_IMPS_I2C5, "imps_i2c5", "i2c_sel", 2),
+ GATE_IMPS(CLK_IMPS_I2C6, "imps_i2c6", "i2c_sel", 3),
+};
+
+static const struct mtk_clk_desc imps_mcd = {
+ .clks = imps_clks,
+ .num_clks = ARRAY_SIZE(imps_clks),
+};
+
+static const struct mtk_gate_regs impws_cg_regs = {
+ .set_ofs = 0x8,
+ .clr_ofs = 0x4,
+ .sta_ofs = 0x0,
+};
+
+#define GATE_IMPWS(_id, _name, _parent, _shift) \
+ GATE_MTK_FLAGS(_id, _name, _parent, &impws_cg_regs, _shift, \
+ &mtk_clk_gate_ops_setclr, CLK_OPS_PARENT_ENABLE)
+
+static const struct mtk_gate impws_clks[] = {
+ GATE_IMPWS(CLK_IMPWS_I2C2, "impws_i2c2", "i2c_sel", 0),
+};
+
+static const struct mtk_clk_desc impws_mcd = {
+ .clks = impws_clks,
+ .num_clks = ARRAY_SIZE(impws_clks),
+};
+
+static const struct of_device_id of_match_clk_mt8189_iic[] = {
+ { .compatible = "mediatek,mt8189-iic-wrap-e", .data = &impe_mcd },
+ { .compatible = "mediatek,mt8189-iic-wrap-en", .data = &impen_mcd },
+ { .compatible = "mediatek,mt8189-iic-wrap-s", .data = &imps_mcd },
+ { .compatible = "mediatek,mt8189-iic-wrap-ws", .data = &impws_mcd },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, of_match_clk_mt8189_iic);
+
+static struct platform_driver clk_mt8189_iic_drv = {
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
+ .driver = {
+ .name = "clk-mt8189-iic",
+ .of_match_table = of_match_clk_mt8189_iic,
+ },
+};
+module_platform_driver(clk_mt8189_iic_drv);
+
+MODULE_DESCRIPTION("MediaTek MT8189 iic clocks driver");
+MODULE_LICENSE("GPL");
--
2.54.0
^ permalink raw reply related
* [PATCH 15/15] clk: mediatek: Add MT8189 ufs clock support
From: Louis-Alexis Eyraud @ 2026-07-01 13:11 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Brian Masney, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chun-Jie Chen, Philipp Zabel,
Edward-JW Yang, Richard Cochran
Cc: kernel, linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Irving-CH Lin, Louis-Alexis Eyraud
In-Reply-To: <20260701-mt8189-clocks-system-base-v1-0-2b048feea50a@collabora.com>
Add support for the MT8189 ufs clock controller,
which provides clock gate control for Universal Flash Storage.
Co-developed-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
Signed-off-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
Co-developed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
drivers/clk/mediatek/Kconfig | 12 +++
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt8189-ufs.c | 133 ++++++++++++++++++++++++++++++++++
3 files changed, 146 insertions(+)
diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index 919a916f1f4f..34a270a377cc 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -882,6 +882,18 @@ config COMMON_CLK_MT8189_SCP
management for SCP-related features, ensuring proper clock
distribution and gating for power efficiency and functionality.
+config COMMON_CLK_MT8189_UFS
+ tristate "Clock driver for MediaTek MT8189 ufs"
+ depends on COMMON_CLK_MT8189
+ default COMMON_CLK_MT8189
+ help
+ Enable this to support the clock management for the Universal Flash
+ Storage (UFS) interface on MediaTek MT8189 SoCs. This includes
+ clock sources, dividers, and gates that are specific to the UFS
+ feature of the MT8189 platform. It is recommended to enable this
+ option if the system includes a UFS device that relies on the MT8189
+ SoC for clock management.
+
config COMMON_CLK_MT8192
tristate "Clock driver for MediaTek MT8192"
depends on ARM64 || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index a3a93a16b369..1aa9f4265225 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -130,6 +130,7 @@ obj-$(CONFIG_COMMON_CLK_MT8189_DBGAO) += clk-mt8189-dbgao.o
obj-$(CONFIG_COMMON_CLK_MT8189_DVFSRC) += clk-mt8189-dvfsrc.o
obj-$(CONFIG_COMMON_CLK_MT8189_IIC) += clk-mt8189-iic.o
obj-$(CONFIG_COMMON_CLK_MT8189_SCP) += clk-mt8189-scp.o
+obj-$(CONFIG_COMMON_CLK_MT8189_UFS) += clk-mt8189-ufs.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192-apmixedsys.o clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8189-ufs.c b/drivers/clk/mediatek/clk-mt8189-ufs.c
new file mode 100644
index 000000000000..85afab04420f
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8189-ufs.c
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025-2026 MediaTek Inc.
+ * Qiqi Wang <qiqi.wang@mediatek.com>
+ * Irving-CH Lin <irving-ch.lin@mediatek.com>
+ * Copyright (C) 2026 Collabora Ltd.
+ * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ * Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-mtk.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mediatek,mt8189-clk.h>
+#include <dt-bindings/reset/mediatek,mt8189-resets.h>
+
+#define MT8189_UFSCFG_AO_RST0_SET_OFFSET 0x48
+#define MT8189_UFSCFG_PDN_RST0_SET_OFFSET 0x48
+
+static const struct mtk_gate_regs ufscfg_ao_reg_cg_regs = {
+ .set_ofs = 0x8,
+ .clr_ofs = 0xc,
+ .sta_ofs = 0x4,
+};
+
+#define GATE_UFSCFG_AO_REG(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &ufscfg_ao_reg_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+static const struct mtk_gate ufscfg_ao_reg_clks[] = {
+ GATE_UFSCFG_AO_REG(CLK_UFSCFG_AO_REG_UNIPRO_TX_SYM,
+ "ufscfg_ao_unipro_tx_sym", "clk26m", 1),
+ GATE_UFSCFG_AO_REG(CLK_UFSCFG_AO_REG_UNIPRO_RX_SYM0,
+ "ufscfg_ao_unipro_rx_sym0", "clk26m", 2),
+ GATE_UFSCFG_AO_REG(CLK_UFSCFG_AO_REG_UNIPRO_RX_SYM1,
+ "ufscfg_ao_unipro_rx_sym1", "clk26m", 3),
+ GATE_UFSCFG_AO_REG(CLK_UFSCFG_AO_REG_UNIPRO_SYS,
+ "ufscfg_ao_unipro_sys", "ufs_sel", 4),
+ GATE_UFSCFG_AO_REG(CLK_UFSCFG_AO_REG_U_SAP_CFG,
+ "ufscfg_ao_u_sap_cfg", "clk26m", 5),
+ GATE_UFSCFG_AO_REG(CLK_UFSCFG_AO_REG_U_PHY_TOP_AHB_S_BUS,
+ "ufscfg_ao_u_phy_ahb_s_bus", "axi_u_sel", 6),
+};
+
+static u16 ufscfg_ao_rst_ofs[] = {
+ MT8189_UFSCFG_AO_RST0_SET_OFFSET,
+};
+
+static u16 ufscfg_ao_rst_idx_map[] = {
+ [MT8189_UFSAO_RST_UFS_MPHY] = 8,
+};
+
+static const struct mtk_clk_rst_desc ufscfg_ao_rst_desc = {
+ .version = MTK_RST_SET_CLR,
+ .rst_bank_ofs = ufscfg_ao_rst_ofs,
+ .rst_bank_nr = ARRAY_SIZE(ufscfg_ao_rst_ofs),
+ .rst_idx_map = ufscfg_ao_rst_idx_map,
+ .rst_idx_map_nr = ARRAY_SIZE(ufscfg_ao_rst_idx_map),
+};
+
+static const struct mtk_clk_desc ufscfg_ao_reg_mcd = {
+ .clks = ufscfg_ao_reg_clks,
+ .num_clks = ARRAY_SIZE(ufscfg_ao_reg_clks),
+ .rst_desc = &ufscfg_ao_rst_desc,
+};
+
+static const struct mtk_gate_regs ufscfg_pdn_reg_cg_regs = {
+ .set_ofs = 0x8,
+ .clr_ofs = 0xc,
+ .sta_ofs = 0x4,
+};
+
+#define GATE_UFSCFG_PDN_REG(_id, _name, _parent, _shift) \
+ GATE_MTK(_id, _name, _parent, &ufscfg_pdn_reg_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
+
+static const struct mtk_gate ufscfg_pdn_reg_clks[] = {
+ GATE_UFSCFG_PDN_REG(CLK_UFSCFG_REG_UFSHCI_UFS,
+ "ufscfg_ufshci_ufs", "ufs_sel", 0),
+ GATE_UFSCFG_PDN_REG(CLK_UFSCFG_REG_UFSHCI_AES,
+ "ufscfg_ufshci_aes", "aes_ufsfde_sel", 1),
+ GATE_UFSCFG_PDN_REG(CLK_UFSCFG_REG_UFSHCI_U_AHB,
+ "ufscfg_ufshci_u_ahb", "axi_u_sel", 3),
+ GATE_UFSCFG_PDN_REG(CLK_UFSCFG_REG_UFSHCI_U_AXI,
+ "ufscfg_ufshci_u_axi", "mem_sub_u_sel", 5),
+};
+
+static u16 ufscfg_pdn_rst_ofs[] = {
+ MT8189_UFSCFG_PDN_RST0_SET_OFFSET,
+};
+
+static u16 ufscfg_pdn_rst_idx_map[] = {
+ [MT8189_UFSPDN_RST_UFS_UNIPRO] = 0,
+ [MT8189_UFSPDN_RST_UFS_CRYPTO] = 1,
+ [MT8189_UFSPDN_RST_UFS_HCI] = 2,
+};
+
+static const struct mtk_clk_rst_desc ufscfg_pdn_rst_desc = {
+ .version = MTK_RST_SET_CLR,
+ .rst_bank_ofs = ufscfg_pdn_rst_ofs,
+ .rst_bank_nr = ARRAY_SIZE(ufscfg_pdn_rst_ofs),
+ .rst_idx_map = ufscfg_pdn_rst_idx_map,
+ .rst_idx_map_nr = ARRAY_SIZE(ufscfg_pdn_rst_idx_map),
+};
+
+static const struct mtk_clk_desc ufscfg_pdn_reg_mcd = {
+ .clks = ufscfg_pdn_reg_clks,
+ .num_clks = ARRAY_SIZE(ufscfg_pdn_reg_clks),
+ .rst_desc = &ufscfg_pdn_rst_desc,
+};
+
+static const struct of_device_id of_match_clk_mt8189_ufs[] = {
+ { .compatible = "mediatek,mt8189-ufscfg-ao", .data = &ufscfg_ao_reg_mcd },
+ { .compatible = "mediatek,mt8189-ufscfg-pdn", .data = &ufscfg_pdn_reg_mcd },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, of_match_clk_mt8189_ufs);
+
+static struct platform_driver clk_mt8189_ufs_drv = {
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
+ .driver = {
+ .name = "clk-mt8189-ufs",
+ .of_match_table = of_match_clk_mt8189_ufs,
+ },
+};
+module_platform_driver(clk_mt8189_ufs_drv);
+
+MODULE_DESCRIPTION("MediaTek MT8189 ufs clocks driver");
+MODULE_LICENSE("GPL");
--
2.54.0
^ permalink raw reply related
* [PATCH v2 0/5] arm64: dts: describe the Lynx 10G and 28G SerDes blocks for Layerscape SoCs
From: Ioana Ciornei @ 2026-07-01 13:11 UTC (permalink / raw)
To: Frank.Li, robh, krzk+dt, conor+dt, devicetree
Cc: vladimir.oltean, linux-arm-kernel, linux-kernel, imx
This patch set adds the device tree nodes for the Lynx10G SerDes blocks
found on the LS1028A, LS1046A, LS1088A and LS2088A SoCs.
The first patch also transitions the LX2160A SoC dtsi to use the
device-specific Lynx28G SerDes compatible.
Changes in v2:
- Enable serdes_1 on all board DTs that has consumers for it.
- Use the proper name for serdes_3 in fsl-lx2162a.dtsi.
- Remove paragraph from commit message which mentioned some consumer
changes that are no longer needed nor part of the commit.
- Change the size of the SerDes region to 0x2000
Ioana Ciornei (1):
arm64: dts: ls1088a: describe the Lynx 10G SerDes blocks
Vladimir Oltean (4):
arm64: dts: lx2160a: transition to device-specific SerDes compatible
strings
arm64: dts: ls1028a: describe the Lynx 10G SerDes
arm64: dts: ls1046a: describe the Lynx 10G SerDes blocks
arm64: dts: ls208xa: describe the Lynx 10G SerDes blocks
.../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 29 ++++
.../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 60 +++++++
.../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 58 +++++++
.../arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 98 ++++++++++++
.../freescale/fsl-lx2160a-clearfog-itx.dtsi | 4 +
.../dts/freescale/fsl-lx2160a-half-twins.dts | 4 +
.../boot/dts/freescale/fsl-lx2160a-rdb.dts | 4 +
.../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 150 +++++++++++++++++-
.../dts/freescale/fsl-lx2162a-clearfog.dts | 6 +-
.../boot/dts/freescale/fsl-lx2162a-qds.dts | 2 +-
.../arm64/boot/dts/freescale/fsl-lx2162a.dtsi | 24 +++
11 files changed, 435 insertions(+), 4 deletions(-)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2162a.dtsi
--
2.25.1
^ permalink raw reply
* [PATCH v2 3/5] arm64: dts: ls1046a: describe the Lynx 10G SerDes blocks
From: Ioana Ciornei @ 2026-07-01 13:11 UTC (permalink / raw)
To: Frank.Li, robh, krzk+dt, conor+dt, devicetree
Cc: vladimir.oltean, linux-arm-kernel, linux-kernel, imx
In-Reply-To: <20260701131137.940145-1-ioana.ciornei@nxp.com>
From: Vladimir Oltean <vladimir.oltean@nxp.com>
Describe the two Lynx 10G SerDes blocks and their associated lanes found
on the LS1046A SoC. The nodes are left disabled at the SoC level; board
DTs will be expected to enable them once the consumer Ethernet nodes
appear.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v2:
- Change the size of the region to 0x2000
---
.../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 60 +++++++++++++++++++
1 file changed, 60 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 6fefe837f434..270a97711a69 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -424,6 +424,66 @@ sfp: efuse@1e80000 {
clock-names = "sfp";
};
+ serdes1: phy@1ea0000 {
+ compatible = "fsl,ls1046a-serdes1";
+ reg = <0x00 0x1ea0000 0x0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #phy-cells = <1>;
+ big-endian;
+ status = "disabled";
+
+ serdes1_lane_a: phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ serdes1_lane_b: phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+
+ serdes1_lane_c: phy@2 {
+ reg = <2>;
+ #phy-cells = <0>;
+ };
+
+ serdes1_lane_d: phy@3 {
+ reg = <3>;
+ #phy-cells = <0>;
+ };
+ };
+
+ serdes2: phy@1eb0000 {
+ compatible = "fsl,ls1046a-serdes2";
+ reg = <0x00 0x1eb0000 0x0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #phy-cells = <1>;
+ big-endian;
+ status = "disabled";
+
+ serdes2_lane_a: phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ serdes2_lane_b: phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+
+ serdes2_lane_c: phy@2 {
+ reg = <2>;
+ #phy-cells = <0>;
+ };
+
+ serdes2_lane_d: phy@3 {
+ reg = <3>;
+ #phy-cells = <0>;
+ };
+ };
+
dcfg: dcfg@1ee0000 {
compatible = "fsl,ls1046a-dcfg", "syscon";
reg = <0x0 0x1ee0000 0x0 0x1000>;
--
2.25.1
^ permalink raw reply related
* [PATCH v2 1/5] arm64: dts: lx2160a: transition to device-specific SerDes compatible strings
From: Ioana Ciornei @ 2026-07-01 13:11 UTC (permalink / raw)
To: Frank.Li, robh, krzk+dt, conor+dt, devicetree
Cc: vladimir.oltean, linux-arm-kernel, linux-kernel, imx
In-Reply-To: <20260701131137.940145-1-ioana.ciornei@nxp.com>
From: Vladimir Oltean <vladimir.oltean@nxp.com>
Align to the modern fsl,lynx-28g.yaml binding, where the SoC and SerDes
instance is present in the compatible string, to allow reliable per-lane
capability detection and per-lane customization of electrical properties.
The modern bindings are backward-incompatible with old kernels, due
to the consumer phandles being either in one form or in another, as
explained here:
https://lore.kernel.org/lkml/20250930140735.mvo3jii7wgmzh2bs@skbuf/
One of the major differences between the LX2160A and LX2162A is the
SerDes. So far, LX2162A has used fsl-lx2160a-rev2.dtsi, but we need to
split that up even further, and derive a fsl-lx2162a.dtsi which
overrides the SerDes properties.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v2:
- Enable serdes_1 on all board DTs that has consumers for it.
- Use the proper name for serdes_3 in fsl-lx2162a.dtsi.
- Remove paragraph from commit message which mentioned some consumer
changes that are no longer needed nor part of the commit.
---
.../freescale/fsl-lx2160a-clearfog-itx.dtsi | 4 +
.../dts/freescale/fsl-lx2160a-half-twins.dts | 4 +
.../boot/dts/freescale/fsl-lx2160a-rdb.dts | 4 +
.../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 150 +++++++++++++++++-
.../dts/freescale/fsl-lx2162a-clearfog.dts | 6 +-
.../boot/dts/freescale/fsl-lx2162a-qds.dts | 2 +-
.../arm64/boot/dts/freescale/fsl-lx2162a.dtsi | 24 +++
7 files changed, 190 insertions(+), 4 deletions(-)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2162a.dtsi
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
index 4bc151d721dd..1f946d3a4ec0 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-clearfog-itx.dtsi
@@ -135,6 +135,10 @@ &sata3 {
status = "okay";
};
+&serdes_1 {
+ status = "okay";
+};
+
&uart0 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-half-twins.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-half-twins.dts
index d16e27307275..954b9955b1b3 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-half-twins.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-half-twins.dts
@@ -805,6 +805,10 @@ &rgmii_phy1 {
status = "disabled";
};
+&serdes_1 {
+ status = "okay";
+};
+
&serdes_2 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 935f421475ac..a40a968b9533 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -329,6 +329,10 @@ &uart0 {
status = "okay";
};
+&serdes_1 {
+ status = "okay";
+};
+
&uart1 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index 1d73abffa6b7..a687eb3e3190 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -621,17 +621,163 @@ soc: soc {
ranges;
dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
+ /* Note on the interpretation of SerDes lane numbering from
+ * LX2160ARM lane mappings for RCW[SRDS_PRTCL_S1]:
+ * The letters (A-H) correspond to logical lane numbers in the
+ * SerDes register map (lane A's registers start with LNAGCR0),
+ * while the numbers (0-7) correspond to physical lanes as
+ * routed to pins. SerDes block #1 is flipped in the LX2160A
+ * floorplan (logical lane A goes to physical lane 7's pins),
+ * while SerDes blocks #2 and #3 are not. The lanes below are
+ * listed right to left when looking at that table.
+ * Both the numbers and the letters are according to the logical
+ * numbering scheme, and do not account for the flipping.
+ */
serdes_1: phy@1ea0000 {
- compatible = "fsl,lynx-28g";
+ compatible = "fsl,lx2160a-serdes1", "fsl,lynx-28g";
reg = <0x0 0x1ea0000 0x0 0x1e30>;
+ #address-cells = <1>;
+ #size-cells = <0>;
#phy-cells = <1>;
+ status = "disabled";
+
+ serdes_1_lane_a: phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ serdes_1_lane_b: phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+
+ serdes_1_lane_c: phy@2 {
+ reg = <2>;
+ #phy-cells = <0>;
+ };
+
+ serdes_1_lane_d: phy@3 {
+ reg = <3>;
+ #phy-cells = <0>;
+ };
+
+ serdes_1_lane_e: phy@4 {
+ reg = <4>;
+ #phy-cells = <0>;
+ };
+
+ serdes_1_lane_f: phy@5 {
+ reg = <5>;
+ #phy-cells = <0>;
+ };
+
+ serdes_1_lane_g: phy@6 {
+ reg = <6>;
+ #phy-cells = <0>;
+ };
+
+ serdes_1_lane_h: phy@7 {
+ reg = <7>;
+ #phy-cells = <0>;
+ };
};
serdes_2: phy@1eb0000 {
- compatible = "fsl,lynx-28g";
+ compatible = "fsl,lx2160a-serdes2", "fsl,lynx-28g";
reg = <0x0 0x1eb0000 0x0 0x1e30>;
+ #address-cells = <1>;
+ #size-cells = <0>;
#phy-cells = <1>;
status = "disabled";
+
+ serdes_2_lane_a: phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ serdes_2_lane_b: phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+
+ serdes_2_lane_c: phy@2 {
+ reg = <2>;
+ #phy-cells = <0>;
+ };
+
+ serdes_2_lane_d: phy@3 {
+ reg = <3>;
+ #phy-cells = <0>;
+ };
+
+ serdes_2_lane_e: phy@4 {
+ reg = <4>;
+ #phy-cells = <0>;
+ };
+
+ serdes_2_lane_f: phy@5 {
+ reg = <5>;
+ #phy-cells = <0>;
+ };
+
+ serdes_2_lane_g: phy@6 {
+ reg = <6>;
+ #phy-cells = <0>;
+ };
+
+ serdes_2_lane_h: phy@7 {
+ reg = <7>;
+ #phy-cells = <0>;
+ };
+ };
+
+ serdes_3: phy@1ec0000 {
+ compatible = "fsl,lx2160a-serdes3";
+ reg = <0x0 0x1ec0000 0x0 0x1e30>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ #phy-cells = <1>;
+
+ serdes_3_lane_a: phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ serdes_3_lane_b: phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+
+ serdes_3_lane_c: phy@2 {
+ reg = <2>;
+ #phy-cells = <0>;
+ };
+
+ serdes_3_lane_d: phy@3 {
+ reg = <3>;
+ #phy-cells = <0>;
+ };
+
+ serdes_3_lane_e: phy@4 {
+ reg = <4>;
+ #phy-cells = <0>;
+ };
+
+ serdes_3_lane_f: phy@5 {
+ reg = <5>;
+ #phy-cells = <0>;
+ };
+
+ serdes_3_lane_g: phy@6 {
+ reg = <6>;
+ #phy-cells = <0>;
+ };
+
+ serdes_3_lane_h: phy@7 {
+ reg = <7>;
+ #phy-cells = <0>;
+ };
};
crypto: crypto@8000000 {
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
index 99ee2b1c0f13..63f161610caa 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts
@@ -8,7 +8,7 @@
#include <dt-bindings/leds/common.h>
-#include "fsl-lx2160a-rev2.dtsi"
+#include "fsl-lx2162a.dtsi"
#include "fsl-lx2162a-sr-som.dtsi"
/ {
@@ -367,6 +367,10 @@ &pcs_mdio18 {
status = "okay";
};
+&serdes_1 {
+ status = "okay";
+};
+
&serdes_2 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts
index 7a595fddc027..0ba56b9819ac 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-qds.dts
@@ -6,7 +6,7 @@
/dts-v1/;
-#include "fsl-lx2160a-rev2.dtsi"
+#include "fsl-lx2162a.dtsi"
/ {
model = "NXP Layerscape LX2162AQDS";
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2162a.dtsi
new file mode 100644
index 000000000000..0e92ac6acd92
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+//
+// Device Tree Include file for Layerscape-LX2162A family SoC.
+//
+// Copyright 2025 NXP
+
+#include "fsl-lx2160a-rev2.dtsi"
+
+&serdes_1 {
+ compatible = "fsl,lx2162a-serdes1", "fsl,lynx-28g";
+
+ /delete-node/ phy@0;
+ /delete-node/ phy@1;
+ /delete-node/ phy@2;
+ /delete-node/ phy@3;
+};
+
+&serdes_2 {
+ compatible = "fsl,lx2162a-serdes2", "fsl,lynx-28g";
+};
+
+&soc {
+ /delete-node/ phy@1ec0000;
+};
--
2.25.1
^ permalink raw reply related
* [PATCH v2 4/5] arm64: dts: ls208xa: describe the Lynx 10G SerDes blocks
From: Ioana Ciornei @ 2026-07-01 13:11 UTC (permalink / raw)
To: Frank.Li, robh, krzk+dt, conor+dt, devicetree
Cc: vladimir.oltean, linux-arm-kernel, linux-kernel, imx
In-Reply-To: <20260701131137.940145-1-ioana.ciornei@nxp.com>
From: Vladimir Oltean <vladimir.oltean@nxp.com>
Describe the two Lynx 10G SerDes blocks and their associated lanes found
on the LS208xA SoC. The nodes are left disabled at the SoC level; board
DTs will enable them once there are consumers.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v2:
- Change the size of the region to 0x2000
---
.../arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 98 +++++++++++++++++++
1 file changed, 98 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
index 6073e426774a..cc1a64e63ed5 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -280,6 +280,104 @@ sfp: efuse@1e80000 {
clock-names = "sfp";
};
+ serdes1: phy@1ea0000 {
+ compatible = "fsl,ls2088a-serdes1";
+ reg = <0x00 0x1ea0000 0x0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #phy-cells = <1>;
+ status = "disabled";
+
+ serdes1_lane_a: phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ serdes1_lane_b: phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+
+ serdes1_lane_c: phy@2 {
+ reg = <2>;
+ #phy-cells = <0>;
+ };
+
+ serdes1_lane_d: phy@3 {
+ reg = <3>;
+ #phy-cells = <0>;
+ };
+
+ serdes1_lane_e: phy@4 {
+ reg = <4>;
+ #phy-cells = <0>;
+ };
+
+ serdes1_lane_f: phy@5 {
+ reg = <5>;
+ #phy-cells = <0>;
+ };
+
+ serdes1_lane_g: phy@6 {
+ reg = <6>;
+ #phy-cells = <0>;
+ };
+
+ serdes1_lane_h: phy@7 {
+ reg = <7>;
+ #phy-cells = <0>;
+ };
+ };
+
+ serdes2: phy@1eb0000 {
+ compatible = "fsl,ls2088a-serdes2";
+ reg = <0x00 0x1eb0000 0x0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #phy-cells = <1>;
+ status = "disabled";
+
+ serdes2_lane_a: phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ serdes2_lane_b: phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+
+ serdes2_lane_c: phy@2 {
+ reg = <2>;
+ #phy-cells = <0>;
+ };
+
+ serdes2_lane_d: phy@3 {
+ reg = <3>;
+ #phy-cells = <0>;
+ };
+
+ serdes2_lane_e: phy@4 {
+ reg = <4>;
+ #phy-cells = <0>;
+ };
+
+ serdes2_lane_f: phy@5 {
+ reg = <5>;
+ #phy-cells = <0>;
+ };
+
+ serdes2_lane_g: phy@6 {
+ reg = <6>;
+ #phy-cells = <0>;
+ };
+
+ serdes2_lane_h: phy@7 {
+ reg = <7>;
+ #phy-cells = <0>;
+ };
+ };
+
isc: syscon@1f70000 {
compatible = "fsl,ls2080a-isc", "syscon";
reg = <0x0 0x1f70000 0x0 0x10000>;
--
2.25.1
^ permalink raw reply related
* [PATCH v2 2/5] arm64: dts: ls1028a: describe the Lynx 10G SerDes
From: Ioana Ciornei @ 2026-07-01 13:11 UTC (permalink / raw)
To: Frank.Li, robh, krzk+dt, conor+dt, devicetree
Cc: vladimir.oltean, linux-arm-kernel, linux-kernel, imx
In-Reply-To: <20260701131137.940145-1-ioana.ciornei@nxp.com>
From: Vladimir Oltean <vladimir.oltean@nxp.com>
Describe the Lynx 10G SerDes block and its 4 SerDes lanes found on the
LS1028A SoC. The node is left disabled at the SoC level; board DTs will
be expected to enable it once the consumer Ethernet nodes use it.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v2:
- Change the size of the region to 0x2000
---
.../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 29 +++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index f4ba3d16ab86..ef62968590fa 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -250,6 +250,35 @@ ls1028a_uid: unique-id@1c {
};
};
+ serdes: phy@1ea0000 {
+ compatible = "fsl,ls1028a-serdes";
+ reg = <0x00 0x1ea0000 0x0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #phy-cells = <1>;
+ status = "disabled";
+
+ serdes_lane_a: phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ serdes_lane_b: phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+
+ serdes_lane_c: phy@2 {
+ reg = <2>;
+ #phy-cells = <0>;
+ };
+
+ serdes_lane_d: phy@3 {
+ reg = <3>;
+ #phy-cells = <0>;
+ };
+ };
+
scfg: syscon@1fc0000 {
compatible = "fsl,ls1028a-scfg", "syscon";
reg = <0x0 0x1fc0000 0x0 0x10000>;
--
2.25.1
^ permalink raw reply related
* [PATCH v2 5/5] arm64: dts: ls1088a: describe the Lynx 10G SerDes blocks
From: Ioana Ciornei @ 2026-07-01 13:11 UTC (permalink / raw)
To: Frank.Li, robh, krzk+dt, conor+dt, devicetree
Cc: vladimir.oltean, linux-arm-kernel, linux-kernel, imx
In-Reply-To: <20260701131137.940145-1-ioana.ciornei@nxp.com>
Describe the two Lynx 10G SerDes blocks and their associated lanes found
on the LS1088A SoC. The nodes are left disabled at the SoC level; board
DTs will enable them once there are consumers.
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v2:
- Change the size of the region to 0x2000
---
.../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 58 +++++++++++++++++++
1 file changed, 58 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index 99016768b73f..e02f34329988 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -239,6 +239,64 @@ reset: syscon@1e60000 {
reg = <0x0 0x1e60000 0x0 0x10000>;
};
+ serdes1: phy@1ea0000 {
+ compatible = "fsl,ls1088a-serdes1";
+ reg = <0x00 0x1ea0000 0x0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #phy-cells = <1>;
+ status = "disabled";
+
+ serdes1_lane_a: phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ serdes1_lane_b: phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+
+ serdes1_lane_c: phy@2 {
+ reg = <2>;
+ #phy-cells = <0>;
+ };
+
+ serdes1_lane_d: phy@3 {
+ reg = <3>;
+ #phy-cells = <0>;
+ };
+ };
+
+ serdes2: phy@1eb0000 {
+ compatible = "fsl,ls1088a-serdes2";
+ reg = <0x00 0x1eb0000 0x0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #phy-cells = <1>;
+ status = "disabled";
+
+ serdes2_lane_a: phy@0 {
+ reg = <0>;
+ #phy-cells = <0>;
+ };
+
+ serdes2_lane_b: phy@1 {
+ reg = <1>;
+ #phy-cells = <0>;
+ };
+
+ serdes2_lane_c: phy@2 {
+ reg = <2>;
+ #phy-cells = <0>;
+ };
+
+ serdes2_lane_d: phy@3 {
+ reg = <3>;
+ #phy-cells = <0>;
+ };
+ };
+
isc: syscon@1f70000 {
compatible = "fsl,ls1088a-isc", "syscon";
reg = <0x0 0x1f70000 0x0 0x10000>;
--
2.25.1
^ permalink raw reply related
* Re: [PATCH v2 1/9] time: Respect COMPAT_32BIT_TIME for old time type functions
From: Arnd Bergmann @ 2026-07-01 13:11 UTC (permalink / raw)
To: Thomas Weißschuh
Cc: Andy Lutomirski, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
Dave Hansen, x86, H. Peter Anvin, Russell King, Catalin Marinas,
Will Deacon, Madhavan Srinivasan, Michael Ellerman,
Nicholas Piggin, Christophe Leroy, Thomas Bogendoerfer,
Vincenzo Frascino, John Stultz, Stephen Boyd, David S . Miller,
Andreas Larsson, linux-kernel, linux-arm-kernel, linuxppc-dev,
linux-mips, linux-api, sparclinux
In-Reply-To: <20260701102912-ea8f3291-7bba-407b-9a7d-7c367a4c9398@linutronix.de>
On Wed, Jul 1, 2026, at 10:40, Thomas Weißschuh wrote:
> On Tue, Jun 30, 2026 at 03:00:37PM +0200, Arnd Bergmann wrote:
>> On Tue, Jun 30, 2026, at 09:38, Thomas Weißschuh wrote:
>> > The "old" time types use 32-bit seconds which are not y2038-safe.
>> > Respect COMPAT_32BIT_TIME for functions using those types.
>> > time(), stime() and gettimeofday() are disabled completely.
>>
>> Looks good, yes
>
> Sashiko found an issue [0], which I think is valid. I'll change that for v3.
Ok
>> > settimeofday() is kept as it is required to do the initial timewarping
>> > after boot. However the 'tv' argument will be rejected.
>>
>> Not sure about this part, did we already discuss this last time?
>
> This is my interpretation of [1].
Indeed, we did.
>> I can see how keeping the timewarping functionality is the easy way
>> out, but completely disabling the settimeofday syscall the same
>> way we do on new architectures seems so much more consistent.
>
> Shouldn't we then do this completely? Irrespective of COMPAT_32BIT_TIME?
> And then remove all of the timewarping and kernel timezone bits.
I don't think we can simply kill the timewarping code since that
likely has users on architectures including on x86-64.
COMPAT_32BIT_TIME=n is somewhat special because this is an
intentional (and optional) ABI break already and requires
updated userspace that avoids the time32 syscalls. Having the
timewarp still in settimeofday() or dropping it entirely is not
that different for userspace.
I was slightly worried about whether returning -EINVAL or -ENOSYS
is the better option here, but I think your choice is the correct
one after seeing that this is what glibc does other invalid
cases, and that in all of codesearch.debian.net, I could not
find a single caller that would care about the difference.
> It would be nice however if this series, and my other ones blocked behind it,
> are not blocked on that larger rework.
Sure.
I think you can go ahead with this version. I would prefer
to not have any settimeofday() for the COMPAT_32BIT_TIME=n
case, but if nobody else has a strong opinion on the matter,
let's do it your way.
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
^ permalink raw reply
* [PATCH 05/11] drm/mediatek: mtk_dp: Rework register offsets for proper PHY usage
From: AngeloGioacchino Del Regno @ 2026-07-01 12:20 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard, tzimmermann,
robh, krzk+dt, conor+dt, matthias.bgg, angelogioacchino.delregno,
jitao.shi, granquet, rex-bc.chen, dmitry.osipenko, ck.hu,
amergnat, justin.yeh, jason-jh.lin, dri-devel, linux-mediatek,
devicetree, linux-kernel, linux-arm-kernel, kernel
In-Reply-To: <20260701122024.19557-1-angelogioacchino.delregno@collabora.com>
Rework all of the register offsets to subtract the DP PHY register
range from the MediaTek DisplayPort IP register range which starts
from TOP_OFFSET instead.
This is done in preparation for adding support for registering the
PHY from devicetree, and also for properly handling PHY registers
in the PHY driver (instead of half and half...), which is also one
prerogative to add support for new IP versions in the future.
Note that the current regmap_config was renamed to make sure that
it being legacy is mentioned, as a new config will be required in
future changes.
Of course, with the TOP offset being related to hardware registers
this will never change for the currently supported SoCs, hence for
simplifying code, the MTK_DP_TOP_OFFSET_LEGACY is added statically
to the legacy regmap configuration while, on the other hand, it is
added dynamically to the mtk_dp structure, as the latter is used
to add an offset to every register write in the mtk_dp driver.
The regmap_config provided reg_base (which does exactly the same)
cannot be used here, because the PHY driver is using the very same
regmap pointer, and the offset shall not be taken into account in
writes performed by the PHY driver (only ones performed by mtk_dp!).
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_dp.c | 60 ++++--
drivers/gpu/drm/mediatek/mtk_dp_reg.h | 255 ++++++++++++--------------
2 files changed, 164 insertions(+), 151 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/mtk_dp.c
index f551c4543f4e..97bce8966a1f 100644
--- a/drivers/gpu/drm/mediatek/mtk_dp.c
+++ b/drivers/gpu/drm/mediatek/mtk_dp.c
@@ -35,6 +35,27 @@
#include "mtk_dp_reg.h"
+/* PHY Registers - for legacy only */
+#define DP_PHY_GLB_BIAS_GEN_00 0x0
+# define RG_XTP_GLB_BIAS_INTR_CTRL GENMASK(20, 16)
+#define DP_PHY_GLB_DPAUX_TX 0x8
+# define RG_CKM_PT0_CKTX_IMPSEL GENMASK(23, 20)
+#define MTK_DP_0034 0x34
+# define DA_CKM_CKTX0_EN_FORCE_EN BIT(10)
+#define DP_PHY_LANE_TX_0 0x104
+#define DP_PHY_LANE_TX_1 0x204
+#define DP_PHY_LANE_TX_2 0x304
+#define DP_PHY_LANE_TX_3 0x404
+# define RG_XTP_LNx_TX_IMPSEL_PMOS GENMASK(15, 12)
+# define RG_XTP_LNx_TX_IMPSEL_NMOS GENMASK(19, 16)
+#define DP_PHY_AUX_RX_CTL 0x1040
+# define RG_DPAUX_RX_VALID_DEGLITCH_EN BIT(2)
+# define RG_XTP_GLB_CKDET_EN BIT(1)
+# define RG_DPAUX_RX_EN BIT(0)
+
+/* TOP Register offset - for legacy only */
+#define MTK_DP_TOP_OFFSET_LEGACY 0x2000
+
#define MTK_DP_SIP_CONTROL_AARCH32 MTK_SIP_SMC_CMD(0x523)
#define MTK_DP_SIP_ATF_EDP_VIDEO_UNMUTE 33
#define MTK_DP_SIP_ATF_VIDEO_UNMUTE 32
@@ -126,6 +147,9 @@ struct mtk_dp {
struct regmap *regs;
struct timer_list debounce_timer;
+ /* For legacy devicetree compatibility */
+ u16 legacy_regoff;
+
/* For audio */
bool audio_enable;
hdmi_codec_plugged_cb plugged_cb;
@@ -394,11 +418,11 @@ static const struct mtk_dp_efuse_fmt mt8195_dp_efuse_fmt[MTK_DP_CAL_MAX] = {
},
};
-static const struct regmap_config mtk_dp_regmap_config = {
+static const struct regmap_config mtk_dp_regmap_legacy_config = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
- .max_register = SEC_OFFSET + 0x90,
+ .max_register = MTK_DP_TOP_OFFSET_LEGACY + SEC_OFFSET + 0x90,
.name = "mtk-dp-registers",
};
@@ -412,7 +436,7 @@ static u32 mtk_dp_read(struct mtk_dp *mtk_dp, u32 offset)
u32 read_val;
int ret;
- ret = regmap_read(mtk_dp->regs, offset, &read_val);
+ ret = regmap_read(mtk_dp->regs, offset + mtk_dp->legacy_regoff, &read_val);
if (ret) {
dev_err(mtk_dp->dev, "Failed to read register 0x%x: %d\n",
offset, ret);
@@ -424,7 +448,7 @@ static u32 mtk_dp_read(struct mtk_dp *mtk_dp, u32 offset)
static int mtk_dp_write(struct mtk_dp *mtk_dp, u32 offset, u32 val)
{
- int ret = regmap_write(mtk_dp->regs, offset, val);
+ int ret = regmap_write(mtk_dp->regs, offset + mtk_dp->legacy_regoff, val);
if (ret)
dev_err(mtk_dp->dev,
@@ -436,7 +460,7 @@ static int mtk_dp_write(struct mtk_dp *mtk_dp, u32 offset, u32 val)
static int mtk_dp_update_bits(struct mtk_dp *mtk_dp, u32 offset,
u32 val, u32 mask)
{
- int ret = regmap_update_bits(mtk_dp->regs, offset, mask, val);
+ int ret = regmap_update_bits(mtk_dp->regs, offset + mtk_dp->legacy_regoff, mask, val);
if (ret)
dev_err(mtk_dp->dev,
@@ -1229,28 +1253,28 @@ static void mtk_dp_set_calibration_data(struct mtk_dp *mtk_dp)
RG_XTP_GLB_BIAS_INTR_CTRL);
mtk_dp_update_bits(mtk_dp, DP_PHY_LANE_TX_0,
cal_data[MTK_DP_CAL_LN_TX_IMPSEL_PMOS_0] << 12,
- RG_XTP_LN0_TX_IMPSEL_PMOS);
+ RG_XTP_LNx_TX_IMPSEL_PMOS);
mtk_dp_update_bits(mtk_dp, DP_PHY_LANE_TX_0,
cal_data[MTK_DP_CAL_LN_TX_IMPSEL_NMOS_0] << 16,
- RG_XTP_LN0_TX_IMPSEL_NMOS);
+ RG_XTP_LNx_TX_IMPSEL_NMOS);
mtk_dp_update_bits(mtk_dp, DP_PHY_LANE_TX_1,
cal_data[MTK_DP_CAL_LN_TX_IMPSEL_PMOS_1] << 12,
- RG_XTP_LN1_TX_IMPSEL_PMOS);
+ RG_XTP_LNx_TX_IMPSEL_PMOS);
mtk_dp_update_bits(mtk_dp, DP_PHY_LANE_TX_1,
cal_data[MTK_DP_CAL_LN_TX_IMPSEL_NMOS_1] << 16,
- RG_XTP_LN1_TX_IMPSEL_NMOS);
+ RG_XTP_LNx_TX_IMPSEL_NMOS);
mtk_dp_update_bits(mtk_dp, DP_PHY_LANE_TX_2,
cal_data[MTK_DP_CAL_LN_TX_IMPSEL_PMOS_2] << 12,
- RG_XTP_LN2_TX_IMPSEL_PMOS);
+ RG_XTP_LNx_TX_IMPSEL_PMOS);
mtk_dp_update_bits(mtk_dp, DP_PHY_LANE_TX_2,
cal_data[MTK_DP_CAL_LN_TX_IMPSEL_NMOS_2] << 16,
- RG_XTP_LN2_TX_IMPSEL_NMOS);
+ RG_XTP_LNx_TX_IMPSEL_NMOS);
mtk_dp_update_bits(mtk_dp, DP_PHY_LANE_TX_3,
cal_data[MTK_DP_CAL_LN_TX_IMPSEL_PMOS_3] << 12,
- RG_XTP_LN3_TX_IMPSEL_PMOS);
+ RG_XTP_LNx_TX_IMPSEL_PMOS);
mtk_dp_update_bits(mtk_dp, DP_PHY_LANE_TX_3,
cal_data[MTK_DP_CAL_LN_TX_IMPSEL_NMOS_3] << 16,
- RG_XTP_LN3_TX_IMPSEL_NMOS);
+ RG_XTP_LNx_TX_IMPSEL_NMOS);
}
static int mtk_dp_phy_configure(struct mtk_dp *mtk_dp,
@@ -1401,7 +1425,7 @@ static void mtk_dp_power_enable(struct mtk_dp *mtk_dp)
SW_RST_B_PHYD, SW_RST_B_PHYD);
mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE,
DP_PWR_STATE_BANDGAP_TPLL, DP_PWR_STATE_MASK);
- mtk_dp_write(mtk_dp, MTK_DP_1040,
+ mtk_dp_write(mtk_dp, DP_PHY_AUX_RX_CTL,
RG_DPAUX_RX_VALID_DEGLITCH_EN | RG_XTP_GLB_CKDET_EN |
RG_DPAUX_RX_EN);
mtk_dp_update_bits(mtk_dp, MTK_DP_0034, 0, DA_CKM_CKTX0_EN_FORCE_EN);
@@ -1415,7 +1439,7 @@ static void mtk_dp_power_disable(struct mtk_dp *mtk_dp)
DA_CKM_CKTX0_EN_FORCE_EN, DA_CKM_CKTX0_EN_FORCE_EN);
/* Disable RX */
- mtk_dp_write(mtk_dp, MTK_DP_1040, 0);
+ mtk_dp_write(mtk_dp, DP_PHY_AUX_RX_CTL, 0);
mtk_dp_write(mtk_dp, MTK_DP_TOP_MEM_PD,
0x550 | FUSE_SEL | MEM_ISO_EN);
}
@@ -2067,7 +2091,8 @@ static int mtk_dp_wait_hpd_asserted(struct drm_dp_aux *mtk_aux, unsigned long wa
u32 val;
int ret;
- ret = regmap_read_poll_timeout(mtk_dp->regs, MTK_DP_TRANS_P0_3414,
+ ret = regmap_read_poll_timeout(mtk_dp->regs,
+ MTK_DP_TRANS_P0_3414 + mtk_dp->legacy_regoff,
val, !!(val & HPD_DB_DP_TRANS_P0_MASK),
wait_us / 100, wait_us);
if (ret) {
@@ -2100,7 +2125,7 @@ static int mtk_dp_dt_parse(struct mtk_dp *mtk_dp,
if (IS_ERR(base))
return PTR_ERR(base);
- mtk_dp->regs = devm_regmap_init_mmio(dev, base, &mtk_dp_regmap_config);
+ mtk_dp->regs = devm_regmap_init_mmio(dev, base, &mtk_dp_regmap_legacy_config);
if (IS_ERR(mtk_dp->regs))
return PTR_ERR(mtk_dp->regs);
@@ -2778,6 +2803,7 @@ static int mtk_dp_probe(struct platform_device *pdev)
mtk_dp->dev = dev;
mtk_dp->data = (struct mtk_dp_data *)of_device_get_match_data(dev);
+ mtk_dp->legacy_regoff = MTK_DP_TOP_OFFSET_LEGACY;
ret = mtk_dp_dt_parse(mtk_dp, pdev);
if (ret)
diff --git a/drivers/gpu/drm/mediatek/mtk_dp_reg.h b/drivers/gpu/drm/mediatek/mtk_dp_reg.h
index 8ad7a9cc259e..616ea6440b08 100644
--- a/drivers/gpu/drm/mediatek/mtk_dp_reg.h
+++ b/drivers/gpu/drm/mediatek/mtk_dp_reg.h
@@ -2,62 +2,22 @@
/*
* Copyright (c) 2019-2022 MediaTek Inc.
* Copyright (c) 2022 BayLibre
+ * Copyright (c) 2026 Collabora Ltd.
*/
#ifndef _MTK_DP_REG_H_
#define _MTK_DP_REG_H_
-#define SEC_OFFSET 0x4000
-
#define MTK_DP_HPD_DISCONNECT BIT(1)
#define MTK_DP_HPD_CONNECT BIT(2)
#define MTK_DP_HPD_INTERRUPT BIT(3)
-/* offset: 0x0 */
-#define DP_PHY_GLB_BIAS_GEN_00 0x0
-#define RG_XTP_GLB_BIAS_INTR_CTRL GENMASK(20, 16)
-#define DP_PHY_GLB_DPAUX_TX 0x8
-#define RG_CKM_PT0_CKTX_IMPSEL GENMASK(23, 20)
-#define MTK_DP_0034 0x34
-#define DA_XTP_GLB_CKDET_EN_FORCE_VAL BIT(15)
-#define DA_XTP_GLB_CKDET_EN_FORCE_EN BIT(14)
-#define DA_CKM_INTCKTX_EN_FORCE_VAL BIT(13)
-#define DA_CKM_INTCKTX_EN_FORCE_EN BIT(12)
-#define DA_CKM_CKTX0_EN_FORCE_VAL BIT(11)
-#define DA_CKM_CKTX0_EN_FORCE_EN BIT(10)
-#define DA_CKM_XTAL_CK_FORCE_VAL BIT(9)
-#define DA_CKM_XTAL_CK_FORCE_EN BIT(8)
-#define DA_CKM_BIAS_LPF_EN_FORCE_VAL BIT(7)
-#define DA_CKM_BIAS_LPF_EN_FORCE_EN BIT(6)
-#define DA_CKM_BIAS_EN_FORCE_VAL BIT(5)
-#define DA_CKM_BIAS_EN_FORCE_EN BIT(4)
-#define DA_XTP_GLB_AVD10_ON_FORCE_VAL BIT(3)
-#define DA_XTP_GLB_AVD10_ON_FORCE BIT(2)
-#define DA_XTP_GLB_LDO_EN_FORCE_VAL BIT(1)
-#define DA_XTP_GLB_LDO_EN_FORCE_EN BIT(0)
-#define DP_PHY_LANE_TX_0 0x104
-#define RG_XTP_LN0_TX_IMPSEL_PMOS GENMASK(15, 12)
-#define RG_XTP_LN0_TX_IMPSEL_NMOS GENMASK(19, 16)
-#define DP_PHY_LANE_TX_1 0x204
-#define RG_XTP_LN1_TX_IMPSEL_PMOS GENMASK(15, 12)
-#define RG_XTP_LN1_TX_IMPSEL_NMOS GENMASK(19, 16)
-#define DP_PHY_LANE_TX_2 0x304
-#define RG_XTP_LN2_TX_IMPSEL_PMOS GENMASK(15, 12)
-#define RG_XTP_LN2_TX_IMPSEL_NMOS GENMASK(19, 16)
-#define DP_PHY_LANE_TX_3 0x404
-#define RG_XTP_LN3_TX_IMPSEL_PMOS GENMASK(15, 12)
-#define RG_XTP_LN3_TX_IMPSEL_NMOS GENMASK(19, 16)
-#define MTK_DP_1040 0x1040
-#define RG_DPAUX_RX_VALID_DEGLITCH_EN BIT(2)
-#define RG_XTP_GLB_CKDET_EN BIT(1)
-#define RG_DPAUX_RX_EN BIT(0)
-
-/* offset: TOP_OFFSET (0x2000) */
-#define MTK_DP_TOP_PWR_STATE 0x2000
+/* offset: TOP_OFFSET (0x0) */
+#define MTK_DP_TOP_PWR_STATE 0x0
#define DP_PWR_STATE_MASK GENMASK(1, 0)
#define DP_PWR_STATE_BANDGAP BIT(0)
#define DP_PWR_STATE_BANDGAP_TPLL BIT(1)
#define DP_PWR_STATE_BANDGAP_TPLL_LANE GENMASK(1, 0)
-#define MTK_DP_TOP_SWING_EMP 0x2004
+#define MTK_DP_TOP_SWING_EMP 0x4
#define DP_TX0_VOLT_SWING_MASK GENMASK(1, 0)
#define DP_TX0_VOLT_SWING_SHIFT 0
#define DP_TX0_PRE_EMPH_MASK GENMASK(3, 2)
@@ -69,43 +29,59 @@
#define DP_TX2_PRE_EMPH_MASK GENMASK(19, 18)
#define DP_TX3_VOLT_SWING_MASK GENMASK(25, 24)
#define DP_TX3_PRE_EMPH_MASK GENMASK(27, 26)
-#define MTK_DP_TOP_RESET_AND_PROBE 0x2020
+#define MTK_DP_TOP_RESET_AND_PROBE 0x20
#define SW_RST_B_PHYD BIT(4)
-#define MTK_DP_TOP_IRQ_MASK 0x202c
+#define RG_SW_RST_MASK GENMASK(7, 0)
+#define RG_SW_RST 0xff
+#define RG_PROBE_LOW_SEL_MASK GENMASK(18, 16)
+#define RG_PROBE_LOW_SEL BIT(16)
+#define RG_PROBE_LOW_HIGH_SWAP_MASK BIT(23)
+#define RG_PROBE_LOW_HIGH_SWAP BIT(23)
+
+#define MTK_DP_TOP_IRQ_MASK 0x2c
+#define ENCODER_IRQ_MSK BIT(0)
+#define TRANS_IRQ_MSK BIT(1)
#define IRQ_MASK_AUX_TOP_IRQ BIT(2)
-#define MTK_DP_TOP_MEM_PD 0x2038
+
+#define MTK_DP_TOP_MEM_PD 0x38
#define MEM_ISO_EN BIT(0)
#define FUSE_SEL BIT(2)
-/* offset: ENC0_OFFSET (0x3000) */
-#define MTK_DP_ENC0_P0_3000 0x3000
+#define EDP_TX_TOP_CLKGEN_0 0x74
+#define EDP_TX_TOP_CLKGEN_REST_MASK 0xf
+#define EDP_TX_TOP_CLKGEN_REST_VALUE 0xf
+
+/* offset: ENC0_OFFSET (0x1000) */
+#define MTK_DP_ENC0_P0_3000 0x1000
#define LANE_NUM_DP_ENC0_P0_MASK GENMASK(1, 0)
#define VIDEO_MUTE_SW_DP_ENC0_P0 BIT(2)
#define VIDEO_MUTE_SEL_DP_ENC0_P0 BIT(3)
#define ENHANCED_FRAME_EN_DP_ENC0_P0 BIT(4)
-#define MTK_DP_ENC0_P0_3004 0x3004
+#define DP_I_MODE_ENABLE BIT(6)
+#define REG_BS_SYMBOL_CNT_RESET BIT(7)
+#define MTK_DP_ENC0_P0_3004 0x1004
#define VIDEO_M_CODE_SEL_DP_ENC0_P0_MASK BIT(8)
#define DP_TX_ENCODER_4P_RESET_SW_DP_ENC0_P0 BIT(9)
#define SDP_RESET_SW_DP_ENC0_P0 BIT(13)
-#define MTK_DP_ENC0_P0_3010 0x3010
+#define MTK_DP_ENC0_P0_3010 0x1010
#define HTOTAL_SW_DP_ENC0_P0_MASK GENMASK(15, 0)
-#define MTK_DP_ENC0_P0_3014 0x3014
+#define MTK_DP_ENC0_P0_3014 0x1014
#define VTOTAL_SW_DP_ENC0_P0_MASK GENMASK(15, 0)
-#define MTK_DP_ENC0_P0_3018 0x3018
+#define MTK_DP_ENC0_P0_3018 0x1018
#define HSTART_SW_DP_ENC0_P0_MASK GENMASK(15, 0)
-#define MTK_DP_ENC0_P0_301C 0x301c
+#define MTK_DP_ENC0_P0_301C 0x101c
#define VSTART_SW_DP_ENC0_P0_MASK GENMASK(15, 0)
-#define MTK_DP_ENC0_P0_3020 0x3020
+#define MTK_DP_ENC0_P0_3020 0x1020
#define HWIDTH_SW_DP_ENC0_P0_MASK GENMASK(15, 0)
-#define MTK_DP_ENC0_P0_3024 0x3024
+#define MTK_DP_ENC0_P0_3024 0x1024
#define VHEIGHT_SW_DP_ENC0_P0_MASK GENMASK(15, 0)
-#define MTK_DP_ENC0_P0_3028 0x3028
+#define MTK_DP_ENC0_P0_3028 0x1028
#define HSW_SW_DP_ENC0_P0_MASK GENMASK(14, 0)
#define HSP_SW_DP_ENC0_P0_MASK BIT(15)
-#define MTK_DP_ENC0_P0_302C 0x302c
+#define MTK_DP_ENC0_P0_302C 0x102c
#define VSW_SW_DP_ENC0_P0_MASK GENMASK(14, 0)
#define VSP_SW_DP_ENC0_P0_MASK BIT(15)
-#define MTK_DP_ENC0_P0_3030 0x3030
+#define MTK_DP_ENC0_P0_3030 0x1030
#define HTOTAL_SEL_DP_ENC0_P0 BIT(0)
#define VTOTAL_SEL_DP_ENC0_P0 BIT(1)
#define HSTART_SEL_DP_ENC0_P0 BIT(2)
@@ -118,10 +94,10 @@
#define VSW_SEL_DP_ENC0_P0 BIT(9)
#define VBID_AUDIO_MUTE_FLAG_SW_DP_ENC0_P0 BIT(11)
#define VBID_AUDIO_MUTE_FLAG_SEL_DP_ENC0_P0 BIT(12)
-#define MTK_DP_ENC0_P0_3034 0x3034
-#define MTK_DP_ENC0_P0_3038 0x3038
+#define MTK_DP_ENC0_P0_3034 0x1034
+#define MTK_DP_ENC0_P0_3038 0x1038
#define VIDEO_SOURCE_SEL_DP_ENC0_P0_MASK BIT(11)
-#define MTK_DP_ENC0_P0_303C 0x303c
+#define MTK_DP_ENC0_P0_303C 0x103c
#define SRAM_START_READ_THRD_DP_ENC0_P0_MASK GENMASK(5, 0)
#define VIDEO_COLOR_DEPTH_DP_ENC0_P0_MASK GENMASK(10, 8)
#define VIDEO_COLOR_DEPTH_DP_ENC0_P0_16BIT (0 << 8)
@@ -130,34 +106,36 @@
#define VIDEO_COLOR_DEPTH_DP_ENC0_P0_8BIT (3 << 8)
#define VIDEO_COLOR_DEPTH_DP_ENC0_P0_6BIT (4 << 8)
#define PIXEL_ENCODE_FORMAT_DP_ENC0_P0_MASK GENMASK(14, 12)
-#define PIXEL_ENCODE_FORMAT_DP_ENC0_P0_RGB (0 << 12)
-#define PIXEL_ENCODE_FORMAT_DP_ENC0_P0_YCBCR422 (1 << 12)
-#define PIXEL_ENCODE_FORMAT_DP_ENC0_P0_YCBCR420 (2 << 12)
+# define PIXEL_ENCODE_FORMAT_DP_ENC0_P0_RGB 0
+# define PIXEL_ENCODE_FORMAT_DP_ENC0_P0_YCBCR422 1
+# define PIXEL_ENCODE_FORMAT_DP_ENC0_P0_YCBCR420 2
+# define PIXEL_ENCODE_FORMAT_DP_ENC0_P0_YONLY 3
+# define PIXEL_ENCODE_FORMAT_DP_ENC0_P0_RAW 4
#define VIDEO_MN_GEN_EN_DP_ENC0_P0 BIT(15)
-#define MTK_DP_ENC0_P0_3040 0x3040
+#define MTK_DP_ENC0_P0_3040 0x1040
#define SDP_DOWN_CNT_DP_ENC0_P0_VAL 0x20
#define SDP_DOWN_CNT_INIT_DP_ENC0_P0_MASK GENMASK(11, 0)
-#define MTK_DP_ENC0_P0_304C 0x304c
+#define MTK_DP_ENC0_P0_304C 0x104c
#define VBID_VIDEO_MUTE_DP_ENC0_P0_MASK BIT(2)
#define SDP_VSYNC_RISING_MASK_DP_ENC0_P0_MASK BIT(8)
-#define MTK_DP_ENC0_P0_3064 0x3064
+#define MTK_DP_ENC0_P0_3064 0x1064
#define HDE_NUM_LAST_DP_ENC0_P0_MASK GENMASK(15, 0)
-#define MTK_DP_ENC0_P0_3088 0x3088
+#define MTK_DP_ENC0_P0_3088 0x1088
#define AU_EN_DP_ENC0_P0 BIT(6)
#define AUDIO_8CH_EN_DP_ENC0_P0_MASK BIT(7)
#define AUDIO_8CH_SEL_DP_ENC0_P0_MASK BIT(8)
#define AUDIO_2CH_EN_DP_ENC0_P0_MASK BIT(14)
#define AUDIO_2CH_SEL_DP_ENC0_P0_MASK BIT(15)
-#define MTK_DP_ENC0_P0_308C 0x308c
+#define MTK_DP_ENC0_P0_308C 0x108c
#define CH_STATUS_0_DP_ENC0_P0_MASK GENMASK(15, 0)
-#define MTK_DP_ENC0_P0_3090 0x3090
+#define MTK_DP_ENC0_P0_3090 0x1090
#define CH_STATUS_1_DP_ENC0_P0_MASK GENMASK(15, 0)
-#define MTK_DP_ENC0_P0_3094 0x3094
+#define MTK_DP_ENC0_P0_3094 0x1094
#define CH_STATUS_2_DP_ENC0_P0_MASK GENMASK(7, 0)
-#define MTK_DP_ENC0_P0_30A4 0x30a4
+#define MTK_DP_ENC0_P0_30A4 0x10a4
#define AU_TS_CFG_DP_ENC0_P0_MASK GENMASK(7, 0)
-#define MTK_DP_ENC0_P0_30A8 0x30a8
-#define MTK_DP_ENC0_P0_30BC 0x30bc
+#define MTK_DP_ENC0_P0_30A8 0x10a8
+#define MTK_DP_ENC0_P0_30BC 0x10bc
#define ISRC_CONT_DP_ENC0_P0 BIT(0)
#define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MASK GENMASK(10, 8)
#define MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_2 (1 << 8)
@@ -172,63 +150,65 @@
#define MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2 (4 << 8)
#define MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_4 (5 << 8)
#define MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_8 (7 << 8)
-#define MTK_DP_ENC0_P0_30D8 0x30d8
-#define MTK_DP_ENC0_P0_312C 0x312c
+#define MTK_DP_ENC0_P0_30D8 0x10d8
+#define MTK_DP_ENC0_P0_312C 0x112c
#define ASP_HB2_DP_ENC0_P0_MASK GENMASK(7, 0)
#define ASP_HB3_DP_ENC0_P0_MASK GENMASK(15, 8)
-#define MTK_DP_ENC0_P0_3154 0x3154
+#define MTK_DP_ENC0_P0_3154 0x1154
#define PGEN_HTOTAL_DP_ENC0_P0_MASK GENMASK(13, 0)
-#define MTK_DP_ENC0_P0_3158 0x3158
+#define MTK_DP_ENC0_P0_3158 0x1158
#define PGEN_HSYNC_RISING_DP_ENC0_P0_MASK GENMASK(13, 0)
-#define MTK_DP_ENC0_P0_315C 0x315c
+#define MTK_DP_ENC0_P0_315C 0x115c
#define PGEN_HSYNC_PULSE_WIDTH_DP_ENC0_P0_MASK GENMASK(13, 0)
-#define MTK_DP_ENC0_P0_3160 0x3160
+#define MTK_DP_ENC0_P0_3160 0x1160
#define PGEN_HFDE_START_DP_ENC0_P0_MASK GENMASK(13, 0)
-#define MTK_DP_ENC0_P0_3164 0x3164
+#define MTK_DP_ENC0_P0_3164 0x1164
#define PGEN_HFDE_ACTIVE_WIDTH_DP_ENC0_P0_MASK GENMASK(13, 0)
-#define MTK_DP_ENC0_P0_3168 0x3168
+#define MTK_DP_ENC0_P0_3168 0x1168
#define PGEN_VTOTAL_DP_ENC0_P0_MASK GENMASK(12, 0)
-#define MTK_DP_ENC0_P0_316C 0x316c
+#define MTK_DP_ENC0_P0_316C 0x116c
#define PGEN_VSYNC_RISING_DP_ENC0_P0_MASK GENMASK(12, 0)
-#define MTK_DP_ENC0_P0_3170 0x3170
+#define MTK_DP_ENC0_P0_3170 0x1170
#define PGEN_VSYNC_PULSE_WIDTH_DP_ENC0_P0_MASK GENMASK(12, 0)
-#define MTK_DP_ENC0_P0_3174 0x3174
+#define MTK_DP_ENC0_P0_3174 0x1174
#define PGEN_VFDE_START_DP_ENC0_P0_MASK GENMASK(12, 0)
-#define MTK_DP_ENC0_P0_3178 0x3178
+#define MTK_DP_ENC0_P0_3178 0x1178
#define PGEN_VFDE_ACTIVE_WIDTH_DP_ENC0_P0_MASK GENMASK(12, 0)
-#define MTK_DP_ENC0_P0_31B0 0x31b0
+#define MTK_DP_ENC0_P0_31B0 0x11b0
#define PGEN_PATTERN_SEL_VAL 4
#define PGEN_PATTERN_SEL_MASK GENMASK(6, 4)
-#define MTK_DP_ENC0_P0_31EC 0x31ec
+#define MTK_DP_ENC0_P0_31EC 0x11ec
#define AUDIO_CH_SRC_SEL_DP_ENC0_P0 BIT(4)
#define ISRC1_HB3_DP_ENC0_P0_MASK GENMASK(15, 8)
-/* offset: ENC1_OFFSET (0x3200) */
-#define MTK_DP_ENC1_P0_3200 0x3200
-#define MTK_DP_ENC1_P0_3280 0x3280
+/* offset: ENC1_OFFSET (0x1200) */
+#define MTK_DP_ENC1_P0_3200 0x1200
+#define MTK_DP_ENC1_P0_3280 0x1280
#define SDP_PACKET_TYPE_DP_ENC1_P0_MASK GENMASK(4, 0)
#define SDP_PACKET_W_DP_ENC1_P0 BIT(5)
#define SDP_PACKET_W_DP_ENC1_P0_MASK BIT(5)
-#define MTK_DP_ENC1_P0_3300 0x3300
+#define MTK_DP_ENC1_P0_3300 0x1300
#define VIDEO_AFIFO_RDY_SEL_DP_ENC1_P0_VAL 2
#define VIDEO_AFIFO_RDY_SEL_DP_ENC1_P0_MASK GENMASK(9, 8)
-#define MTK_DP_ENC1_P0_3304 0x3304
+#define MTK_DP_ENC1_P0_3304 0x1304
#define AU_PRTY_REGEN_DP_ENC1_P0_MASK BIT(8)
#define AU_CH_STS_REGEN_DP_ENC1_P0_MASK BIT(9)
#define AUDIO_SAMPLE_PRSENT_REGEN_DP_ENC1_P0_MASK BIT(12)
-#define MTK_DP_ENC1_P0_3324 0x3324
+#define MTK_DP_ENC1_P0_3324 0x1324
#define AUDIO_SOURCE_MUX_DP_ENC1_P0_MASK GENMASK(9, 8)
#define AUDIO_SOURCE_MUX_DP_ENC1_P0_DPRX 0
-#define MTK_DP_ENC1_P0_3364 0x3364
+#define MTK_DP_ENC1_P0_3364 0x1364
#define SDP_DOWN_CNT_IN_HBLANK_DP_ENC1_P0_VAL 0x20
#define SDP_DOWN_CNT_INIT_IN_HBLANK_DP_ENC1_P0_MASK GENMASK(11, 0)
#define FIFO_READ_START_POINT_DP_ENC1_P0_VAL 4
#define FIFO_READ_START_POINT_DP_ENC1_P0_MASK GENMASK(15, 12)
-#define MTK_DP_ENC1_P0_3368 0x3368
+#define MTK_DP_ENC1_P0_3368 0x1368
#define VIDEO_SRAM_FIFO_CNT_RESET_SEL_DP_ENC1_P0 BIT(0)
+#define VIDEO_SRAM_FIFO_CNT_RESET_SEL_MASK GENMASK(1, 0)
#define VIDEO_STABLE_CNT_THRD_DP_ENC1_P0 BIT(4)
#define SDP_DP13_EN_DP_ENC1_P0 BIT(8)
#define BS2BS_MODE_DP_ENC1_P0 BIT(12)
+#define BS_FOLLOW_SEL_DP_ENC0_P0 BIT(15)
#define BS2BS_MODE_DP_ENC1_P0_MASK GENMASK(13, 12)
#define BS2BS_MODE_DP_ENC1_P0_VAL 1
#define DP_ENC1_P0_3368_VAL (VIDEO_SRAM_FIFO_CNT_RESET_SEL_DP_ENC1_P0 | \
@@ -236,94 +216,94 @@
SDP_DP13_EN_DP_ENC1_P0 | \
BS2BS_MODE_DP_ENC1_P0)
-#define MTK_DP_ENC1_P0_3374 0x3374
+#define MTK_DP_ENC1_P0_3374 0x1374
#define SDP_ASP_INSERT_IN_HBLANK_DP_ENC1_P0_MASK BIT(12)
#define SDP_DOWN_ASP_CNT_INIT_DP_ENC1_P0_MASK GENMASK(11, 0)
-#define MTK_DP_ENC1_P0_33F4 0x33f4
+#define MTK_DP_ENC1_P0_33F4 0x13f4
#define DP_ENC_DUMMY_RW_1_AUDIO_RST_EN BIT(0)
#define DP_ENC_DUMMY_RW_1 BIT(9)
-/* offset: TRANS_OFFSET (0x3400) */
-#define MTK_DP_TRANS_P0_3400 0x3400
+/* offset: TRANS_OFFSET (0x1400) */
+#define MTK_DP_TRANS_P0_3400 0x1400
#define PATTERN1_EN_DP_TRANS_P0_MASK BIT(12)
#define PATTERN2_EN_DP_TRANS_P0_MASK BIT(13)
#define PATTERN3_EN_DP_TRANS_P0_MASK BIT(14)
#define PATTERN4_EN_DP_TRANS_P0_MASK BIT(15)
-#define MTK_DP_TRANS_P0_3404 0x3404
+#define MTK_DP_TRANS_P0_3404 0x1404
#define DP_SCR_EN_DP_TRANS_P0_MASK BIT(0)
-#define MTK_DP_TRANS_P0_340C 0x340c
+#define MTK_DP_TRANS_P0_340C 0x140c
#define DP_TX_TRANSMITTER_4P_RESET_SW_DP_TRANS_P0 BIT(13)
-#define MTK_DP_TRANS_P0_3410 0x3410
+#define MTK_DP_TRANS_P0_3410 0x1410
#define HPD_DEB_THD_DP_TRANS_P0_MASK GENMASK(3, 0)
#define HPD_INT_THD_DP_TRANS_P0_MASK GENMASK(7, 4)
#define HPD_INT_THD_DP_TRANS_P0_LOWER_500US (2 << 4)
#define HPD_INT_THD_DP_TRANS_P0_UPPER_1100US (2 << 6)
#define HPD_DISC_THD_DP_TRANS_P0_MASK GENMASK(11, 8)
#define HPD_CONN_THD_DP_TRANS_P0_MASK GENMASK(15, 12)
-#define MTK_DP_TRANS_P0_3414 0x3414
+#define MTK_DP_TRANS_P0_3414 0x1414
#define HPD_DB_DP_TRANS_P0_MASK BIT(2)
-#define MTK_DP_TRANS_P0_3418 0x3418
+#define MTK_DP_TRANS_P0_3418 0x1418
#define IRQ_CLR_DP_TRANS_P0_MASK GENMASK(3, 0)
#define IRQ_MASK_DP_TRANS_P0_MASK GENMASK(7, 4)
#define IRQ_MASK_DP_TRANS_P0_DISC_IRQ (BIT(1) << 4)
#define IRQ_MASK_DP_TRANS_P0_CONN_IRQ (BIT(2) << 4)
#define IRQ_MASK_DP_TRANS_P0_INT_IRQ (BIT(3) << 4)
#define IRQ_STATUS_DP_TRANS_P0_MASK GENMASK(15, 12)
-#define MTK_DP_TRANS_P0_342C 0x342c
+#define MTK_DP_TRANS_P0_342C 0x142c
#define XTAL_FREQ_DP_TRANS_P0_DEFAULT (BIT(0) | BIT(3) | BIT(5) | BIT(6))
#define XTAL_FREQ_DP_TRANS_P0_MASK GENMASK(7, 0)
-#define MTK_DP_TRANS_P0_3430 0x3430
+#define MTK_DP_TRANS_P0_3430 0x1430
#define HPD_INT_THD_ECO_DP_TRANS_P0_MASK GENMASK(1, 0)
#define HPD_INT_THD_ECO_DP_TRANS_P0_HIGH_BOUND_EXT BIT(1)
-#define MTK_DP_TRANS_P0_34A4 0x34a4
+#define MTK_DP_TRANS_P0_34A4 0x14a4
#define LANE_NUM_DP_TRANS_P0_MASK GENMASK(3, 2)
-#define MTK_DP_TRANS_P0_3540 0x3540
+#define MTK_DP_TRANS_P0_3540 0x1540
#define FEC_EN_DP_TRANS_P0_MASK BIT(0)
#define FEC_CLOCK_EN_MODE_DP_TRANS_P0 BIT(3)
-#define MTK_DP_TRANS_P0_3580 0x3580
+#define MTK_DP_TRANS_P0_3580 0x1580
#define POST_MISC_DATA_LANE0_OV_DP_TRANS_P0_MASK BIT(8)
#define POST_MISC_DATA_LANE1_OV_DP_TRANS_P0_MASK BIT(9)
#define POST_MISC_DATA_LANE2_OV_DP_TRANS_P0_MASK BIT(10)
#define POST_MISC_DATA_LANE3_OV_DP_TRANS_P0_MASK BIT(11)
-#define MTK_DP_TRANS_P0_35C8 0x35c8
+#define MTK_DP_TRANS_P0_35C8 0x15c8
#define SW_IRQ_CLR_DP_TRANS_P0_MASK GENMASK(15, 0)
#define SW_IRQ_STATUS_DP_TRANS_P0_MASK GENMASK(15, 0)
-#define MTK_DP_TRANS_P0_35D0 0x35d0
+#define MTK_DP_TRANS_P0_35D0 0x15d0
#define SW_IRQ_FINAL_STATUS_DP_TRANS_P0_MASK GENMASK(15, 0)
-#define MTK_DP_TRANS_P0_35F0 0x35f0
+#define MTK_DP_TRANS_P0_35F0 0x15f0
#define DP_TRANS_DUMMY_RW_0 BIT(3)
#define DP_TRANS_DUMMY_RW_0_MASK GENMASK(3, 2)
-/* offset: AUX_OFFSET (0x3600) */
-#define MTK_DP_AUX_P0_360C 0x360c
+/* offset: AUX_OFFSET (0x1600) */
+#define MTK_DP_AUX_P0_360C 0x160c
#define AUX_TIMEOUT_THR_AUX_TX_P0_MASK GENMASK(12, 0)
#define AUX_TIMEOUT_THR_AUX_TX_P0_VAL 0x1595
-#define MTK_DP_AUX_P0_3614 0x3614
+#define MTK_DP_AUX_P0_3614 0x1614
#define AUX_RX_UI_CNT_THR_AUX_TX_P0_MASK GENMASK(6, 0)
#define AUX_RX_UI_CNT_THR_AUX_FOR_26M 13
-#define MTK_DP_AUX_P0_3618 0x3618
+#define MTK_DP_AUX_P0_3618 0x1618
#define AUX_RX_FIFO_FULL_AUX_TX_P0_MASK BIT(9)
#define AUX_RX_FIFO_WRITE_POINTER_AUX_TX_P0_MASK GENMASK(3, 0)
-#define MTK_DP_AUX_P0_3620 0x3620
+#define MTK_DP_AUX_P0_3620 0x1620
#define AUX_RD_MODE_AUX_TX_P0_MASK BIT(9)
#define AUX_RX_FIFO_READ_PULSE_TX_P0 BIT(8)
#define AUX_RX_FIFO_READ_DATA_AUX_TX_P0_MASK GENMASK(7, 0)
-#define MTK_DP_AUX_P0_3624 0x3624
+#define MTK_DP_AUX_P0_3624 0x1624
#define AUX_RX_REPLY_COMMAND_AUX_TX_P0_MASK GENMASK(3, 0)
-#define MTK_DP_AUX_P0_3628 0x3628
+#define MTK_DP_AUX_P0_3628 0x1628
#define AUX_RX_PHY_STATE_AUX_TX_P0_MASK GENMASK(9, 0)
#define AUX_RX_PHY_STATE_AUX_TX_P0_RX_IDLE BIT(0)
-#define MTK_DP_AUX_P0_362C 0x362c
+#define MTK_DP_AUX_P0_362C 0x162c
#define AUX_NO_LENGTH_AUX_TX_P0 BIT(0)
#define AUX_TX_AUXTX_OV_EN_AUX_TX_P0_MASK BIT(1)
#define AUX_RESERVED_RW_0_AUX_TX_P0_MASK GENMASK(15, 2)
-#define MTK_DP_AUX_P0_3630 0x3630
+#define MTK_DP_AUX_P0_3630 0x1630
#define AUX_TX_REQUEST_READY_AUX_TX_P0 BIT(3)
-#define MTK_DP_AUX_P0_3634 0x3634
+#define MTK_DP_AUX_P0_3634 0x1634
#define AUX_TX_OVER_SAMPLE_RATE_AUX_TX_P0_MASK GENMASK(15, 8)
#define AUX_TX_OVER_SAMPLE_RATE_FOR_26M 25
-#define MTK_DP_AUX_P0_3640 0x3640
+#define MTK_DP_AUX_P0_3640 0x1640
#define AUX_RX_AUX_RECV_COMPLETE_IRQ_AUX_TX_P0 BIT(6)
#define AUX_RX_EDID_RECV_COMPLETE_IRQ_AUX_TX_P0 BIT(5)
#define AUX_RX_MCCS_RECV_COMPLETE_IRQ_AUX_TX_P0 BIT(4)
@@ -338,25 +318,32 @@
AUX_RX_MCCS_RECV_COMPLETE_IRQ_AUX_TX_P0 | \
AUX_RX_EDID_RECV_COMPLETE_IRQ_AUX_TX_P0 | \
AUX_RX_AUX_RECV_COMPLETE_IRQ_AUX_TX_P0)
-#define MTK_DP_AUX_P0_3644 0x3644
+#define MTK_DP_AUX_P0_3644 0x1644
#define MCU_REQUEST_COMMAND_AUX_TX_P0_MASK GENMASK(3, 0)
-#define MTK_DP_AUX_P0_3648 0x3648
+#define MTK_DP_AUX_P0_3648 0x1648
#define MCU_REQUEST_ADDRESS_LSB_AUX_TX_P0_MASK GENMASK(15, 0)
-#define MTK_DP_AUX_P0_364C 0x364c
+#define MTK_DP_AUX_P0_364C 0x164c
#define MCU_REQUEST_ADDRESS_MSB_AUX_TX_P0_MASK GENMASK(3, 0)
-#define MTK_DP_AUX_P0_3650 0x3650
+#define MTK_DP_AUX_P0_3650 0x1650
#define MCU_REQ_DATA_NUM_AUX_TX_P0_MASK GENMASK(15, 12)
#define PHY_FIFO_RST_AUX_TX_P0_MASK BIT(9)
#define MCU_ACK_TRAN_COMPLETE_AUX_TX_P0 BIT(8)
-#define MTK_DP_AUX_P0_3658 0x3658
+#define MTK_DP_AUX_P0_3658 0x1658
#define AUX_TX_OV_EN_AUX_TX_P0_MASK BIT(0)
-#define MTK_DP_AUX_P0_3690 0x3690
+#define MTK_DP_AUX_P0_3690 0x1690
#define RX_REPLY_COMPLETE_MODE_AUX_TX_P0 BIT(8)
-#define MTK_DP_AUX_P0_3704 0x3704
+
+#define REG_36A0_AUX_TX_P0 0x16a0
+#define DP_TX_INIT_MASK_15_TO_2 GENMASK(15, 2)
+
+#define MTK_DP_AUX_P0_3704 0x1704
#define AUX_TX_FIFO_WDATA_NEW_MODE_T_AUX_TX_P0_MASK BIT(1)
#define AUX_TX_FIFO_NEW_MODE_EN_AUX_TX_P0 BIT(2)
-#define MTK_DP_AUX_P0_3708 0x3708
-#define MTK_DP_AUX_P0_37C8 0x37c8
+#define MTK_DP_AUX_P0_3708 0x1708
+#define MTK_DP_AUX_P0_37C8 0x17c8
#define MTK_ATOP_EN_AUX_TX_P0 BIT(0)
+/* offset: SEC_OFFSET (0x2000) */
+#define SEC_OFFSET 0x2000
+
#endif /*_MTK_DP_REG_H_*/
--
2.54.0
^ permalink raw reply related
* Re: [PATCH 1/3] dt-bindings: rtc: Add sii,wakealarm-output-pin property for S35390A
From: Markus Probst @ 2026-07-01 13:25 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Alexandre Belloni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Uwe Kleine-König, Andrew Lunn, Gregory Clement,
Sebastian Hesselbarth, linux-arm-kernel, linux-rtc, devicetree,
linux-kernel
In-Reply-To: <20260701-bronze-jaguar-of-perfection-028bac@quoll>
[-- Attachment #1: Type: text/plain, Size: 2712 bytes --]
On Wed, 2026-07-01 at 09:35 +0200, Krzysztof Kozlowski wrote:
> On Tue, Jun 30, 2026 at 07:22:21PM +0000, Markus Probst wrote:
> > Synology NAS devices use the output pin for interrupt signal 1 to wake up
> > the system.
> >
> > Move devicetree bindings for sii,s35390a into its own file.
> > Add sii,wakealarm-output-pin property to enable the use of the output
> > pin for interrupt signal 1 for the wake alarm, which makes it possible to
> > set an wake alarm on Synology NAS devices.
> >
> > Signed-off-by: Markus Probst <markus.probst@posteo.de>
> > ---
> > .../devicetree/bindings/rtc/sii,s35390a.yaml | 54 ++++++++++++++++++++++
> > .../devicetree/bindings/rtc/trivial-rtc.yaml | 3 --
> > MAINTAINERS | 1 +
> > include/dt-bindings/rtc/s35390a.h | 9 ++++
> > 4 files changed, 64 insertions(+), 3 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/rtc/sii,s35390a.yaml b/Documentation/devicetree/bindings/rtc/sii,s35390a.yaml
> > new file mode 100644
> > index 000000000000..31a578673870
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/rtc/sii,s35390a.yaml
> > @@ -0,0 +1,54 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/rtc/sii,s35390a.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: S-35390A 2-WIRE REAL-TIME CLOCK
> > +
> > +maintainers:
> > + - Alexandre Belloni <alexandre.belloni@bootlin.com>
>
> This should be someone caring about this hardware.
He does have the majority of commits on this driver (excluding merge
commits and commits not exclusive to this driver), although most of
them are pretty tiny.
Who would you suggest instead?
>
> > +
> > +description:
> > + The S-35390A is a CMOS 2-wire real-time clock IC which operates with the
> > + very low current consumption in the wide range of operation voltage.
> > +
> > +allOf:
> > + - $ref: rtc.yaml#
> > +
> > +properties:
> > + compatible:
> > + const: sii,s35390a
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + sii,wakealarm-output-pin:
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + enum: [1, 2]
> > + description: |
> > + The output pin to wake up the system.
> > + Default will use the output pin for interrupt signal 2.
> > + <S35390A_OUTPUT_PIN_INT1> : Output pin for interrupt signal 1
> > + <S35390A_OUTPUT_PIN_INT2> : Output pin for interrupt signal 2
>
> Does that mean device generates the interrupts?
Yes.
Thanks
- Markus Probst
>
> Best regards,
> Krzysztof
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^ permalink raw reply
* Re: [PATCH v4 1/5] dt-bindings: arm: coresight-tnoc: Add standalone qcom,coresight-agtnoc compatible
From: Krzysztof Kozlowski @ 2026-07-01 13:30 UTC (permalink / raw)
To: Konrad Dybcio, Jie Gan
Cc: Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Tingwei Zhang, Jingyi Wang, Abel Vesa,
Suzuki K Poulose, Mike Leach, James Clark, Leo Yan,
Yuanfang Zhang, Abel Vesa, Alexander Shishkin, linux-arm-msm,
devicetree, linux-kernel, coresight, linux-arm-kernel
In-Reply-To: <12709ff6-bb42-4d3b-9f9d-e327cd8d89cb@oss.qualcomm.com>
On 01/07/2026 15:09, Konrad Dybcio wrote:
> On 7/1/26 2:54 PM, Jie Gan wrote:
>>
>>
>> On 7/1/2026 7:02 PM, Konrad Dybcio wrote:
>>> On 7/1/26 9:31 AM, Jie Gan wrote:
>>>>
>>>>
>>>> On 7/1/2026 3:26 PM, Krzysztof Kozlowski wrote:
>>>>> On 01/07/2026 09:16, Jie Gan wrote:
>>>>>>
>>>>>>
>>>>>> On 7/1/2026 2:57 PM, Krzysztof Kozlowski wrote:
>>>>>>> On Wed, Jul 01, 2026 at 09:53:41AM +0800, Jie Gan wrote:
>>>>>>>> The TNOC compatible previously only allowed the two-string AMBA form
>>>>>>>> "qcom,coresight-tnoc", "arm,primecell", which forces the device onto the
>>>>>>>> AMBA bus.
>>>>>>>>
>>>>>>>> Convert the compatible to a oneOf and add a standalone
>>>>>>>> "qcom,coresight-agtnoc" compatible alongside the existing AMBA form. The
>>>>>>>> standalone string carries no "arm,primecell" entry, so the device is
>>>>>>>> created on the platform bus instead of the AMBA bus.
>>>
>>> [...]
>>>
>>>>>> AMBA primecell identification. The purpose of the new compatible is to
>>>>>> clearly distinguish this platform-specific case from the standard
>>>>>> AMBA-based implementation. Or shall I re-use the existing compatible
>>>>>> "qcom,coresight-tnoc" as platform standalone compatible?
>>>>>>
>>>>>> We already have a similar pattern for the interconnect TraceNoC device,
>>>>>> which uses the platform-specific compatible string qcom,coresight-itnoc.
>>>>> I do not see there a fake, duplicated compatible for the same device.
>>>>> Can you elaborate how is that relevant?
>>>>
>>>> Will fix it by removing AMBA related description.
>>>>
>>>> Shall I update the clock name from apb_pclk to apb as a platform device?
>>>
>>> Why?
>>
>> For the previous platform devices, we got comments to add the clock-name with "apb" instead of "apb_pclk".
>>
>> Please check the qcom,coresight-ctcu.yaml and qcom,coresight-itnoc.yaml
>
> Well, if you need to break the bindings already, might as well on
> the grounds of choosing a saner ("clock names shouldn't include _clk")
> name.. Not sure if Krzysztof will like it
I miss the rationale for doing the change, why exactly this binding
should have clocks corrected.
Best regards,
Krzysztof
^ permalink raw reply
* [PATCH 0/6] MediaTek MMSYS/Mute-X new-style part 1
From: AngeloGioacchino Del Regno @ 2026-07-01 12:20 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, maarten.lankhorst, mripard, tzimmermann, airlied, simona,
robh, krzk+dt, conor+dt, mcoquelin.stm32, alexandre.torgue,
matthias.bgg, angelogioacchino.delregno, andi.shyti, djakov,
broonie, jitao.shi, ck.hu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-stm32, linux-arm-kernel, justin.yeh,
jason-jh.lin, kernel
This series part 1 of a huge restructuring of the entire multimedia
part of MediaTek SoCs, especially mediatek-drm, and contains only a
set of changes that don't require any simultaneous updates in the
mediatek-drm driver.
This adds support for correctly advertising the MediaTek Mute-X IP
as a source of trigger signals (because that's what it is), hence
for adding #trigger-source-cells in the Mute-X devicetree node and
for specifying a Mute-X trigger-source in all of the MTK Display
Controller components supporting or requiring one, as previously
it was kind of hacked up as a static array in the Mute-X driver,
for both MDP and DISP components, which is, well, depending on the
point of view, actually wrong.
Moreover, this goes on with the first part for a rework of MediaTek
MMSYS, which is a requirement for the upcoming huge restructuring
of the mediatek-drm driver; this starts adding boilerplate required
for setting up MMSYS entries with decoupling of "component type" to
"component instance number".
As of now, all of the components in MediaTek DRM, hence also in the
MMSYS driver, are thrown in a catch-all enumeration that does not
make any distinction between Type-Instance relationship, and it is
like so (mock-up names ahead):
DISPLAY_DITHER0
DISPLAY_DITHER1
DISPLAY_DSI0
DISPLAY_DSI1
... and so on.
Since the number of components is now becoming uncontrollably large,
the catch-all enumeration poses a big issue as the mediatek-drm driver
is allocating a huge array that will be only half full (optimistically,
because usually it's way less than half full) and with repeated ops
assignment for each and every instance of the very same Sub-IP,
effectively treating every instance of a Sub-IP like it is completely
different from one another (for example, like DSI0 and DSI1 are as
different as DITHER0 and DSI1).
This has to change. It had to change months ago, but now it has become
not only a maintenance burden, but also a... (sorry) big mess.
And well, that... especially looking forward to add support for newer
SoCs, using even more components in one pipeline, and using different
and newer components (of new types...), making the catch-all enum to
grow of another ~20 entries or more.
So, this is PART 1 of this huge restructuring, which will impact many
drivers, including soc/mediatek's mutex and mmsys, most of drm/mediatek
and, in the future, also media/mediatek/mtk-mdp3 (and eventually its
firmwareless implementation which, for components handling, will be
as complicated as mediatek-drm and, without this restructuring, would
be yet another boulder).
AngeloGioacchino Del Regno (6):
dt-bindings: soc: mediatek: mutex: Improve title and description
dt-bindings: soc: mediatek: mutex: Allow #trigger-source-cells
dt-bindings: display: mediatek: Allow trigger-sources on relevant HW
soc: mediatek: mtk-mutex: Add new functions to add/remove triggers
soc: mediatek: mtk-mmsys: Rework routes to specify component ID
soc: mediatek: mtk-mmsys: Use MMSYS_ROUTE() in default routing table
.../display/mediatek/mediatek,aal.yaml | 3 +
.../display/mediatek/mediatek,ccorr.yaml | 3 +
.../display/mediatek/mediatek,color.yaml | 3 +
.../display/mediatek/mediatek,dither.yaml | 3 +
.../display/mediatek/mediatek,dp.yaml | 3 +
.../display/mediatek/mediatek,dpi.yaml | 3 +
.../display/mediatek/mediatek,dsc.yaml | 3 +
.../display/mediatek/mediatek,dsi.yaml | 3 +
.../display/mediatek/mediatek,ethdr.yaml | 3 +
.../display/mediatek/mediatek,gamma.yaml | 3 +
.../display/mediatek/mediatek,merge.yaml | 3 +
.../display/mediatek/mediatek,od.yaml | 3 +
.../display/mediatek/mediatek,ovl-2l.yaml | 3 +
.../display/mediatek/mediatek,ovl.yaml | 3 +
.../display/mediatek/mediatek,padding.yaml | 3 +
.../display/mediatek/mediatek,postmask.yaml | 3 +
.../display/mediatek/mediatek,rdma.yaml | 3 +
.../display/mediatek/mediatek,split.yaml | 3 +
.../display/mediatek/mediatek,ufoe.yaml | 3 +
.../display/mediatek/mediatek,wdma.yaml | 3 +
.../bindings/soc/mediatek/mediatek,mutex.yaml | 21 +-
drivers/soc/mediatek/mt6893-mmsys.h | 34 +-
drivers/soc/mediatek/mt8167-mmsys.h | 21 +-
drivers/soc/mediatek/mt8173-mmsys.h | 28 +-
drivers/soc/mediatek/mt8183-mmsys.h | 14 +-
drivers/soc/mediatek/mt8186-mmsys.h | 22 +-
drivers/soc/mediatek/mt8188-mmsys.h | 78 ++---
drivers/soc/mediatek/mt8192-mmsys.h | 20 +-
drivers/soc/mediatek/mt8195-mmsys.h | 181 +++++------
drivers/soc/mediatek/mt8365-mmsys.h | 20 +-
drivers/soc/mediatek/mtk-mmsys.h | 299 ++++++++----------
drivers/soc/mediatek/mtk-mutex.c | 60 ++++
include/linux/soc/mediatek/mtk-mutex.h | 6 +
33 files changed, 474 insertions(+), 390 deletions(-)
--
2.54.0
^ permalink raw reply
* Re: [PATCH v3 1/3] KVM: arm64: skip pKVM cache flushes for non cacheable mappings
From: Vincent Donnefort @ 2026-07-01 13:31 UTC (permalink / raw)
To: Bradley Morgan
Cc: Marc Zyngier, Oliver Upton, Fuad Tabba, Joey Gouly, Steffen Eiden,
Suzuki K Poulose, Zenghui Yu, Catalin Marinas, Will Deacon,
Quentin Perret, Gavin Shan, Alexandru Elisei, linux-arm-kernel,
kvmarm, linux-kernel
In-Reply-To: <20260624160028.15591-2-include@grrlz.net>
On Wed, Jun 24, 2026 at 04:00:26PM +0000, Bradley Morgan wrote:
> pKVM keeps its own mapping list for stage 2 operations. Its flush path
> uses that list directly, so it lost the PTE attribute check done by the
> generic stage 2 walker.
>
> Record whether a mapping is cacheable and skip cache maintenance for
> mappings that are not cacheable.
>
> Fixes: e912efed485a ("KVM: arm64: Introduce the EL1 pKVM MMU")
> Signed-off-by: Bradley Morgan <include@grrlz.net>
> ---
> arch/arm64/kvm/pkvm.c | 51 ++++++++++++++++++++++++++++++++++---------
> 1 file changed, 41 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm64/kvm/pkvm.c b/arch/arm64/kvm/pkvm.c
> index 428723b1b0f5..ca6e823028c2 100644
> --- a/arch/arm64/kvm/pkvm.c
> +++ b/arch/arm64/kvm/pkvm.c
> @@ -302,9 +302,32 @@ static u64 __pkvm_mapping_start(struct pkvm_mapping *m)
> return m->gfn * PAGE_SIZE;
> }
>
> +#define PKVM_MAPPING_NR_PAGES_MASK GENMASK_ULL(47, 0)
> +#define PKVM_MAPPING_CACHEABLE BIT_ULL(48)
Probably better to make it "_NC". Protected VMs only support cacheable and they
also use struct pkvm_mapping.
> +
> +static u64 pkvm_mapping_nr_pages(struct pkvm_mapping *m)
> +{
> + return m->nr_pages & PKVM_MAPPING_NR_PAGES_MASK;
> +}
> +
> +static bool pkvm_mapping_is_cacheable(struct pkvm_mapping *m)
> +{
> + return m->nr_pages & PKVM_MAPPING_CACHEABLE;
> +}
> +
> +static void pkvm_mapping_set_nr_pages(struct pkvm_mapping *m, u64 nr_pages,
> + bool cacheable)
> +{
> + WARN_ON_ONCE(nr_pages & ~PKVM_MAPPING_NR_PAGES_MASK);
> +
> + m->nr_pages = nr_pages & PKVM_MAPPING_NR_PAGES_MASK;
> + if (cacheable)
> + m->nr_pages |= PKVM_MAPPING_CACHEABLE;
> +}
> +
> static u64 __pkvm_mapping_end(struct pkvm_mapping *m)
> {
> - return (m->gfn + m->nr_pages) * PAGE_SIZE - 1;
> + return (m->gfn + pkvm_mapping_nr_pages(m)) * PAGE_SIZE - 1;
> }
Perhaps using a bitfield would heavily simplify this code?
struct pkvm_mapping {
...
u64 nr_pages : 63
u64 flags : 1
}
Or alternatively, could just make nr_pages u32 and flags u32. nr_pages will not
exceed PMD_SIZE / PAGE_SIZE, which is at worst 8192 on 64K systems.
>
> INTERVAL_TREE_DEFINE(struct pkvm_mapping, node, u64, __subtree_last,
> @@ -350,7 +373,7 @@ static int __pkvm_pgtable_stage2_reclaim(struct kvm_pgtable *pgt, u64 start, u64
> continue;
>
> page = pfn_to_page(mapping->pfn);
> - WARN_ON_ONCE(mapping->nr_pages != 1);
> + WARN_ON_ONCE(pkvm_mapping_nr_pages(mapping) != 1);
> unpin_user_pages_dirty_lock(&page, 1, true);
> account_locked_vm(kvm->mm, 1, false);
> pkvm_mapping_remove(mapping, &pgt->pkvm_mappings);
> @@ -369,7 +392,7 @@ static int __pkvm_pgtable_stage2_unshare(struct kvm_pgtable *pgt, u64 start, u64
>
> for_each_mapping_in_range_safe(pgt, start, end, mapping) {
> ret = kvm_call_hyp_nvhe(__pkvm_host_unshare_guest, handle, mapping->gfn,
> - mapping->nr_pages);
> + pkvm_mapping_nr_pages(mapping));
> if (WARN_ON(ret))
> return ret;
> pkvm_mapping_remove(mapping, &pgt->pkvm_mappings);
> @@ -448,7 +471,7 @@ int pkvm_pgtable_stage2_map(struct kvm_pgtable *pgt, u64 addr, u64 size,
> * permission faults are handled in the relax_perms() path.
> */
> if (mapping) {
> - if (size == (mapping->nr_pages * PAGE_SIZE))
> + if (size == (pkvm_mapping_nr_pages(mapping) * PAGE_SIZE))
> return -EAGAIN;
>
> /*
> @@ -472,7 +495,9 @@ int pkvm_pgtable_stage2_map(struct kvm_pgtable *pgt, u64 addr, u64 size,
> swap(mapping, cache->mapping);
> mapping->gfn = gfn;
> mapping->pfn = pfn;
> - mapping->nr_pages = size / PAGE_SIZE;
> + pkvm_mapping_set_nr_pages(mapping, size / PAGE_SIZE,
> + !(prot & (KVM_PGTABLE_PROT_DEVICE |
> + KVM_PGTABLE_PROT_NORMAL_NC)));
> pkvm_mapping_insert(mapping, &pgt->pkvm_mappings);
>
> return ret;
> @@ -503,7 +528,7 @@ int pkvm_pgtable_stage2_wrprotect(struct kvm_pgtable *pgt, u64 addr, u64 size)
> lockdep_assert_held(&kvm->mmu_lock);
> for_each_mapping_in_range_safe(pgt, addr, addr + size, mapping) {
> ret = kvm_call_hyp_nvhe(__pkvm_host_wrprotect_guest, handle, mapping->gfn,
> - mapping->nr_pages);
> + pkvm_mapping_nr_pages(mapping));
> if (WARN_ON(ret))
> break;
> }
> @@ -517,9 +542,13 @@ int pkvm_pgtable_stage2_flush(struct kvm_pgtable *pgt, u64 addr, u64 size)
> struct pkvm_mapping *mapping;
>
> lockdep_assert_held(&kvm->mmu_lock);
> - for_each_mapping_in_range_safe(pgt, addr, addr + size, mapping)
> + for_each_mapping_in_range_safe(pgt, addr, addr + size, mapping) {
> + if (!pkvm_mapping_is_cacheable(mapping))
> + continue;
> +
> __clean_dcache_guest_page(pfn_to_kaddr(mapping->pfn),
> - PAGE_SIZE * mapping->nr_pages);
> + PAGE_SIZE * pkvm_mapping_nr_pages(mapping));
> + }
>
> return 0;
> }
> @@ -536,8 +565,10 @@ bool pkvm_pgtable_stage2_test_clear_young(struct kvm_pgtable *pgt, u64 addr, u64
>
> lockdep_assert_held(&kvm->mmu_lock);
> for_each_mapping_in_range_safe(pgt, addr, addr + size, mapping)
> - young |= kvm_call_hyp_nvhe(__pkvm_host_test_clear_young_guest, handle, mapping->gfn,
> - mapping->nr_pages, mkold);
> + young |= kvm_call_hyp_nvhe(__pkvm_host_test_clear_young_guest,
> + handle, mapping->gfn,
> + pkvm_mapping_nr_pages(mapping),
> + mkold);
>
> return young;
> }
> --
> 2.53.0
>
^ permalink raw reply
* Re: [PATCH rc v7 0/7] iommu/arm-smmu-v3: Fix device crash on kdump kernel
From: Pranjal Shrivastava @ 2026-07-01 13:36 UTC (permalink / raw)
To: Mostafa Saleh
Cc: Jason Gunthorpe, Nicolin Chen, will, robin.murphy, joro, kees,
baolu.lu, kevin.tian, miko.lenczewski, linux-arm-kernel, iommu,
linux-kernel, stable, jamien
In-Reply-To: <akUQj2pa1W-MekgF@google.com>
On Wed, Jul 01, 2026 at 01:05:19PM +0000, Mostafa Saleh wrote:
> On Tue, Jun 30, 2026 at 03:59:42PM -0300, Jason Gunthorpe wrote:
> > On Tue, Jun 30, 2026 at 03:33:12PM +0000, Mostafa Saleh wrote:
> >
> > > For example patch#1 verifies log2size and split and both are read
> > > from HW registers. Same for the base address or other addresses as
> > > the page tables, they might be corrupted due to a buggy driver.
> > > My point is that, it is really hard to assume that the previous state
> > > of registers/STE/page-tables were valid or even consistent, when the
> > > kernel crashed and did not transition the state gracefully.
> >
> > Sure, and this mechanism is probably not very useful for debugging
> > these kinds of errors in the SMMU driver. Oh well, that isn't a common
> > source of kernel crashes :)
>
> I hope not! Although memory corruption can happen due to many other
> reasons :/
>
> I am not trying to bikeshed, but I wondering if there is a more
> reliable way rather than doing archaeology from a panicked kernel
> SMMUv3 configuration, as I am worried that will be even harder to
> debug if it goes wrong.
>
> >
> > > Similarly for TLBs, the kernel might have panicked in the middle of an
> > > unmap or free domain. (not to mention what that means for RPM where
> > > a device reset with unknown TLBs)
> >
> > TLB is fine. kdump works by carving out a chunk of memory for the
> > future crash kernel. When the kernel boots it ignores all the memory
> > used by the prior kernel. So DMA can keep running into the old kernels
> > memory with no issue. It doesn't matter if the TLBs are inconsistent or
> > not.
>
> Ideally if a TLB is to be missed (because of the panic), it should not
> point to kdump memory as it is carved-out. However, it is still a leap to
> assume that the TLBs are in a good shape as I mentioned with RPM (or
> even if the device resets transiently for some reason) it can end up
> with garbage in its TLBs.
Regarding RPM, I can say that even if we panicked while SMMU was off in
the previous kernel, when we call device_reset() in the new kernel we
still issue the TLBI_ALL with the reset.
However, I agree with the overall problem, i.e. IF an active device
unmaps the DMA addr after the transaction in the previous kernel,
(with the SMMU powered ON) but the TLBI was missed due to a crash/panic,
Any new DMA in the new kernel may alias onto a memory in the previous
(crashed) kernel, not the kdump kernel.
That way, I agree that continuing DMA could be problematic as we may
corrupt the very memory we'd wanna analyze for a crash.
Thanks,
Praan
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