* Re: [PATCH v2 1/5] arm64: dts: lx2160a: transition to device-specific SerDes compatible strings
From: Frank Li @ 2026-07-01 14:27 UTC (permalink / raw)
To: Ioana Ciornei
Cc: Frank.Li, robh, krzk+dt, conor+dt, devicetree, vladimir.oltean,
linux-arm-kernel, linux-kernel, imx
In-Reply-To: <20260701131137.940145-2-ioana.ciornei@nxp.com>
On Wed, Jul 01, 2026 at 04:11:33PM +0300, Ioana Ciornei wrote:
> From: Vladimir Oltean <vladimir.oltean@nxp.com>
>
> Align to the modern fsl,lynx-28g.yaml binding, where the SoC and SerDes
> instance is present in the compatible string, to allow reliable per-lane
> capability detection and per-lane customization of electrical properties.
>
> The modern bindings are backward-incompatible with old kernels, due
> to the consumer phandles being either in one form or in another, as
> explained here:
> https://lore.kernel.org/lkml/20250930140735.mvo3jii7wgmzh2bs@skbuf/
>
> One of the major differences between the LX2160A and LX2162A is the
> SerDes. So far, LX2162A has used fsl-lx2160a-rev2.dtsi, but we need to
> split that up even further, and derive a fsl-lx2162a.dtsi which
> overrides the SerDes properties.
>
> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
> ---
> Changes in v2:
> - Enable serdes_1 on all board DTs that has consumers for it.
> - Use the proper name for serdes_3 in fsl-lx2162a.dtsi.
> - Remove paragraph from commit message which mentioned some consumer
> changes that are no longer needed nor part of the commit.
> ---
> .../freescale/fsl-lx2160a-clearfog-itx.dtsi | 4 +
> .../dts/freescale/fsl-lx2160a-half-twins.dts | 4 +
> .../boot/dts/freescale/fsl-lx2160a-rdb.dts | 4 +
> .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 150 +++++++++++++++++-
> .../dts/freescale/fsl-lx2162a-clearfog.dts | 6 +-
> .../boot/dts/freescale/fsl-lx2162a-qds.dts | 2 +-
> .../arm64/boot/dts/freescale/fsl-lx2162a.dtsi | 24 +++
> 7 files changed, 190 insertions(+), 4 deletions(-)
> create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2162a.dtsi
>
...
>
> +&serdes_1 {
> + status = "okay";
> +};
> +
Can you try keep alphabet order? may old file is not ordersed, but try
best, at least should before &uart0
> &uart1 {
> status = "okay";
> };
> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> index 1d73abffa6b7..a687eb3e3190 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
Please split chips dtsi and boards dts to two patch.
> @@ -621,17 +621,163 @@ soc: soc {
> ranges;
> dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
>
> + /* Note on the interpretation of SerDes lane numbering from
> + * LX2160ARM lane mappings for RCW[SRDS_PRTCL_S1]:
> + * The letters (A-H) correspond to logical lane numbers in the
> + * SerDes register map (lane A's registers start with LNAGCR0),
> + * while the numbers (0-7) correspond to physical lanes as
> + * routed to pins. SerDes block #1 is flipped in the LX2160A
> + * floorplan (logical lane A goes to physical lane 7's pins),
> + * while SerDes blocks #2 and #3 are not. The lanes below are
> + * listed right to left when looking at that table.
> + * Both the numbers and the letters are according to the logical
> + * numbering scheme, and do not account for the flipping.
> + */
...
> + compatible = "fsl,lx2160a-serdes3";
> + reg = <0x0 0x1ec0000 0x0 0x1e30>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
status should be last property
> + #phy-cells = <1>;
> +
> + serdes_3_lane_a: phy@0 {
> + reg = <0>;
> + #phy-cells = <0>;
> + };
> +
...
> +
> +#include "fsl-lx2160a-rev2.dtsi"
> +
> +&serdes_1 {
> + compatible = "fsl,lx2162a-serdes1", "fsl,lynx-28g";
> +
> + /delete-node/ phy@0;
> + /delete-node/ phy@1;
> + /delete-node/ phy@2;
> + /delete-node/ phy@3;
Now, do not perfer delete-node. if ver2 is not include phy@0, ...
create ver2 files, let ver2 include it. Now most people like A + B, not
A - B.
Frank
> +};
> +
> +&serdes_2 {
> + compatible = "fsl,lx2162a-serdes2", "fsl,lynx-28g";
> +};
> +
> +&soc {
> + /delete-node/ phy@1ec0000;
> +};
> --
> 2.25.1
>
>
^ permalink raw reply
* [PATCH v4 net-next 2/2] arm64: dts: ti: Add PLL1 refclk to J784S4 SoC SERDES node
From: Gokul Praveen @ 2026-07-01 14:24 UTC (permalink / raw)
To: conor+dt, devicetree, krzk+dt, linux-arm-kernel, linux-kernel,
linux-phy, neil.armstrong, nm, robh, sjakhade, kristo, vigneshr,
vkoul, yamonkar, g-praveen
In-Reply-To: <20260701142457.81874-1-g-praveen@ti.com>
Add PLL1 refclk to "clocks" and "clock-names" parameter of SERDES0,
SERDES1,SERDES2 and SERDES4 node as "assigned clocks" parameter has PLL1
and serdes multilink configuration fails without PLL1.
Signed-off-by: Gokul Praveen <g-praveen@ti.com>
---
arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi | 9 ++++++---
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 3 ++-
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
index c2636e624f18..e5224bd7f538 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
@@ -1149,8 +1149,9 @@ serdes0: serdes@5060000 {
resets = <&serdes_wiz0 0>;
reset-names = "torrent_reset";
clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
<&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
- clock-names = "refclk", "phy_en_refclk";
+ clock-names = "refclk", "pll1_refclk", "phy_en_refclk";
assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
<&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
<&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
@@ -1186,8 +1187,9 @@ serdes1: serdes@5070000 {
resets = <&serdes_wiz1 0>;
reset-names = "torrent_reset";
clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>,
<&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>;
- clock-names = "refclk", "phy_en_refclk";
+ clock-names = "refclk", "pll1_refclk", "phy_en_refclk";
assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
<&serdes_wiz1 TI_WIZ_PLL1_REFCLK>,
<&serdes_wiz1 TI_WIZ_REFCLK_DIG>;
@@ -1229,8 +1231,9 @@ serdes4: serdes@5050000 {
resets = <&serdes_wiz4 0>;
reset-names = "torrent_reset";
clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>,
<&serdes_wiz4 TI_WIZ_PHY_EN_REFCLK>;
- clock-names = "refclk", "phy_en_refclk";
+ clock-names = "refclk", "pll1_refclk", "phy_en_refclk";
assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
<&serdes_wiz4 TI_WIZ_PLL1_REFCLK>,
<&serdes_wiz4 TI_WIZ_REFCLK_DIG>;
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index 78fcd0c40abc..53109e2fe527 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -122,8 +122,9 @@ serdes2: serdes@5020000 {
resets = <&serdes_wiz2 0>;
reset-names = "torrent_reset";
clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz2 TI_WIZ_PLL1_REFCLK>,
<&serdes_wiz2 TI_WIZ_PHY_EN_REFCLK>;
- clock-names = "refclk", "phy_en_refclk";
+ clock-names = "refclk", "pll1_refclk", "phy_en_refclk";
assigned-clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>,
<&serdes_wiz2 TI_WIZ_PLL1_REFCLK>,
<&serdes_wiz2 TI_WIZ_REFCLK_DIG>;
--
2.34.1
^ permalink raw reply related
* [PATCH v4 net-next 0/2] Add multilink SERDES configuration support
From: Gokul Praveen @ 2026-07-01 14:24 UTC (permalink / raw)
To: conor+dt, devicetree, krzk+dt, linux-arm-kernel, linux-kernel,
linux-phy, neil.armstrong, nm, robh, sjakhade, kristo, vigneshr,
vkoul, yamonkar, g-praveen
Add multilink SERDES configuration support for SERDES0,SERDES1
SERDES2 and SERDES4 node on TI J784S4 EVM.
This patch series add multilink SERDES configurations support
for SERDES0,SERDES1 SERDES2 and SERDES4 node on TI J784S4 EVM
by adding the PLL1 refclk.
Gokul Praveen (2):
dt-bindings: phy: cadence-torrent: Update property values to support 3
clocks
arm64: dts: ti: Add PLL1 refclk to J784S4 SoC SERDES node
.../bindings/phy/phy-cadence-torrent.yaml | 16 ++++++++++++----
.../dts/ti/k3-j784s4-j742s2-main-common.dtsi | 9 ++++++---
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 3 ++-
3 files changed, 20 insertions(+), 8 deletions(-)
--
2.34.1
^ permalink raw reply
* Re: [PATCH 40/42] dt-bindings: display: mediatek: Introduce MT8196 Image Resizer
From: Rob Herring (Arm) @ 2026-07-01 14:23 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: dri-devel, p.zabel, tzimmermann, justin.yeh, krzk+dt,
linux-kernel, linux-arm-kernel, kernel, mripard, chunkuang.hu,
maarten.lankhorst, conor+dt, matthias.bgg, linux-mediatek,
jason-jh.lin, devicetree, airlied, simona
In-Reply-To: <20260701122057.19648-41-angelogioacchino.delregno@collabora.com>
On Wed, 01 Jul 2026 14:20:55 +0200, AngeloGioacchino Del Regno wrote:
> Add documentation for the Image Resizer "RSZ" Scaler block found
> in the MT8196 SoC and its variants.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> .../display/mediatek/mediatek,mt8196-rsz.yaml | 97 +++++++++++++++++++
> 1 file changed, 97 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mt8196-rsz.yaml
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8196-rsz.yaml: ignoring, error in schema: properties: compatible
Documentation/devicetree/bindings/display/mediatek/mediatek,mt8196-rsz.example.dtb: /example-0/scaler@329d0000: failed to match any schema with compatible: ['mediatek,mt8196-disp-rsz']
doc reference errors (make refcheckdocs):
See https://patchwork.kernel.org/project/devicetree/patch/20260701122057.19648-41-angelogioacchino.delregno@collabora.com
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
^ permalink raw reply
* Re: [PATCH 30/42] dt-bindings: display: mediatek: Introduce MT8196 Output Processor
From: Rob Herring (Arm) @ 2026-07-01 14:23 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: linux-kernel, matthias.bgg, jason-jh.lin, airlied,
maarten.lankhorst, conor+dt, mripard, kernel, tzimmermann,
dri-devel, devicetree, chunkuang.hu, simona, linux-arm-kernel,
p.zabel, justin.yeh, linux-mediatek, krzk+dt
In-Reply-To: <20260701122057.19648-31-angelogioacchino.delregno@collabora.com>
On Wed, 01 Jul 2026 14:20:45 +0200, AngeloGioacchino Del Regno wrote:
> Add documentation for the Overlay Output Processor IP found in
> the newer Generation SoCs like MT8196, MT8894, MT6991, and their
> variants.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> .../mediatek/mediatek,mt8196-outproc.yaml | 107 ++++++++++++++++++
> 1 file changed, 107 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mt8196-outproc.yaml
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8196-outproc.yaml: ignoring, error in schema: properties: compatible
Documentation/devicetree/bindings/display/mediatek/mediatek,mt8196-outproc.example.dtb: /example-0/outproc@32970000: failed to match any schema with compatible: ['mediatek,mt8196-disp-outproc']
doc reference errors (make refcheckdocs):
See https://patchwork.kernel.org/project/devicetree/patch/20260701122057.19648-31-angelogioacchino.delregno@collabora.com
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
^ permalink raw reply
* Re: [PATCH 38/42] dt-bindings: display: mediatek: Introduce MT8196 2D Sharpness Processor
From: Rob Herring (Arm) @ 2026-07-01 14:23 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: linux-kernel, chunkuang.hu, matthias.bgg, mripard, jason-jh.lin,
kernel, devicetree, justin.yeh, simona, p.zabel, tzimmermann,
conor+dt, airlied, maarten.lankhorst, dri-devel, krzk+dt,
linux-mediatek, linux-arm-kernel
In-Reply-To: <20260701122057.19648-39-angelogioacchino.delregno@collabora.com>
On Wed, 01 Jul 2026 14:20:53 +0200, AngeloGioacchino Del Regno wrote:
> Add documentation for the Two-Dimension Sharpness Processor, or
> "TDSHP", found in many MediaTek SoCs including MT8196 and its
> variants.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> .../mediatek/mediatek,mt8196-tdshp.yaml | 98 +++++++++++++++++++
> 1 file changed, 98 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mt8196-tdshp.yaml
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8196-tdshp.yaml: ignoring, error in schema: properties: compatible
Documentation/devicetree/bindings/display/mediatek/mediatek,mt8196-tdshp.example.dtb: /example-0/tdshp@321e0000: failed to match any schema with compatible: ['mediatek,mt8196-disp-tdshp']
doc reference errors (make refcheckdocs):
See https://patchwork.kernel.org/project/devicetree/patch/20260701122057.19648-39-angelogioacchino.delregno@collabora.com
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
^ permalink raw reply
* Re: [PATCH 28/42] dt-bindings: display: mediatek: Introduce MT8196 extended DMA Engine
From: Rob Herring (Arm) @ 2026-07-01 14:23 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: conor+dt, mripard, devicetree, maarten.lankhorst, p.zabel,
krzk+dt, chunkuang.hu, matthias.bgg, tzimmermann, airlied,
linux-mediatek, simona, dri-devel, linux-kernel, kernel,
linux-arm-kernel, jason-jh.lin, justin.yeh
In-Reply-To: <20260701122057.19648-29-angelogioacchino.delregno@collabora.com>
On Wed, 01 Jul 2026 14:20:43 +0200, AngeloGioacchino Del Regno wrote:
> Add documentation for the extended DMA Engine (exDMA) IP found in
> the newer generation SoCs like MT8196, MT8894, MT6991, and their
> variants.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> .../mediatek/mediatek,mt8196-exdma.yaml | 104 ++++++++++++++++++
> 1 file changed, 104 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mt8196-exdma.yaml
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8196-exdma.yaml: ignoring, error in schema: properties: compatible
Documentation/devicetree/bindings/display/mediatek/mediatek,mt8196-exdma.example.dtb: /example-0/dma-controller@32850000: failed to match any schema with compatible: ['mediatek,mt8196-disp-exdma']
doc reference errors (make refcheckdocs):
See https://patchwork.kernel.org/project/devicetree/patch/20260701122057.19648-29-angelogioacchino.delregno@collabora.com
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
^ permalink raw reply
* Re: [PATCH 26/42] dt-bindings: display: mediatek: Introduce MT8196 Layer Blender
From: Rob Herring (Arm) @ 2026-07-01 14:23 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: linux-kernel, kernel, airlied, dri-devel, mripard, conor+dt,
justin.yeh, devicetree, jason-jh.lin, linux-arm-kernel, simona,
chunkuang.hu, tzimmermann, linux-mediatek, matthias.bgg,
maarten.lankhorst, p.zabel, krzk+dt
In-Reply-To: <20260701122057.19648-27-angelogioacchino.delregno@collabora.com>
On Wed, 01 Jul 2026 14:20:41 +0200, AngeloGioacchino Del Regno wrote:
> Add documentation for the Overlay Layer Blender IP found in the
> newer generation SoCs like MT8196, MT8894, MT6991, and their
> variants.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> .../mediatek/mediatek,mt8196-blender.yaml | 97 +++++++++++++++++++
> 1 file changed, 97 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mt8196-blender.yaml
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8196-blender.yaml: ignoring, error in schema: properties: compatible
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8196-blender.yaml: properties:compatible: [{'const': 'mediatek,mt8196-disp-blender'}] is not of type 'object', 'boolean'
from schema $id: http://devicetree.org/meta-schemas/keywords.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8196-blender.yaml: properties:compatible: [{'const': 'mediatek,mt8196-disp-blender'}] is not of type 'object', 'boolean'
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8196-blender.yaml: properties:compatible: [{'const': 'mediatek,mt8196-disp-blender'}] is not of type 'object', 'boolean'
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8196-blender.yaml: properties:compatible: [{'const': 'mediatek,mt8196-disp-blender'}] is not of type 'object', 'boolean'
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8196-blender.yaml: properties:compatible: [{'const': 'mediatek,mt8196-disp-blender'}] is not of type 'object', 'boolean'
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8196-blender.yaml: properties:compatible: [{'const': 'mediatek,mt8196-disp-blender'}] is not of type 'object', 'boolean'
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8196-blender.yaml: properties:compatible: [{'const': 'mediatek,mt8196-disp-blender'}] is not of type 'object', 'boolean'
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8196-blender.yaml: properties:compatible: [{'const': 'mediatek,mt8196-disp-blender'}] is not of type 'object', 'boolean'
Documentation/devicetree/bindings/display/mediatek/mediatek,mt8196-blender.example.dtb: /example-0/blender@328e0000: failed to match any schema with compatible: ['mediatek,mt8196-disp-blender']
doc reference errors (make refcheckdocs):
See https://patchwork.kernel.org/project/devicetree/patch/20260701122057.19648-27-angelogioacchino.delregno@collabora.com
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
^ permalink raw reply
* Re: [PATCH 23/42] dt-bindings: display: mediatek: Introduce Digital Video Output HW
From: Rob Herring (Arm) @ 2026-07-01 14:23 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: krzk+dt, dri-devel, linux-kernel, p.zabel, kernel, tzimmermann,
chunkuang.hu, simona, linux-arm-kernel, jason-jh.lin, airlied,
conor+dt, maarten.lankhorst, linux-mediatek, matthias.bgg,
mripard, devicetree, justin.yeh
In-Reply-To: <20260701122057.19648-24-angelogioacchino.delregno@collabora.com>
On Wed, 01 Jul 2026 14:20:38 +0200, AngeloGioacchino Del Regno wrote:
> Add documentation for the Digital Video Output (DVO) IP found in
> the newer generation SoCs MT8196, MT8189 and their variants.
>
> This is effectively a more capable block replacing the DisplayPort
> Interface (DPI/DP_INTF) one found in older SoCs.
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> .../display/mediatek/mediatek,mt8196-dvo.yaml | 142 ++++++++++++++++++
> 1 file changed, 142 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mt8196-dvo.yaml
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8196-dvo.yaml: ignoring, error in schema: properties: compatible
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8196-dvo.yaml: properties:compatible: [{'const': 'mediatek,mt8189-dp-dvo'}, {'const': 'mediatek,mt8189-edp-dvo'}, {'const': 'mediatek,mt8196-edp-dvo'}] is not of type 'object', 'boolean'
from schema $id: http://devicetree.org/meta-schemas/keywords.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8196-dvo.yaml: properties:compatible: [{'const': 'mediatek,mt8189-dp-dvo'}, {'const': 'mediatek,mt8189-edp-dvo'}, {'const': 'mediatek,mt8196-edp-dvo'}] is not of type 'object', 'boolean'
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8196-dvo.yaml: properties:compatible: [{'const': 'mediatek,mt8189-dp-dvo'}, {'const': 'mediatek,mt8189-edp-dvo'}, {'const': 'mediatek,mt8196-edp-dvo'}] is not of type 'object', 'boolean'
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8196-dvo.yaml: properties:compatible: [{'const': 'mediatek,mt8189-dp-dvo'}, {'const': 'mediatek,mt8189-edp-dvo'}, {'const': 'mediatek,mt8196-edp-dvo'}] is not of type 'object', 'boolean'
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8196-dvo.yaml: properties:compatible: [{'const': 'mediatek,mt8189-dp-dvo'}, {'const': 'mediatek,mt8189-edp-dvo'}, {'const': 'mediatek,mt8196-edp-dvo'}] is not of type 'object', 'boolean'
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8196-dvo.yaml: properties:compatible: [{'const': 'mediatek,mt8189-dp-dvo'}, {'const': 'mediatek,mt8189-edp-dvo'}, {'const': 'mediatek,mt8196-edp-dvo'}] is not of type 'object', 'boolean'
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8196-dvo.yaml: properties:compatible: [{'const': 'mediatek,mt8189-dp-dvo'}, {'const': 'mediatek,mt8189-edp-dvo'}, {'const': 'mediatek,mt8196-edp-dvo'}] is not of type 'object', 'boolean'
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8196-dvo.yaml: properties:compatible: [{'const': 'mediatek,mt8189-dp-dvo'}, {'const': 'mediatek,mt8189-edp-dvo'}, {'const': 'mediatek,mt8196-edp-dvo'}] is not of type 'object', 'boolean'
Traceback (most recent call last):
File "/usr/local/bin/dt-doc-validate", line 8, in <module>
sys.exit(main())
~~~~^^
File "/usr/local/lib/python3.13/dist-packages/dtschema/doc_validate.py", line 66, in main
ret |= check_doc(f)
~~~~~~~~~^^^
File "/usr/local/lib/python3.13/dist-packages/dtschema/doc_validate.py", line 37, in check_doc
dtsch.check_schema_refs()
~~~~~~~~~~~~~~~~~~~~~~~^^
File "/usr/local/lib/python3.13/dist-packages/dtschema/schema.py", line 242, in check_schema_refs
self._check_schema_refs(resolver, self)
~~~~~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/usr/local/lib/python3.13/dist-packages/dtschema/schema.py", line 212, in _check_schema_refs
self._check_schema_refs(resolver, v, parent=k, is_common=is_common,
~~~~~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
has_constraint=has_constraint)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/usr/local/lib/python3.13/dist-packages/dtschema/schema.py", line 212, in _check_schema_refs
self._check_schema_refs(resolver, v, parent=k, is_common=is_common,
~~~~~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
has_constraint=has_constraint)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
File "/usr/local/lib/python3.13/dist-packages/dtschema/schema.py", line 203, in _check_schema_refs
ref_sch = resolver.lookup(schema['$ref']).contents
~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/usr/local/lib/python3.13/dist-packages/referencing/_core.py", line 682, in lookup
retrieved = self._registry.get_or_retrieve(uri)
File "/usr/local/lib/python3.13/dist-packages/referencing/_core.py", line 422, in get_or_retrieve
registry = self.crawl()
File "/usr/local/lib/python3.13/dist-packages/referencing/_core.py", line 500, in crawl
id = resource.id()
File "/usr/local/lib/python3.13/dist-packages/referencing/_core.py", line 231, in id
id = self._specification.id_of(self.contents)
File "/usr/local/lib/python3.13/dist-packages/referencing/jsonschema.py", line 50, in _dollar_id
return contents.get("$id")
^^^^^^^^^^^^
AttributeError: 'list' object has no attribute 'get'
Documentation/devicetree/bindings/display/mediatek/mediatek,mt8196-dvo.example.dtb: /example-0/dvo@324c0000: failed to match any schema with compatible: ['mediatek,mt8196-edp-dvo']
doc reference errors (make refcheckdocs):
See https://patchwork.kernel.org/project/devicetree/patch/20260701122057.19648-24-angelogioacchino.delregno@collabora.com
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
^ permalink raw reply
* [PATCH v7 2/2] m68k: defconfig: update stmark2 defconfig
From: Angelo Dureghello @ 2026-07-01 14:17 UTC (permalink / raw)
To: Jonathan Cameron, David Lechner, Nuno Sá, Andy Shevchenko,
Geert Uytterhoeven, Maxime Coquelin, Alexandre Torgue
Cc: linux-kernel, linux-iio, linux-m68k, linux-stm32,
linux-arm-kernel, Angelo Dureghello
In-Reply-To: <20260701-wip-stmark2-dac-v7-0-ff8fdcc8010a@baylibre.com>
From: Angelo Dureghello <adureghello@baylibre.com>
Update stmark2 defconfig enabling MCF5441X DACs.
Signed-off-by: Angelo Dureghello <adureghello@baylibre.com>
---
Changes for v5:
- move this patch after new Kconfig symbols are added
---
arch/m68k/configs/stmark2_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/m68k/configs/stmark2_defconfig b/arch/m68k/configs/stmark2_defconfig
index b3fb95f73a95..3941113bc60b 100644
--- a/arch/m68k/configs/stmark2_defconfig
+++ b/arch/m68k/configs/stmark2_defconfig
@@ -76,6 +76,8 @@ CONFIG_DMADEVICES=y
CONFIG_MCF_EDMA=y
# CONFIG_VIRTIO_MENU is not set
# CONFIG_VHOST_MENU is not set
+CONFIG_IIO=y
+CONFIG_MCF54415_DAC=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
CONFIG_EXT2_FS_POSIX_ACL=y
--
2.54.0
^ permalink raw reply related
* [PATCH v7 1/2] iio: dac: add mcf54415 DAC
From: Angelo Dureghello @ 2026-07-01 14:17 UTC (permalink / raw)
To: Jonathan Cameron, David Lechner, Nuno Sá, Andy Shevchenko,
Geert Uytterhoeven, Maxime Coquelin, Alexandre Torgue
Cc: linux-kernel, linux-iio, linux-m68k, linux-stm32,
linux-arm-kernel, Angelo Dureghello, Andy Shevchenko
In-Reply-To: <20260701-wip-stmark2-dac-v7-0-ff8fdcc8010a@baylibre.com>
From: Angelo Dureghello <adureghello@baylibre.com>
Add basic version of mcf54415 DAC driver. DAC is embedded in the SoC and
DAC configuration registers are mapped in the internal IO address space.
The DAC accepts a 12-bit digital signal and creates a monotonic 12-bit
analog output varying from DAC_VREFL to DAC_VREFH. The DAC module
consists of a conversion unit, an output amplifier, and the associated
digital control blocks. Default register values for DAC_VREFL and DAC_VREFH
are respectively 0 and 0xfff, left untouched in this initial version.
This initial version of the driver is minimalistic, "output raw" only, to
be extended in the future. DMA and external sync are disabled, default mode
is high speed, default format is right-justified 12-bit on 16-bit word.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com>
Signed-off-by: Angelo Dureghello <adureghello@baylibre.com>
---
Changes in v2:
- remove tests from commit message, moved to patch 0
- remove additional blank lines
- remove dead code and unused definitions
- use regmap
- add limit check on raw write
- non functional style fixes
- add COMPILE_TEST to Kconfig
Changes in v3:
- add comments where needed
- code style changes
- remove unneeded variables
- use regmap_set_bits where possible
- remove macro not needed to define a single channel
- set up regmap to big_endian accesses for next patches that will come,
that will adjust ColdFire readx/writex as standard LE (links in 0/x).
- add return value check on regmap calls
- sashiko: remove unneeded .io_port from regmap init.
- sashiko: add select REGMAP_MMIO in Kconfig
Changes in v4:
- remove unused includes
- sashiko: return "ret" as regmap_read ret value in case of error
- sashiko: using u32 as regmap_read value
- use local variable in mcf54415_dac_init() for better readability
- sashiko: check mcf54415_dac_init return value also in resume()
Changes in v5:
- commit syntax fixes
- minor code style fixes
- use include <linux/type.h>
- removed unneeded cast
- disable clock in case of DAC init error
- use unsigned int for regmap_read and GENMASK for masking 12 bits
- add id table to match "mcfdac" platform device name
Changes in v6:
- removed pm ops, can't be tested for mcf54415 with mmu enabled
- Kconfig desc line rewrap
- minor coding style fixes
Changes in v7:
- remove unused includes
- remove unneeded call to platform_set_drvdata()
---
drivers/iio/dac/Kconfig | 11 +++
drivers/iio/dac/Makefile | 1 +
drivers/iio/dac/mcf54415_dac.c | 180 +++++++++++++++++++++++++++++++++++++++++
3 files changed, 192 insertions(+)
diff --git a/drivers/iio/dac/Kconfig b/drivers/iio/dac/Kconfig
index 657c68e75542..ebf7144f922a 100644
--- a/drivers/iio/dac/Kconfig
+++ b/drivers/iio/dac/Kconfig
@@ -527,6 +527,17 @@ config MAX5821
Say yes here to build support for Maxim MAX5821
10 bits DAC.
+config MCF54415_DAC
+ tristate "NXP MCF54415 DAC driver"
+ depends on M5441x || COMPILE_TEST
+ select REGMAP_MMIO
+ help
+ Say yes here if you want to build support for NXP ColdFire
+ MCF54415/6/7/8 12-bit DAC module.
+
+ To compile this driver as a module, choose M here: the module
+ will be called mcf54415_dac.
+
config MCP4725
tristate "MCP4725/6 DAC driver"
depends on I2C
diff --git a/drivers/iio/dac/Makefile b/drivers/iio/dac/Makefile
index 003431798498..5d20d37e44ce 100644
--- a/drivers/iio/dac/Makefile
+++ b/drivers/iio/dac/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_MAX517) += max517.o
obj-$(CONFIG_MAX22007) += max22007.o
obj-$(CONFIG_MAX5522) += max5522.o
obj-$(CONFIG_MAX5821) += max5821.o
+obj-$(CONFIG_MCF54415_DAC) += mcf54415_dac.o
obj-$(CONFIG_MCP4725) += mcp4725.o
obj-$(CONFIG_MCP4728) += mcp4728.o
obj-$(CONFIG_MCP47FEB02) += mcp47feb02.o
diff --git a/drivers/iio/dac/mcf54415_dac.c b/drivers/iio/dac/mcf54415_dac.c
new file mode 100644
index 000000000000..e2c12241a534
--- /dev/null
+++ b/drivers/iio/dac/mcf54415_dac.c
@@ -0,0 +1,180 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * NXP mcf54415 DAC driver
+ *
+ * Copyright 2026 BayLibre - adureghello@baylibre.com
+ */
+
+#include <linux/bitfield.h>
+#include <linux/bits.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/types.h>
+
+#include <linux/iio/iio.h>
+
+#define MCF54415_DAC_CR 0x00
+#define MCF54415_DAC_CR_PDN BIT(0)
+#define MCF54415_DAC_CR_HSLS BIT(6)
+#define MCF54415_DAC_CR_WMLVL GENMASK(9, 8)
+#define MCF54415_DAC_CR_FILT BIT(12)
+
+#define MCF54415_DAC_DATA 0x02
+
+struct mcf54415_dac {
+ struct regmap *map;
+ struct clk *clk;
+};
+
+static const struct regmap_config mcf54415_dac_regmap_config = {
+ .reg_bits = 16,
+ .reg_stride = 2,
+ .val_bits = 16,
+ .max_register = 0x0c, /* DACX_FILTCNT, R.M. Table 30-2 */
+ .val_format_endian = REGMAP_ENDIAN_BIG,
+ .reg_format_endian = REGMAP_ENDIAN_BIG,
+};
+
+static int mcf54415_dac_init(struct mcf54415_dac *info)
+{
+ u16 val = MCF54415_DAC_CR_FILT | FIELD_PREP(MCF54415_DAC_CR_WMLVL, 1);
+ int ret;
+
+ /* Fixed defaults and enable DAC (bit 0 set to 0) */
+ ret = regmap_write(info->map, MCF54415_DAC_CR, val);
+ if (ret)
+ return ret;
+
+ /* DAC is ready after 12us, from RM table 40-3 */
+ fsleep(12);
+
+ return 0;
+}
+
+static void mcf54415_dac_exit(void *data)
+{
+ struct mcf54415_dac *info = data;
+
+ regmap_set_bits(info->map, MCF54415_DAC_CR, MCF54415_DAC_CR_PDN);
+}
+
+static const struct iio_chan_spec mcf54415_dac_iio_channel = {
+ .type = IIO_VOLTAGE,
+ .output = 1,
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
+ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
+};
+
+static int mcf54415_read_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int *val, int *val2, long mask)
+{
+ struct mcf54415_dac *info = iio_priv(indio_dev);
+ unsigned int reg;
+ int ret;
+
+ switch (mask) {
+ case IIO_CHAN_INFO_RAW:
+ ret = regmap_read(info->map, MCF54415_DAC_DATA, ®);
+ if (ret)
+ return ret;
+ *val = reg & GENMASK(11, 0);
+ return IIO_VAL_INT;
+ case IIO_CHAN_INFO_SCALE:
+ /* Reference voltage as per ColdFire datasheet is 3.3V */
+ *val = 3300 /* mV */;
+ *val2 = 12;
+ return IIO_VAL_FRACTIONAL_LOG2;
+ default:
+ return -EINVAL;
+ }
+}
+
+static int mcf54415_write_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int val, int val2, long mask)
+{
+ struct mcf54415_dac *info = iio_priv(indio_dev);
+
+ switch (mask) {
+ case IIO_CHAN_INFO_RAW:
+ /* Check based on RM 30.3.2 (DACn_DATA) reg. resolution */
+ if (val < 0 || val > 4095)
+ return -EINVAL;
+ return regmap_write(info->map, MCF54415_DAC_DATA, val);
+ default:
+ return -EINVAL;
+ }
+}
+
+static const struct iio_info mcf54415_dac_iio_info = {
+ .read_raw = &mcf54415_read_raw,
+ .write_raw = &mcf54415_write_raw,
+};
+
+static int mcf54415_dac_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct iio_dev *indio_dev;
+ struct mcf54415_dac *info;
+ void __iomem *regs;
+ int ret;
+
+ indio_dev = devm_iio_device_alloc(dev, sizeof(*info));
+ if (!indio_dev)
+ return -ENOMEM;
+
+ info = iio_priv(indio_dev);
+
+ regs = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(regs))
+ return dev_err_probe(dev, PTR_ERR(regs), "failed to get io regs\n");
+
+ info->map = devm_regmap_init_mmio(dev, regs, &mcf54415_dac_regmap_config);
+ if (IS_ERR(info->map))
+ return PTR_ERR(info->map);
+
+ info->clk = devm_clk_get_enabled(dev, "dac");
+ if (IS_ERR(info->clk))
+ return dev_err_probe(dev, PTR_ERR(info->clk), "failed getting clock\n");
+
+ indio_dev->name = "mcf54415";
+ indio_dev->info = &mcf54415_dac_iio_info;
+ indio_dev->modes = INDIO_DIRECT_MODE;
+ indio_dev->channels = &mcf54415_dac_iio_channel;
+ indio_dev->num_channels = 1;
+
+ ret = mcf54415_dac_init(info);
+ if (ret)
+ return ret;
+
+ ret = devm_add_action_or_reset(dev, mcf54415_dac_exit, info);
+ if (ret)
+ return ret;
+
+ return devm_iio_device_register(dev, indio_dev);
+}
+
+static const struct platform_device_id mcf54415_dac_ids[] = {
+ { .name = "mcfdac" },
+ { }
+};
+MODULE_DEVICE_TABLE(platform, mcf54415_dac_ids);
+
+static struct platform_driver mcf54415_dac_driver = {
+ .driver = {
+ .name = "mcf54415_dac",
+ },
+ .probe = mcf54415_dac_probe,
+ .id_table = mcf54415_dac_ids,
+};
+module_platform_driver(mcf54415_dac_driver);
+
+MODULE_AUTHOR("Angelo Dureghello <angelo@kernel-space.org>");
+MODULE_DESCRIPTION("NXP MCF54415 DAC driver");
+MODULE_LICENSE("GPL");
--
2.54.0
^ permalink raw reply related
* [PATCH v7 0/2] add mcf54415 DAC driver
From: Angelo Dureghello @ 2026-07-01 14:17 UTC (permalink / raw)
To: Jonathan Cameron, David Lechner, Nuno Sá, Andy Shevchenko,
Geert Uytterhoeven, Maxime Coquelin, Alexandre Torgue
Cc: linux-kernel, linux-iio, linux-m68k, linux-stm32,
linux-arm-kernel, Angelo Dureghello, Andy Shevchenko
This patchset adds a minimalistic DAC driver for the NXP mcf54415/6/7/8
builtin DACs.
Currently the driver enables the raw write only. Feature as dma, sync, or
format are not supoprted for this version.
Additional options suppoerted by the DAC module will be added to the driver
later on, as needed.
The same patchset prepares the m68k/coldfire architecture to support
the driver.
Below some basic tests done on stmark2 mcf54415-based board, voltage check
on DAC0 and DAC1:
~ # cd /sys/bus/iio/devices/iio:device0/
/sys/bus/iio/devices/iio:device0 # ls
name out_voltage_scale uevent
out_voltage_raw subsystem
/sys/bus/iio/devices/iio:device0 # cat name
mcf54415
/sys/bus/iio/devices/iio:device0 # echo 4095 > out_voltage_raw
/sys/bus/iio/devices/iio:device0 # echo 2048 > out_voltage_raw
/sys/bus/iio/devices/iio:device0 # echo 4096 > out_voltage_raw
sh: write error: Invalid argument
/sys/bus/iio/devices/iio:device0 # cat out_voltage_raw
2048
/sys/bus/iio/devices/iio:device0 #
Same behavior for /sys/bus/iio/devices/iio:device1.
Generated a sine wave by shell script, sine shape is good.
is actually in progress:
Note: this patchset depends on mew mcf_read/mcf_write implementation that
Link: https://lore.kernel.org/linux-m68k/209d0653-6386-4b64-9e15-e358f84453ab@app.fastmail.com/T/#t
Link: https://lore.kernel.org/linux-m68k/20260506142644.3234270-2-gerg@kernel.org/
---
Changes in v7:
- keeping changelog in each single patch, where any
- Link to v6: https://patch.msgid.link/20260618-wip-stmark2-dac-v6-0-48761dbb96d7@baylibre.com
Changes in v6:
- Removed patches 1 to 8, already pushed in m68knommu for-next by
Greg Ungerer <gerg@linux-m68k.org>
- keeping changelog in each single patch, where any
- Link to v5: https://patch.msgid.link/20260610-wip-stmark2-dac-v5-0-b76b83366d5c@baylibre.com
Changes in v5:
- keeping changelog in each single patch, where any
- Link to v4: https://patch.msgid.link/20260531-wip-stmark2-dac-v4-0-7e65ab4215dd@baylibre.com
Changes in v4:
- keeping changelog in each single patch, where any
- Link to v3: https://patch.msgid.link/20260522-wip-stmark2-dac-v3-0-16be0ad35a67@baylibre.com
Changes in v3:
- keeping changelog in each single patch, where any
- Link to v2: https://patch.msgid.link/20260513-wip-stmark2-dac-v2-0-fcdae50cf51a@baylibre.com
Changes in v2:
- keeping changelog in each single patch, where any
- Link to v1: https://patch.msgid.link/20260504-wip-stmark2-dac-v1-0-874c36a4910d@baylibre.com
To: Jonathan Cameron <jic23@kernel.org>
To: David Lechner <dlechner@baylibre.com>
To: Nuno Sá <nuno.sa@analog.com>
To: Andy Shevchenko <andy@kernel.org>
To: Geert Uytterhoeven <geert@linux-m68k.org>
To: Maxime Coquelin <mcoquelin.stm32@gmail.com>
To: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: linux-kernel@vger.kernel.org
Cc: linux-iio@vger.kernel.org
Cc: linux-m68k@lists.linux-m68k.org
Cc: linux-stm32@st-md-mailman.stormreply.com
Cc: linux-arm-kernel@lists.infradead.org
---
Angelo Dureghello (2):
iio: dac: add mcf54415 DAC
m68k: defconfig: update stmark2 defconfig
arch/m68k/configs/stmark2_defconfig | 2 +
drivers/iio/dac/Kconfig | 11 +++
drivers/iio/dac/Makefile | 1 +
drivers/iio/dac/mcf54415_dac.c | 180 ++++++++++++++++++++++++++++++++++++
4 files changed, 194 insertions(+)
---
base-commit: bc5a85a5441632f4bd7acd38620fdcbe4852a44f
change-id: 20260430-wip-stmark2-dac-7060f49dd94f
Best regards,
--
Angelo Dureghello <adureghello@baylibre.com>
^ permalink raw reply
* Re: [PATCH 2/7] i2c: nomadik: optimize layout of struct nmk_i2c_dev
From: Dmitry Guzman @ 2026-07-01 13:46 UTC (permalink / raw)
To: Linus Walleij
Cc: Andi Shyti, Steven Rostedt, Masami Hiramatsu, Mathieu Desnoyers,
linux-i2c, linux-kernel, linux-trace-kernel, linux-arm-kernel
In-Reply-To: <CAD++jLmqtG-j=Q-Ctr-1-GKVqYzcwOwWUF6AYHcKf5aXUSKE5A@mail.gmail.com>
On Thu, 25 Jun 2026 00:36:49 +0200
Linus Walleij <linusw@kernel.org> wrote:
> Hi Dmitry,
>
> thanks for your patch!
>
> Also nice to see some kernel contributions directly from
> MobilEye!
Thanks for you review!
> > struct nmk_i2c_dev {
> > struct i2c_vendor_data *vendor;
> > @@ -206,13 +206,13 @@ struct nmk_i2c_dev {
> > u32 clk_freq;
> > unsigned char tft;
> > unsigned char rft;
>
> ^
> Maybe you want to take the opportunity to change these
> two into u8 if you're anyway changing the layout of this
> struct?
I'm waiting for review of patch 1 in the set. If I need to submit next
version of the patchset, I'll change these two unsigned chars, as well
as `unsigned char *buffer` in `struct i2c_nmk_client`, into u8.
Best Regards,
--
Dmitry Guzman <Dmitry.Guzman@mobileye.com>
^ permalink raw reply
* [PATCH 04/12] phy: phy-mtk-dp: Migrate register offsets to SoC specific pdata
From: AngeloGioacchino Del Regno @ 2026-07-01 12:20 UTC (permalink / raw)
To: chunfeng.yun
Cc: vkoul, neil.armstrong, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, chunkuang.hu, p.zabel, justin.yeh,
linux-arm-kernel, linux-mediatek, linux-phy, devicetree,
linux-kernel, dri-devel, kernel
In-Reply-To: <20260701122008.19509-1-angelogioacchino.delregno@collabora.com>
In preparation for adding support for newer SoCs and for adding
more capabilities to this driver in an efficient manner, migrate
all of the hardcoded register offsets to SoC specific pdata and
assign that for both DT and platform probing.
While at it also cleanup writing the driving parameters to the PHY
by iterating through all lanes with a loop instead.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/phy/mediatek/phy-mtk-dp.c | 138 +++++++++++++++++++++++-------
1 file changed, 109 insertions(+), 29 deletions(-)
diff --git a/drivers/phy/mediatek/phy-mtk-dp.c b/drivers/phy/mediatek/phy-mtk-dp.c
index 98e05fe05ce3..ce33f6812bae 100644
--- a/drivers/phy/mediatek/phy-mtk-dp.c
+++ b/drivers/phy/mediatek/phy-mtk-dp.c
@@ -4,6 +4,10 @@
*
* Copyright (c) 2022, BayLibre Inc.
* Copyright (c) 2022, MediaTek Inc.
+ *
+ * Major refactoring
+ * Copyright (c) 2026, Collabora Ltd.
+ * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
*/
#include <linux/delay.h>
@@ -14,24 +18,25 @@
#include <linux/platform_device.h>
#include <linux/regmap.h>
-#define PHY_OFFSET 0x1000
+#define MTK_DP_PHY_MAX_LANES 4
-#define MTK_DP_PHY_DIG_PLL_CTL_1 (PHY_OFFSET + 0x14)
+/* DP_PHYD_PLL_CTL_1 */
#define TPLL_SSC_EN BIT(3)
-#define MTK_DP_PHY_DIG_BIT_RATE (PHY_OFFSET + 0x3C)
-#define BIT_RATE_RBR 0
-#define BIT_RATE_HBR 1
-#define BIT_RATE_HBR2 2
-#define BIT_RATE_HBR3 3
+/* DP_PHYD_BIT_RATE */
+#define PHYD_DIG_RG_BIT_RATE GENMASK(1, 0)
+# define BIT_RATE_RBR 0
+# define BIT_RATE_HBR 1
+# define BIT_RATE_HBR2 2
+# define BIT_RATE_HBR3 3
-#define MTK_DP_PHY_DIG_SW_RST (PHY_OFFSET + 0x38)
-#define DP_GLB_SW_RST_PHYD BIT(0)
+/* DP_PHYD_SW_RST */
+#define PHYD_DIG_GLB_SW_RST_B GENMASK(7, 0)
+# define DP_GLB_SW_RST_PHYD BIT(0)
+# define DP_GLB_SW_RST_TFIFO_ANA BIT(1)
+# define DP_GLB_SW_RST_XTAL_CLK BIT(2)
+# define DP_GLB_SW_RST_MAIN_LINK BIT(3)
-#define MTK_DP_LANE0_DRIVING_PARAM_3 (PHY_OFFSET + 0x138)
-#define MTK_DP_LANE1_DRIVING_PARAM_3 (PHY_OFFSET + 0x238)
-#define MTK_DP_LANE2_DRIVING_PARAM_3 (PHY_OFFSET + 0x338)
-#define MTK_DP_LANE3_DRIVING_PARAM_3 (PHY_OFFSET + 0x438)
#define XTP_LN_TX_LCTXC0_SW0_PRE0_DEFAULT BIT(4)
#define XTP_LN_TX_LCTXC0_SW0_PRE1_DEFAULT (BIT(10) | BIT(12))
#define XTP_LN_TX_LCTXC0_SW0_PRE2_DEFAULT GENMASK(20, 19)
@@ -78,14 +83,58 @@
#define DRIVING_PARAM_8_DEFAULT (XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT | \
XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT)
+enum mtk_dp_phyd_dig_lane_regidx {
+ DP_PHYD_LAN_DRIVING_PARAM_0,
+ DP_PHYD_LAN_MAX
+};
+
+enum mtk_dp_phyd_dig_glb_regidx {
+ DP_PHYD_PLL_CTL_0,
+ DP_PHYD_PLL_CTL_1,
+ DP_PHYD_SW_RST,
+ DP_PHYD_BIT_RATE,
+ DP_PHYD_GLOBAL_MAX
+};
+
+static const u8 mt8195_phy_dig_lane_regs[DP_PHYD_LAN_MAX] = {
+ [DP_PHYD_LAN_DRIVING_PARAM_0] = 0x2c,
+};
+
+static const u8 mt8195_phy_dig_glb_regs[DP_PHYD_GLOBAL_MAX] = {
+ [DP_PHYD_PLL_CTL_0] = 0x10,
+ [DP_PHYD_PLL_CTL_1] = 0x14,
+ [DP_PHYD_SW_RST] = 0x38,
+ [DP_PHYD_BIT_RATE] = 0x3c,
+};
+
+/**
+ * struct mtk_dp_phy_pdata - Platform data and defaults for MediaTek DP/eDP PHY
+ * @off_dig_glb: Base offset for dptx_phyd_sifslv_dig_glb
+ * @off_dig_lane: Base offsets for dptx_phyd_sifslv_dig_lan (for each lane)
+ * @regs_dig_glb: Register (layout) offsets for dig_glb
+ * @regs_dig_lane: Register (layout) offsets for dig_lan
+ */
+struct mtk_dp_phy_pdata {
+ /* Register offsets */
+ u16 off_dig_glb;
+ u16 off_dig_lane[MTK_DP_PHY_MAX_LANES];
+
+ /* Register maps */
+ const u8 *regs_dig_glb;
+ const u8 *regs_dig_lane;
+};
+
struct mtk_dp_phy {
struct device *dev;
struct regmap *regmap;
+ const struct mtk_dp_phy_pdata *pdata;
};
static int mtk_dp_phy_init(struct phy *phy)
{
struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy);
+ const struct mtk_dp_phy_pdata *pdata = dp_phy->pdata;
+ const u32 reg = pdata->regs_dig_lane[DP_PHYD_LAN_DRIVING_PARAM_0];
static const u32 driving_params[] = {
DRIVING_PARAM_3_DEFAULT,
DRIVING_PARAM_4_DEFAULT,
@@ -94,15 +143,21 @@ static int mtk_dp_phy_init(struct phy *phy)
DRIVING_PARAM_7_DEFAULT,
DRIVING_PARAM_8_DEFAULT
};
-
- regmap_bulk_write(dp_phy->regmap, MTK_DP_LANE0_DRIVING_PARAM_3,
- driving_params, ARRAY_SIZE(driving_params));
- regmap_bulk_write(dp_phy->regmap, MTK_DP_LANE1_DRIVING_PARAM_3,
- driving_params, ARRAY_SIZE(driving_params));
- regmap_bulk_write(dp_phy->regmap, MTK_DP_LANE2_DRIVING_PARAM_3,
- driving_params, ARRAY_SIZE(driving_params));
- regmap_bulk_write(dp_phy->regmap, MTK_DP_LANE3_DRIVING_PARAM_3,
- driving_params, ARRAY_SIZE(driving_params));
+ int i, ret;
+
+ /*
+ * Assume that all lanes need the same driving parameters: this
+ * will bulk write from DRIVING_PARAM_0 to DRIVING_PARAM_8 on
+ * all lanes (a grand total of [9 * num_lanes] 32-bit writes)
+ */
+ for (i = 0; i < MTK_DP_PHY_MAX_LANES; i++) {
+ ret = regmap_bulk_write(dp_phy->regmap,
+ pdata->off_dig_lane[i] + reg,
+ driving_params,
+ ARRAY_SIZE(driving_params));
+ if (ret)
+ return ret;
+ };
return 0;
}
@@ -110,9 +165,12 @@ static int mtk_dp_phy_init(struct phy *phy)
static int mtk_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
{
struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy);
+ const struct mtk_dp_phy_pdata *pdata = dp_phy->pdata;
u32 val;
if (opts->dp.set_rate) {
+ const u32 reg_bit_rate = pdata->regs_dig_glb[DP_PHYD_BIT_RATE];
+
switch (opts->dp.link_rate) {
default:
dev_err(&phy->dev,
@@ -132,10 +190,11 @@ static int mtk_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
val = BIT_RATE_HBR3;
break;
}
- regmap_write(dp_phy->regmap, MTK_DP_PHY_DIG_BIT_RATE, val);
+ regmap_write(dp_phy->regmap, pdata->off_dig_glb + reg_bit_rate, val);
}
- regmap_update_bits(dp_phy->regmap, MTK_DP_PHY_DIG_PLL_CTL_1,
+ regmap_update_bits(dp_phy->regmap,
+ pdata->off_dig_glb + pdata->regs_dig_glb[DP_PHYD_PLL_CTL_1],
TPLL_SSC_EN, opts->dp.ssc ? TPLL_SSC_EN : 0);
return 0;
@@ -144,12 +203,17 @@ static int mtk_dp_phy_configure(struct phy *phy, union phy_configure_opts *opts)
static int mtk_dp_phy_reset(struct phy *phy)
{
struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy);
+ const struct mtk_dp_phy_pdata *pdata = dp_phy->pdata;
+ const u32 reg_rst = pdata->regs_dig_glb[DP_PHYD_SW_RST];
+
+ /* Clearing bits sets reset state */
+ regmap_clear_bits(dp_phy->regmap, pdata->off_dig_glb + reg_rst, DP_GLB_SW_RST_PHYD);
- regmap_update_bits(dp_phy->regmap, MTK_DP_PHY_DIG_SW_RST,
- DP_GLB_SW_RST_PHYD, 0);
+ /* PHYD needs 50uS to guarantee reset done */
usleep_range(50, 200);
- regmap_update_bits(dp_phy->regmap, MTK_DP_PHY_DIG_SW_RST,
- DP_GLB_SW_RST_PHYD, 1);
+
+ /* Setting bits means go out of reset */
+ regmap_set_bits(dp_phy->regmap, pdata->off_dig_glb + reg_rst, DP_GLB_SW_RST_PHYD);
return 0;
}
@@ -161,11 +225,18 @@ static const struct phy_ops mtk_dp_phy_dev_ops = {
.owner = THIS_MODULE,
};
+static const struct mtk_dp_phy_pdata mt8195_dp_phy_data;
+
static int mtk_dp_phy_legacy_probe(struct platform_device *pdev, struct mtk_dp_phy *dp_phy)
{
struct device *dev = &pdev->dev;
struct phy *phy;
+ /*
+ * If legacy platform driver probe, assume this is MT8195 or compatible
+ * with a devicetree that was not migrated to the new, proper bindings.
+ */
+ dp_phy->pdata = &mt8195_dp_phy_data;
dp_phy->regmap = *(struct regmap **)dev->platform_data;
if (!dp_phy->regmap)
return dev_err_probe(dev, -EINVAL, "No platform data available\n");
@@ -214,6 +285,8 @@ static int mtk_dp_phy_probe(struct platform_device *pdev)
if (IS_ERR(dp_phy->regmap))
return PTR_ERR(dp_phy->regmap);
+ dp_phy->pdata = device_get_match_data(dev);
+
phy = devm_phy_create(dev, NULL, &mtk_dp_phy_dev_ops);
if (IS_ERR(phy))
return dev_err_probe(dev, PTR_ERR(phy),
@@ -231,8 +304,15 @@ static int mtk_dp_phy_probe(struct platform_device *pdev)
return 0;
}
+static const struct mtk_dp_phy_pdata mt8195_dp_phy_data = {
+ .off_dig_glb = 0x1000,
+ .off_dig_lane = (const u16[]) { 0x1100, 0x1200, 0x1300, 0x1400 },
+ .regs_dig_glb = mt8195_phy_dig_glb_regs,
+ .regs_dig_lane = mt8195_phy_dig_lane_regs,
+};
+
static const struct of_device_id mtk_dp_phy_of_match[] = {
- { .compatible = "mediatek,mt8195-dp-phy" },
+ { .compatible = "mediatek,mt8195-dp-phy", .data = &mt8195_dp_phy_data },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mtk_dp_phy_of_match);
--
2.54.0
^ permalink raw reply related
* Re: [PATCH 07/10] HID: apple: Add support for DockChannel HID keyboards
From: Michael Reeves @ 2026-07-01 14:01 UTC (permalink / raw)
To: Sasha Finkelstein
Cc: Sven Peter, Janne Grunau, Neal Gompa, Jassi Brar, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Hector Martin,
Joerg Roedel (AMD), Will Deacon, Robin Murphy, Dmitry Torokhov,
Jiri Kosina, Benjamin Tissoires, asahi, linux-arm-kernel,
linux-kernel, devicetree, iommu, linux-input
In-Reply-To: <B22C8EFD-DEDE-49C1-AD8E-BAEB5C91B6A6@chaosmail.tech>
On Tue, Jun 30, 2026 at 11:41 PM Sasha Finkelstein <k@chaosmail.tech> wrote:
[...]
> It looks like this section is duplicated in the following commit (8).
> Is that correct?
>
Yes, it is duplicated, thank you for the pick up. I moved the fixup to
the transport layer driver (in the following commit 8), which works
better, but must have forgotten to delete it here.
I will correct this in v2.
Thank you again!
^ permalink raw reply
* [PATCH 08/12] phy: phy-mtk-dp: Add support for digital and analog calibration
From: AngeloGioacchino Del Regno @ 2026-07-01 12:20 UTC (permalink / raw)
To: chunfeng.yun
Cc: vkoul, neil.armstrong, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, chunkuang.hu, p.zabel, justin.yeh,
linux-arm-kernel, linux-mediatek, linux-phy, devicetree,
linux-kernel, dri-devel, kernel
In-Reply-To: <20260701122008.19509-1-angelogioacchino.delregno@collabora.com>
Add support for reading the calibration values from eFuse: if
present, write those - otherwise, rely on the defaults from
SoC-specific data.
This also adds support for writing the calibration values for
the analog part of the PHY.
Note that before this change, only default hardcoded calibration
values were supported for the digital driving parameters.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/phy/mediatek/phy-mtk-dp.c | 286 ++++++++++++++++++++++++++++--
1 file changed, 267 insertions(+), 19 deletions(-)
diff --git a/drivers/phy/mediatek/phy-mtk-dp.c b/drivers/phy/mediatek/phy-mtk-dp.c
index 17d871530cca..b1b526ee44eb 100644
--- a/drivers/phy/mediatek/phy-mtk-dp.c
+++ b/drivers/phy/mediatek/phy-mtk-dp.c
@@ -13,6 +13,7 @@
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/mfd/syscon.h>
+#include <linux/nvmem-consumer.h>
#include <linux/of.h>
#include <linux/phy/phy.h>
#include <linux/platform_device.h>
@@ -20,6 +21,19 @@
#define MTK_DP_PHY_MAX_LANES 4
+/* DP_PHYA_GLB_BIAS_GEN_0 (PHYA - Analog) */
+#define XTP_GLB_BIAS_INT_R_CTRL GENMASK(20, 16)
+
+/* DP_PHYA_GLB_FORCE_CTRL_1 */
+#define CKM_CKTX0_EN_FORCE_MODE BIT(10)
+
+/* DP_PHYA_GLB_DPAUX_TX */
+#define CKM_PT0_CKTX_IMPSEL GENMASK(23, 20)
+
+/* DP_PHYA_LAN_LANE_TX_0 */
+#define XTP_LN_TX_IMPSEL_PMOS GENMASK(15, 12)
+#define XTP_LN_TX_IMPSEL_NMOS GENMASK(19, 16)
+
/* DP_PHYA_GLB_FORCE_CTRL_1 */
#define CKM_CKTX0_EN_FORCE_MODE BIT(10)
@@ -53,11 +67,29 @@
#define PHYD_DP_TX_FORCE_VOLT_SWING_VAL GENMASK(2, 1)
#define PHYD_DP_TX_FORCE_PRE_EMPH_VAL GENMASK(4, 3)
+/*
+ * DRIVING_PARAM_X (PHYD - Digital)
+ *
+ * Driving param registers are split in three sets, all containing settings
+ * for Voltage Swing and Pre-Emphasis for each lane's differential pair.
+ *
+ * All three sets share the same layout, but for different physical signals;
+ * In particular:
+ * [0-2]: LC TX CM (Minus / Negative Edge)
+ * [3-5]: LC TX C (Logic State Change Point)
+ * [6-8]: LC TX CP (Plus / Positive Edge)
+ *
+ * And they contain values for:
+ * [0,3,6]: Swing 0 Pre[0-3]
+ * [1,4,7]: Swing 1 Pre[0-2] and Swing 2 Pre0
+ * [2,5,8]: Swing 2 Pre1 and Swing 3 Pre0
+ */
+#define PHYD_DIG_NUM_DRV_PARA_REGS 9
#define XTP_LN_TX_LCTXC0_SW0_PRE0_DEFAULT BIT(4)
#define XTP_LN_TX_LCTXC0_SW0_PRE1_DEFAULT (BIT(10) | BIT(12))
#define XTP_LN_TX_LCTXC0_SW0_PRE2_DEFAULT GENMASK(20, 19)
#define XTP_LN_TX_LCTXC0_SW0_PRE3_DEFAULT GENMASK(29, 29)
-#define DRIVING_PARAM_3_DEFAULT (XTP_LN_TX_LCTXC0_SW0_PRE0_DEFAULT | \
+#define MT8195_DRIVING_PARAM_3_DEFAULT (XTP_LN_TX_LCTXC0_SW0_PRE0_DEFAULT | \
XTP_LN_TX_LCTXC0_SW0_PRE1_DEFAULT | \
XTP_LN_TX_LCTXC0_SW0_PRE2_DEFAULT | \
XTP_LN_TX_LCTXC0_SW0_PRE3_DEFAULT)
@@ -66,21 +98,21 @@
#define XTP_LN_TX_LCTXC0_SW1_PRE1_DEFAULT GENMASK(12, 9)
#define XTP_LN_TX_LCTXC0_SW1_PRE2_DEFAULT (BIT(18) | BIT(21))
#define XTP_LN_TX_LCTXC0_SW2_PRE0_DEFAULT GENMASK(29, 29)
-#define DRIVING_PARAM_4_DEFAULT (XTP_LN_TX_LCTXC0_SW1_PRE0_DEFAULT | \
+#define MT8195_DRIVING_PARAM_4_DEFAULT (XTP_LN_TX_LCTXC0_SW1_PRE0_DEFAULT | \
XTP_LN_TX_LCTXC0_SW1_PRE1_DEFAULT | \
XTP_LN_TX_LCTXC0_SW1_PRE2_DEFAULT | \
XTP_LN_TX_LCTXC0_SW2_PRE0_DEFAULT)
#define XTP_LN_TX_LCTXC0_SW2_PRE1_DEFAULT (BIT(3) | BIT(5))
#define XTP_LN_TX_LCTXC0_SW3_PRE0_DEFAULT GENMASK(13, 12)
-#define DRIVING_PARAM_5_DEFAULT (XTP_LN_TX_LCTXC0_SW2_PRE1_DEFAULT | \
+#define MT8195_DRIVING_PARAM_5_DEFAULT (XTP_LN_TX_LCTXC0_SW2_PRE1_DEFAULT | \
XTP_LN_TX_LCTXC0_SW3_PRE0_DEFAULT)
#define XTP_LN_TX_LCTXCP1_SW0_PRE0_DEFAULT 0
#define XTP_LN_TX_LCTXCP1_SW0_PRE1_DEFAULT GENMASK(10, 10)
#define XTP_LN_TX_LCTXCP1_SW0_PRE2_DEFAULT GENMASK(19, 19)
#define XTP_LN_TX_LCTXCP1_SW0_PRE3_DEFAULT GENMASK(28, 28)
-#define DRIVING_PARAM_6_DEFAULT (XTP_LN_TX_LCTXCP1_SW0_PRE0_DEFAULT | \
+#define MT8195_DRIVING_PARAM_6_DEFAULT (XTP_LN_TX_LCTXCP1_SW0_PRE0_DEFAULT | \
XTP_LN_TX_LCTXCP1_SW0_PRE1_DEFAULT | \
XTP_LN_TX_LCTXCP1_SW0_PRE2_DEFAULT | \
XTP_LN_TX_LCTXCP1_SW0_PRE3_DEFAULT)
@@ -89,22 +121,30 @@
#define XTP_LN_TX_LCTXCP1_SW1_PRE1_DEFAULT GENMASK(10, 9)
#define XTP_LN_TX_LCTXCP1_SW1_PRE2_DEFAULT GENMASK(19, 18)
#define XTP_LN_TX_LCTXCP1_SW2_PRE0_DEFAULT 0
-#define DRIVING_PARAM_7_DEFAULT (XTP_LN_TX_LCTXCP1_SW1_PRE0_DEFAULT | \
+#define MT8195_DRIVING_PARAM_7_DEFAULT (XTP_LN_TX_LCTXCP1_SW1_PRE0_DEFAULT | \
XTP_LN_TX_LCTXCP1_SW1_PRE1_DEFAULT | \
XTP_LN_TX_LCTXCP1_SW1_PRE2_DEFAULT | \
XTP_LN_TX_LCTXCP1_SW2_PRE0_DEFAULT)
#define XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT GENMASK(3, 3)
#define XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT 0
-#define DRIVING_PARAM_8_DEFAULT (XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT | \
+#define MT8195_DRIVING_PARAM_8_DEFAULT (XTP_LN_TX_LCTXCP1_SW2_PRE1_DEFAULT | \
XTP_LN_TX_LCTXCP1_SW3_PRE0_DEFAULT)
enum mtk_dp_phya_ana_glb_regidx {
+ DP_PHYA_GLB_BIAS_GEN_0,
+ DP_PHYA_GLB_BIAS_GEN_1,
+ DP_PHYA_GLB_DPAUX_TX,
DP_PHYA_GLB_FORCE_CTRL_0,
DP_PHYA_GLB_FORCE_CTRL_1,
DP_PHYA_GLOBAL_MAX
};
+enum mtk_dp_phya_ana_lane_regidx {
+ DP_PHYA_LAN_LANE_TX_0,
+ DP_PHYA_LAN_MAX
+};
+
enum mtk_dp_phyd_dig_lane_regidx {
DP_PHYD_LAN_DRIVING_FORCE,
DP_PHYD_LAN_DRIVING_PARAM_0,
@@ -122,10 +162,17 @@ enum mtk_dp_phyd_dig_glb_regidx {
};
static const u8 mt8195_phy_ana_glb_regs[DP_PHYA_GLOBAL_MAX] = {
+ [DP_PHYA_GLB_BIAS_GEN_0] = 0x0,
+ [DP_PHYA_GLB_BIAS_GEN_1] = 0x4,
+ [DP_PHYA_GLB_DPAUX_TX] = 0x8,
[DP_PHYA_GLB_FORCE_CTRL_0] = 0x30,
[DP_PHYA_GLB_FORCE_CTRL_1] = 0x34,
};
+static const u8 mt8195_phy_ana_lane_regs[DP_PHYA_LAN_MAX] = {
+ [DP_PHYA_LAN_LANE_TX_0] = 0x4,
+};
+
static const u8 mt8195_phy_dig_lane_regs[DP_PHYD_LAN_MAX] = {
[DP_PHYD_LAN_DRIVING_FORCE] = 0x18,
[DP_PHYD_LAN_DRIVING_PARAM_0] = 0x2c,
@@ -140,46 +187,100 @@ static const u8 mt8195_phy_dig_glb_regs[DP_PHYD_GLOBAL_MAX] = {
[DP_PHYD_TX_CTL_0] = 0x44,
};
+/**
+ * struct mtk_dp_phya_imp_sel - Per-Lane Impedance Selection
+ * @pmos: Impedance selection for P-Channel MOSFET
+ * @nmos: Impedance selection for N-Channel MOSFET
+ */
+struct mtk_dp_phya_imp_sel {
+ u8 pmos : 4;
+ u8 nmos : 4;
+};
+
/**
* struct mtk_dp_phy_pdata - Platform data and defaults for MediaTek DP/eDP PHY
* @off_ana_glb: Base offset for dptx_phyd_sifslv_ana_glb
+ * @off_ana_lane: Base offsets for dptx_phyd_sifslv_ana_lan (for each lane)
* @off_dig_glb: Base offset for dptx_phyd_sifslv_dig_glb
* @off_dig_lane: Base offsets for dptx_phyd_sifslv_dig_lan (for each lane)
* @regs_ana_glb: Register (layout) offsets for ana_glb
+ * @regs_ana_lane: Register (layout) offsets for ana_lan
* @regs_dig_glb: Register (layout) offsets for dig_glb
* @regs_dig_lane: Register (layout) offsets for dig_lan
+ * @ana_bias_r: Internal resistance "R" Selection Settings (global)
+ * @ana_cktx_imp: TX Clock Impedance Selection Settings (global)
+ * @ana_lanes_imp: TX Impedance Selection Settings (for all lanes)
+ * @driving_params: Voltage Swing and Pre-Emphasis settings (for all lanes)
*/
struct mtk_dp_phy_pdata {
/* Register offsets */
u16 off_ana_glb;
+ u16 off_ana_lane[MTK_DP_PHY_MAX_LANES];
u16 off_dig_glb;
u16 off_dig_lane[MTK_DP_PHY_MAX_LANES];
/* Register maps */
const u8 *regs_ana_glb;
+ const u8 *regs_ana_lane;
const u8 *regs_dig_glb;
const u8 *regs_dig_lane;
+
+ /* Calibration defaults */
+ u8 ana_bias_r;
+ u8 ana_cktx_imp;
+ struct mtk_dp_phya_imp_sel ana_lanes_imp;
+ u32 driving_params[PHYD_DIG_NUM_DRV_PARA_REGS];
};
struct mtk_dp_phy {
struct device *dev;
struct regmap *regmap;
const struct mtk_dp_phy_pdata *pdata;
+
+ u8 ana_bias_r;
+ u8 ana_cktx_imp;
+ struct mtk_dp_phya_imp_sel ana_impsel[MTK_DP_PHY_MAX_LANES];
+ bool efuse_cal_present;
};
-static int mtk_dp_phy_init(struct phy *phy)
+static int mtk_dp_phy_set_analog_calibration_params(struct mtk_dp_phy *dp_phy)
+{
+ const struct mtk_dp_phy_pdata *pdata = dp_phy->pdata;
+ const u8 *regs_ana_glb = pdata->regs_ana_glb;
+ const u8 *regs_ana_lane = pdata->regs_ana_lane;
+ int i, ret;
+
+ ret = regmap_update_bits(dp_phy->regmap,
+ pdata->off_ana_glb + regs_ana_glb[DP_PHYA_GLB_BIAS_GEN_0],
+ XTP_GLB_BIAS_INT_R_CTRL, pdata->ana_bias_r);
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(dp_phy->regmap,
+ pdata->off_ana_glb + regs_ana_glb[DP_PHYA_GLB_DPAUX_TX],
+ CKM_PT0_CKTX_IMPSEL, pdata->ana_cktx_imp);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < MTK_DP_PHY_MAX_LANES; i++) {
+ struct mtk_dp_phya_imp_sel *ana_imp = &dp_phy->ana_impsel[i];
+ u32 val = FIELD_PREP(XTP_LN_TX_IMPSEL_PMOS, ana_imp->pmos) |
+ FIELD_PREP(XTP_LN_TX_IMPSEL_NMOS, ana_imp->nmos);
+ u32 off_ana_lane = pdata->off_ana_lane[i];
+
+ ret = regmap_update_bits(dp_phy->regmap,
+ off_ana_lane + regs_ana_lane[DP_PHYA_LAN_LANE_TX_0],
+ XTP_LN_TX_IMPSEL_PMOS | XTP_LN_TX_IMPSEL_NMOS, val);
+ if (ret)
+ return ret;
+ }
+ return 0;
+}
+
+static int mtk_dp_phy_set_digital_drv_params(struct mtk_dp_phy *dp_phy)
{
- struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy);
const struct mtk_dp_phy_pdata *pdata = dp_phy->pdata;
const u32 reg = pdata->regs_dig_lane[DP_PHYD_LAN_DRIVING_PARAM_0];
- static const u32 driving_params[] = {
- DRIVING_PARAM_3_DEFAULT,
- DRIVING_PARAM_4_DEFAULT,
- DRIVING_PARAM_5_DEFAULT,
- DRIVING_PARAM_6_DEFAULT,
- DRIVING_PARAM_7_DEFAULT,
- DRIVING_PARAM_8_DEFAULT
- };
int i, ret;
/*
@@ -190,11 +291,31 @@ static int mtk_dp_phy_init(struct phy *phy)
for (i = 0; i < MTK_DP_PHY_MAX_LANES; i++) {
ret = regmap_bulk_write(dp_phy->regmap,
pdata->off_dig_lane[i] + reg,
- driving_params,
- ARRAY_SIZE(driving_params));
+ pdata->driving_params,
+ ARRAY_SIZE(pdata->driving_params));
if (ret)
return ret;
};
+ return 0;
+}
+
+static int mtk_dp_phy_init(struct phy *phy)
+{
+ struct mtk_dp_phy *dp_phy = phy_get_drvdata(phy);
+ struct device *dev = &phy->dev;
+ int ret;
+
+ ret = mtk_dp_phy_set_digital_drv_params(dp_phy);
+ if (ret) {
+ dev_err(dev, "Cannot set driving params\n");
+ return ret;
+ }
+
+ ret = mtk_dp_phy_set_analog_calibration_params(dp_phy);
+ if (ret) {
+ dev_err(dev, "Cannot set analog calibration\n");
+ return ret;
+ }
return 0;
}
@@ -396,6 +517,109 @@ static const struct phy_ops mtk_dp_phy_dev_ops = {
.owner = THIS_MODULE,
};
+static void mtk_dp_phy_get_default_cal_data(struct mtk_dp_phy *dp_phy)
+{
+ const struct mtk_dp_phy_pdata *pdata = dp_phy->pdata;
+ int i;
+
+ dp_phy->ana_bias_r = pdata->ana_bias_r;
+ dp_phy->ana_cktx_imp = pdata->ana_cktx_imp;
+
+ /* Copy the default lane impedance settings to all lanes */
+ for (i = 0; i < MTK_DP_PHY_MAX_LANES; i++)
+ memcpy(&dp_phy->ana_impsel[i], &pdata->ana_lanes_imp,
+ sizeof(dp_phy->ana_impsel[0]));
+
+ return;
+}
+
+static int mtk_dp_phy_get_one_cal_para(struct device *dev, const char *name, u8 max_val)
+{
+ u16 buf = 0;
+ int ret;
+
+ /*
+ * All of the calibrations are always max 8 bits long, but some may
+ * be split between two different 8-bits cells: handle this corner
+ * case by retrying reading as u16.
+ */
+ ret = nvmem_cell_read_u8(dev, name, (u8 *)&buf);
+ if (ret)
+ ret = nvmem_cell_read_u16(dev, name, &buf);
+
+ if (ret) {
+ dev_err(dev, "Cannot get calibration data for %s: %d\n", name, ret);
+ return ret;
+ };
+
+ if (buf == 0) {
+ dev_warn(dev, "No calibration for %s. Using defaults\n", name);
+ return -ENOENT;
+ }
+
+ if (buf > max_val) {
+ dev_err(dev, "Bad value %u retrieved for %s. Returning.\n", buf, name);
+ return -ERANGE;
+ };
+
+ return buf;
+}
+
+static int mtk_dp_phy_get_calibration_data(struct mtk_dp_phy *dp_phy)
+{
+ char mtk_dp_cal_lane_imp_name[] = "impedance-laneXM";
+ struct device *dev = dp_phy->dev;
+ int i, ret;
+
+ ret = mtk_dp_phy_get_one_cal_para(dev, "rbias-trim", FIELD_MAX(XTP_GLB_BIAS_INT_R_CTRL));
+ if (ret < 0)
+ goto end;
+ dp_phy->ana_bias_r = ret;
+
+ ret = mtk_dp_phy_get_one_cal_para(dev, "impedance-txclk", FIELD_MAX(CKM_PT0_CKTX_IMPSEL));
+ if (ret < 0)
+ goto end;
+ dp_phy->ana_cktx_imp = ret;
+
+ /* Get impedance params for each lane */
+ for (i = 0; i < MTK_DP_PHY_MAX_LANES; i++) {
+ /* P-MOSFET first */
+ snprintf(mtk_dp_cal_lane_imp_name, ARRAY_SIZE(mtk_dp_cal_lane_imp_name),
+ "impedance-lane%dp", i);
+ ret = mtk_dp_phy_get_one_cal_para(dev, mtk_dp_cal_lane_imp_name,
+ FIELD_MAX(XTP_LN_TX_IMPSEL_PMOS));
+ if (ret < 0)
+ goto end;
+ dp_phy->ana_impsel[i].pmos = ret;
+
+ /* ...and then N-MOSFET too */
+ snprintf(mtk_dp_cal_lane_imp_name, ARRAY_SIZE(mtk_dp_cal_lane_imp_name),
+ "impedance-lane%dn", i);
+ ret = mtk_dp_phy_get_one_cal_para(dev, mtk_dp_cal_lane_imp_name,
+ FIELD_MAX(XTP_LN_TX_IMPSEL_PMOS));
+ if (ret < 0)
+ goto end;
+ dp_phy->ana_impsel[i].nmos = ret;
+ }
+end:
+ if (ret < 0) {
+ /*
+ * If any of the calibration values is missing, or if there
+ * is no calibration at all in the eFuses, copy the default
+ * one entirely (as partial values shall not be mixed!)
+ */
+ if (ret == -ENOENT) {
+ dev_info(dev, "Using calibration default values\n");
+ mtk_dp_phy_get_default_cal_data(dp_phy);
+ return 0;
+ }
+ return ret;
+ };
+ dp_phy->efuse_cal_present = true;
+
+ return 0;
+}
+
static const struct mtk_dp_phy_pdata mt8195_dp_phy_data;
static int mtk_dp_phy_legacy_probe(struct platform_device *pdev, struct mtk_dp_phy *dp_phy)
@@ -437,6 +661,7 @@ static int mtk_dp_phy_probe(struct platform_device *pdev)
struct mtk_dp_phy *dp_phy;
void __iomem *base;
struct phy *phy;
+ int ret;
dp_phy = devm_kzalloc(dev, sizeof(*dp_phy), GFP_KERNEL);
if (!dp_phy)
@@ -458,6 +683,10 @@ static int mtk_dp_phy_probe(struct platform_device *pdev)
dp_phy->pdata = device_get_match_data(dev);
+ ret = mtk_dp_phy_get_calibration_data(dp_phy);
+ if (ret)
+ return ret;
+
phy = devm_phy_create(dev, NULL, &mtk_dp_phy_dev_ops);
if (IS_ERR(phy))
return dev_err_probe(dev, PTR_ERR(phy),
@@ -476,12 +705,31 @@ static int mtk_dp_phy_probe(struct platform_device *pdev)
}
static const struct mtk_dp_phy_pdata mt8195_dp_phy_data = {
- .off_ana_glb = 0x0,
+ .off_ana_glb = 0,
+ .off_ana_lane = (const u16[]) { 0x100, 0x200, 0x300, 0x400 },
.off_dig_glb = 0x1000,
.off_dig_lane = (const u16[]) { 0x1100, 0x1200, 0x1300, 0x1400 },
.regs_ana_glb = mt8195_phy_ana_glb_regs,
+ .regs_ana_lane = mt8195_phy_ana_lane_regs,
.regs_dig_glb = mt8195_phy_dig_glb_regs,
.regs_dig_lane = mt8195_phy_dig_lane_regs,
+ .ana_bias_r = 15,
+ .ana_cktx_imp = 8,
+ .ana_lanes_imp = {
+ .pmos = 8,
+ .nmos = 8,
+ },
+ .driving_params = (const u32[]) {
+ [0] = 0,
+ [1] = 0,
+ [2] = 0,
+ [3] = MT8195_DRIVING_PARAM_3_DEFAULT,
+ [4] = MT8195_DRIVING_PARAM_4_DEFAULT,
+ [5] = MT8195_DRIVING_PARAM_5_DEFAULT,
+ [6] = MT8195_DRIVING_PARAM_6_DEFAULT,
+ [7] = MT8195_DRIVING_PARAM_7_DEFAULT,
+ [8] = MT8195_DRIVING_PARAM_8_DEFAULT
+ },
};
static const struct of_device_id mtk_dp_phy_of_match[] = {
--
2.54.0
^ permalink raw reply related
* Re: [PATCH v14 29/44] arm64: RMI: Runtime faulting of memory
From: Lorenzo Pieralisi @ 2026-07-01 13:58 UTC (permalink / raw)
To: Gavin Shan
Cc: Suzuki K Poulose, Steven Price, kvm, kvmarm, Catalin Marinas,
Marc Zyngier, Will Deacon, James Morse, Oliver Upton, Zenghui Yu,
linux-arm-kernel, linux-kernel, Joey Gouly, Alexandru Elisei,
Christoffer Dall, Fuad Tabba, linux-coco, Ganapatrao Kulkarni,
Shanker Donthineni, Alper Gun, Aneesh Kumar K . V, Emi Kisanuki,
Vishal Annapurve, WeiLin.Chang, Lorenzo.Pieralisi2
In-Reply-To: <901398bb-ed6c-4997-b3cd-ce2829b09c87@redhat.com>
On Sun, Jun 28, 2026 at 08:33:01PM +1000, Gavin Shan wrote:
> On 6/27/26 2:44 AM, Lorenzo Pieralisi wrote:
> > On Fri, Jun 26, 2026 at 09:43:03PM +1000, Gavin Shan wrote:
> > > On 6/26/26 6:47 PM, Suzuki K Poulose wrote:
> > > > On 26/06/2026 08:43, Gavin Shan wrote:
> > > > > On 6/26/26 1:58 AM, Suzuki K Poulose wrote:
> > > > > > On 25/06/2026 14:53, Gavin Shan wrote:
> > > > > > > On 6/6/26 12:35 AM, Lorenzo Pieralisi wrote:
> > > > > > > > On Fri, Jun 05, 2026 at 06:11:11PM +1000, Gavin Shan wrote:
> > > > > > > > > On 6/5/26 5:28 PM, Lorenzo Pieralisi wrote:
> > > > > > > > > > On Fri, Jun 05, 2026 at 04:23:15PM +1000, Gavin Shan wrote:
> > > > >
> > > > > [...]
> > > > >
> > > > > > > > >
> > > > > > > > > I tried to rebase Jean's latest QEMU series [1] to upstream QEMU, and found
> > > > > > > > > that memory slots backed by THP are broken. With THP disabled on the host and
> > > > > > > > > other fixes (mentioned in my prevous replies) applied on the top of this (v14)
> > > > > > > > > series, I'm able to boot a realm guest with rebased QEMU series [2], plus more
> > > > > > > > > fxies on the top.
> > > > > > > > >
> > > > > > > > > [1] https://git.codelinaro.org/linaro/dcap/qemu.git (branch: cca/ latest)
> > > > > > > > > [2] https://git.qemu.org/git/qemu.git (branch: cca/ gavin)
> > > > > > > > >
> > > > > > > > > Lorenzo, You may be saying there is someone making QEMU to support ARM/CCA?
> > > > > > > >
> > > > > > > > Mathieu and I are working on that yes and with Steven/Suzuki to fix the THP
> > > > > > > > issues you pointed out above.
> > > > > > > >
> > > > > > > > > If so, I'm not sure if there is a QEMU repository for me to try?
> > > > > > > >
> > > > > > > > We should be able to submit patches by end of June - we shall let you know
> > > > > > > > whether we can make something available earlier.
> > > > > > > >
> > > > > > >
> > > > > > > Not sure if there are other known issues in this series. It seems the stage2
> > > > > > > page fault handling on the shared space isn't working well. In my test, the
> > > > > > > vring (struct vring_desc) of virtio-net-pci is updated by the guest, and the
> > > > > > > data isn't seen by QEMU, I'm suspecting if the host-page-frame-number is properly
> > > > > > > resolved in the s2 page fault handler for shared (unprotected) space.
> > > > > > >
> > > > > > > - I rebased Jean's latest qemu branch to the upstream qemu;
> > > > > > >
> > > > > > > - On the host, which is emulated by qemu/tcg, the THP (transparent huge page) is
> > > > > > > disabled.
> > > > > > >
> > > > > > > - On the guest, I can see the virtio vring (struct vring_desc) is updated. The
> > > > > > > S1 page-table entry looks correct because the corresponding physical address
> > > > > > > 0x10046880000 is a sane shared (unprotected) space address.
> > > > > > >
> > > > > > > [ 52.094143] software IO TLB: Memory encryption is active and system is using DMA bounce buffers
> > > > > > > [ 52.289746] virtqueue_add_desc_split: desc[0]@0xffff000006880000, [00000100b983f000 00000640 0002 0001]
> > > > > > > [ 52.432150] PTE 0x00e8010046880707 at address 0xffff000006880000
> > > > > > >
> > > > > > > - On the host, the s2 page-table-entry is unmapped due to attribute transition (private -> shared).
> > > > > > > A subsequent S2 page fault is raised against the adress and the s2 page-table-entry is built.
> > > > > > >
> > > > > > > [ 109.259077] ====> realm_unmap_shared_range: tracked_unprot_addr=0x10046880000
> > > > > > > [ 109.260249] realm_unmap_shared_range: unmapped shared range at 0x10046880000
> > > > > > > [ 109.317786] realm_unmap_shared_range: unmapped shared range at 0x10046880000
> > > > > > > [ 109.629939] ====> kvm_handle_guest_abort: fault_ipa=0x10046880000, esr=0x92000007
> > > > > > > [ 109.630245] realm_map_non_secure: ipa=0x10046880000, pfn=0xb8b59, size=0x1000, prot=0xf
> > > > > > > [ 109.630331] realm_map_non_secure: ipa=0x10046880000, ipa_top=0x10046881000, flags=0x1e0001, range_desc=0xb8b59004
> > > > > >
> > > > > > Are you able to correlate the order of the transitions and the Guest
> > > > > > access with RMM log ? We haven't seen this from our end. We are aware
> > > > > > of permission fault issues with Unprotected IPA when backing the memslot
> > > > > > with MAP_PRIVATE areas. But this looks different.
> > > > > >
> > > > > > Lorenzo, have you run into this ?
> > > > > >
> > > > >
> > > > > It's hard to correlate the order since the logs are collected from two separate
> > > > > consoles. For the write permission, I add code to the host where the permission
> > > > > is always added for all s2 page faults in the shared space. Otherwise, qemu can
> > > > > be killed by -EFAULT or similar error.
> > > >
> > > > This is the problem. We can't add WRITE permission by default. I believe
> > > > you may have MAP_PRIVATE mapping and it has to be mapped as READ only
> > > > and on a permission fault, we replace it with a writable page. By
> > > > overriding the WRITE permission, you let the guest write to a page
> > > > that may not be seen by the VMM.
> > > >
> > > > We identified this as a bug in the KVM driver in this series (reported
> > > > by Lorenzo) and there is a corresponding tf-RMM change that is required
> > > > to get this working. So, please could you wait until the next series
> > > > when this will be addressed ? Or you could switch to using MAP_SHARED
> > > > for the "shared" memory in the memslot.
> > > >
> > >
> > > Exactly. the syntax for MAP_PRIVATE is broken if the write permission is
> > > enforced for a read fault in the shared space. In my case, the host page can
> > > be the zero page and eventually multiple s2 page-table entries (for multiple
> > > unprotected or shared pages) point to the zero page. It's why clearing the
> > > 3rd queue (Ctrl queue) also clears the first queue (Rx queue) in my case.
> > >
> > > Yes, this issue can be avoid by using a shared memory backend in qemu, something
> > > like below. With this, I'm able to see virtio-net-pci starts to work...
> > >
> > > -object memory-backend-ram,id=mem0,size=2G,share=yes
> >
> > Yes, as Suzuki said that's what we have been fixing. QEmu patches
> > will be on the mailing lists very shortly - the KVM/tf-RMM fixes
> > to make MAP_PRIVATE work will be included in the next posting.
> >
> > Feel free to drop your QEmu command line so that I can give it
> > a shot and check whether the fixes solve the problem you hit
> > (I think so because that's precisely the kind of issue I got
> > into when I started debugging THP/MAP_PRIVATE but it is better
> > to check).
> >
>
> The virtio-net-pci doesn't work with the following command lines. The guest
> kernel image is built from upstream kernel (v7.1.rc7).
>
> qemu-system-aarch64 -enable-kvm -object rme-guest,id=rme0, \
> -machine virt,gic-version=3,confidential-guest-support=rme0 \
> -cpu host,pmu=off \
> -smp maxcpus=2,cpus=2,sockets=1,clusters=1,cores=1,threads=2 \
> -m 2G -object memory-backend-ram,id=mem0,size=2G \
> -numa node,nodeid=0,cpus=0-1,memdev=mem0 \
> -serial mon:stdio -monitor none -nographic -nodefaults \
> -kernel /mnt/linux/arch/arm64/boot/Image \
> -initrd /mnt/buildroot/output/images/rootfs.cpio.xz \
> -append earlycon=pl011,mmio,0x10009000000 \
> -device pcie-root-port,bus=pcie.0,chassis=1,id=pcie.1 \
> -device pcie-root-port,bus=pcie.0,chassis=2,id=pcie.2 \
> -device pcie-root-port,bus=pcie.0,chassis=3,id=pcie.3 \
> -device pcie-root-port,bus=pcie.0,chassis=4,id=pcie.4 \
> -netdev tap,id=tap1,vhost=on,script=/etc/qemu-ifup,downscript=/etc/qemu-ifdown \
> -device virtio-net-pci,bus=pcie.2,netdev=tap1,mac=b8:3f:d2:1d:3e:c0
Tested with private RAM backend, THP left enabled (and additional KVM and
RMM patches that will be included in v15) looks like the net interface
comes up cleanly.
Probably it is best to sync up on the upcoming v15 posting that I am
testing in the background to make sure you don't spend more time chasing
it.
Thanks,
Lorenzo
>
> The virtio-net-pci starts to work with the shareable memory-backend.
>
> -object memory-backend-ram,id=mem0,size=2G,share=yes
>
> Note that THP is disabled on my host.
>
> root@host:~# cat /sys/kernel/mm/transparent_hugepage/enabled
> always madvise [never]
^ permalink raw reply
* Re: [RFC 0/2] arm64: kprobes: Fix single-step fault and reentry handling
From: Pu Hu @ 2026-07-01 13:56 UTC (permalink / raw)
To: Masami Hiramatsu (Google)
Cc: Hongyan Xia, Jiazi Li, catalin.marinas@arm.com, naveen@kernel.org,
linux-kernel@vger.kernel.org, yang@os.amperecomputing.com,
will@kernel.org, davem@davemloft.net,
linux-arm-kernel@lists.infradead.org,
linux-trace-kernel@vger.kernel.org
In-Reply-To: <20260701224345.c3a215ece3660a0cbae67645@kernel.org>
On 7/1/2026 9:43 PM, Masami Hiramatsu wrote:
> On Wed, 1 Jul 2026 12:14:54 +0000
> Pu Hu <hupu@transsion.com> wrote:
>
>> From: hupu <hupu@transsion.com>
>>
>> This series fixes two arm64 kprobes issues observed when running
>> simpleperf with preemptirq tracepoints and dwarf callchains while a
>> kprobe is active on a frequently executed kernel function.
>>
>> The crash happens in the kprobe debug exception path. While a kprobe is
>> preparing or executing its XOL single-step instruction, perf/trace code
>> can run in the same window. That code may either take a fault of its own
>> or hit another kprobe.
>>
>> Patch 1 makes kprobe_fault_handler() handle a fault in
>> KPROBE_HIT_SS/KPROBE_REENTER only when the faulting PC points at the
>> current kprobe's XOL instruction. Otherwise the fault is left to the
>> normal fault handling path.
>>
>> Patch 2 allows a kprobe hit in KPROBE_HIT_SS to be handled as a
>> recoverable one-level reentry. Only a hit while already in
>> KPROBE_REENTER remains unrecoverable.
>>
>> This follows the same logic as the existing x86 fixes:
>> 6381c24cd6d5 ("kprobes/x86: Fix page-fault handling logic")
>> 6a5022a56ac3 ("kprobes/x86: Allow to handle reentered kprobe on single-stepping")
>
> Good catch!!
> The series looks good to me.
>
> Acked-by: Masami Hiramatsu (Google) <mhiramat@kernel.org>
>
> But it should be reviewed by arm64 maintainers too.
>
> BTW, if you are "Pu Hu", the Signed-off-by tag should be
> "Pu Hu <...>" instead of "hupu <...>".
>
Hi Masami,
Thank you for your reply and Acked-by.
Yes, thanks for pointing this out. I will fix the author name and the
Signed-off-by tags to use a consistent name in the next version of the
patchset.
Thanks,
hupu
^ permalink raw reply
* [PATCH 19/42] drm/mediatek: Fully migrate to new Display Controller HW indexing
From: AngeloGioacchino Del Regno @ 2026-07-01 12:20 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard, tzimmermann,
robh, krzk+dt, conor+dt, matthias.bgg, angelogioacchino.delregno,
dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, justin.yeh, jason-jh.lin, kernel
In-Reply-To: <20260701122057.19648-1-angelogioacchino.delregno@collabora.com>
Perform a full migration to HW Type -> HW Instance ID indexing
for all of the currently supported Display Controller hardware
sub-components.
This allows to remove the big fixed-size catch-all components
array (that contains as many element as much as the number of
supported hardware and number of instances of that), which is
currently growing bigger and bigger at every sub-ip support
addition in mediatek-drm.
Note that this cleanup became necessary seen the need to add
support for new components found in MT8196, MT8994 and other
variants of it, and of course those SoCs won't be the last
ones to be upstreamed... so the size of that array would get
out of control pretty fast (and again, it's already very big).
As a side effect, while saving memory compared to before this
change, this also allows to have up to 24 (as an extensible fixed
size declared in this driver) instances of the same HW Type with
no further increase in memory footprint.
Similarly, adding support for new hardware will not produce an
increase of memory footprint on all SoCs (if not only temporarily
while the probe process is in place) as there's no more catch-all
array, but only a dynamically allocated list of per display output
components.
Unfortunately, this change needs to go along with the related one
in the mtk-mmsys driver, otherwise functionality of the Display
Controller will regress.
The only way to make this possible in two steps is to duplicate
all of the routes structure arrays for all of the SoCs, which
would result in a total of around ~1200 lines changed twice, and
that ignores the big increase in size for this driver during the
migration process so, in order to avoid useless bloat, I opted
for an inter-dependency between the two changes: mediatek-drm
and mtk-mmsys.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_crtc.c | 126 ++--
drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 131 ++--
drivers/gpu/drm/mediatek/mtk_ddp_comp.h | 28 +-
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 9 +-
.../gpu/drm/mediatek/mtk_disp_ovl_adaptor.c | 108 ++--
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 74 +--
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 9 +-
drivers/gpu/drm/mediatek/mtk_drm_legacy.c | 602 +++++++++---------
drivers/gpu/drm/mediatek/mtk_drm_legacy.h | 3 +-
9 files changed, 538 insertions(+), 552 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_crtc.c b/drivers/gpu/drm/mediatek/mtk_crtc.c
index 6a1af60de469..ee23a50cf4d1 100644
--- a/drivers/gpu/drm/mediatek/mtk_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_crtc.c
@@ -415,28 +415,32 @@ static int mtk_crtc_ddp_hw_init(struct mtk_crtc *mtk_crtc)
}
for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
- if (!mtk_ddp_comp_connect(mtk_crtc->ddp_comp[i], mtk_crtc->mmsys_dev,
- mtk_crtc->ddp_comp[i + 1]->id))
- mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev,
- mtk_crtc->ddp_comp[i]->id,
- mtk_crtc->ddp_comp[i + 1]->id);
- if (!mtk_ddp_comp_add(mtk_crtc->ddp_comp[i], mtk_crtc->mutex))
- mtk_mutex_add_comp(mtk_crtc->mutex,
- mtk_crtc->ddp_comp[i]->id);
-
- /* For now, only single DSI is supported */
- if (mtk_crtc->ddp_comp[i]->id >= DDP_COMPONENT_DSI0 &&
- mtk_crtc->ddp_comp[i]->id <= DDP_COMPONENT_DSI3)
- if (!comp_dsi)
- comp_dsi = mtk_crtc->ddp_comp[i];
-
- if (mtk_crtc->ddp_comp[i]->id == DDP_COMPONENT_DSC0 ||
- mtk_crtc->ddp_comp[i]->id == DDP_COMPONENT_DSC1)
- if (!comp_dsc)
- comp_dsc = mtk_crtc->ddp_comp[i];
+ struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[i];
+ struct mtk_ddp_comp *next = mtk_crtc->ddp_comp[i + 1];
+
+ if (!mtk_ddp_comp_connect(comp, mtk_crtc->mmsys_dev, next))
+ mtk_mmsys_hw_connect(mtk_crtc->mmsys_dev,
+ comp->type, comp->inst_id,
+ next->type, next->inst_id);
+
+ if (!mtk_ddp_comp_add(comp, mtk_crtc->mutex))
+ mtk_mutex_add_trigger(mtk_crtc->mutex,
+ comp->type, comp->inst_id,
+ comp->mtx_trig_id);
+
+ /* For DSC only single DSI is supported at the moment */
+ if (comp->type == MTK_DISP_DSI && !comp_dsi)
+ comp_dsi = mtk_crtc->ddp_comp[i];
+
+ if (comp->type == MTK_DISP_DSC && !comp_dsc)
+ comp_dsc = mtk_crtc->ddp_comp[i];
}
if (!mtk_ddp_comp_add(mtk_crtc->ddp_comp[i], mtk_crtc->mutex))
- mtk_mutex_add_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id);
+ mtk_mutex_add_trigger(mtk_crtc->mutex,
+ mtk_crtc->ddp_comp[i]->type,
+ mtk_crtc->ddp_comp[i]->inst_id,
+ mtk_crtc->ddp_comp[i]->mtx_trig_id);
+
mtk_mutex_enable(mtk_crtc->mutex);
for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
@@ -493,21 +497,31 @@ static void mtk_crtc_ddp_hw_fini(struct mtk_crtc *mtk_crtc)
for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
if (!mtk_ddp_comp_remove(mtk_crtc->ddp_comp[i], mtk_crtc->mutex))
- mtk_mutex_remove_comp(mtk_crtc->mutex,
- mtk_crtc->ddp_comp[i]->id);
+ mtk_mutex_remove_trigger(mtk_crtc->mutex,
+ mtk_crtc->ddp_comp[i]->type,
+ mtk_crtc->ddp_comp[i]->inst_id,
+ mtk_crtc->ddp_comp[i]->mtx_trig_id);
mtk_mutex_disable(mtk_crtc->mutex);
for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
- if (!mtk_ddp_comp_disconnect(mtk_crtc->ddp_comp[i], mtk_crtc->mmsys_dev,
- mtk_crtc->ddp_comp[i + 1]->id))
- mtk_mmsys_ddp_disconnect(mtk_crtc->mmsys_dev,
- mtk_crtc->ddp_comp[i]->id,
- mtk_crtc->ddp_comp[i + 1]->id);
+ struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[i];
+ struct mtk_ddp_comp *next = mtk_crtc->ddp_comp[i + 1];
+
+ if (!mtk_ddp_comp_disconnect(comp, mtk_crtc->mmsys_dev, next))
+ mtk_mmsys_hw_disconnect(mtk_crtc->mmsys_dev,
+ comp->type, comp->inst_id,
+ next->type, next->inst_id);
+
if (!mtk_ddp_comp_remove(mtk_crtc->ddp_comp[i], mtk_crtc->mutex))
- mtk_mutex_remove_comp(mtk_crtc->mutex,
- mtk_crtc->ddp_comp[i]->id);
+ mtk_mutex_remove_trigger(mtk_crtc->mutex,
+ mtk_crtc->ddp_comp[i]->type,
+ mtk_crtc->ddp_comp[i]->inst_id,
+ mtk_crtc->ddp_comp[i]->mtx_trig_id);
}
if (!mtk_ddp_comp_remove(mtk_crtc->ddp_comp[i], mtk_crtc->mutex))
- mtk_mutex_remove_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id);
+ mtk_mutex_remove_trigger(mtk_crtc->mutex,
+ mtk_crtc->ddp_comp[i]->type,
+ mtk_crtc->ddp_comp[i]->inst_id,
+ mtk_crtc->ddp_comp[i]->mtx_trig_id);
mtk_crtc_ddp_clk_disable(mtk_crtc);
mtk_mutex_unprepare(mtk_crtc->mutex);
@@ -738,15 +752,16 @@ static void mtk_crtc_update_output(struct drm_crtc *crtc,
const struct mtk_drm_route *conn_route = &mtk_crtc->conn_routes[i];
struct mtk_ddp_comp *comp;
- comp = mtk_ddp_comp_find_by_id(&priv->hlist, conn_route->route_ddp);
+ comp = mtk_ddp_comp_find_by_id(&priv->hlist, conn_route->route_ddp_type,
+ conn_route->route_ddp_inst_id);
if (!comp)
continue;
if (comp->encoder_index >= 0 &&
(encoder_mask & BIT(comp->encoder_index))) {
mtk_crtc->ddp_comp[mtk_crtc->ddp_comp_nr - 1] = comp;
- dev_dbg(dev, "Add comp_id: %d at path index %d\n",
- comp->id, mtk_crtc->ddp_comp_nr - 1);
+ dev_dbg(dev, "Add comp %u-%u at path index %d\n",
+ comp->type, comp->inst_id, mtk_crtc->ddp_comp_nr - 1);
break;
}
}
@@ -1142,25 +1157,15 @@ int mtk_crtc_create(struct drm_device *drm_dev,
crtc_i++;
for (i = 0; i < output_path[i].len; i++) {
- enum mtk_ddp_comp_id comp_id = output_path->comp[i].type;
- struct device_node *node;
+ enum mtk_ddp_comp_type comp_type = output_path->comp[i].type;
+ u8 comp_inst = output_path->comp[i].inst_id;
struct mtk_ddp_comp *comp;
- node = priv->comp_node[comp_id];
- comp = mtk_ddp_comp_find_by_id(&priv->hlist, comp_id);
-
- /* Not all drm components have a DTS device node, such as ovl_adaptor,
- * which is the drm bring up sub driver
- */
- if (!node && comp_id != DDP_COMPONENT_DRM_OVL_ADAPTOR) {
- dev_info(dev,
- "Not creating crtc %d because component %d is disabled or missing\n",
- crtc_i, comp_id);
- return 0;
- }
-
+ comp = mtk_ddp_comp_find_by_id(&priv->hlist, comp_type, comp_inst);
if (!comp || !comp->dev) {
- dev_err(dev, "Component %pOF not initialized\n", node);
+ dev_err(dev,
+ "CRTC%d: Component type=%u inst=%u not initialized\n",
+ crtc_i, comp_type, comp_inst);
return -ENODEV;
}
}
@@ -1190,13 +1195,14 @@ int mtk_crtc_create(struct drm_device *drm_dev,
mtk_crtc->config_comp_idx = -EINVAL;
for (i = 0, j = 0; i < mtk_crtc->ddp_comp_nr; i++, j++) {
- unsigned int comp_id = output_path->comp[i].type;
+ enum mtk_ddp_comp_type comp_type = output_path->comp[i].type;
+ u8 comp_inst = output_path->comp[i].inst_id;
struct mtk_ddp_comp *comp;
- comp = mtk_ddp_comp_find_by_id(&priv->hlist, comp_id);
+ comp = mtk_ddp_comp_find_by_id(&priv->hlist, comp_type, comp_inst);
if (!comp) {
j--;
- dev_dbg(dev, "Cannot find component %d.\n", comp_id);
+ dev_dbg(dev, "Cannot find component %u-%u.\n", comp_type, comp_inst);
continue;
}
mtk_crtc->ddp_comp[j] = comp;
@@ -1308,7 +1314,9 @@ int mtk_crtc_create(struct drm_device *drm_dev,
* In the case of ovl_adaptor sub driver, it needs to use the
* dma_dev_get function to get representative dma dev.
*/
- dma_comp = mtk_ddp_comp_find_by_id(&priv->hlist, output_path->comp[0].type);
+ dma_comp = mtk_ddp_comp_find_by_id(&priv->hlist,
+ output_path->comp[0].type,
+ output_path->comp[0].inst_id);
if (dma_comp == NULL) {
dev_err(dev, "Could not find appropriate DMA device!\n");
return -EINVAL;
@@ -1370,13 +1378,15 @@ int mtk_crtc_create(struct drm_device *drm_dev,
if (conn_routes) {
for (i = 0; i < num_conn_routes; i++) {
- unsigned int comp_id = conn_routes[i].route_ddp;
- struct device_node *node = priv->comp_node[comp_id];
- struct mtk_ddp_comp *comp = mtk_ddp_comp_find_by_id(&priv->hlist, comp_id);
+ enum mtk_ddp_comp_type comp_type = conn_routes[i].route_ddp_type;
+ u8 comp_inst = conn_routes[i].route_ddp_inst_id;
+ struct mtk_ddp_comp *comp;
+ comp = mtk_ddp_comp_find_by_id(&priv->hlist, comp_type, comp_inst);
if (!comp || !comp->dev) {
- dev_dbg(dev, "comp_id:%d, Component %pOF not initialized\n",
- comp_id, node);
+ dev_dbg(dev, "Cannot find conn_route component %u-%u.\n",
+ comp_type, comp_inst);
+
/* mark encoder_index to -1, if route comp device is not enabled */
if (comp)
comp->encoder_index = -1;
diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
index f45588ae7342..3be891f740d3 100644
--- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
@@ -4,6 +4,10 @@
* Authors:
* YT Shen <yt.shen@mediatek.com>
* CK Hu <ck.hu@mediatek.com>
+ *
+ * Major refactoring
+ * Copyright (c) 2026 Collabora Ltd.
+ * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
*/
#include <linux/clk.h>
@@ -428,65 +432,36 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_DSI] = "dsi",
};
-struct mtk_ddp_comp_match {
- enum mtk_ddp_comp_type type;
- int alias_id;
- const struct mtk_ddp_comp_funcs *funcs;
-};
-
-static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_DRM_ID_MAX] = {
- [DDP_COMPONENT_AAL0] = { MTK_DISP_AAL, 0, &ddp_aal },
- [DDP_COMPONENT_AAL1] = { MTK_DISP_AAL, 1, &ddp_aal },
- [DDP_COMPONENT_BLS] = { MTK_DISP_BLS, 0, NULL },
- [DDP_COMPONENT_CCORR] = { MTK_DISP_CCORR, 0, &ddp_ccorr },
- [DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color },
- [DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color },
- [DDP_COMPONENT_DITHER0] = { MTK_DISP_DITHER, 0, &ddp_dither },
- [DDP_COMPONENT_DP_INTF0] = { MTK_DISP_DP_INTF, 0, &ddp_dpi },
- [DDP_COMPONENT_DP_INTF1] = { MTK_DISP_DP_INTF, 1, &ddp_dpi },
- [DDP_COMPONENT_DPI0] = { MTK_DISP_DPI, 0, &ddp_dpi },
- [DDP_COMPONENT_DPI1] = { MTK_DISP_DPI, 1, &ddp_dpi },
- [DDP_COMPONENT_DRM_OVL_ADAPTOR] = { MTK_DISP_OVL_ADAPTOR, 0, &ddp_ovl_adaptor },
- [DDP_COMPONENT_DSC0] = { MTK_DISP_DSC, 0, &ddp_dsc },
- [DDP_COMPONENT_DSC1] = { MTK_DISP_DSC, 1, &ddp_dsc },
- [DDP_COMPONENT_DSI0] = { MTK_DISP_DSI, 0, &ddp_dsi },
- [DDP_COMPONENT_DSI1] = { MTK_DISP_DSI, 1, &ddp_dsi },
- [DDP_COMPONENT_DSI2] = { MTK_DISP_DSI, 2, &ddp_dsi },
- [DDP_COMPONENT_DSI3] = { MTK_DISP_DSI, 3, &ddp_dsi },
- [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma },
- [DDP_COMPONENT_MERGE0] = { MTK_DISP_MERGE, 0, &ddp_merge },
- [DDP_COMPONENT_MERGE1] = { MTK_DISP_MERGE, 1, &ddp_merge },
- [DDP_COMPONENT_MERGE2] = { MTK_DISP_MERGE, 2, &ddp_merge },
- [DDP_COMPONENT_MERGE3] = { MTK_DISP_MERGE, 3, &ddp_merge },
- [DDP_COMPONENT_MERGE4] = { MTK_DISP_MERGE, 4, &ddp_merge },
- [DDP_COMPONENT_MERGE5] = { MTK_DISP_MERGE, 5, &ddp_merge },
- [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od },
- [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od },
- [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl },
- [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, &ddp_ovl },
- [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, &ddp_ovl },
- [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, &ddp_ovl },
- [DDP_COMPONENT_OVL_2L2] = { MTK_DISP_OVL_2L, 2, &ddp_ovl },
- [DDP_COMPONENT_POSTMASK0] = { MTK_DISP_POSTMASK, 0, &ddp_postmask },
- [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL },
- [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL },
- [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL },
- [DDP_COMPONENT_RDMA0] = { MTK_DISP_RDMA, 0, &ddp_rdma },
- [DDP_COMPONENT_RDMA1] = { MTK_DISP_RDMA, 1, &ddp_rdma },
- [DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma },
- [DDP_COMPONENT_RDMA4] = { MTK_DISP_RDMA, 4, &ddp_rdma },
- [DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe },
- [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, &ddp_wdma },
- [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, &ddp_wdma },
+static const struct mtk_ddp_comp_funcs *mtk_ddp_funcs[MTK_DDP_COMP_TYPE_MAX] = {
+ [MTK_DISP_AAL] = &ddp_aal,
+ [MTK_DISP_BLS] = NULL,
+ [MTK_DISP_CCORR] = &ddp_ccorr,
+ [MTK_DISP_COLOR] = &ddp_color,
+ [MTK_DISP_DITHER] = &ddp_dither,
+ [MTK_DISP_DSC] = &ddp_dsc,
+ [MTK_DISP_GAMMA] = &ddp_gamma,
+ [MTK_DISP_MERGE] = &ddp_merge,
+ [MTK_DISP_OD] = &ddp_od,
+ [MTK_DISP_OVL] = &ddp_ovl,
+ [MTK_DISP_OVL_2L] = &ddp_ovl,
+ [MTK_DISP_OVL_ADAPTOR] = &ddp_ovl_adaptor,
+ [MTK_DISP_POSTMASK] = &ddp_postmask,
+ [MTK_DISP_PWM] = NULL,
+ [MTK_DISP_RDMA] = &ddp_rdma,
+ [MTK_DISP_UFOE] = &ddp_ufoe,
+ [MTK_DISP_WDMA] = &ddp_wdma,
+ [MTK_DISP_DPI] = &ddp_dpi,
+ [MTK_DISP_DP_INTF] = &ddp_dpi,
+ [MTK_DISP_DSI] = &ddp_dsi,
};
static bool mtk_ddp_find_comp_dev_in_table(const struct mtk_drm_comp_list *hlist,
- const unsigned int comp_id,
+ const unsigned int comp_type,
struct device *dev)
{
struct mtk_ddp_comp *ddp_comp;
- hash_for_each_possible(hlist->ddp_list, ddp_comp, lnode, comp_id) {
+ hash_for_each_possible(hlist->ddp_list, ddp_comp, lnode, comp_type) {
if (ddp_comp->dev == dev)
return true;
}
@@ -518,42 +493,23 @@ static int mtk_ddp_comp_find_in_route(struct device *dev,
return -EINVAL;
for (i = 0; i < num_routes; i++)
- if (mtk_ddp_find_comp_dev_in_table(hlist, routes[i].route_ddp, dev))
+ if (mtk_ddp_find_comp_dev_in_table(hlist, routes[i].route_ddp_type, dev))
return BIT(routes[i].crtc_id);
return -ENODEV;
}
-static bool mtk_ddp_path_available(const struct mtk_drm_path_definition *output_path,
- struct device_node **comp_node)
-{
- unsigned int i;
-
- for (i = 0U; i < output_path->len; i++) {
- /* OVL_ADAPTOR doesn't have a device node */
- if (output_path->comp[i].type == DDP_COMPONENT_DRM_OVL_ADAPTOR)
- continue;
-
- if (!comp_node[output_path->comp[i].type])
- return false;
- }
-
- return true;
-}
-
int mtk_ddp_comp_get_id(struct device_node *node,
enum mtk_ddp_comp_type comp_type)
{
- int id = of_alias_get_id(node, mtk_ddp_comp_stem[comp_type]);
- int i;
-
- for (i = 0; i < ARRAY_SIZE(mtk_ddp_matches); i++) {
- if (comp_type == mtk_ddp_matches[i].type &&
- (id < 0 || id == mtk_ddp_matches[i].alias_id))
- return i;
+ /* If there's an alias, return the ID from that */
+ if (mtk_ddp_comp_stem[comp_type]) {
+ int alias_id = of_alias_get_id(node, mtk_ddp_comp_stem[comp_type]);
+ if (alias_id >= 0)
+ return alias_id;
}
- return -EINVAL;
+ return 0;
}
int mtk_find_possible_crtcs(struct drm_device *drm, struct device *dev)
@@ -561,7 +517,7 @@ int mtk_find_possible_crtcs(struct drm_device *drm, struct device *dev)
struct mtk_drm_private *private = drm->dev_private;
const struct mtk_mmsys_driver_data *data;
struct mtk_drm_private *priv_n;
- int i = 0, j;
+ int i, j;
int ret;
for (j = 0; j < private->data->mmsys_dev_num; j++) {
@@ -674,24 +630,22 @@ static int mtk_ddp_comp_init_internal_comp(struct device *dev, struct device *co
int mtk_ddp_comp_init(struct device *dev, struct device_node *node,
struct mtk_drm_comp_list *hlist,
- unsigned int comp_id)
+ enum mtk_ddp_comp_type comp_type, int comp_inst_id)
{
struct platform_device *comp_pdev;
struct mtk_ddp_comp *comp;
- enum mtk_ddp_comp_type type;
int ret;
- if (comp_id >= DDP_COMPONENT_DRM_ID_MAX)
+ if (comp_type >= MTK_DDP_COMP_TYPE_MAX)
return -EINVAL;
comp = devm_kzalloc(dev, sizeof(*comp), GFP_KERNEL);
if (!comp)
return -ENOMEM;
- type = mtk_ddp_matches[comp_id].type;
-
- comp->id = comp_id;
- comp->funcs = mtk_ddp_matches[comp_id].funcs;
+ comp->type = comp_type;
+ comp->inst_id = comp_inst_id;
+ comp->funcs = mtk_ddp_funcs[comp_type];
/* Not all drm components have a DTS device node, such as ovl_adaptor,
* which is the drm bring up sub driver
*/
@@ -716,13 +670,14 @@ int mtk_ddp_comp_init(struct device *dev, struct device_node *node,
comp->mtx_trig_id = ret;
/* If there's no external driver for this component, allocate and init now */
- if (mtk_ddp_comp_is_internal_comp(type) || mtk_ddp_comp_is_backlight_comp(type)) {
+ if (mtk_ddp_comp_is_internal_comp(comp->type) ||
+ mtk_ddp_comp_is_backlight_comp(comp->type)) {
ret = mtk_ddp_comp_init_internal_comp(dev, comp->dev);
if (ret)
return ret;
}
end:
- hash_add(hlist->ddp_list, &comp->lnode, comp->id);
+ hash_add(hlist->ddp_list, &comp->lnode, comp->type);
return 0;
}
diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
index a7ed46a95037..ab9d5e4dfb98 100644
--- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
@@ -16,6 +16,7 @@
#include <drm/drm_modes.h>
#define MTK_DISP_CONTROLLER_MAX_COMP_PER_PATH 24
+#define MTK_DISP_CONTROLLER_MAX_HW_COMP_INSTANCE 32
struct device;
struct device_node;
@@ -70,8 +71,10 @@ struct mtk_ddp_comp_funcs {
const u32 *(*get_formats)(struct device *dev);
size_t (*get_num_formats)(struct device *dev);
bool (*is_afbc_supported)(struct device *dev);
- void (*connect)(struct device *dev, struct device *mmsys_dev, unsigned int next);
- void (*disconnect)(struct device *dev, struct device *mmsys_dev, unsigned int next);
+ void (*connect)(struct mtk_ddp_comp *comp, struct device *mmsys_dev,
+ struct mtk_ddp_comp *next);
+ void (*disconnect)(struct mtk_ddp_comp *comp, struct device *mmsys_dev,
+ struct mtk_ddp_comp *next);
void (*add)(struct device *dev, struct mtk_mutex *mutex);
void (*remove)(struct device *dev, struct mtk_mutex *mutex);
unsigned int (*encoder_index)(struct device *dev);
@@ -81,7 +84,8 @@ struct mtk_ddp_comp_funcs {
struct mtk_ddp_comp {
struct device *dev;
int irq;
- unsigned int id;
+ enum mtk_ddp_comp_type type;
+ u8 inst_id;
u8 mtx_trig_id;
int encoder_index;
const struct mtk_ddp_comp_funcs *funcs;
@@ -326,20 +330,20 @@ static inline bool mtk_ddp_comp_remove(struct mtk_ddp_comp *comp, struct mtk_mut
}
static inline bool mtk_ddp_comp_connect(struct mtk_ddp_comp *comp, struct device *mmsys_dev,
- unsigned int next)
+ struct mtk_ddp_comp *next)
{
if (comp->funcs && comp->funcs->connect) {
- comp->funcs->connect(comp->dev, mmsys_dev, next);
+ comp->funcs->connect(comp, mmsys_dev, next);
return true;
}
return false;
}
static inline bool mtk_ddp_comp_disconnect(struct mtk_ddp_comp *comp, struct device *mmsys_dev,
- unsigned int next)
+ struct mtk_ddp_comp *next)
{
if (comp->funcs && comp->funcs->disconnect) {
- comp->funcs->disconnect(comp->dev, mmsys_dev, next);
+ comp->funcs->disconnect(comp, mmsys_dev, next);
return true;
}
return false;
@@ -353,12 +357,14 @@ static inline void mtk_ddp_comp_encoder_index_set(struct mtk_ddp_comp *comp)
static inline struct mtk_ddp_comp
*mtk_ddp_comp_find_by_id(struct mtk_drm_comp_list *hlist,
- const unsigned int id)
+ const unsigned int comp_type,
+ const unsigned int comp_inst_id)
{
struct mtk_ddp_comp *ddp_comp;
- hash_for_each_possible(hlist->ddp_list, ddp_comp, lnode, id)
- return ddp_comp;
+ hash_for_each_possible(hlist->ddp_list, ddp_comp, lnode, comp_type)
+ if (ddp_comp->inst_id == comp_inst_id)
+ return ddp_comp;
return NULL;
}
@@ -369,7 +375,7 @@ int mtk_ddp_comp_get_id(struct device_node *node,
int mtk_find_possible_crtcs(struct drm_device *drm, struct device *dev);
int mtk_ddp_comp_init(struct device *dev, struct device_node *node,
struct mtk_drm_comp_list *hlist,
- unsigned int comp_id);
+ enum mtk_ddp_comp_type comp_type, int comp_inst_id);
int mtk_ddp_comp_get_mutex_trigger(struct device_node *node, unsigned int index);
enum mtk_ddp_comp_type mtk_ddp_comp_get_type(unsigned int comp_id);
void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value,
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 7706d95b3be8..c4b44b761633 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -11,6 +11,7 @@
#include <linux/soc/mediatek/mtk-cmdq.h>
#include <linux/soc/mediatek/mtk-mmsys.h>
#include <linux/soc/mediatek/mtk-mutex.h>
+#include "mtk_ddp_comp.h"
#include "mtk_mdp_rdma.h"
#include "mtk_plane.h"
@@ -122,10 +123,10 @@ bool mtk_ovl_is_afbc_supported(struct device *dev);
void mtk_ovl_adaptor_add_comp(struct device *dev, struct mtk_mutex *mutex);
void mtk_ovl_adaptor_remove_comp(struct device *dev, struct mtk_mutex *mutex);
bool mtk_ovl_adaptor_is_comp_present(struct device_node *node);
-void mtk_ovl_adaptor_connect(struct device *dev, struct device *mmsys_dev,
- unsigned int next);
-void mtk_ovl_adaptor_disconnect(struct device *dev, struct device *mmsys_dev,
- unsigned int next);
+void mtk_ovl_adaptor_connect(struct mtk_ddp_comp *comp, struct device *mmsys_dev,
+ struct mtk_ddp_comp *next);
+void mtk_ovl_adaptor_disconnect(struct mtk_ddp_comp *comp, struct device *mmsys_dev,
+ struct mtk_ddp_comp *next);
int mtk_ovl_adaptor_power_on(struct device *dev);
void mtk_ovl_adaptor_power_off(struct device *dev);
int mtk_ovl_adaptor_clk_enable(struct device *dev);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
index 78bc3bee0794..225ab87bca71 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl_adaptor.c
@@ -61,7 +61,7 @@ enum mtk_ovl_adaptor_comp_id {
struct ovl_adaptor_comp_match {
enum mtk_ovl_adaptor_comp_type type;
- enum mtk_ddp_comp_id comp_id;
+ enum mtk_ddp_comp_type comp_type;
int alias_id;
const struct mtk_ddp_comp_funcs *funcs;
};
@@ -108,27 +108,27 @@ static const struct mtk_ddp_comp_funcs rdma = {
};
static const struct ovl_adaptor_comp_match comp_matches[OVL_ADAPTOR_ID_MAX] = {
- [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, DDP_COMPONENT_ETHDR_MIXER, 0, ðdr },
- [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA0, 0, &rdma },
- [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA1, 1, &rdma },
- [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA2, 2, &rdma },
- [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA3, 3, &rdma },
- [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA4, 4, &rdma },
- [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA5, 5, &rdma },
- [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA6, 6, &rdma },
- [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_MDP_RDMA, DDP_COMPONENT_MDP_RDMA7, 7, &rdma },
- [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE1, 1, &merge },
- [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE2, 2, &merge },
- [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE3, 3, &merge },
- [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, DDP_COMPONENT_MERGE4, 4, &merge },
- [OVL_ADAPTOR_PADDING0] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING0, 0, &padding },
- [OVL_ADAPTOR_PADDING1] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING1, 1, &padding },
- [OVL_ADAPTOR_PADDING2] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING2, 2, &padding },
- [OVL_ADAPTOR_PADDING3] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING3, 3, &padding },
- [OVL_ADAPTOR_PADDING4] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING4, 4, &padding },
- [OVL_ADAPTOR_PADDING5] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING5, 5, &padding },
- [OVL_ADAPTOR_PADDING6] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING6, 6, &padding },
- [OVL_ADAPTOR_PADDING7] = { OVL_ADAPTOR_TYPE_PADDING, DDP_COMPONENT_PADDING7, 7, &padding },
+ [OVL_ADAPTOR_ETHDR0] = { OVL_ADAPTOR_TYPE_ETHDR, MTK_DISP_ETHDR_MIXER, 0, ðdr },
+ [OVL_ADAPTOR_MDP_RDMA0] = { OVL_ADAPTOR_TYPE_MDP_RDMA, MTK_DISP_MDP_RDMA, 0, &rdma },
+ [OVL_ADAPTOR_MDP_RDMA1] = { OVL_ADAPTOR_TYPE_MDP_RDMA, MTK_DISP_MDP_RDMA, 1, &rdma },
+ [OVL_ADAPTOR_MDP_RDMA2] = { OVL_ADAPTOR_TYPE_MDP_RDMA, MTK_DISP_MDP_RDMA, 2, &rdma },
+ [OVL_ADAPTOR_MDP_RDMA3] = { OVL_ADAPTOR_TYPE_MDP_RDMA, MTK_DISP_MDP_RDMA, 3, &rdma },
+ [OVL_ADAPTOR_MDP_RDMA4] = { OVL_ADAPTOR_TYPE_MDP_RDMA, MTK_DISP_MDP_RDMA, 4, &rdma },
+ [OVL_ADAPTOR_MDP_RDMA5] = { OVL_ADAPTOR_TYPE_MDP_RDMA, MTK_DISP_MDP_RDMA, 5, &rdma },
+ [OVL_ADAPTOR_MDP_RDMA6] = { OVL_ADAPTOR_TYPE_MDP_RDMA, MTK_DISP_MDP_RDMA, 6, &rdma },
+ [OVL_ADAPTOR_MDP_RDMA7] = { OVL_ADAPTOR_TYPE_MDP_RDMA, MTK_DISP_MDP_RDMA, 7, &rdma },
+ [OVL_ADAPTOR_MERGE0] = { OVL_ADAPTOR_TYPE_MERGE, MTK_DISP_MERGE, 1, &merge },
+ [OVL_ADAPTOR_MERGE1] = { OVL_ADAPTOR_TYPE_MERGE, MTK_DISP_MERGE, 2, &merge },
+ [OVL_ADAPTOR_MERGE2] = { OVL_ADAPTOR_TYPE_MERGE, MTK_DISP_MERGE, 3, &merge },
+ [OVL_ADAPTOR_MERGE3] = { OVL_ADAPTOR_TYPE_MERGE, MTK_DISP_MERGE, 4, &merge },
+ [OVL_ADAPTOR_PADDING0] = { OVL_ADAPTOR_TYPE_PADDING, MTK_DISP_PADDING, 0, &padding },
+ [OVL_ADAPTOR_PADDING1] = { OVL_ADAPTOR_TYPE_PADDING, MTK_DISP_PADDING, 1, &padding },
+ [OVL_ADAPTOR_PADDING2] = { OVL_ADAPTOR_TYPE_PADDING, MTK_DISP_PADDING, 2, &padding },
+ [OVL_ADAPTOR_PADDING3] = { OVL_ADAPTOR_TYPE_PADDING, MTK_DISP_PADDING, 3, &padding },
+ [OVL_ADAPTOR_PADDING4] = { OVL_ADAPTOR_TYPE_PADDING, MTK_DISP_PADDING, 4, &padding },
+ [OVL_ADAPTOR_PADDING5] = { OVL_ADAPTOR_TYPE_PADDING, MTK_DISP_PADDING, 5, &padding },
+ [OVL_ADAPTOR_PADDING6] = { OVL_ADAPTOR_TYPE_PADDING, MTK_DISP_PADDING, 6, &padding },
+ [OVL_ADAPTOR_PADDING7] = { OVL_ADAPTOR_TYPE_PADDING, MTK_DISP_PADDING, 7, &padding },
};
void mtk_ovl_adaptor_layer_config(struct device *dev, unsigned int idx,
@@ -431,7 +431,11 @@ void mtk_ovl_adaptor_add_comp(struct device *dev, struct mtk_mutex *mutex)
for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
if (!ovl_adaptor->ovl_adaptor_comp[i])
continue;
- mtk_mutex_add_comp(mutex, comp_matches[i].comp_id);
+
+ mtk_mutex_add_trigger(mutex,
+ comp_matches[i].comp_type,
+ comp_matches[i].alias_id,
+ ovl_adaptor->mtx_trig_ids[i]);
}
}
@@ -443,32 +447,38 @@ void mtk_ovl_adaptor_remove_comp(struct device *dev, struct mtk_mutex *mutex)
for (i = 0; i < OVL_ADAPTOR_ID_MAX; i++) {
if (!ovl_adaptor->ovl_adaptor_comp[i])
continue;
- mtk_mutex_remove_comp(mutex, comp_matches[i].comp_id);
+
+ mtk_mutex_remove_trigger(mutex,
+ comp_matches[i].comp_type,
+ comp_matches[i].alias_id,
+ ovl_adaptor->mtx_trig_ids[i]);
}
}
-void mtk_ovl_adaptor_connect(struct device *dev, struct device *mmsys_dev, unsigned int next)
+void mtk_ovl_adaptor_connect(struct mtk_ddp_comp *comp, struct device *mmsys_dev,
+ struct mtk_ddp_comp *next)
{
- mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_ETHDR_MIXER, next);
- mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1);
- mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1);
- mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2);
- mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER);
- mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER);
- mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER);
- mtk_mmsys_ddp_connect(mmsys_dev, DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER);
+ mtk_mmsys_hw_connect(mmsys_dev, MTK_DISP_ETHDR_MIXER, 0, next->type, next->inst_id);
+ mtk_mmsys_hw_connect(mmsys_dev, MTK_DISP_MDP_RDMA, 0, MTK_DISP_MERGE, 1);
+ mtk_mmsys_hw_connect(mmsys_dev, MTK_DISP_MDP_RDMA, 1, MTK_DISP_MERGE, 1);
+ mtk_mmsys_hw_connect(mmsys_dev, MTK_DISP_MDP_RDMA, 2, MTK_DISP_MERGE, 2);
+ mtk_mmsys_hw_connect(mmsys_dev, MTK_DISP_MERGE, 1, MTK_DISP_ETHDR_MIXER, 0);
+ mtk_mmsys_hw_connect(mmsys_dev, MTK_DISP_MERGE, 2, MTK_DISP_ETHDR_MIXER, 0);
+ mtk_mmsys_hw_connect(mmsys_dev, MTK_DISP_MERGE, 3, MTK_DISP_ETHDR_MIXER, 0);
+ mtk_mmsys_hw_connect(mmsys_dev, MTK_DISP_MERGE, 4, MTK_DISP_ETHDR_MIXER, 0);
}
-void mtk_ovl_adaptor_disconnect(struct device *dev, struct device *mmsys_dev, unsigned int next)
+void mtk_ovl_adaptor_disconnect(struct mtk_ddp_comp *comp, struct device *mmsys_dev,
+ struct mtk_ddp_comp *next)
{
- mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_ETHDR_MIXER, next);
- mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MDP_RDMA0, DDP_COMPONENT_MERGE1);
- mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MDP_RDMA1, DDP_COMPONENT_MERGE1);
- mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MDP_RDMA2, DDP_COMPONENT_MERGE2);
- mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MERGE1, DDP_COMPONENT_ETHDR_MIXER);
- mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MERGE2, DDP_COMPONENT_ETHDR_MIXER);
- mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MERGE3, DDP_COMPONENT_ETHDR_MIXER);
- mtk_mmsys_ddp_disconnect(mmsys_dev, DDP_COMPONENT_MERGE4, DDP_COMPONENT_ETHDR_MIXER);
+ mtk_mmsys_hw_disconnect(mmsys_dev, MTK_DISP_ETHDR_MIXER, 0, next->type, next->inst_id);
+ mtk_mmsys_hw_disconnect(mmsys_dev, MTK_DISP_MDP_RDMA, 0, MTK_DISP_MERGE, 1);
+ mtk_mmsys_hw_disconnect(mmsys_dev, MTK_DISP_MDP_RDMA, 1, MTK_DISP_MERGE, 1);
+ mtk_mmsys_hw_disconnect(mmsys_dev, MTK_DISP_MDP_RDMA, 2, MTK_DISP_MERGE, 2);
+ mtk_mmsys_hw_disconnect(mmsys_dev, MTK_DISP_MERGE, 1, MTK_DISP_ETHDR_MIXER, 0);
+ mtk_mmsys_hw_disconnect(mmsys_dev, MTK_DISP_MERGE, 2, MTK_DISP_ETHDR_MIXER, 0);
+ mtk_mmsys_hw_disconnect(mmsys_dev, MTK_DISP_MERGE, 3, MTK_DISP_ETHDR_MIXER, 0);
+ mtk_mmsys_hw_disconnect(mmsys_dev, MTK_DISP_MERGE, 4, MTK_DISP_ETHDR_MIXER, 0);
}
static int ovl_adaptor_comp_get_id(struct device *dev, struct device_node *node,
@@ -557,12 +567,12 @@ static int ovl_adaptor_comp_init(struct device *dev, struct device_node *mutex_n
parent = dev->parent->parent->of_node->parent;
for_each_child_of_node_scoped(parent, node) {
- enum mtk_ovl_adaptor_comp_type type;
- enum mtk_ddp_comp_id ddp_type;
+ enum mtk_ovl_adaptor_comp_type ovla_type;
+ enum mtk_ddp_comp_type ddp_type;
+ u8 ddp_inst_id, mtx_id;
int id, ret;
- u8 mtx_id;
- ret = ovl_adaptor_of_get_ddp_comp_type(node, &type);
+ ret = ovl_adaptor_of_get_ddp_comp_type(node, &ovla_type);
if (ret)
continue;
@@ -572,15 +582,17 @@ static int ovl_adaptor_comp_init(struct device *dev, struct device_node *mutex_n
continue;
}
- id = ovl_adaptor_comp_get_id(dev, node, type);
+ id = ovl_adaptor_comp_get_id(dev, node, ovla_type);
if (id < 0) {
dev_warn(dev, "Skipping unknown component %pOF\n",
node);
continue;
}
- ddp_type = comp_matches[id].comp_id;
+ ddp_type = comp_matches[id].comp_type;
+ ddp_inst_id = comp_matches[id].alias_id;
mtx_id = mtk_drm_legacy_get_ovl_adaptor_mutex_trig_id(ddp_type,
+ ddp_inst_id,
mutex_node);
comp_pdev = of_find_device_by_node(node);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index cdff5edd09da..f7cbf9b47672 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -102,8 +102,8 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
};
static const struct mtk_drm_route mt8188_mtk_ddp_main_routes[] = {
- { 0, DDP_COMPONENT_DP_INTF0 },
- { 0, DDP_COMPONENT_DSI0 },
+ { 0, MTK_DISP_DP_INTF, 0 },
+ { 0, MTK_DISP_DSI, 0 },
};
static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = {
@@ -245,7 +245,8 @@ static bool mtk_drm_get_all_drm_priv(struct device *dev)
return false;
}
-static bool mtk_drm_find_mmsys_comp(struct mtk_drm_private *private, int comp_id)
+static bool mtk_drm_find_mmsys_comp(struct mtk_drm_private *private,
+ enum mtk_ddp_comp_type type, u8 inst_id)
{
const struct mtk_mmsys_driver_data *data = private->data;
int i, j;
@@ -254,7 +255,8 @@ static bool mtk_drm_find_mmsys_comp(struct mtk_drm_private *private, int comp_id
const struct mtk_drm_path_definition *output_path = &data->output_paths[i];
for (j = 0; j < output_path->len; j++) {
- if (output_path->comp[j].type != comp_id)
+ if (output_path->comp[j].type != type ||
+ output_path->comp[j].inst_id != inst_id)
continue;
return true;
@@ -263,7 +265,8 @@ static bool mtk_drm_find_mmsys_comp(struct mtk_drm_private *private, int comp_id
if (data->num_conn_routes)
for (i = 0; i < data->num_conn_routes; i++)
- if (data->conn_routes[i].route_ddp == comp_id)
+ if (data->conn_routes[i].route_ddp_type == type &&
+ data->conn_routes[i].route_ddp_inst_id == inst_id)
return true;
return false;
@@ -635,7 +638,7 @@ static int mtk_drm_of_get_ddp_comp_type(struct device_node *node, enum mtk_ddp_c
return 0;
}
-static int mtk_drm_of_get_ddp_ep_cid(struct device_node *node,
+static int mtk_drm_of_get_ddp_ep_cid(struct device *dev, struct device_node *node,
int output_port, enum mtk_crtc_path crtc_path,
struct device_node **next,
struct mtk_drm_comp_definition *comp_def)
@@ -666,7 +669,9 @@ static int mtk_drm_of_get_ddp_ep_cid(struct device_node *node,
ret = mtk_drm_of_get_ddp_comp_type(ep_dev_node, &comp_type);
if (ret) {
if (mtk_ovl_adaptor_is_comp_present(ep_dev_node)) {
- comp_def->type = DDP_COMPONENT_DRM_OVL_ADAPTOR;
+ comp_def->type = MTK_DISP_OVL_ADAPTOR;
+ comp_def->inst_id = 0;
+
return 0;
}
return ret;
@@ -677,7 +682,11 @@ static int mtk_drm_of_get_ddp_ep_cid(struct device_node *node,
return ret;
/* All ok! Pass the Component ID to the caller. */
- comp_def->type = ret;
+ comp_def->type = comp_type;
+ comp_def->inst_id = ret;
+
+ dev_vdbg(dev, "Found component %pOF with Type:%u, HW Instance:%u\n",
+ ep_dev_node, comp_def->type, comp_def->inst_id);
return 0;
}
@@ -710,9 +719,9 @@ static int mtk_drm_of_ddp_path_build_one(struct device *dev, enum mtk_crtc_path
int ret;
/* Get the first entry for the temp_path array */
- ret = mtk_drm_of_get_ddp_ep_cid(vdo, 0, cpath, &next, &temp_path[idx]);
+ ret = mtk_drm_of_get_ddp_ep_cid(dev, vdo, 0, cpath, &next, &temp_path[idx]);
if (ret) {
- if (next && temp_path[idx].type == DDP_COMPONENT_DRM_OVL_ADAPTOR) {
+ if (next && temp_path[idx].type == MTK_DISP_OVL_ADAPTOR) {
dev_dbg(dev, "Adding OVL Adaptor for %pOF\n", next);
ovl_adaptor_comp_added = true;
} else {
@@ -732,9 +741,10 @@ static int mtk_drm_of_ddp_path_build_one(struct device *dev, enum mtk_crtc_path
*/
do {
prev = next;
- ret = mtk_drm_of_get_ddp_ep_cid(next, 1, cpath, &next, &temp_path[idx]);
+ ret = mtk_drm_of_get_ddp_ep_cid(dev, next, 1, cpath, &next, &temp_path[idx]);
of_node_put(prev);
if (ret) {
+ dev_vdbg(dev, "Invalid comp reached with result %d\n", ret);
of_node_put(next);
break;
}
@@ -746,13 +756,13 @@ static int mtk_drm_of_ddp_path_build_one(struct device *dev, enum mtk_crtc_path
* to probe that component master driver of which only one instance
* is needed and possible.
*/
- if (temp_path[idx].type == DDP_COMPONENT_DRM_OVL_ADAPTOR) {
+ if (temp_path[idx].type == MTK_DISP_OVL_ADAPTOR) {
if (!ovl_adaptor_comp_added)
ovl_adaptor_comp_added = true;
else
idx--;
}
- } while (++idx < DDP_COMPONENT_DRM_ID_MAX);
+ } while (++idx < MTK_DISP_CONTROLLER_MAX_COMP_PER_PATH);
/*
* The device component might not be enabled: in that case, don't
@@ -763,18 +773,13 @@ static int mtk_drm_of_ddp_path_build_one(struct device *dev, enum mtk_crtc_path
/* If the last entry is not a final display output, the configuration is wrong */
switch (temp_path[idx - 1].type) {
- case DDP_COMPONENT_DP_INTF0:
- case DDP_COMPONENT_DP_INTF1:
- case DDP_COMPONENT_DPI0:
- case DDP_COMPONENT_DPI1:
- case DDP_COMPONENT_DSI0:
- case DDP_COMPONENT_DSI1:
- case DDP_COMPONENT_DSI2:
- case DDP_COMPONENT_DSI3:
+ case MTK_DISP_DP_INTF:
+ case MTK_DISP_DPI:
+ case MTK_DISP_DSI:
break;
default:
- dev_err(dev, "Invalid display hw pipeline. Last component: %d (ret=%d)\n",
- temp_path[idx - 1].type, ret);
+ dev_err(dev, "Invalid display hw pipeline. Last component: %u-%u (ret=%d)\n",
+ temp_path[idx - 1].type, temp_path[idx - 1].inst_id, ret);
return -EINVAL;
}
@@ -852,7 +857,6 @@ static int mtk_drm_probe(struct platform_device *pdev)
struct device_node *node;
struct component_match *match = NULL;
int ret;
- int i;
private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL);
if (!private)
@@ -901,7 +905,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
/* Iterate over sibling DISP function blocks */
for_each_child_of_node(phandle->parent, node) {
enum mtk_ddp_comp_type comp_type;
- int comp_id;
+ u8 comp_inst_id;
ret = mtk_drm_of_get_ddp_comp_type(node, &comp_type);
if (ret)
@@ -924,18 +928,16 @@ static int mtk_drm_probe(struct platform_device *pdev)
continue;
}
- comp_id = mtk_ddp_comp_get_id(node, comp_type);
- if (comp_id < 0) {
+ comp_inst_id = mtk_ddp_comp_get_id(node, comp_type);
+ if (comp_inst_id < 0) {
dev_warn(dev, "Skipping unknown component %pOF\n",
node);
continue;
}
- if (!mtk_drm_find_mmsys_comp(private, comp_id))
+ if (!mtk_drm_find_mmsys_comp(private, comp_type, comp_inst_id))
continue;
- private->comp_node[comp_id] = of_node_get(node);
-
/*
* Currently only the AAL, CCORR, COLOR, GAMMA, MERGE, OVL, RDMA, DSI, and DPI
* blocks have separate component platform drivers and initialize their own
@@ -949,7 +951,8 @@ static int mtk_drm_probe(struct platform_device *pdev)
node);
}
- ret = mtk_ddp_comp_init(dev, node, &private->hlist, comp_id);
+ ret = mtk_ddp_comp_init(dev, node, &private->hlist,
+ comp_type, comp_inst_id);
if (ret) {
of_node_put(node);
goto err_node;
@@ -970,7 +973,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
}
/* Bringup ovl_adaptor */
- if (mtk_drm_find_mmsys_comp(private, DDP_COMPONENT_DRM_OVL_ADAPTOR))
+ if (mtk_drm_find_mmsys_comp(private, MTK_DISP_OVL_ADAPTOR, 0))
mtk_drm_legacy_ovl_adaptor_probe(dev, private, &match);
pm_runtime_enable(dev);
@@ -987,21 +990,16 @@ static int mtk_drm_probe(struct platform_device *pdev)
pm_runtime_disable(dev);
err_node:
of_node_put(private->mutex_node);
- for (i = 0; i < DDP_COMPONENT_DRM_ID_MAX; i++)
- of_node_put(private->comp_node[i]);
return ret;
}
static void mtk_drm_remove(struct platform_device *pdev)
{
struct mtk_drm_private *private = platform_get_drvdata(pdev);
- int i;
component_master_del(&pdev->dev, &mtk_drm_ops);
pm_runtime_disable(&pdev->dev);
of_node_put(private->mutex_node);
- for (i = 0; i < DDP_COMPONENT_DRM_ID_MAX; i++)
- of_node_put(private->comp_node[i]);
}
static void mtk_drm_shutdown(struct platform_device *pdev)
@@ -1085,4 +1083,6 @@ module_exit(mtk_drm_exit);
MODULE_AUTHOR("YT SHEN <yt.shen@mediatek.com>");
MODULE_DESCRIPTION("Mediatek SoC DRM driver");
+MODULE_IMPORT_NS("MTK_MMSYS");
+MODULE_IMPORT_NS("MTK_MUTEX");
MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 7dc208669c2e..d86175180e11 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -10,8 +10,6 @@
#include "mtk_ddp_comp.h"
#define MAX_CONNECTOR 2
-#define DDP_COMPONENT_DRM_OVL_ADAPTOR (DDP_COMPONENT_ID_MAX + 1)
-#define DDP_COMPONENT_DRM_ID_MAX (DDP_COMPONENT_DRM_OVL_ADAPTOR + 1)
enum mtk_crtc_path {
CRTC_MAIN,
@@ -30,11 +28,13 @@ struct regmap;
struct mtk_drm_route {
const unsigned int crtc_id;
- const unsigned int route_ddp;
+ const enum mtk_ddp_comp_type route_ddp_type;
+ const u8 route_ddp_inst_id;
};
struct mtk_drm_comp_definition {
- enum mtk_ddp_comp_id type;
+ enum mtk_ddp_comp_type type;
+ u8 inst_id;
};
struct mtk_drm_path_definition {
@@ -66,7 +66,6 @@ struct mtk_drm_private {
struct device *mutex_dev;
struct device *mmsys_dev;
struct mtk_drm_comp_list hlist;
- struct device_node *comp_node[DDP_COMPONENT_DRM_ID_MAX];
struct mtk_mmsys_driver_data *data;
struct drm_atomic_commit *suspend_state;
unsigned int mbox_index;
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_legacy.c b/drivers/gpu/drm/mediatek/mtk_drm_legacy.c
index d6e3ab7e08ba..801e0ab43ff5 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_legacy.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_legacy.c
@@ -248,16 +248,16 @@ struct mtk_drm_legacy_mtx_data {
};
static const struct mtk_drm_comp_definition mt2701_mtk_ddp_main[] = {
- { DDP_COMPONENT_OVL0 },
- { DDP_COMPONENT_RDMA0 },
- { DDP_COMPONENT_COLOR0 },
- { DDP_COMPONENT_BLS },
- { DDP_COMPONENT_DSI0 },
+ { MTK_DISP_OVL, 0 },
+ { MTK_DISP_RDMA, 0 },
+ { MTK_DISP_COLOR, 0 },
+ { MTK_DISP_BLS, 0 },
+ { MTK_DISP_DSI, 0 },
};
static const struct mtk_drm_comp_definition mt2701_mtk_ddp_ext[] = {
- { DDP_COMPONENT_RDMA1 },
- { DDP_COMPONENT_DPI0 },
+ { MTK_DISP_RDMA, 1 },
+ { MTK_DISP_DPI, 0 },
};
struct mtk_drm_path_definition mt2701_legacy_paths[MAX_CRTC] = {
@@ -272,29 +272,29 @@ struct mtk_drm_path_definition mt2701_legacy_paths[MAX_CRTC] = {
};
static const struct mtk_drm_comp_definition mt2712_mtk_ddp_main[] = {
- { DDP_COMPONENT_OVL0 },
- { DDP_COMPONENT_COLOR0 },
- { DDP_COMPONENT_AAL0 },
- { DDP_COMPONENT_OD0 },
- { DDP_COMPONENT_RDMA0 },
- { DDP_COMPONENT_DPI0 },
- { DDP_COMPONENT_PWM0 },
+ { MTK_DISP_OVL, 0 },
+ { MTK_DISP_COLOR, 0 },
+ { MTK_DISP_AAL, 0 },
+ { MTK_DISP_OD, 0 },
+ { MTK_DISP_RDMA, 0 },
+ { MTK_DISP_DPI, 0 },
+ { MTK_DISP_PWM, 0 },
};
static const struct mtk_drm_comp_definition mt2712_mtk_ddp_ext[] = {
- { DDP_COMPONENT_OVL1 },
- { DDP_COMPONENT_COLOR1 },
- { DDP_COMPONENT_AAL1 },
- { DDP_COMPONENT_OD1 },
- { DDP_COMPONENT_RDMA1 },
- { DDP_COMPONENT_DPI1 },
- { DDP_COMPONENT_PWM1 },
+ { MTK_DISP_OVL, 1 },
+ { MTK_DISP_COLOR, 1 },
+ { MTK_DISP_AAL, 1 },
+ { MTK_DISP_OD, 1 },
+ { MTK_DISP_RDMA, 1 },
+ { MTK_DISP_DPI, 1 },
+ { MTK_DISP_PWM, 1 },
};
static const struct mtk_drm_comp_definition mt2712_mtk_ddp_third[] = {
- { DDP_COMPONENT_RDMA2 },
- { DDP_COMPONENT_DSI3 },
- { DDP_COMPONENT_PWM2 },
+ { MTK_DISP_RDMA, 2 },
+ { MTK_DISP_DSI, 3 },
+ { MTK_DISP_PWM, 2 },
};
struct mtk_drm_path_definition mt2712_legacy_paths[MAX_CRTC] = {
@@ -313,16 +313,16 @@ struct mtk_drm_path_definition mt2712_legacy_paths[MAX_CRTC] = {
};
static const struct mtk_drm_comp_definition mt7623_mtk_ddp_main[] = {
- { DDP_COMPONENT_OVL0 },
- { DDP_COMPONENT_RDMA0 },
- { DDP_COMPONENT_COLOR0 },
- { DDP_COMPONENT_BLS },
- { DDP_COMPONENT_DPI0 },
+ { MTK_DISP_OVL, 0 },
+ { MTK_DISP_RDMA, 0 },
+ { MTK_DISP_COLOR, 0 },
+ { MTK_DISP_BLS, 0 },
+ { MTK_DISP_DPI, 0 },
};
static const struct mtk_drm_comp_definition mt7623_mtk_ddp_ext[] = {
- { DDP_COMPONENT_RDMA1 },
- { DDP_COMPONENT_DSI0 },
+ { MTK_DISP_RDMA, 1 },
+ { MTK_DISP_DSI, 0 },
};
struct mtk_drm_path_definition mt7623_legacy_paths[MAX_CRTC] = {
@@ -337,14 +337,14 @@ struct mtk_drm_path_definition mt7623_legacy_paths[MAX_CRTC] = {
};
static const struct mtk_drm_comp_definition mt8167_mtk_ddp_main[] = {
- { DDP_COMPONENT_OVL0 },
- { DDP_COMPONENT_COLOR0 },
- { DDP_COMPONENT_CCORR },
- { DDP_COMPONENT_AAL0 },
- { DDP_COMPONENT_GAMMA },
- { DDP_COMPONENT_DITHER0 },
- { DDP_COMPONENT_RDMA0 },
- { DDP_COMPONENT_DSI0 },
+ { MTK_DISP_OVL, 0 },
+ { MTK_DISP_COLOR, 0 },
+ { MTK_DISP_CCORR, 0 },
+ { MTK_DISP_AAL, 0 },
+ { MTK_DISP_GAMMA, 0 },
+ { MTK_DISP_DITHER, 0 },
+ { MTK_DISP_RDMA, 0 },
+ { MTK_DISP_DSI, 0 },
};
struct mtk_drm_path_definition mt8167_legacy_paths[MAX_CRTC] = {
@@ -355,22 +355,22 @@ struct mtk_drm_path_definition mt8167_legacy_paths[MAX_CRTC] = {
};
static const struct mtk_drm_comp_definition mt8173_mtk_ddp_main[] = {
- { DDP_COMPONENT_OVL0 },
- { DDP_COMPONENT_COLOR0 },
- { DDP_COMPONENT_AAL0 },
- { DDP_COMPONENT_OD0 },
- { DDP_COMPONENT_RDMA0 },
- { DDP_COMPONENT_UFOE },
- { DDP_COMPONENT_DSI0 },
- { DDP_COMPONENT_PWM0 },
+ { MTK_DISP_OVL, 0 },
+ { MTK_DISP_COLOR, 0 },
+ { MTK_DISP_AAL, 0 },
+ { MTK_DISP_OD, 0 },
+ { MTK_DISP_RDMA, 0 },
+ { MTK_DISP_UFOE, 0 },
+ { MTK_DISP_DSI, 0 },
+ { MTK_DISP_PWM, 0 },
};
static const struct mtk_drm_comp_definition mt8173_mtk_ddp_ext[] = {
- { DDP_COMPONENT_OVL1 },
- { DDP_COMPONENT_COLOR1 },
- { DDP_COMPONENT_GAMMA },
- { DDP_COMPONENT_RDMA1 },
- { DDP_COMPONENT_DPI0 },
+ { MTK_DISP_OVL, 1 },
+ { MTK_DISP_COLOR, 1 },
+ { MTK_DISP_GAMMA, 0 },
+ { MTK_DISP_RDMA, 1 },
+ { MTK_DISP_DPI, 0 },
};
struct mtk_drm_path_definition mt8173_legacy_paths[MAX_CRTC] = {
@@ -385,21 +385,21 @@ struct mtk_drm_path_definition mt8173_legacy_paths[MAX_CRTC] = {
};
static const struct mtk_drm_comp_definition mt8183_mtk_ddp_main[] = {
- { DDP_COMPONENT_OVL0 },
- { DDP_COMPONENT_OVL_2L0 },
- { DDP_COMPONENT_RDMA0 },
- { DDP_COMPONENT_COLOR0 },
- { DDP_COMPONENT_CCORR },
- { DDP_COMPONENT_AAL0 },
- { DDP_COMPONENT_GAMMA },
- { DDP_COMPONENT_DITHER0 },
- { DDP_COMPONENT_DSI0 },
+ { MTK_DISP_OVL, 0 },
+ { MTK_DISP_OVL_2L, 0 },
+ { MTK_DISP_RDMA, 0 },
+ { MTK_DISP_COLOR, 0 },
+ { MTK_DISP_CCORR, 0 },
+ { MTK_DISP_AAL, 0 },
+ { MTK_DISP_GAMMA, 0 },
+ { MTK_DISP_DITHER, 0 },
+ { MTK_DISP_DSI, 0 },
};
static const struct mtk_drm_comp_definition mt8183_mtk_ddp_ext[] = {
- { DDP_COMPONENT_OVL_2L1 },
- { DDP_COMPONENT_RDMA1 },
- { DDP_COMPONENT_DPI0 },
+ { MTK_DISP_OVL_2L, 1 },
+ { MTK_DISP_RDMA, 1 },
+ { MTK_DISP_DPI, 0 },
};
struct mtk_drm_path_definition mt8183_legacy_paths[MAX_CRTC] = {
@@ -414,21 +414,21 @@ struct mtk_drm_path_definition mt8183_legacy_paths[MAX_CRTC] = {
};
static const struct mtk_drm_comp_definition mt8186_mtk_ddp_main[] = {
- { DDP_COMPONENT_OVL0 },
- { DDP_COMPONENT_RDMA0 },
- { DDP_COMPONENT_COLOR0 },
- { DDP_COMPONENT_CCORR },
- { DDP_COMPONENT_AAL0 },
- { DDP_COMPONENT_GAMMA },
- { DDP_COMPONENT_POSTMASK0 },
- { DDP_COMPONENT_DITHER0 },
- { DDP_COMPONENT_DSI0 },
+ { MTK_DISP_OVL, 0 },
+ { MTK_DISP_RDMA, 0 },
+ { MTK_DISP_COLOR, 0 },
+ { MTK_DISP_CCORR, 0 },
+ { MTK_DISP_AAL, 0 },
+ { MTK_DISP_GAMMA, 0 },
+ { MTK_DISP_POSTMASK, 0 },
+ { MTK_DISP_DITHER, 0 },
+ { MTK_DISP_DSI, 0 },
};
static const struct mtk_drm_comp_definition mt8186_mtk_ddp_ext[] = {
- { DDP_COMPONENT_OVL_2L0 },
- { DDP_COMPONENT_RDMA1 },
- { DDP_COMPONENT_DPI0 },
+ { MTK_DISP_OVL_2L, 0 },
+ { MTK_DISP_RDMA, 1 },
+ { MTK_DISP_DPI, 0 },
};
struct mtk_drm_path_definition mt8186_legacy_paths[MAX_CRTC] = {
@@ -443,14 +443,14 @@ struct mtk_drm_path_definition mt8186_legacy_paths[MAX_CRTC] = {
};
static const struct mtk_drm_comp_definition mt8188_mtk_ddp_main[] = {
- { DDP_COMPONENT_OVL0 },
- { DDP_COMPONENT_RDMA0 },
- { DDP_COMPONENT_COLOR0 },
- { DDP_COMPONENT_CCORR },
- { DDP_COMPONENT_AAL0 },
- { DDP_COMPONENT_GAMMA },
- { DDP_COMPONENT_POSTMASK0 },
- { DDP_COMPONENT_DITHER0 },
+ { MTK_DISP_OVL, 0 },
+ { MTK_DISP_RDMA, 0 },
+ { MTK_DISP_COLOR, 0 },
+ { MTK_DISP_CCORR, 0 },
+ { MTK_DISP_AAL, 0 },
+ { MTK_DISP_GAMMA, 0 },
+ { MTK_DISP_POSTMASK, 0 },
+ { MTK_DISP_DITHER, 0 },
};
struct mtk_drm_path_definition mt8188_legacy_paths[MAX_CRTC] = {
@@ -461,22 +461,22 @@ struct mtk_drm_path_definition mt8188_legacy_paths[MAX_CRTC] = {
};
static const struct mtk_drm_comp_definition mt8192_mtk_ddp_main[] = {
- { DDP_COMPONENT_OVL0 },
- { DDP_COMPONENT_OVL_2L0 },
- { DDP_COMPONENT_RDMA0 },
- { DDP_COMPONENT_COLOR0 },
- { DDP_COMPONENT_CCORR },
- { DDP_COMPONENT_AAL0 },
- { DDP_COMPONENT_GAMMA },
- { DDP_COMPONENT_POSTMASK0 },
- { DDP_COMPONENT_DITHER0 },
- { DDP_COMPONENT_DSI0 },
+ { MTK_DISP_OVL, 0 },
+ { MTK_DISP_OVL_2L, 0 },
+ { MTK_DISP_RDMA, 0 },
+ { MTK_DISP_COLOR, 0 },
+ { MTK_DISP_CCORR, 0 },
+ { MTK_DISP_AAL, 0 },
+ { MTK_DISP_GAMMA, 0 },
+ { MTK_DISP_POSTMASK, 0 },
+ { MTK_DISP_DITHER, 0 },
+ { MTK_DISP_DSI, 0 },
};
static const struct mtk_drm_comp_definition mt8192_mtk_ddp_ext[] = {
- { DDP_COMPONENT_OVL_2L2 },
- { DDP_COMPONENT_RDMA4 },
- { DDP_COMPONENT_DPI0 },
+ { MTK_DISP_OVL_2L, 2 },
+ { MTK_DISP_RDMA, 4 },
+ { MTK_DISP_DPI, 0 },
};
struct mtk_drm_path_definition mt8192_legacy_paths[MAX_CRTC] = {
@@ -491,22 +491,22 @@ struct mtk_drm_path_definition mt8192_legacy_paths[MAX_CRTC] = {
};
static const struct mtk_drm_comp_definition mt8195_mtk_ddp_main[] = {
- { DDP_COMPONENT_OVL0 },
- { DDP_COMPONENT_RDMA0 },
- { DDP_COMPONENT_COLOR0 },
- { DDP_COMPONENT_CCORR },
- { DDP_COMPONENT_AAL0 },
- { DDP_COMPONENT_GAMMA },
- { DDP_COMPONENT_DITHER0 },
- { DDP_COMPONENT_DSC0 },
- { DDP_COMPONENT_MERGE0 },
- { DDP_COMPONENT_DP_INTF0 },
+ { MTK_DISP_OVL, 0 },
+ { MTK_DISP_RDMA, 0 },
+ { MTK_DISP_COLOR, 0 },
+ { MTK_DISP_CCORR, 0 },
+ { MTK_DISP_AAL, 0 },
+ { MTK_DISP_GAMMA, 0 },
+ { MTK_DISP_DITHER, 0 },
+ { MTK_DISP_DSC, 0 },
+ { MTK_DISP_MERGE, 0 },
+ { MTK_DISP_DP_INTF, 0 },
};
static const struct mtk_drm_comp_definition mt8195_mtk_ddp_ext[] = {
- { DDP_COMPONENT_DRM_OVL_ADAPTOR },
- { DDP_COMPONENT_MERGE5 },
- { DDP_COMPONENT_DP_INTF1 },
+ { MTK_DISP_OVL_ADAPTOR, 0 },
+ { MTK_DISP_MERGE, 5 },
+ { MTK_DISP_DP_INTF, 1 },
};
struct mtk_drm_path_definition mt8195_vdo0_legacy_paths[MAX_CRTC] = {
@@ -524,12 +524,12 @@ struct mtk_drm_path_definition mt8195_vdo1_legacy_paths[MAX_CRTC] = {
};
static const struct mtk_drm_legacy_mtx_pairs mt2701_legacy_mtx_trig_ids[] = {
- { { DDP_COMPONENT_BLS }, MT2701_MUTEX_MOD_DISP_BLS },
- { { DDP_COMPONENT_COLOR0 }, MT2701_MUTEX_MOD_DISP_COLOR },
- { { DDP_COMPONENT_OVL0 }, MT2701_MUTEX_MOD_DISP_OVL },
- { { DDP_COMPONENT_RDMA0 }, MT2701_MUTEX_MOD_DISP_RDMA0 },
- { { DDP_COMPONENT_RDMA1 }, MT2701_MUTEX_MOD_DISP_RDMA1 },
- { { DDP_COMPONENT_WDMA0 }, MT2701_MUTEX_MOD_DISP_WDMA },
+ { { MTK_DISP_BLS, 0 }, MT2701_MUTEX_MOD_DISP_BLS },
+ { { MTK_DISP_COLOR, 0 }, MT2701_MUTEX_MOD_DISP_COLOR },
+ { { MTK_DISP_OVL, 0 }, MT2701_MUTEX_MOD_DISP_OVL },
+ { { MTK_DISP_RDMA, 0 }, MT2701_MUTEX_MOD_DISP_RDMA0 },
+ { { MTK_DISP_RDMA, 1 }, MT2701_MUTEX_MOD_DISP_RDMA1 },
+ { { MTK_DISP_WDMA, 0 }, MT2701_MUTEX_MOD_DISP_WDMA },
};
const struct mtk_drm_legacy_mtx_data mt2701_legacy_mtx_data = {
@@ -538,23 +538,23 @@ const struct mtk_drm_legacy_mtx_data mt2701_legacy_mtx_data = {
};
static const struct mtk_drm_legacy_mtx_pairs mt2712_legacy_mtx_trig_ids[] = {
- { { DDP_COMPONENT_AAL0 }, MT2712_MUTEX_MOD_DISP_AAL0 },
- { { DDP_COMPONENT_AAL1 }, MT2712_MUTEX_MOD2_DISP_AAL1 },
- { { DDP_COMPONENT_COLOR0 }, MT2712_MUTEX_MOD_DISP_COLOR0 },
- { { DDP_COMPONENT_COLOR1 }, MT2712_MUTEX_MOD_DISP_COLOR1 },
- { { DDP_COMPONENT_OD0 }, MT2712_MUTEX_MOD_DISP_OD0 },
- { { DDP_COMPONENT_OD1 }, MT2712_MUTEX_MOD2_DISP_OD1 },
- { { DDP_COMPONENT_OVL0 }, MT2712_MUTEX_MOD_DISP_OVL0 },
- { { DDP_COMPONENT_OVL1 }, MT2712_MUTEX_MOD_DISP_OVL1 },
- { { DDP_COMPONENT_PWM0 }, MT2712_MUTEX_MOD_DISP_PWM0 },
- { { DDP_COMPONENT_PWM1 }, MT2712_MUTEX_MOD_DISP_PWM1 },
- { { DDP_COMPONENT_PWM2 }, MT2712_MUTEX_MOD_DISP_PWM2 },
- { { DDP_COMPONENT_RDMA0 }, MT2712_MUTEX_MOD_DISP_RDMA0 },
- { { DDP_COMPONENT_RDMA1 }, MT2712_MUTEX_MOD_DISP_RDMA1 },
- { { DDP_COMPONENT_RDMA2 }, MT2712_MUTEX_MOD_DISP_RDMA2 },
- { { DDP_COMPONENT_UFOE }, MT2712_MUTEX_MOD_DISP_UFOE },
- { { DDP_COMPONENT_WDMA0 }, MT2712_MUTEX_MOD_DISP_WDMA0 },
- { { DDP_COMPONENT_WDMA1 }, MT2712_MUTEX_MOD_DISP_WDMA1 },
+ { { MTK_DISP_AAL, 0 }, MT2712_MUTEX_MOD_DISP_AAL0 },
+ { { MTK_DISP_AAL, 1 }, MT2712_MUTEX_MOD2_DISP_AAL1 },
+ { { MTK_DISP_COLOR, 0 }, MT2712_MUTEX_MOD_DISP_COLOR0 },
+ { { MTK_DISP_COLOR, 1 }, MT2712_MUTEX_MOD_DISP_COLOR1 },
+ { { MTK_DISP_OD, 0 }, MT2712_MUTEX_MOD_DISP_OD0 },
+ { { MTK_DISP_OD, 1 }, MT2712_MUTEX_MOD2_DISP_OD1 },
+ { { MTK_DISP_OVL, 0 }, MT2712_MUTEX_MOD_DISP_OVL0 },
+ { { MTK_DISP_OVL, 1 }, MT2712_MUTEX_MOD_DISP_OVL1 },
+ { { MTK_DISP_PWM, 0 }, MT2712_MUTEX_MOD_DISP_PWM0 },
+ { { MTK_DISP_PWM, 1 }, MT2712_MUTEX_MOD_DISP_PWM1 },
+ { { MTK_DISP_PWM, 2 }, MT2712_MUTEX_MOD_DISP_PWM2 },
+ { { MTK_DISP_RDMA, 0 }, MT2712_MUTEX_MOD_DISP_RDMA0 },
+ { { MTK_DISP_RDMA, 1 }, MT2712_MUTEX_MOD_DISP_RDMA1 },
+ { { MTK_DISP_RDMA, 2 }, MT2712_MUTEX_MOD_DISP_RDMA2 },
+ { { MTK_DISP_UFOE, 0 }, MT2712_MUTEX_MOD_DISP_UFOE },
+ { { MTK_DISP_WDMA, 0 }, MT2712_MUTEX_MOD_DISP_WDMA0 },
+ { { MTK_DISP_WDMA, 1 }, MT2712_MUTEX_MOD_DISP_WDMA1 },
};
const struct mtk_drm_legacy_mtx_data mt2712_legacy_mtx_data = {
@@ -563,31 +563,31 @@ const struct mtk_drm_legacy_mtx_data mt2712_legacy_mtx_data = {
};
static const struct mtk_drm_legacy_mtx_pairs mt6893_legacy_mtx_trig_ids[] = {
- { { DDP_COMPONENT_AAL0 }, MT6893_MUTEX_MOD_DISP_AAL0 },
- { { DDP_COMPONENT_AAL1 }, MT6893_MUTEX_MOD_DISP_AAL1 },
- { { DDP_COMPONENT_CCORR }, MT6893_MUTEX_MOD_DISP_CCORR0 },
- { { DDP_COMPONENT_COLOR0 }, MT6893_MUTEX_MOD_DISP_COLOR0 },
- { { DDP_COMPONENT_COLOR1 }, MT6893_MUTEX_MOD_DISP_COLOR1 },
- { { DDP_COMPONENT_DITHER0 }, MT6893_MUTEX_MOD_DISP_DITHER0 },
- { { DDP_COMPONENT_DITHER1 }, MT6893_MUTEX_MOD_DISP_DITHER1 },
- { { DDP_COMPONENT_DP_INTF0 }, MT6893_MUTEX_MOD_DISP_DP },
- { { DDP_COMPONENT_DSC0 }, MT6893_MUTEX_MOD_DISP_DSC0 },
- { { DDP_COMPONENT_DSI0 }, MT6893_MUTEX_MOD_DISP_DSI0 },
- { { DDP_COMPONENT_DSI1 }, MT6893_MUTEX_MOD_DISP_DSI1 },
- { { DDP_COMPONENT_GAMMA }, MT6893_MUTEX_MOD_DISP_GAMMA0 },
- { { DDP_COMPONENT_MERGE1 }, MT6893_MUTEX_MOD_DISP_MERGE1 },
- { { DDP_COMPONENT_OVL0 }, MT6893_MUTEX_MOD_DISP_OVL0 },
- { { DDP_COMPONENT_OVL1 }, MT6893_MUTEX_MOD_DISP_OVL1 },
- { { DDP_COMPONENT_OVL_2L0 }, MT6893_MUTEX_MOD_DISP_OVL0_2L },
- { { DDP_COMPONENT_OVL_2L1 }, MT6893_MUTEX_MOD_DISP_OVL1_2L },
- { { DDP_COMPONENT_OVL_2L2 }, MT6893_MUTEX_MOD_DISP_OVL2 },
- { { DDP_COMPONENT_POSTMASK0 }, MT6893_MUTEX_MOD_DISP_POSTMASK0 },
- { { DDP_COMPONENT_PWM0 }, MT6893_MUTEX_MOD_DISP_PWM0 },
- { { DDP_COMPONENT_RDMA0 }, MT6893_MUTEX_MOD_DISP_RDMA0 },
- { { DDP_COMPONENT_RDMA1 }, MT6893_MUTEX_MOD_DISP_RDMA1 },
- { { DDP_COMPONENT_RDMA4 }, MT6893_MUTEX_MOD_DISP_RDMA4 },
- { { DDP_COMPONENT_WDMA0 }, MT6893_MUTEX_MOD_DISP_WDMA0 },
- { { DDP_COMPONENT_WDMA1 }, MT6893_MUTEX_MOD_DISP_WDMA1 },
+ { { MTK_DISP_AAL, 0 }, MT6893_MUTEX_MOD_DISP_AAL0 },
+ { { MTK_DISP_AAL, 1 }, MT6893_MUTEX_MOD_DISP_AAL1 },
+ { { MTK_DISP_CCORR, 0 }, MT6893_MUTEX_MOD_DISP_CCORR0 },
+ { { MTK_DISP_COLOR, 0 }, MT6893_MUTEX_MOD_DISP_COLOR0 },
+ { { MTK_DISP_COLOR, 1 }, MT6893_MUTEX_MOD_DISP_COLOR1 },
+ { { MTK_DISP_DITHER, 0 }, MT6893_MUTEX_MOD_DISP_DITHER0 },
+ { { MTK_DISP_DITHER, 1 }, MT6893_MUTEX_MOD_DISP_DITHER1 },
+ { { MTK_DISP_DP_INTF, 0 }, MT6893_MUTEX_MOD_DISP_DP },
+ { { MTK_DISP_DSC, 0 }, MT6893_MUTEX_MOD_DISP_DSC0 },
+ { { MTK_DISP_DSI, 0 }, MT6893_MUTEX_MOD_DISP_DSI0 },
+ { { MTK_DISP_DSI, 1 }, MT6893_MUTEX_MOD_DISP_DSI1 },
+ { { MTK_DISP_GAMMA, 0 }, MT6893_MUTEX_MOD_DISP_GAMMA0 },
+ { { MTK_DISP_MERGE, 1 }, MT6893_MUTEX_MOD_DISP_MERGE1 },
+ { { MTK_DISP_OVL, 0 }, MT6893_MUTEX_MOD_DISP_OVL0 },
+ { { MTK_DISP_OVL, 1 }, MT6893_MUTEX_MOD_DISP_OVL1 },
+ { { MTK_DISP_OVL_2L, 0 }, MT6893_MUTEX_MOD_DISP_OVL0_2L },
+ { { MTK_DISP_OVL_2L, 1 }, MT6893_MUTEX_MOD_DISP_OVL1_2L },
+ { { MTK_DISP_OVL_2L, 2 }, MT6893_MUTEX_MOD_DISP_OVL2 },
+ { { MTK_DISP_POSTMASK, 0 }, MT6893_MUTEX_MOD_DISP_POSTMASK0 },
+ { { MTK_DISP_PWM, 0 }, MT6893_MUTEX_MOD_DISP_PWM0 },
+ { { MTK_DISP_RDMA, 0 }, MT6893_MUTEX_MOD_DISP_RDMA0 },
+ { { MTK_DISP_RDMA, 1 }, MT6893_MUTEX_MOD_DISP_RDMA1 },
+ { { MTK_DISP_RDMA, 4 }, MT6893_MUTEX_MOD_DISP_RDMA4 },
+ { { MTK_DISP_WDMA, 0 }, MT6893_MUTEX_MOD_DISP_WDMA0 },
+ { { MTK_DISP_WDMA, 1 }, MT6893_MUTEX_MOD_DISP_WDMA1 },
};
const struct mtk_drm_legacy_mtx_data mt6893_legacy_mtx_data = {
@@ -596,18 +596,18 @@ const struct mtk_drm_legacy_mtx_data mt6893_legacy_mtx_data = {
};
static const struct mtk_drm_legacy_mtx_pairs mt8167_legacy_mtx_trig_ids[] = {
- { { DDP_COMPONENT_AAL0 }, MT8167_MUTEX_MOD_DISP_AAL },
- { { DDP_COMPONENT_CCORR }, MT8167_MUTEX_MOD_DISP_CCORR },
- { { DDP_COMPONENT_COLOR0 }, MT8167_MUTEX_MOD_DISP_COLOR },
- { { DDP_COMPONENT_DITHER0 }, MT8167_MUTEX_MOD_DISP_DITHER },
- { { DDP_COMPONENT_GAMMA }, MT8167_MUTEX_MOD_DISP_GAMMA },
- { { DDP_COMPONENT_OVL0 }, MT8167_MUTEX_MOD_DISP_OVL0 },
- { { DDP_COMPONENT_OVL1 }, MT8167_MUTEX_MOD_DISP_OVL1 },
- { { DDP_COMPONENT_PWM0 }, MT8167_MUTEX_MOD_DISP_PWM },
- { { DDP_COMPONENT_RDMA0 }, MT8167_MUTEX_MOD_DISP_RDMA0 },
- { { DDP_COMPONENT_RDMA1 }, MT8167_MUTEX_MOD_DISP_RDMA1 },
- { { DDP_COMPONENT_UFOE }, MT8167_MUTEX_MOD_DISP_UFOE },
- { { DDP_COMPONENT_WDMA0 }, MT8167_MUTEX_MOD_DISP_WDMA0 },
+ { { MTK_DISP_AAL, 0 }, MT8167_MUTEX_MOD_DISP_AAL },
+ { { MTK_DISP_CCORR, 0 }, MT8167_MUTEX_MOD_DISP_CCORR },
+ { { MTK_DISP_COLOR, 0 }, MT8167_MUTEX_MOD_DISP_COLOR },
+ { { MTK_DISP_DITHER, 0 }, MT8167_MUTEX_MOD_DISP_DITHER },
+ { { MTK_DISP_GAMMA, 0 }, MT8167_MUTEX_MOD_DISP_GAMMA },
+ { { MTK_DISP_OVL, 0 }, MT8167_MUTEX_MOD_DISP_OVL0 },
+ { { MTK_DISP_OVL, 1 }, MT8167_MUTEX_MOD_DISP_OVL1 },
+ { { MTK_DISP_PWM, 0 }, MT8167_MUTEX_MOD_DISP_PWM },
+ { { MTK_DISP_RDMA, 0 }, MT8167_MUTEX_MOD_DISP_RDMA0 },
+ { { MTK_DISP_RDMA, 1 }, MT8167_MUTEX_MOD_DISP_RDMA1 },
+ { { MTK_DISP_UFOE, 0 }, MT8167_MUTEX_MOD_DISP_UFOE },
+ { { MTK_DISP_WDMA, 0 }, MT8167_MUTEX_MOD_DISP_WDMA0 },
};
const struct mtk_drm_legacy_mtx_data mt8167_legacy_mtx_data = {
@@ -616,21 +616,21 @@ const struct mtk_drm_legacy_mtx_data mt8167_legacy_mtx_data = {
};
static const struct mtk_drm_legacy_mtx_pairs mt8173_legacy_mtx_trig_ids[] = {
- { { DDP_COMPONENT_AAL0 }, MT8173_MUTEX_MOD_DISP_AAL },
- { { DDP_COMPONENT_COLOR0 }, MT8173_MUTEX_MOD_DISP_COLOR0 },
- { { DDP_COMPONENT_COLOR1 }, MT8173_MUTEX_MOD_DISP_COLOR1 },
- { { DDP_COMPONENT_GAMMA }, MT8173_MUTEX_MOD_DISP_GAMMA },
- { { DDP_COMPONENT_OD0 }, MT8173_MUTEX_MOD_DISP_OD },
- { { DDP_COMPONENT_OVL0 }, MT8173_MUTEX_MOD_DISP_OVL0 },
- { { DDP_COMPONENT_OVL1 }, MT8173_MUTEX_MOD_DISP_OVL1 },
- { { DDP_COMPONENT_PWM0 }, MT8173_MUTEX_MOD_DISP_PWM0 },
- { { DDP_COMPONENT_PWM1 }, MT8173_MUTEX_MOD_DISP_PWM1 },
- { { DDP_COMPONENT_RDMA0 }, MT8173_MUTEX_MOD_DISP_RDMA0 },
- { { DDP_COMPONENT_RDMA1 }, MT8173_MUTEX_MOD_DISP_RDMA1 },
- { { DDP_COMPONENT_RDMA2 }, MT8173_MUTEX_MOD_DISP_RDMA2 },
- { { DDP_COMPONENT_UFOE }, MT8173_MUTEX_MOD_DISP_UFOE },
- { { DDP_COMPONENT_WDMA0 }, MT8173_MUTEX_MOD_DISP_WDMA0 },
- { { DDP_COMPONENT_WDMA1 }, MT8173_MUTEX_MOD_DISP_WDMA1 },
+ { { MTK_DISP_AAL, 0 }, MT8173_MUTEX_MOD_DISP_AAL },
+ { { MTK_DISP_COLOR, 0 }, MT8173_MUTEX_MOD_DISP_COLOR0 },
+ { { MTK_DISP_COLOR, 1 }, MT8173_MUTEX_MOD_DISP_COLOR1 },
+ { { MTK_DISP_GAMMA, 0 }, MT8173_MUTEX_MOD_DISP_GAMMA },
+ { { MTK_DISP_OD, 0 }, MT8173_MUTEX_MOD_DISP_OD },
+ { { MTK_DISP_OVL, 0 }, MT8173_MUTEX_MOD_DISP_OVL0 },
+ { { MTK_DISP_OVL, 1 }, MT8173_MUTEX_MOD_DISP_OVL1 },
+ { { MTK_DISP_PWM, 0 }, MT8173_MUTEX_MOD_DISP_PWM0 },
+ { { MTK_DISP_PWM, 1 }, MT8173_MUTEX_MOD_DISP_PWM1 },
+ { { MTK_DISP_RDMA, 0 }, MT8173_MUTEX_MOD_DISP_RDMA0 },
+ { { MTK_DISP_RDMA, 1 }, MT8173_MUTEX_MOD_DISP_RDMA1 },
+ { { MTK_DISP_RDMA, 2 }, MT8173_MUTEX_MOD_DISP_RDMA2 },
+ { { MTK_DISP_UFOE, 0 }, MT8173_MUTEX_MOD_DISP_UFOE },
+ { { MTK_DISP_WDMA, 0 }, MT8173_MUTEX_MOD_DISP_WDMA0 },
+ { { MTK_DISP_WDMA, 1 }, MT8173_MUTEX_MOD_DISP_WDMA1 },
};
const struct mtk_drm_legacy_mtx_data mt8173_legacy_mtx_data = {
@@ -639,17 +639,17 @@ const struct mtk_drm_legacy_mtx_data mt8173_legacy_mtx_data = {
};
static const struct mtk_drm_legacy_mtx_pairs mt8183_legacy_mtx_trig_ids[] = {
- { { DDP_COMPONENT_AAL0 }, MT8183_MUTEX_MOD_DISP_AAL0 },
- { { DDP_COMPONENT_CCORR }, MT8183_MUTEX_MOD_DISP_CCORR0 },
- { { DDP_COMPONENT_COLOR0 }, MT8183_MUTEX_MOD_DISP_COLOR0 },
- { { DDP_COMPONENT_DITHER0 }, MT8183_MUTEX_MOD_DISP_DITHER0 },
- { { DDP_COMPONENT_GAMMA }, MT8183_MUTEX_MOD_DISP_GAMMA0 },
- { { DDP_COMPONENT_OVL0 }, MT8183_MUTEX_MOD_DISP_OVL0 },
- { { DDP_COMPONENT_OVL_2L0 }, MT8183_MUTEX_MOD_DISP_OVL0_2L },
- { { DDP_COMPONENT_OVL_2L1 }, MT8183_MUTEX_MOD_DISP_OVL1_2L },
- { { DDP_COMPONENT_RDMA0 }, MT8183_MUTEX_MOD_DISP_RDMA0 },
- { { DDP_COMPONENT_RDMA1 }, MT8183_MUTEX_MOD_DISP_RDMA1 },
- { { DDP_COMPONENT_WDMA0 }, MT8183_MUTEX_MOD_DISP_WDMA0 },
+ { { MTK_DISP_AAL, 0 }, MT8183_MUTEX_MOD_DISP_AAL0 },
+ { { MTK_DISP_CCORR, 0 }, MT8183_MUTEX_MOD_DISP_CCORR0 },
+ { { MTK_DISP_COLOR, 0 }, MT8183_MUTEX_MOD_DISP_COLOR0 },
+ { { MTK_DISP_DITHER, 0 }, MT8183_MUTEX_MOD_DISP_DITHER0 },
+ { { MTK_DISP_GAMMA, 0 }, MT8183_MUTEX_MOD_DISP_GAMMA0 },
+ { { MTK_DISP_OVL, 0 }, MT8183_MUTEX_MOD_DISP_OVL0 },
+ { { MTK_DISP_OVL_2L, 0 }, MT8183_MUTEX_MOD_DISP_OVL0_2L },
+ { { MTK_DISP_OVL_2L, 1 }, MT8183_MUTEX_MOD_DISP_OVL1_2L },
+ { { MTK_DISP_RDMA, 0 }, MT8183_MUTEX_MOD_DISP_RDMA0 },
+ { { MTK_DISP_RDMA, 1 }, MT8183_MUTEX_MOD_DISP_RDMA1 },
+ { { MTK_DISP_WDMA, 0 }, MT8183_MUTEX_MOD_DISP_WDMA0 },
};
const struct mtk_drm_legacy_mtx_data mt8183_legacy_mtx_data = {
@@ -658,16 +658,16 @@ const struct mtk_drm_legacy_mtx_data mt8183_legacy_mtx_data = {
};
static const struct mtk_drm_legacy_mtx_pairs mt8186_legacy_mtx_trig_ids[] = {
- { { DDP_COMPONENT_AAL0 }, MT8186_MUTEX_MOD_DISP_AAL0 },
- { { DDP_COMPONENT_CCORR }, MT8186_MUTEX_MOD_DISP_CCORR0 },
- { { DDP_COMPONENT_COLOR0 }, MT8186_MUTEX_MOD_DISP_COLOR0 },
- { { DDP_COMPONENT_DITHER0 }, MT8186_MUTEX_MOD_DISP_DITHER0 },
- { { DDP_COMPONENT_GAMMA }, MT8186_MUTEX_MOD_DISP_GAMMA0 },
- { { DDP_COMPONENT_OVL0 }, MT8186_MUTEX_MOD_DISP_OVL0 },
- { { DDP_COMPONENT_OVL_2L0 }, MT8186_MUTEX_MOD_DISP_OVL0_2L },
- { { DDP_COMPONENT_POSTMASK0 }, MT8186_MUTEX_MOD_DISP_POSTMASK0 },
- { { DDP_COMPONENT_RDMA0 }, MT8186_MUTEX_MOD_DISP_RDMA0 },
- { { DDP_COMPONENT_RDMA1 }, MT8186_MUTEX_MOD_DISP_RDMA1 },
+ { { MTK_DISP_AAL, 0 }, MT8186_MUTEX_MOD_DISP_AAL0 },
+ { { MTK_DISP_CCORR, 0 }, MT8186_MUTEX_MOD_DISP_CCORR0 },
+ { { MTK_DISP_COLOR, 0 }, MT8186_MUTEX_MOD_DISP_COLOR0 },
+ { { MTK_DISP_DITHER, 0 }, MT8186_MUTEX_MOD_DISP_DITHER0 },
+ { { MTK_DISP_GAMMA, 0 }, MT8186_MUTEX_MOD_DISP_GAMMA0 },
+ { { MTK_DISP_OVL, 0 }, MT8186_MUTEX_MOD_DISP_OVL0 },
+ { { MTK_DISP_OVL_2L, 0 }, MT8186_MUTEX_MOD_DISP_OVL0_2L },
+ { { MTK_DISP_POSTMASK, 0 }, MT8186_MUTEX_MOD_DISP_POSTMASK0 },
+ { { MTK_DISP_RDMA, 0 }, MT8186_MUTEX_MOD_DISP_RDMA0 },
+ { { MTK_DISP_RDMA, 1 }, MT8186_MUTEX_MOD_DISP_RDMA1 },
};
const struct mtk_drm_legacy_mtx_data mt8186_legacy_mtx_data = {
@@ -676,44 +676,44 @@ const struct mtk_drm_legacy_mtx_data mt8186_legacy_mtx_data = {
};
static const struct mtk_drm_legacy_mtx_pairs mt8188_legacy_mtx_trig_ids[] = {
- { { DDP_COMPONENT_OVL0 }, MT8188_MUTEX_MOD_DISP_OVL0 },
- { { DDP_COMPONENT_WDMA0 }, MT8188_MUTEX_MOD_DISP_WDMA0 },
- { { DDP_COMPONENT_RDMA0 }, MT8188_MUTEX_MOD_DISP_RDMA0 },
- { { DDP_COMPONENT_COLOR0 }, MT8188_MUTEX_MOD_DISP_COLOR0 },
- { { DDP_COMPONENT_CCORR }, MT8188_MUTEX_MOD_DISP_CCORR0 },
- { { DDP_COMPONENT_AAL0 }, MT8188_MUTEX_MOD_DISP_AAL0 },
- { { DDP_COMPONENT_GAMMA }, MT8188_MUTEX_MOD_DISP_GAMMA0 },
- { { DDP_COMPONENT_POSTMASK0 }, MT8188_MUTEX_MOD_DISP_POSTMASK0 },
- { { DDP_COMPONENT_DITHER0 }, MT8188_MUTEX_MOD_DISP_DITHER0 },
- { { DDP_COMPONENT_MERGE0 }, MT8188_MUTEX_MOD_DISP_VPP_MERGE },
- { { DDP_COMPONENT_DSC0 }, MT8188_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 },
- { { DDP_COMPONENT_DSI0 }, MT8188_MUTEX_MOD_DISP_DSI0 },
- { { DDP_COMPONENT_PWM0 }, MT8188_MUTEX_MOD2_DISP_PWM0 },
- { { DDP_COMPONENT_DP_INTF0 }, MT8188_MUTEX_MOD_DISP_DP_INTF0 },
- { { DDP_COMPONENT_DP_INTF1 }, MT8188_MUTEX_MOD_DISP1_DP_INTF1 },
- { { DDP_COMPONENT_DPI1 }, MT8188_MUTEX_MOD_DISP1_DPI1 },
- { { DDP_COMPONENT_ETHDR_MIXER }, MT8188_MUTEX_MOD_DISP1_DISP_MIXER },
- { { DDP_COMPONENT_MDP_RDMA0 }, MT8188_MUTEX_MOD_DISP1_MDP_RDMA0 },
- { { DDP_COMPONENT_MDP_RDMA1 }, MT8188_MUTEX_MOD_DISP1_MDP_RDMA1 },
- { { DDP_COMPONENT_MDP_RDMA2 }, MT8188_MUTEX_MOD_DISP1_MDP_RDMA2 },
- { { DDP_COMPONENT_MDP_RDMA3 }, MT8188_MUTEX_MOD_DISP1_MDP_RDMA3 },
- { { DDP_COMPONENT_MDP_RDMA4 }, MT8188_MUTEX_MOD_DISP1_MDP_RDMA4 },
- { { DDP_COMPONENT_MDP_RDMA5 }, MT8188_MUTEX_MOD_DISP1_MDP_RDMA5 },
- { { DDP_COMPONENT_MDP_RDMA6 }, MT8188_MUTEX_MOD_DISP1_MDP_RDMA6 },
- { { DDP_COMPONENT_MDP_RDMA7 }, MT8188_MUTEX_MOD_DISP1_MDP_RDMA7 },
- { { DDP_COMPONENT_PADDING0 }, MT8188_MUTEX_MOD_DISP1_PADDING0 },
- { { DDP_COMPONENT_PADDING1 }, MT8188_MUTEX_MOD_DISP1_PADDING1 },
- { { DDP_COMPONENT_PADDING2 }, MT8188_MUTEX_MOD_DISP1_PADDING2 },
- { { DDP_COMPONENT_PADDING3 }, MT8188_MUTEX_MOD_DISP1_PADDING3 },
- { { DDP_COMPONENT_PADDING4 }, MT8188_MUTEX_MOD_DISP1_PADDING4 },
- { { DDP_COMPONENT_PADDING5 }, MT8188_MUTEX_MOD_DISP1_PADDING5 },
- { { DDP_COMPONENT_PADDING6 }, MT8188_MUTEX_MOD_DISP1_PADDING6 },
- { { DDP_COMPONENT_PADDING7 }, MT8188_MUTEX_MOD_DISP1_PADDING7 },
- { { DDP_COMPONENT_MERGE1 }, MT8188_MUTEX_MOD_DISP1_VPP_MERGE0 },
- { { DDP_COMPONENT_MERGE2 }, MT8188_MUTEX_MOD_DISP1_VPP_MERGE1 },
- { { DDP_COMPONENT_MERGE3 }, MT8188_MUTEX_MOD_DISP1_VPP_MERGE2 },
- { { DDP_COMPONENT_MERGE4 }, MT8188_MUTEX_MOD_DISP1_VPP_MERGE3 },
- { { DDP_COMPONENT_MERGE5 }, MT8188_MUTEX_MOD_DISP1_VPP_MERGE4 },
+ { { MTK_DISP_OVL, 0 }, MT8188_MUTEX_MOD_DISP_OVL0 },
+ { { MTK_DISP_WDMA, 0 }, MT8188_MUTEX_MOD_DISP_WDMA0 },
+ { { MTK_DISP_RDMA, 0 }, MT8188_MUTEX_MOD_DISP_RDMA0 },
+ { { MTK_DISP_COLOR, 0 }, MT8188_MUTEX_MOD_DISP_COLOR0 },
+ { { MTK_DISP_CCORR, 0 }, MT8188_MUTEX_MOD_DISP_CCORR0 },
+ { { MTK_DISP_AAL, 0 }, MT8188_MUTEX_MOD_DISP_AAL0 },
+ { { MTK_DISP_GAMMA, 0 }, MT8188_MUTEX_MOD_DISP_GAMMA0 },
+ { { MTK_DISP_POSTMASK, 0 }, MT8188_MUTEX_MOD_DISP_POSTMASK0 },
+ { { MTK_DISP_DITHER, 0 }, MT8188_MUTEX_MOD_DISP_DITHER0 },
+ { { MTK_DISP_MERGE, 0 }, MT8188_MUTEX_MOD_DISP_VPP_MERGE },
+ { { MTK_DISP_DSC, 0 }, MT8188_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 },
+ { { MTK_DISP_DSI, 0 }, MT8188_MUTEX_MOD_DISP_DSI0 },
+ { { MTK_DISP_PWM, 0 }, MT8188_MUTEX_MOD2_DISP_PWM0 },
+ { { MTK_DISP_DP_INTF, 0 }, MT8188_MUTEX_MOD_DISP_DP_INTF0 },
+ { { MTK_DISP_DP_INTF, 1 }, MT8188_MUTEX_MOD_DISP1_DP_INTF1 },
+ { { MTK_DISP_DPI, 1 }, MT8188_MUTEX_MOD_DISP1_DPI1 },
+ { { MTK_DISP_ETHDR_MIXER, 0 }, MT8188_MUTEX_MOD_DISP1_DISP_MIXER },
+ { { MTK_DISP_MDP_RDMA, 0 }, MT8188_MUTEX_MOD_DISP1_MDP_RDMA0 },
+ { { MTK_DISP_MDP_RDMA, 1 }, MT8188_MUTEX_MOD_DISP1_MDP_RDMA1 },
+ { { MTK_DISP_MDP_RDMA, 2 }, MT8188_MUTEX_MOD_DISP1_MDP_RDMA2 },
+ { { MTK_DISP_MDP_RDMA, 3 }, MT8188_MUTEX_MOD_DISP1_MDP_RDMA3 },
+ { { MTK_DISP_MDP_RDMA, 4 }, MT8188_MUTEX_MOD_DISP1_MDP_RDMA4 },
+ { { MTK_DISP_MDP_RDMA, 5 }, MT8188_MUTEX_MOD_DISP1_MDP_RDMA5 },
+ { { MTK_DISP_MDP_RDMA, 6 }, MT8188_MUTEX_MOD_DISP1_MDP_RDMA6 },
+ { { MTK_DISP_MDP_RDMA, 7 }, MT8188_MUTEX_MOD_DISP1_MDP_RDMA7 },
+ { { MTK_DISP_PADDING, 0 }, MT8188_MUTEX_MOD_DISP1_PADDING0 },
+ { { MTK_DISP_PADDING, 1 }, MT8188_MUTEX_MOD_DISP1_PADDING1 },
+ { { MTK_DISP_PADDING, 2 }, MT8188_MUTEX_MOD_DISP1_PADDING2 },
+ { { MTK_DISP_PADDING, 3 }, MT8188_MUTEX_MOD_DISP1_PADDING3 },
+ { { MTK_DISP_PADDING, 4 }, MT8188_MUTEX_MOD_DISP1_PADDING4 },
+ { { MTK_DISP_PADDING, 5 }, MT8188_MUTEX_MOD_DISP1_PADDING5 },
+ { { MTK_DISP_PADDING, 6 }, MT8188_MUTEX_MOD_DISP1_PADDING6 },
+ { { MTK_DISP_PADDING, 7 }, MT8188_MUTEX_MOD_DISP1_PADDING7 },
+ { { MTK_DISP_MERGE, 1 }, MT8188_MUTEX_MOD_DISP1_VPP_MERGE0 },
+ { { MTK_DISP_MERGE, 2 }, MT8188_MUTEX_MOD_DISP1_VPP_MERGE1 },
+ { { MTK_DISP_MERGE, 3 }, MT8188_MUTEX_MOD_DISP1_VPP_MERGE2 },
+ { { MTK_DISP_MERGE, 4 }, MT8188_MUTEX_MOD_DISP1_VPP_MERGE3 },
+ { { MTK_DISP_MERGE, 5 }, MT8188_MUTEX_MOD_DISP1_VPP_MERGE4 },
};
const struct mtk_drm_legacy_mtx_data mt8188_legacy_mtx_data = {
@@ -722,17 +722,17 @@ const struct mtk_drm_legacy_mtx_data mt8188_legacy_mtx_data = {
};
static const struct mtk_drm_legacy_mtx_pairs mt8192_legacy_mtx_trig_ids[] = {
- { { DDP_COMPONENT_AAL0 }, MT8192_MUTEX_MOD_DISP_AAL0 },
- { { DDP_COMPONENT_CCORR }, MT8192_MUTEX_MOD_DISP_CCORR0 },
- { { DDP_COMPONENT_COLOR0 }, MT8192_MUTEX_MOD_DISP_COLOR0 },
- { { DDP_COMPONENT_DITHER0 }, MT8192_MUTEX_MOD_DISP_DITHER0 },
- { { DDP_COMPONENT_GAMMA }, MT8192_MUTEX_MOD_DISP_GAMMA0 },
- { { DDP_COMPONENT_POSTMASK0 }, MT8192_MUTEX_MOD_DISP_POSTMASK0 },
- { { DDP_COMPONENT_OVL0 }, MT8192_MUTEX_MOD_DISP_OVL0 },
- { { DDP_COMPONENT_OVL_2L0 }, MT8192_MUTEX_MOD_DISP_OVL0_2L },
- { { DDP_COMPONENT_OVL_2L2 }, MT8192_MUTEX_MOD_DISP_OVL2_2L },
- { { DDP_COMPONENT_RDMA0 }, MT8192_MUTEX_MOD_DISP_RDMA0 },
- { { DDP_COMPONENT_RDMA4 }, MT8192_MUTEX_MOD_DISP_RDMA4 },
+ { { MTK_DISP_AAL, 0 }, MT8192_MUTEX_MOD_DISP_AAL0 },
+ { { MTK_DISP_CCORR, 0 }, MT8192_MUTEX_MOD_DISP_CCORR0 },
+ { { MTK_DISP_COLOR, 0 }, MT8192_MUTEX_MOD_DISP_COLOR0 },
+ { { MTK_DISP_DITHER, 0 }, MT8192_MUTEX_MOD_DISP_DITHER0 },
+ { { MTK_DISP_GAMMA, 0 }, MT8192_MUTEX_MOD_DISP_GAMMA0 },
+ { { MTK_DISP_POSTMASK, 0 }, MT8192_MUTEX_MOD_DISP_POSTMASK0 },
+ { { MTK_DISP_OVL, 0 }, MT8192_MUTEX_MOD_DISP_OVL0 },
+ { { MTK_DISP_OVL_2L, 0 }, MT8192_MUTEX_MOD_DISP_OVL0_2L },
+ { { MTK_DISP_OVL_2L, 2 }, MT8192_MUTEX_MOD_DISP_OVL2_2L },
+ { { MTK_DISP_RDMA, 0 }, MT8192_MUTEX_MOD_DISP_RDMA0 },
+ { { MTK_DISP_RDMA, 4 }, MT8192_MUTEX_MOD_DISP_RDMA4 },
};
const struct mtk_drm_legacy_mtx_data mt8192_legacy_mtx_data = {
@@ -741,34 +741,34 @@ const struct mtk_drm_legacy_mtx_data mt8192_legacy_mtx_data = {
};
static const struct mtk_drm_legacy_mtx_pairs mt8195_legacy_mtx_trig_ids[] = {
- { { DDP_COMPONENT_OVL0 }, MT8195_MUTEX_MOD_DISP_OVL0 },
- { { DDP_COMPONENT_WDMA0 }, MT8195_MUTEX_MOD_DISP_WDMA0 },
- { { DDP_COMPONENT_RDMA0 }, MT8195_MUTEX_MOD_DISP_RDMA0 },
- { { DDP_COMPONENT_COLOR0 }, MT8195_MUTEX_MOD_DISP_COLOR0 },
- { { DDP_COMPONENT_CCORR }, MT8195_MUTEX_MOD_DISP_CCORR0 },
- { { DDP_COMPONENT_AAL0 }, MT8195_MUTEX_MOD_DISP_AAL0 },
- { { DDP_COMPONENT_GAMMA }, MT8195_MUTEX_MOD_DISP_GAMMA0 },
- { { DDP_COMPONENT_DITHER0 }, MT8195_MUTEX_MOD_DISP_DITHER0 },
- { { DDP_COMPONENT_MERGE0 }, MT8195_MUTEX_MOD_DISP_VPP_MERGE },
- { { DDP_COMPONENT_DSC0 }, MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 },
- { { DDP_COMPONENT_DSI0 }, MT8195_MUTEX_MOD_DISP_DSI0 },
- { { DDP_COMPONENT_PWM0 }, MT8195_MUTEX_MOD_DISP_PWM0 },
- { { DDP_COMPONENT_DP_INTF0 }, MT8195_MUTEX_MOD_DISP_DP_INTF0 },
- { { DDP_COMPONENT_MDP_RDMA0 }, MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 },
- { { DDP_COMPONENT_MDP_RDMA1 }, MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 },
- { { DDP_COMPONENT_MDP_RDMA2 }, MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 },
- { { DDP_COMPONENT_MDP_RDMA3 }, MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 },
- { { DDP_COMPONENT_MDP_RDMA4 }, MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 },
- { { DDP_COMPONENT_MDP_RDMA5 }, MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 },
- { { DDP_COMPONENT_MDP_RDMA6 }, MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 },
- { { DDP_COMPONENT_MDP_RDMA7 }, MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 },
- { { DDP_COMPONENT_MERGE1 }, MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 },
- { { DDP_COMPONENT_MERGE2 }, MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 },
- { { DDP_COMPONENT_MERGE3 }, MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 },
- { { DDP_COMPONENT_MERGE4 }, MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 },
- { { DDP_COMPONENT_ETHDR_MIXER }, MT8195_MUTEX_MOD_DISP1_DISP_MIXER },
- { { DDP_COMPONENT_MERGE5 }, MT8195_MUTEX_MOD_DISP1_VPP_MERGE4 },
- { { DDP_COMPONENT_DP_INTF1 }, MT8195_MUTEX_MOD_DISP1_DP_INTF0 },
+ { { MTK_DISP_OVL, 0 }, MT8195_MUTEX_MOD_DISP_OVL0 },
+ { { MTK_DISP_WDMA, 0 }, MT8195_MUTEX_MOD_DISP_WDMA0 },
+ { { MTK_DISP_RDMA, 0 }, MT8195_MUTEX_MOD_DISP_RDMA0 },
+ { { MTK_DISP_COLOR, 0 }, MT8195_MUTEX_MOD_DISP_COLOR0 },
+ { { MTK_DISP_CCORR, 0 }, MT8195_MUTEX_MOD_DISP_CCORR0 },
+ { { MTK_DISP_AAL, 0 }, MT8195_MUTEX_MOD_DISP_AAL0 },
+ { { MTK_DISP_GAMMA, 0 }, MT8195_MUTEX_MOD_DISP_GAMMA0 },
+ { { MTK_DISP_DITHER, 0 }, MT8195_MUTEX_MOD_DISP_DITHER0 },
+ { { MTK_DISP_MERGE, 0 }, MT8195_MUTEX_MOD_DISP_VPP_MERGE },
+ { { MTK_DISP_DSC, 0 }, MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 },
+ { { MTK_DISP_DSI, 0 }, MT8195_MUTEX_MOD_DISP_DSI0 },
+ { { MTK_DISP_PWM, 0 }, MT8195_MUTEX_MOD_DISP_PWM0 },
+ { { MTK_DISP_DP_INTF, 0 }, MT8195_MUTEX_MOD_DISP_DP_INTF0 },
+ { { MTK_DISP_MDP_RDMA, 0 }, MT8195_MUTEX_MOD_DISP1_MDP_RDMA0 },
+ { { MTK_DISP_MDP_RDMA, 1 }, MT8195_MUTEX_MOD_DISP1_MDP_RDMA1 },
+ { { MTK_DISP_MDP_RDMA, 2 }, MT8195_MUTEX_MOD_DISP1_MDP_RDMA2 },
+ { { MTK_DISP_MDP_RDMA, 3 }, MT8195_MUTEX_MOD_DISP1_MDP_RDMA3 },
+ { { MTK_DISP_MDP_RDMA, 4 }, MT8195_MUTEX_MOD_DISP1_MDP_RDMA4 },
+ { { MTK_DISP_MDP_RDMA, 5 }, MT8195_MUTEX_MOD_DISP1_MDP_RDMA5 },
+ { { MTK_DISP_MDP_RDMA, 6 }, MT8195_MUTEX_MOD_DISP1_MDP_RDMA6 },
+ { { MTK_DISP_MDP_RDMA, 7 }, MT8195_MUTEX_MOD_DISP1_MDP_RDMA7 },
+ { { MTK_DISP_MERGE, 1 }, MT8195_MUTEX_MOD_DISP1_VPP_MERGE0 },
+ { { MTK_DISP_MERGE, 2 }, MT8195_MUTEX_MOD_DISP1_VPP_MERGE1 },
+ { { MTK_DISP_MERGE, 3 }, MT8195_MUTEX_MOD_DISP1_VPP_MERGE2 },
+ { { MTK_DISP_MERGE, 4 }, MT8195_MUTEX_MOD_DISP1_VPP_MERGE3 },
+ { { MTK_DISP_ETHDR_MIXER, 0 }, MT8195_MUTEX_MOD_DISP1_DISP_MIXER },
+ { { MTK_DISP_MERGE, 5 }, MT8195_MUTEX_MOD_DISP1_VPP_MERGE4 },
+ { { MTK_DISP_DP_INTF, 1 }, MT8195_MUTEX_MOD_DISP1_DP_INTF0 },
};
const struct mtk_drm_legacy_mtx_data mt8195_legacy_mtx_data = {
@@ -777,19 +777,19 @@ const struct mtk_drm_legacy_mtx_data mt8195_legacy_mtx_data = {
};
static const struct mtk_drm_legacy_mtx_pairs mt8365_legacy_mtx_trig_ids[] = {
- { { DDP_COMPONENT_AAL0 }, MT8365_MUTEX_MOD_DISP_AAL },
- { { DDP_COMPONENT_CCORR }, MT8365_MUTEX_MOD_DISP_CCORR },
- { { DDP_COMPONENT_COLOR0 }, MT8365_MUTEX_MOD_DISP_COLOR0 },
- { { DDP_COMPONENT_DITHER0 }, MT8365_MUTEX_MOD_DISP_DITHER },
- { { DDP_COMPONENT_DPI0 }, MT8365_MUTEX_MOD_DISP_DPI0 },
- { { DDP_COMPONENT_DSI0 }, MT8365_MUTEX_MOD_DISP_DSI0 },
- { { DDP_COMPONENT_GAMMA }, MT8365_MUTEX_MOD_DISP_GAMMA },
- { { DDP_COMPONENT_OVL0 }, MT8365_MUTEX_MOD_DISP_OVL0 },
- { { DDP_COMPONENT_OVL_2L0 }, MT8365_MUTEX_MOD_DISP_OVL0_2L },
- { { DDP_COMPONENT_PWM0 }, MT8365_MUTEX_MOD_DISP_PWM0 },
- { { DDP_COMPONENT_RDMA0 }, MT8365_MUTEX_MOD_DISP_RDMA0 },
- { { DDP_COMPONENT_RDMA1 }, MT8365_MUTEX_MOD_DISP_RDMA1 },
- { { DDP_COMPONENT_WDMA0 }, MT8365_MUTEX_MOD_DISP_WDMA0 },
+ { { MTK_DISP_AAL, 0 }, MT8365_MUTEX_MOD_DISP_AAL },
+ { { MTK_DISP_CCORR, 0 }, MT8365_MUTEX_MOD_DISP_CCORR },
+ { { MTK_DISP_COLOR, 0 }, MT8365_MUTEX_MOD_DISP_COLOR0 },
+ { { MTK_DISP_DITHER, 0 }, MT8365_MUTEX_MOD_DISP_DITHER },
+ { { MTK_DISP_DPI, 0 }, MT8365_MUTEX_MOD_DISP_DPI0 },
+ { { MTK_DISP_DSI, 0 }, MT8365_MUTEX_MOD_DISP_DSI0 },
+ { { MTK_DISP_GAMMA, 0 }, MT8365_MUTEX_MOD_DISP_GAMMA },
+ { { MTK_DISP_OVL, 0 }, MT8365_MUTEX_MOD_DISP_OVL0 },
+ { { MTK_DISP_OVL_2L, 0 }, MT8365_MUTEX_MOD_DISP_OVL0_2L },
+ { { MTK_DISP_PWM, 0 }, MT8365_MUTEX_MOD_DISP_PWM0 },
+ { { MTK_DISP_RDMA, 0 }, MT8365_MUTEX_MOD_DISP_RDMA0 },
+ { { MTK_DISP_RDMA, 1 }, MT8365_MUTEX_MOD_DISP_RDMA1 },
+ { { MTK_DISP_WDMA, 0 }, MT8365_MUTEX_MOD_DISP_WDMA0 },
};
const struct mtk_drm_legacy_mtx_data mt8365_legacy_mtx_data = {
@@ -831,13 +831,15 @@ int mtk_drm_legacy_inject_mutex_trig_ids(struct mtk_drm_comp_list *hlist,
const struct mtk_drm_comp_definition *comp = &data->pairs[i].comp;
hash_for_each_possible(hlist->ddp_list, ddp_comp, lnode, comp->type)
- ddp_comp->mtx_trig_id = data->pairs[i].mtx_trig_id;
+ if (ddp_comp->inst_id == comp->inst_id)
+ ddp_comp->mtx_trig_id = data->pairs[i].mtx_trig_id;
}
return 0;
}
-u8 mtk_drm_legacy_get_ovl_adaptor_mutex_trig_id(enum mtk_ddp_comp_id ddp_type,
+u8 mtk_drm_legacy_get_ovl_adaptor_mutex_trig_id(enum mtk_ddp_comp_type ddp_type,
+ u8 ddp_inst_id,
struct device_node *mutex_node)
{
struct mtk_drm_legacy_mtx_data *data;
@@ -853,7 +855,7 @@ u8 mtk_drm_legacy_get_ovl_adaptor_mutex_trig_id(enum mtk_ddp_comp_id ddp_type,
for (i = 0; i < data->num_pairs; i++) {
const struct mtk_drm_comp_definition *comp = &data->pairs[i].comp;
- if (ddp_type != comp->type)
+ if (ddp_type != comp->type || ddp_inst_id != comp->inst_id)
continue;
return data->pairs[i].mtx_trig_id;
@@ -871,6 +873,6 @@ void mtk_drm_legacy_ovl_adaptor_probe(struct device *dev, struct mtk_drm_private
PLATFORM_DEVID_AUTO,
(void *)priv, sizeof(*priv));
- mtk_ddp_comp_init(&ovl_adaptor->dev, NULL, &priv->hlist, DDP_COMPONENT_DRM_OVL_ADAPTOR);
+ mtk_ddp_comp_init(&ovl_adaptor->dev, NULL, &priv->hlist, MTK_DISP_OVL_ADAPTOR, 0);
component_match_add(dev, match, component_compare_dev, &ovl_adaptor->dev);
}
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_legacy.h b/drivers/gpu/drm/mediatek/mtk_drm_legacy.h
index 45bcf2674628..da0395d859d2 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_legacy.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_legacy.h
@@ -27,7 +27,8 @@ extern struct mtk_drm_path_definition mt8195_vdo1_legacy_paths[];
int mtk_drm_legacy_inject_mutex_trig_ids(struct mtk_drm_comp_list *hlist,
struct device_node *mutex_node);
-u8 mtk_drm_legacy_get_ovl_adaptor_mutex_trig_id(enum mtk_ddp_comp_id ddp_type,
+u8 mtk_drm_legacy_get_ovl_adaptor_mutex_trig_id(enum mtk_ddp_comp_type ddp_type,
+ u8 ddp_inst_id,
struct device_node *mutex_node);
void mtk_drm_legacy_ovl_adaptor_probe(struct device *dev, struct mtk_drm_private *priv,
--
2.54.0
^ permalink raw reply related
* Re: [PATCH v2] wifi: mt76: add wcid publish check in mt76_sta_add
From: Greg KH @ 2026-07-01 13:48 UTC (permalink / raw)
To: Thorsten Leemhuis
Cc: stable@vger.kernel.org, Sasha Levin, Felix Fietkau,
Lorenzo Bianconi, Jiajia Liu, Ryder Lee, Shayne Chen, Sean Wang,
Matthias Brugger, AngeloGioacchino Del Regno, Ming Yen Hsieh,
Leon Yen, linux-wireless, linux-kernel, linux-arm-kernel,
linux-mediatek, Linux kernel regressions list
In-Reply-To: <dc7657b2-e3d5-4777-af52-1169fe743761@leemhuis.info>
On Wed, Jul 01, 2026 at 08:16:07AM +0200, Thorsten Leemhuis wrote:
> On 7/1/26 07:39, Jiajia Liu wrote:
> > On Tue, Jun 30, 2026 at 01:29:51PM +0200, Thorsten Leemhuis wrote:
> >> On 5/28/26 05:38, Jiajia Liu wrote:
> >>> Since mt7925_mac_sta_add publishes wcid, add publish check in mt76_sta_add
> >>> to avoid reinitializing the wcid->poll_list.
> >>>
> >>> Found dev->sta_poll_list corruption when using mt7925 and 7.1-rc4.
> >>
> >> Jiajia Liu, Felox:
>
> BTW: @Felix, sorry for the typo!
>
> >> given that the problem seems to be in 7.1, should we
> >> ask the stable team to pick this regression fix up, as this change was
> >> mainlined (as 20b126920a259d ("wifi: mt76: add wcid publish check in
> >> mt76_sta_add") [v7.2-rc1]), but lacks both a Fixes and a Stable tag?
> >
> > Yes. It seems to be related to cbf5e61da660 ("wifi: mt76: initialize
> > more wcid fields mt76_wcid_init") [v6.14-rc1]. But I didn't reproduce
> > when I checked it out and tested. So Fixes was not added.
>
> In that case:
>
> @Stable team, you you please pick up 20b126920a259d ("wifi: mt76: add
> wcid publish check in mt76_sta_add") [v7.2-rc1] for 7.1? It lacks a
> fixes tag and the problem might be older, but I saw two reports about
> this with 7.1-rc -- so it seems some recent change made that problem
> more likely to occur, so it might be good to fix it at least in 7.1.y.
Now queued up for 6.18.y and 7.1.y, thanks.
greg k-h
^ permalink raw reply
* [PATCH 05/42] drm/mediatek: Rename all display component type to have DISP_ prefix
From: AngeloGioacchino Del Regno @ 2026-07-01 12:20 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard, tzimmermann,
robh, krzk+dt, conor+dt, matthias.bgg, angelogioacchino.delregno,
dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, justin.yeh, jason-jh.lin, kernel
In-Reply-To: <20260701122057.19648-1-angelogioacchino.delregno@collabora.com>
The mtk_ddp_comp_type enumeration will end up containing both the
Display Controller and Media Data Path Controller components: this
is because those can be interconnected together (as in, using MDP
components in Display Controller paths is possible!) and because
both MMSYS and MuteX are managing both of those in practically the
same way.
Rename all of the Display Controller related HW components in the
list to always have a "DISP_" prefix.
This includes components that are in the MDP Controller instead,
and the strategy here is for some of those to also have the same
DISP_ prefix, so that:
- Display Controller specific components have a DISP_ prefix
- Example: MTK_DISP_(NAME)
- MDP Controller components that can be interconnected to the
Display Controller will have both DISP_ and MDP_ prefixes
- Example: MTK_DISP_MDP_(NAME)
- MDP Controller components that are exclusive to MDP and can
not be interconnected with Display Controller will only have
an MDP_ prefix but not a DISP_ prefix
- Example: MTK_MDP_(NAME).
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 28 +++++++++----------
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 36 ++++++++++++-------------
include/linux/soc/mediatek/mtk-mmsys.h | 6 ++---
3 files changed, 35 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
index 94b356da6de7..a6c1815ffa39 100644
--- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
@@ -423,9 +423,9 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_RDMA] = "rdma",
[MTK_DISP_UFOE] = "ufoe",
[MTK_DISP_WDMA] = "wdma",
- [MTK_DP_INTF] = "dp-intf",
- [MTK_DPI] = "dpi",
- [MTK_DSI] = "dsi",
+ [MTK_DISP_DP_INTF] = "dp-intf",
+ [MTK_DISP_DPI] = "dpi",
+ [MTK_DISP_DSI] = "dsi",
};
struct mtk_ddp_comp_match {
@@ -442,17 +442,17 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_DRM_ID_MAX]
[DDP_COMPONENT_COLOR0] = { MTK_DISP_COLOR, 0, &ddp_color },
[DDP_COMPONENT_COLOR1] = { MTK_DISP_COLOR, 1, &ddp_color },
[DDP_COMPONENT_DITHER0] = { MTK_DISP_DITHER, 0, &ddp_dither },
- [DDP_COMPONENT_DP_INTF0] = { MTK_DP_INTF, 0, &ddp_dpi },
- [DDP_COMPONENT_DP_INTF1] = { MTK_DP_INTF, 1, &ddp_dpi },
- [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi },
- [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi },
+ [DDP_COMPONENT_DP_INTF0] = { MTK_DISP_DP_INTF, 0, &ddp_dpi },
+ [DDP_COMPONENT_DP_INTF1] = { MTK_DISP_DP_INTF, 1, &ddp_dpi },
+ [DDP_COMPONENT_DPI0] = { MTK_DISP_DPI, 0, &ddp_dpi },
+ [DDP_COMPONENT_DPI1] = { MTK_DISP_DPI, 1, &ddp_dpi },
[DDP_COMPONENT_DRM_OVL_ADAPTOR] = { MTK_DISP_OVL_ADAPTOR, 0, &ddp_ovl_adaptor },
[DDP_COMPONENT_DSC0] = { MTK_DISP_DSC, 0, &ddp_dsc },
[DDP_COMPONENT_DSC1] = { MTK_DISP_DSC, 1, &ddp_dsc },
- [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi },
- [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi },
- [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi },
- [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi },
+ [DDP_COMPONENT_DSI0] = { MTK_DISP_DSI, 0, &ddp_dsi },
+ [DDP_COMPONENT_DSI1] = { MTK_DISP_DSI, 1, &ddp_dsi },
+ [DDP_COMPONENT_DSI2] = { MTK_DISP_DSI, 2, &ddp_dsi },
+ [DDP_COMPONENT_DSI3] = { MTK_DISP_DSI, 3, &ddp_dsi },
[DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma },
[DDP_COMPONENT_MERGE0] = { MTK_DISP_MERGE, 0, &ddp_merge },
[DDP_COMPONENT_MERGE1] = { MTK_DISP_MERGE, 1, &ddp_merge },
@@ -659,9 +659,9 @@ int mtk_ddp_comp_init(struct device *dev, struct device_node *node, struct mtk_d
type == MTK_DISP_PWM ||
type == MTK_DISP_RDMA ||
type == MTK_DISP_WDMA ||
- type == MTK_DPI ||
- type == MTK_DP_INTF ||
- type == MTK_DSI)
+ type == MTK_DISP_DPI ||
+ type == MTK_DISP_DP_INTF ||
+ type == MTK_DISP_DSI)
return 0;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index e54f0654f2f9..9c6dfc1e384b 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -801,35 +801,35 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
{ .compatible = "mediatek,mt8173-disp-wdma",
.data = (void *)MTK_DISP_WDMA },
{ .compatible = "mediatek,mt2701-dpi",
- .data = (void *)MTK_DPI },
+ .data = (void *)MTK_DISP_DPI },
{ .compatible = "mediatek,mt8167-dsi",
- .data = (void *)MTK_DSI },
+ .data = (void *)MTK_DISP_DSI },
{ .compatible = "mediatek,mt8173-dpi",
- .data = (void *)MTK_DPI },
+ .data = (void *)MTK_DISP_DPI },
{ .compatible = "mediatek,mt8183-dpi",
- .data = (void *)MTK_DPI },
+ .data = (void *)MTK_DISP_DPI },
{ .compatible = "mediatek,mt8186-dpi",
- .data = (void *)MTK_DPI },
+ .data = (void *)MTK_DISP_DPI },
{ .compatible = "mediatek,mt8188-dp-intf",
- .data = (void *)MTK_DP_INTF },
+ .data = (void *)MTK_DISP_DP_INTF },
{ .compatible = "mediatek,mt8192-dpi",
- .data = (void *)MTK_DPI },
+ .data = (void *)MTK_DISP_DPI },
{ .compatible = "mediatek,mt8195-dp-intf",
- .data = (void *)MTK_DP_INTF },
+ .data = (void *)MTK_DISP_DP_INTF },
{ .compatible = "mediatek,mt8195-dpi",
- .data = (void *)MTK_DPI },
+ .data = (void *)MTK_DISP_DPI },
{ .compatible = "mediatek,mt2701-dsi",
- .data = (void *)MTK_DSI },
+ .data = (void *)MTK_DISP_DSI },
{ .compatible = "mediatek,mt8173-dsi",
- .data = (void *)MTK_DSI },
+ .data = (void *)MTK_DISP_DSI },
{ .compatible = "mediatek,mt8183-dsi",
- .data = (void *)MTK_DSI },
+ .data = (void *)MTK_DISP_DSI },
{ .compatible = "mediatek,mt8186-dsi",
- .data = (void *)MTK_DSI },
+ .data = (void *)MTK_DISP_DSI },
{ .compatible = "mediatek,mt8188-dsi",
- .data = (void *)MTK_DSI },
+ .data = (void *)MTK_DISP_DSI },
{ .compatible = "mediatek,mt8196-dsi",
- .data = (void *)MTK_DSI },
+ .data = (void *)MTK_DISP_DSI },
{ }
};
@@ -1176,9 +1176,9 @@ static int mtk_drm_probe(struct platform_device *pdev)
comp_type == MTK_DISP_OVL_ADAPTOR ||
comp_type == MTK_DISP_RDMA ||
comp_type == MTK_DISP_WDMA ||
- comp_type == MTK_DP_INTF ||
- comp_type == MTK_DPI ||
- comp_type == MTK_DSI) {
+ comp_type == MTK_DISP_DP_INTF ||
+ comp_type == MTK_DISP_DPI ||
+ comp_type == MTK_DISP_DSI) {
dev_info(dev, "Adding component match for %pOF\n",
node);
drm_of_component_match_add(dev, &match, component_compare_of,
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 3ddfdeac658d..bbdd0b01927d 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -111,9 +111,9 @@ enum mtk_ddp_comp_type {
MTK_DISP_MDP_RDMA,
/* Keep Display outputs at the end for readability */
- MTK_DPI,
- MTK_DP_INTF,
- MTK_DSI,
+ MTK_DISP_DPI,
+ MTK_DISP_DP_INTF,
+ MTK_DISP_DSI,
MTK_DDP_COMP_TYPE_MAX
};
--
2.54.0
^ permalink raw reply related
* [PATCH 10/11] drm/mediatek: mtk_dp: Add support for eDP1.5 IPs and MT8196 SoC
From: AngeloGioacchino Del Regno @ 2026-07-01 12:20 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard, tzimmermann,
robh, krzk+dt, conor+dt, matthias.bgg, angelogioacchino.delregno,
jitao.shi, granquet, rex-bc.chen, dmitry.osipenko, ck.hu,
amergnat, justin.yeh, jason-jh.lin, dri-devel, linux-mediatek,
devicetree, linux-kernel, linux-arm-kernel, kernel
In-Reply-To: <20260701122024.19557-1-angelogioacchino.delregno@collabora.com>
Add support for MediaTek's Embedded DisplayPort (eDP) v1.5 IP as
found in the MT8196 SoC and other variants, and enclose some of
the new register writes in specific platform data booleans, as:
- SDP on Encoder1 can be supported by both old and new IPs
but it was chosen to use Encoder0 for SDP in the new ones
in order to decrease the load on the secondary encoder;
- PSR can be supported by older IPs as well, but was not tested
on those yet (requires a display with PSR support connected
to a device with older SoC, and I don't have it right now);
- Power State forcing may not be needed on newer revisions of
the eDP/DP IP (in SoCs newer than MT8196/MT6991).
As a note, even if this effectively adds some partial support for
the DisplayPort 1.4 IP from the same SoC (because the DP1.4 and
eDP1.5 IPs in this SoC have some little common parts in common),
there is still a long road ahead to actually enable support for
the DP1.4 IP itself.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_dp.c | 283 +++++++++++++++++++++++---
drivers/gpu/drm/mediatek/mtk_dp_reg.h | 61 +++++-
2 files changed, 310 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/mtk_dp.c
index 2d58eacb3d3e..605ead7fa9bf 100644
--- a/drivers/gpu/drm/mediatek/mtk_dp.c
+++ b/drivers/gpu/drm/mediatek/mtk_dp.c
@@ -2,6 +2,8 @@
/*
* Copyright (c) 2019-2022 MediaTek Inc.
* Copyright (c) 2022 BayLibre
+ * Copyright (c) 2026 Collabora Ltd
+ * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
*/
#include <drm/display/drm_dp_aux_bus.h>
@@ -57,6 +59,8 @@
#define MTK_DP_TOP_OFFSET_LEGACY 0x2000
#define MTK_DP_SIP_CONTROL_AARCH32 MTK_SIP_SMC_CMD(0x523)
+#define MTK_DP_SIP_ATF_EDP_SET_VID_MUTE 34
+# define MTK_DP_SIP_REQ_VIDEO_UNMUTE 0xfefd
#define MTK_DP_SIP_ATF_EDP_VIDEO_UNMUTE 33
#define MTK_DP_SIP_ATF_VIDEO_UNMUTE 32
@@ -168,7 +172,11 @@ struct mtk_dp_data {
bool audio_pkt_in_hblank_area;
u16 audio_m_div2_bit;
u8 hw_max_link_rate;
+ bool hwip_v1p4;
bool aux_hpd_supported;
+ bool sdp_encoder1_enable;
+ bool force_pwr_states;
+ bool psr_supported;
};
static const struct mtk_dp_efuse_fmt mt8188_dp_efuse_fmt[MTK_DP_CAL_MAX] = {
@@ -507,6 +515,7 @@ static void mtk_dp_msa_bypass_enable(struct mtk_dp *mtk_dp, bool enable)
static void mtk_dp_set_msa(struct mtk_dp *mtk_dp)
{
+ u32 fde_start_val;
struct drm_display_mode mode;
struct videomode *vm = &mtk_dp->info.vm;
@@ -549,9 +558,14 @@ static void mtk_dp_set_msa(struct mtk_dp *mtk_dp)
mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_315C,
vm->hsync_len,
PGEN_HSYNC_PULSE_WIDTH_DP_ENC0_P0_MASK);
+
+ fde_start_val = vm->hback_porch + vm->hsync_len;
+ if (mtk_dp->data->psr_supported)
+ fde_start_val += vm->hfront_porch;
+
mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3160,
- vm->hback_porch + vm->hsync_len,
- PGEN_HFDE_START_DP_ENC0_P0_MASK);
+ fde_start_val, PGEN_HFDE_START_DP_ENC0_P0_MASK);
+
mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3164,
vm->hactive,
PGEN_HFDE_ACTIVE_WIDTH_DP_ENC0_P0_MASK);
@@ -566,9 +580,14 @@ static void mtk_dp_set_msa(struct mtk_dp *mtk_dp)
mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3170,
vm->vsync_len,
PGEN_VSYNC_PULSE_WIDTH_DP_ENC0_P0_MASK);
+
+ fde_start_val = vm->vback_porch + vm->vsync_len;
+ if (mtk_dp->data->psr_supported)
+ fde_start_val += vm->vfront_porch;
+
mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3174,
- vm->vback_porch + vm->vsync_len,
- PGEN_VFDE_START_DP_ENC0_P0_MASK);
+ fde_start_val, PGEN_VFDE_START_DP_ENC0_P0_MASK);
+
mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3178,
vm->vactive,
PGEN_VFDE_ACTIVE_WIDTH_DP_ENC0_P0_MASK);
@@ -632,6 +651,8 @@ static void mtk_dp_set_sram_read_start(struct mtk_dp *mtk_dp, u32 val)
static void mtk_dp_setup_encoder(struct mtk_dp *mtk_dp)
{
+ u32 val, mask;
+
mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_303C,
VIDEO_MN_GEN_EN_DP_ENC0_P0,
VIDEO_MN_GEN_EN_DP_ENC0_P0);
@@ -647,7 +668,16 @@ static void mtk_dp_setup_encoder(struct mtk_dp *mtk_dp)
mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3364,
FIFO_READ_START_POINT_DP_ENC1_P0_VAL << 12,
FIFO_READ_START_POINT_DP_ENC1_P0_MASK);
- mtk_dp_write(mtk_dp, MTK_DP_ENC1_P0_3368, DP_ENC1_P0_3368_VAL);
+
+ mask = VIDEO_SRAM_FIFO_CNT_RESET_SEL_DP_ENC1_P0 | VIDEO_STABLE_CNT_THRD_DP_ENC1_P0;
+ mask |= BS2BS_MODE_DP_ENC1_P0;
+
+ val = mask;
+
+ if (mtk_dp->data->sdp_encoder1_enable)
+ val |= SDP_DP13_EN_DP_ENC1_P0;
+
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3368, val, mask);
}
static void mtk_dp_pg_enable(struct mtk_dp *mtk_dp, bool enable)
@@ -1106,6 +1136,72 @@ static void mtk_dp_hwirq_enable(struct mtk_dp *mtk_dp, bool enable)
IRQ_MASK_DP_TRANS_P0_MASK);
}
+static void mtk_dp_encoder_force_bias_power_on(struct mtk_dp *mtk_dp)
+{
+ /* Force MCU to enable BIAS */
+ mtk_dp_update_bits(mtk_dp, REG_3F44_DP_ENC_P0_3,
+ ENC_PHY_PWR_OVERWRITE_EN, ENC_PHY_PWR_OVERWRITE_EN);
+ mtk_dp_update_bits(mtk_dp, REG_3F44_DP_ENC_P0_3,
+ FIELD_PREP_CONST(ENC_PHY_PWR_STATE_OVERWRITE_MASK,
+ ENC_PHY_BIAS_PWR_ON),
+ ENC_PHY_PWR_STATE_OVERWRITE_MASK);
+
+ /* Wait for the MCU to get LDO ready in PHYD */
+ msleep(50);
+
+ mtk_dp_update_bits(mtk_dp, REG_3F44_DP_ENC_P0_3,
+ 0, ENC_PHY_PWR_OVERWRITE_EN);
+}
+
+static void mtk_dp_encoder_force_bias_power_off(struct mtk_dp *mtk_dp)
+{
+ /* Force MCU to disable power */
+ mtk_dp_update_bits(mtk_dp, REG_3F44_DP_ENC_P0_3,
+ ENC_PHY_PWR_OVERWRITE_EN, ENC_PHY_PWR_OVERWRITE_EN);
+ mtk_dp_update_bits(mtk_dp, REG_3F44_DP_ENC_P0_3,
+ FIELD_PREP_CONST(ENC_PHY_PWR_STATE_OVERWRITE_MASK,
+ ENC_PHY_ALL_PWR_OFF),
+ ENC_PHY_PWR_STATE_OVERWRITE_MASK);
+ mtk_dp_update_bits(mtk_dp, REG_3F44_DP_ENC_P0_3,
+ 0, ENC_PHY_PWR_OVERWRITE_EN);
+}
+
+static void mtk_dp_initialize_psr_settings(struct mtk_dp *mtk_dp)
+{
+ mtk_dp_update_bits(mtk_dp, MTK_DP_PSR_FRAME_START_MARKER_0, 0,
+ DP_ENC_P0_3_FRAME_MARKER_MASK);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_PSR_FRAME_END_MARKER_0, 1,
+ DP_ENC_P0_3_FRAME_MARKER_MASK);
+
+ mtk_dp_update_bits(mtk_dp, MTK_DP_PSR_FRAME_START_MARKER_1, 8,
+ DP_ENC_P0_3_FRAME_MARKER_MASK);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_PSR_FRAME_END_MARKER_1, 9,
+ DP_ENC_P0_3_FRAME_MARKER_MASK);
+
+ mtk_dp_update_bits(mtk_dp, REG_33C0_DP_ENCODER1_P0, 0,
+ SDP_TESTBUS_SEL_DP_ENC_MASK);
+ mtk_dp_update_bits(mtk_dp, REG_33C4_DP_ENCODER1_P0,
+ DP_TX_ENCODER_TESTBUS_SEL_DP_ENC,
+ DP_TX_ENCODER_TESTBUS_SEL_DP_ENC_MASK);
+ mtk_dp_update_bits(mtk_dp, REG_3F28_DP_ENC_P0_3,
+ DP_TX_SDP_PSR_AS_TESTBUS << 2,
+ DP_TX_SDP_PSR_AS_TESTBUS_MASK);
+}
+
+static void mtk_dp_initialize_settings_v2p1(struct mtk_dp *mtk_dp)
+{
+ /* For DP2.1 and eDP1.5 IPs, reset all and enable probing */
+ mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_RESET_AND_PROBE,
+ RG_SW_RST_ALL, RG_SW_RST_ALL);
+
+ mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_RESET_AND_PROBE,
+ FIELD_PREP_CONST(RG_PROBE_LOW_SEL_MASK, RG_PROBE_ENCODER0),
+ RG_PROBE_LOW_SEL_MASK);
+
+ mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_RESET_AND_PROBE,
+ RG_PROBE_LOW_HIGH_SWAP, RG_PROBE_LOW_HIGH_SWAP);
+}
+
static void mtk_dp_initialize_settings(struct mtk_dp *mtk_dp)
{
mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_342C,
@@ -1119,12 +1215,15 @@ static void mtk_dp_initialize_settings(struct mtk_dp *mtk_dp)
AUDIO_CH_SRC_SEL_DP_ENC0_P0);
mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_304C,
0, SDP_VSYNC_RISING_MASK_DP_ENC0_P0_MASK);
- mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_IRQ_MASK,
- IRQ_MASK_AUX_TOP_IRQ, IRQ_MASK_AUX_TOP_IRQ);
}
static void mtk_dp_initialize_aux_hpd_detect_settings(struct mtk_dp *mtk_dp)
{
+ /* Mask Encoder and Transmitter interrupts, unmask AUX TOP */
+ mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_IRQ_MASK,
+ ENCODER0_IRQ_MSK | TRANS_IRQ_MSK,
+ ENCODER0_IRQ_MSK | TRANS_IRQ_MSK | AUX_TOP_IRQ_MSK);
+
/* Set interrupt debounce threshold time */
mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_364C,
FIELD_PREP_CONST(HPD_INT_LOW_TIME_THD, 2) |
@@ -1151,6 +1250,10 @@ static void mtk_dp_initialize_hpd_detect_settings(struct mtk_dp *mtk_dp)
{
u32 val;
+ /* Mask AUX TOP interrupt, as this uses transmitter for HPD */
+ mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_IRQ_MASK,
+ AUX_TOP_IRQ_MSK, AUX_TOP_IRQ_MSK);
+
/* Debounce threshold */
mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3410,
8, HPD_DEB_THD_DP_TRANS_P0_MASK);
@@ -1200,24 +1303,87 @@ static void mtk_dp_initialize_aux_settings(struct mtk_dp *mtk_dp)
RX_REPLY_COMPLETE_MODE_AUX_TX_P0);
}
-static void mtk_dp_initialize_digital_settings(struct mtk_dp *mtk_dp)
+static void mtk_dp_initialize_common_digital_settings(struct mtk_dp *mtk_dp)
{
mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_304C,
0, VBID_VIDEO_MUTE_DP_ENC0_P0_MASK);
mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3368,
- BS2BS_MODE_DP_ENC1_P0_VAL << 12,
- BS2BS_MODE_DP_ENC1_P0_MASK);
+ BS2BS_MODE_DP_ENC1_P0, BS2BS_MODE_DP_ENC1_P0_MASK);
+}
+
+static void mtk_dp_initialize_digital_settings_v2p1(struct mtk_dp *mtk_dp)
+{
+ /* Set XTAL frequency for Panel Self Refresh (PSR) */
+ if (mtk_dp->data->psr_supported)
+ mtk_dp_update_bits(mtk_dp, REG_3FF8_DP_ENC_P0_3,
+ FIELD_PREP(DP_ENCODER_PSR_XTAL_FREQ_MHZ_MASK, 25),
+ DP_ENCODER_PSR_XTAL_FREQ_MHZ_MASK);
+
+ /* Enable I-Mode */
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3000,
+ DP_I_MODE_ENABLE, DP_I_MODE_ENABLE);
+
+ /* Reset Video SRAM and Symbol count */
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3000,
+ REG_BS_SYMBOL_CNT_RESET, REG_BS_SYMBOL_CNT_RESET);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3368,
+ VIDEO_SRAM_FIFO_CNT_RESET_SEL_DP_ENC1_P0,
+ VIDEO_SRAM_FIFO_CNT_RESET_SEL_MASK);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3368,
+ BS_FOLLOW_SEL_DP_ENC0_P0, BS_FOLLOW_SEL_DP_ENC0_P0);
+
+ /* [5:0] Video SRAM start address */
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_303C,
+ 0x8, SRAM_START_READ_THRD_DP_ENC0_P0_MASK);
+
+ /* Disable Pattern Generator in Panel Self Refresh mode */
+ if (mtk_dp->data->psr_supported)
+ mtk_dp_update_bits(mtk_dp, REG_3F80_DP_ENC_P0_3,
+ 0, PSR_PATGEN_AVT_EN_FLDMASK);
+
+ /* Force MCU to enable BIAS and PLL */
+ mtk_dp_encoder_force_bias_power_on(mtk_dp);
+
+ mtk_dp_update_bits(mtk_dp, REG_3FF8_DP_ENC_P0_3,
+ PHY_STATE_W_1_DP_ENC_P0_3, PHY_STATE_W_1_DP_ENC_P0_3);
+ /* Force enable Digital Video Output */
+ mtk_dp_update_bits(mtk_dp, REG_3FF8_DP_ENC_P0_3,
+ DP_ENCODER_DVO_ON_W_1, DP_ENCODER_DVO_ON_W_1);
+}
+
+static void mtk_dp_encoder_reset(struct mtk_dp *mtk_dp)
+{
/* dp tx encoder reset all sw */
mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3004,
DP_TX_ENCODER_4P_RESET_SW_DP_ENC0_P0,
DP_TX_ENCODER_4P_RESET_SW_DP_ENC0_P0);
+ if (mtk_dp->data->hwip_v1p4) {
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3004, 0,
+ DP_TX_ENCODER_4P_RESET_SW_DP_ENC0_P0);
+ mtk_dp_update_bits(mtk_dp, REG_3FF8_DP_ENC_P0_3,
+ ENC_PHY_STATE_RESET_ALL_MASK,
+ ENC_PHY_STATE_RESET_ALL_MASK);
+ }
+
/* Wait for sw reset to complete */
usleep_range(1000, 5000);
- mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3004,
- 0, DP_TX_ENCODER_4P_RESET_SW_DP_ENC0_P0);
+
+ if (!mtk_dp->data->hwip_v1p4)
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3004,
+ 0, DP_TX_ENCODER_4P_RESET_SW_DP_ENC0_P0);
+}
+
+static void mtk_dp_initialize_digital_settings(struct mtk_dp *mtk_dp)
+{
+ mtk_dp_initialize_common_digital_settings(mtk_dp);
+
+ if (mtk_dp->data->hwip_v1p4)
+ mtk_dp_initialize_digital_settings_v2p1(mtk_dp);
+
+ mtk_dp_encoder_reset(mtk_dp);
}
static void mtk_dp_digital_sw_reset(struct mtk_dp *mtk_dp)
@@ -1230,6 +1396,26 @@ static void mtk_dp_digital_sw_reset(struct mtk_dp *mtk_dp)
usleep_range(1000, 5000);
mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_340C,
0, DP_TX_TRANSMITTER_4P_RESET_SW_DP_TRANS_P0);
+
+ /* Only for the new eDP 1.5 IP, set the internal clock generators */
+ if (mtk_dp->data->hwip_v1p4 &&
+ mtk_dp->data->bridge_type == DRM_MODE_CONNECTOR_eDP) {
+ u32 val;
+
+ /* Enable internal clock outputs for AUX TOP, DATA and MUX */
+ val = EDP_TX_TOP_CLKGEN_AUX_P0_EN | EDP_TX_TOP_CLKGEN_AUX_MUX_DATA_EN |
+ EDP_TX_TOP_CLKGEN_AUX_MUX_VALID_EN;
+
+ /* Enable XTAL output */
+ val |= EDP_TX_TOP_CLKGEN_XTAL_P0_EN;
+
+ /* VSC and Encoders */
+ val |= EDP_TX_TOP_CLKGEN_LS_VSC_W_0_EN;
+ val |= EDP_TX_TOP_CLKGEN_LS_ENCODER_L0_EN | EDP_TX_TOP_CLKGEN_LS_ENCODER_L1_EN;
+ val |= EDP_TX_TOP_CLKGEN_LS_ENCODER_L2_EN | EDP_TX_TOP_CLKGEN_LS_ENCODER_L3_EN;
+
+ mtk_dp_update_bits(mtk_dp, EDP_TX_TOP_CLKGEN_0, val, val);
+ }
}
static void mtk_dp_sdp_path_reset(struct mtk_dp *mtk_dp)
@@ -1246,6 +1432,9 @@ static void mtk_dp_sdp_path_reset(struct mtk_dp *mtk_dp)
static void mtk_dp_set_lanes(struct mtk_dp *mtk_dp, int lanes)
{
+ if (mtk_dp->data->force_pwr_states)
+ mtk_dp_encoder_force_bias_power_on(mtk_dp);
+
mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_35F0,
lanes == 0 ? 0 : DP_TRANS_DUMMY_RW_0,
DP_TRANS_DUMMY_RW_0_MASK);
@@ -1361,8 +1550,10 @@ static int mtk_dp_phy_configure(struct mtk_dp *mtk_dp,
}
};
- mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE, DP_PWR_STATE_BANDGAP,
- DP_PWR_STATE_MASK);
+ /* Set power state requests only if power states are not forced */
+ if (!mtk_dp->data->force_pwr_states)
+ mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE, DP_PWR_STATE_BANDGAP,
+ DP_PWR_STATE_MASK);
ret = phy_configure(mtk_dp->phy, &phy_opts);
if (ret)
@@ -1375,6 +1566,11 @@ static int mtk_dp_phy_configure(struct mtk_dp *mtk_dp,
if (mtk_dp->phy_dev)
mtk_dp_set_calibration_data(mtk_dp);
+ if (mtk_dp->data->force_pwr_states)
+ mtk_dp_update_bits(mtk_dp, REG_3FF8_DP_ENC_P0_3,
+ PHY_STATE_W_1_DP_ENC_P0_3,
+ PHY_STATE_W_1_DP_ENC_P0_3);
+
mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE,
DP_PWR_STATE_BANDGAP_TPLL_LANE, DP_PWR_STATE_MASK);
@@ -1424,17 +1620,24 @@ static void mtk_dp_training_set_scramble(struct mtk_dp *mtk_dp, bool enable)
static void mtk_dp_video_mute(struct mtk_dp *mtk_dp, bool enable)
{
struct arm_smccc_res res;
- u32 val = VIDEO_MUTE_SEL_DP_ENC0_P0 |
- (enable ? VIDEO_MUTE_SW_DP_ENC0_P0 : 0);
+ const u32 mask = VIDEO_MUTE_SEL_DP_ENC0_P0 | VIDEO_MUTE_SW_DP_ENC0_P0;
+ u32 val = VIDEO_MUTE_SEL_DP_ENC0_P0 | (enable ? VIDEO_MUTE_SW_DP_ENC0_P0 : 0);
+ u32 smc_para, smc_val;
- mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3000,
- val,
- VIDEO_MUTE_SEL_DP_ENC0_P0 |
- VIDEO_MUTE_SW_DP_ENC0_P0);
+ /* Set VIDEO_MUTE in unsecured world... */
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3000, val, mask);
+
+ /* ...and do the same in ATF as well */
+ if (mtk_dp->data->hwip_v1p4) {
+ smc_para = (mtk_dp->data->smc_cmd << 16) | enable;
+ smc_val = MTK_DP_SIP_REQ_VIDEO_UNMUTE;
+ } else {
+ smc_para = 0;
+ smc_val = 0;
+ }
- arm_smccc_smc(MTK_DP_SIP_CONTROL_AARCH32,
- mtk_dp->data->smc_cmd, enable,
- 0, 0, 0, 0, 0, &res);
+ arm_smccc_smc(MTK_DP_SIP_CONTROL_AARCH32, mtk_dp->data->smc_cmd, enable,
+ smc_para, smc_val, 0, 0, 0, &res);
dev_dbg(mtk_dp->dev, "smc cmd: 0x%x, p1: %s, ret: 0x%lx-0x%lx\n",
mtk_dp->data->smc_cmd, enable ? "enable" : "disable", res.a0, res.a1);
@@ -1522,6 +1725,9 @@ static void mtk_dp_power_disable(struct mtk_dp *mtk_dp)
mtk_dp_write(mtk_dp, MTK_DP_TOP_PWR_STATE, 0);
+ if (mtk_dp->data->force_pwr_states)
+ mtk_dp_encoder_force_bias_power_off(mtk_dp);
+
if (unlikely(mtk_dp->phy_dev)) {
mtk_dp_update_bits(mtk_dp, MTK_DP_0034,
DA_CKM_CKTX0_EN_FORCE_EN, DA_CKM_CKTX0_EN_FORCE_EN);
@@ -2081,7 +2287,14 @@ static void mtk_dp_init_port(struct mtk_dp *mtk_dp)
mtk_dp_set_idle_pattern(mtk_dp, true);
mtk_dp_initialize_priv_data(mtk_dp);
- mtk_dp_initialize_settings(mtk_dp);
+ if (mtk_dp->data->psr_supported)
+ mtk_dp_initialize_psr_settings(mtk_dp);
+
+ if (mtk_dp->data->hwip_v1p4)
+ mtk_dp_initialize_settings_v2p1(mtk_dp);
+ else
+ mtk_dp_initialize_settings(mtk_dp);
+
mtk_dp_initialize_aux_settings(mtk_dp);
mtk_dp_initialize_digital_settings(mtk_dp);
@@ -2583,6 +2796,9 @@ static void mtk_dp_bridge_atomic_disable(struct drm_bridge *bridge,
/* SDP path reset sw*/
mtk_dp_sdp_path_reset(mtk_dp);
+ if (mtk_dp->data->force_pwr_states)
+ mtk_dp_encoder_force_bias_power_on(mtk_dp);
+
/* Ensure the sink is muted */
msleep(20);
}
@@ -3089,6 +3305,7 @@ static const struct mtk_dp_data mt8188_dp_data = {
.audio_pkt_in_hblank_area = true,
.audio_m_div2_bit = MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2,
.hw_max_link_rate = DP_LINK_BW_5_4,
+ .sdp_encoder1_enable = true,
};
static const struct mtk_dp_data mt8195_edp_data = {
@@ -3098,6 +3315,7 @@ static const struct mtk_dp_data mt8195_edp_data = {
.audio_supported = false,
.audio_m_div2_bit = MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2,
.hw_max_link_rate = DP_LINK_BW_5_4,
+ .sdp_encoder1_enable = true,
};
static const struct mtk_dp_data mt8195_dp_data = {
@@ -3107,6 +3325,19 @@ static const struct mtk_dp_data mt8195_dp_data = {
.audio_supported = true,
.audio_m_div2_bit = MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2,
.hw_max_link_rate = DP_LINK_BW_5_4,
+ .sdp_encoder1_enable = true,
+};
+
+static const struct mtk_dp_data mt8196_edp_data = {
+ .bridge_type = DRM_MODE_CONNECTOR_eDP,
+ .smc_cmd = MTK_DP_SIP_ATF_EDP_SET_VID_MUTE,
+ .audio_supported = false,
+ .audio_m_div2_bit = MT8195_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2,
+ .hw_max_link_rate = DP_LINK_BW_8_1,
+ .hwip_v1p4 = true,
+ .aux_hpd_supported = true,
+ .force_pwr_states = true,
+ .psr_supported = true,
};
static const struct of_device_id mtk_dp_of_match[] = {
@@ -3126,6 +3357,10 @@ static const struct of_device_id mtk_dp_of_match[] = {
.compatible = "mediatek,mt8195-dp-tx",
.data = &mt8195_dp_data,
},
+ {
+ .compatible = "mediatek,mt8196-edp-tx",
+ .data = &mt8196_edp_data,
+ },
{},
};
MODULE_DEVICE_TABLE(of, mtk_dp_of_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_dp_reg.h b/drivers/gpu/drm/mediatek/mtk_dp_reg.h
index 5a3b3e2b4f49..9caf743f4fe6 100644
--- a/drivers/gpu/drm/mediatek/mtk_dp_reg.h
+++ b/drivers/gpu/drm/mediatek/mtk_dp_reg.h
@@ -31,25 +31,38 @@
#define DP_TX3_PRE_EMPH_MASK GENMASK(27, 26)
#define MTK_DP_TOP_RESET_AND_PROBE 0x20
#define SW_RST_B_PHYD BIT(4)
-#define RG_SW_RST_MASK GENMASK(7, 0)
-#define RG_SW_RST 0xff
+#define RG_SW_RST_ALL GENMASK(7, 0)
#define RG_PROBE_LOW_SEL_MASK GENMASK(18, 16)
+# define RG_PROBE_SW 0
+# define RG_PROBE_ENCODER0 1
+# define RG_PROBE_TRANSMITTER 2
+# define RG_PROBE_AUX_TOP 3
+# define RG_PROBE_PHY 4
+# define RG_PROBE_MST14 5
+# define RG_PROBE_ENCODER1 6
#define RG_PROBE_LOW_SEL BIT(16)
-#define RG_PROBE_LOW_HIGH_SWAP_MASK BIT(23)
#define RG_PROBE_LOW_HIGH_SWAP BIT(23)
#define MTK_DP_TOP_IRQ_MASK 0x2c
-#define ENCODER_IRQ_MSK BIT(0)
+#define ENCODER0_IRQ_MSK BIT(0)
#define TRANS_IRQ_MSK BIT(1)
-#define IRQ_MASK_AUX_TOP_IRQ BIT(2)
+#define AUX_TOP_IRQ_MSK BIT(2)
+#define ENCODER1_IRQ_MSK BIT(3)
#define MTK_DP_TOP_MEM_PD 0x38
#define MEM_ISO_EN BIT(0)
#define FUSE_SEL BIT(2)
#define EDP_TX_TOP_CLKGEN_0 0x74
-#define EDP_TX_TOP_CLKGEN_REST_MASK 0xf
-#define EDP_TX_TOP_CLKGEN_REST_VALUE 0xf
+#define EDP_TX_TOP_CLKGEN_AUX_P0_EN BIT(0)
+#define EDP_TX_TOP_CLKGEN_AUX_MUX_DATA_EN BIT(1)
+#define EDP_TX_TOP_CLKGEN_AUX_MUX_VALID_EN BIT(2)
+#define EDP_TX_TOP_CLKGEN_XTAL_P0_EN BIT(3)
+#define EDP_TX_TOP_CLKGEN_LS_VSC_W_0_EN BIT(4)
+#define EDP_TX_TOP_CLKGEN_LS_ENCODER_L0_EN BIT(5)
+#define EDP_TX_TOP_CLKGEN_LS_ENCODER_L1_EN BIT(6)
+#define EDP_TX_TOP_CLKGEN_LS_ENCODER_L2_EN BIT(7)
+#define EDP_TX_TOP_CLKGEN_LS_ENCODER_L3_EN BIT(8)
/* offset: ENC0_OFFSET (0x1000) */
#define MTK_DP_ENC0_P0_3000 0x1000
@@ -210,16 +223,19 @@
#define BS2BS_MODE_DP_ENC1_P0 BIT(12)
#define BS_FOLLOW_SEL_DP_ENC0_P0 BIT(15)
#define BS2BS_MODE_DP_ENC1_P0_MASK GENMASK(13, 12)
-#define BS2BS_MODE_DP_ENC1_P0_VAL 1
#define DP_ENC1_P0_3368_VAL (VIDEO_SRAM_FIFO_CNT_RESET_SEL_DP_ENC1_P0 | \
VIDEO_STABLE_CNT_THRD_DP_ENC1_P0 | \
SDP_DP13_EN_DP_ENC1_P0 | \
BS2BS_MODE_DP_ENC1_P0)
-
#define MTK_DP_ENC1_P0_3374 0x1374
#define SDP_ASP_INSERT_IN_HBLANK_DP_ENC1_P0_MASK BIT(12)
#define SDP_DOWN_ASP_CNT_INIT_DP_ENC1_P0_MASK GENMASK(11, 0)
-
+#define REG_33C0_DP_ENCODER1_P0 0x13c0
+#define SDP_TESTBUS_SEL_DP_ENC_MASK GENMASK(15, 12)
+#define SDP_TESTBUS_SEL_BIT_DP_ENC BIT(7)
+#define REG_33C4_DP_ENCODER1_P0 0x13c4
+#define DP_TX_ENCODER_TESTBUS_SEL_DP_ENC_MASK GENMASK(6, 5)
+#define DP_TX_ENCODER_TESTBUS_SEL_DP_ENC BIT(5)
#define MTK_DP_ENC1_P0_33F4 0x13f4
#define DP_ENC_DUMMY_RW_1_AUDIO_RST_EN BIT(0)
#define DP_ENC_DUMMY_RW_1 BIT(9)
@@ -361,6 +377,31 @@
#define MTK_DP_AUX_P0_37C8 0x17c8
#define MTK_ATOP_EN_AUX_TX_P0 BIT(0)
+/* offset info queue */
+#define MTK_DP_PSR_FRAME_START_MARKER_0 0x1f04
+#define MTK_DP_PSR_FRAME_START_MARKER_1 0x1f08
+#define MTK_DP_PSR_FRAME_END_MARKER_0 0x1f0c
+#define MTK_DP_PSR_FRAME_END_MARKER_1 0x1f10
+#define DP_ENC_P0_3_FRAME_MARKER_MASK GENMASK(15, 0)
+#define REG_3F28_DP_ENC_P0_3 0x1f28
+#define DP_TX_SDP_PSR_AS_TESTBUS_MASK GENMASK(5, 2)
+#define DP_TX_SDP_PSR_AS_TESTBUS 10
+#define REG_3F40_DP_ENC_P0_3 0x1f40
+#define REG_3F44_DP_ENC_P0_3 0x1f44
+#define ENC_PHY_PWR_STATE_OVERWRITE_MASK GENMASK(4, 3)
+#define ENC_PHY_ALL_PWR_OFF 0
+#define ENC_PHY_BIAS_PWR_ON 1
+#define ENC_PHY_BIAS_PLL_PWR_ON 2
+#define ENC_PHY_ALL_PWR_ON 3
+#define ENC_PHY_PWR_OVERWRITE_EN BIT(2)
+#define REG_3F80_DP_ENC_P0_3 0x1f80
+#define PSR_PATGEN_AVT_EN_FLDMASK 0x20
+#define REG_3FF8_DP_ENC_P0_3 0x1ff8
+#define ENC_PHY_STATE_RESET_ALL_MASK GENMASK(7, 0)
+#define PHY_STATE_W_1_DP_ENC_P0_3 BIT(6)
+#define DP_ENCODER_DVO_ON_W_1 BIT(5)
+#define DP_ENCODER_PSR_XTAL_FREQ_MHZ_MASK GENMASK(13, 9)
+
/* offset: SEC_OFFSET (0x2000) */
#define SEC_OFFSET 0x2000
--
2.54.0
^ permalink raw reply related
* Re: [RFC 0/2] arm64: kprobes: Fix single-step fault and reentry handling
From: Masami Hiramatsu @ 2026-07-01 13:43 UTC (permalink / raw)
To: Pu Hu
Cc: Hongyan Xia, Jiazi Li, catalin.marinas@arm.com, naveen@kernel.org,
linux-kernel@vger.kernel.org, yang@os.amperecomputing.com,
will@kernel.org, davem@davemloft.net,
linux-arm-kernel@lists.infradead.org,
linux-trace-kernel@vger.kernel.org
In-Reply-To: <20260701121448.3926-1-hupu@transsion.com>
On Wed, 1 Jul 2026 12:14:54 +0000
Pu Hu <hupu@transsion.com> wrote:
> From: hupu <hupu@transsion.com>
>
> This series fixes two arm64 kprobes issues observed when running
> simpleperf with preemptirq tracepoints and dwarf callchains while a
> kprobe is active on a frequently executed kernel function.
>
> The crash happens in the kprobe debug exception path. While a kprobe is
> preparing or executing its XOL single-step instruction, perf/trace code
> can run in the same window. That code may either take a fault of its own
> or hit another kprobe.
>
> Patch 1 makes kprobe_fault_handler() handle a fault in
> KPROBE_HIT_SS/KPROBE_REENTER only when the faulting PC points at the
> current kprobe's XOL instruction. Otherwise the fault is left to the
> normal fault handling path.
>
> Patch 2 allows a kprobe hit in KPROBE_HIT_SS to be handled as a
> recoverable one-level reentry. Only a hit while already in
> KPROBE_REENTER remains unrecoverable.
>
> This follows the same logic as the existing x86 fixes:
> 6381c24cd6d5 ("kprobes/x86: Fix page-fault handling logic")
> 6a5022a56ac3 ("kprobes/x86: Allow to handle reentered kprobe on single-stepping")
Good catch!!
The series looks good to me.
Acked-by: Masami Hiramatsu (Google) <mhiramat@kernel.org>
But it should be reviewed by arm64 maintainers too.
BTW, if you are "Pu Hu", the Signed-off-by tag should be
"Pu Hu <...>" instead of "hupu <...>".
Thank you,
>
> Reproducer:
>
> simpleperf record -p <pid> -f 10000 \
> -e preemptirq:preempt_disable \
> -e preemptirq:preempt_enable \
> --duration 9 --call-graph dwarf \
> -o /data/local/tmp/perf.data
>
> Before this series, the crash reproduced frequently. With both patches
> applied, it was no longer reproduced in our testing.
>
> hupu (2):
> arm64: kprobes: Do not handle non-XOL faults as kprobe faults
> arm64: kprobes: Allow reentering kprobes while single-stepping
>
> arch/arm64/kernel/probes/kprobes.c | 22 +++++++++++++++++++++-
> 1 file changed, 21 insertions(+), 1 deletion(-)
>
> --
> 2.43.0
>
>
--
Masami Hiramatsu (Google) <mhiramat@kernel.org>
^ permalink raw reply
* [PATCH 16/42] drm/mediatek: mtk_crtc: Minimize spinlocked time in cmdq callback
From: AngeloGioacchino Del Regno @ 2026-07-01 12:20 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard, tzimmermann,
robh, krzk+dt, conor+dt, matthias.bgg, angelogioacchino.delregno,
dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, justin.yeh, jason-jh.lin, kernel
In-Reply-To: <20260701122057.19648-1-angelogioacchino.delregno@collabora.com>
In ddp_cmdq_cb (the CMDQ mailbox callback), the config_lock spin
lock is being locked to read the config_updating variable in the
mtk_crtc structure, as, if configuration is updating, the callback
function shall not run (or shall run at a later time).
It is therefore unnecessary to keep the spinlock until the end of
the function, in case pending config, planes, or async planes
bools need to be updated.
Though the cmdq callback is not a performance path in this case,
this may be running for each frame that is pushed to the display,
so from 30 (or less) up to 144 times (or more) per second.
Add a temporary "cfg_updating" variable to aid with readability,
and unlock the spinlock as soon as the config_updating variable
read operation is done as a micro-optimization.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_crtc.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_crtc.c b/drivers/gpu/drm/mediatek/mtk_crtc.c
index e543fae9c580..35e78ece899a 100644
--- a/drivers/gpu/drm/mediatek/mtk_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_crtc.c
@@ -287,6 +287,7 @@ static void ddp_cmdq_cb(struct mbox_client *cl, void *mssg)
struct mtk_crtc_state *state;
unsigned int i;
unsigned long flags;
+ bool cfg_updating;
/* release GCE HW usage and start autosuspend */
pm_runtime_mark_last_busy(cmdq_cl->chan->mbox->dev);
@@ -298,7 +299,10 @@ static void ddp_cmdq_cb(struct mbox_client *cl, void *mssg)
state = to_mtk_crtc_state(mtk_crtc->base.state);
spin_lock_irqsave(&mtk_crtc->config_lock, flags);
- if (mtk_crtc->config_updating)
+ cfg_updating = mtk_crtc->config_updating;
+ spin_unlock_irqrestore(&mtk_crtc->config_lock, flags);
+
+ if (cfg_updating)
goto ddp_cmdq_cb_out;
state->pending_config = false;
@@ -328,14 +332,11 @@ static void ddp_cmdq_cb(struct mbox_client *cl, void *mssg)
}
ddp_cmdq_cb_out:
-
if (mtk_crtc->pending_needs_vblank) {
mtk_crtc_finish_page_flip(mtk_crtc);
mtk_crtc->pending_needs_vblank = false;
}
- spin_unlock_irqrestore(&mtk_crtc->config_lock, flags);
-
mtk_crtc->cmdq_vblank_cnt = 0;
wake_up(&mtk_crtc->cb_blocking_queue);
}
--
2.54.0
^ permalink raw reply related
* Re: [PATCH rc v7 0/7] iommu/arm-smmu-v3: Fix device crash on kdump kernel
From: Pranjal Shrivastava @ 2026-07-01 13:36 UTC (permalink / raw)
To: Mostafa Saleh
Cc: Jason Gunthorpe, Nicolin Chen, will, robin.murphy, joro, kees,
baolu.lu, kevin.tian, miko.lenczewski, linux-arm-kernel, iommu,
linux-kernel, stable, jamien
In-Reply-To: <akUQj2pa1W-MekgF@google.com>
On Wed, Jul 01, 2026 at 01:05:19PM +0000, Mostafa Saleh wrote:
> On Tue, Jun 30, 2026 at 03:59:42PM -0300, Jason Gunthorpe wrote:
> > On Tue, Jun 30, 2026 at 03:33:12PM +0000, Mostafa Saleh wrote:
> >
> > > For example patch#1 verifies log2size and split and both are read
> > > from HW registers. Same for the base address or other addresses as
> > > the page tables, they might be corrupted due to a buggy driver.
> > > My point is that, it is really hard to assume that the previous state
> > > of registers/STE/page-tables were valid or even consistent, when the
> > > kernel crashed and did not transition the state gracefully.
> >
> > Sure, and this mechanism is probably not very useful for debugging
> > these kinds of errors in the SMMU driver. Oh well, that isn't a common
> > source of kernel crashes :)
>
> I hope not! Although memory corruption can happen due to many other
> reasons :/
>
> I am not trying to bikeshed, but I wondering if there is a more
> reliable way rather than doing archaeology from a panicked kernel
> SMMUv3 configuration, as I am worried that will be even harder to
> debug if it goes wrong.
>
> >
> > > Similarly for TLBs, the kernel might have panicked in the middle of an
> > > unmap or free domain. (not to mention what that means for RPM where
> > > a device reset with unknown TLBs)
> >
> > TLB is fine. kdump works by carving out a chunk of memory for the
> > future crash kernel. When the kernel boots it ignores all the memory
> > used by the prior kernel. So DMA can keep running into the old kernels
> > memory with no issue. It doesn't matter if the TLBs are inconsistent or
> > not.
>
> Ideally if a TLB is to be missed (because of the panic), it should not
> point to kdump memory as it is carved-out. However, it is still a leap to
> assume that the TLBs are in a good shape as I mentioned with RPM (or
> even if the device resets transiently for some reason) it can end up
> with garbage in its TLBs.
Regarding RPM, I can say that even if we panicked while SMMU was off in
the previous kernel, when we call device_reset() in the new kernel we
still issue the TLBI_ALL with the reset.
However, I agree with the overall problem, i.e. IF an active device
unmaps the DMA addr after the transaction in the previous kernel,
(with the SMMU powered ON) but the TLBI was missed due to a crash/panic,
Any new DMA in the new kernel may alias onto a memory in the previous
(crashed) kernel, not the kdump kernel.
That way, I agree that continuing DMA could be problematic as we may
corrupt the very memory we'd wanna analyze for a crash.
Thanks,
Praan
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