* [PATCH 2/7] arm64: dts: mediatek: mt8173: Add and use UART AP_DMA controller
From: AngeloGioacchino Del Regno @ 2026-07-01 12:19 UTC (permalink / raw)
To: linux-mediatek
Cc: robh, krzk+dt, conor+dt, matthias.bgg, angelogioacchino.delregno,
devicetree, linux-kernel, linux-arm-kernel, kernel, justin.yeh
In-Reply-To: <20260701121929.19374-1-angelogioacchino.delregno@collabora.com>
This SoC has a DMA controller (AP_DMA) that provides one channel
for each data direction (transmit and receive) for all of the
UART controllers in the SoC.
In order to increase the efficiency of data TX/RX over the UART
controllers, add the UART DMA controller and assign the right
channels to each of the four UART controllers.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 27 ++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 81ddb4eec48e..43159ae6da8f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -673,6 +673,25 @@ gic: interrupt-controller@10221000 {
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
+ apdma: dma-controller@11000300 {
+ compatible = "mediatek,mt8173-uart-dma", "mediatek,mt6577-uart-dma";
+ reg = <0 0x11000300 0 0x80>, <0 0x11000380 0 0x80>,
+ <0 0x11000400 0 0x80>, <0 0x11000480 0 0x80>,
+ <0 0x11000500 0 0x80>, <0 0x11000580 0 0x80>,
+ <0 0x11000600 0 0x80>, <0 0x11000680 0 0x80>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_AP_DMA>;
+ #dma-cells = <1>;
+ dma-requests = <8>;
+ };
+
auxadc: auxadc@11001000 {
compatible = "mediatek,mt8173-auxadc";
reg = <0 0x11001000 0 0x1000>;
@@ -688,6 +707,8 @@ uart0: serial@11002000 {
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
clock-names = "baud", "bus";
+ dmas = <&apdma 0>, <&apdma 1>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -698,6 +719,8 @@ uart1: serial@11003000 {
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
clock-names = "baud", "bus";
+ dmas = <&apdma 2>, <&apdma 3>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -708,6 +731,8 @@ uart2: serial@11004000 {
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
clock-names = "baud", "bus";
+ dmas = <&apdma 4>, <&apdma 5>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -718,6 +743,8 @@ uart3: serial@11005000 {
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
clock-names = "baud", "bus";
+ dmas = <&apdma 6>, <&apdma 7>;
+ dma-names = "tx", "rx";
status = "disabled";
};
--
2.54.0
^ permalink raw reply related
* Re: [for-next][PATCH 04/15] tracepoint: Add lockdep rcu_is_watching() check to trace_##name##_enabled()
From: Steven Rostedt @ 2026-07-01 17:11 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: David Carlier, linux-kernel, Masami Hiramatsu, Mark Rutland,
Mathieu Desnoyers, Andrew Morton, Vineeth Pillai (Google),
Peter Zijlstra, Linux ARM, Linux-Renesas
In-Reply-To: <CAMuHMdUdsTHCMnitVEHdZvRFe9xgmLLTjSr=QqvOi0dxFjkTEA@mail.gmail.com>
On Wed, 1 Jul 2026 11:24:31 +0200
Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> Thanks, it does not trigger with the commit reverted and the "echo 1 > ...".
Ah found the issue;
#define trace(point, args) \
do { \
if (trace_##point##_enabled()) { \
bool exit_rcu = false; \
if (in_nmi()) \
break; \
if (!IS_ENABLED(CONFIG_TINY_RCU) && \
is_idle_task(current)) { \
ct_irq_enter(); \
exit_rcu = true; \
} \
trace_##point(args); \
if (exit_rcu) \
ct_irq_exit(); \
} \
} while (0)
#endif
The code within the enabled() call checks if RCU is watching, and if
not, it makes it watch. So yeah, this is a special case.
The following patch should fix the issue:
diff --git a/include/linux/tracepoint.h b/include/linux/tracepoint.h
index 4a0c36f40fe2..e0d838c9ce93 100644
--- a/include/linux/tracepoint.h
+++ b/include/linux/tracepoint.h
@@ -292,13 +292,18 @@ static inline struct tracepoint *tracepoint_ptr_deref(tracepoint_ptr_t *p)
{ \
} \
static inline bool \
+ __trace_##name##_enabled(void) \
+ { \
+ return static_branch_unlikely(&__tracepoint_##name.key);\
+ } \
+ static inline bool \
trace_##name##_enabled(void) \
{ \
if (IS_ENABLED(CONFIG_LOCKDEP)) { \
WARN_ONCE(!rcu_is_watching(), \
"RCU not watching for tracepoint"); \
} \
- return static_branch_unlikely(&__tracepoint_##name.key);\
+ return __trace_##name##_enabled(); \
}
#define __DECLARE_TRACE(name, proto, args, cond, data_proto) \
@@ -457,6 +462,11 @@ static inline struct tracepoint *tracepoint_ptr_deref(tracepoint_ptr_t *p)
{ \
} \
static inline bool \
+ __trace_##name##_enabled(void) \
+ { \
+ return false; \
+ } \
+ static inline bool \
trace_##name##_enabled(void) \
{ \
return false; \
diff --git a/kernel/trace/trace_preemptirq.c b/kernel/trace/trace_preemptirq.c
index 0c42b15c3800..b63e3558948f 100644
--- a/kernel/trace/trace_preemptirq.c
+++ b/kernel/trace/trace_preemptirq.c
@@ -30,7 +30,7 @@
#else
#define trace(point, args) \
do { \
- if (trace_##point##_enabled()) { \
+ if (__trace_##point##_enabled()) { \
bool exit_rcu = false; \
if (in_nmi()) \
break; \
^ permalink raw reply related
* [PATCH 06/42] drm/mediatek: Use hashtable for components discovery and registration
From: AngeloGioacchino Del Regno @ 2026-07-01 12:20 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard, tzimmermann,
robh, krzk+dt, conor+dt, matthias.bgg, angelogioacchino.delregno,
dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, justin.yeh, jason-jh.lin, kernel
In-Reply-To: <20260701122057.19648-1-angelogioacchino.delregno@collabora.com>
As a preparation for refactoring the concept of hardware component
identification, search, and final usage, remove the ddp_comp array
of components and replace it with a hashtable, indexed by ID.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_crtc.c | 44 ++++++++++++++++-------
drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 48 ++++++++++++++++++-------
drivers/gpu/drm/mediatek/mtk_ddp_comp.h | 23 +++++++++++-
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 7 ++--
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 2 +-
5 files changed, 94 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_crtc.c b/drivers/gpu/drm/mediatek/mtk_crtc.c
index f39f197057a7..3f4d6ab1bfc2 100644
--- a/drivers/gpu/drm/mediatek/mtk_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_crtc.c
@@ -725,8 +725,12 @@ static void mtk_crtc_update_output(struct drm_crtc *crtc,
crtc_state->connectors_changed, encoder_mask, crtc_index);
for (i = 0; i < mtk_crtc->num_conn_routes; i++) {
- unsigned int comp_id = mtk_crtc->conn_routes[i].route_ddp;
- struct mtk_ddp_comp *comp = &priv->ddp_comp[comp_id];
+ const struct mtk_drm_route *conn_route = &mtk_crtc->conn_routes[i];
+ struct mtk_ddp_comp *comp;
+
+ comp = mtk_ddp_comp_find_by_id(&priv->hlist, conn_route->route_ddp);
+ if (!comp)
+ continue;
if (comp->encoder_index >= 0 &&
(encoder_mask & BIT(comp->encoder_index))) {
@@ -1028,10 +1032,11 @@ int mtk_crtc_create(struct drm_device *drm_dev, const unsigned int *path,
{
struct mtk_drm_private *priv = drm_dev->dev_private;
struct device *dev = drm_dev->dev;
+ struct mtk_ddp_comp *dma_comp;
struct mtk_crtc *mtk_crtc;
unsigned int num_comp_planes = 0;
int ret;
- int i;
+ int i, j;
bool has_ctm = false;
uint gamma_lut_size = 0;
struct drm_crtc *tmp;
@@ -1051,7 +1056,7 @@ int mtk_crtc_create(struct drm_device *drm_dev, const unsigned int *path,
struct mtk_ddp_comp *comp;
node = priv->comp_node[comp_id];
- comp = &priv->ddp_comp[comp_id];
+ comp = mtk_ddp_comp_find_by_id(&priv->hlist, comp_id);
/* Not all drm components have a DTS device node, such as ovl_adaptor,
* which is the drm bring up sub driver
@@ -1063,7 +1068,7 @@ int mtk_crtc_create(struct drm_device *drm_dev, const unsigned int *path,
return 0;
}
- if (!comp->dev) {
+ if (!comp || !comp->dev) {
dev_err(dev, "Component %pOF not initialized\n", node);
return -ENODEV;
}
@@ -1089,12 +1094,17 @@ int mtk_crtc_create(struct drm_device *drm_dev, const unsigned int *path,
return ret;
}
- for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
+ for (i = 0, j = 0; i < mtk_crtc->ddp_comp_nr; i++, j++) {
unsigned int comp_id = path[i];
struct mtk_ddp_comp *comp;
- comp = &priv->ddp_comp[comp_id];
- mtk_crtc->ddp_comp[i] = comp;
+ comp = mtk_ddp_comp_find_by_id(&priv->hlist, comp_id);
+ if (!comp) {
+ j--;
+ dev_dbg(dev, "Cannot find component %d.\n", comp_id);
+ continue;
+ }
+ mtk_crtc->ddp_comp[j] = comp;
if (comp->funcs) {
if (comp->funcs->gamma_set && comp->funcs->gamma_get_lut_size) {
@@ -1131,7 +1141,14 @@ int mtk_crtc_create(struct drm_device *drm_dev, const unsigned int *path,
* In the case of ovl_adaptor sub driver, it needs to use the
* dma_dev_get function to get representative dma dev.
*/
- mtk_crtc->dma_dev = mtk_ddp_comp_dma_dev_get(&priv->ddp_comp[path[0]]);
+ dma_comp = mtk_ddp_comp_find_by_id(&priv->hlist, path[0]);
+ if (dma_comp == NULL) {
+ dev_err(dev, "Could not find appropriate DMA device!\n");
+ return -EINVAL;
+ }
+
+ mtk_crtc->dma_dev = mtk_ddp_comp_dma_dev_get(dma_comp);
+ dev_dbg(dev, "Using DMA device %pOF\n", mtk_crtc->dma_dev->of_node);
ret = mtk_crtc_init(drm_dev, mtk_crtc, crtc_i);
if (ret < 0)
@@ -1188,17 +1205,18 @@ int mtk_crtc_create(struct drm_device *drm_dev, const unsigned int *path,
for (i = 0; i < num_conn_routes; i++) {
unsigned int comp_id = conn_routes[i].route_ddp;
struct device_node *node = priv->comp_node[comp_id];
- struct mtk_ddp_comp *comp = &priv->ddp_comp[comp_id];
+ struct mtk_ddp_comp *comp = mtk_ddp_comp_find_by_id(&priv->hlist, comp_id);
- if (!comp->dev) {
+ if (!comp || !comp->dev) {
dev_dbg(dev, "comp_id:%d, Component %pOF not initialized\n",
comp_id, node);
/* mark encoder_index to -1, if route comp device is not enabled */
- comp->encoder_index = -1;
+ if (comp)
+ comp->encoder_index = -1;
continue;
}
- mtk_ddp_comp_encoder_index_set(&priv->ddp_comp[comp_id]);
+ mtk_ddp_comp_encoder_index_set(comp);
}
mtk_crtc->num_conn_routes = num_conn_routes;
diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
index a6c1815ffa39..d716fd9f8a70 100644
--- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
@@ -480,10 +480,24 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_DRM_ID_MAX]
[DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, &ddp_wdma },
};
+static bool mtk_ddp_find_comp_dev_in_table(const struct mtk_drm_comp_list *hlist,
+ const unsigned int comp_id,
+ struct device *dev)
+{
+ struct mtk_ddp_comp *ddp_comp;
+
+ hash_for_each_possible(hlist->ddp_list, ddp_comp, lnode, comp_id) {
+ if (ddp_comp->dev == dev)
+ return true;
+ }
+
+ return false;
+}
+
static bool mtk_ddp_comp_find(struct device *dev,
const unsigned int *path,
unsigned int path_len,
- struct mtk_ddp_comp *ddp_comp)
+ const struct mtk_drm_comp_list *hlist)
{
unsigned int i;
@@ -491,7 +505,7 @@ static bool mtk_ddp_comp_find(struct device *dev,
return false;
for (i = 0U; i < path_len; i++)
- if (dev == ddp_comp[path[i]].dev)
+ if (mtk_ddp_find_comp_dev_in_table(hlist, path[i], dev))
return true;
return false;
@@ -500,7 +514,7 @@ static bool mtk_ddp_comp_find(struct device *dev,
static int mtk_ddp_comp_find_in_route(struct device *dev,
const struct mtk_drm_route *routes,
unsigned int num_routes,
- struct mtk_ddp_comp *ddp_comp)
+ const struct mtk_drm_comp_list *hlist)
{
unsigned int i;
@@ -508,7 +522,7 @@ static int mtk_ddp_comp_find_in_route(struct device *dev,
return -EINVAL;
for (i = 0; i < num_routes; i++)
- if (dev == ddp_comp[routes[i].route_ddp].dev)
+ if (mtk_ddp_find_comp_dev_in_table(hlist, routes[i].route_ddp, dev))
return BIT(routes[i].crtc_id);
return -ENODEV;
@@ -566,7 +580,7 @@ int mtk_find_possible_crtcs(struct drm_device *drm, struct device *dev)
priv_n->comp_node)) {
if (mtk_ddp_comp_find(dev, data->main_path,
data->main_len,
- priv_n->ddp_comp))
+ &priv_n->hlist))
return BIT(i);
i++;
}
@@ -575,7 +589,7 @@ int mtk_find_possible_crtcs(struct drm_device *drm, struct device *dev)
priv_n->comp_node)) {
if (mtk_ddp_comp_find(dev, data->ext_path,
data->ext_len,
- priv_n->ddp_comp))
+ &priv_n->hlist))
return BIT(i);
i++;
}
@@ -584,7 +598,7 @@ int mtk_find_possible_crtcs(struct drm_device *drm, struct device *dev)
priv_n->comp_node)) {
if (mtk_ddp_comp_find(dev, data->third_path,
data->third_len,
- priv_n->ddp_comp))
+ &priv_n->hlist))
return BIT(i);
i++;
}
@@ -593,7 +607,7 @@ int mtk_find_possible_crtcs(struct drm_device *drm, struct device *dev)
ret = mtk_ddp_comp_find_in_route(dev,
private->data->conn_routes,
private->data->num_conn_routes,
- private->ddp_comp);
+ &private->hlist);
if (ret < 0)
DRM_INFO("Failed to find comp in ddp table, ret = %d\n", ret);
@@ -615,10 +629,12 @@ static void mtk_ddp_comp_clk_put(void *_clk)
clk_put(clk);
}
-int mtk_ddp_comp_init(struct device *dev, struct device_node *node, struct mtk_ddp_comp *comp,
+int mtk_ddp_comp_init(struct device *dev, struct device_node *node,
+ struct mtk_drm_comp_list *hlist,
unsigned int comp_id)
{
struct platform_device *comp_pdev;
+ struct mtk_ddp_comp *comp;
enum mtk_ddp_comp_type type;
struct mtk_ddp_comp_dev *priv;
int ret;
@@ -626,6 +642,10 @@ int mtk_ddp_comp_init(struct device *dev, struct device_node *node, struct mtk_d
if (comp_id >= DDP_COMPONENT_DRM_ID_MAX)
return -EINVAL;
+ comp = devm_kzalloc(dev, sizeof(*comp), GFP_KERNEL);
+ if (!comp)
+ return -ENOMEM;
+
type = mtk_ddp_matches[comp_id].type;
comp->id = comp_id;
@@ -633,8 +653,10 @@ int mtk_ddp_comp_init(struct device *dev, struct device_node *node, struct mtk_d
/* Not all drm components have a DTS device node, such as ovl_adaptor,
* which is the drm bring up sub driver
*/
- if (!node)
- return 0;
+ if (!node) {
+ comp->dev = dev;
+ goto end;
+ }
comp_pdev = of_find_device_by_node(node);
if (!comp_pdev) {
@@ -662,7 +684,7 @@ int mtk_ddp_comp_init(struct device *dev, struct device_node *node, struct mtk_d
type == MTK_DISP_DPI ||
type == MTK_DISP_DP_INTF ||
type == MTK_DISP_DSI)
- return 0;
+ goto end;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
@@ -687,6 +709,8 @@ int mtk_ddp_comp_init(struct device *dev, struct device_node *node, struct mtk_d
#endif
platform_set_drvdata(comp_pdev, priv);
+end:
+ hash_add(hlist->ddp_list, &comp->lnode, comp->id);
return 0;
}
diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
index bbc66072fe6b..4203eecb2a7b 100644
--- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h
@@ -6,6 +6,7 @@
#ifndef MTK_DDP_COMP_H
#define MTK_DDP_COMP_H
+#include <linux/hashtable.h>
#include <linux/io.h>
#include <linux/pm_runtime.h>
#include <linux/soc/mediatek/mtk-cmdq.h>
@@ -24,6 +25,11 @@ struct drm_dsc_config;
struct mtk_ddp_comp;
struct cmdq_pkt;
+
+struct mtk_drm_comp_list {
+ DECLARE_HASHTABLE(ddp_list, 8);
+};
+
struct mtk_ddp_comp_funcs {
int (*power_on)(struct device *dev);
void (*power_off)(struct device *dev);
@@ -75,6 +81,8 @@ struct mtk_ddp_comp {
unsigned int id;
int encoder_index;
const struct mtk_ddp_comp_funcs *funcs;
+
+ struct hlist_node lnode;
};
static inline int mtk_ddp_comp_power_on(struct mtk_ddp_comp *comp)
@@ -331,10 +339,23 @@ static inline void mtk_ddp_comp_encoder_index_set(struct mtk_ddp_comp *comp)
comp->encoder_index = (int)comp->funcs->encoder_index(comp->dev);
}
+static inline struct mtk_ddp_comp
+*mtk_ddp_comp_find_by_id(struct mtk_drm_comp_list *hlist,
+ const unsigned int id)
+{
+ struct mtk_ddp_comp *ddp_comp;
+
+ hash_for_each_possible(hlist->ddp_list, ddp_comp, lnode, id)
+ return ddp_comp;
+
+ return NULL;
+}
+
int mtk_ddp_comp_get_id(struct device_node *node,
enum mtk_ddp_comp_type comp_type);
int mtk_find_possible_crtcs(struct drm_device *drm, struct device *dev);
-int mtk_ddp_comp_init(struct device *dev, struct device_node *comp_node, struct mtk_ddp_comp *comp,
+int mtk_ddp_comp_init(struct device *dev, struct device_node *node,
+ struct mtk_drm_comp_list *hlist,
unsigned int comp_id);
enum mtk_ddp_comp_type mtk_ddp_comp_get_type(unsigned int comp_id);
void mtk_ddp_write(struct cmdq_pkt *cmdq_pkt, unsigned int value,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 9c6dfc1e384b..e956e1966b86 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -1086,6 +1086,8 @@ static int mtk_drm_probe(struct platform_device *pdev)
if (!mtk_drm_data)
return -EINVAL;
+ hash_init(private->hlist.ddp_list);
+
/* Try to build the display pipeline from devicetree graphs */
if (of_graph_is_present(phandle)) {
dev_dbg(dev, "Building display pipeline for MMSYS %u\n",
@@ -1116,8 +1118,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
PLATFORM_DEVID_AUTO,
(void *)private->mmsys_dev,
sizeof(*private->mmsys_dev));
- private->ddp_comp[DDP_COMPONENT_DRM_OVL_ADAPTOR].dev = &ovl_adaptor->dev;
- mtk_ddp_comp_init(dev, NULL, &private->ddp_comp[DDP_COMPONENT_DRM_OVL_ADAPTOR],
+ mtk_ddp_comp_init(&ovl_adaptor->dev, NULL, &private->hlist,
DDP_COMPONENT_DRM_OVL_ADAPTOR);
component_match_add(dev, &match, compare_dev, &ovl_adaptor->dev);
}
@@ -1185,7 +1186,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
node);
}
- ret = mtk_ddp_comp_init(dev, node, &private->ddp_comp[comp_id], comp_id);
+ ret = mtk_ddp_comp_init(dev, node, &private->hlist, comp_id);
if (ret) {
of_node_put(node);
goto err_node;
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 8b5c51d93f72..a171126d580e 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -60,8 +60,8 @@ struct mtk_drm_private {
struct device_node *mutex_node;
struct device *mutex_dev;
struct device *mmsys_dev;
+ struct mtk_drm_comp_list hlist;
struct device_node *comp_node[DDP_COMPONENT_DRM_ID_MAX];
- struct mtk_ddp_comp ddp_comp[DDP_COMPONENT_DRM_ID_MAX];
struct mtk_mmsys_driver_data *data;
struct drm_atomic_commit *suspend_state;
unsigned int mbox_index;
--
2.54.0
^ permalink raw reply related
* Re: [PATCH] drm/mxsfb/lcdif: don't hide lcdif_attach_bridge() deferral messages
From: Luca Ceresoli @ 2026-07-01 17:19 UTC (permalink / raw)
To: Marek Vasut, Stefan Agner, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, David Airlie, Simona Vetter, Frank Li,
Sascha Hauer, Pengutronix Kernel Team, Fabio Estevam,
Luca Ceresoli
Cc: Hui Pu, Ian Ray, Thomas Petazzoni, dri-devel, imx,
linux-arm-kernel, linux-kernel
In-Reply-To: <20260619-drm-lcdif-deferral-msg-v1-1-ce2392dca985@bootlin.com>
On Fri, 19 Jun 2026 09:02:13 +0200, Luca Ceresoli wrote:
> lcdif_attach_bridge() uses dev_err_probe() on all its error returns to
> store a specific deferral message.
>
> However its caller lcdif_load() calls dev_err_probe() again on error,
> overwriting the specific deferral messages with a unique, unavoidably
> generic, message.
>
> [...]
Applied, thanks!
[1/1] drm/mxsfb/lcdif: don't hide lcdif_attach_bridge() deferral messages
commit: cff96362794a5c1f3adb013b4a46c7233149a629
Best regards,
--
Luca Ceresoli, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply
* Re: [PATCH RFC v5 00/12] ZTE zx297520v3 clock bindings and driver
From: Stefan Dösinger @ 2026-07-01 17:22 UTC (permalink / raw)
To: Conor Dooley
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Brian Masney, linux-clk, devicetree,
linux-kernel, linux-arm-kernel
In-Reply-To: <20260629-unwelcome-raking-3df3d8ff0422@spud>
[-- Attachment #1: Type: text/plain, Size: 1708 bytes --]
Am Montag, 29. Juni 2026, 18:49:08 Ostafrikanische Zeit schrieb Conor Dooley:
> Bindings seem fine to me, I'll be happy to give you some r-b tags when
> you go non-RFC. To be frank, I think you should drop them as you've got
> no significant questions here I think and you'll be taken a bt more
> seriously.
Thanks for all the advice so far!
Here's one more binding related question: Philipp's request to give the PHY
reset its own reset ID means I need a node and driver to consume that reset.
My question is if it should be another MFD subdevice of topcrm or not. I am
leaning towards not:
usb_phy: phy@2 {
compatible = "zte,zx29-usb2-phy";
interrupts = <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>, <GIC_SPI 43
IRQ_TYPE_EDGE_RISING>;
interrupt-names = "powerup", "powerdown";
syscon = <&topcrm 0x84 0x2>;
resets = <&topcrm ZX297520V3_USB_PHY_RESET>;
reset-names = "phy";
#phy-cells = <0>;
};
usb0: usb@1500000 {
compatible = "snps,dwc2";
reg = <0x01500000 0x1000>;
...
phys = <&usb_phy>;
phy-names = "usb2-phy";
};
I am not aware of any IO region to configure the PHY, although one may exist.
topcrm + 0x84 has two status bits reporting if USB and HSIC are powered and
out of reset. Nevertheless, the PHY feels distinct enough from topcrm that it
should have its own binding. The phy driver would merely deassert the reset
and wait for the ready bit and maybe in the future do something useful with
the connect/disconnect IRQs.
Interestingly the USB IO region is actually downstream of the AHB bus and
matrix controller, but it has its clocks and resets in topcrm. I suspect the
purpose of this setup is to allow wake-by-USB IRQs while shutting down the
main data path.
Cheers,
Stefan
[-- Attachment #2: This is a digitally signed message part. --]
[-- Type: application/pgp-signature, Size: 870 bytes --]
^ permalink raw reply
* [PATCH 03/11] drm/mediatek: mtk_dp: Fix hdmi codec and phy driver unregistration
From: AngeloGioacchino Del Regno @ 2026-07-01 12:20 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard, tzimmermann,
robh, krzk+dt, conor+dt, matthias.bgg, angelogioacchino.delregno,
jitao.shi, granquet, rex-bc.chen, dmitry.osipenko, ck.hu,
amergnat, justin.yeh, jason-jh.lin, dri-devel, linux-mediatek,
devicetree, linux-kernel, linux-arm-kernel, kernel
In-Reply-To: <20260701122024.19557-1-angelogioacchino.delregno@collabora.com>
During probe, this driver is registering two platform devices: one
for the HDMI Codec driver and one for the DisplayPort PHY driver.
In the probe function, none of the error cases are unregistering
any of the two platform devices and this may cause registration
of multiple instances of those in case this driver returns one or
more probe deferral(s) in the "wrong" spots.
In order to fix this, add devm actions to unregister those and
remove the manual calls to platform_device_unregister in the
mtk_dp_remove() function, as those would otherwise be redundant.
Fixes: e71a8ebbe086 ("drm/mediatek: dp: Audio support for MT8195")
Fixes: caf2ae486742 ("drm/mediatek: dp: Add support for embedded DisplayPort aux-bus")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_dp.c | 30 ++++++++++++++++++++++++++----
1 file changed, 26 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/mtk_dp.c
index eefbc7e0f9c8..2c738c16dafa 100644
--- a/drivers/gpu/drm/mediatek/mtk_dp.c
+++ b/drivers/gpu/drm/mediatek/mtk_dp.c
@@ -2670,6 +2670,13 @@ static const struct hdmi_codec_ops mtk_dp_audio_codec_ops = {
.hook_plugged_cb = mtk_dp_audio_hook_plugged_cb,
};
+static void mtk_dp_unregister_pdevs(void *data)
+{
+ struct platform_device *ext_pdev = data;
+
+ platform_device_unregister(ext_pdev);
+}
+
static int mtk_dp_register_audio_driver(struct device *dev)
{
struct mtk_dp *mtk_dp = dev_get_drvdata(dev);
@@ -2680,18 +2687,29 @@ static int mtk_dp_register_audio_driver(struct device *dev)
.data = mtk_dp,
.no_capture_mute = 1,
};
+ int ret;
mtk_dp->audio_pdev = platform_device_register_data(dev,
HDMI_CODEC_DRV_NAME,
PLATFORM_DEVID_AUTO,
&codec_data,
sizeof(codec_data));
- return PTR_ERR_OR_ZERO(mtk_dp->audio_pdev);
+ if (IS_ERR(mtk_dp->audio_pdev))
+ return PTR_ERR(mtk_dp->audio_pdev);
+
+ ret = devm_add_action_or_reset(dev, mtk_dp_unregister_pdevs, mtk_dp->phy_dev);
+ if (ret) {
+ platform_device_unregister(mtk_dp->audio_pdev);
+ return dev_err_probe(dev, ret,
+ "Failed to add codec unregister devm action");
+ }
+ return 0;
}
static int mtk_dp_register_phy(struct mtk_dp *mtk_dp)
{
struct device *dev = mtk_dp->dev;
+ int ret;
mtk_dp->phy_dev = platform_device_register_data(dev, "mediatek-dp-phy",
PLATFORM_DEVID_AUTO,
@@ -2701,6 +2719,13 @@ static int mtk_dp_register_phy(struct mtk_dp *mtk_dp)
return dev_err_probe(dev, PTR_ERR(mtk_dp->phy_dev),
"Failed to create device mediatek-dp-phy\n");
+ ret = devm_add_action_or_reset(dev, mtk_dp_unregister_pdevs, mtk_dp->phy_dev);
+ if (ret) {
+ platform_device_unregister(mtk_dp->phy_dev);
+ return dev_err_probe(dev, ret,
+ "Failed to add phy unregister devm action");
+ }
+
mtk_dp_get_calibration_data(mtk_dp);
mtk_dp->phy = devm_phy_get(&mtk_dp->phy_dev->dev, "dp");
@@ -2870,9 +2895,6 @@ static void mtk_dp_remove(struct platform_device *pdev)
pm_runtime_disable(&pdev->dev);
if (mtk_dp->data->bridge_type != DRM_MODE_CONNECTOR_eDP)
timer_delete_sync(&mtk_dp->debounce_timer);
- platform_device_unregister(mtk_dp->phy_dev);
- if (mtk_dp->audio_pdev)
- platform_device_unregister(mtk_dp->audio_pdev);
}
#ifdef CONFIG_PM_SLEEP
--
2.54.0
^ permalink raw reply related
* [PATCH 00/12] PHY: MediaTek DP PHY refactor and MT8196 eDP
From: AngeloGioacchino Del Regno @ 2026-07-01 12:19 UTC (permalink / raw)
To: chunfeng.yun
Cc: vkoul, neil.armstrong, robh, krzk+dt, conor+dt, matthias.bgg,
angelogioacchino.delregno, chunkuang.hu, p.zabel, justin.yeh,
linux-arm-kernel, linux-mediatek, linux-phy, devicetree,
linux-kernel, dri-devel, kernel
This series performs major refactoring on the MediaTek DisplayPort PHY
driver, makes it probe with devicetree instead of getting registered
by the mtk_dp DRM driver, adds power_on/off() callbacks, and honors
the phy configure opts' set_lanes and set_voltages for, respectively,
varying the number of lanes and setting the voltage pre-emphasis and
swing on the PHY, for each lane.
This driver now also properly gets the PHY (EYE) Calibration Data from
NVMEM (eFuse array) if provided, instead of getting it (improperly)
injected by the mtk_dp driver.
Additionally, all of the driving parameters calculations and most of
the other register definitions were refactored to greatly enhance the
human readability of this code.
As a last step, this also transfers the register offsets for both the
digital and analog phy registers in arrays assigned to soc specific
data, in an effort to both introduce support for new minor revisions
of the MediaTek DisplayPort PHY and to have a clearer view of the
register related differences between those (for example, it is easily
understandable that the analog part remained exactly the same between
MT8195 and MT8196, but the digital part gets a slight update).
Speaking of which, as a last step, this also adds support for the
MT8196 SoC (and its derivatives), which uses this PHY only for its
Embedded DisplayPort (eDP) IP (spoiler: the DP one seems to be way
too different and requiring an entirely new PHY driver).
In this state, this driver can also easily support the MT8189 SoC
with a few lines of code: even though I do have clean code to add
support for this one, I was not (*yet*) able to test it on upstream
based kernels, and for this reason I decided to leave that one out
for now (but it's coming later for sure).
NOTE!
Despite all the apparently breaking changes in the refactoring, full
compatibility with older MTK_DP driver and with old devicetrees was
retained and carefully tested on multiple platforms!
P.S.: I am aware of the BUILD_DRIVING_PARAM_0( 0, 2, 4, 7) checkpatch
warning and I didn't fix it in bigger favor of human readability.
AngeloGioacchino Del Regno (12):
dt-bindings: phy: Document MT8195 and MT8196 DisplayPort PHYs
phy: phy-mtk-dp: Rename regs to regmap in struct mtk_dp_phy
phy: phy-mtk-dp: Allow probing with devicetree match
phy: phy-mtk-dp: Migrate register offsets to SoC specific pdata
phy: phy-mtk-dp: Implement power_on and power_off PHY callbacks
phy: phy-mtk-dp: Support set_lanes in configure and properly cleanup
phy: phy-mtk-dp: Support setting volt swing and preemphasis values
phy: phy-mtk-dp: Add support for digital and analog calibration
phy: phy-mtk-dp: Rewrite and document default driving param macros
phy: phy-mtk-dp: Add bitrate register val definitions to SoC data
phy: phy-mtk-dp: Add PHYD Lane EN register mask to SoC data
phy: phy-mtk-dp: Add support for MT8196 eDP PHY
.../bindings/phy/mediatek,mt8195-dp-phy.yaml | 77 ++
drivers/phy/mediatek/phy-mtk-dp.c | 828 ++++++++++++++++--
2 files changed, 808 insertions(+), 97 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/mediatek,mt8195-dp-phy.yaml
--
2.54.0
^ permalink raw reply
* [PATCH 09/11] drm/mediatek: mtk_dp: Add support for HotPlug Detection in DP AUX
From: AngeloGioacchino Del Regno @ 2026-07-01 12:20 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard, tzimmermann,
robh, krzk+dt, conor+dt, matthias.bgg, angelogioacchino.delregno,
jitao.shi, granquet, rex-bc.chen, dmitry.osipenko, ck.hu,
amergnat, justin.yeh, jason-jh.lin, dri-devel, linux-mediatek,
devicetree, linux-kernel, linux-arm-kernel, kernel
In-Reply-To: <20260701122024.19557-1-angelogioacchino.delregno@collabora.com>
Newer MediaTek DisplayPort IPs can finally use the AUX to perform
hotplug detection (HPD) without having to power up the entire eDP
or DP IP (transmitter, encoder, etc).
Enable support for configuring and performing HPD in AUX and check
the correct HPD strategy with a new platform data variable.
This is done in preparation for adding support for the embedded
DisplayPort (eDP) IP found in the MT8196 SoC.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_dp.c | 96 ++++++++++++++++++++++++---
drivers/gpu/drm/mediatek/mtk_dp_reg.h | 18 +++++
2 files changed, 103 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/mtk_dp.c
index 5272e717bfda..2d58eacb3d3e 100644
--- a/drivers/gpu/drm/mediatek/mtk_dp.c
+++ b/drivers/gpu/drm/mediatek/mtk_dp.c
@@ -168,6 +168,7 @@ struct mtk_dp_data {
bool audio_pkt_in_hblank_area;
u16 audio_m_div2_bit;
u8 hw_max_link_rate;
+ bool aux_hpd_supported;
};
static const struct mtk_dp_efuse_fmt mt8188_dp_efuse_fmt[MTK_DP_CAL_MAX] = {
@@ -1046,7 +1047,21 @@ static u32 mtk_dp_swirq_get_clear(struct mtk_dp *mtk_dp)
return irq_status;
}
-static u32 mtk_dp_hwirq_get_clear(struct mtk_dp *mtk_dp)
+static u32 mtk_dp_aux_hwirq_get_clear(struct mtk_dp *mtk_dp)
+{
+ u32 irq_status = mtk_dp_read(mtk_dp, MTK_DP_AUX_TX_P0_INT_STA);
+
+ if (irq_status) {
+ mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_TX_P0_INT_CLR,
+ irq_status, irq_status);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_TX_P0_INT_CLR,
+ 0, irq_status);
+ }
+
+ return irq_status;
+}
+
+static u32 mtk_dp_trans_hwirq_get_clear(struct mtk_dp *mtk_dp)
{
u32 irq_status = (mtk_dp_read(mtk_dp, MTK_DP_TRANS_P0_3418) &
IRQ_STATUS_DP_TRANS_P0_MASK) >> 12;
@@ -1061,8 +1076,28 @@ static u32 mtk_dp_hwirq_get_clear(struct mtk_dp *mtk_dp)
return irq_status;
}
+static inline u32 mtk_dp_hwirq_get_clear(struct mtk_dp *mtk_dp)
+{
+ if (mtk_dp->data->aux_hpd_supported)
+ return mtk_dp_aux_hwirq_get_clear(mtk_dp);
+
+ return mtk_dp_trans_hwirq_get_clear(mtk_dp);
+}
+
static void mtk_dp_hwirq_enable(struct mtk_dp *mtk_dp, bool enable)
{
+ u32 mask, val;
+
+ /* Valid only for SoCs with working AUX HPD, this register is ignored on the others */
+ if (enable) {
+ mask = HPD_CONNECT_EVENT | HPD_INTERRUPT_EVENT | HPD_DISCONNECT_EVENT;
+ val = 0;
+ } else {
+ mask = DP_TX_AUX_INT_MASK;
+ val = DP_TX_AUX_INT_MASK;
+ }
+ mtk_dp_update_bits(mtk_dp, MTK_DP_TX_AUX_INT_MASKING, val, mask);
+
mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3418,
enable ? 0 :
IRQ_MASK_DP_TRANS_P0_DISC_IRQ |
@@ -1088,9 +1123,34 @@ static void mtk_dp_initialize_settings(struct mtk_dp *mtk_dp)
IRQ_MASK_AUX_TOP_IRQ, IRQ_MASK_AUX_TOP_IRQ);
}
+static void mtk_dp_initialize_aux_hpd_detect_settings(struct mtk_dp *mtk_dp)
+{
+ /* Set interrupt debounce threshold time */
+ mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_364C,
+ FIELD_PREP_CONST(HPD_INT_LOW_TIME_THD, 2) |
+ FIELD_PREP_CONST(HPD_INT_HIGH_TIME_THD, 6),
+ HPD_INT_LOW_TIME_THD | HPD_INT_HIGH_TIME_THD);
+
+ /* Connection detect threshold time: 1.5ms + (0.1 * (x)) ms*/
+ mtk_dp_update_bits(mtk_dp, MTK_DP_AUX_P0_367C,
+ FIELD_PREP(HPD_CONN_THD_DP_TX_AUX_MASK, 5),
+ HPD_CONN_THD_DP_TX_AUX_MASK);
+
+ /* Disconnection detect threshold and debounce time */
+ mtk_dp_write(mtk_dp, MTK_DP_AUX_P0_37A0,
+ FIELD_PREP_CONST(HPD_DISC_THD_AUX_TX, 5) |
+ FIELD_PREP_CONST(HPD_DISC_DEB_AUX_TX, 8));
+
+ /* Crystal frequency for 1us timing normalization: set to 26MHz */
+ mtk_dp_update_bits(mtk_dp, REG_366C_AUX_TX_P0,
+ FIELD_PREP_CONST(XTAL_FREQ_DP_TX_AUX_MASK, XTAL_FREQ_DP_TX_AUX_VAL),
+ XTAL_FREQ_DP_TX_AUX_MASK);
+}
+
static void mtk_dp_initialize_hpd_detect_settings(struct mtk_dp *mtk_dp)
{
u32 val;
+
/* Debounce threshold */
mtk_dp_update_bits(mtk_dp, MTK_DP_TRANS_P0_3410,
8, HPD_DEB_THD_DP_TRANS_P0_MASK);
@@ -2024,7 +2084,11 @@ static void mtk_dp_init_port(struct mtk_dp *mtk_dp)
mtk_dp_initialize_settings(mtk_dp);
mtk_dp_initialize_aux_settings(mtk_dp);
mtk_dp_initialize_digital_settings(mtk_dp);
- mtk_dp_initialize_hpd_detect_settings(mtk_dp);
+
+ if (mtk_dp->data->aux_hpd_supported)
+ mtk_dp_initialize_aux_hpd_detect_settings(mtk_dp);
+ else
+ mtk_dp_initialize_hpd_detect_settings(mtk_dp);
mtk_dp_digital_sw_reset(mtk_dp);
}
@@ -2091,6 +2155,7 @@ static irqreturn_t mtk_dp_hpd_event(int hpd, void *dev)
unsigned long flags;
u32 irq_status = mtk_dp_swirq_get_clear(mtk_dp) |
mtk_dp_hwirq_get_clear(mtk_dp);
+ u32 val;
if (!irq_status)
return IRQ_HANDLED;
@@ -2109,11 +2174,15 @@ static irqreturn_t mtk_dp_hpd_event(int hpd, void *dev)
spin_unlock_irqrestore(&mtk_dp->irq_thread_lock, flags);
if (cable_sta_chg) {
- if (!!(mtk_dp_read(mtk_dp, MTK_DP_TRANS_P0_3414) &
- HPD_DB_DP_TRANS_P0_MASK))
- mtk_dp->train_info.cable_plugged_in = true;
- else
- mtk_dp->train_info.cable_plugged_in = false;
+ if (mtk_dp->data->aux_hpd_supported) {
+ val = mtk_dp_read(mtk_dp, MTK_DP_AUX_P0_364C);
+ val &= HPD_STATUS_DP_AUX_TX_P0_MASK;
+ } else {
+ val = mtk_dp_read(mtk_dp, MTK_DP_TRANS_P0_3414);
+ val &= HPD_DB_DP_TRANS_P0_MASK;
+ }
+
+ mtk_dp->train_info.cable_plugged_in = val > 0;
}
return IRQ_WAKE_THREAD;
@@ -2125,10 +2194,15 @@ static int mtk_dp_wait_hpd_asserted(struct drm_dp_aux *mtk_aux, unsigned long wa
u32 val;
int ret;
- ret = regmap_read_poll_timeout(mtk_dp->regs,
- MTK_DP_TRANS_P0_3414 + mtk_dp->legacy_regoff,
- val, !!(val & HPD_DB_DP_TRANS_P0_MASK),
- wait_us / 100, wait_us);
+ if (mtk_dp->data->aux_hpd_supported)
+ ret = regmap_read_poll_timeout(mtk_dp->regs, MTK_DP_AUX_P0_364C,
+ val, !!(val & HPD_STATUS_DP_AUX_TX_P0_MASK),
+ wait_us / 100, wait_us);
+ else
+ ret = regmap_read_poll_timeout(mtk_dp->regs,
+ MTK_DP_TRANS_P0_3414 + mtk_dp->legacy_regoff,
+ val, !!(val & HPD_DB_DP_TRANS_P0_MASK),
+ wait_us / 100, wait_us);
if (ret) {
mtk_dp->train_info.cable_plugged_in = false;
return ret;
diff --git a/drivers/gpu/drm/mediatek/mtk_dp_reg.h b/drivers/gpu/drm/mediatek/mtk_dp_reg.h
index 616ea6440b08..5a3b3e2b4f49 100644
--- a/drivers/gpu/drm/mediatek/mtk_dp_reg.h
+++ b/drivers/gpu/drm/mediatek/mtk_dp_reg.h
@@ -276,6 +276,11 @@
#define DP_TRANS_DUMMY_RW_0_MASK GENMASK(3, 2)
/* offset: AUX_OFFSET (0x1600) */
+#define MTK_DP_AUX_TX_P0_INT_STA 0x1608
+#define HPD_CONNECT_EVENT BIT(0)
+#define HPD_INTERRUPT_EVENT BIT(2)
+#define HPD_DISCONNECT_EVENT BIT(10)
+#define DP_TX_AUX_INT_MASK GENMASK(15, 0)
#define MTK_DP_AUX_P0_360C 0x160c
#define AUX_TIMEOUT_THR_AUX_TX_P0_MASK GENMASK(12, 0)
#define AUX_TIMEOUT_THR_AUX_TX_P0_VAL 0x1595
@@ -323,6 +328,9 @@
#define MTK_DP_AUX_P0_3648 0x1648
#define MCU_REQUEST_ADDRESS_LSB_AUX_TX_P0_MASK GENMASK(15, 0)
#define MTK_DP_AUX_P0_364C 0x164c
+#define HPD_STATUS_DP_AUX_TX_P0_MASK BIT(15)
+#define HPD_INT_HIGH_TIME_THD GENMASK(9, 7)
+#define HPD_INT_LOW_TIME_THD GENMASK(6, 4)
#define MCU_REQUEST_ADDRESS_MSB_AUX_TX_P0_MASK GENMASK(3, 0)
#define MTK_DP_AUX_P0_3650 0x1650
#define MCU_REQ_DATA_NUM_AUX_TX_P0_MASK GENMASK(15, 12)
@@ -330,6 +338,13 @@
#define MCU_ACK_TRAN_COMPLETE_AUX_TX_P0 BIT(8)
#define MTK_DP_AUX_P0_3658 0x1658
#define AUX_TX_OV_EN_AUX_TX_P0_MASK BIT(0)
+#define MTK_DP_TX_AUX_INT_MASKING 0x1660
+#define MTK_DP_AUX_TX_P0_INT_CLR 0x1668
+#define REG_366C_AUX_TX_P0 0x166c
+#define XTAL_FREQ_DP_TX_AUX_VAL 0x68
+#define XTAL_FREQ_DP_TX_AUX_MASK GENMASK(15, 8)
+#define MTK_DP_AUX_P0_367C 0x167c
+#define HPD_CONN_THD_DP_TX_AUX_MASK GENMASK(9, 6)
#define MTK_DP_AUX_P0_3690 0x1690
#define RX_REPLY_COMPLETE_MODE_AUX_TX_P0 BIT(8)
@@ -340,6 +355,9 @@
#define AUX_TX_FIFO_WDATA_NEW_MODE_T_AUX_TX_P0_MASK BIT(1)
#define AUX_TX_FIFO_NEW_MODE_EN_AUX_TX_P0 BIT(2)
#define MTK_DP_AUX_P0_3708 0x1708
+#define MTK_DP_AUX_P0_37A0 0x17a0
+#define HPD_DISC_THD_AUX_TX GENMASK(7, 4)
+#define HPD_DISC_DEB_AUX_TX GENMASK(3, 0)
#define MTK_DP_AUX_P0_37C8 0x17c8
#define MTK_ATOP_EN_AUX_TX_P0 BIT(0)
--
2.54.0
^ permalink raw reply related
* Re: [PATCH v2 3/6] KVM: arm64: ptdump: Fix UAF when mmu->pgt is freed
From: Wei-Lin Chang @ 2026-07-01 17:27 UTC (permalink / raw)
To: Leonardo Bras
Cc: linux-arm-kernel, kvmarm, linux-kernel, Marc Zyngier,
Oliver Upton, Fuad Tabba, Joey Gouly, Steffen Eiden,
Suzuki K Poulose, Zenghui Yu, Catalin Marinas, Will Deacon,
Itaru Kitayama, Sebastian Ene
In-Reply-To: <akUrmfQnKmIXTigs@LeoBrasDK>
On Wed, Jul 01, 2026 at 04:00:41PM +0100, Leonardo Bras wrote:
> Hi Wei Lin,
>
> On Tue, Jun 30, 2026 at 01:10:02PM +0100, Wei-Lin Chang wrote:
> > ptdump files can still be read after the pgt of the canonical mmu is
> > freed, if they are opened before the VM debugfs directory is removed.
> > This triggers UAF in places where we cache the pgt pointer or access it
> > without checking its validity.
> >
> > Check the pgt is still alive under the mmu_lock before accessing the
> > pgt.
> >
> > Reported-by: Sashiko <sashiko-bot@kernel.org>
> > Closes: https://sashiko.dev/#/patchset/20260623142443.648972-1-weilin.chang@arm.com?part=1
> > Signed-off-by: Wei-Lin Chang <weilin.chang@arm.com>
> > ---
> > arch/arm64/kvm/ptdump.c | 38 ++++++++++++++++++++++++--------------
> > 1 file changed, 24 insertions(+), 14 deletions(-)
> >
> > diff --git a/arch/arm64/kvm/ptdump.c b/arch/arm64/kvm/ptdump.c
> > index d5aa9eff08d1..752d8e0cd25c 100644
> > --- a/arch/arm64/kvm/ptdump.c
> > +++ b/arch/arm64/kvm/ptdump.c
> > @@ -115,13 +115,21 @@ static int kvm_ptdump_build_levels(struct ptdump_pg_level *level, u32 start_lvl)
> > static struct kvm_ptdump_guest_state *kvm_ptdump_parser_create(struct kvm *kvm)
> > {
> > struct kvm_ptdump_guest_state *st;
> > - struct kvm_pgtable *pgtable = kvm->arch.mmu.pgt;
> > + struct kvm_pgtable *pgtable;
> > int ret;
> >
> > st = kzalloc_obj(struct kvm_ptdump_guest_state, GFP_KERNEL_ACCOUNT);
> > if (!st)
> > return ERR_PTR(-ENOMEM);
> >
> > + guard(write_lock)(&kvm->mmu_lock);
> > + if (!kvm->arch.mmu.pgt) {
> > + kfree(st);
> > + return ERR_PTR(-ENXIO);
> > + }
> > +
> > + pgtable = kvm->arch.mmu.pgt;
> > +
> > ret = kvm_ptdump_build_levels(&st->level[0], pgtable->start_level);
> > if (ret) {
> > kfree(st);
> > @@ -137,7 +145,6 @@ static struct kvm_ptdump_guest_state *kvm_ptdump_parser_create(struct kvm *kvm)
> >
> > static int kvm_ptdump_guest_show(struct seq_file *m, void *unused)
> > {
> > - int ret;
> > struct kvm_ptdump_guest_state *st = m->private;
> > struct kvm *kvm = st->kvm;
> > struct kvm_s2_mmu *mmu = &kvm->arch.mmu;
> > @@ -154,11 +161,11 @@ static int kvm_ptdump_guest_show(struct seq_file *m, void *unused)
> > .seq = m,
> > };
> >
> > - write_lock(&kvm->mmu_lock);
> > - ret = kvm_pgtable_walk(mmu->pgt, 0, BIT(mmu->pgt->ia_bits), &walker);
> > - write_unlock(&kvm->mmu_lock);
> > + guard(write_lock)(&kvm->mmu_lock);
> > + if (mmu->pgt)
> > + return kvm_pgtable_walk(mmu->pgt, 0, BIT(mmu->pgt->ia_bits), &walker);
>
> IIUC, that's the same behavior, right?
> Just changed to look about the same with the rest of this file?
I'm not too sure what you are referring to, if you mean the
write_lock/unlock -> guard(write_lock) change, then yes, mostly. Just
also checking mmu->pgt is still not freed.
>
> >
> > - return ret;
> > + return 0;
> > }
>
> So if the pgt does not exist anymore, it returns zero. Is that the desired
> behavior?
Good question, so the question is what contract between the ptdump and
user do we want to make for this case. I guess returning some error like -EIO
could make a little more sense than just printing nothing?
>
> I guess it's aligned with the idea of single file mentioned in the cover,
> right?
Sorry, I don't get what you are asking here?
>
> >
> > static int kvm_ptdump_guest_open(struct inode *m, struct file *file)
> > @@ -206,17 +213,23 @@ static const struct file_operations kvm_ptdump_guest_fops = {
> >
> > static int kvm_pgtable_range_show(struct seq_file *m, void *unused)
> > {
> > - struct kvm_pgtable *pgtable = m->private;
> > + struct kvm *kvm = m->private;
> > +
> > + guard(write_lock)(&kvm->mmu_lock);
> > + if (kvm->arch.mmu.pgt)
> > + seq_printf(m, "%2u\n", kvm->arch.mmu.pgt->ia_bits);
> >
> > - seq_printf(m, "%2u\n", pgtable->ia_bits);
> > return 0;
> > }
> >
> > static int kvm_pgtable_levels_show(struct seq_file *m, void *unused)
> > {
> > - struct kvm_pgtable *pgtable = m->private;
> > + struct kvm *kvm = m->private;
> > +
> > + guard(write_lock)(&kvm->mmu_lock);
> > + if (kvm->arch.mmu.pgt)
> > + seq_printf(m, "%1d\n", KVM_PGTABLE_MAX_LEVELS - kvm->arch.mmu.pgt->start_level);
> >
> > - seq_printf(m, "%1d\n", KVM_PGTABLE_MAX_LEVELS - pgtable->start_level);
> > return 0;
> > }
> >
> > @@ -224,15 +237,12 @@ static int kvm_pgtable_debugfs_open(struct inode *m, struct file *file,
> > int (*show)(struct seq_file *, void *))
> > {
> > struct kvm *kvm = m->i_private;
> > - struct kvm_pgtable *pgtable;
> > int ret;
> >
> > if (!kvm_get_kvm_safe(kvm))
> > return -ENOENT;
> >
> > - pgtable = kvm->arch.mmu.pgt;
> > -
> > - ret = single_open(file, show, pgtable);
> > + ret = single_open(file, show, kvm);
>
> Maybe this change is more related with the previous patch?
I see your point, but I divided it into first fixing mmu UAF, then the
pgt UAF, which I also think makes sense.
Thanks,
Wei-Lin Chang
>
> > if (ret < 0)
> > kvm_put_kvm(kvm);
> > return ret;
> > --
> > 2.43.0
> >
>
> Thanks!
> Leo
^ permalink raw reply
* [PATCH 10/10] drm/mediatek: Add Write DMA (WDMA) Engine for Writeback support
From: AngeloGioacchino Del Regno @ 2026-07-01 12:19 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, maarten.lankhorst, mripard, tzimmermann, airlied, simona,
robh, krzk+dt, conor+dt, matthias.bgg, angelogioacchino.delregno,
jitao.shi, dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, kernel, justin.yeh, jason-jh.lin
In-Reply-To: <20260701121950.19454-1-angelogioacchino.delregno@collabora.com>
Add a basic driver for the Write DMA Engine and initial compatible
for the MediaTek MT8173 and MediaTek Dimensity 1200 MT6893, and
hook it up to the mtk_ddp_comp and mtk_drm_drv in order for it to
probe.
This display controller component is used to enable the writeback
engine that can be used for faster display image capturing in the
userspace (for example, screenshots and screen recording).
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/Makefile | 1 +
drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 21 +-
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 20 +
drivers/gpu/drm/mediatek/mtk_disp_wdma.c | 611 +++++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
6 files changed, 656 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_wdma.c
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index 03b3470ea5b5..8079962597c8 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -11,6 +11,7 @@ mediatek-drm-y := mtk_crtc.o \
mtk_disp_ovl.o \
mtk_disp_ovl_adaptor.o \
mtk_disp_rdma.o \
+ mtk_disp_wdma.o \
mtk_drm_drv.o \
mtk_dsi.o \
mtk_dpi.o \
diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
index 13aaf12ecbe5..94b356da6de7 100644
--- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c
@@ -357,6 +357,22 @@ static const struct mtk_ddp_comp_funcs ddp_rdma = {
.get_num_formats = mtk_rdma_get_num_formats,
};
+static const struct mtk_ddp_comp_funcs ddp_wdma = {
+ .clk_enable = mtk_wdma_clk_enable,
+ .clk_disable = mtk_wdma_clk_disable,
+ .config = mtk_wdma_config,
+ .start = mtk_wdma_start,
+ .stop = mtk_wdma_stop,
+ .register_vblank_cb = mtk_wdma_register_vblank_cb,
+ .unregister_vblank_cb = mtk_wdma_unregister_vblank_cb,
+ .enable_vblank = mtk_wdma_enable_vblank,
+ .disable_vblank = mtk_wdma_disable_vblank,
+ .layer_nr = mtk_wdma_layer_nr,
+ .layer_config = mtk_wdma_layer_config,
+ .get_formats = mtk_wdma_get_formats,
+ .get_num_formats = mtk_wdma_get_num_formats,
+};
+
static const struct mtk_ddp_comp_funcs ddp_ufoe = {
.clk_enable = mtk_ddp_clk_enable,
.clk_disable = mtk_ddp_clk_disable,
@@ -460,8 +476,8 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_DRM_ID_MAX]
[DDP_COMPONENT_RDMA2] = { MTK_DISP_RDMA, 2, &ddp_rdma },
[DDP_COMPONENT_RDMA4] = { MTK_DISP_RDMA, 4, &ddp_rdma },
[DDP_COMPONENT_UFOE] = { MTK_DISP_UFOE, 0, &ddp_ufoe },
- [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, NULL },
- [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, NULL },
+ [DDP_COMPONENT_WDMA0] = { MTK_DISP_WDMA, 0, &ddp_wdma },
+ [DDP_COMPONENT_WDMA1] = { MTK_DISP_WDMA, 1, &ddp_wdma },
};
static bool mtk_ddp_comp_find(struct device *dev,
@@ -642,6 +658,7 @@ int mtk_ddp_comp_init(struct device *dev, struct device_node *node, struct mtk_d
type == MTK_DISP_OVL_2L ||
type == MTK_DISP_PWM ||
type == MTK_DISP_RDMA ||
+ type == MTK_DISP_WDMA ||
type == MTK_DPI ||
type == MTK_DP_INTF ||
type == MTK_DSI)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 5e2d8748120a..e0c30c6c7cc8 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -181,6 +181,26 @@ void mtk_mdp_rdma_config(struct device *dev, struct mtk_mdp_rdma_cfg *cfg,
const u32 *mtk_mdp_rdma_get_formats(struct device *dev);
size_t mtk_mdp_rdma_get_num_formats(struct device *dev);
+int mtk_wdma_clk_enable(struct device *dev);
+void mtk_wdma_clk_disable(struct device *dev);
+void mtk_wdma_config(struct device *dev, unsigned int width,
+ unsigned int height, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+unsigned int mtk_wdma_layer_nr(struct device *dev);
+void mtk_wdma_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt);
+void mtk_wdma_start(struct device *dev);
+void mtk_wdma_stop(struct device *dev);
+void mtk_wdma_register_vblank_cb(struct device *dev,
+ void (*vblank_cb)(void *),
+ void *vblank_cb_data);
+void mtk_wdma_unregister_vblank_cb(struct device *dev);
+void mtk_wdma_enable_vblank(struct device *dev);
+void mtk_wdma_disable_vblank(struct device *dev);
+const u32 *mtk_wdma_get_formats(struct device *dev);
+size_t mtk_wdma_get_num_formats(struct device *dev);
+
int mtk_padding_clk_enable(struct device *dev);
void mtk_padding_clk_disable(struct device *dev);
void mtk_padding_start(struct device *dev);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_wdma.c b/drivers/gpu/drm/mediatek/mtk_disp_wdma.c
new file mode 100644
index 000000000000..761dbe0148d8
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_wdma.c
@@ -0,0 +1,611 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Copyright (c) 2025 Collabora Ltd
+ * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ */
+
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_connector.h>
+#include <drm/drm_edid.h>
+#include <drm/drm_fourcc.h>
+#include <drm/drm_framebuffer.h>
+#include <drm/drm_gem_dma_helper.h>
+#include <drm/drm_probe_helper.h>
+#include <drm/drm_writeback.h>
+
+#include <linux/align.h>
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+#include <linux/wordpart.h>
+
+#include "mtk_crtc.h"
+#include "mtk_ddp_comp.h"
+#include "mtk_disp_drv.h"
+#include "mtk_drm_drv.h"
+
+#define DISP_REG_WDMA_INT_ENABLE 0x000
+ #define WDMA_FRAME_COMPLETE_INT BIT(0)
+#define DISP_REG_WDMA_INT_STATUS 0x004
+#define DISP_REG_WDMA_EN 0x008
+ #define WDMA_ENGINE_EN BIT(0)
+#define DISP_REG_WDMA_CFG 0x014
+ #define WDMA_CFG_OUT_FMT GENMASK(7, 4)
+ #define WDMA_OUT_FMT_RGB565 0
+ #define WDMA_OUT_FMT_RGB888 1
+ #define WDMA_OUT_FMT_RGBA8888 2
+ #define WDMA_OUT_FMT_ARGB8888 3
+ #define WDMA_OUT_FMT_UYVY 4
+ #define WDMA_OUT_FMT_YUY2 5
+ #define WDMA_OUT_FMT_P010 6
+ #define WDMA_OUT_FMT_Y_ONLY 7
+ #define WDMA_OUT_FMT_I420 8
+ #define WDMA_OUT_FMT_ARGB2101010 11
+ #define WDMA_OUT_FMT_NV12 12
+ #define WDMA_CT_EN BIT(11)
+ #define WDMA_CFG_SWAP BIT(16)
+ #define WDMA_UFO_DCP_ENABLE BIT(17)
+ #define WDMA_INT_MTX_SEL GENMASK(27, 23)
+ #define WDMA_CT_COEF_RGB_TO_JPEG 0
+ #define WDMA_CT_COEF_JPEG_TO_RGB 4
+#define DISP_REG_WDMA_SRC_SIZE 0x018
+#define DISP_REG_WDMA_CLIP_SIZE 0x01c
+ #define WDMA_HEIGHT_PX GENMASK(29, 16)
+ #define WDMA_WIDTH_PX GENMASK(13, 0)
+#define DISP_REG_WDMA_CLIP_COORD 0x020
+ #define WDMA_CLIP_Y_COORD GENMASK(29, 16)
+ #define WDMA_CLIP_X_COORD GENMASK(13, 0)
+#define DISP_REG_WDMA_SHADOW_CTRL 0x024
+ #define WDMA_FORCE_COMMIT BIT(0)
+ #define WDMA_BYPASS_SHADOW BIT(1)
+#define DISP_REG_WDMA_DST_W_IN_BYTE 0x028
+#define DISP_REG_WDMA_DST_UV_PITCH 0x078
+ #define WDMA_UV_DST_W_IN_BYTE GENMASK(15, 0)
+#define DISP_REG_WDMA_DST_ADDR_LSB 0xf00
+#define DISP_REG_WDMA_DST_ADDR_MSB_MT6893 0xf20
+#define DISP_REG_WDMA_DST_ADDRX(r, x) (r + (x * 0x4))
+
+static const u32 mtk_wdma_wb_output_formats[] = {
+ DRM_FORMAT_RGB888
+};
+
+static const u32 mt6893_formats[] = {
+ DRM_FORMAT_XRGB8888,
+ DRM_FORMAT_ARGB8888,
+ DRM_FORMAT_BGRX8888,
+ DRM_FORMAT_BGRA8888,
+ DRM_FORMAT_ABGR8888,
+ DRM_FORMAT_XBGR8888,
+ DRM_FORMAT_RGB888,
+ DRM_FORMAT_BGR888,
+ DRM_FORMAT_RGB565,
+ DRM_FORMAT_YUV420,
+ DRM_FORMAT_YVU420,
+ DRM_FORMAT_UYVY,
+ DRM_FORMAT_YUYV,
+};
+
+struct mtk_disp_wdma_data {
+ u32 reg_wdma_dst_addr0_msb;
+ const u32 *formats;
+ size_t num_formats;
+};
+
+struct mtk_disp_wdma {
+ struct device *dev;
+ struct clk *clk;
+ void __iomem *regs;
+ struct cmdq_client_reg cmdq_reg;
+ const struct mtk_disp_wdma_data *data;
+ void (*vblank_cb)(void *data);
+ void *vblank_cb_data;
+ int irq;
+ struct drm_writeback_connector wb_connector;
+ bool wb_pending;
+};
+
+static inline struct mtk_disp_wdma *connector_to_wdma(struct drm_connector *connector)
+{
+ return container_of(connector, struct mtk_disp_wdma, wb_connector.base);
+}
+
+static irqreturn_t mtk_disp_wdma_irq_handler(int irq, void *dev_id)
+{
+ struct mtk_disp_wdma *wdma = dev_id;
+
+ /* Clear frame completion interrupt */
+ writel(0x0, wdma->regs + DISP_REG_WDMA_INT_STATUS);
+
+ if (!wdma->vblank_cb)
+ return IRQ_NONE;
+
+ wdma->vblank_cb(wdma->vblank_cb_data);
+
+ /* TODO: Move completion signaling to CMDQ interrupt callback */
+ if (wdma->wb_pending) {
+ drm_writeback_signal_completion(&wdma->wb_connector, 0);
+ wdma->wb_pending = false;
+ }
+
+ return IRQ_HANDLED;
+}
+
+static void wdma_update_bits(struct device *dev, unsigned int reg,
+ unsigned int mask, unsigned int val)
+{
+ struct mtk_disp_wdma *wdma = dev_get_drvdata(dev);
+ unsigned int tmp = readl(wdma->regs + reg);
+
+ tmp = (tmp & ~mask) | (val & mask);
+ writel(tmp, wdma->regs + reg);
+}
+
+void mtk_wdma_register_vblank_cb(struct device *dev,
+ void (*vblank_cb)(void *),
+ void *vblank_cb_data)
+{
+ struct mtk_disp_wdma *wdma = dev_get_drvdata(dev);
+
+ wdma->vblank_cb = vblank_cb;
+ wdma->vblank_cb_data = vblank_cb_data;
+}
+
+void mtk_wdma_unregister_vblank_cb(struct device *dev)
+{
+ struct mtk_disp_wdma *wdma = dev_get_drvdata(dev);
+
+ wdma->vblank_cb = NULL;
+ wdma->vblank_cb_data = NULL;
+}
+
+void mtk_wdma_enable_vblank(struct device *dev)
+{
+ wdma_update_bits(dev, DISP_REG_WDMA_INT_ENABLE, WDMA_FRAME_COMPLETE_INT,
+ WDMA_FRAME_COMPLETE_INT);
+}
+
+void mtk_wdma_disable_vblank(struct device *dev)
+{
+ wdma_update_bits(dev, DISP_REG_WDMA_INT_ENABLE, WDMA_FRAME_COMPLETE_INT, 0);
+}
+
+const u32 *mtk_wdma_get_formats(struct device *dev)
+{
+ struct mtk_disp_wdma *wdma = dev_get_drvdata(dev);
+
+ return wdma->data->formats;
+}
+
+size_t mtk_wdma_get_num_formats(struct device *dev)
+{
+ struct mtk_disp_wdma *wdma = dev_get_drvdata(dev);
+
+ return wdma->data->num_formats;
+}
+
+int mtk_wdma_clk_enable(struct device *dev)
+{
+ struct mtk_disp_wdma *wdma = dev_get_drvdata(dev);
+
+ return clk_prepare_enable(wdma->clk);
+}
+
+void mtk_wdma_clk_disable(struct device *dev)
+{
+ struct mtk_disp_wdma *wdma = dev_get_drvdata(dev);
+
+ clk_disable_unprepare(wdma->clk);
+}
+
+void mtk_wdma_start(struct device *dev)
+{
+ wdma_update_bits(dev, DISP_REG_WDMA_EN, WDMA_ENGINE_EN,
+ WDMA_ENGINE_EN);
+}
+
+void mtk_wdma_stop(struct device *dev)
+{
+ wdma_update_bits(dev, DISP_REG_WDMA_EN, WDMA_ENGINE_EN, 0);
+}
+
+void mtk_wdma_config(struct device *dev, unsigned int width,
+ unsigned int height, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_disp_wdma *wdma = dev_get_drvdata(dev);
+
+ writel(WDMA_FORCE_COMMIT | WDMA_BYPASS_SHADOW,
+ wdma->regs + DISP_REG_WDMA_SHADOW_CTRL);
+}
+
+static u32 wdma_fmt_convert(unsigned int fmt)
+{
+ switch (fmt) {
+ default:
+ case DRM_FORMAT_RGB565:
+ return FIELD_PREP(WDMA_CFG_OUT_FMT, WDMA_OUT_FMT_RGB565);
+ case DRM_FORMAT_BGR565:
+ return FIELD_PREP(WDMA_CFG_OUT_FMT, WDMA_OUT_FMT_RGB565) | WDMA_CFG_SWAP;
+ case DRM_FORMAT_RGB888:
+ return FIELD_PREP(WDMA_CFG_OUT_FMT, WDMA_OUT_FMT_RGB888);
+ case DRM_FORMAT_BGR888:
+ return FIELD_PREP(WDMA_CFG_OUT_FMT, WDMA_OUT_FMT_RGB888) | WDMA_CFG_SWAP;
+ case DRM_FORMAT_RGBX8888:
+ case DRM_FORMAT_RGBA8888:
+ return FIELD_PREP(WDMA_CFG_OUT_FMT, WDMA_OUT_FMT_RGBA8888);
+ case DRM_FORMAT_BGRX8888:
+ case DRM_FORMAT_BGRA8888:
+ return FIELD_PREP(WDMA_CFG_OUT_FMT, WDMA_OUT_FMT_RGBA8888) | WDMA_CFG_SWAP;
+ case DRM_FORMAT_XRGB8888:
+ case DRM_FORMAT_ARGB8888:
+ return FIELD_PREP(WDMA_CFG_OUT_FMT, WDMA_OUT_FMT_ARGB8888);
+ case DRM_FORMAT_XBGR8888:
+ case DRM_FORMAT_ABGR8888:
+ return FIELD_PREP(WDMA_CFG_OUT_FMT, WDMA_OUT_FMT_ARGB8888) | WDMA_CFG_SWAP;
+ case DRM_FORMAT_UYVY:
+ return FIELD_PREP(WDMA_CFG_OUT_FMT, WDMA_OUT_FMT_UYVY);
+ case DRM_FORMAT_YUYV:
+ return FIELD_PREP(WDMA_CFG_OUT_FMT, WDMA_OUT_FMT_YUY2);
+ case DRM_FORMAT_YUV420:
+ return FIELD_PREP(WDMA_CFG_OUT_FMT, WDMA_OUT_FMT_I420);
+ case DRM_FORMAT_YVU420:
+ return FIELD_PREP(WDMA_CFG_OUT_FMT, WDMA_OUT_FMT_I420) | WDMA_CFG_SWAP;
+ }
+}
+
+unsigned int mtk_wdma_layer_nr(struct device *dev)
+{
+ return 1;
+}
+
+static void mtk_wdma_ddp_write_dst_addr(struct cmdq_pkt *cmdq_pkt, u64 val,
+ u8 reg_id, struct mtk_disp_wdma *wdma)
+{
+ mtk_ddp_write(cmdq_pkt, lower_32_bits(val), &wdma->cmdq_reg, wdma->regs,
+ DISP_REG_WDMA_DST_ADDRX(DISP_REG_WDMA_DST_ADDR_LSB, 1));
+
+ if (wdma->data->reg_wdma_dst_addr0_msb == 0)
+ return;
+
+ mtk_ddp_write(cmdq_pkt, upper_32_bits(val), &wdma->cmdq_reg, wdma->regs,
+ DISP_REG_WDMA_DST_ADDRX(wdma->data->reg_wdma_dst_addr0_msb, 1));
+}
+
+static void mtk_wdma_format_config(struct mtk_disp_wdma *wdma,
+ struct mtk_plane_pending_state *pending,
+ const struct drm_format_info *fmt_info,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ unsigned int u_off, u_stride, u_size, v_off;
+ u32 val;
+
+ /*
+ * For RGB formats, this sets the image destination address;
+ * For YUV formats, this sets the Y component destination address.
+ */
+ mtk_wdma_ddp_write_dst_addr(cmdq_pkt, pending->addr, 0, wdma);
+
+ if (!fmt_info->is_yuv) {
+ /* Disable color transform matrix and data compression */
+ mtk_ddp_write_mask(cmdq_pkt, 0, &wdma->cmdq_reg, wdma->regs,
+ DISP_REG_WDMA_CFG,
+ WDMA_UFO_DCP_ENABLE | WDMA_CT_EN);
+ return;
+ }
+
+ /* Additional format config required only for 420 sampling */
+ if (!drm_format_info_is_yuv_sampling_420(fmt_info))
+ return;
+
+ u_off = pending->pitch * pending->height;
+ u_stride = pending->pitch / 2;
+
+ if (drm_format_info_is_yuv_planar(fmt_info)) {
+ /* YUV420 or YVU420 */
+ u_stride = ALIGN(u_stride, 16);
+ u_size = u_stride * pending->height / 2;
+ v_off = u_off + u_size;
+ } else {
+ /* NV12 or NV21 */
+ u_size = u_stride * pending->height / 2;
+ v_off = 0;
+ }
+
+ /* Set U and V components destination addresses */
+ mtk_wdma_ddp_write_dst_addr(cmdq_pkt, pending->addr + u_off, 1, wdma);
+ mtk_wdma_ddp_write_dst_addr(cmdq_pkt, pending->addr + v_off, 2, wdma);
+
+ mtk_ddp_write(cmdq_pkt, FIELD_PREP(WDMA_UV_DST_W_IN_BYTE, u_stride),
+ &wdma->cmdq_reg, wdma->regs, DISP_REG_WDMA_DST_UV_PITCH);
+
+ /* Color transform coefficient selection */
+ val = FIELD_PREP_CONST(WDMA_INT_MTX_SEL, WDMA_CT_COEF_JPEG_TO_RGB);
+ mtk_ddp_write_mask(cmdq_pkt, val, &wdma->cmdq_reg, wdma->regs,
+ DISP_REG_WDMA_CFG, WDMA_INT_MTX_SEL);
+
+ /* Enable color transform matrix, disable data compression */
+ mtk_ddp_write_mask(cmdq_pkt, WDMA_CT_EN, &wdma->cmdq_reg, wdma->regs,
+ DISP_REG_WDMA_CFG, WDMA_UFO_DCP_ENABLE | WDMA_CT_EN);
+}
+
+void mtk_wdma_layer_config(struct device *dev, unsigned int idx,
+ struct mtk_plane_state *state,
+ struct cmdq_pkt *cmdq_pkt)
+{
+ struct mtk_disp_wdma *wdma = dev_get_drvdata(dev);
+ struct mtk_plane_pending_state *pending = &state->pending;
+ unsigned int pitch = pending->pitch & 0xffff;
+ unsigned int fmt = pending->format;
+ unsigned int con = wdma_fmt_convert(fmt);
+ const struct drm_format_info *fmt_info = drm_format_info(fmt);
+ u16 clip_sz_h = pending->height;
+ u16 clip_sz_w = pending->width;
+ u32 val;
+
+ val = FIELD_PREP(WDMA_HEIGHT_PX, pending->height);
+ val |= FIELD_PREP(WDMA_WIDTH_PX, pending->width);
+ mtk_ddp_write(cmdq_pkt, val, &wdma->cmdq_reg, wdma->regs,
+ DISP_REG_WDMA_SRC_SIZE);
+
+ val = FIELD_PREP(WDMA_HEIGHT_PX, pending->y);
+ val |= FIELD_PREP(WDMA_WIDTH_PX, pending->x);
+ mtk_ddp_write(cmdq_pkt, val, &wdma->cmdq_reg, wdma->regs,
+ DISP_REG_WDMA_CLIP_COORD);
+
+ if (fmt_info->is_yuv) {
+ if ((pending->y + pending->height) % 2)
+ clip_sz_h--;
+
+ if ((pending->x + pending->width) % 2)
+ clip_sz_w--;
+ }
+ val = FIELD_PREP(WDMA_HEIGHT_PX, clip_sz_h);
+ val |= FIELD_PREP(WDMA_WIDTH_PX, clip_sz_w);
+ mtk_ddp_write(cmdq_pkt, val, &wdma->cmdq_reg, wdma->regs,
+ DISP_REG_WDMA_CLIP_SIZE);
+
+ mtk_ddp_write(cmdq_pkt, con, &wdma->cmdq_reg, wdma->regs,
+ DISP_REG_WDMA_CFG);
+ mtk_ddp_write(cmdq_pkt, pitch, &wdma->cmdq_reg, wdma->regs,
+ DISP_REG_WDMA_DST_W_IN_BYTE);
+
+ mtk_wdma_format_config(wdma, pending, fmt_info, cmdq_pkt);
+
+ drm_writeback_queue_job(&wdma->wb_connector, wdma->wb_connector.base.state);
+}
+
+static enum drm_connector_status
+mtk_wdma_wb_connector_detect(struct drm_connector *connector, bool force)
+{
+ return connector_status_connected;
+}
+
+static const struct drm_connector_funcs mtk_wdma_wb_connector_funcs = {
+ .detect = mtk_wdma_wb_connector_detect,
+ .fill_modes = drm_helper_probe_single_connector_modes,
+ .destroy = drm_connector_cleanup,
+ .reset = drm_atomic_helper_connector_reset,
+ .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+};
+
+static int mtk_wdma_wb_atomic_check(struct drm_encoder *encoder,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state)
+{
+ const struct drm_display_mode *mode = &crtc_state->mode;
+ struct drm_framebuffer *fb;
+ int i;
+
+ if (!conn_state->writeback_job || !conn_state->writeback_job->fb)
+ return 0;
+
+ fb = conn_state->writeback_job->fb;
+ if (fb->width != mode->hdisplay || fb->height != mode->vdisplay)
+ return -EINVAL;
+
+ for (i = 0; i < ARRAY_SIZE(mtk_wdma_wb_output_formats); i++) {
+ if (fb->format->format == mtk_wdma_wb_output_formats[i])
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+static const struct drm_encoder_helper_funcs mtk_wdma_wb_encoder_helper_funcs = {
+ .atomic_check = mtk_wdma_wb_atomic_check,
+};
+
+static int mtk_wdma_wb_connector_get_modes(struct drm_connector *connector)
+{
+ struct drm_device *dev = connector->dev;
+
+ return drm_add_modes_noedid(connector, dev->mode_config.max_width,
+ dev->mode_config.max_height);
+}
+
+static enum drm_mode_status
+mtk_wdma_wb_connector_mode_valid(struct drm_connector *connector,
+ const struct drm_display_mode *mode)
+{
+ struct drm_device *dev = connector->dev;
+ struct drm_mode_config *mode_config = &dev->mode_config;
+ int w = mode->hdisplay, h = mode->vdisplay;
+
+ if (w < mode_config->min_width || w > mode_config->max_width)
+ return MODE_BAD_HVALUE;
+
+ if (h < mode_config->min_height || h > mode_config->max_height)
+ return MODE_BAD_VVALUE;
+
+ return MODE_OK;
+}
+
+static void mtk_wdma_wb_connector_atomic_commit(struct drm_connector *connector,
+ struct drm_atomic_commit *state)
+{
+ struct drm_connector_state *conn_state =
+ drm_atomic_get_new_connector_state(state, connector);
+ struct mtk_disp_wdma *wdma = connector_to_wdma(connector);
+ struct drm_framebuffer *fb;
+ struct drm_gem_object *gem;
+ struct drm_gem_dma_object *dma_obj;
+ dma_addr_t addr;
+
+ if (WARN_ON(!conn_state->writeback_job))
+ return;
+
+ fb = conn_state->writeback_job->fb;
+ gem = fb->obj[0];
+ dma_obj = to_drm_gem_dma_obj(gem);
+ addr = dma_obj->dma_addr;
+
+ /* Store writeback pending state before queuing the job */
+ wdma->wb_pending = true;
+
+ mtk_wdma_ddp_write_dst_addr(NULL, addr, 0, wdma);
+ drm_writeback_queue_job(&wdma->wb_connector, conn_state);
+}
+
+static const struct drm_connector_helper_funcs mtk_wdma_wb_connector_helper_funcs = {
+ .get_modes = mtk_wdma_wb_connector_get_modes,
+ .mode_valid = mtk_wdma_wb_connector_mode_valid,
+ .atomic_commit = mtk_wdma_wb_connector_atomic_commit,
+};
+
+static int mtk_disp_wdma_bind(struct device *dev, struct device *master,
+ void *data)
+{
+ struct mtk_disp_wdma *wdma = dev_get_drvdata(dev);
+ struct drm_device *drm_dev = data;
+ int crtcs, ret;
+
+ crtcs = mtk_find_possible_crtcs(drm_dev, wdma->dev);
+ if (crtcs < 0)
+ return crtcs;
+
+ drm_connector_helper_add(&wdma->wb_connector.base,
+ &mtk_wdma_wb_connector_helper_funcs);
+
+ ret = drm_writeback_connector_init(drm_dev, &wdma->wb_connector,
+ &mtk_wdma_wb_connector_funcs,
+ &mtk_wdma_wb_encoder_helper_funcs,
+ mtk_wdma_wb_output_formats,
+ ARRAY_SIZE(mtk_wdma_wb_output_formats),
+ crtcs);
+ if (ret)
+ return ret;
+
+ /* Disable and clear pending interrupts */
+ writel(0x0, wdma->regs + DISP_REG_WDMA_INT_ENABLE);
+ writel(0x0, wdma->regs + DISP_REG_WDMA_INT_STATUS);
+
+ enable_irq(wdma->irq);
+ return 0;
+}
+
+static void mtk_disp_wdma_unbind(struct device *dev, struct device *master,
+ void *data)
+{
+ struct mtk_disp_wdma *wdma = dev_get_drvdata(dev);
+
+ disable_irq(wdma->irq);
+}
+
+static const struct component_ops mtk_disp_wdma_component_ops = {
+ .bind = mtk_disp_wdma_bind,
+ .unbind = mtk_disp_wdma_unbind,
+};
+
+static int mtk_disp_wdma_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct mtk_disp_wdma *priv;
+ struct resource *res;
+ int ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->dev = dev;
+
+ priv->irq = platform_get_irq(pdev, 0);
+ if (priv->irq < 0)
+ return priv->irq;
+
+ priv->clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(priv->clk))
+ return dev_err_probe(dev, PTR_ERR(priv->clk),
+ "failed to get wdma clk\n");
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ priv->regs = devm_ioremap_resource(dev, res);
+ if (IS_ERR(priv->regs))
+ return dev_err_probe(dev, PTR_ERR(priv->regs),
+ "failed to ioremap wdma\n");
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
+ if (ret)
+ dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+
+ ret = devm_request_irq(dev, priv->irq, mtk_disp_wdma_irq_handler,
+ IRQF_NO_AUTOEN, dev_name(dev), priv);
+ if (ret < 0)
+ return dev_err_probe(dev, ret, "Failed to request irq\n");
+
+ priv->data = of_device_get_match_data(dev);
+
+ platform_set_drvdata(pdev, priv);
+
+ pm_runtime_enable(dev);
+
+ ret = component_add(dev, &mtk_disp_wdma_component_ops);
+ if (ret) {
+ pm_runtime_disable(dev);
+ return dev_err_probe(dev, ret, "Failed to add component\n");
+ }
+
+ return 0;
+}
+
+static void mtk_disp_wdma_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &mtk_disp_wdma_component_ops);
+
+ pm_runtime_disable(&pdev->dev);
+}
+
+static const struct mtk_disp_wdma_data mt6893_wdma_driver_data = {
+ .reg_wdma_dst_addr0_msb = DISP_REG_WDMA_DST_ADDR_MSB_MT6893,
+ .formats = mt6893_formats,
+ .num_formats = ARRAY_SIZE(mt6893_formats),
+};
+
+static const struct mtk_disp_wdma_data mt8173_wdma_driver_data = {
+ .formats = mt6893_formats,
+ .num_formats = ARRAY_SIZE(mt6893_formats),
+};
+
+static const struct of_device_id mtk_disp_wdma_driver_dt_match[] = {
+ { .compatible = "mediatek,mt6893-disp-wdma", .data = &mt6893_wdma_driver_data },
+ { .compatible = "mediatek,mt8173-disp-wdma", .data = &mt8173_wdma_driver_data },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, mtk_disp_wdma_driver_dt_match);
+
+struct platform_driver mtk_disp_wdma_driver = {
+ .probe = mtk_disp_wdma_probe,
+ .remove = mtk_disp_wdma_remove,
+ .driver = {
+ .name = "mediatek-disp-wdma",
+ .of_match_table = mtk_disp_wdma_driver_dt_match,
+ },
+};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 9a4c59849c4b..e54f0654f2f9 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -796,6 +796,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_RDMA },
{ .compatible = "mediatek,mt8173-disp-ufoe",
.data = (void *)MTK_DISP_UFOE },
+ { .compatible = "mediatek,mt6893-disp-wdma",
+ .data = (void *)MTK_DISP_WDMA },
{ .compatible = "mediatek,mt8173-disp-wdma",
.data = (void *)MTK_DISP_WDMA },
{ .compatible = "mediatek,mt2701-dpi",
@@ -1173,6 +1175,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
comp_type == MTK_DISP_OVL_2L ||
comp_type == MTK_DISP_OVL_ADAPTOR ||
comp_type == MTK_DISP_RDMA ||
+ comp_type == MTK_DISP_WDMA ||
comp_type == MTK_DP_INTF ||
comp_type == MTK_DPI ||
comp_type == MTK_DSI) {
@@ -1281,6 +1284,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
&mtk_disp_ovl_adaptor_driver,
&mtk_disp_ovl_driver,
&mtk_disp_rdma_driver,
+ &mtk_disp_wdma_driver,
&mtk_dpi_driver,
&mtk_drm_platform_driver,
&mtk_dsi_driver,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 43aac2d956e7..8b5c51d93f72 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -77,6 +77,7 @@ extern struct platform_driver mtk_disp_merge_driver;
extern struct platform_driver mtk_disp_ovl_adaptor_driver;
extern struct platform_driver mtk_disp_ovl_driver;
extern struct platform_driver mtk_disp_rdma_driver;
+extern struct platform_driver mtk_disp_wdma_driver;
extern struct platform_driver mtk_dpi_driver;
extern struct platform_driver mtk_dsi_driver;
extern struct platform_driver mtk_ethdr_driver;
--
2.54.0
^ permalink raw reply related
* Re: [PATCH v2 6/6] KVM: arm64: ptdump: Introduce the shadow ptdump file
From: Wei-Lin Chang @ 2026-07-01 17:35 UTC (permalink / raw)
To: Leonardo Bras
Cc: linux-arm-kernel, kvmarm, linux-kernel, Marc Zyngier,
Oliver Upton, Fuad Tabba, Joey Gouly, Steffen Eiden,
Suzuki K Poulose, Zenghui Yu, Catalin Marinas, Will Deacon,
Itaru Kitayama, Sebastian Ene
In-Reply-To: <akUyI3Z9JbggzE5P@LeoBrasDK>
On Wed, Jul 01, 2026 at 04:28:35PM +0100, Leonardo Bras wrote:
> On Tue, Jun 30, 2026 at 01:10:05PM +0100, Wei-Lin Chang wrote:
> > Create a ptdump file for all shadow page tables. It will dump out all
> > valid shadow page tables at the time of request, with the mmu's index,
> > guest VTCR_EL2, VTTBR_EL2, and whether the guest stage-2 is enabled or
> > not.
> >
> > Also detach the nested mmu array under the mmu_lock in
> > kvm_arch_flush_shadow_all() so readers cannot race with the array being
> > removed, then free the old array after dropping the lock.
>
> Out of curiosity: why drop the lock before kfree'ing ?
Because kvfree() can sleep! :)
Thanks,
Wei-Lin Chang
>
> Thanks!
> Leo
>
> >
> > Signed-off-by: Wei-Lin Chang <weilin.chang@arm.com>
> > ---
> > arch/arm64/kvm/nested.c | 12 ++++++--
> > arch/arm64/kvm/ptdump.c | 61 ++++++++++++++++++++++++++++++++++++++++-
> > 2 files changed, 69 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/arm64/kvm/nested.c b/arch/arm64/kvm/nested.c
> > index 6435efd65cb5..17a180ddf6ca 100644
> > --- a/arch/arm64/kvm/nested.c
> > +++ b/arch/arm64/kvm/nested.c
> > @@ -1283,6 +1283,7 @@ void kvm_nested_s2_flush(struct kvm *kvm)
> >
> > void kvm_arch_flush_shadow_all(struct kvm *kvm)
> > {
> > + struct kvm_s2_mmu *mmus;
> > int i;
> >
> > for (i = 0; i < kvm->arch.nested_mmus_size; i++) {
> > @@ -1291,9 +1292,14 @@ void kvm_arch_flush_shadow_all(struct kvm *kvm)
> > if (!WARN_ON(atomic_read(&mmu->refcnt)))
> > kvm_free_stage2_pgd(mmu);
> > }
> > - kvfree(kvm->arch.nested_mmus);
> > - kvm->arch.nested_mmus = NULL;
> > - kvm->arch.nested_mmus_size = 0;
> > +
> > + scoped_guard(write_lock, &kvm->mmu_lock) {
> > + mmus = kvm->arch.nested_mmus;
> > + kvm->arch.nested_mmus = NULL;
> > + kvm->arch.nested_mmus_size = 0;
> > + }
> > +
> > + kvfree(mmus);
> > kvm_uninit_stage2_mmu(kvm);
> > }
> >
> > diff --git a/arch/arm64/kvm/ptdump.c b/arch/arm64/kvm/ptdump.c
> > index 40f93b7c7ad9..1649eaa75798 100644
> > --- a/arch/arm64/kvm/ptdump.c
> > +++ b/arch/arm64/kvm/ptdump.c
> > @@ -181,6 +181,50 @@ static int kvm_ptdump_guest_canonical_show(struct seq_file *m, void *unused)
> > return 0;
> > }
> >
> > +static int kvm_ptdump_guest_nested_show(struct seq_file *m, void *unused)
> > +{
> > + int ret = 0, i;
> > + struct kvm_ptdump_guest_state *st = m->private;
> > + struct kvm *kvm = st->kvm;
> > + struct kvm_pgtable_walker walker = (struct kvm_pgtable_walker) {
> > + .cb = kvm_ptdump_visitor,
> > + .arg = &st->parser_state,
> > + .flags = KVM_PGTABLE_WALK_LEAF,
> > + };
> > +
> > + guard(write_lock)(&kvm->mmu_lock);
> > +
> > + if (!kvm->arch.nested_mmus)
> > + return 0;
> > +
> > + for (i = 0; i < kvm->arch.nested_mmus_size; i++) {
> > + struct kvm_s2_mmu *mmu = &kvm->arch.nested_mmus[i];
> > +
> > + if (!mmu->pgt)
> > + continue;
> > +
> > + if (kvm_s2_mmu_valid(mmu)) {
> > + memset(st, 0, sizeof(*st));
> > + ret = kvm_ptdump_parser_init(st, kvm, mmu->pgt);
> > + if (ret)
> > + return ret;
> > + st->parser_state = (struct ptdump_pg_state) {
> > + .marker = &st->ipa_marker[0],
> > + .level = -1,
> > + .pg_level = &st->level[0],
> > + .seq = m,
> > + };
> > + seq_printf(m, "nested mmu %d VTCR: 0x%016llx VTTBR: 0x%016llx s2: %s\n",
> > + i, mmu->tlb_vtcr, mmu->tlb_vttbr,
> > + mmu->nested_stage2_enabled ? "enabled" : "disabled");
> > + ret = kvm_pgtable_walk(mmu->pgt, 0, BIT(mmu->pgt->ia_bits), &walker);
> > + if (ret)
> > + return ret;
> > + }
> > + }
> > + return ret;
> > +}
> > +
> > static int kvm_ptdump_guest_open(struct inode *m, struct file *file,
> > int (*show)(struct seq_file *, void *))
> > {
> > @@ -212,6 +256,11 @@ static int kvm_ptdump_guest_canonical_open(struct inode *m, struct file *file)
> > return kvm_ptdump_guest_open(m, file, kvm_ptdump_guest_canonical_show);
> > }
> >
> > +static int kvm_ptdump_guest_nested_open(struct inode *m, struct file *file)
> > +{
> > + return kvm_ptdump_guest_open(m, file, kvm_ptdump_guest_nested_show);
> > +}
> > +
> > static int kvm_ptdump_guest_close(struct inode *m, struct file *file)
> > {
> > struct kvm *kvm = m->i_private;
> > @@ -230,6 +279,13 @@ static const struct file_operations kvm_ptdump_guest_canonical_fops = {
> > .release = kvm_ptdump_guest_close,
> > };
> >
> > +static const struct file_operations kvm_ptdump_guest_nested_fops = {
> > + .open = kvm_ptdump_guest_nested_open,
> > + .read = seq_read,
> > + .llseek = seq_lseek,
> > + .release = kvm_ptdump_guest_close,
> > +};
> > +
> > static int kvm_pgtable_range_show(struct seq_file *m, void *unused)
> > {
> > struct kvm *kvm = m->private;
> > @@ -307,6 +363,9 @@ void kvm_s2_ptdump_create_debugfs(struct kvm *kvm)
> > kvm, &kvm_pgtable_range_fops);
> > debugfs_create_file("stage2_levels", 0400, kvm->debugfs_dentry,
> > kvm, &kvm_pgtable_levels_fops);
> > - if (cpus_have_final_cap(ARM64_HAS_NESTED_VIRT))
> > + if (cpus_have_final_cap(ARM64_HAS_NESTED_VIRT)) {
> > kvm->arch.debugfs_nv_dentry = debugfs_create_dir("nested", kvm->debugfs_dentry);
> > + debugfs_create_file("shadow_page_tables", 0400, kvm->arch.debugfs_nv_dentry,
> > + kvm, &kvm_ptdump_guest_nested_fops);
> > + }
> > }
> > --
> > 2.43.0
> >
^ permalink raw reply
* [PATCH net v2] net: airoha: fix MIB stats collection to be lossless
From: Aniket Negi @ 2026-07-01 17:39 UTC (permalink / raw)
To: lorenzo, netdev
Cc: Aniket Negi, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, linux-arm-kernel, linux-mediatek,
linux-kernel
In-Reply-To: <20260630111834.233643-1-aniket.negi03@gmail.com>
The current driver resets hardware MIB counters after every read via
REG_FE_GDM_MIB_CLEAR. This creates a race window: packets arriving
between the read and the clear are silently lost from statistics.
Fix this by removing the MIB clear and switching to a delta-based
software tracking approach:
- 64-bit H+L registers (tx/rx ok pkts, ok bytes, E64..L1023):
read the absolute hardware total directly each poll.
- 32-bit registers (drops, bc, mc, errors, runt, long, ...):
store the previous raw register value in mib_prev and accumulate
(u32)(curr - prev) into a 64-bit software counter. Unsigned
subtraction handles wrap-around transparently.
- tx_len[0]/rx_len[0] ({0,64} RMON bucket) combines RUNT_CNT
(32-bit, delta-tracked via mib_prev.tx_runt_cnt) and E64_CNT
(64-bit, absolute). A u64 accumulator tx_runt_accum64 holds the
running RUNT delta sum so that each poll sets:
tx_len[0] = tx_runt_accum64 + E64_abs
without double-counting the E64 value.
Merge airoha_dev_get_hw_stats() into airoha_update_hw_stats(),
moving the port spin_lock inside so callers do not need a separate
wrapper.
Signed-off-by: Aniket Negi <aniket.negi03@gmail.com>
---
Changes in v2:
- Store _CNT_L register reads in val before adding to stats, improving
readability (suggested by Lorenzo Bianconi)
- Fix double-counting bug in the RUNT+E64 combined bucket: previously
"+=" for E64 re-added the full absolute counter each poll; now a
dedicated tx_runt_accum64/rx_runt_accum64 accumulator holds the
running RUNT delta, and tx_len[0] is assigned (not accumulated) each
poll as runt_accum64 + E64_abs
- Replace 7-element tx_len[]/rx_len[] shadow arrays in mib_prev with
focused tx_runt_cnt/tx_long_cnt and rx_runt_cnt/rx_long_cnt fields;
only RUNT and LONG are 32-bit and need wrap-around tracking
- Rename inner struct hw_prev_stats to mib_prev; rename accumulator
fields to tx_runt_accum64/rx_runt_accum64 for clarity
- Fix comment alignment in mib_prev struct block
- Rename airoha_dev_get_hw_stats() to airoha_update_hw_stats() and
move the port spin_lock inside, removing the separate wrapper
drivers/net/ethernet/airoha/airoha_eth.c | 115 +++++++++++++----------
drivers/net/ethernet/airoha/airoha_eth.h | 27 ++++++
2 files changed, 92 insertions(+), 50 deletions(-)
diff --git a/drivers/net/ethernet/airoha/airoha_eth.c b/drivers/net/ethernet/airoha/airoha_eth.c
index 59001fd4b6f7..4b7c547de165 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.c
+++ b/drivers/net/ethernet/airoha/airoha_eth.c
@@ -1686,12 +1686,14 @@ static void airoha_qdma_stop_napi(struct airoha_qdma *qdma)
}
}
-static void airoha_dev_get_hw_stats(struct airoha_gdm_dev *dev)
+static void airoha_update_hw_stats(struct airoha_gdm_dev *dev)
{
struct airoha_gdm_port *port = dev->port;
struct airoha_eth *eth = dev->eth;
u32 val, i = 0;
+ spin_lock(&port->stats_lock);
+
/* Read relevant MIB for GDM with multiple port attached */
if (port->id == AIROHA_GDM3_IDX || port->id == AIROHA_GDM4_IDX)
airoha_fe_rmw(eth, REG_FE_GDM_MIB_CFG(port->id),
@@ -1701,152 +1703,165 @@ static void airoha_dev_get_hw_stats(struct airoha_gdm_dev *dev)
u64_stats_update_begin(&dev->stats.syncp);
- /* TX */
+ /* TX - 64-bit H+L registers: hw accumulates the total, read directly. */
val = airoha_fe_rr(eth, REG_FE_GDM_TX_OK_PKT_CNT_H(port->id));
- dev->stats.tx_ok_pkts += ((u64)val << 32);
+ dev->stats.tx_ok_pkts = (u64)val << 32;
val = airoha_fe_rr(eth, REG_FE_GDM_TX_OK_PKT_CNT_L(port->id));
dev->stats.tx_ok_pkts += val;
val = airoha_fe_rr(eth, REG_FE_GDM_TX_OK_BYTE_CNT_H(port->id));
- dev->stats.tx_ok_bytes += ((u64)val << 32);
+ dev->stats.tx_ok_bytes = (u64)val << 32;
val = airoha_fe_rr(eth, REG_FE_GDM_TX_OK_BYTE_CNT_L(port->id));
dev->stats.tx_ok_bytes += val;
+ /* TX - 32-bit registers: accumulate delta to handle wrap-around. */
val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_DROP_CNT(port->id));
- dev->stats.tx_drops += val;
+ dev->stats.tx_drops += (u32)(val - dev->stats.mib_prev.tx_drops);
+ dev->stats.mib_prev.tx_drops = val;
val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_BC_CNT(port->id));
- dev->stats.tx_broadcast += val;
+ dev->stats.tx_broadcast += (u32)(val - dev->stats.mib_prev.tx_broadcast);
+ dev->stats.mib_prev.tx_broadcast = val;
val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_MC_CNT(port->id));
- dev->stats.tx_multicast += val;
+ dev->stats.tx_multicast += (u32)(val - dev->stats.mib_prev.tx_multicast);
+ dev->stats.mib_prev.tx_multicast = val;
val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_RUNT_CNT(port->id));
- dev->stats.tx_len[i] += val;
+ dev->stats.mib_prev.tx_runt_accum64 +=
+ (u32)(val - dev->stats.mib_prev.tx_runt_cnt);
+ dev->stats.mib_prev.tx_runt_cnt = val;
+
+ /* tx_len[0]: RUNT (32-bit, delta) + E64 (64-bit, absolute) → {0, 64} bucket.
+ * Accumulate RUNT delta in tx_runt_accum64, then assign tx_len[0] as
+ * accum + E64_abs so each call gives the correct combined total.
+ */
+
+ dev->stats.tx_len[i] = dev->stats.mib_prev.tx_runt_accum64;
val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_E64_CNT_H(port->id));
- dev->stats.tx_len[i] += ((u64)val << 32);
+ dev->stats.tx_len[i] += (u64)val << 32;
val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_E64_CNT_L(port->id));
dev->stats.tx_len[i++] += val;
val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L64_CNT_H(port->id));
- dev->stats.tx_len[i] += ((u64)val << 32);
+ dev->stats.tx_len[i] = (u64)val << 32;
val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L64_CNT_L(port->id));
dev->stats.tx_len[i++] += val;
val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L127_CNT_H(port->id));
- dev->stats.tx_len[i] += ((u64)val << 32);
+ dev->stats.tx_len[i] = (u64)val << 32;
val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L127_CNT_L(port->id));
dev->stats.tx_len[i++] += val;
val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L255_CNT_H(port->id));
- dev->stats.tx_len[i] += ((u64)val << 32);
+ dev->stats.tx_len[i] = (u64)val << 32;
val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L255_CNT_L(port->id));
dev->stats.tx_len[i++] += val;
val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L511_CNT_H(port->id));
- dev->stats.tx_len[i] += ((u64)val << 32);
+ dev->stats.tx_len[i] = (u64)val << 32;
val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L511_CNT_L(port->id));
dev->stats.tx_len[i++] += val;
val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L1023_CNT_H(port->id));
- dev->stats.tx_len[i] += ((u64)val << 32);
+ dev->stats.tx_len[i] = (u64)val << 32;
val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_L1023_CNT_L(port->id));
dev->stats.tx_len[i++] += val;
val = airoha_fe_rr(eth, REG_FE_GDM_TX_ETH_LONG_CNT(port->id));
- dev->stats.tx_len[i++] += val;
+ dev->stats.tx_len[i++] += (u32)(val - dev->stats.mib_prev.tx_long_cnt);
+ dev->stats.mib_prev.tx_long_cnt = val;
/* RX */
val = airoha_fe_rr(eth, REG_FE_GDM_RX_OK_PKT_CNT_H(port->id));
- dev->stats.rx_ok_pkts += ((u64)val << 32);
+ dev->stats.rx_ok_pkts = (u64)val << 32;
val = airoha_fe_rr(eth, REG_FE_GDM_RX_OK_PKT_CNT_L(port->id));
dev->stats.rx_ok_pkts += val;
val = airoha_fe_rr(eth, REG_FE_GDM_RX_OK_BYTE_CNT_H(port->id));
- dev->stats.rx_ok_bytes += ((u64)val << 32);
+ dev->stats.rx_ok_bytes = (u64)val << 32;
val = airoha_fe_rr(eth, REG_FE_GDM_RX_OK_BYTE_CNT_L(port->id));
dev->stats.rx_ok_bytes += val;
val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_DROP_CNT(port->id));
- dev->stats.rx_drops += val;
+ dev->stats.rx_drops += (u32)(val - dev->stats.mib_prev.rx_drops);
+ dev->stats.mib_prev.rx_drops = val;
val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_BC_CNT(port->id));
- dev->stats.rx_broadcast += val;
+ dev->stats.rx_broadcast += (u32)(val - dev->stats.mib_prev.rx_broadcast);
+ dev->stats.mib_prev.rx_broadcast = val;
val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_MC_CNT(port->id));
- dev->stats.rx_multicast += val;
+ dev->stats.rx_multicast += (u32)(val - dev->stats.mib_prev.rx_multicast);
+ dev->stats.mib_prev.rx_multicast = val;
val = airoha_fe_rr(eth, REG_FE_GDM_RX_ERROR_DROP_CNT(port->id));
- dev->stats.rx_errors += val;
+ dev->stats.rx_errors += (u32)(val - dev->stats.mib_prev.rx_errors);
+ dev->stats.mib_prev.rx_errors = val;
val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_CRC_ERR_CNT(port->id));
- dev->stats.rx_crc_error += val;
+ dev->stats.rx_crc_error += (u32)(val - dev->stats.mib_prev.rx_crc_error);
+ dev->stats.mib_prev.rx_crc_error = val;
val = airoha_fe_rr(eth, REG_FE_GDM_RX_OVERFLOW_DROP_CNT(port->id));
- dev->stats.rx_over_errors += val;
+ dev->stats.rx_over_errors += (u32)(val - dev->stats.mib_prev.rx_over_errors);
+ dev->stats.mib_prev.rx_over_errors = val;
val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_FRAG_CNT(port->id));
- dev->stats.rx_fragment += val;
+ dev->stats.rx_fragment += (u32)(val - dev->stats.mib_prev.rx_fragment);
+ dev->stats.mib_prev.rx_fragment = val;
val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_JABBER_CNT(port->id));
- dev->stats.rx_jabber += val;
+ dev->stats.rx_jabber += (u32)(val - dev->stats.mib_prev.rx_jabber);
+ dev->stats.mib_prev.rx_jabber = val;
i = 0;
val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_RUNT_CNT(port->id));
- dev->stats.rx_len[i] += val;
+ dev->stats.mib_prev.rx_runt_accum64 +=
+ (u32)(val - dev->stats.mib_prev.rx_runt_cnt);
+ dev->stats.mib_prev.rx_runt_cnt = val;
+
+ /* rx_len[0]: RUNT (32-bit, delta) + E64 (64-bit, absolute) → {0, 64} bucket.
+ * then assign rx_len[0] = rx_runt_accum64 + E64_abs.
+ */
+ dev->stats.rx_len[i] = dev->stats.mib_prev.rx_runt_accum64;
val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_E64_CNT_H(port->id));
- dev->stats.rx_len[i] += ((u64)val << 32);
+ dev->stats.rx_len[i] += (u64)val << 32;
val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_E64_CNT_L(port->id));
dev->stats.rx_len[i++] += val;
val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L64_CNT_H(port->id));
- dev->stats.rx_len[i] += ((u64)val << 32);
+ dev->stats.rx_len[i] = (u64)val << 32;
val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L64_CNT_L(port->id));
dev->stats.rx_len[i++] += val;
val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L127_CNT_H(port->id));
- dev->stats.rx_len[i] += ((u64)val << 32);
+ dev->stats.rx_len[i] = (u64)val << 32;
val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L127_CNT_L(port->id));
dev->stats.rx_len[i++] += val;
val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L255_CNT_H(port->id));
- dev->stats.rx_len[i] += ((u64)val << 32);
+ dev->stats.rx_len[i] = (u64)val << 32;
val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L255_CNT_L(port->id));
dev->stats.rx_len[i++] += val;
val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L511_CNT_H(port->id));
- dev->stats.rx_len[i] += ((u64)val << 32);
+ dev->stats.rx_len[i] = (u64)val << 32;
val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L511_CNT_L(port->id));
dev->stats.rx_len[i++] += val;
val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L1023_CNT_H(port->id));
- dev->stats.rx_len[i] += ((u64)val << 32);
+ dev->stats.rx_len[i] = (u64)val << 32;
val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_L1023_CNT_L(port->id));
dev->stats.rx_len[i++] += val;
val = airoha_fe_rr(eth, REG_FE_GDM_RX_ETH_LONG_CNT(port->id));
- dev->stats.rx_len[i++] += val;
+ dev->stats.rx_len[i] += (u32)(val - dev->stats.mib_prev.rx_long_cnt);
+ dev->stats.mib_prev.rx_long_cnt = val;
u64_stats_update_end(&dev->stats.syncp);
-}
-
-static void airoha_update_hw_stats(struct airoha_gdm_dev *dev)
-{
- struct airoha_gdm_port *port = dev->port;
- int i;
-
- spin_lock(&port->stats_lock);
-
- for (i = 0; i < ARRAY_SIZE(port->devs); i++) {
- if (port->devs[i])
- airoha_dev_get_hw_stats(port->devs[i]);
- }
-
- /* Reset MIB counters */
- airoha_fe_set(dev->eth, REG_FE_GDM_MIB_CLEAR(port->id),
- FE_GDM_MIB_RX_CLEAR_MASK | FE_GDM_MIB_TX_CLEAR_MASK);
spin_unlock(&port->stats_lock);
}
diff --git a/drivers/net/ethernet/airoha/airoha_eth.h b/drivers/net/ethernet/airoha/airoha_eth.h
index f6d01a8e8da1..3af1c49dd62d 100644
--- a/drivers/net/ethernet/airoha/airoha_eth.h
+++ b/drivers/net/ethernet/airoha/airoha_eth.h
@@ -245,6 +245,33 @@ struct airoha_hw_stats {
u64 rx_fragment;
u64 rx_jabber;
u64 rx_len[7];
+
+ struct {
+ /* Previous HW register values for 32-bit counter delta
+ * tracking. Storing the last seen value and accumulating
+ * (u32)(curr - prev) into the 64-bit software counter
+ * handles wrap-around transparently via unsigned arithmetic.
+ * tx_runt_accum64/rx_runt_accum64 hold the running sum of
+ * runt deltas. These fields are never reported to userspace.
+ */
+ u32 tx_drops;
+ u32 tx_broadcast;
+ u32 tx_multicast;
+ u32 tx_runt_cnt;
+ u32 tx_long_cnt;
+ u64 tx_runt_accum64;
+ u32 rx_drops;
+ u32 rx_broadcast;
+ u32 rx_multicast;
+ u32 rx_errors;
+ u32 rx_crc_error;
+ u32 rx_over_errors;
+ u32 rx_fragment;
+ u32 rx_jabber;
+ u32 rx_runt_cnt;
+ u32 rx_long_cnt;
+ u64 rx_runt_accum64;
+ } mib_prev;
};
enum {
base-commit: a225f8c20712713406ae47024b8df42deacddd4a
--
2.43.0
^ permalink raw reply related
* Re: [PATCH v8 19/22] tools/perf: Support event code for arch standard events
From: Ian Rogers @ 2026-07-01 17:44 UTC (permalink / raw)
To: Atish Patra
Cc: Jiri Olsa, Paul Walmsley, Mark Rutland, Rob Herring, Anup Patel,
Namhyung Kim, Arnaldo Carvalho de Melo, Krzysztof Kozlowski,
Will Deacon, James Clark, linux-arm-kernel, linux-riscv,
linux-kernel, devicetree, linux-perf-users, Conor Dooley
In-Reply-To: <20260701-counter_delegation-v8-19-7909f863a645@meta.com>
On Wed, Jul 1, 2026 at 1:48 AM Atish Patra <atish.patra@linux.dev> wrote:
>
> From: Atish Patra <atishp@rivosinc.com>
>
> RISC-V relies on the event encoding from the json file. That includes
> arch standard events. If event code is present, event is already updated
> with correct encoding. No need to update it again which results in losing
> the event encoding.
>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Ian Rogers <irogers@google.com>
Thanks,
Ian
> ---
> tools/perf/pmu-events/arch/riscv/arch-standard.json | 10 ++++++++++
> tools/perf/pmu-events/jevents.py | 9 ++++++++-
> 2 files changed, 18 insertions(+), 1 deletion(-)
>
> diff --git a/tools/perf/pmu-events/arch/riscv/arch-standard.json b/tools/perf/pmu-events/arch/riscv/arch-standard.json
> new file mode 100644
> index 000000000000..96e21f088558
> --- /dev/null
> +++ b/tools/perf/pmu-events/arch/riscv/arch-standard.json
> @@ -0,0 +1,10 @@
> +[
> + {
> + "EventName": "cycles",
> + "BriefDescription": "cycle executed"
> + },
> + {
> + "EventName": "instructions",
> + "BriefDescription": "instruction retired"
> + }
> +]
> diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py
> index 3a1bcdcdc685..0cf9d26315b3 100755
> --- a/tools/perf/pmu-events/jevents.py
> +++ b/tools/perf/pmu-events/jevents.py
> @@ -413,7 +413,14 @@ class JsonEvent:
> self.long_desc = None
> if arch_std:
> if arch_std.lower() in _arch_std_events:
> - event = _arch_std_events[arch_std.lower()].event
> + # Inherit the arch-standard encoding only if this event defines no
> + # explicit encoding of its own. Events with explicit EventCode,
> + # ConfigCode, etc. may carry alternate encodings and appended modifiers
> + # that must survive.
> + if ('EventCode' not in jd and 'ExtSel' not in jd and
> + configcode is None and eventidcode is None and
> + legacy_hw_config is None and legacy_cache_config is None):
> + event = _arch_std_events[arch_std.lower()].event
> # Copy from the architecture standard event to self for undefined fields.
> for attr, value in _arch_std_events[arch_std.lower()].__dict__.items():
> if hasattr(self, attr) and not getattr(self, attr):
>
> --
> 2.53.0-Meta
>
^ permalink raw reply
* Re: [PATCH v8 20/22] tools/perf: Add RISC-V CounterIDMask event field
From: Ian Rogers @ 2026-07-01 17:44 UTC (permalink / raw)
To: Atish Patra
Cc: Jiri Olsa, Paul Walmsley, Mark Rutland, Rob Herring, Anup Patel,
Namhyung Kim, Arnaldo Carvalho de Melo, Krzysztof Kozlowski,
Will Deacon, James Clark, linux-arm-kernel, linux-riscv,
linux-kernel, devicetree, linux-perf-users, Conor Dooley
In-Reply-To: <20260701-counter_delegation-v8-20-7909f863a645@meta.com>
On Wed, Jul 1, 2026 at 1:48 AM Atish Patra <atish.patra@linux.dev> wrote:
>
> From: Atish Patra <atishp@rivosinc.com>
>
> Counter delegation lets supervisor mode choose the hpmcounter for an event,
> but the hardware may only allow a given event on a subset of counters. Add
> a RISC-V specific "CounterIDMask" json event field, handled like the other
> arch-specific entries in event_fields[], that carries the allowed-counter
> bitmask through to the driver's existing counterid_mask (config2:0-31)
> format.
>
> The value is the bitmask directly so no counter-list to bitmask
> conversion is needed, and because the field is RISC-V specific it is a
> no-op for every other architecture's events (unlike the shared "Counter"
> field).
>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Ian Rogers <irogers@google.com>
Thanks,
Ian
> ---
> tools/perf/pmu-events/jevents.py | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py
> index 0cf9d26315b3..516fb73886ed 100755
> --- a/tools/perf/pmu-events/jevents.py
> +++ b/tools/perf/pmu-events/jevents.py
> @@ -396,6 +396,7 @@ class JsonEvent:
> ('EnAllSlices', 'enallslices='),
> ('SliceId', 'sliceid='),
> ('ThreadMask', 'threadmask='),
> + ('CounterIDMask', 'counterid_mask='),
> ]
> for key, value in event_fields:
> if key in jd and not is_zero(jd[key]):
>
> --
> 2.53.0-Meta
>
^ permalink raw reply
* [PATCH] iommu/arm-smmu-v3: Add HAFT support for SVA
From: Robin Murphy @ 2026-07-01 17:45 UTC (permalink / raw)
To: will, joro
Cc: jpb, catalin.marinas, yangyicong, linux-arm-kernel, iommu, stable
Since table access flags cannot be software-managed, if process
pagetables are using HAFT then SVA must require the SMMU to support and
enable it too, otherwise page aging is liable to get out of whack.
Cc: <stable@vger.kernel.org>
Fixes: 62df5870ebf7 ("arm64: Enable ARCH_HAS_NONLEAF_PMD_YOUNG")
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 5 +++++
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 6 ++++++
drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 3 +++
3 files changed, 14 insertions(+)
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c
index 1ed8a6f29dc4..ef11e9493f93 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c
@@ -102,6 +102,8 @@ void arm_smmu_make_sva_cd(struct arm_smmu_cd *target,
target->data[0] |= cpu_to_le64(CTXDESC_CD_0_TCR_HA);
if (master->smmu->features & ARM_SMMU_FEAT_HD)
target->data[0] |= cpu_to_le64(CTXDESC_CD_0_TCR_HD);
+ if (master->smmu->features & ARM_SMMU_FEAT_HAFT && system_supports_haft())
+ target->data[1] |= cpu_to_le64(CTXDESC_CD_1_HAFT);
} else {
target->data[0] |= cpu_to_le64(CTXDESC_CD_0_TCR_EPD0);
@@ -211,6 +213,9 @@ bool arm_smmu_sva_supported(struct arm_smmu_device *smmu)
if (system_supports_bbml2_noabort())
feat_mask |= ARM_SMMU_FEAT_BBML2;
+ if (system_supports_haft())
+ feat_mask |= ARM_SMMU_FEAT_HAFT;
+
if ((smmu->features & feat_mask) != feat_mask)
return false;
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
index a10affb483a4..7637e9128533 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c
@@ -4925,6 +4925,9 @@ static void arm_smmu_get_httu(struct arm_smmu_device *smmu, u32 reg)
u32 hw_features = 0;
switch (FIELD_GET(IDR0_HTTU, reg)) {
+ case IDR0_HTTU_ACCESS_DIRTY_HAFT:
+ hw_features |= ARM_SMMU_FEAT_HAFT;
+ fallthrough;
case IDR0_HTTU_ACCESS_DIRTY:
hw_features |= ARM_SMMU_FEAT_HD;
fallthrough;
@@ -5256,6 +5259,9 @@ static int arm_smmu_device_acpi_probe(struct platform_device *pdev,
smmu->features |= ARM_SMMU_FEAT_COHERENCY;
switch (FIELD_GET(ACPI_IORT_SMMU_V3_HTTU_OVERRIDE, iort_smmu->flags)) {
+ case IDR0_HTTU_ACCESS_DIRTY_HAFT:
+ smmu->features |= ARM_SMMU_FEAT_HAFT;
+ fallthrough;
case IDR0_HTTU_ACCESS_DIRTY:
smmu->features |= ARM_SMMU_FEAT_HD;
fallthrough;
diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
index c909c9a88538..61a7df5afb99 100644
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h
@@ -40,6 +40,7 @@ struct arm_vsmmu;
#define IDR0_HTTU GENMASK(7, 6)
#define IDR0_HTTU_ACCESS 1
#define IDR0_HTTU_ACCESS_DIRTY 2
+#define IDR0_HTTU_ACCESS_DIRTY_HAFT 3
#define IDR0_COHACC (1 << 4)
#define IDR0_TTF GENMASK(3, 2)
#define IDR0_TTF_AARCH64 2
@@ -369,6 +370,7 @@ static inline unsigned int arm_smmu_cdtab_l2_idx(unsigned int ssid)
#define CTXDESC_CD_0_ASET (1UL << 47)
#define CTXDESC_CD_0_ASID GENMASK_ULL(63, 48)
+#define CTXDESC_CD_1_HAFT (1UL << 3)
#define CTXDESC_CD_1_TTB0_MASK GENMASK_ULL(51, 4)
/*
@@ -921,6 +923,7 @@ struct arm_smmu_device {
#define ARM_SMMU_FEAT_HD (1 << 22)
#define ARM_SMMU_FEAT_S2FWB (1 << 23)
#define ARM_SMMU_FEAT_BBML2 (1 << 24)
+#define ARM_SMMU_FEAT_HAFT (1 << 25)
u32 features;
#define ARM_SMMU_OPT_SKIP_PREFETCH (1 << 0)
--
2.54.0.dirty
^ permalink raw reply related
* [PATCH 6/7] arm64: dts: mediatek: mt8192: Add and use UART AP_DMA controller
From: AngeloGioacchino Del Regno @ 2026-07-01 12:19 UTC (permalink / raw)
To: linux-mediatek
Cc: robh, krzk+dt, conor+dt, matthias.bgg, angelogioacchino.delregno,
devicetree, linux-kernel, linux-arm-kernel, kernel, justin.yeh
In-Reply-To: <20260701121929.19374-1-angelogioacchino.delregno@collabora.com>
This SoC has a DMA controller (AP_DMA) that provides one channel
for each data direction (transmit and receive) for all of the
UART controllers in the SoC.
In order to increase the efficiency of data TX/RX over the UART
controllers, add the UART DMA controller and assign the right
channels to its two uart controllers.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 465567c3be54..d05a5ac61534 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -732,6 +732,19 @@ spmi: spmi@10027000 {
assigned-clock-parents = <&topckgen CLK_TOP_OSC_D10>;
};
+ apdma: dma-controller@10217a80 {
+ compatible = "mediatek,mt8192-uart-dma", "mediatek,mt6835-uart-dma";
+ reg = <0 0x10217a80 0 0x80>, <0 0x10217b00 0 0x80>,
+ <0 0x10217b80 0 0x80>, <0 0x10217c00 0 0x80>;
+ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&infracfg CLK_INFRA_AP_DMA>;
+ #dma-cells = <1>;
+ dma-requests = <4>;
+ };
+
gce: mailbox@10228000 {
compatible = "mediatek,mt8192-gce";
reg = <0 0x10228000 0 0x4000>;
@@ -756,6 +769,8 @@ uart0: serial@11002000 {
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
clock-names = "baud", "bus";
+ dmas = <&apdma 0>, <&apdma 1>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -766,6 +781,8 @@ uart1: serial@11003000 {
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
clock-names = "baud", "bus";
+ dmas = <&apdma 2>, <&apdma 3>;
+ dma-names = "tx", "rx";
status = "disabled";
};
--
2.54.0
^ permalink raw reply related
* [PATCH 09/10] dt-bindings: display: mediatek: wdma: Add compatibles for more SoCs
From: AngeloGioacchino Del Regno @ 2026-07-01 12:19 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, maarten.lankhorst, mripard, tzimmermann, airlied, simona,
robh, krzk+dt, conor+dt, matthias.bgg, angelogioacchino.delregno,
jitao.shi, dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, kernel, justin.yeh, jason-jh.lin
In-Reply-To: <20260701121950.19454-1-angelogioacchino.delregno@collabora.com>
Multiple MediaTek SoCs have the Write DMA hardware in their Display
Controller: add the missing compatibles for Dimensity 1200 (MT6893)
and for Kompanio 500/520/820/1200 (MT8183/MT8186/MT8192/MT8195).
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
.../devicetree/bindings/display/mediatek/mediatek,wdma.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
index 97d052b0fb61..c3ed867d058d 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml
@@ -22,11 +22,16 @@ properties:
compatible:
oneOf:
- enum:
+ - mediatek,mt6893-disp-wdma
- mediatek,mt8173-disp-wdma
- items:
- enum:
- mediatek,mt6795-disp-wdma
- mediatek,mt8167-disp-wdma
+ - mediatek,mt8183-disp-wdma
+ - mediatek,mt8186-disp-wdma
+ - mediatek,mt8192-disp-wdma
+ - mediatek,mt8195-disp-wdma
- const: mediatek,mt8173-disp-wdma
reg:
--
2.54.0
^ permalink raw reply related
* Re: [PATCH v7 0/2] add mcf54415 DAC driver
From: Jonathan Cameron @ 2026-07-01 18:00 UTC (permalink / raw)
To: Angelo Dureghello
Cc: David Lechner, Nuno Sá, Andy Shevchenko, Geert Uytterhoeven,
Maxime Coquelin, Alexandre Torgue, linux-kernel, linux-iio,
linux-m68k, linux-stm32, linux-arm-kernel, Andy Shevchenko
In-Reply-To: <20260701-wip-stmark2-dac-v7-0-ff8fdcc8010a@baylibre.com>
On Wed, 01 Jul 2026 16:17:22 +0200
Angelo Dureghello <adureghello@baylibre.com> wrote:
> This patchset adds a minimalistic DAC driver for the NXP mcf54415/6/7/8
> builtin DACs.
Applied patch 1 to the testing branch of iio.git.
Thanks,
Jonathan
^ permalink raw reply
* [PATCH 07/10] drm/mediatek: mtk_dsi: Add support for MT8196
From: AngeloGioacchino Del Regno @ 2026-07-01 12:19 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, maarten.lankhorst, mripard, tzimmermann, airlied, simona,
robh, krzk+dt, conor+dt, matthias.bgg, angelogioacchino.delregno,
jitao.shi, dri-devel, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, kernel, justin.yeh, jason-jh.lin
In-Reply-To: <20260701121950.19454-1-angelogioacchino.delregno@collabora.com>
Add support for the new DSI IP found in the Kompanio Ultra MT8196
SoC and its Dimensity and Genio variants.
Differently from the older DSI IPs, the one from MT8196 requires
the initialization of all of the QoS parameters and can make use
of a DSI SRAM reserved buffer (present also on older SoCs but not
mandatory on those).
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 +
drivers/gpu/drm/mediatek/mtk_dsi.c | 197 +++++++++++++++++++++++++
2 files changed, 199 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index bd2d17017bd2..9a4c59849c4b 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -826,6 +826,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DSI },
{ .compatible = "mediatek,mt8188-dsi",
.data = (void *)MTK_DSI },
+ { .compatible = "mediatek,mt8196-dsi",
+ .data = (void *)MTK_DSI },
{ }
};
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
index ba96c12a8ceb..fc6f846208d6 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -153,6 +153,18 @@
#define FORCE_COMMIT BIT(0)
#define BYPASS_SHADOW BIT(1)
+/* DSI_VDE */
+#define VDE_BLOCK_ULTRA BIT(29)
+
+/* DSI_BUF_CON0 */
+#define DSI_QOS_BUF_EN BIT(0)
+
+/* DSI_BUF_CON1 */
+#define BUF_OUT_VALID_THRESH GENMASK(14, 0)
+
+/* DSI_BUF_SODI_HIGH, SODI_LOW and other BUF registers */
+#define BUF_THRESHOLD_PARAM GENMASK(19, 0)
+
/* CMDQ related bits */
#define CONFIG GENMASK(7, 0)
#define SHORT_PACKET 0
@@ -165,6 +177,16 @@
#define NS_TO_CYCLE(n, c) ((n) / (c) + (((n) % (c)) ? 1 : 0))
+/* HW QoS and Anti-Latency Buffer related bits */
+#define MTK_DSI_MAX_FIFO_BYTES 1554
+#define MTK_DSI_DEFAULT_QOS_VALID_FIFO_US 25
+#define MTK_DSI_DEFAULT_QOS_PREULTRA_HI_US 36
+#define MTK_DSI_DEFAULT_QOS_PREULTRA_LO_US 35
+#define MTK_DSI_DEFAULT_QOS_ULTRA_HI_US 26
+#define MTK_DSI_DEFAULT_QOS_ULTRA_LO_US 25
+#define MTK_DSI_DEFAULT_QOS_URGENT_LO_US 11
+#define MTK_DSI_DEFAULT_QOS_URGENT_HI_US 12
+
#define MTK_DSI_HOST_IS_READ(type) \
((type == MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM) || \
(type == MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM) || \
@@ -207,9 +229,26 @@ enum mtk_dsi_adv_regidx {
DSI_VM_CMD_CON,
DSI_SHADOW_DEBUG,
DSI_CMDQ,
+ DSI_VDE,
DSI_ADV_REG_MAX
};
+enum mtk_dsi_qos_regidx {
+ DSI_QOS_BUF_CON0,
+ DSI_QOS_BUF_CON1,
+ DSI_QOS_TX_BUF_RW_TIMES,
+ DSI_QOS_SODI_HIGH,
+ DSI_QOS_SODI_LOW,
+ DSI_QOS_PREULTRA_HIGH,
+ DSI_QOS_PREULTRA_LOW,
+ DSI_QOS_ULTRA_HIGH,
+ DSI_QOS_ULTRA_LOW,
+ DSI_QOS_URGENT_HIGH,
+ DSI_QOS_URGENT_LOW,
+ DSI_QOS_PREURGENT_HIGH,
+ DSI_QOS_REG_MAX
+};
+
struct mtk_phy_timing {
u32 lpx;
u32 da_hs_prepare;
@@ -234,8 +273,12 @@ struct phy;
struct mtk_dsi_driver_data {
const u16 *reg_main;
const u16 *reg_adv;
+ const u16 *reg_qos;
const u16 max_link_rate_mbps;
+ const u8 dsi_sram_bytes;
+ const u8 pixels_per_iter;
+ const u8 num_burst_lines;
bool has_size_ctl;
bool cmdq_long_packet_ctl;
@@ -329,6 +372,59 @@ static const u16 mtk_dsi_regs_mt8186[DSI_ADV_REG_MAX] = {
[DSI_CMDQ] = 0xd00,
};
+static const u16 mtk_dsi_regs_main_v2[DSI_MAIN_REG_MAX] = {
+ [DSI_START] = 0x00,
+ [DSI_INTEN] = 0x08,
+ [DSI_INTSTA] = 0x0c,
+ [DSI_CON_CTRL] = 0x30,
+ [DSI_MODE_CTRL] = 0x34,
+ [DSI_TXRX_CTRL] = 0x38,
+ [DSI_PSCTRL] = 0x3c,
+ [DSI_VSA_NL] = 0x60,
+ [DSI_VBP_NL] = 0x64,
+ [DSI_VFP_NL] = 0x68,
+ [DSI_VACT_NL] = 0x6c,
+ [DSI_SIZE_CON] = 0x2c,
+ [DSI_HSA_WC] = 0x80,
+ [DSI_HBP_WC] = 0x84,
+ [DSI_HFP_WC] = 0x88,
+ [DSI_CMDQ_SIZE] = 0x44,
+ [DSI_HSTX_CKL_WC] = 0x100,
+ [DSI_RX_DATA0] = 0xa4,
+ [DSI_RX_DATA1] = 0xa8,
+ [DSI_RX_DATA2] = 0xac,
+ [DSI_RX_DATA3] = 0xb0,
+ [DSI_RACK] = 0xb4,
+ [DSI_PHY_LCCON] = 0x7d0,
+ [DSI_PHY_LD0CON] = 0x7d4,
+ [DSI_PHY_TIMECON0] = 0x600,
+ [DSI_PHY_TIMECON1] = 0x604,
+ [DSI_PHY_TIMECON2] = 0x608,
+ [DSI_PHY_TIMECON3] = 0x60c,
+};
+
+static const u16 mtk_dsi_regs_qos_v2[DSI_QOS_REG_MAX] = {
+ [DSI_QOS_BUF_CON0] = 0x300,
+ [DSI_QOS_BUF_CON1] = 0x304,
+ [DSI_QOS_TX_BUF_RW_TIMES] = 0x310,
+ [DSI_QOS_SODI_HIGH] = 0x314,
+ [DSI_QOS_SODI_LOW] = 0x318,
+ [DSI_QOS_PREULTRA_HIGH] = 0x324,
+ [DSI_QOS_PREULTRA_LOW] = 0x328,
+ [DSI_QOS_ULTRA_HIGH] = 0x32c,
+ [DSI_QOS_ULTRA_LOW] = 0x330,
+ [DSI_QOS_URGENT_HIGH] = 0x334,
+ [DSI_QOS_URGENT_LOW] = 0x338,
+ [DSI_QOS_PREURGENT_HIGH] = 0x33c
+};
+
+static const u16 mtk_dsi_regs_mt8196[DSI_ADV_REG_MAX] = {
+ [DSI_VM_CMD_CON] = 0x110,
+ [DSI_SHADOW_DEBUG] = 0xd0,
+ [DSI_CMDQ] = 0x400,
+ [DSI_VDE] = 0x3f8,
+};
+
static inline struct mtk_dsi *bridge_to_dsi(struct drm_bridge *b)
{
return container_of(b, struct mtk_dsi, bridge);
@@ -752,6 +848,89 @@ static int mtk_dsi_set_dsc_params(struct mtk_dsi *dsi)
return drm_dsc_compute_rc_parameters(dsc);
}
+static void mtk_dsi_config_hw_buffers(struct mtk_dsi *dsi)
+{
+ const struct mtk_dsi_driver_data *data = dsi->driver_data;
+ const u16 *reg_qos = data->reg_qos;
+ u32 buffer_unit, sram_unit, num_hw_buffers;
+ u32 preultra_hi, preultra_lo;
+ u32 urgent_hi, urgent_lo;
+ u32 ultra_hi, ultra_lo;
+ u32 sodi_hi, sodi_lo;
+ u32 data_rate_per_buf;
+ u32 out_valid_thresh;
+ u32 dsi_buf_bpp;
+ u32 fill_rate;
+ u32 pclk_mhz;
+ u32 rw_times;
+ u32 val;
+
+ /*
+ * At the time of writing, only MT8196 is implemented and, for this SoC,
+ * the buffer unit is equal to the SRAM bytes.
+ *
+ * There are other SoCs already out in the wild that do support the HW
+ * buffers and that have different sizes, so keep the calculation as-is!
+ */
+ buffer_unit = data->dsi_sram_bytes;
+ sram_unit = data->dsi_sram_bytes;
+ num_hw_buffers = sram_unit / buffer_unit;
+
+ if (data->support_per_frame_lp)
+ val = CMDMODE_WAIT_DATA_EVERY_LINE_EN;
+ else
+ val = 0;
+
+ mtk_dsi_mask(dsi, data->reg_main[DSI_CON_CTRL],
+ CMDMODE_WAIT_DATA_EVERY_LINE_EN, val);
+
+ data_rate_per_buf = dsi->data_rate * dsi->lanes / 8 / buffer_unit;
+
+ /* Calculate valid threshold and avoid exceeding FIFO size */
+ out_valid_thresh = MTK_DSI_DEFAULT_QOS_VALID_FIFO_US * data_rate_per_buf;
+ out_valid_thresh = min(out_valid_thresh, MTK_DSI_MAX_FIFO_BYTES - 1);
+ mtk_dsi_mask(dsi, reg_qos[DSI_QOS_BUF_CON1], BUF_OUT_VALID_THRESH, out_valid_thresh);
+
+ /* Enable ULTRA signal trigger between SOF and VACT */
+ mtk_dsi_mask(dsi, data->reg_adv[DSI_VDE], VDE_BLOCK_ULTRA, 0);
+
+ /* Calculate fill rate with line counter mode for DSI Video Mode */
+ if (dsi->format == MIPI_DSI_FMT_RGB565)
+ dsi_buf_bpp = 2;
+ else
+ dsi_buf_bpp = 3;
+
+ pclk_mhz = dsi->vm.pixelclock / HZ_PER_MHZ;
+ fill_rate = pclk_mhz * data->pixels_per_iter * dsi_buf_bpp / buffer_unit;
+
+ /* Calculate QoS Anti-Latency parameters */
+ sodi_hi = MTK_DSI_MAX_FIFO_BYTES * num_hw_buffers;
+ sodi_hi -= (fill_rate - data_rate_per_buf) * 12 / 10;
+ sodi_lo = (23 + 5) * data_rate_per_buf;
+ preultra_hi = MTK_DSI_DEFAULT_QOS_PREULTRA_HI_US * data_rate_per_buf;
+ preultra_lo = MTK_DSI_DEFAULT_QOS_PREULTRA_LO_US * data_rate_per_buf;
+ ultra_hi = MTK_DSI_DEFAULT_QOS_ULTRA_HI_US * data_rate_per_buf;
+ ultra_lo = MTK_DSI_DEFAULT_QOS_ULTRA_LO_US * data_rate_per_buf;
+ urgent_hi = MTK_DSI_DEFAULT_QOS_URGENT_HI_US * data_rate_per_buf;
+ urgent_lo = MTK_DSI_DEFAULT_QOS_URGENT_LO_US * data_rate_per_buf;
+ rw_times = dsi->vm.vactive * dsi_buf_bpp;
+ rw_times /= data->num_burst_lines * data->pixels_per_iter;
+
+ /* Write all QoS parameters: Screen On Deep Idle, (pre)Ultra, Urgent, RW times */
+ mtk_dsi_mask(dsi, reg_qos[DSI_QOS_SODI_HIGH], BUF_THRESHOLD_PARAM, sodi_hi);
+ mtk_dsi_mask(dsi, reg_qos[DSI_QOS_SODI_LOW], BUF_THRESHOLD_PARAM, sodi_lo);
+ mtk_dsi_mask(dsi, reg_qos[DSI_QOS_PREULTRA_HIGH], BUF_THRESHOLD_PARAM, preultra_hi);
+ mtk_dsi_mask(dsi, reg_qos[DSI_QOS_PREULTRA_LOW], BUF_THRESHOLD_PARAM, preultra_lo);
+ mtk_dsi_mask(dsi, reg_qos[DSI_QOS_ULTRA_HIGH], BUF_THRESHOLD_PARAM, ultra_hi);
+ mtk_dsi_mask(dsi, reg_qos[DSI_QOS_ULTRA_LOW], BUF_THRESHOLD_PARAM, ultra_lo);
+ mtk_dsi_mask(dsi, reg_qos[DSI_QOS_URGENT_HIGH], BUF_THRESHOLD_PARAM, urgent_hi);
+ mtk_dsi_mask(dsi, reg_qos[DSI_QOS_URGENT_LOW], BUF_THRESHOLD_PARAM, urgent_lo);
+ writel(rw_times, dsi->regs + reg_qos[DSI_QOS_TX_BUF_RW_TIMES]);
+
+ /* Finally, activate internal line-buffering */
+ mtk_dsi_mask(dsi, reg_qos[DSI_QOS_BUF_CON0], DSI_QOS_BUF_EN, DSI_QOS_BUF_EN);
+}
+
static int mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
{
const struct mtk_dsi_driver_data *data = dsi->driver_data;
@@ -929,6 +1108,10 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi)
mtk_dsi_reset_engine(dsi);
mtk_dsi_phy_timconfig(dsi);
+ /* Setup HW FIFO if DSI supports QoS Anti-Latency buffers */
+ if (data->dsi_sram_bytes && data->reg_qos)
+ mtk_dsi_config_hw_buffers(dsi);
+
mtk_dsi_ps_control(dsi, true);
mtk_dsi_set_vm_cmd(dsi);
ret = mtk_dsi_config_vdo_timing(dsi);
@@ -1549,6 +1732,19 @@ static const struct mtk_dsi_driver_data mt8189_dsi_driver_data = {
.support_per_frame_lp = true,
};
+static const struct mtk_dsi_driver_data mt8196_dsi_driver_data = {
+ .reg_main = mtk_dsi_regs_main_v2,
+ .reg_qos = mtk_dsi_regs_qos_v2,
+ .reg_adv = mtk_dsi_regs_mt8196,
+ .max_link_rate_mbps = 2000,
+ .dsi_sram_bytes = 32,
+ .pixels_per_iter = 2,
+ .num_burst_lines = 8,
+ .has_size_ctl = true,
+ .cmdq_long_packet_ctl = true,
+ .support_per_frame_lp = true,
+};
+
static const struct of_device_id mtk_dsi_of_match[] = {
{ .compatible = "mediatek,mt2701-dsi", .data = &mt2701_dsi_driver_data },
{ .compatible = "mediatek,mt8173-dsi", .data = &mt8173_dsi_driver_data },
@@ -1556,6 +1752,7 @@ static const struct of_device_id mtk_dsi_of_match[] = {
{ .compatible = "mediatek,mt8186-dsi", .data = &mt8186_dsi_driver_data },
{ .compatible = "mediatek,mt8188-dsi", .data = &mt8188_dsi_driver_data },
{ .compatible = "mediatek,mt8189-dsi", .data = &mt8189_dsi_driver_data },
+ { .compatible = "mediatek,mt8196-dsi", .data = &mt8196_dsi_driver_data },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mtk_dsi_of_match);
--
2.54.0
^ permalink raw reply related
* [PATCH v7 02/11] arm64: dts: ti: k3-am62d2-evm: Fix wkup R5F memory region size
From: Markus Schneider-Pargmann (TI) @ 2026-07-01 12:39 UTC (permalink / raw)
To: Nishanth Menon, Vignesh Raghavendra, Tero Kristo, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Nathan Chancellor,
Nick Desaulniers, Bill Wendling, Justin Stitt, Judith Mendez,
Daniel Schultz, Andrew Davis, Siddharth Vadapalli, Paresh Bhagat,
Bryan Brattlof, Jai Luthra, Devarsh Thakkar, Beleswar Padhi,
Francesco Dolcini, Stefano Radaelli
Cc: Vishal Mahaveer, Kevin Hilman, Sebin Francis, Kendall Willis,
Akashdeep Kaur, linux-arm-kernel, devicetree, linux-kernel, llvm,
Hari Nagalla, Markus Schneider-Pargmann (TI)
In-Reply-To: <20260701-topic-am62a-ioddr-dt-v6-19-v7-0-e9db8b16821a@baylibre.com>
The wkup_r5fss0_core0_memory_region was reserved with only
0x0f00000 but the MCU SDK linker for the wkup R5F firmware on
AM62A defines the DM code/data DDR footprint differently:
/* DDR for DM R5F code/data [ size 27 MiB + 364 KB ] */
DDR : ORIGIN = 0x9CAA5000 LENGTH = 0x1B5B000
which results in an end at 0x9e600000. For this memory region which
starts at 0x9c900000 this means a length of:
0x9e600000 - 0x9c900000 = 0x1d00000
Link: https://github.com/TexasInstruments/mcupsdk-core-k3/blob/k3_main/examples/drivers/ipc/ipc_rpmsg_echo_linux/am62ax-sk/r5fss0-0_freertos/ti-arm-clang/linker.cmd
Fixes: 1544bca2f188 ("arm64: dts: ti: Add support for AM62D2-EVM")
Signed-off-by: Markus Schneider-Pargmann (TI) <msp@baylibre.com>
---
arch/arm64/boot/dts/ti/k3-am62d2-evm.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts
index f5ceb6a1b5debabf1ead67eea634b48db1540186..463a3f6130b8f2927a032137e87c01df446cffda 100644
--- a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts
@@ -67,7 +67,7 @@ wkup_r5fss0_core0_dma_memory_region: memory@9c800000 {
wkup_r5fss0_core0_memory_region: memory@9c900000 {
compatible = "shared-dma-pool";
- reg = <0x00 0x9c900000 0x00 0xf00000>;
+ reg = <0x00 0x9c900000 0x00 0x01d00000>;
no-map;
bootph-pre-ram;
};
--
2.53.0
^ permalink raw reply related
* [PATCH 6/6] soc: mediatek: mtk-mmsys: Use MMSYS_ROUTE() in default routing table
From: AngeloGioacchino Del Regno @ 2026-07-01 12:20 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, maarten.lankhorst, mripard, tzimmermann, airlied, simona,
robh, krzk+dt, conor+dt, mcoquelin.stm32, alexandre.torgue,
matthias.bgg, angelogioacchino.delregno, andi.shyti, djakov,
broonie, jitao.shi, ck.hu, dri-devel, linux-mediatek, devicetree,
linux-kernel, linux-stm32, linux-arm-kernel, justin.yeh,
jason-jh.lin, kernel
In-Reply-To: <20260701122043.19612-1-angelogioacchino.delregno@collabora.com>
All of the mtk_mmsys_routes tables for all SoCs were converted to
use the MMSYS_ROUTE() macro but the default one used for MT2701,
MT2712 and SoCs from that generation was not: convert this one as
well.
This brings no functional change.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/soc/mediatek/mtk-mmsys.h | 279 +++++++++++++------------------
1 file changed, 114 insertions(+), 165 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index b37d859b6c14..d534d43aad6f 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -157,171 +157,120 @@ struct mtk_mmsys_driver_data {
* to an independent table.
*/
static const struct mtk_mmsys_routes mmsys_default_routing_table[] = {
- {
- DDP_COMPONENT_BLS, DDP_COMPONENT_DSI0,
- DISP_REG_CONFIG_OUT_SEL, BLS_RDMA1_DSI_DPI_MASK,
- BLS_TO_DSI_RDMA1_TO_DPI1
- }, {
- DDP_COMPONENT_BLS, DDP_COMPONENT_DSI0,
- DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_MASK,
- DSI_SEL_IN_BLS
- }, {
- DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0,
- DISP_REG_CONFIG_OUT_SEL, BLS_RDMA1_DSI_DPI_MASK,
- BLS_TO_DPI_RDMA1_TO_DSI
- }, {
- DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0,
- DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_MASK,
- DSI_SEL_IN_RDMA
- }, {
- DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0,
- DISP_REG_CONFIG_DPI_SEL, DPI_SEL_IN_MASK,
- DPI_SEL_IN_BLS
- }, {
- DDP_COMPONENT_GAMMA, DDP_COMPONENT_RDMA1,
- DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN, GAMMA_MOUT_EN_RDMA1,
- GAMMA_MOUT_EN_RDMA1
- }, {
- DDP_COMPONENT_OD0, DDP_COMPONENT_RDMA0,
- DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD_MOUT_EN_RDMA0,
- OD_MOUT_EN_RDMA0
- }, {
- DDP_COMPONENT_OD1, DDP_COMPONENT_RDMA1,
- DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD1_MOUT_EN_RDMA1,
- OD1_MOUT_EN_RDMA1
- }, {
- DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
- DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0,
- OVL0_MOUT_EN_COLOR0
- }, {
- DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
- DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0,
- COLOR0_SEL_IN_OVL0
- }, {
- DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
- DISP_REG_CONFIG_DISP_OVL_MOUT_EN, OVL_MOUT_EN_RDMA,
- OVL_MOUT_EN_RDMA
- }, {
- DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1,
- DISP_REG_CONFIG_DISP_OVL1_MOUT_EN, OVL1_MOUT_EN_COLOR1,
- OVL1_MOUT_EN_COLOR1
- }, {
- DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1,
- DISP_REG_CONFIG_DISP_COLOR1_SEL_IN, COLOR1_SEL_IN_OVL1,
- COLOR1_SEL_IN_OVL1
- }, {
- DDP_COMPONENT_RDMA0, DDP_COMPONENT_DPI0,
- DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
- RDMA0_SOUT_DPI0
- }, {
- DDP_COMPONENT_RDMA0, DDP_COMPONENT_DPI1,
- DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
- RDMA0_SOUT_DPI1
- }, {
- DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI1,
- DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
- RDMA0_SOUT_DSI1
- }, {
- DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI2,
- DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
- RDMA0_SOUT_DSI2
- }, {
- DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI3,
- DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
- RDMA0_SOUT_DSI3
- }, {
- DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
- DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
- RDMA1_SOUT_DPI0
- }, {
- DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
- DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_MASK,
- DPI0_SEL_IN_RDMA1
- }, {
- DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI1,
- DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
- RDMA1_SOUT_DPI1
- }, {
- DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI1,
- DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_MASK,
- DPI1_SEL_IN_RDMA1
- }, {
- DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI0,
- DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_MASK,
- DSI0_SEL_IN_RDMA1
- }, {
- DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI1,
- DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
- RDMA1_SOUT_DSI1
- }, {
- DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI1,
- DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_MASK,
- DSI1_SEL_IN_RDMA1
- }, {
- DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI2,
- DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
- RDMA1_SOUT_DSI2
- }, {
- DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI2,
- DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_MASK,
- DSI2_SEL_IN_RDMA1
- }, {
- DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI3,
- DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
- RDMA1_SOUT_DSI3
- }, {
- DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI3,
- DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_MASK,
- DSI3_SEL_IN_RDMA1
- }, {
- DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI0,
- DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
- RDMA2_SOUT_DPI0
- }, {
- DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI0,
- DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_MASK,
- DPI0_SEL_IN_RDMA2
- }, {
- DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI1,
- DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
- RDMA2_SOUT_DPI1
- }, {
- DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI1,
- DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_MASK,
- DPI1_SEL_IN_RDMA2
- }, {
- DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI0,
- DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_MASK,
- DSI0_SEL_IN_RDMA2
- }, {
- DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI1,
- DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
- RDMA2_SOUT_DSI1
- }, {
- DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI1,
- DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_MASK,
- DSI1_SEL_IN_RDMA2
- }, {
- DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI2,
- DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
- RDMA2_SOUT_DSI2
- }, {
- DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI2,
- DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_MASK,
- DSI2_SEL_IN_RDMA2
- }, {
- DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI3,
- DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
- RDMA2_SOUT_DSI3
- }, {
- DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI3,
- DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_MASK,
- DSI3_SEL_IN_RDMA2
- }, {
- DDP_COMPONENT_UFOE, DDP_COMPONENT_DSI0,
- DISP_REG_CONFIG_DISP_UFOE_MOUT_EN, UFOE_MOUT_EN_DSI0,
- UFOE_MOUT_EN_DSI0
- }
+ MMSYS_ROUTE(BLS, 0, DSI, 0,
+ DISP_REG_CONFIG_OUT_SEL, BLS_RDMA1_DSI_DPI_MASK,
+ BLS_TO_DSI_RDMA1_TO_DPI1),
+ MMSYS_ROUTE(BLS, 0, DSI, 0,
+ DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_MASK,
+ DSI_SEL_IN_BLS),
+ MMSYS_ROUTE(BLS, 0, DPI, 0,
+ DISP_REG_CONFIG_OUT_SEL, BLS_RDMA1_DSI_DPI_MASK,
+ BLS_TO_DPI_RDMA1_TO_DSI),
+ MMSYS_ROUTE(BLS, 0, DPI, 0,
+ DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_MASK,
+ DSI_SEL_IN_RDMA),
+ MMSYS_ROUTE(BLS, 0, DPI, 0,
+ DISP_REG_CONFIG_DPI_SEL, DPI_SEL_IN_MASK,
+ DPI_SEL_IN_BLS),
+ MMSYS_ROUTE(GAMMA, 0, RDMA, 1,
+ DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN, GAMMA_MOUT_EN_RDMA1,
+ GAMMA_MOUT_EN_RDMA1),
+ MMSYS_ROUTE(OD, 0, RDMA, 0,
+ DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD_MOUT_EN_RDMA0,
+ OD_MOUT_EN_RDMA0),
+ MMSYS_ROUTE(OD, 1, RDMA, 1,
+ DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD1_MOUT_EN_RDMA1,
+ OD1_MOUT_EN_RDMA1),
+ MMSYS_ROUTE(OVL, 0, COLOR, 0,
+ DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0,
+ OVL0_MOUT_EN_COLOR0),
+ MMSYS_ROUTE(OVL, 0, COLOR, 0,
+ DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0,
+ COLOR0_SEL_IN_OVL0),
+ MMSYS_ROUTE(OVL, 0, RDMA, 0,
+ DISP_REG_CONFIG_DISP_OVL_MOUT_EN, OVL_MOUT_EN_RDMA,
+ OVL_MOUT_EN_RDMA),
+ MMSYS_ROUTE(OVL, 1, COLOR, 1,
+ DISP_REG_CONFIG_DISP_OVL1_MOUT_EN, OVL1_MOUT_EN_COLOR1,
+ OVL1_MOUT_EN_COLOR1),
+ MMSYS_ROUTE(OVL, 1, COLOR, 1,
+ DISP_REG_CONFIG_DISP_COLOR1_SEL_IN, COLOR1_SEL_IN_OVL1,
+ COLOR1_SEL_IN_OVL1),
+ MMSYS_ROUTE(RDMA, 0, DPI, 0,
+ DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
+ RDMA0_SOUT_DPI0),
+ MMSYS_ROUTE(RDMA, 0, DPI, 1,
+ DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
+ RDMA0_SOUT_DPI1),
+ MMSYS_ROUTE(RDMA, 0, DSI, 1,
+ DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
+ RDMA0_SOUT_DSI1),
+ MMSYS_ROUTE(RDMA, 0, DSI, 2,
+ DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
+ RDMA0_SOUT_DSI2),
+ MMSYS_ROUTE(RDMA, 0, DSI, 3,
+ DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
+ RDMA0_SOUT_DSI3),
+ MMSYS_ROUTE(RDMA, 1, DPI, 0,
+ DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
+ RDMA1_SOUT_DPI0),
+ MMSYS_ROUTE(RDMA, 1, DPI, 0,
+ DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_MASK,
+ DPI0_SEL_IN_RDMA1),
+ MMSYS_ROUTE(RDMA, 1, DPI, 1,
+ DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
+ RDMA1_SOUT_DPI1),
+ MMSYS_ROUTE(RDMA, 1, DPI, 1,
+ DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_MASK,
+ DPI1_SEL_IN_RDMA1),
+ MMSYS_ROUTE(RDMA, 1, DSI, 0,
+ DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_MASK,
+ DSI0_SEL_IN_RDMA1),
+ MMSYS_ROUTE(RDMA, 1, DSI, 1,
+ DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
+ RDMA1_SOUT_DSI1),
+ MMSYS_ROUTE(RDMA, 1, DSI, 1,
+ DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_MASK,
+ DSI1_SEL_IN_RDMA1),
+ MMSYS_ROUTE(RDMA, 1, DSI, 2,
+ DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
+ RDMA1_SOUT_DSI2),
+ MMSYS_ROUTE(RDMA, 1, DSI, 2,
+ DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_MASK,
+ DSI2_SEL_IN_RDMA1),
+ MMSYS_ROUTE(RDMA, 1, DSI, 3,
+ DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
+ RDMA1_SOUT_DSI3),
+ MMSYS_ROUTE(RDMA, 1, DSI, 3,
+ DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_MASK,
+ DSI3_SEL_IN_RDMA1),
+ MMSYS_ROUTE(RDMA, 2, DPI, 0,
+ DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
+ RDMA2_SOUT_DPI0),
+ MMSYS_ROUTE(RDMA, 2, DPI, 0,
+ DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_MASK,
+ DPI0_SEL_IN_RDMA2),
+ MMSYS_ROUTE(RDMA, 2, DPI, 1,
+ DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
+ RDMA2_SOUT_DPI1),
+ MMSYS_ROUTE(RDMA, 2, DPI, 1,
+ DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_MASK,
+ DPI1_SEL_IN_RDMA2),
+ MMSYS_ROUTE(RDMA, 2, DSI, 0,
+ DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_MASK,
+ DSI0_SEL_IN_RDMA2),
+ MMSYS_ROUTE(RDMA, 2, DSI, 1,
+ DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
+ RDMA2_SOUT_DSI1),
+ MMSYS_ROUTE(RDMA, 2, DSI, 1,
+ DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_MASK,
+ DSI1_SEL_IN_RDMA2),
+ MMSYS_ROUTE(RDMA, 2, DSI, 2,
+ DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
+ RDMA2_SOUT_DSI2),
+ MMSYS_ROUTE(RDMA, 2, DSI, 2,
+ DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_MASK,
+ DSI2_SEL_IN_RDMA2),
};
#endif /* __SOC_MEDIATEK_MTK_MMSYS_H */
--
2.54.0
^ permalink raw reply related
* [PATCH 08/15] clk: mediatek: Add MT8189 vlpckgen clock support
From: Louis-Alexis Eyraud @ 2026-07-01 13:11 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Brian Masney, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Chun-Jie Chen, Philipp Zabel,
Edward-JW Yang, Richard Cochran
Cc: kernel, linux-clk, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, netdev, Irving-CH Lin, Louis-Alexis Eyraud
In-Reply-To: <20260701-mt8189-clocks-system-base-v1-0-2b048feea50a@collabora.com>
Add support for the MT8189 vlpckgen clock controller, which provides
muxes and dividers for clock selection in vlp domain for other IP blocks.
Co-developed-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
Signed-off-by: Irving-CH Lin <irving-ch.lin@mediatek.com>
Co-developed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
---
drivers/clk/mediatek/Makefile | 3 +-
drivers/clk/mediatek/clk-mt8189-vlpckgen.c | 284 +++++++++++++++++++++++++++++
2 files changed, 286 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 9d3d2983bfb2..3b25df9e7b50 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -123,7 +123,8 @@ obj-$(CONFIG_COMMON_CLK_MT8188_VDOSYS) += clk-mt8188-vdo0.o clk-mt8188-vdo1.o
obj-$(CONFIG_COMMON_CLK_MT8188_VENCSYS) += clk-mt8188-venc.o
obj-$(CONFIG_COMMON_CLK_MT8188_VPPSYS) += clk-mt8188-vpp0.o clk-mt8188-vpp1.o
obj-$(CONFIG_COMMON_CLK_MT8188_WPESYS) += clk-mt8188-wpe.o
-obj-$(CONFIG_COMMON_CLK_MT8189) += clk-mt8189-apmixedsys.o clk-mt8189-topckgen.o
+obj-$(CONFIG_COMMON_CLK_MT8189) += clk-mt8189-apmixedsys.o clk-mt8189-topckgen.o \
+ clk-mt8189-vlpckgen.o
obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192-apmixedsys.o clk-mt8192.o
obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8189-vlpckgen.c b/drivers/clk/mediatek/clk-mt8189-vlpckgen.c
new file mode 100644
index 000000000000..39ca051b9ef8
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8189-vlpckgen.c
@@ -0,0 +1,284 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025-2026 MediaTek Inc.
+ * Qiqi Wang <qiqi.wang@mediatek.com>
+ * Irving-CH Lin <irving-ch.lin@mediatek.com>
+ * Copyright (C) 2026 Collabora Ltd.
+ * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+ * Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com>
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#include "clk-mtk.h"
+#include "clk-mux.h"
+#include "clk-gate.h"
+
+#include <dt-bindings/clock/mediatek,mt8189-clk.h>
+
+static DEFINE_SPINLOCK(mt8189_vlpclk_lock);
+
+static const char * const vlp_26m_oscd10_parents[] = {
+ "clk26m",
+ "osc_d10"
+};
+
+static const char * const vlp_vadsp_vowpll_parents[] = {
+ "clk26m",
+ "vowpll"
+};
+
+static const char * const vlp_sspm_ulposc_parents[] = {
+ "ulposc",
+ "univpll_d5_d2",
+ "osc_d10"
+};
+
+static const char * const vlp_aud_adc_parents[] = {
+ "clk26m",
+ "vowpll",
+ "aud_adc_ext",
+ "osc_d10"
+};
+
+static const char * const vlp_scp_iic_spi_parents[] = {
+ "clk26m",
+ "mainpll_d5_d4",
+ "mainpll_d7_d2",
+ "osc_d10"
+};
+
+static const char * const vlp_vadsp_uarthub_b_parents[] = {
+ "clk26m",
+ "osc_d10",
+ "univpll_d6_d4",
+ "univpll_d6_d2"
+};
+
+static const char * const vlp_axi_kp_parents[] = {
+ "clk26m",
+ "osc_d10",
+ "osc_d2",
+ "mainpll_d7_d4",
+ "mainpll_d7_d2"
+};
+
+static const char * const vlp_sspm_parents[] = {
+ "clk26m",
+ "osc_d10",
+ "mainpll_d5_d2",
+ "ulposc",
+ "mainpll_d6"
+};
+
+static const char * const vlp_pwm_vlp_parents[] = {
+ "clk26m",
+ "osc_d4",
+ "clk32k",
+ "osc_d10",
+ "mainpll_d4_d8"
+};
+
+static const char * const vlp_pwrap_ulposc_parents[] = {
+ "clk26m",
+ "osc_d10",
+ "osc_d7",
+ "osc_d8",
+ "osc_d16",
+ "mainpll_d7_d8"
+};
+
+static const char * const vlp_vadsp_parents[] = {
+ "clk26m",
+ "osc_d20",
+ "osc_d10",
+ "osc_d2",
+ "ulposc",
+ "mainpll_d4_d2"
+};
+
+static const char * const vlp_scp_parents[] = {
+ "clk26m",
+ "univpll_d4",
+ "univpll_d3",
+ "mainpll_d3",
+ "univpll_d6",
+ "apll1",
+ "mainpll_d4",
+ "mainpll_d6",
+ "mainpll_d7",
+ "osc_d10"
+};
+
+static const char * const vlp_spmi_p_parents[] = {
+ "clk26m",
+ "f26m_d2",
+ "osc_d8",
+ "osc_d10",
+ "osc_d16",
+ "osc_d7",
+ "clk32k",
+ "mainpll_d7_d8",
+ "mainpll_d6_d8",
+ "mainpll_d5_d8"
+};
+
+static const char * const vlp_camtg_parents[] = {
+ "clk26m",
+ "univpll_192m_d8",
+ "univpll_d6_d8",
+ "univpll_192m_d4",
+ "osc_d16",
+ "osc_d20",
+ "osc_d10",
+ "univpll_d6_d16",
+ "tvdpll1_d16",
+ "f26m_d2",
+ "univpll_192m_d10",
+ "univpll_192m_d16",
+ "univpll_192m_d32"
+};
+
+static const struct mtk_mux vlp_ck_muxes[] = {
+ /* VLP_CLK_CFG_0 */
+ MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_SCP_SEL, "vlp_scp_sel",
+ vlp_scp_parents, 0x008, 0x00c, 0x010,
+ 0, 4, 7, 0x04, 0),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_PWRAP_ULPOSC_SEL, "vlp_pwrap_ulposc_sel",
+ vlp_pwrap_ulposc_parents, 0x008, 0x00c, 0x010,
+ 8, 3, 0x04, 1),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SPMI_P_MST_SEL, "vlp_spmi_p_sel",
+ vlp_spmi_p_parents, 0x008, 0x00c, 0x010,
+ 16, 4, 0x04, 2),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_DVFSRC_SEL, "vlp_dvfsrc_sel",
+ vlp_26m_oscd10_parents, 0x008, 0x00c, 0x010,
+ 24, 1, 0x04, 3),
+ /* VLP_CLK_CFG_1 */
+ MUX_CLR_SET_UPD(CLK_VLP_CK_PWM_VLP_SEL, "vlp_pwm_vlp_sel",
+ vlp_pwm_vlp_parents, 0x014, 0x018, 0x01c,
+ 0, 3, 0x04, 4),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_AXI_VLP_SEL, "vlp_axi_vlp_sel",
+ vlp_axi_kp_parents, 0x014, 0x018, 0x01c,
+ 8, 3, 0x04, 5),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SYSTIMER_26M_SEL, "vlp_timer_26m_sel",
+ vlp_26m_oscd10_parents, 0x014, 0x018, 0x01c,
+ 16, 1, 0x04, 6),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SSPM_SEL, "vlp_sspm_sel",
+ vlp_sspm_parents, 0x014, 0x018, 0x01c,
+ 24, 3, 0x04, 7),
+ /* VLP_CLK_CFG_2 */
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SSPM_F26M_SEL, "vlp_sspm_f26m_sel",
+ vlp_26m_oscd10_parents, 0x020, 0x024, 0x028,
+ 0, 1, 0x04, 8),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SRCK_SEL, "vlp_srck_sel",
+ vlp_26m_oscd10_parents, 0x020, 0x024, 0x028,
+ 8, 1, 0x04, 9),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SCP_SPI_SEL, "vlp_scp_spi_sel",
+ vlp_scp_iic_spi_parents, 0x020, 0x024, 0x028,
+ 16, 2, 0x04, 10),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SCP_IIC_SEL, "vlp_scp_iic_sel",
+ vlp_scp_iic_spi_parents, 0x020, 0x024, 0x028,
+ 24, 2, 0x04, 11),
+ /* VLP_CLK_CFG_3 */
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SCP_SPI_HIGH_SPD_SEL,
+ "vlp_scp_spi_hs_sel",
+ vlp_scp_iic_spi_parents, 0x02c, 0x030, 0x034,
+ 0, 2, 0x04, 12),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SCP_IIC_HIGH_SPD_SEL,
+ "vlp_scp_iic_hs_sel",
+ vlp_scp_iic_spi_parents, 0x02c, 0x030, 0x034,
+ 8, 2, 0x04, 13),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_SSPM_ULPOSC_SEL, "vlp_sspm_ulposc_sel",
+ vlp_sspm_ulposc_parents, 0x02c, 0x030, 0x034,
+ 16, 2, 0x04, 14),
+ MUX_CLR_SET_UPD(CLK_VLP_CK_APXGPT_26M_SEL, "vlp_apxgpt_26m_sel",
+ vlp_26m_oscd10_parents, 0x02c, 0x030, 0x034,
+ 24, 1, 0x04, 15),
+ /* VLP_CLK_CFG_4 */
+ MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_VADSP_SEL, "vlp_vadsp_sel",
+ vlp_vadsp_parents, 0x038, 0x03c, 0x040,
+ 0, 3, 7, 0x04, 16),
+ MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_VADSP_VOWPLL_SEL,
+ "vlp_vadsp_vowpll_sel",
+ vlp_vadsp_vowpll_parents, 0x038, 0x03c, 0x040,
+ 8, 1, 15, 0x04, 17),
+ MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_VADSP_UARTHUB_BCLK_SEL,
+ "vlp_vadsp_uarthub_b_sel",
+ vlp_vadsp_uarthub_b_parents,
+ 0x038, 0x03c, 0x040, 16, 2, 23, 0x04, 18),
+ MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_CAMTG0_SEL, "vlp_camtg0_sel",
+ vlp_camtg_parents, 0x038, 0x03c, 0x040,
+ 24, 4, 31, 0x04, 19),
+ /* VLP_CLK_CFG_5 */
+ MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_CAMTG1_SEL, "vlp_camtg1_sel",
+ vlp_camtg_parents, 0x044, 0x048, 0x04c,
+ 0, 4, 7, 0x04, 20),
+ MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_CAMTG2_SEL, "vlp_camtg2_sel",
+ vlp_camtg_parents, 0x044, 0x048, 0x04c,
+ 8, 4, 15, 0x04, 21),
+ MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_AUD_ADC_SEL, "vlp_aud_adc_sel",
+ vlp_aud_adc_parents, 0x044, 0x048, 0x04c,
+ 16, 2, 23, 0x04, 22),
+ MUX_GATE_CLR_SET_UPD(CLK_VLP_CK_KP_IRQ_GEN_SEL, "vlp_kp_irq_sel",
+ vlp_axi_kp_parents, 0x044, 0x048, 0x04c,
+ 24, 3, 31, 0x04, 23),
+};
+
+static const struct mtk_gate_regs vlp_ck_cg_regs = {
+ .set_ofs = 0x1f4,
+ .clr_ofs = 0x1f8,
+ .sta_ofs = 0x1f0,
+};
+
+#define GATE_VLP_CK_FLAGS(_id, _name, _parent, _shift, _flag) { \
+ .id = _id, \
+ .name = _name, \
+ .parent_name = _parent, \
+ .regs = &vlp_ck_cg_regs, \
+ .shift = _shift, \
+ .flags = _flag, \
+ .ops = &mtk_clk_gate_ops_setclr_inv, \
+ }
+
+#define GATE_VLP_CK(_id, _name, _parent, _shift) \
+ GATE_VLP_CK_FLAGS(_id, _name, _parent, _shift, 0)
+
+static const struct mtk_gate vlp_ck_clks[] = {
+ GATE_VLP_CK(CLK_VLP_CK_VADSYS_VLP_26M_EN, "vlp_vadsys_vlp_26m", "clk26m", 1),
+ GATE_VLP_CK_FLAGS(CLK_VLP_CK_FMIPI_CSI_UP26M_CK_EN, "vlp_fmipi_csi_up26m",
+ "fmipi_csi_up26m", 11, CLK_IS_CRITICAL),
+};
+
+static const struct mtk_clk_desc vlpck_desc = {
+ .mux_clks = vlp_ck_muxes,
+ .num_mux_clks = ARRAY_SIZE(vlp_ck_muxes),
+ .clks = vlp_ck_clks,
+ .num_clks = ARRAY_SIZE(vlp_ck_clks),
+ .clk_lock = &mt8189_vlpclk_lock,
+};
+
+static const struct of_device_id of_match_clk_mt8189_vlpck[] = {
+ { .compatible = "mediatek,mt8189-vlpckgen", .data = &vlpck_desc },
+ { /* sentinel */ }
+};
+
+static struct platform_driver clk_mt8189_vlpck_drv = {
+ .probe = mtk_clk_simple_probe,
+ .remove = mtk_clk_simple_remove,
+ .driver = {
+ .name = "clk-mt8189-vlpck",
+ .of_match_table = of_match_clk_mt8189_vlpck,
+ },
+};
+module_platform_driver(clk_mt8189_vlpck_drv);
+
+MODULE_DESCRIPTION("MediaTek MT8189 vlpckgen clocks driver");
+MODULE_LICENSE("GPL");
--
2.54.0
^ permalink raw reply related
* [PATCH 06/11] drm/mediatek: mtk_dp: Use PHY API for PHY power sequences
From: AngeloGioacchino Del Regno @ 2026-07-01 12:20 UTC (permalink / raw)
To: chunkuang.hu
Cc: p.zabel, airlied, simona, maarten.lankhorst, mripard, tzimmermann,
robh, krzk+dt, conor+dt, matthias.bgg, angelogioacchino.delregno,
jitao.shi, granquet, rex-bc.chen, dmitry.osipenko, ck.hu,
amergnat, justin.yeh, jason-jh.lin, dri-devel, linux-mediatek,
devicetree, linux-kernel, linux-arm-kernel, kernel
In-Reply-To: <20260701122024.19557-1-angelogioacchino.delregno@collabora.com>
The PHY driver has gained support for .power_on() and .power_off()
callbacks: use the API provided phy_power_on(), phy_power_off()
functions instead of writing into PHY registers from this driver.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
drivers/gpu/drm/mediatek/mtk_dp.c | 32 ++++++++++++++++++++++++-------
1 file changed, 25 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/mtk_dp.c
index 97bce8966a1f..3b5348ab487d 100644
--- a/drivers/gpu/drm/mediatek/mtk_dp.c
+++ b/drivers/gpu/drm/mediatek/mtk_dp.c
@@ -1415,6 +1415,8 @@ static void mtk_dp_aux_panel_poweron(struct mtk_dp *mtk_dp, bool pwron)
static void mtk_dp_power_enable(struct mtk_dp *mtk_dp)
{
+ int ret;
+
mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_RESET_AND_PROBE,
0, SW_RST_B_PHYD);
@@ -1425,21 +1427,37 @@ static void mtk_dp_power_enable(struct mtk_dp *mtk_dp)
SW_RST_B_PHYD, SW_RST_B_PHYD);
mtk_dp_update_bits(mtk_dp, MTK_DP_TOP_PWR_STATE,
DP_PWR_STATE_BANDGAP_TPLL, DP_PWR_STATE_MASK);
- mtk_dp_write(mtk_dp, DP_PHY_AUX_RX_CTL,
- RG_DPAUX_RX_VALID_DEGLITCH_EN | RG_XTP_GLB_CKDET_EN |
- RG_DPAUX_RX_EN);
- mtk_dp_update_bits(mtk_dp, MTK_DP_0034, 0, DA_CKM_CKTX0_EN_FORCE_EN);
+
+ if (mtk_dp->phy_dev) {
+ mtk_dp_write(mtk_dp, DP_PHY_AUX_RX_CTL,
+ RG_DPAUX_RX_VALID_DEGLITCH_EN | RG_XTP_GLB_CKDET_EN |
+ RG_DPAUX_RX_EN);
+ mtk_dp_update_bits(mtk_dp, MTK_DP_0034, 0, DA_CKM_CKTX0_EN_FORCE_EN);
+ } else {
+ ret = phy_power_on(mtk_dp->phy);
+ if (ret)
+ dev_warn(mtk_dp->dev, "Could not power on PHY!\n");
+ }
}
static void mtk_dp_power_disable(struct mtk_dp *mtk_dp)
{
+ int ret;
+
mtk_dp_write(mtk_dp, MTK_DP_TOP_PWR_STATE, 0);
- mtk_dp_update_bits(mtk_dp, MTK_DP_0034,
+ if (unlikely(mtk_dp->phy_dev)) {
+ mtk_dp_update_bits(mtk_dp, MTK_DP_0034,
DA_CKM_CKTX0_EN_FORCE_EN, DA_CKM_CKTX0_EN_FORCE_EN);
- /* Disable RX */
- mtk_dp_write(mtk_dp, DP_PHY_AUX_RX_CTL, 0);
+ /* Disable RX */
+ mtk_dp_write(mtk_dp, DP_PHY_AUX_RX_CTL, 0);
+ } else {
+ ret = phy_power_off(mtk_dp->phy);
+ if (ret)
+ dev_warn(mtk_dp->dev, "Could not power off PHY!\n");
+ }
+
mtk_dp_write(mtk_dp, MTK_DP_TOP_MEM_PD,
0x550 | FUSE_SEL | MEM_ISO_EN);
}
--
2.54.0
^ permalink raw reply related
* Re: [PATCH v4 0/4] AUXADC driver for the MediaTek mt6323 PMIC
From: Jonathan Cameron @ 2026-07-01 18:29 UTC (permalink / raw)
To: David Lechner
Cc: rva333, Nuno Sá, Andy Shevchenko, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Matthias Brugger,
AngeloGioacchino Del Regno, Lee Jones, linux-iio, devicetree,
linux-kernel, linux-arm-kernel, linux-mediatek, Ben Grisdale,
Conor Dooley, Andy Shevchenko
In-Reply-To: <3f914030-44e8-4f63-ae72-7fde7d843325@baylibre.com>
On Sun, 28 Jun 2026 12:34:20 -0500
David Lechner <dlechner@baylibre.com> wrote:
> On 6/23/26 3:16 AM, Roman Vivchar via B4 Relay wrote:
> > This series adds support for the 15-bit AUXADC hardware block found on
> > the MediaTek mt6323 PMIC.
> >
> > The previous version of the series for all AUXADC, EFUSE and thermal
> > drivers was split after Krzysztof's comment [1].
> >
> > Tested on the MediaTek mt6572 and mt8163 SoCs (Ben), both paired with a
> > mt6323.
> >
> > [1]: https://lore.kernel.org/linux-mediatek/20260504-mt6323-v1-0-799b58b355ff@protonmail.com/T/#med30fad67a090be35f549231336b2dec295233f6
> >
> > Tested-by: Ben Grisdale <bengris32@protonmail.ch> # Amazon Echo Dot (2nd Generation)
> > Signed-off-by: Roman Vivchar <rva333@protonmail.com>
> > ---
> Reviewed-by: David Lechner <dlechner@baylibre.com>
>
Applied patch 1 - with some hand editing due to another change
to that binding, and patch 2 to the testing branch of iio.git
which I'll push out as togreg once the bots have given it a clean
bill of health.
I'm assuming 3 will go via mfd and 4 via the soc tree.
Thanks,
Jonathan
^ permalink raw reply
* Re: [PATCH v6] soc: aspeed: lpc-snoop: Fix usercopy overflow in snoop_file_read
From: Karthikeyan KS @ 2026-07-01 17:15 UTC (permalink / raw)
To: andrew
Cc: joel, andrew, Kees Cook, linux-arm-kernel, linux-aspeed,
linux-kernel, linux-hardening
In-Reply-To: <033f2657ae6a94ad13d22f717a2900afb75d892d.camel@codeconstruct.com.au>
Hi Andrew,
Just following up, it's been about two weeks since I shared the
hardware validation results. I believe I've addressed the questions
raised in the thread, but please let me know if there's anything
else you'd like me to do.
Thanks,
Karthikeyan
^ permalink raw reply
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