* [PATCH v2 14/15] arm_mpam: prevent MPAM-Fb accesses inside IRQ handler
From: Andre Przywara @ 2026-07-02 16:22 UTC (permalink / raw)
To: Lorenzo Pieralisi, Hanjun Guo, Sudeep Holla, Catalin Marinas,
Will Deacon, Rafael J . Wysocki, Len Brown, James Morse,
Ben Horgan, Reinette Chatre, Fenghua Yu
Cc: Jonathan Cameron, Srivathsa L Rao, Ganapatrao Kulkarni,
Trilok Soni, Srinivas Ramana, Niyas Sait, linux-acpi,
linux-arm-kernel, linux-kernel
In-Reply-To: <20260702162229.4008659-1-andre.przywara@arm.com>
When an MPAM MSC gets into an error condition, it can trigger an error
IRQ. We cannot really do much about those errors, but we at least query
and log the error, then disable MPAM functionality.
This error report relies on reading the MSC's error status register
(ESR) in the IRQ handler, which is not possible for MPAM-Fb based
MSC accesses, since they involve mailbox routines that might sleep.
The same is true for clearing the interrupt at the source, which
requires MSC access.
For simplicity just skip the ESR read when the MSC is not using direct
MMIO accesses, and just ignore the pending interrupts. We will wrap up
MPAM functionality regardless, knowing the exact error value will not
change that.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
drivers/resctrl/mpam_devices.c | 35 +++++++++++++++++++---------------
1 file changed, 20 insertions(+), 15 deletions(-)
diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c
index b858ff389bff..4a088e6cd235 100644
--- a/drivers/resctrl/mpam_devices.c
+++ b/drivers/resctrl/mpam_devices.c
@@ -2639,7 +2639,7 @@ static int mpam_disable_msc_ecr(void *_msc)
static irqreturn_t __mpam_irq_handler(int irq, struct mpam_msc *msc)
{
- u64 reg;
+ u64 reg = 0;
u16 partid;
u8 errcode, pmg, ris;
@@ -2648,25 +2648,30 @@ static irqreturn_t __mpam_irq_handler(int irq, struct mpam_msc *msc)
&msc->accessibility)))
return IRQ_NONE;
- mpam_msc_read_esr(msc, ®);
+ /* MPAM-Fb MSC accesses cannot be done in atomic context. */
+ if (msc->iface == MPAM_IFACE_MMIO) {
+ mpam_msc_read_esr(msc, ®);
- errcode = FIELD_GET(MPAMF_ESR_ERRCODE, reg);
- if (!errcode)
- return IRQ_NONE;
+ errcode = FIELD_GET(MPAMF_ESR_ERRCODE, reg);
+ if (!errcode)
+ return IRQ_NONE;
- /* Clear level triggered irq */
- mpam_msc_clear_esr(msc);
+ /* Clear level triggered irq */
+ mpam_msc_clear_esr(msc);
- partid = FIELD_GET(MPAMF_ESR_PARTID_MON, reg);
- pmg = FIELD_GET(MPAMF_ESR_PMG, reg);
- ris = FIELD_GET(MPAMF_ESR_RIS, reg);
+ partid = FIELD_GET(MPAMF_ESR_PARTID_MON, reg);
+ pmg = FIELD_GET(MPAMF_ESR_PMG, reg);
+ ris = FIELD_GET(MPAMF_ESR_RIS, reg);
- pr_err_ratelimited("error irq from msc:%u '%s', partid:%u, pmg: %u, ris: %u\n",
- msc->id, mpam_errcode_names[errcode], partid, pmg,
- ris);
+ pr_err_ratelimited("error irq from msc:%u '%s', partid:%u, pmg: %u, ris: %u\n",
+ msc->id, mpam_errcode_names[errcode], partid,
+ pmg, ris);
- /* Disable this interrupt. */
- mpam_disable_msc_ecr(msc);
+ /* Disable this interrupt. */
+ mpam_disable_msc_ecr(msc);
+ } else {
+ pr_err_ratelimited("unknown error irq from msc:%u\n", msc->id);
+ }
/* Are we racing with the thread disabling MPAM? */
if (!mpam_is_enabled())
--
2.43.0
^ permalink raw reply related
* [PATCH v2 13/15] arm_mpam: add MPAM-Fb MSC firmware access support
From: Andre Przywara @ 2026-07-02 16:22 UTC (permalink / raw)
To: Lorenzo Pieralisi, Hanjun Guo, Sudeep Holla, Catalin Marinas,
Will Deacon, Rafael J . Wysocki, Len Brown, James Morse,
Ben Horgan, Reinette Chatre, Fenghua Yu
Cc: Jonathan Cameron, Srivathsa L Rao, Ganapatrao Kulkarni,
Trilok Soni, Srinivas Ramana, Niyas Sait, linux-acpi,
linux-arm-kernel, linux-kernel
In-Reply-To: <20260702162229.4008659-1-andre.przywara@arm.com>
The Arm MPAM Firmware-backed (Fb) Profile document[1] describes an
alternative way of accessing the "Memory System Components" (MSC) in an
MPAM enabled system.
Normally the MSCs are MMIO mapped, but in some implementations this
might not be possible (MSC located outside of the local socket, MSC
mapped secure-only) or desirable (direct MMIO access too slow or needs
to be mediated through a control processor). MPAM-fb standardises a
protocol to abstract MSC accesses, building on the SCMI protocol.
Add functions that do an MSC read or write access by redirecting the
request through a firmware interface. For now this done via an ACPI
PCC shared memory and mailbox combination.
Since the protocol used is only a small subset of the full SCMI spec,
and the SCMI protocol has no full ACPI support anyway, open-code the
SCMI message generation and handshake, for just the fields we need.
[1] https://developer.arm.com/documentation/den0144/latest
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
drivers/resctrl/Makefile | 2 +-
drivers/resctrl/mpam_devices.c | 27 +++++--
drivers/resctrl/mpam_fb.c | 137 ++++++++++++++++++++++++++++++++
drivers/resctrl/mpam_fb.h | 17 ++++
drivers/resctrl/mpam_internal.h | 12 +++
include/linux/arm_mpam.h | 2 +-
6 files changed, 190 insertions(+), 7 deletions(-)
create mode 100644 drivers/resctrl/mpam_fb.c
create mode 100644 drivers/resctrl/mpam_fb.h
diff --git a/drivers/resctrl/Makefile b/drivers/resctrl/Makefile
index 4f6d0e81f9b8..097c036724e9 100644
--- a/drivers/resctrl/Makefile
+++ b/drivers/resctrl/Makefile
@@ -1,5 +1,5 @@
obj-$(CONFIG_ARM64_MPAM_DRIVER) += mpam.o
-mpam-y += mpam_devices.o
+mpam-y += mpam_devices.o mpam_fb.o
mpam-$(CONFIG_ARM64_MPAM_RESCTRL_FS) += mpam_resctrl.o
ccflags-$(CONFIG_ARM64_MPAM_DRIVER_DEBUG) += -DDEBUG
diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c
index 824bc6c97851..b858ff389bff 100644
--- a/drivers/resctrl/mpam_devices.c
+++ b/drivers/resctrl/mpam_devices.c
@@ -28,6 +28,7 @@
#include <linux/workqueue.h>
#include "mpam_internal.h"
+#include "mpam_fb.h"
/* Values for the T241 errata workaround */
#define T241_CHIPS_MAX 4
@@ -181,6 +182,9 @@ static int __mpam_read_reg(struct mpam_msc *msc, u16 reg, u32 *res)
{
WARN_ON_ONCE(!cpumask_test_cpu(smp_processor_id(), &msc->accessibility));
+ if (msc->iface == MPAM_IFACE_PCC)
+ return mpam_fb_send_read_request(msc, reg, res);
+
*res = readl_relaxed(msc->mapped_hwpage + reg);
return 0;
@@ -197,9 +201,12 @@ static inline int _mpam_read_partsel_reg(struct mpam_msc *msc, u16 reg,
static int __mpam_write_reg(struct mpam_msc *msc, u16 reg, u32 val)
{
- WARN_ON_ONCE(reg + sizeof(u32) > msc->mapped_hwpage_sz);
WARN_ON_ONCE(!cpumask_test_cpu(smp_processor_id(), &msc->accessibility));
+ if (msc->iface == MPAM_IFACE_PCC)
+ return mpam_fb_send_write_request(msc, reg, val);
+
+ WARN_ON_ONCE(reg + sizeof(u32) > msc->mapped_hwpage_sz);
writel_relaxed(val, msc->mapped_hwpage + reg);
return 0;
@@ -1127,7 +1134,8 @@ static u64 mpam_msc_read_mbwu_l(struct mpam_msc *msc)
mpam_mon_sel_lock_held(msc);
- WARN_ON_ONCE((MSMON_MBWU_L + sizeof(u64)) > msc->mapped_hwpage_sz);
+ if (msc->iface == MPAM_IFACE_MMIO)
+ WARN_ON_ONCE((MSMON_MBWU_L + sizeof(u64)) > msc->mapped_hwpage_sz);
WARN_ON_ONCE(!cpumask_test_cpu(smp_processor_id(), &msc->accessibility));
ret = __mpam_read_reg(msc, MSMON_MBWU_L + 4, &mbwu_l_high2);
@@ -1475,9 +1483,15 @@ static int _msmon_read(struct mpam_component *comp, struct mon_read *arg)
srcu_read_lock_held(&mpam_srcu)) {
arg->ris = ris;
- err = smp_call_function_any(&msc->accessibility,
- __ris_msmon_read, arg,
- true);
+ if (msc->iface == MPAM_IFACE_MMIO) {
+ err = smp_call_function_any(&msc->accessibility,
+ __ris_msmon_read,
+ arg, true);
+ } else {
+ __ris_msmon_read(arg);
+ err = 0;
+ }
+
if (!err && arg->err)
err = arg->err;
@@ -1913,6 +1927,9 @@ static int mpam_get_msc_preferred_cpu(struct mpam_msc *msc)
static int mpam_touch_msc(struct mpam_msc *msc, int (*fn)(void *a), void *arg)
{
+ if (msc->iface != MPAM_IFACE_MMIO)
+ return fn(arg);
+
lockdep_assert_irqs_enabled();
lockdep_assert_cpus_held();
WARN_ON_ONCE(!srcu_read_lock_held((&mpam_srcu)));
diff --git a/drivers/resctrl/mpam_fb.c b/drivers/resctrl/mpam_fb.c
new file mode 100644
index 000000000000..687be6f8a152
--- /dev/null
+++ b/drivers/resctrl/mpam_fb.c
@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (C) 2024 Arm Ltd.
+
+#include <linux/arm_mpam.h>
+#include <linux/cleanup.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/gfp.h>
+#include <linux/list.h>
+#include <linux/mailbox_client.h>
+#include <linux/mutex.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/printk.h>
+#include <linux/processor.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+
+#include <acpi/pcc.h>
+
+#include <asm/mpam.h>
+
+#include "mpam_fb.h"
+
+#define MPAM_FB_PROTOCOL_ID 0x1a
+#define MPAM_MSC_ATTRIBUTES_CMD 0x3
+#define MPAM_MSC_READ_CMD 0x4
+#define MPAM_MSC_WRITE_CMD 0x5
+
+#define MPAM_MSC_PROT_ID_MASK GENMASK(17, 10)
+#define MPAM_MSC_TOKEN_MASK GENMASK(27, 18)
+
+#define PCC_CHAN_FLAGS_IRQ BIT(0)
+#define MPAM_READ_MSG_SIZE (PCC_TYPE3_MSG_PAYLOAD_OFS + 3 * sizeof(u32))
+#define MPAM_WRITE_MSG_SIZE (PCC_TYPE3_MSG_PAYLOAD_OFS + 4 * sizeof(u32))
+
+static atomic_t mpam_fb_token = ATOMIC_INIT(0);
+
+static int mpam_fb_build_read_message(int msc_id, int reg, unsigned int token,
+ void __iomem *msg_buf)
+{
+ struct acpi_pcct_ext_pcc_shared_memory *pcc_shmem = msg_buf;
+ void __iomem *payload_ofs = msg_buf + sizeof(*pcc_shmem);
+
+ writel_relaxed(PCC_CHAN_FLAGS_IRQ, &pcc_shmem->flags);
+ writel_relaxed(MPAM_READ_MSG_SIZE, &pcc_shmem->length);
+ writel_relaxed(MPAM_MSC_READ_CMD |
+ FIELD_PREP(MPAM_MSC_TOKEN_MASK, token) |
+ FIELD_PREP(MPAM_MSC_PROT_ID_MASK, MPAM_FB_PROTOCOL_ID),
+ &pcc_shmem->command);
+
+ writel_relaxed(cpu_to_le32(msc_id), payload_ofs + 0x0);
+ writel_relaxed(0, payload_ofs + 0x4);
+ writel_relaxed(cpu_to_le32(reg), payload_ofs + 0x8);
+
+ return MPAM_READ_MSG_SIZE;
+}
+
+static int mpam_fb_build_write_message(int msc_id, int reg, u32 val,
+ unsigned int token,
+ void __iomem *msg_buf)
+{
+ struct acpi_pcct_ext_pcc_shared_memory *pcc_shmem = msg_buf;
+ void __iomem *payload_ofs = msg_buf + sizeof(*pcc_shmem);
+
+ writel_relaxed(MPAM_WRITE_MSG_SIZE, &pcc_shmem->length);
+ writel_relaxed(MPAM_MSC_WRITE_CMD |
+ FIELD_PREP(MPAM_MSC_TOKEN_MASK, token) |
+ FIELD_PREP(MPAM_MSC_PROT_ID_MASK, MPAM_FB_PROTOCOL_ID),
+ &pcc_shmem->command);
+
+ writel_relaxed(cpu_to_le32(msc_id), payload_ofs + 0x0);
+ writel_relaxed(0, payload_ofs + 0x4);
+ writel_relaxed(cpu_to_le32(reg), payload_ofs + 0x8);
+ writel_relaxed(cpu_to_le32(val), payload_ofs + 0xc);
+
+ return MPAM_WRITE_MSG_SIZE;
+}
+
+static int mpam_fb_send_request(struct mpam_msc *msc, u16 reg, u32 *result,
+ bool is_write)
+{
+ unsigned int token = atomic_inc_return(&mpam_fb_token);
+ struct acpi_pcct_ext_pcc_shared_memory *pcc_shmem;
+ struct mpam_pcc_chan *pcc_chan = msc->pcc_chan;
+ struct pcc_mbox_chan *chan;
+ void __iomem *payload_ofs;
+ u32 status;
+ int ret;
+
+ if (!pcc_chan)
+ return -ENODEV;
+
+ chan = pcc_chan->pcc_chan;
+
+ guard(mutex)(&pcc_chan->pcc_chan_lock);
+
+ if (is_write)
+ ret = mpam_fb_build_write_message(msc->mpam_fb_msc_id, reg,
+ *result, token, chan->shmem);
+ else
+ ret = mpam_fb_build_read_message(msc->mpam_fb_msc_id, reg,
+ token, chan->shmem);
+ if (ret < 0)
+ return ret;
+
+ ret = mbox_send_message(chan->mchan, NULL);
+ if (ret < 0)
+ return ret;
+
+ pcc_shmem = chan->shmem;
+ payload_ofs = chan->shmem + sizeof(*pcc_shmem);
+ status = readl(&pcc_shmem->command);
+ if (FIELD_GET(MPAM_MSC_TOKEN_MASK, status) != token)
+ return -ETIMEDOUT;
+
+ ret = readl(payload_ofs + 0x0);
+ if (ret < 0)
+ return ret;
+
+ if (!is_write)
+ *result = readl(payload_ofs + 0x4);
+
+ return 0;
+}
+
+int mpam_fb_send_read_request(struct mpam_msc *msc, u16 reg, u32 *result)
+{
+ return mpam_fb_send_request(msc, reg, result, false);
+}
+
+int mpam_fb_send_write_request(struct mpam_msc *msc, u16 reg, u32 value)
+{
+ return mpam_fb_send_request(msc, reg, &value, true);
+}
diff --git a/drivers/resctrl/mpam_fb.h b/drivers/resctrl/mpam_fb.h
new file mode 100644
index 000000000000..45cd572a28ad
--- /dev/null
+++ b/drivers/resctrl/mpam_fb.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+// Copyright (C) 2024-2025 Arm Ltd.
+
+#ifndef MPAM_FB_H_
+#define MPAM_FB_H_
+
+#include <linux/types.h>
+#include "mpam_internal.h"
+
+#define PCC_TYPE3_MSG_PAYLOAD_OFS 0x10
+#define MPAM_WRITE_MSG_SIZE (PCC_TYPE3_MSG_PAYLOAD_OFS + 4 * sizeof(u32))
+#define MPAM_FB_MAX_MSG_SIZE MPAM_WRITE_MSG_SIZE
+
+int mpam_fb_send_read_request(struct mpam_msc *msc, u16 reg, u32 *result);
+int mpam_fb_send_write_request(struct mpam_msc *msc, u16 reg, u32 value);
+
+#endif
diff --git a/drivers/resctrl/mpam_internal.h b/drivers/resctrl/mpam_internal.h
index 4616f1283f1a..9e7778534143 100644
--- a/drivers/resctrl/mpam_internal.h
+++ b/drivers/resctrl/mpam_internal.h
@@ -11,6 +11,7 @@
#include <linux/io.h>
#include <linux/jump_label.h>
#include <linux/llist.h>
+#include <linux/mailbox_client.h>
#include <linux/mutex.h>
#include <linux/resctrl.h>
#include <linux/spinlock.h>
@@ -57,6 +58,15 @@ struct mpam_garbage {
struct platform_device *pdev;
};
+struct mpam_pcc_chan {
+ struct list_head pcc_chans;
+ struct mbox_client pcc_cl;
+ struct pcc_mbox_chan *pcc_chan;
+ struct mutex pcc_chan_lock; /* only one message at a time */
+ int subspace_id;
+ int refcount;
+};
+
struct mpam_msc {
/* member of mpam_all_msc */
struct list_head all_msc_list;
@@ -66,6 +76,8 @@ struct mpam_msc {
/* Not modified after mpam_is_enabled() becomes true */
enum mpam_msc_iface iface;
+ struct mpam_pcc_chan *pcc_chan;
+ int mpam_fb_msc_id; /* in its own name space */
u32 nrdy_usec;
cpumask_t accessibility;
bool has_extd_esr;
diff --git a/include/linux/arm_mpam.h b/include/linux/arm_mpam.h
index f92a36187a52..002f56e15362 100644
--- a/include/linux/arm_mpam.h
+++ b/include/linux/arm_mpam.h
@@ -12,7 +12,7 @@ struct mpam_msc;
enum mpam_msc_iface {
MPAM_IFACE_MMIO, /* a real MPAM MSC */
- MPAM_IFACE_PCC, /* a fake MPAM MSC */
+ MPAM_IFACE_PCC, /* using the MPAM-Fb firmware redirection */
};
enum mpam_class_types {
--
2.43.0
^ permalink raw reply related
* [PATCH v2 12/15] arm_mpam: Split the locking around the mon_sel registers
From: Andre Przywara @ 2026-07-02 16:22 UTC (permalink / raw)
To: Lorenzo Pieralisi, Hanjun Guo, Sudeep Holla, Catalin Marinas,
Will Deacon, Rafael J . Wysocki, Len Brown, James Morse,
Ben Horgan, Reinette Chatre, Fenghua Yu
Cc: Jonathan Cameron, Srivathsa L Rao, Ganapatrao Kulkarni,
Trilok Soni, Srinivas Ramana, Niyas Sait, linux-acpi,
linux-arm-kernel, linux-kernel
In-Reply-To: <20260702162229.4008659-1-andre.przywara@arm.com>
From: James Morse <james.morse@arm.com>
The MSC MON_SEL register needs to be accessed from hardirq for the overflow
interrupt, and when taking an IPI to access these registers on platforms
where MSC are not accesible from every CPU. This makes an irqsave
spinlock the obvious lock to protect these registers. On systems with SCMI
mailboxes it must be able to sleep, meaning a mutex must be used. The
SCMI platforms can't support an overflow interrupt.
Clearly these two can't exist for one MSC at the same time.
Split the existing helper into a raw spinlock and a mutex, named inner
and outer. The outer lock must be taken in an a pre-emptible context
before the inner lock can be taken. On systems with SCMI mailboxes
where the MON_SEL accesses must sleep - the inner lock will fail to be
taken if the caller is unable to sleep.
This will allow callers to fail without having to explicitly check
the interface type of each MSC.
Signed-off-by: James Morse <james.morse@arm.com>
[Andre: remove redundant outer lock in mpam_reprogram_msc()]
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
drivers/resctrl/mpam_devices.c | 56 +++++++++++++++++++--------
drivers/resctrl/mpam_internal.h | 67 ++++++++++++++++++++++++---------
2 files changed, 90 insertions(+), 33 deletions(-)
diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c
index addc25e78345..824bc6c97851 100644
--- a/drivers/resctrl/mpam_devices.c
+++ b/drivers/resctrl/mpam_devices.c
@@ -787,7 +787,7 @@ static bool mpam_ris_hw_probe_csu_nrdy(struct mpam_msc_ris *ris)
bool can_set, can_clear;
struct mpam_msc *msc = ris->vmsc->msc;
- if (WARN_ON_ONCE(!mpam_mon_sel_lock(msc)))
+ if (WARN_ON_ONCE(!mpam_mon_sel_inner_lock(msc)))
return false;
mon_sel = FIELD_PREP(MSMON_CFG_MON_SEL_MON_SEL, 0) |
@@ -819,7 +819,7 @@ static bool mpam_ris_hw_probe_csu_nrdy(struct mpam_msc_ris *ris)
if (_mpam_read_monsel_reg(msc, MSMON_CSU, &now))
return false;
can_clear = !(now & MSMON___NRDY);
- mpam_mon_sel_unlock(msc);
+ mpam_mon_sel_inner_unlock(msc);
return (!can_set || !can_clear);
}
@@ -961,7 +961,9 @@ static int mpam_ris_hw_probe(struct mpam_msc_ris *ris)
mpam_set_feature(mpam_feat_msmon_csu_xcl, props);
/* Is NRDY hardware managed? */
+ mpam_mon_sel_outer_lock(msc);
hw_managed = mpam_ris_hw_probe_csu_nrdy(ris);
+ mpam_mon_sel_outer_unlock(msc);
/*
* Accept the missing firmware property if NRDY appears
@@ -1334,7 +1336,7 @@ static void __ris_msmon_read(void *arg)
struct mpam_msc *msc = m->ris->vmsc->msc;
u32 mon_sel, ctl_val, flt_val, cur_ctl, cur_flt;
- if (!mpam_mon_sel_lock(msc)) {
+ if (!mpam_mon_sel_inner_lock(msc)) {
m->err = -EIO;
return;
}
@@ -1441,7 +1443,7 @@ static void __ris_msmon_read(void *arg)
default:
m->err = -EINVAL;
}
- mpam_mon_sel_unlock(msc);
+ mpam_mon_sel_inner_unlock(msc);
if (nrdy)
m->err = -EBUSY;
@@ -1452,7 +1454,7 @@ static void __ris_msmon_read(void *arg)
return;
out_unlock:
- mpam_mon_sel_unlock(msc);
+ mpam_mon_sel_inner_unlock(msc);
m->err = ret;
}
@@ -1468,6 +1470,7 @@ static int _msmon_read(struct mpam_component *comp, struct mon_read *arg)
struct mpam_msc *msc = vmsc->msc;
struct mpam_msc_ris *ris;
+ mpam_mon_sel_outer_lock(msc);
list_for_each_entry_srcu(ris, &vmsc->ris, vmsc_list,
srcu_read_lock_held(&mpam_srcu)) {
arg->ris = ris;
@@ -1486,6 +1489,7 @@ static int _msmon_read(struct mpam_component *comp, struct mon_read *arg)
if (err)
any_err = err;
}
+ mpam_mon_sel_outer_unlock(msc);
}
return any_err;
@@ -1568,18 +1572,20 @@ void mpam_msmon_reset_mbwu(struct mpam_component *comp, struct mon_cfg *ctx)
continue;
msc = vmsc->msc;
+ mpam_mon_sel_outer_lock(msc);
list_for_each_entry_srcu(ris, &vmsc->ris, vmsc_list,
srcu_read_lock_held(&mpam_srcu)) {
if (!mpam_has_feature(mpam_feat_msmon_mbwu, &ris->props))
continue;
- if (WARN_ON_ONCE(!mpam_mon_sel_lock(msc)))
+ if (WARN_ON_ONCE(!mpam_mon_sel_inner_lock(msc)))
continue;
ris->mbwu_state[ctx->mon].correction = 0;
ris->mbwu_state[ctx->mon].reset_on_next_read = true;
- mpam_mon_sel_unlock(msc);
+ mpam_mon_sel_inner_unlock(msc);
}
+ mpam_mon_sel_outer_unlock(msc);
}
}
@@ -1781,8 +1787,11 @@ static int mpam_restore_mbwu_state(void *_ris)
int ret = 0;
struct mon_read mwbu_arg;
struct mpam_msc_ris *ris = _ris;
+ struct mpam_msc *msc = ris->vmsc->msc;
struct mpam_class *class = ris->vmsc->comp->class;
+ mpam_mon_sel_outer_lock(msc);
+
for (i = 0; i < ris->props.num_mbwu_mon; i++) {
if (ris->mbwu_state[i].enabled) {
mwbu_arg.ris = ris;
@@ -1798,10 +1807,12 @@ static int mpam_restore_mbwu_state(void *_ris)
}
}
+ mpam_mon_sel_outer_unlock(msc);
+
return ret;
}
-/* Call with MSC cfg_lock held */
+/* Call with MSC cfg_lock and outer mon_sel lock held */
static int mpam_save_mbwu_state(void *arg)
{
int i;
@@ -1817,7 +1828,7 @@ static int mpam_save_mbwu_state(void *arg)
mbwu_state = &ris->mbwu_state[i];
cfg = &mbwu_state->cfg;
- if (WARN_ON_ONCE(!mpam_mon_sel_lock(msc)))
+ if (WARN_ON_ONCE(!mpam_mon_sel_inner_lock(msc)))
return -EIO;
mon_sel = FIELD_PREP(MSMON_CFG_MON_SEL_MON_SEL, i) |
@@ -1853,7 +1864,9 @@ static int mpam_save_mbwu_state(void *arg)
mbwu_state->correction += val;
mbwu_state->enabled = FIELD_GET(MSMON_CFG_x_CTL_EN, cur_ctl);
}
- mpam_mon_sel_unlock(msc);
+
+ mpam_mon_sel_inner_unlock(msc);
+
if (ret)
break;
}
@@ -2050,6 +2063,7 @@ static int mpam_cpu_offline(unsigned int cpu)
struct mpam_msc_ris *ris;
mutex_lock(&msc->cfg_lock);
+ mpam_mon_sel_outer_lock(msc);
list_for_each_entry_srcu(ris, &msc->ris, msc_list,
srcu_read_lock_held(&mpam_srcu)) {
mpam_touch_msc(msc, &mpam_reset_ris, ris);
@@ -2063,6 +2077,7 @@ static int mpam_cpu_offline(unsigned int cpu)
if (mpam_is_enabled())
mpam_touch_msc(msc, &mpam_save_mbwu_state, ris);
}
+ mpam_mon_sel_outer_unlock(msc);
mutex_unlock(&msc->cfg_lock);
}
}
@@ -2756,11 +2771,13 @@ static void __destroy_component_cfg(struct mpam_component *comp)
list_for_each_entry(vmsc, &comp->vmsc, comp_list) {
msc = vmsc->msc;
- if (mpam_mon_sel_lock(msc)) {
+ mpam_mon_sel_outer_lock(msc);
+ if (mpam_mon_sel_inner_lock(msc)) {
list_for_each_entry(ris, &vmsc->ris, vmsc_list)
add_to_garbage(ris->mbwu_state);
- mpam_mon_sel_unlock(msc);
+ mpam_mon_sel_inner_unlock(msc);
}
+ mpam_mon_sel_outer_unlock(msc);
}
}
@@ -2807,6 +2824,7 @@ static int __allocate_component_cfg(struct mpam_component *comp)
mpam_reset_component_cfg(comp);
list_for_each_entry(vmsc, &comp->vmsc, comp_list) {
+ int err = 0;
struct mpam_msc *msc;
struct mpam_msc_ris *ris;
struct msmon_mbwu_state *mbwu_state;
@@ -2815,6 +2833,7 @@ static int __allocate_component_cfg(struct mpam_component *comp)
continue;
msc = vmsc->msc;
+ mpam_mon_sel_outer_lock(msc);
list_for_each_entry(ris, &vmsc->ris, vmsc_list) {
if (!ris->props.num_mbwu_mon)
continue;
@@ -2823,16 +2842,21 @@ static int __allocate_component_cfg(struct mpam_component *comp)
ris->props.num_mbwu_mon);
if (!mbwu_state) {
__destroy_component_cfg(comp);
- return -ENOMEM;
+ err = -ENOMEM;
+ break;
}
init_garbage(&mbwu_state[0].garbage);
- if (mpam_mon_sel_lock(msc)) {
+ if (mpam_mon_sel_inner_lock(msc)) {
ris->mbwu_state = mbwu_state;
- mpam_mon_sel_unlock(msc);
+ mpam_mon_sel_inner_unlock(msc);
}
}
+ mpam_mon_sel_outer_unlock(msc);
+
+ if (err)
+ return err;
}
return 0;
@@ -3085,12 +3109,14 @@ int mpam_apply_config(struct mpam_component *comp, u16 partid,
msc = vmsc->msc;
mutex_lock(&msc->cfg_lock);
+ mpam_mon_sel_outer_lock(msc);
list_for_each_entry_srcu(ris, &vmsc->ris, vmsc_list,
srcu_read_lock_held(&mpam_srcu)) {
arg.ris = ris;
mpam_touch_msc(msc, __write_config, &arg);
ris->in_reset_state = false;
}
+ mpam_mon_sel_outer_unlock(msc);
mutex_unlock(&msc->cfg_lock);
}
diff --git a/drivers/resctrl/mpam_internal.h b/drivers/resctrl/mpam_internal.h
index 04d1a59f02af..4616f1283f1a 100644
--- a/drivers/resctrl/mpam_internal.h
+++ b/drivers/resctrl/mpam_internal.h
@@ -116,16 +116,20 @@ struct mpam_msc {
/*
* mon_sel_lock protects access to the MSC hardware registers that are
* affected by MPAMCFG_MON_SEL, and the mbwu_state.
- * Access to mon_sel is needed from both process and interrupt contexts,
- * but is complicated by firmware-backed platforms that can't make any
- * access unless they can sleep.
- * Always use the mpam_mon_sel_lock() helpers.
- * Accesses to mon_sel need to be able to fail if they occur in the wrong
- * context.
+ * Both the 'inner' and 'outer' must be taken.
+ * For real MMIO MSC, the outer lock is unnecessary - but keeps the
+ * code common with:
+ * Firmware backed MSC need to sleep when accessing the MSC, which
+ * means some code-paths will always fail. For these MSC the outer
+ * lock is providing the protection, and the inner lock fails to
+ * be taken if the task is unable to sleep.
+ *
* If needed, take msc->probe_lock first.
*/
- raw_spinlock_t _mon_sel_lock;
- unsigned long _mon_sel_flags;
+ struct mutex outer_mon_sel_lock;
+ bool outer_lock_held;
+ raw_spinlock_t inner_mon_sel_lock;
+ unsigned long inner_mon_sel_flags;
void __iomem *mapped_hwpage;
size_t mapped_hwpage_sz;
@@ -137,29 +141,56 @@ struct mpam_msc {
};
/* Returning false here means accesses to mon_sel must fail and report an error. */
-static inline bool __must_check mpam_mon_sel_lock(struct mpam_msc *msc)
+static inline bool __must_check mpam_mon_sel_inner_lock(struct mpam_msc *msc)
{
- /* Locking will require updating to support a firmware backed interface */
- if (WARN_ON_ONCE(msc->iface != MPAM_IFACE_MMIO))
- return false;
+ /*
+ * The outer lock may be taken by a CPU that then issues an IPI to run
+ * a helper that takes the inner lock. lockdep can't help us here.
+ */
+ WARN_ON_ONCE(!READ_ONCE(msc->outer_lock_held));
+
+ if (msc->iface == MPAM_IFACE_MMIO) {
+ raw_spin_lock_irqsave(&msc->inner_mon_sel_lock, msc->inner_mon_sel_flags);
+ return true;
+ }
+
+ /* Accesses must fail if we are not pre-emptible */
+ return !!preemptible();
+}
- raw_spin_lock_irqsave(&msc->_mon_sel_lock, msc->_mon_sel_flags);
- return true;
+static inline void mpam_mon_sel_inner_unlock(struct mpam_msc *msc)
+{
+ WARN_ON_ONCE(!READ_ONCE(msc->outer_lock_held));
+
+ if (msc->iface == MPAM_IFACE_MMIO)
+ raw_spin_unlock_irqrestore(&msc->inner_mon_sel_lock, msc->inner_mon_sel_flags);
+}
+
+static inline void mpam_mon_sel_outer_lock(struct mpam_msc *msc)
+{
+ mutex_lock(&msc->outer_mon_sel_lock);
+ msc->outer_lock_held = true;
}
-static inline void mpam_mon_sel_unlock(struct mpam_msc *msc)
+static inline void mpam_mon_sel_outer_unlock(struct mpam_msc *msc)
{
- raw_spin_unlock_irqrestore(&msc->_mon_sel_lock, msc->_mon_sel_flags);
+ msc->outer_lock_held = false;
+ mutex_unlock(&msc->outer_mon_sel_lock);
}
static inline void mpam_mon_sel_lock_held(struct mpam_msc *msc)
{
- lockdep_assert_held_once(&msc->_mon_sel_lock);
+ WARN_ON_ONCE(!READ_ONCE(msc->outer_lock_held));
+ if (msc->iface == MPAM_IFACE_MMIO)
+ lockdep_assert_held_once(&msc->inner_mon_sel_lock);
+ else
+ lockdep_assert_preemption_enabled();
}
static inline void mpam_mon_sel_lock_init(struct mpam_msc *msc)
{
- raw_spin_lock_init(&msc->_mon_sel_lock);
+ raw_spin_lock_init(&msc->inner_mon_sel_lock);
+ mutex_init(&msc->outer_mon_sel_lock);
}
/* Bits for mpam features bitmaps */
--
2.43.0
^ permalink raw reply related
* [PATCH v2 11/15] arm_mpam: propagate MSC write errors for remaining MSC write users
From: Andre Przywara @ 2026-07-02 16:22 UTC (permalink / raw)
To: Lorenzo Pieralisi, Hanjun Guo, Sudeep Holla, Catalin Marinas,
Will Deacon, Rafael J . Wysocki, Len Brown, James Morse,
Ben Horgan, Reinette Chatre, Fenghua Yu
Cc: Jonathan Cameron, Srivathsa L Rao, Ganapatrao Kulkarni,
Trilok Soni, Srinivas Ramana, Niyas Sait, linux-acpi,
linux-arm-kernel, linux-kernel
In-Reply-To: <20260702162229.4008659-1-andre.przywara@arm.com>
Allow the remaining MSC device functions to return an error, and
propagate write errors from the lower level up.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
propagate write errors up for mpam_save_mbwu_state()
---
drivers/resctrl/mpam_devices.c | 76 ++++++++++++++++++++++------------
1 file changed, 49 insertions(+), 27 deletions(-)
diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c
index f3558d248c38..addc25e78345 100644
--- a/drivers/resctrl/mpam_devices.c
+++ b/drivers/resctrl/mpam_devices.c
@@ -1150,15 +1150,20 @@ static u64 mpam_msc_read_mbwu_l(struct mpam_msc *msc)
return MSMON___L_NRDY;
}
-static void mpam_msc_zero_mbwu_l(struct mpam_msc *msc)
+static int mpam_msc_zero_mbwu_l(struct mpam_msc *msc)
{
+ int ret;
+
mpam_mon_sel_lock_held(msc);
WARN_ON_ONCE((MSMON_MBWU_L + sizeof(u64)) > msc->mapped_hwpage_sz);
WARN_ON_ONCE(!cpumask_test_cpu(smp_processor_id(), &msc->accessibility));
- __mpam_write_reg(msc, MSMON_MBWU_L, 0);
- __mpam_write_reg(msc, MSMON_MBWU_L + 4, 0);
+ ret = __mpam_write_reg(msc, MSMON_MBWU_L, 0);
+ if (!ret)
+ ret = __mpam_write_reg(msc, MSMON_MBWU_L + 4, 0);
+
+ return ret;
}
static void gen_msmon_ctl_flt_vals(struct mon_read *m, u32 *ctl_val,
@@ -1237,10 +1242,11 @@ static inline void clean_msmon_ctl_val(u32 *cur_ctl)
*cur_ctl &= ~MSMON_CFG_MBWU_CTL_OFLOW_STATUS_L;
}
-static void write_msmon_ctl_flt_vals(struct mon_read *m, u32 ctl_val,
- u32 flt_val)
+static int write_msmon_ctl_flt_vals(struct mon_read *m, u32 ctl_val,
+ u32 flt_val)
{
struct mpam_msc *msc = m->ris->vmsc->msc;
+ int ret;
/*
* Write the ctl_val with the enable bit cleared, reset the counter,
@@ -1248,26 +1254,37 @@ static void write_msmon_ctl_flt_vals(struct mon_read *m, u32 ctl_val,
*/
switch (m->type) {
case mpam_feat_msmon_csu:
- mpam_write_monsel_reg(msc, CFG_CSU_FLT, flt_val);
- mpam_write_monsel_reg(msc, CFG_CSU_CTL, ctl_val);
- mpam_write_monsel_reg(msc, CSU, 0);
- mpam_write_monsel_reg(msc, CFG_CSU_CTL, ctl_val | MSMON_CFG_x_CTL_EN);
+ ret = mpam_write_monsel_reg(msc, CFG_CSU_FLT, flt_val);
+ if (!ret)
+ ret = mpam_write_monsel_reg(msc, CFG_CSU_CTL, ctl_val);
+ if (!ret)
+ ret = mpam_write_monsel_reg(msc, CSU, 0);
+ if (!ret)
+ ret = mpam_write_monsel_reg(msc, CFG_CSU_CTL, ctl_val | MSMON_CFG_x_CTL_EN);
break;
case mpam_feat_msmon_mbwu_31counter:
case mpam_feat_msmon_mbwu_44counter:
case mpam_feat_msmon_mbwu_63counter:
- mpam_write_monsel_reg(msc, CFG_MBWU_FLT, flt_val);
- mpam_write_monsel_reg(msc, CFG_MBWU_CTL, ctl_val);
- mpam_write_monsel_reg(msc, CFG_MBWU_CTL, ctl_val | MSMON_CFG_x_CTL_EN);
+ ret = mpam_write_monsel_reg(msc, CFG_MBWU_FLT, flt_val);
+ if (!ret)
+ ret = mpam_write_monsel_reg(msc, CFG_MBWU_CTL, ctl_val);
+ if (!ret)
+ ret = mpam_write_monsel_reg(msc, CFG_MBWU_CTL,
+ ctl_val | MSMON_CFG_x_CTL_EN);
/* Counting monitors require NRDY to be reset by software */
- if (m->type == mpam_feat_msmon_mbwu_31counter)
- mpam_write_monsel_reg(msc, MBWU, 0);
- else
- mpam_msc_zero_mbwu_l(m->ris->vmsc->msc);
+ if (!ret) {
+ if (m->type == mpam_feat_msmon_mbwu_31counter)
+ ret = mpam_write_monsel_reg(msc, MBWU, 0);
+ else
+ ret = mpam_msc_zero_mbwu_l(m->ris->vmsc->msc);
+ }
break;
default:
pr_warn("Unexpected monitor type %d\n", m->type);
+ return -EINVAL;
}
+
+ return ret;
}
static u64 __mpam_msmon_overflow_val(enum mpam_device_features type)
@@ -1323,7 +1340,9 @@ static void __ris_msmon_read(void *arg)
}
mon_sel = FIELD_PREP(MSMON_CFG_MON_SEL_MON_SEL, ctx->mon) |
FIELD_PREP(MSMON_CFG_MON_SEL_RIS, ris->ris_idx);
- mpam_write_monsel_reg(msc, CFG_MON_SEL, mon_sel);
+ ret = mpam_write_monsel_reg(msc, CFG_MON_SEL, mon_sel);
+ if (ret)
+ goto out_unlock;
switch (m->type) {
case mpam_feat_msmon_mbwu_31counter:
@@ -1359,14 +1378,16 @@ static void __ris_msmon_read(void *arg)
cur_ctl != (ctl_val | MSMON_CFG_x_CTL_EN);
if (config_mismatch || reset_on_next_read) {
- write_msmon_ctl_flt_vals(m, ctl_val, flt_val);
+ ret = write_msmon_ctl_flt_vals(m, ctl_val, flt_val);
overflow = false;
} else if (overflow) {
- mpam_write_monsel_reg(msc, CFG_MBWU_CTL,
- cur_ctl &
- ~(MSMON_CFG_x_CTL_OFLOW_STATUS |
- MSMON_CFG_MBWU_CTL_OFLOW_STATUS_L));
+ ret = mpam_write_monsel_reg(msc, CFG_MBWU_CTL,
+ cur_ctl &
+ ~(MSMON_CFG_x_CTL_OFLOW_STATUS |
+ MSMON_CFG_MBWU_CTL_OFLOW_STATUS_L));
}
+ if (ret)
+ goto out_unlock;
switch (m->type) {
case mpam_feat_msmon_csu:
@@ -1801,24 +1822,25 @@ static int mpam_save_mbwu_state(void *arg)
mon_sel = FIELD_PREP(MSMON_CFG_MON_SEL_MON_SEL, i) |
FIELD_PREP(MSMON_CFG_MON_SEL_RIS, ris->ris_idx);
- mpam_write_monsel_reg(msc, CFG_MON_SEL, mon_sel);
- ret = mpam_read_monsel_reg(msc, CFG_MBWU_FLT, &cur_flt);
+ ret = mpam_write_monsel_reg(msc, CFG_MON_SEL, mon_sel);
+ if (!ret)
+ ret = mpam_read_monsel_reg(msc, CFG_MBWU_FLT, &cur_flt);
if (!ret)
ret = mpam_read_monsel_reg(msc, CFG_MBWU_CTL, &cur_ctl);
if (!ret)
- mpam_write_monsel_reg(msc, CFG_MBWU_CTL, 0);
+ ret = mpam_write_monsel_reg(msc, CFG_MBWU_CTL, 0);
if (!ret) {
if (mpam_ris_has_mbwu_long_counter(ris)) {
val = mpam_msc_read_mbwu_l(msc);
- mpam_msc_zero_mbwu_l(msc);
+ ret = mpam_msc_zero_mbwu_l(msc);
} else {
u32 val32;
ret = mpam_read_monsel_reg(msc, MBWU, &val32);
if (!ret) {
val = val32;
- mpam_write_monsel_reg(msc, MBWU, 0);
+ ret = mpam_write_monsel_reg(msc, MBWU, 0);
}
}
}
--
2.43.0
^ permalink raw reply related
* [PATCH v2 10/15] arm_mpam: propagate MSC write errors for hardware probe functions
From: Andre Przywara @ 2026-07-02 16:22 UTC (permalink / raw)
To: Lorenzo Pieralisi, Hanjun Guo, Sudeep Holla, Catalin Marinas,
Will Deacon, Rafael J . Wysocki, Len Brown, James Morse,
Ben Horgan, Reinette Chatre, Fenghua Yu
Cc: Jonathan Cameron, Srivathsa L Rao, Ganapatrao Kulkarni,
Trilok Soni, Srinivas Ramana, Niyas Sait, linux-acpi,
linux-arm-kernel, linux-kernel
In-Reply-To: <20260702162229.4008659-1-andre.przywara@arm.com>
Allow the MSC write accesses in the hardware probe functions to return an
error, and propagate write errors from the lower level up.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
drivers/resctrl/mpam_devices.c | 29 +++++++++++++++++++----------
1 file changed, 19 insertions(+), 10 deletions(-)
diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c
index 23a5deb290b3..f3558d248c38 100644
--- a/drivers/resctrl/mpam_devices.c
+++ b/drivers/resctrl/mpam_devices.c
@@ -792,24 +792,30 @@ static bool mpam_ris_hw_probe_csu_nrdy(struct mpam_msc_ris *ris)
mon_sel = FIELD_PREP(MSMON_CFG_MON_SEL_MON_SEL, 0) |
FIELD_PREP(MSMON_CFG_MON_SEL_RIS, ris->ris_idx);
- mpam_write_monsel_reg(msc, CFG_MON_SEL, mon_sel);
+ if (mpam_write_monsel_reg(msc, CFG_MON_SEL, mon_sel))
+ return false;
/* Hardware might ignore nrdy if it's not enabled */
ctl_val = MSMON_CFG_CSU_CTL_TYPE_CSU;
ctl_val |= MSMON_CFG_x_CTL_MATCH_PARTID;
ctl_val |= MSMON_CFG_x_CTL_MATCH_PMG;
ctl_val |= MSMON_CFG_x_CTL_EN;
- mpam_write_monsel_reg(msc, CFG_CSU_FLT, 0);
- mpam_write_monsel_reg(msc, CFG_CSU_CTL, ctl_val);
+ if (mpam_write_monsel_reg(msc, CFG_CSU_FLT, 0))
+ return false;
+ if (mpam_write_monsel_reg(msc, CFG_CSU_CTL, ctl_val))
+ return false;
- _mpam_write_monsel_reg(msc, MSMON_CSU, MSMON___NRDY);
+ if (_mpam_write_monsel_reg(msc, MSMON_CSU, MSMON___NRDY))
+ return false;
if (_mpam_read_monsel_reg(msc, MSMON_CSU, &now))
return false;
can_set = now & MSMON___NRDY;
- _mpam_write_monsel_reg(msc, MSMON_CSU, 0);
+ if (_mpam_write_monsel_reg(msc, MSMON_CSU, 0))
+ return false;
/* Configuration change to try and coax hardware into setting nrdy */
- mpam_write_monsel_reg(msc, CFG_CSU_FLT, 0x1);
+ if (mpam_write_monsel_reg(msc, CFG_CSU_FLT, 0x1))
+ return false;
if (_mpam_read_monsel_reg(msc, MSMON_CSU, &now))
return false;
can_clear = !(now & MSMON___NRDY);
@@ -1052,8 +1058,9 @@ static int mpam_msc_hw_probe(struct mpam_msc *msc)
for (ris_idx = 0; ris_idx <= msc->ris_max; ris_idx++) {
mutex_lock(&msc->part_sel_lock);
- __mpam_part_sel(ris_idx, 0, msc);
- ret = mpam_msc_read_idr(msc, &idr);
+ ret = __mpam_part_sel(ris_idx, 0, msc);
+ if (!ret)
+ ret = mpam_msc_read_idr(msc, &idr);
mutex_unlock(&msc->part_sel_lock);
if (ret)
return ret;
@@ -1072,9 +1079,11 @@ static int mpam_msc_hw_probe(struct mpam_msc *msc)
ris->idr = idr;
mutex_lock(&msc->part_sel_lock);
- __mpam_part_sel(ris_idx, 0, msc);
- ret = mpam_ris_hw_probe(ris);
+ ret = __mpam_part_sel(ris_idx, 0, msc);
+ if (!ret)
+ ret = mpam_ris_hw_probe(ris);
mutex_unlock(&msc->part_sel_lock);
+
if (ret)
return ret;
}
--
2.43.0
^ permalink raw reply related
* [PATCH v2 09/15] arm_mpam: propagate MSC write errors for ESR and part_sel wrappers
From: Andre Przywara @ 2026-07-02 16:22 UTC (permalink / raw)
To: Lorenzo Pieralisi, Hanjun Guo, Sudeep Holla, Catalin Marinas,
Will Deacon, Rafael J . Wysocki, Len Brown, James Morse,
Ben Horgan, Reinette Chatre, Fenghua Yu
Cc: Jonathan Cameron, Srivathsa L Rao, Ganapatrao Kulkarni,
Trilok Soni, Srinivas Ramana, Niyas Sait, linux-acpi,
linux-arm-kernel, linux-kernel
In-Reply-To: <20260702162229.4008659-1-andre.przywara@arm.com>
Allow the wrapper functions for part_sel and ESR accesses to return an
error, and propagate write errors from the lower level up.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
drivers/resctrl/mpam_devices.c | 23 ++++++++++++-----------
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c
index a7adc75a079c..23a5deb290b3 100644
--- a/drivers/resctrl/mpam_devices.c
+++ b/drivers/resctrl/mpam_devices.c
@@ -284,12 +284,13 @@ static int mpam_msc_clear_esr(struct mpam_msc *msc)
* lower half prevent hardware from updating either half of the
* register.
*/
- if (msc->has_extd_esr)
- __mpam_write_reg(msc, MPAMF_ESR + 4, 0);
-
- __mpam_write_reg(msc, MPAMF_ESR, 0);
+ if (msc->has_extd_esr) {
+ ret = __mpam_write_reg(msc, MPAMF_ESR + 4, 0);
+ if (ret)
+ return ret;
+ }
- return 0;
+ return __mpam_write_reg(msc, MPAMF_ESR, 0);
}
static int mpam_msc_read_esr(struct mpam_msc *msc, u64 *res)
@@ -312,28 +313,28 @@ static int mpam_msc_read_esr(struct mpam_msc *msc, u64 *res)
return 0;
}
-static void __mpam_part_sel_raw(u32 partsel, struct mpam_msc *msc)
+static int __mpam_part_sel_raw(u32 partsel, struct mpam_msc *msc)
{
lockdep_assert_held(&msc->part_sel_lock);
- mpam_write_partsel_reg(msc, PART_SEL, partsel);
+ return mpam_write_partsel_reg(msc, PART_SEL, partsel);
}
-static void __mpam_part_sel(u8 ris_idx, u16 partid, struct mpam_msc *msc)
+static int __mpam_part_sel(u8 ris_idx, u16 partid, struct mpam_msc *msc)
{
u32 partsel = FIELD_PREP(MPAMCFG_PART_SEL_RIS, ris_idx) |
FIELD_PREP(MPAMCFG_PART_SEL_PARTID_SEL, partid);
- __mpam_part_sel_raw(partsel, msc);
+ return __mpam_part_sel_raw(partsel, msc);
}
-static void __mpam_intpart_sel(u8 ris_idx, u16 intpartid, struct mpam_msc *msc)
+static int __mpam_intpart_sel(u8 ris_idx, u16 intpartid, struct mpam_msc *msc)
{
u32 partsel = FIELD_PREP(MPAMCFG_PART_SEL_RIS, ris_idx) |
FIELD_PREP(MPAMCFG_PART_SEL_PARTID_SEL, intpartid) |
MPAMCFG_PART_SEL_INTERNAL;
- __mpam_part_sel_raw(partsel, msc);
+ return __mpam_part_sel_raw(partsel, msc);
}
int mpam_register_requestor(u16 partid_max, u8 pmg_max)
--
2.43.0
^ permalink raw reply related
* [PATCH v2 08/15] arm_mpam: let low level MSC write accessors return an error
From: Andre Przywara @ 2026-07-02 16:22 UTC (permalink / raw)
To: Lorenzo Pieralisi, Hanjun Guo, Sudeep Holla, Catalin Marinas,
Will Deacon, Rafael J . Wysocki, Len Brown, James Morse,
Ben Horgan, Reinette Chatre, Fenghua Yu
Cc: Jonathan Cameron, Srivathsa L Rao, Ganapatrao Kulkarni,
Trilok Soni, Srinivas Ramana, Niyas Sait, linux-acpi,
linux-arm-kernel, linux-kernel
In-Reply-To: <20260702162229.4008659-1-andre.przywara@arm.com>
The upcoming MPAM-Fb support does not use MMIO primitives to access an
MSC, but employs a shared-memory/doorbell based firmware protocol.
Its complexity means that is must be able to handle errors, whereas we
always assume an MSC access succeeds today.
Change the __mpam_write_reg() low level accessor function to return an
error code. At the moment this is always 0, but this will change with
alternative MSC access methods.
Also change some low level wrappers to propagate the error.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
drivers/resctrl/mpam_devices.c | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c
index c50ca0e4f426..a7adc75a079c 100644
--- a/drivers/resctrl/mpam_devices.c
+++ b/drivers/resctrl/mpam_devices.c
@@ -195,18 +195,20 @@ static inline int _mpam_read_partsel_reg(struct mpam_msc *msc, u16 reg,
#define mpam_read_partsel_reg(msc, reg, res) _mpam_read_partsel_reg(msc, MPAMF_##reg, res)
-static void __mpam_write_reg(struct mpam_msc *msc, u16 reg, u32 val)
+static int __mpam_write_reg(struct mpam_msc *msc, u16 reg, u32 val)
{
WARN_ON_ONCE(reg + sizeof(u32) > msc->mapped_hwpage_sz);
WARN_ON_ONCE(!cpumask_test_cpu(smp_processor_id(), &msc->accessibility));
writel_relaxed(val, msc->mapped_hwpage + reg);
+
+ return 0;
}
-static inline void _mpam_write_partsel_reg(struct mpam_msc *msc, u16 reg, u32 val)
+static inline int _mpam_write_partsel_reg(struct mpam_msc *msc, u16 reg, u32 val)
{
lockdep_assert_held_once(&msc->part_sel_lock);
- __mpam_write_reg(msc, reg, val);
+ return __mpam_write_reg(msc, reg, val);
}
#define mpam_write_partsel_reg(msc, reg, val) _mpam_write_partsel_reg(msc, MPAMCFG_##reg, val)
@@ -220,10 +222,10 @@ static inline int _mpam_read_monsel_reg(struct mpam_msc *msc, u16 reg,
#define mpam_read_monsel_reg(msc, reg, res) _mpam_read_monsel_reg(msc, MSMON_##reg, res)
-static inline void _mpam_write_monsel_reg(struct mpam_msc *msc, u16 reg, u32 val)
+static inline int _mpam_write_monsel_reg(struct mpam_msc *msc, u16 reg, u32 val)
{
mpam_mon_sel_lock_held(msc);
- __mpam_write_reg(msc, reg, val);
+ return __mpam_write_reg(msc, reg, val);
}
#define mpam_write_monsel_reg(msc, reg, val) _mpam_write_monsel_reg(msc, MSMON_##reg, val)
--
2.43.0
^ permalink raw reply related
* [PATCH v2 07/15] arm_mpam: propagate MSC read errors for state saving functions
From: Andre Przywara @ 2026-07-02 16:22 UTC (permalink / raw)
To: Lorenzo Pieralisi, Hanjun Guo, Sudeep Holla, Catalin Marinas,
Will Deacon, Rafael J . Wysocki, Len Brown, James Morse,
Ben Horgan, Reinette Chatre, Fenghua Yu
Cc: Jonathan Cameron, Srivathsa L Rao, Ganapatrao Kulkarni,
Trilok Soni, Srinivas Ramana, Niyas Sait, linux-acpi,
linux-arm-kernel, linux-kernel
In-Reply-To: <20260702162229.4008659-1-andre.przywara@arm.com>
Allow the mpam_save_mbwu_state() function to return an error, and
propagate read errors from the lower level up.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
drivers/resctrl/mpam_devices.c | 47 +++++++++++++++++++++-------------
1 file changed, 29 insertions(+), 18 deletions(-)
diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c
index d18c7be86aaa..c50ca0e4f426 100644
--- a/drivers/resctrl/mpam_devices.c
+++ b/drivers/resctrl/mpam_devices.c
@@ -1773,6 +1773,7 @@ static int mpam_save_mbwu_state(void *arg)
{
int i;
u64 val;
+ int ret;
struct mon_cfg *cfg;
u32 cur_flt, cur_ctl, mon_sel;
struct mpam_msc_ris *ris = arg;
@@ -1789,31 +1790,41 @@ static int mpam_save_mbwu_state(void *arg)
mon_sel = FIELD_PREP(MSMON_CFG_MON_SEL_MON_SEL, i) |
FIELD_PREP(MSMON_CFG_MON_SEL_RIS, ris->ris_idx);
mpam_write_monsel_reg(msc, CFG_MON_SEL, mon_sel);
- mpam_read_monsel_reg(msc, CFG_MBWU_FLT, &cur_flt);
- mpam_read_monsel_reg(msc, CFG_MBWU_CTL, &cur_ctl);
- mpam_write_monsel_reg(msc, CFG_MBWU_CTL, 0);
+ ret = mpam_read_monsel_reg(msc, CFG_MBWU_FLT, &cur_flt);
+ if (!ret)
+ ret = mpam_read_monsel_reg(msc, CFG_MBWU_CTL, &cur_ctl);
+ if (!ret)
+ mpam_write_monsel_reg(msc, CFG_MBWU_CTL, 0);
- if (mpam_ris_has_mbwu_long_counter(ris)) {
- val = mpam_msc_read_mbwu_l(msc);
- mpam_msc_zero_mbwu_l(msc);
- } else {
- u32 val32;
+ if (!ret) {
+ if (mpam_ris_has_mbwu_long_counter(ris)) {
+ val = mpam_msc_read_mbwu_l(msc);
+ mpam_msc_zero_mbwu_l(msc);
+ } else {
+ u32 val32;
- mpam_read_monsel_reg(msc, MBWU, &val32);
- val = val32;
- mpam_write_monsel_reg(msc, MBWU, 0);
+ ret = mpam_read_monsel_reg(msc, MBWU, &val32);
+ if (!ret) {
+ val = val32;
+ mpam_write_monsel_reg(msc, MBWU, 0);
+ }
+ }
}
- cfg->mon = i;
- cfg->pmg = FIELD_GET(MSMON_CFG_x_FLT_PMG, cur_flt);
- cfg->match_pmg = FIELD_GET(MSMON_CFG_x_CTL_MATCH_PMG, cur_ctl);
- cfg->partid = FIELD_GET(MSMON_CFG_x_FLT_PARTID, cur_flt);
- mbwu_state->correction += val;
- mbwu_state->enabled = FIELD_GET(MSMON_CFG_x_CTL_EN, cur_ctl);
+ if (!ret && val != MSMON___L_NRDY) {
+ cfg->mon = i;
+ cfg->pmg = FIELD_GET(MSMON_CFG_x_FLT_PMG, cur_flt);
+ cfg->match_pmg = FIELD_GET(MSMON_CFG_x_CTL_MATCH_PMG, cur_ctl);
+ cfg->partid = FIELD_GET(MSMON_CFG_x_FLT_PARTID, cur_flt);
+ mbwu_state->correction += val;
+ mbwu_state->enabled = FIELD_GET(MSMON_CFG_x_CTL_EN, cur_ctl);
+ }
mpam_mon_sel_unlock(msc);
+ if (ret)
+ break;
}
- return 0;
+ return ret;
}
/*
--
2.43.0
^ permalink raw reply related
* [PATCH v2 06/15] arm_mpam: propagate MSC read errors for __ris_msmon_read()
From: Andre Przywara @ 2026-07-02 16:22 UTC (permalink / raw)
To: Lorenzo Pieralisi, Hanjun Guo, Sudeep Holla, Catalin Marinas,
Will Deacon, Rafael J . Wysocki, Len Brown, James Morse,
Ben Horgan, Reinette Chatre, Fenghua Yu
Cc: Jonathan Cameron, Srivathsa L Rao, Ganapatrao Kulkarni,
Trilok Soni, Srinivas Ramana, Niyas Sait, linux-acpi,
linux-arm-kernel, linux-kernel
In-Reply-To: <20260702162229.4008659-1-andre.przywara@arm.com>
Allow the function for RIS accesses to return an error, and propagate
read errors from the lower level up.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
drivers/resctrl/mpam_devices.c | 35 +++++++++++++++++++++++++++-------
1 file changed, 28 insertions(+), 7 deletions(-)
diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c
index b259fe20a614..d18c7be86aaa 100644
--- a/drivers/resctrl/mpam_devices.c
+++ b/drivers/resctrl/mpam_devices.c
@@ -1285,9 +1285,14 @@ static u64 mpam_msmon_overflow_val(enum mpam_device_features type,
return overflow_val;
}
+/*
+ * This function might be called via smp_call_function_any(), so propagate
+ * errors inside the arg struct.
+ */
static void __ris_msmon_read(void *arg)
{
u64 now;
+ int ret;
u32 now32;
bool nrdy = false;
bool config_mismatch;
@@ -1326,7 +1331,9 @@ static void __ris_msmon_read(void *arg)
* Read the existing configuration to avoid re-writing the same values.
* This saves waiting for 'nrdy' on subsequent reads.
*/
- read_msmon_ctl_flt_vals(m, &cur_ctl, &cur_flt);
+ ret = read_msmon_ctl_flt_vals(m, &cur_ctl, &cur_flt);
+ if (ret)
+ goto out_unlock;
if (mpam_feat_msmon_mbwu_31counter == m->type)
overflow = cur_ctl & MSMON_CFG_x_CTL_OFLOW_STATUS;
@@ -1351,7 +1358,9 @@ static void __ris_msmon_read(void *arg)
switch (m->type) {
case mpam_feat_msmon_csu:
- mpam_read_monsel_reg(msc, CSU, &now32);
+ ret = mpam_read_monsel_reg(msc, CSU, &now32);
+ if (ret)
+ goto out_unlock;
nrdy = now32 & MSMON___NRDY;
now = FIELD_GET(MSMON___VALUE, now32);
@@ -1371,7 +1380,9 @@ static void __ris_msmon_read(void *arg)
else
now = FIELD_GET(MSMON___L_VALUE, now);
} else {
- mpam_read_monsel_reg(msc, MBWU, &now32);
+ ret = mpam_read_monsel_reg(msc, MBWU, &now32);
+ if (ret)
+ goto out_unlock;
nrdy = now32 & MSMON___NRDY;
now = FIELD_GET(MSMON___VALUE, now32);
}
@@ -1402,10 +1413,15 @@ static void __ris_msmon_read(void *arg)
if (nrdy)
m->err = -EBUSY;
- if (m->err)
- return;
+ if (!m->err)
+ *m->val += now;
+
+ return;
- *m->val += now;
+out_unlock:
+ mpam_mon_sel_unlock(msc);
+
+ m->err = ret;
}
static int _msmon_read(struct mpam_component *comp, struct mon_read *arg)
@@ -1729,6 +1745,7 @@ static int mpam_restore_mbwu_state(void *_ris)
{
int i;
u64 val;
+ int ret = 0;
struct mon_read mwbu_arg;
struct mpam_msc_ris *ris = _ris;
struct mpam_class *class = ris->vmsc->comp->class;
@@ -1741,10 +1758,14 @@ static int mpam_restore_mbwu_state(void *_ris)
mwbu_arg.val = &val;
__ris_msmon_read(&mwbu_arg);
+ if (mwbu_arg.err) {
+ ret = mwbu_arg.err;
+ break;
+ }
}
}
- return 0;
+ return ret;
}
/* Call with MSC cfg_lock held */
--
2.43.0
^ permalink raw reply related
* [PATCH v2 05/15] arm_mpam: propagate MSC read errors for msmon helpers
From: Andre Przywara @ 2026-07-02 16:22 UTC (permalink / raw)
To: Lorenzo Pieralisi, Hanjun Guo, Sudeep Holla, Catalin Marinas,
Will Deacon, Rafael J . Wysocki, Len Brown, James Morse,
Ben Horgan, Reinette Chatre, Fenghua Yu
Cc: Jonathan Cameron, Srivathsa L Rao, Ganapatrao Kulkarni,
Trilok Soni, Srinivas Ramana, Niyas Sait, linux-acpi,
linux-arm-kernel, linux-kernel
In-Reply-To: <20260702162229.4008659-1-andre.przywara@arm.com>
Allow the helper functions for msmon accesses to return an error, and
propagate read errors from the lower level up.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
drivers/resctrl/mpam_devices.c | 18 ++++++++++++------
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c
index 1d06902fb970..b259fe20a614 100644
--- a/drivers/resctrl/mpam_devices.c
+++ b/drivers/resctrl/mpam_devices.c
@@ -1189,25 +1189,31 @@ static void gen_msmon_ctl_flt_vals(struct mon_read *m, u32 *ctl_val,
}
}
-static void read_msmon_ctl_flt_vals(struct mon_read *m, u32 *ctl_val,
- u32 *flt_val)
+static int read_msmon_ctl_flt_vals(struct mon_read *m, u32 *ctl_val,
+ u32 *flt_val)
{
struct mpam_msc *msc = m->ris->vmsc->msc;
+ int ret;
switch (m->type) {
case mpam_feat_msmon_csu:
- mpam_read_monsel_reg(msc, CFG_CSU_CTL, ctl_val);
- mpam_read_monsel_reg(msc, CFG_CSU_FLT, flt_val);
+ ret = mpam_read_monsel_reg(msc, CFG_CSU_CTL, ctl_val);
+ if (!ret)
+ ret = mpam_read_monsel_reg(msc, CFG_CSU_FLT, flt_val);
break;
case mpam_feat_msmon_mbwu_31counter:
case mpam_feat_msmon_mbwu_44counter:
case mpam_feat_msmon_mbwu_63counter:
- mpam_read_monsel_reg(msc, CFG_MBWU_CTL, ctl_val);
- mpam_read_monsel_reg(msc, CFG_MBWU_FLT, flt_val);
+ ret = mpam_read_monsel_reg(msc, CFG_MBWU_CTL, ctl_val);
+ if (!ret)
+ ret = mpam_read_monsel_reg(msc, CFG_MBWU_FLT, flt_val);
break;
default:
pr_warn("Unexpected monitor type %d\n", m->type);
+ return -EINVAL;
}
+
+ return ret;
}
/* Remove values set by the hardware to prevent apparent mismatches. */
--
2.43.0
^ permalink raw reply related
* [PATCH v2 04/15] arm_mpam: propagate MSC read errors for mpam_msc_read_mbwu_l()
From: Andre Przywara @ 2026-07-02 16:22 UTC (permalink / raw)
To: Lorenzo Pieralisi, Hanjun Guo, Sudeep Holla, Catalin Marinas,
Will Deacon, Rafael J . Wysocki, Len Brown, James Morse,
Ben Horgan, Reinette Chatre, Fenghua Yu
Cc: Jonathan Cameron, Srivathsa L Rao, Ganapatrao Kulkarni,
Trilok Soni, Srinivas Ramana, Niyas Sait, linux-acpi,
linux-arm-kernel, linux-kernel
In-Reply-To: <20260702162229.4008659-1-andre.przywara@arm.com>
Allow the mpam_msc_read_mbwu_l() function to return an error, and
propagate read errors from the lower level up.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
drivers/resctrl/mpam_devices.c | 13 ++++++++++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c
index 011d1e3544d7..1d06902fb970 100644
--- a/drivers/resctrl/mpam_devices.c
+++ b/drivers/resctrl/mpam_devices.c
@@ -1106,6 +1106,7 @@ static bool mpam_ris_has_mbwu_long_counter(struct mpam_msc_ris *ris)
static u64 mpam_msc_read_mbwu_l(struct mpam_msc *msc)
{
+ int ret;
int retry = 3;
u32 mbwu_l_low;
u32 mbwu_l_high1, mbwu_l_high2;
@@ -1115,11 +1116,17 @@ static u64 mpam_msc_read_mbwu_l(struct mpam_msc *msc)
WARN_ON_ONCE((MSMON_MBWU_L + sizeof(u64)) > msc->mapped_hwpage_sz);
WARN_ON_ONCE(!cpumask_test_cpu(smp_processor_id(), &msc->accessibility));
- __mpam_read_reg(msc, MSMON_MBWU_L + 4, &mbwu_l_high2);
+ ret = __mpam_read_reg(msc, MSMON_MBWU_L + 4, &mbwu_l_high2);
+ if (ret)
+ return MSMON___L_NRDY;
+
do {
mbwu_l_high1 = mbwu_l_high2;
- __mpam_read_reg(msc, MSMON_MBWU_L, &mbwu_l_low);
- __mpam_read_reg(msc, MSMON_MBWU_L + 4, &mbwu_l_high2);
+ ret = __mpam_read_reg(msc, MSMON_MBWU_L, &mbwu_l_low);
+ if (!ret)
+ ret = __mpam_read_reg(msc, MSMON_MBWU_L + 4, &mbwu_l_high2);
+ if (ret)
+ return MSMON___L_NRDY;
retry--;
} while (mbwu_l_high1 != mbwu_l_high2 && retry > 0);
--
2.43.0
^ permalink raw reply related
* [PATCH v2 03/15] arm_mpam: propagate MSC read errors for hw_probe functions
From: Andre Przywara @ 2026-07-02 16:22 UTC (permalink / raw)
To: Lorenzo Pieralisi, Hanjun Guo, Sudeep Holla, Catalin Marinas,
Will Deacon, Rafael J . Wysocki, Len Brown, James Morse,
Ben Horgan, Reinette Chatre, Fenghua Yu
Cc: Jonathan Cameron, Srivathsa L Rao, Ganapatrao Kulkarni,
Trilok Soni, Srinivas Ramana, Niyas Sait, linux-acpi,
linux-arm-kernel, linux-kernel
In-Reply-To: <20260702162229.4008659-1-andre.przywara@arm.com>
Allow the functions probing for MSC hardware and features to return an
error, and propagate read errors from the lower level up.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
drivers/resctrl/mpam_devices.c | 62 ++++++++++++++++++++++++----------
1 file changed, 44 insertions(+), 18 deletions(-)
diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c
index ce8738adb6ff..011d1e3544d7 100644
--- a/drivers/resctrl/mpam_devices.c
+++ b/drivers/resctrl/mpam_devices.c
@@ -800,20 +800,22 @@ static bool mpam_ris_hw_probe_csu_nrdy(struct mpam_msc_ris *ris)
mpam_write_monsel_reg(msc, CFG_CSU_CTL, ctl_val);
_mpam_write_monsel_reg(msc, MSMON_CSU, MSMON___NRDY);
- _mpam_read_monsel_reg(msc, MSMON_CSU, &now);
+ if (_mpam_read_monsel_reg(msc, MSMON_CSU, &now))
+ return false;
can_set = now & MSMON___NRDY;
_mpam_write_monsel_reg(msc, MSMON_CSU, 0);
/* Configuration change to try and coax hardware into setting nrdy */
mpam_write_monsel_reg(msc, CFG_CSU_FLT, 0x1);
- _mpam_read_monsel_reg(msc, MSMON_CSU, &now);
+ if (_mpam_read_monsel_reg(msc, MSMON_CSU, &now))
+ return false;
can_clear = !(now & MSMON___NRDY);
mpam_mon_sel_unlock(msc);
return (!can_set || !can_clear);
}
-static void mpam_ris_hw_probe(struct mpam_msc_ris *ris)
+static int mpam_ris_hw_probe(struct mpam_msc_ris *ris)
{
int err;
struct mpam_msc *msc = ris->vmsc->msc;
@@ -828,7 +830,9 @@ static void mpam_ris_hw_probe(struct mpam_msc_ris *ris)
if (FIELD_GET(MPAMF_IDR_HAS_CCAP_PART, ris->idr)) {
u32 ccap_features;
- mpam_read_partsel_reg(msc, CCAP_IDR, &ccap_features);
+ err = mpam_read_partsel_reg(msc, CCAP_IDR, &ccap_features);
+ if (err)
+ return err;
props->cmax_wd = FIELD_GET(MPAMF_CCAP_IDR_CMAX_WD, ccap_features);
if (props->cmax_wd &&
@@ -853,7 +857,9 @@ static void mpam_ris_hw_probe(struct mpam_msc_ris *ris)
if (FIELD_GET(MPAMF_IDR_HAS_CPOR_PART, ris->idr)) {
u32 cpor_features;
- mpam_read_partsel_reg(msc, CPOR_IDR, &cpor_features);
+ err = mpam_read_partsel_reg(msc, CPOR_IDR, &cpor_features);
+ if (err)
+ return err;
props->cpbm_wd = FIELD_GET(MPAMF_CPOR_IDR_CPBM_WD, cpor_features);
if (props->cpbm_wd)
@@ -863,8 +869,9 @@ static void mpam_ris_hw_probe(struct mpam_msc_ris *ris)
/* Memory bandwidth partitioning */
if (FIELD_GET(MPAMF_IDR_HAS_MBW_PART, ris->idr)) {
u32 mbw_features;
-
- mpam_read_partsel_reg(msc, MBW_IDR, &mbw_features);
+ err = mpam_read_partsel_reg(msc, MBW_IDR, &mbw_features);
+ if (err)
+ return err;
/* portion bitmap resolution */
props->mbw_pbm_bits = FIELD_GET(MPAMF_MBW_IDR_BWPBM_WD, mbw_features);
@@ -893,8 +900,9 @@ static void mpam_ris_hw_probe(struct mpam_msc_ris *ris)
/* Priority partitioning */
if (FIELD_GET(MPAMF_IDR_HAS_PRI_PART, ris->idr)) {
u32 pri_features;
-
- mpam_read_partsel_reg(msc, PRI_IDR, &pri_features);
+ err = mpam_read_partsel_reg(msc, PRI_IDR, &pri_features);
+ if (err)
+ return err;
props->intpri_wd = FIELD_GET(MPAMF_PRI_IDR_INTPRI_WD, pri_features);
if (props->intpri_wd && FIELD_GET(MPAMF_PRI_IDR_HAS_INTPRI, pri_features)) {
@@ -915,7 +923,9 @@ static void mpam_ris_hw_probe(struct mpam_msc_ris *ris)
if (FIELD_GET(MPAMF_IDR_HAS_MSMON, ris->idr)) {
u32 msmon_features;
- mpam_read_partsel_reg(msc, MSMON_IDR, &msmon_features);
+ err = mpam_read_partsel_reg(msc, MSMON_IDR, &msmon_features);
+ if (err)
+ return err;
/*
* If the firmware max-nrdy-us property is missing, the
@@ -928,7 +938,9 @@ static void mpam_ris_hw_probe(struct mpam_msc_ris *ris)
if (FIELD_GET(MPAMF_MSMON_IDR_MSMON_CSU, msmon_features)) {
u32 csumonidr;
- mpam_read_partsel_reg(msc, CSUMON_IDR, &csumonidr);
+ err = mpam_read_partsel_reg(msc, CSUMON_IDR, &csumonidr);
+ if (err)
+ return err;
props->num_csu_mon = FIELD_GET(MPAMF_CSUMON_IDR_NUM_MON, csumonidr);
if (props->num_csu_mon) {
@@ -954,7 +966,9 @@ static void mpam_ris_hw_probe(struct mpam_msc_ris *ris)
bool has_long;
u32 mbwumon_idr;
- mpam_read_partsel_reg(msc, MBWUMON_IDR, &mbwumon_idr);
+ err = mpam_read_partsel_reg(msc, MBWUMON_IDR, &mbwumon_idr);
+ if (err)
+ return err;
props->num_mbwu_mon = FIELD_GET(MPAMF_MBWUMON_IDR_NUM_MON, mbwumon_idr);
if (props->num_mbwu_mon) {
@@ -987,16 +1001,22 @@ static void mpam_ris_hw_probe(struct mpam_msc_ris *ris)
u16 partid_max;
u32 nrwidr;
- mpam_read_partsel_reg(msc, PARTID_NRW_IDR, &nrwidr);
+ err = mpam_read_partsel_reg(msc, PARTID_NRW_IDR, &nrwidr);
+ if (err)
+ return err;
+
partid_max = FIELD_GET(MPAMF_PARTID_NRW_IDR_INTPARTID_MAX, nrwidr);
mpam_set_feature(mpam_feat_partid_nrw, props);
msc->partid_max = min(msc->partid_max, partid_max);
}
+
+ return 0;
}
static int mpam_msc_hw_probe(struct mpam_msc *msc)
{
+ int ret;
u64 idr;
u16 partid_max;
u8 ris_idx, pmg_max;
@@ -1012,10 +1032,12 @@ static int mpam_msc_hw_probe(struct mpam_msc *msc)
/* Grab an IDR value to find out how many RIS there are */
mutex_lock(&msc->part_sel_lock);
- mpam_msc_read_idr(msc, &idr);
- mpam_read_partsel_reg(msc, IIDR, &msc->iidr);
-
+ ret = mpam_msc_read_idr(msc, &idr);
+ if (!ret)
+ ret = mpam_read_partsel_reg(msc, IIDR, &msc->iidr);
mutex_unlock(&msc->part_sel_lock);
+ if (ret)
+ return ret;
mpam_enable_quirks(msc);
@@ -1028,8 +1050,10 @@ static int mpam_msc_hw_probe(struct mpam_msc *msc)
for (ris_idx = 0; ris_idx <= msc->ris_max; ris_idx++) {
mutex_lock(&msc->part_sel_lock);
__mpam_part_sel(ris_idx, 0, msc);
- mpam_msc_read_idr(msc, &idr);
+ ret = mpam_msc_read_idr(msc, &idr);
mutex_unlock(&msc->part_sel_lock);
+ if (ret)
+ return ret;
partid_max = FIELD_GET(MPAMF_IDR_PARTID_MAX, idr);
pmg_max = FIELD_GET(MPAMF_IDR_PMG_MAX, idr);
@@ -1046,8 +1070,10 @@ static int mpam_msc_hw_probe(struct mpam_msc *msc)
mutex_lock(&msc->part_sel_lock);
__mpam_part_sel(ris_idx, 0, msc);
- mpam_ris_hw_probe(ris);
+ ret = mpam_ris_hw_probe(ris);
mutex_unlock(&msc->part_sel_lock);
+ if (ret)
+ return ret;
}
/* Clear any stale errors */
--
2.43.0
^ permalink raw reply related
* [PATCH v2 02/15] arm_mpam: propagate MSC read errors for wrapper functions
From: Andre Przywara @ 2026-07-02 16:22 UTC (permalink / raw)
To: Lorenzo Pieralisi, Hanjun Guo, Sudeep Holla, Catalin Marinas,
Will Deacon, Rafael J . Wysocki, Len Brown, James Morse,
Ben Horgan, Reinette Chatre, Fenghua Yu
Cc: Jonathan Cameron, Srivathsa L Rao, Ganapatrao Kulkarni,
Trilok Soni, Srinivas Ramana, Niyas Sait, linux-acpi,
linux-arm-kernel, linux-kernel
In-Reply-To: <20260702162229.4008659-1-andre.przywara@arm.com>
Allow the wrapper functions for IDR and ESR accesses to return an
error, and propagate read errors from the lower level up.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
drivers/resctrl/mpam_devices.c | 51 +++++++++++++++++++++++-----------
1 file changed, 35 insertions(+), 16 deletions(-)
diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c
index df14b4513382..ce8738adb6ff 100644
--- a/drivers/resctrl/mpam_devices.c
+++ b/drivers/resctrl/mpam_devices.c
@@ -247,27 +247,34 @@ static bool mpam_msc_check_aidr(struct mpam_msc *msc)
return true;
}
-static u64 mpam_msc_read_idr(struct mpam_msc *msc)
+static int mpam_msc_read_idr(struct mpam_msc *msc, u64 *res)
{
u32 idr_high = 0, idr_low;
+ int ret;
lockdep_assert_held(&msc->part_sel_lock);
- mpam_read_partsel_reg(msc, IDR, &idr_low);
- if (FIELD_GET(MPAMF_IDR_EXT, idr_low))
- mpam_read_partsel_reg(msc, IDR + 4, &idr_high);
+ ret = mpam_read_partsel_reg(msc, IDR, &idr_low);
+ if (!ret && FIELD_GET(MPAMF_IDR_EXT, idr_low))
+ ret = mpam_read_partsel_reg(msc, IDR + 4, &idr_high);
- return ((u64)idr_high << 32) | idr_low;
+ if (!ret)
+ *res = ((u64)idr_high << 32) | idr_low;
+
+ return ret;
}
-static void mpam_msc_clear_esr(struct mpam_msc *msc)
+static int mpam_msc_clear_esr(struct mpam_msc *msc)
{
u32 esr_low;
+ int ret;
- __mpam_read_reg(msc, MPAMF_ESR, &esr_low);
+ ret = __mpam_read_reg(msc, MPAMF_ESR, &esr_low);
+ if (ret)
+ return ret;
if (!esr_low)
- return;
+ return 0;
/*
* Clearing the high/low bits of MPAMF_ESR can not be atomic.
@@ -277,18 +284,30 @@ static void mpam_msc_clear_esr(struct mpam_msc *msc)
*/
if (msc->has_extd_esr)
__mpam_write_reg(msc, MPAMF_ESR + 4, 0);
+
__mpam_write_reg(msc, MPAMF_ESR, 0);
+
+ return 0;
}
-static u64 mpam_msc_read_esr(struct mpam_msc *msc)
+static int mpam_msc_read_esr(struct mpam_msc *msc, u64 *res)
{
u32 esr_high = 0, esr_low;
+ int ret;
- __mpam_read_reg(msc, MPAMF_ESR, &esr_low);
- if (msc->has_extd_esr)
- __mpam_read_reg(msc, MPAMF_ESR + 4, &esr_high);
+ ret = __mpam_read_reg(msc, MPAMF_ESR, &esr_low);
+ if (ret)
+ return ret;
+
+ if (msc->has_extd_esr) {
+ ret = __mpam_read_reg(msc, MPAMF_ESR + 4, &esr_high);
+ if (ret)
+ return ret;
+ }
- return ((u64)esr_high << 32) | esr_low;
+ *res = ((u64)esr_high << 32) | esr_low;
+
+ return 0;
}
static void __mpam_part_sel_raw(u32 partsel, struct mpam_msc *msc)
@@ -993,7 +1012,7 @@ static int mpam_msc_hw_probe(struct mpam_msc *msc)
/* Grab an IDR value to find out how many RIS there are */
mutex_lock(&msc->part_sel_lock);
- idr = mpam_msc_read_idr(msc);
+ mpam_msc_read_idr(msc, &idr);
mpam_read_partsel_reg(msc, IIDR, &msc->iidr);
mutex_unlock(&msc->part_sel_lock);
@@ -1009,7 +1028,7 @@ static int mpam_msc_hw_probe(struct mpam_msc *msc)
for (ris_idx = 0; ris_idx <= msc->ris_max; ris_idx++) {
mutex_lock(&msc->part_sel_lock);
__mpam_part_sel(ris_idx, 0, msc);
- idr = mpam_msc_read_idr(msc);
+ mpam_msc_read_idr(msc, &idr);
mutex_unlock(&msc->part_sel_lock);
partid_max = FIELD_GET(MPAMF_IDR_PARTID_MAX, idr);
@@ -2492,7 +2511,7 @@ static irqreturn_t __mpam_irq_handler(int irq, struct mpam_msc *msc)
&msc->accessibility)))
return IRQ_NONE;
- reg = mpam_msc_read_esr(msc);
+ mpam_msc_read_esr(msc, ®);
errcode = FIELD_GET(MPAMF_ESR_ERRCODE, reg);
if (!errcode)
--
2.43.0
^ permalink raw reply related
* [PATCH v2 01/15] arm_mpam: let low level MSC read accessors return an error
From: Andre Przywara @ 2026-07-02 16:22 UTC (permalink / raw)
To: Lorenzo Pieralisi, Hanjun Guo, Sudeep Holla, Catalin Marinas,
Will Deacon, Rafael J . Wysocki, Len Brown, James Morse,
Ben Horgan, Reinette Chatre, Fenghua Yu
Cc: Jonathan Cameron, Srivathsa L Rao, Ganapatrao Kulkarni,
Trilok Soni, Srinivas Ramana, Niyas Sait, linux-acpi,
linux-arm-kernel, linux-kernel
In-Reply-To: <20260702162229.4008659-1-andre.przywara@arm.com>
The upcoming MPAM-Fb support does not use MMIO primitives to access an
MSC, but employs a shared-memory/doorbell based firmware protocol.
Its complexity means that is must be able to handle errors, whereas we
always assume an MSC access succeeds today.
Change the __mpam_read_reg() low level accessor function to return the
requested data through a pointer, and return an error code instead.
At the moment this is always 0, but this will change with alternative
MSC access methods.
Change all users of those MSC read wrappers to comply with the new
prototype, though at the moment without propagating any errors.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
drivers/resctrl/mpam_devices.c | 129 ++++++++++++++++++++-------------
1 file changed, 78 insertions(+), 51 deletions(-)
diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c
index b69f99488111..df14b4513382 100644
--- a/drivers/resctrl/mpam_devices.c
+++ b/drivers/resctrl/mpam_devices.c
@@ -177,20 +177,23 @@ static void mpam_assert_partid_sizes_fixed(void)
WARN_ON_ONCE(!partid_max_published);
}
-static u32 __mpam_read_reg(struct mpam_msc *msc, u16 reg)
+static int __mpam_read_reg(struct mpam_msc *msc, u16 reg, u32 *res)
{
WARN_ON_ONCE(!cpumask_test_cpu(smp_processor_id(), &msc->accessibility));
- return readl_relaxed(msc->mapped_hwpage + reg);
+ *res = readl_relaxed(msc->mapped_hwpage + reg);
+
+ return 0;
}
-static inline u32 _mpam_read_partsel_reg(struct mpam_msc *msc, u16 reg)
+static inline int _mpam_read_partsel_reg(struct mpam_msc *msc, u16 reg,
+ u32 *res)
{
lockdep_assert_held_once(&msc->part_sel_lock);
- return __mpam_read_reg(msc, reg);
+ return __mpam_read_reg(msc, reg, res);
}
-#define mpam_read_partsel_reg(msc, reg) _mpam_read_partsel_reg(msc, MPAMF_##reg)
+#define mpam_read_partsel_reg(msc, reg, res) _mpam_read_partsel_reg(msc, MPAMF_##reg, res)
static void __mpam_write_reg(struct mpam_msc *msc, u16 reg, u32 val)
{
@@ -208,13 +211,14 @@ static inline void _mpam_write_partsel_reg(struct mpam_msc *msc, u16 reg, u32 va
#define mpam_write_partsel_reg(msc, reg, val) _mpam_write_partsel_reg(msc, MPAMCFG_##reg, val)
-static inline u32 _mpam_read_monsel_reg(struct mpam_msc *msc, u16 reg)
+static inline int _mpam_read_monsel_reg(struct mpam_msc *msc, u16 reg,
+ u32 *res)
{
mpam_mon_sel_lock_held(msc);
- return __mpam_read_reg(msc, reg);
+ return __mpam_read_reg(msc, reg, res);
}
-#define mpam_read_monsel_reg(msc, reg) _mpam_read_monsel_reg(msc, MSMON_##reg)
+#define mpam_read_monsel_reg(msc, reg, res) _mpam_read_monsel_reg(msc, MSMON_##reg, res)
static inline void _mpam_write_monsel_reg(struct mpam_msc *msc, u16 reg, u32 val)
{
@@ -226,10 +230,11 @@ static inline void _mpam_write_monsel_reg(struct mpam_msc *msc, u16 reg, u32 val
static bool mpam_msc_check_aidr(struct mpam_msc *msc)
{
- u32 aidr = __mpam_read_reg(msc, MPAMF_AIDR);
- u32 major = FIELD_GET(MPAMF_AIDR_ARCH_MAJOR_REV, aidr);
- u32 minor = FIELD_GET(MPAMF_AIDR_ARCH_MINOR_REV, aidr);
+ u32 aidr, major, minor;
+ __mpam_read_reg(msc, MPAMF_AIDR, &aidr);
+ major = FIELD_GET(MPAMF_AIDR_ARCH_MAJOR_REV, aidr);
+ minor = FIELD_GET(MPAMF_AIDR_ARCH_MINOR_REV, aidr);
/*
* v0.0 and >v2.x aren't supported, but anything else should be backward
* compatible to v0.1 or v1.0.
@@ -244,20 +249,22 @@ static bool mpam_msc_check_aidr(struct mpam_msc *msc)
static u64 mpam_msc_read_idr(struct mpam_msc *msc)
{
- u64 idr_high = 0, idr_low;
+ u32 idr_high = 0, idr_low;
lockdep_assert_held(&msc->part_sel_lock);
- idr_low = mpam_read_partsel_reg(msc, IDR);
+ mpam_read_partsel_reg(msc, IDR, &idr_low);
if (FIELD_GET(MPAMF_IDR_EXT, idr_low))
- idr_high = mpam_read_partsel_reg(msc, IDR + 4);
+ mpam_read_partsel_reg(msc, IDR + 4, &idr_high);
- return (idr_high << 32) | idr_low;
+ return ((u64)idr_high << 32) | idr_low;
}
static void mpam_msc_clear_esr(struct mpam_msc *msc)
{
- u64 esr_low = __mpam_read_reg(msc, MPAMF_ESR);
+ u32 esr_low;
+
+ __mpam_read_reg(msc, MPAMF_ESR, &esr_low);
if (!esr_low)
return;
@@ -275,13 +282,13 @@ static void mpam_msc_clear_esr(struct mpam_msc *msc)
static u64 mpam_msc_read_esr(struct mpam_msc *msc)
{
- u64 esr_high = 0, esr_low;
+ u32 esr_high = 0, esr_low;
- esr_low = __mpam_read_reg(msc, MPAMF_ESR);
+ __mpam_read_reg(msc, MPAMF_ESR, &esr_low);
if (msc->has_extd_esr)
- esr_high = __mpam_read_reg(msc, MPAMF_ESR + 4);
+ __mpam_read_reg(msc, MPAMF_ESR + 4, &esr_high);
- return (esr_high << 32) | esr_low;
+ return ((u64)esr_high << 32) | esr_low;
}
static void __mpam_part_sel_raw(u32 partsel, struct mpam_msc *msc)
@@ -774,13 +781,13 @@ static bool mpam_ris_hw_probe_csu_nrdy(struct mpam_msc_ris *ris)
mpam_write_monsel_reg(msc, CFG_CSU_CTL, ctl_val);
_mpam_write_monsel_reg(msc, MSMON_CSU, MSMON___NRDY);
- now = _mpam_read_monsel_reg(msc, MSMON_CSU);
+ _mpam_read_monsel_reg(msc, MSMON_CSU, &now);
can_set = now & MSMON___NRDY;
_mpam_write_monsel_reg(msc, MSMON_CSU, 0);
/* Configuration change to try and coax hardware into setting nrdy */
mpam_write_monsel_reg(msc, CFG_CSU_FLT, 0x1);
- now = _mpam_read_monsel_reg(msc, MSMON_CSU);
+ _mpam_read_monsel_reg(msc, MSMON_CSU, &now);
can_clear = !(now & MSMON___NRDY);
mpam_mon_sel_unlock(msc);
@@ -800,7 +807,9 @@ static void mpam_ris_hw_probe(struct mpam_msc_ris *ris)
/* Cache Capacity Partitioning */
if (FIELD_GET(MPAMF_IDR_HAS_CCAP_PART, ris->idr)) {
- u32 ccap_features = mpam_read_partsel_reg(msc, CCAP_IDR);
+ u32 ccap_features;
+
+ mpam_read_partsel_reg(msc, CCAP_IDR, &ccap_features);
props->cmax_wd = FIELD_GET(MPAMF_CCAP_IDR_CMAX_WD, ccap_features);
if (props->cmax_wd &&
@@ -823,7 +832,9 @@ static void mpam_ris_hw_probe(struct mpam_msc_ris *ris)
/* Cache Portion partitioning */
if (FIELD_GET(MPAMF_IDR_HAS_CPOR_PART, ris->idr)) {
- u32 cpor_features = mpam_read_partsel_reg(msc, CPOR_IDR);
+ u32 cpor_features;
+
+ mpam_read_partsel_reg(msc, CPOR_IDR, &cpor_features);
props->cpbm_wd = FIELD_GET(MPAMF_CPOR_IDR_CPBM_WD, cpor_features);
if (props->cpbm_wd)
@@ -832,7 +843,9 @@ static void mpam_ris_hw_probe(struct mpam_msc_ris *ris)
/* Memory bandwidth partitioning */
if (FIELD_GET(MPAMF_IDR_HAS_MBW_PART, ris->idr)) {
- u32 mbw_features = mpam_read_partsel_reg(msc, MBW_IDR);
+ u32 mbw_features;
+
+ mpam_read_partsel_reg(msc, MBW_IDR, &mbw_features);
/* portion bitmap resolution */
props->mbw_pbm_bits = FIELD_GET(MPAMF_MBW_IDR_BWPBM_WD, mbw_features);
@@ -860,7 +873,9 @@ static void mpam_ris_hw_probe(struct mpam_msc_ris *ris)
/* Priority partitioning */
if (FIELD_GET(MPAMF_IDR_HAS_PRI_PART, ris->idr)) {
- u32 pri_features = mpam_read_partsel_reg(msc, PRI_IDR);
+ u32 pri_features;
+
+ mpam_read_partsel_reg(msc, PRI_IDR, &pri_features);
props->intpri_wd = FIELD_GET(MPAMF_PRI_IDR_INTPRI_WD, pri_features);
if (props->intpri_wd && FIELD_GET(MPAMF_PRI_IDR_HAS_INTPRI, pri_features)) {
@@ -879,7 +894,9 @@ static void mpam_ris_hw_probe(struct mpam_msc_ris *ris)
/* Performance Monitoring */
if (FIELD_GET(MPAMF_IDR_HAS_MSMON, ris->idr)) {
- u32 msmon_features = mpam_read_partsel_reg(msc, MSMON_IDR);
+ u32 msmon_features;
+
+ mpam_read_partsel_reg(msc, MSMON_IDR, &msmon_features);
/*
* If the firmware max-nrdy-us property is missing, the
@@ -892,7 +909,8 @@ static void mpam_ris_hw_probe(struct mpam_msc_ris *ris)
if (FIELD_GET(MPAMF_MSMON_IDR_MSMON_CSU, msmon_features)) {
u32 csumonidr;
- csumonidr = mpam_read_partsel_reg(msc, CSUMON_IDR);
+ mpam_read_partsel_reg(msc, CSUMON_IDR, &csumonidr);
+
props->num_csu_mon = FIELD_GET(MPAMF_CSUMON_IDR_NUM_MON, csumonidr);
if (props->num_csu_mon) {
bool hw_managed;
@@ -915,7 +933,9 @@ static void mpam_ris_hw_probe(struct mpam_msc_ris *ris)
}
if (FIELD_GET(MPAMF_MSMON_IDR_MSMON_MBWU, msmon_features)) {
bool has_long;
- u32 mbwumon_idr = mpam_read_partsel_reg(msc, MBWUMON_IDR);
+ u32 mbwumon_idr;
+
+ mpam_read_partsel_reg(msc, MBWUMON_IDR, &mbwumon_idr);
props->num_mbwu_mon = FIELD_GET(MPAMF_MBWUMON_IDR_NUM_MON, mbwumon_idr);
if (props->num_mbwu_mon) {
@@ -945,8 +965,11 @@ static void mpam_ris_hw_probe(struct mpam_msc_ris *ris)
*/
if (FIELD_GET(MPAMF_IDR_HAS_PARTID_NRW, ris->idr) &&
class->type != MPAM_CLASS_UNKNOWN) {
- u32 nrwidr = mpam_read_partsel_reg(msc, PARTID_NRW_IDR);
- u16 partid_max = FIELD_GET(MPAMF_PARTID_NRW_IDR_INTPARTID_MAX, nrwidr);
+ u16 partid_max;
+ u32 nrwidr;
+
+ mpam_read_partsel_reg(msc, PARTID_NRW_IDR, &nrwidr);
+ partid_max = FIELD_GET(MPAMF_PARTID_NRW_IDR_INTPARTID_MAX, nrwidr);
mpam_set_feature(mpam_feat_partid_nrw, props);
msc->partid_max = min(msc->partid_max, partid_max);
@@ -971,7 +994,8 @@ static int mpam_msc_hw_probe(struct mpam_msc *msc)
/* Grab an IDR value to find out how many RIS there are */
mutex_lock(&msc->part_sel_lock);
idr = mpam_msc_read_idr(msc);
- msc->iidr = mpam_read_partsel_reg(msc, IIDR);
+ mpam_read_partsel_reg(msc, IIDR, &msc->iidr);
+
mutex_unlock(&msc->part_sel_lock);
mpam_enable_quirks(msc);
@@ -1039,24 +1063,24 @@ static u64 mpam_msc_read_mbwu_l(struct mpam_msc *msc)
{
int retry = 3;
u32 mbwu_l_low;
- u64 mbwu_l_high1, mbwu_l_high2;
+ u32 mbwu_l_high1, mbwu_l_high2;
mpam_mon_sel_lock_held(msc);
WARN_ON_ONCE((MSMON_MBWU_L + sizeof(u64)) > msc->mapped_hwpage_sz);
WARN_ON_ONCE(!cpumask_test_cpu(smp_processor_id(), &msc->accessibility));
- mbwu_l_high2 = __mpam_read_reg(msc, MSMON_MBWU_L + 4);
+ __mpam_read_reg(msc, MSMON_MBWU_L + 4, &mbwu_l_high2);
do {
mbwu_l_high1 = mbwu_l_high2;
- mbwu_l_low = __mpam_read_reg(msc, MSMON_MBWU_L);
- mbwu_l_high2 = __mpam_read_reg(msc, MSMON_MBWU_L + 4);
+ __mpam_read_reg(msc, MSMON_MBWU_L, &mbwu_l_low);
+ __mpam_read_reg(msc, MSMON_MBWU_L + 4, &mbwu_l_high2);
retry--;
} while (mbwu_l_high1 != mbwu_l_high2 && retry > 0);
if (mbwu_l_high1 == mbwu_l_high2)
- return (mbwu_l_high1 << 32) | mbwu_l_low;
+ return ((u64)mbwu_l_high1 << 32) | mbwu_l_low;
pr_warn("Failed to read a stable value\n");
return MSMON___L_NRDY;
@@ -1120,14 +1144,14 @@ static void read_msmon_ctl_flt_vals(struct mon_read *m, u32 *ctl_val,
switch (m->type) {
case mpam_feat_msmon_csu:
- *ctl_val = mpam_read_monsel_reg(msc, CFG_CSU_CTL);
- *flt_val = mpam_read_monsel_reg(msc, CFG_CSU_FLT);
+ mpam_read_monsel_reg(msc, CFG_CSU_CTL, ctl_val);
+ mpam_read_monsel_reg(msc, CFG_CSU_FLT, flt_val);
break;
case mpam_feat_msmon_mbwu_31counter:
case mpam_feat_msmon_mbwu_44counter:
case mpam_feat_msmon_mbwu_63counter:
- *ctl_val = mpam_read_monsel_reg(msc, CFG_MBWU_CTL);
- *flt_val = mpam_read_monsel_reg(msc, CFG_MBWU_FLT);
+ mpam_read_monsel_reg(msc, CFG_MBWU_CTL, ctl_val);
+ mpam_read_monsel_reg(msc, CFG_MBWU_FLT, flt_val);
break;
default:
pr_warn("Unexpected monitor type %d\n", m->type);
@@ -1206,6 +1230,7 @@ static u64 mpam_msmon_overflow_val(enum mpam_device_features type,
static void __ris_msmon_read(void *arg)
{
u64 now;
+ u32 now32;
bool nrdy = false;
bool config_mismatch;
bool overflow = false;
@@ -1268,9 +1293,9 @@ static void __ris_msmon_read(void *arg)
switch (m->type) {
case mpam_feat_msmon_csu:
- now = mpam_read_monsel_reg(msc, CSU);
- nrdy = now & MSMON___NRDY;
- now = FIELD_GET(MSMON___VALUE, now);
+ mpam_read_monsel_reg(msc, CSU, &now32);
+ nrdy = now32 & MSMON___NRDY;
+ now = FIELD_GET(MSMON___VALUE, now32);
if (mpam_has_quirk(IGNORE_CSU_NRDY, msc) && m->waited_timeout)
nrdy = false;
@@ -1288,9 +1313,9 @@ static void __ris_msmon_read(void *arg)
else
now = FIELD_GET(MSMON___L_VALUE, now);
} else {
- now = mpam_read_monsel_reg(msc, MBWU);
- nrdy = now & MSMON___NRDY;
- now = FIELD_GET(MSMON___VALUE, now);
+ mpam_read_monsel_reg(msc, MBWU, &now32);
+ nrdy = now32 & MSMON___NRDY;
+ now = FIELD_GET(MSMON___VALUE, now32);
}
if (mpam_has_quirk(T241_MBW_COUNTER_SCALE_64, msc) &&
@@ -1685,16 +1710,18 @@ static int mpam_save_mbwu_state(void *arg)
mon_sel = FIELD_PREP(MSMON_CFG_MON_SEL_MON_SEL, i) |
FIELD_PREP(MSMON_CFG_MON_SEL_RIS, ris->ris_idx);
mpam_write_monsel_reg(msc, CFG_MON_SEL, mon_sel);
-
- cur_flt = mpam_read_monsel_reg(msc, CFG_MBWU_FLT);
- cur_ctl = mpam_read_monsel_reg(msc, CFG_MBWU_CTL);
+ mpam_read_monsel_reg(msc, CFG_MBWU_FLT, &cur_flt);
+ mpam_read_monsel_reg(msc, CFG_MBWU_CTL, &cur_ctl);
mpam_write_monsel_reg(msc, CFG_MBWU_CTL, 0);
if (mpam_ris_has_mbwu_long_counter(ris)) {
val = mpam_msc_read_mbwu_l(msc);
mpam_msc_zero_mbwu_l(msc);
} else {
- val = mpam_read_monsel_reg(msc, MBWU);
+ u32 val32;
+
+ mpam_read_monsel_reg(msc, MBWU, &val32);
+ val = val32;
mpam_write_monsel_reg(msc, MBWU, 0);
}
--
2.43.0
^ permalink raw reply related
* [PATCH v2 00/15] arm_mpam: Add MPAM-Fb firmware support
From: Andre Przywara @ 2026-07-02 16:22 UTC (permalink / raw)
To: Lorenzo Pieralisi, Hanjun Guo, Sudeep Holla, Catalin Marinas,
Will Deacon, Rafael J . Wysocki, Len Brown, James Morse,
Ben Horgan, Reinette Chatre, Fenghua Yu
Cc: Jonathan Cameron, Srivathsa L Rao, Ganapatrao Kulkarni,
Trilok Soni, Srinivas Ramana, Niyas Sait, linux-acpi,
linux-arm-kernel, linux-kernel
Hi,
version 2 of the MPAM-Fb code, for firmware based MSC accesses.
Major change is a rudimentary propagation of errors during the MSC
accesses, this has been split up into 11 patches, coming first in this
series. The patch to parse additional information from the ACPI table
has been dropped (former patch 1/5), as it's actually not needed for
MPAM-Fb, and the features parsed are not supported by the kernel yet.
Quite some details have been fixed in the remaining patches, thanks to
the diligent reviewers. This should address most of the comments, but
I am pretty sure this won't be the final version ;-)
Find a changelog below. Based on v7.2-rc1.
=======================
The Arm MPAM specification defines Memory System Components (MSCs),
which are devices that are programmed through an MMIO register frame. In
some occasions this turned out to be too limiting: the MSC might be
located behind a separate bus system (for instance inside an on-board
controller), it might be mapped secure-only, or in a different processor
socket without direct MMIO mapping. Also the MMIO access might be too slow
or it would need to be filtered or otherwise access controlled. Finally
there might be bugs in the MSC integration, which require a mediating
firmware to be accessible.
To accommodate all those different use cases, the MPAM-Fb specification
[1] describes an alternative way to access MSCs. Accesses to an MSC
would be wrapped in a message and communicated to the system using a
shared-memory/mailbox system mostly mimicking the Arm SCMI spec.
For ACPI systems, this would be abstracted through an ACPI PCC channel,
which provides the shared-memory region and the mailbox trigger. We can
lean on existing ACPI parsing code to register with these two
subsystems, but cannot rely on the existing SCMI code in the kernel.
This means we somewhat need to open code a very simplified SCMI handler,
which just provides enough functionality for the very basic subset of
SCMI that the MPAM-Fb spec requires.
The first 11 patches rework all MSC access wrappers to propagate error
information. Pure MMIO based MSC accesses would never fail, but the
MPAM-Fb access can go wrong in multiple ways. The patches have been split
up purely for reviewing reasons, if the number is a problem, we could as
well squash them.
Patch 12/15 solves a nasty problem: At the moment we protect stateful MSC
register accesses (mon_sel) through a spinlock. Unfortunately the mailbox
subsystem and the slow nature of the communication through this channel
forbid MPAM-Fb access in atomic context. So this patch splits the lock
in two: the "outer" one is a mutex, and only the inner one is a
spinlock, which would need to be taken when programming MSCs inside an
interrupt handler, for instance. We just deny the latter when using
MPAM-Fb, ideally we wouldn't need that (no need to IPI another core when
the MSC access does not need to be local to one particular core), or we
simply deny that part of the functionality (access through perf).
Patch 13/15 adds the code to redirect MSC accesses through the
PCC shmem/mailbox system.
Patch 14/15 avoids the error IRQ handler to do an MSC access when using
MPAM_Fb, since those accesses cannot run in atomic context.
The final patch 15/15 then adds the code to detect and store the PCC
channel information from the ACPI tables, and eventually enables
MPAM-Fb accesses.
This would enable systems where some MSCs are not accessible via MMIO to
use those components anyway.
Please have a look and test!
Cheers,
Andre
[1] https://developer.arm.com/documentation/den0144/latest
Changelog v1 .. v2:
- add patches to add error propagation to MSC access wrappers
- drop former patch 1/5 (not needed)
- drop lock in mpam_reprogram_msc(), to avoid double lock
- add support for multiple MSCs per PCC channel
- adjust SCMI protocol code to use a PCC subtype 3 channel
- let PCC code handle the PCC channel negotiation (due to subtype 3)
- drop SCMI names in shmem offsets, and use existing PCC type 3 struct
- adjust shmem field offsets to match MPAM-Fb spec, not pure SCMI
- prevent MPAM-Fb calls inside atomic smp_call_function_any() payload
- skip all MSC accesses inside the IRQ handler when using MPAM-Fb
Andre Przywara (14):
arm_mpam: let low level MSC read accessors return an error
arm_mpam: propagate MSC read errors for wrapper functions
arm_mpam: propagate MSC read errors for hw_probe functions
arm_mpam: propagate MSC read errors for mpam_msc_read_mbwu_l()
arm_mpam: propagate MSC read errors for msmon helpers
arm_mpam: propagate MSC read errors for __ris_msmon_read()
arm_mpam: propagate MSC read errors for state saving functions
arm_mpam: let low level MSC write accessors return an error
arm_mpam: propagate MSC write errors for ESR and part_sel wrappers
arm_mpam: propagate MSC write errors for hardware probe functions
arm_mpam: propagate MSC write errors for remaining MSC write users
arm_mpam: add MPAM-Fb MSC firmware access support
arm_mpam: prevent MPAM-Fb accesses inside IRQ handler
arm_mpam: detect and enable MPAM-Fb PCC support
James Morse (1):
arm_mpam: Split the locking around the mon_sel registers
drivers/acpi/arm64/mpam.c | 2 +
drivers/resctrl/Makefile | 2 +-
drivers/resctrl/mpam_devices.c | 630 ++++++++++++++++++++++++--------
drivers/resctrl/mpam_fb.c | 137 +++++++
drivers/resctrl/mpam_fb.h | 17 +
drivers/resctrl/mpam_internal.h | 79 +++-
include/linux/arm_mpam.h | 2 +-
7 files changed, 688 insertions(+), 181 deletions(-)
create mode 100644 drivers/resctrl/mpam_fb.c
create mode 100644 drivers/resctrl/mpam_fb.h
base-commit: dc59e4fea9d83f03bad6bddf3fa2e52491777482
--
2.43.0
^ permalink raw reply
* Re: [PATCH v7 2/8] media: subdev: Add media_async_register_subdev() helper
From: Laurent Pinchart @ 2026-07-02 16:15 UTC (permalink / raw)
To: Frank.Li
Cc: Sakari Ailus, Mauro Carvalho Chehab, Michael Riesch, Frank Li,
Martin Kepplinger-Novakovic, Rui Miguel Silva, Purism Kernel Team,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, linux-media, linux-kernel,
imx, Guoniu Zhou, devicetree, linux-arm-kernel
In-Reply-To: <20260702-imx8qxp_pcam-v7-2-b47d9e363400@nxp.com>
Hi Frank,
Have you missed the comment in v6 ?
https://lore.kernel.org/all/20260629084654.GB3054459@killaraus.ideasonboard.com/
On Thu, Jul 02, 2026 at 12:03:58PM -0400, Frank.Li@oss.nxp.com wrote:
> From: Frank Li <Frank.Li@nxp.com>
>
> Add media_async_register_subdev(), a helper to register a V4L2 sub-device
> with the asynchronous sub-device framework.
>
> The helper requires each port to contain a single endpoint, with port
> addresses starting at 0 and increasing consecutively.
>
> During registration it parses the firmware graph, creates media pads for
> all endpoints, and registers common asynchronous notifiers for sink
> endpoints. These notifiers automatically create media links when the
> corresponding remote source devices become available.
>
> The set_pad_by_ep() callback allows drivers to determine the media pad
> associated with a firmware endpoint and identify whether the endpoint
> represents a sink pad.
>
> By centralizing firmware graph parsing, media pad creation, notifier
> registration, and link creation, this helper reduces duplicated code and
> simplifies error handling in V4L2 sub-device drivers.
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> change in v7
> - don't use saved vep informaiton from media pand
> - fix sashiko report problem
>
> change in v6
> - new patch
> ---
> drivers/media/v4l2-core/v4l2-fwnode.c | 169 ++++++++++++++++++++++++++++++++++
> include/media/v4l2-async.h | 39 ++++++++
> 2 files changed, 208 insertions(+)
>
> diff --git a/drivers/media/v4l2-core/v4l2-fwnode.c b/drivers/media/v4l2-core/v4l2-fwnode.c
> index 62a3a452f7884..4e15adc1af065 100644
> --- a/drivers/media/v4l2-core/v4l2-fwnode.c
> +++ b/drivers/media/v4l2-core/v4l2-fwnode.c
> @@ -26,6 +26,7 @@
>
> #include <media/v4l2-async.h>
> #include <media/v4l2-fwnode.h>
> +#include <media/v4l2-mc.h>
> #include <media/v4l2-subdev.h>
>
> #include "v4l2-subdev-priv.h"
> @@ -1302,6 +1303,174 @@ int __v4l2_async_register_subdev_sensor(struct v4l2_subdev *sd, struct module *m
> }
> EXPORT_SYMBOL_GPL(__v4l2_async_register_subdev_sensor);
>
> +static int v4l2_common_notifier_bound(struct v4l2_async_notifier *notifier,
> + struct v4l2_subdev *sd,
> + struct v4l2_async_connection *asd)
> +{
> + struct media_pad *pad = NULL;
> + struct fwnode_endpoint ep;
> + int ret;
> +
> + if (asd->match.type != V4L2_ASYNC_MATCH_TYPE_FWNODE)
> + return -EINVAL;
> +
> + if (!asd->match.fwnode)
> + return -EINVAL;
> +
> + struct fwnode_handle *remote __free(fwnode_handle) =
> + fwnode_graph_get_remote_endpoint(asd->match.fwnode);
> +
> + ret = fwnode_graph_parse_endpoint(remote, &ep);
> + if (ret)
> + return -EINVAL;
> +
> + for (int i = 0; i < notifier->sd->entity.num_pads; i++) {
> + if (notifier->sd->entity.pads[i].index == ep.port) {
> + pad = ¬ifier->sd->entity.pads[i];
> + break;
> + }
> + }
> +
> + if (!pad) {
> + dev_err(notifier->sd->dev, "failed to find sink pad\n");
> + return -EINVAL;
> + }
> +
> + ret = v4l2_create_fwnode_links_to_pad(sd, pad, MEDIA_LNK_FL_ENABLED);
> + if (ret) {
> + dev_err(sd->dev, "failed to link source pad\n");
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static const struct v4l2_async_notifier_operations v4l2_common_notifier_ops = {
> + .bound = v4l2_common_notifier_bound,
> +};
> +
> +/*
> + * The only one endpoint under one port. And all ports number is continues.
> + */
> +static int
> +v4l2_async_nf_parse_fwnode(struct device *dev, struct media_pad *pads, u32 pads_count,
> + struct v4l2_async_notifier *notifier)
> +{
> + struct v4l2_subdev *sd = notifier->sd;
> + struct v4l2_async_connection *asd;
> + struct v4l2_fwnode_endpoint vep;
> + struct media_pad *pad;
> + int ret;
> +
> + if (!sd->internal_ops || !sd->internal_ops->set_pad_by_ep)
> + return dev_err_probe(dev, -EINVAL,
> + "Missed set_pad_by_ep() callback\n");
> + pad = pads;
> +
> + fwnode_graph_for_each_endpoint_scoped(dev_fwnode(dev), ep) {
> + u32 flags;
> +
> + ret = v4l2_fwnode_endpoint_parse(ep, &vep);
> + if (ret)
> + return dev_err_probe(dev, ret, "failed to parse endpoint\n");
> +
> + if (vep.base.port >= pads_count)
> + return dev_err_probe(dev, -EINVAL,
> + "port number bigger than pad number\n");
> +
> + pad = pads + vep.base.port;
> +
> + ret = sd->internal_ops->set_pad_by_ep(sd, pad, &vep);
> + if (ret < 0)
> + return dev_err_probe(dev, ret, "Can support endpoint\n");
> +
> + flags = pad->flags;
> +
> + if (flags & MEDIA_PAD_FL_SOURCE)
> + continue; /* Bypass source port */
> +
> + notifier->ops = &v4l2_common_notifier_ops;
> +
> + asd = v4l2_async_nf_add_fwnode_remote(notifier, ep,
> + struct v4l2_async_connection);
> + if (IS_ERR(asd))
> + return dev_err_probe(dev, PTR_ERR(asd),
> + "failed to add notifier\n");
> + }
> +
> + return 0;
> +}
> +
> +void media_async_subdev_cleanup(struct v4l2_subdev *sd)
> +{
> + v4l2_async_unregister_subdev(sd);
> + v4l2_subdev_cleanup(sd);
> + media_entity_cleanup(&sd->entity);
> + v4l2_async_nf_unregister(sd->subdev_notifier);
> + v4l2_async_nf_cleanup(sd->subdev_notifier);
> + kfree(sd->entity.pads);
> +}
> +EXPORT_SYMBOL_GPL(media_async_subdev_cleanup);
> +
> +int __media_async_register_subdev(struct v4l2_subdev *sd, struct module *module)
> +{
> + struct device *dev = sd->dev;
> + u32 ep_count;
> + int ret;
> +
> + if (WARN_ON(!sd->dev))
> + return -ENODEV;
> +
> + struct v4l2_async_notifier *notifier __free(kfree) = kzalloc_obj(*notifier);
> + if (!notifier)
> + return -ENOMEM;
> +
> + v4l2_async_subdev_nf_init(notifier, sd);
> +
> + ep_count = fwnode_graph_get_endpoint_count(dev_fwnode(dev),
> + FWNODE_GRAPH_DEVICE_DISABLED);
> + if (!ep_count)
> + return dev_err_probe(dev, -EINVAL, "No connected endpoints\n");
> +
> + struct media_pad *pads __free(kfree) = kzalloc_objs(struct media_pad, ep_count);
> + if (!pads)
> + return -ENOMEM;
> +
> + ret = v4l2_async_nf_parse_fwnode(dev, pads, ep_count, notifier);
> + if (ret < 0)
> + goto out_cleanup;
> +
> + ret = media_entity_pads_init(&sd->entity, ep_count, pads);
> + if (ret)
> + goto out_cleanup;
> +
> + ret = v4l2_async_nf_register(notifier);
> + if (ret < 0)
> + goto out_cleanup;
> +
> + ret = v4l2_subdev_init_finalize(sd);
> + if (ret)
> + goto out_unregister;
> +
> + ret = __v4l2_async_register_subdev(sd, module);
> + if (ret < 0)
> + goto out_unregister;
> +
> + sd->subdev_notifier = no_free_ptr(notifier);
> + retain_and_null_ptr(pads);
> +
> + return 0;
> +
> +out_unregister:
> + v4l2_async_nf_unregister(notifier);
> + v4l2_subdev_cleanup(sd);
> +out_cleanup:
> + v4l2_async_nf_cleanup(notifier);
> +
> + return ret;
> +}
> +EXPORT_SYMBOL_GPL(__media_async_register_subdev);
> +
> MODULE_DESCRIPTION("V4L2 fwnode binding parsing library");
> MODULE_LICENSE("GPL");
> MODULE_AUTHOR("Sakari Ailus <sakari.ailus@linux.intel.com>");
> diff --git a/include/media/v4l2-async.h b/include/media/v4l2-async.h
> index 54a2d9620ed5b..ca41820f776c5 100644
> --- a/include/media/v4l2-async.h
> +++ b/include/media/v4l2-async.h
> @@ -345,4 +345,43 @@ __v4l2_async_register_subdev_sensor(struct v4l2_subdev *sd, struct module *modul
> * @sd: pointer to &struct v4l2_subdev
> */
> void v4l2_async_unregister_subdev(struct v4l2_subdev *sd);
> +
> +enum v4l2_subdev_1to1_pads {
> + V4L2_SUBDEV_1TO1_PADS_SINK,
> + V4L2_SUBDEV_1TO1_PADS_SOURCE,
> + V4L2_SUBDEV_1TO1_PADS_TOTAL,
> +};
> +
> +/**
> + * media_async_register_subdev - registers a sub-device to the asynchronous
> + * sub-device framework and parse set up common
> + * related devices
> + *
> + * @sd: pointer to struct &v4l2_subdev
> + *
> + * Register a V4L2 sub-device with the asynchronous sub-device framework.
> + * In addition to v4l2_async_register_subdev(), this function parses the
> + * firmware graph, creates media pads for the endpoints, and registers common
> + * notifiers to create media links between connected devices.
> + *
> + * This function also init media_pads.
> + *
> + * The sub-device is unregistered and cleanup by media_async_subdev_cleanup()
> + *
> + * While registered, the subdev module is marked as in-use.
> + *
> + * An error is returned if the module is no longer loaded on any attempts
> + * to register it.
> + */
> +#define media_async_register_subdev(sd_1to1) \
> + __media_async_register_subdev(sd_1to1, THIS_MODULE)
> +
> +int __media_async_register_subdev(struct v4l2_subdev *sd_1to1, struct module *module);
> +
> +/**
> + * media_async_subdev_cleanup - unregistered and cleanup subdev and media pads
> + * @sd_1to1: pointer to struct &v4l2_subdev_1to1
> + */
> +void media_async_subdev_cleanup(struct v4l2_subdev *sd_1to1);
> +
> #endif
--
Regards,
Laurent Pinchart
^ permalink raw reply
* [PATCH v8 05/39] drm/display: scdc-helper: Add macro for connector-prefixed debug messages
From: Cristian Ciocaltea @ 2026-07-02 14:46 UTC (permalink / raw)
To: Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Andrzej Hajda, Neil Armstrong, Robert Foss,
Laurent Pinchart, Jonas Karlman, Jernej Skrabec, Luca Ceresoli,
Sandy Huang, Heiko Stübner, Andy Yan, Daniel Stone,
Dave Stevenson, Maíra Canal, Raspberry Pi Kernel Maintenance
Cc: kernel, dri-devel, linux-kernel, linux-arm-kernel, linux-rockchip
In-Reply-To: <20260702-dw-hdmi-qp-scramb-v8-0-d79890d00b6a@collabora.com>
Introduce the drm_scdc_dbg() wrapper over drm_dbg_kms() to help getting
rid of the boilerplate around prefixing the debug messages with the
connector information.
Acked-by: Maxime Ripard <mripard@kernel.org>
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
drivers/gpu/drm/display/drm_scdc_helper.c | 24 +++++++++---------------
1 file changed, 9 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_scdc_helper.c b/drivers/gpu/drm/display/drm_scdc_helper.c
index df878aad4a36..cb6632346aad 100644
--- a/drivers/gpu/drm/display/drm_scdc_helper.c
+++ b/drivers/gpu/drm/display/drm_scdc_helper.c
@@ -55,6 +55,10 @@
#define SCDC_I2C_SLAVE_ADDRESS 0x54
+#define drm_scdc_dbg(connector, fmt, ...) \
+ drm_dbg_kms((connector)->dev, "[CONNECTOR:%d:%s] " fmt, \
+ (connector)->base.id, (connector)->name, ##__VA_ARGS__)
+
/**
* drm_scdc_read - read a block of data from SCDC
* @adapter: I2C controller
@@ -158,9 +162,7 @@ bool drm_scdc_get_scrambling_status(struct drm_connector *connector)
ret = drm_scdc_readb(connector->ddc, SCDC_SCRAMBLER_STATUS, &status);
if (ret < 0) {
- drm_dbg_kms(connector->dev,
- "[CONNECTOR:%d:%s] Failed to read scrambling status: %d\n",
- connector->base.id, connector->name, ret);
+ drm_scdc_dbg(connector, "Failed to read scrambling status: %d\n", ret);
return false;
}
@@ -188,9 +190,7 @@ bool drm_scdc_set_scrambling(struct drm_connector *connector,
ret = drm_scdc_readb(connector->ddc, SCDC_TMDS_CONFIG, &config);
if (ret < 0) {
- drm_dbg_kms(connector->dev,
- "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n",
- connector->base.id, connector->name, ret);
+ drm_scdc_dbg(connector, "Failed to read TMDS config: %d\n", ret);
return false;
}
@@ -201,9 +201,7 @@ bool drm_scdc_set_scrambling(struct drm_connector *connector,
ret = drm_scdc_writeb(connector->ddc, SCDC_TMDS_CONFIG, config);
if (ret < 0) {
- drm_dbg_kms(connector->dev,
- "[CONNECTOR:%d:%s] Failed to enable scrambling: %d\n",
- connector->base.id, connector->name, ret);
+ drm_scdc_dbg(connector, "Failed to enable scrambling: %d\n", ret);
return false;
}
@@ -248,9 +246,7 @@ bool drm_scdc_set_high_tmds_clock_ratio(struct drm_connector *connector,
ret = drm_scdc_readb(connector->ddc, SCDC_TMDS_CONFIG, &config);
if (ret < 0) {
- drm_dbg_kms(connector->dev,
- "[CONNECTOR:%d:%s] Failed to read TMDS config: %d\n",
- connector->base.id, connector->name, ret);
+ drm_scdc_dbg(connector, "Failed to read TMDS config: %d\n", ret);
return false;
}
@@ -261,9 +257,7 @@ bool drm_scdc_set_high_tmds_clock_ratio(struct drm_connector *connector,
ret = drm_scdc_writeb(connector->ddc, SCDC_TMDS_CONFIG, config);
if (ret < 0) {
- drm_dbg_kms(connector->dev,
- "[CONNECTOR:%d:%s] Failed to set TMDS clock ratio: %d\n",
- connector->base.id, connector->name, ret);
+ drm_scdc_dbg(connector, "Failed to set TMDS clock ratio: %d\n", ret);
return false;
}
--
2.54.0
^ permalink raw reply related
* Re: [PATCH v2 03/19] ARM: rework ARM11 CPU selection logic
From: Aaro Koskinen @ 2026-07-02 16:14 UTC (permalink / raw)
To: Arnd Bergmann
Cc: linux-arm-kernel, soc, linux-kernel, Arnd Bergmann,
Alexander Sverdlin, Alexandre Belloni, Alexandre Torgue,
Andrew Lunn, Ard Biesheuvel, Claudiu Beznea, Daniel Mack,
Ethan Nelson-Moore, Frank Li, Gregory Clement, Haojian Zhuang,
Jeremy J. Peper, Kristoffer Ericson, Krzysztof Kozlowski,
Linus Walleij, Mark Brown, Marc Zyngier, Mike Rapoport,
Nicolas Ferre, Patrice Chotard, Ralph Siemsen, Robert Jarzmik,
Russell King, Sascha Hauer, Sebastian Hesselbarth, Stefan Agner,
Stefan Wiehler, Tony Lindgren, Vladimir Zapolskiy, Will Deacon,
Linus Walleij
In-Reply-To: <20260701212353.2196041-4-arnd@kernel.org>
On Wed, Jul 01, 2026 at 11:23:37PM +0200, Arnd Bergmann wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> Support for SMP on ARM1136r0 has been broken for a while, and nobody
> is working on fixing it. I had a plan to change ARMv6 support to no
> longer coexist in a common kernel with ARMv7 CPUs but instead ARMv5 and
> below. This would have addressed the problem, but after a recent mailing
> list discussion, we concluded that an easier approach is to just forbid
> ARM1136r0 CPU support on SMP-enabled kernels.
>
> This mainly affects users of the Nokia N800/N810 tablets using an
> OMAP2420 SoC, which is the only commercial product with an ARM1136r0
> that is still supported by the kernel.
>
> The other machines that are still in the same hardware catogory are:
>
> - TI OMAP2420 H4 reference board
> - TI OMAP2430 SDP software development platform
> - Freescale/NXP i.MX31 Lite Development Kit
> - Buglabs i.MX31 Bug 1.x prototype
> - Arm Integrator/AP with CM1136JF-S core module
>
> To my knowledge, none of these have any actual users aside from
> reference boards being used more easily test the platforms.
>
> There are also a few ARM1136r1 machines, which implement the
> ARMv6K SMP support (barriers, atomics and TLS):
>
> - Eukrea CPUIMX35 reference platform
> - Freescale/NXP i.MX35 Product Development Kit
> - ARM Integrator/CP/IM-LT3 with ARM1136J Core Tile
> - ARM Realview/EB with ARM1136J Core Tile
>
> Again, these are mainly reference implementations rather than
> actual products, but since they support ARMv6K, they should
> continue to work correctly in SMP-enabled kernels. For the
> ARM Core Tile, I have not found a datasheet but instead use
> the revision based on what the respective virtual models
> report.
>
> All the other ARMv6 platforms use an ARM1176 with ARMv6K,
> VMSAv7 and Trustzone support.
>
> To avoid the broken configuration, annotate the ARM1136 based
> machines with specific CPU_ARM1136R0 or CPU_ARM1136R2 symbols
> in Kconfig and make the r0 variants depend on !SMP.
>
> Link: https://lore.kernel.org/linux-arm-kernel/2831c5a6-cfbf-4fe0-b51c-0396e5b0aeb7@app.fastmail.com/T/
> Acked-by: Linus Walleij <linus.walleij@linaro.org>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Aaro Koskinen <aaro.koskinen@iki.fi> # OMAP
> ---
> arch/arm/Kconfig.platforms | 2 +-
> arch/arm/mach-imx/Kconfig | 4 +++-
> arch/arm/mach-omap2/Kconfig | 3 ++-
> arch/arm/mach-versatile/Kconfig | 10 +++++-----
> arch/arm/mm/Kconfig | 24 +++++++++++++++++++++++-
> 5 files changed, 34 insertions(+), 9 deletions(-)
>
> diff --git a/arch/arm/Kconfig.platforms b/arch/arm/Kconfig.platforms
> index 386eccc81868..2e118b65f93b 100644
> --- a/arch/arm/Kconfig.platforms
> +++ b/arch/arm/Kconfig.platforms
> @@ -33,7 +33,7 @@ config ARCH_MULTI_V4_V5
> config ARCH_MULTI_V6
> bool "ARMv6 based platforms (ARM11)"
> select ARCH_MULTI_V6_V7
> - select CPU_V6K
> + select CPU_ARM1176
>
> config ARCH_MULTI_V7
> bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
> diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
> index a361840d7a04..041e73ad203a 100644
> --- a/arch/arm/mach-imx/Kconfig
> +++ b/arch/arm/mach-imx/Kconfig
> @@ -41,13 +41,15 @@ comment "ARM1136 platforms"
>
> config SOC_IMX31
> bool "i.MX31 support"
> - select CPU_V6
> + depends on !SMP
> + select CPU_ARM1136R0
> select MXC_AVIC
> help
> This enables support for Freescale i.MX31 processor
>
> config SOC_IMX35
> bool "i.MX35 support"
> + select CPU_ARM1136R1
> select MXC_AVIC
> help
> This enables support for Freescale i.MX35 processor
> diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
> index f3f19bcfca2c..13987ffbba00 100644
> --- a/arch/arm/mach-omap2/Kconfig
> +++ b/arch/arm/mach-omap2/Kconfig
> @@ -8,8 +8,9 @@ config OMAP_HWMOD
> config ARCH_OMAP2
> bool "TI OMAP2"
> depends on ARCH_MULTI_V6
> + depends on !SMP
> select ARCH_OMAP2PLUS
> - select CPU_V6
> + select CPU_ARM1136R0
> select OMAP_HWMOD
> select SOC_HAS_OMAP2_SDRC
>
> diff --git a/arch/arm/mach-versatile/Kconfig b/arch/arm/mach-versatile/Kconfig
> index 513618078440..de42da7de8c8 100644
> --- a/arch/arm/mach-versatile/Kconfig
> +++ b/arch/arm/mach-versatile/Kconfig
> @@ -113,7 +113,8 @@ config INTEGRATOR_CM1136JFS
> bool "Integrator/CM1136JF-S core module"
> depends on ARCH_INTEGRATOR_AP
> depends on ARCH_MULTI_V6
> - select CPU_V6
> + depends on !SMP
> + select CPU_ARM1136R0
>
> config ARCH_INTEGRATOR_CP
> bool "Support Integrator/CP platform"
> @@ -135,7 +136,7 @@ config INTEGRATOR_CTB36
> bool "Integrator/CTB36 (ARM1136JF-S) core tile"
> depends on ARCH_INTEGRATOR_CP
> depends on ARCH_MULTI_V6
> - select CPU_V6
> + select CPU_ARM1136R1
>
> config ARCH_CINTEGRATOR
> depends on ARCH_INTEGRATOR_CP
> @@ -182,7 +183,7 @@ config MACH_REALVIEW_EB
> config REALVIEW_EB_ARM1136
> bool "Support ARM1136J(F)-S Tile"
> depends on MACH_REALVIEW_EB && ARCH_MULTI_V6
> - select CPU_V6
> + select CPU_ARM1136R1
> help
> Enable support for the ARM1136 tile fitted to the
> Realview(R) Emulation Baseboard platform.
> @@ -201,11 +202,10 @@ config REALVIEW_EB_A9MP
> Enable support for the Cortex-A9MPCore tile fitted to the
> Realview(R) Emulation Baseboard platform.
>
> -# ARMv6 CPU without K extensions, but does have the new exclusive ops
> config MACH_REALVIEW_PB1176
> bool "Support RealView(R) Platform Baseboard for ARM1176JZF-S"
> depends on ARCH_MULTI_V6
> - select CPU_V6
> + select CPU_ARM1176
> select HAVE_TCM
> help
> Include support for the ARM(R) RealView(R) Platform Baseboard for
> diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
> index 871bd58d2ccc..f3d71e89a31f 100644
> --- a/arch/arm/mm/Kconfig
> +++ b/arch/arm/mm/Kconfig
> @@ -376,6 +376,7 @@ config CPU_PJ4B
> # ARMv6
> config CPU_V6
> bool
> + depends on !SMP
> select CPU_32v6
> select CPU_ABRT_EV6
> select CPU_CACHE_V6
> @@ -386,7 +387,6 @@ config CPU_V6
> select CPU_PABRT_V6
> select CPU_THUMB_CAPABLE
> select CPU_TLB_V6 if MMU
> - select SMP_ON_UP if SMP
>
> # ARMv6k
> config CPU_V6K
> @@ -403,6 +403,28 @@ config CPU_V6K
> select CPU_THUMB_CAPABLE
> select CPU_TLB_V6 if MMU
>
> +config CPU_ARM1136R0
> + bool
> + select CPU_V6
> + depends on !SMP
> + help
> + These early revisions of ARM1136 lack support for the
> + ARMv6k extensions for multiprocessing.
> +
> +config CPU_ARM1136R1
> + bool
> + select CPU_V6K
> + help
> + Later revisions of ARM1136 add ARMv6k (atomics, barriers
> + and TLS register) in addition to the features from r0.
> +
> +config CPU_ARM1176
> + bool
> + select CPU_V6K
> + help
> + ARM1176 implements ARMv6k, VMSAv7 and Trustzone in
> + addition to the ARMv6 baseline.
> +
> # ARMv7 and ARMv8 architectures
> config CPU_V7
> bool
> --
> 2.39.5
>
^ permalink raw reply
* [PATCH v8 08/39] drm/display: hdmi: Advertise SCDC source version when scrambling
From: Cristian Ciocaltea @ 2026-07-02 14:46 UTC (permalink / raw)
To: Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Andrzej Hajda, Neil Armstrong, Robert Foss,
Laurent Pinchart, Jonas Karlman, Jernej Skrabec, Luca Ceresoli,
Sandy Huang, Heiko Stübner, Andy Yan, Daniel Stone,
Dave Stevenson, Maíra Canal, Raspberry Pi Kernel Maintenance
Cc: kernel, dri-devel, linux-kernel, linux-arm-kernel, linux-rockchip
In-Reply-To: <20260702-dw-hdmi-qp-scramb-v8-0-d79890d00b6a@collabora.com>
The HDMI 2.0 spec advises that compliant Source devices report their
SCDC version in the Source Version register. Do so when enabling
scrambling by calling drm_scdc_set_source_version().
Failures are non-fatal: SCDC version negotiation is purely informational
and does not gate scrambling or any high-bitrate functionality, so a
flaky DDC bus should not block scrambling setup.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
drivers/gpu/drm/display/drm_hdmi_helper.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_hdmi_helper.c b/drivers/gpu/drm/display/drm_hdmi_helper.c
index 7c96cccf683d..b8ed2a1e47f5 100644
--- a/drivers/gpu/drm/display/drm_hdmi_helper.c
+++ b/drivers/gpu/drm/display/drm_hdmi_helper.c
@@ -16,6 +16,7 @@
#include <drm/drm_print.h>
#include <drm/drm_property.h>
+#define DRM_HDMI_SCDC_SOURCE_VERSION 1
#define DRM_HDMI_SCDC_POLL_DELAY_MS 1000
static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf)
@@ -531,6 +532,12 @@ int drm_connector_hdmi_enable_scrambling(struct drm_connector *connector,
return -EINVAL;
}
+ /*
+ * Advertise our SCDC source version. This is purely informational and
+ * does not gate scrambling, so failures are non-fatal.
+ */
+ drm_scdc_set_source_version(connector, DRM_HDMI_SCDC_SOURCE_VERSION);
+
drm_dbg_kms(dev, "Enabling scrambling\n");
hdmi->scdc_cb = drm_scdc_monitor_scrambler;
--
2.54.0
^ permalink raw reply related
* [PATCH v8 22/39] drm/rockchip: dw_hdmi_qp: Use local dev variable consistently in bind()
From: Cristian Ciocaltea @ 2026-07-02 14:46 UTC (permalink / raw)
To: Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann, David Airlie,
Simona Vetter, Andrzej Hajda, Neil Armstrong, Robert Foss,
Laurent Pinchart, Jonas Karlman, Jernej Skrabec, Luca Ceresoli,
Sandy Huang, Heiko Stübner, Andy Yan, Daniel Stone,
Dave Stevenson, Maíra Canal, Raspberry Pi Kernel Maintenance
Cc: kernel, dri-devel, linux-kernel, linux-arm-kernel, linux-rockchip
In-Reply-To: <20260702-dw-hdmi-qp-scramb-v8-0-d79890d00b6a@collabora.com>
Replace indirect struct device accesses via hdmi->dev and pdev->dev with
the local dev parameter already available in dw_hdmi_qp_rockchip_bind(),
for consistency and readability.
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
---
drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c | 33 +++++++++++++-------------
1 file changed, 16 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c
index 7bd0f6dcbe5d..d2fcfa70ed16 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c
@@ -564,7 +564,7 @@ static int dw_hdmi_qp_rockchip_bind(struct device *dev, struct device *master,
struct clk *ref_clk;
int ret, irq, i;
- if (!pdev->dev.of_node)
+ if (!dev->of_node)
return -ENODEV;
hdmi = drmm_kzalloc(drm, sizeof(*hdmi), GFP_KERNEL);
@@ -584,7 +584,7 @@ static int dw_hdmi_qp_rockchip_bind(struct device *dev, struct device *master,
return dev_err_probe(dev, -ENODEV, "Missing platform ctrl ops\n");
hdmi->ctrl_ops = cfg->ctrl_ops;
- hdmi->dev = &pdev->dev;
+ hdmi->dev = dev;
hdmi->port_id = -ENODEV;
/* Identify port ID by matching base IO address */
@@ -595,7 +595,7 @@ static int dw_hdmi_qp_rockchip_bind(struct device *dev, struct device *master,
}
}
if (hdmi->port_id < 0)
- return dev_err_probe(hdmi->dev, hdmi->port_id,
+ return dev_err_probe(dev, hdmi->port_id,
"Failed to match HDMI port ID\n");
plat_data.phy_ops = cfg->phy_ops;
@@ -623,37 +623,36 @@ static int dw_hdmi_qp_rockchip_bind(struct device *dev, struct device *master,
hdmi->regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
"rockchip,grf");
if (IS_ERR(hdmi->regmap))
- return dev_err_probe(hdmi->dev, PTR_ERR(hdmi->regmap),
+ return dev_err_probe(dev, PTR_ERR(hdmi->regmap),
"Unable to get rockchip,grf\n");
hdmi->vo_regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
"rockchip,vo-grf");
if (IS_ERR(hdmi->vo_regmap))
- return dev_err_probe(hdmi->dev, PTR_ERR(hdmi->vo_regmap),
+ return dev_err_probe(dev, PTR_ERR(hdmi->vo_regmap),
"Unable to get rockchip,vo-grf\n");
- ret = devm_clk_bulk_get_all_enabled(hdmi->dev, &clks);
+ ret = devm_clk_bulk_get_all_enabled(dev, &clks);
if (ret < 0)
- return dev_err_probe(hdmi->dev, ret, "Failed to get clocks\n");
+ return dev_err_probe(dev, ret, "Failed to get clocks\n");
- ref_clk = clk_get(hdmi->dev, "ref");
+ ref_clk = clk_get(dev, "ref");
if (IS_ERR(ref_clk))
- return dev_err_probe(hdmi->dev, PTR_ERR(ref_clk),
+ return dev_err_probe(dev, PTR_ERR(ref_clk),
"Failed to get ref clock\n");
plat_data.ref_clk_rate = clk_get_rate(ref_clk);
clk_put(ref_clk);
- hdmi->frl_enable_gpio = devm_gpiod_get_optional(hdmi->dev, "frl-enable",
+ hdmi->frl_enable_gpio = devm_gpiod_get_optional(dev, "frl-enable",
GPIOD_OUT_LOW);
if (IS_ERR(hdmi->frl_enable_gpio))
- return dev_err_probe(hdmi->dev, PTR_ERR(hdmi->frl_enable_gpio),
+ return dev_err_probe(dev, PTR_ERR(hdmi->frl_enable_gpio),
"Failed to request FRL enable GPIO\n");
hdmi->phy = devm_of_phy_get_by_index(dev, dev->of_node, 0);
if (IS_ERR(hdmi->phy))
- return dev_err_probe(hdmi->dev, PTR_ERR(hdmi->phy),
- "Failed to get phy\n");
+ return dev_err_probe(dev, PTR_ERR(hdmi->phy), "Failed to get phy\n");
cfg->ctrl_ops->io_init(hdmi);
@@ -671,7 +670,7 @@ static int dw_hdmi_qp_rockchip_bind(struct device *dev, struct device *master,
if (irq < 0)
return irq;
- ret = devm_request_threaded_irq(hdmi->dev, irq,
+ ret = devm_request_threaded_irq(dev, irq,
cfg->ctrl_ops->hardirq_callback,
cfg->ctrl_ops->irq_callback,
IRQF_SHARED, "dw-hdmi-qp-hpd",
@@ -682,18 +681,18 @@ static int dw_hdmi_qp_rockchip_bind(struct device *dev, struct device *master,
drm_encoder_helper_add(encoder, &dw_hdmi_qp_rockchip_encoder_helper_funcs);
ret = drmm_encoder_init(drm, encoder, NULL, DRM_MODE_ENCODER_TMDS, NULL);
if (ret)
- return dev_err_probe(hdmi->dev, ret, "Failed to init encoder\n");
+ return dev_err_probe(dev, ret, "Failed to init encoder\n");
platform_set_drvdata(pdev, hdmi);
hdmi->hdmi = dw_hdmi_qp_bind(pdev, encoder, &plat_data);
if (IS_ERR(hdmi->hdmi))
- return dev_err_probe(hdmi->dev, PTR_ERR(hdmi->hdmi),
+ return dev_err_probe(dev, PTR_ERR(hdmi->hdmi),
"Failed to bind dw-hdmi-qp\n");
connector = drm_bridge_connector_init(drm, encoder);
if (IS_ERR(connector))
- return dev_err_probe(hdmi->dev, PTR_ERR(connector),
+ return dev_err_probe(dev, PTR_ERR(connector),
"Failed to init bridge connector\n");
return 0;
--
2.54.0
^ permalink raw reply related
* [PATCH 10/28] KVM: arm64: Relax CNTHCTL_EL2 handling when FEAT_NV2p1 is present
From: Marc Zyngier @ 2026-07-02 16:02 UTC (permalink / raw)
To: kvmarm, linux-arm-kernel, kvm
Cc: Steffen Eiden, Joey Gouly, Suzuki K Poulose, Oliver Upton,
Zenghui Yu
In-Reply-To: <20260702160248.1377250-1-maz@kernel.org>
With NV2p1, it is no longer necessary to use the split approach
where bits of CNTHCTL_EL2 cannot be accessed via CNTKCTL_EL1,
and we can treat the CNTKCTL_EL1 accessor as if it was "normal".
Key the special casing on FEAT_NV2P1 not being implemented.
Signed-off-by: Marc Zyngier <maz@kernel.org>
---
arch/arm64/kvm/arch_timer.c | 10 ++++++++--
arch/arm64/kvm/hyp/vhe/sysreg-sr.c | 13 ++++++++++---
arch/arm64/kvm/sys_regs.c | 6 ++++--
3 files changed, 22 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/kvm/arch_timer.c b/arch/arm64/kvm/arch_timer.c
index 4155fe89b58a1..db60facad9f3c 100644
--- a/arch/arm64/kvm/arch_timer.c
+++ b/arch/arm64/kvm/arch_timer.c
@@ -876,8 +876,14 @@ static void timer_set_traps(struct kvm_vcpu *vcpu, struct timer_map *map)
assign_clear_set_bit(tvt02, CNTHCTL_EL1NVVCT, clr, set);
assign_clear_set_bit(tpt02, CNTHCTL_EL1NVPCT, clr, set);
- /* This only happens on VHE, so use the CNTHCTL_EL2 accessor. */
- sysreg_clear_set(cnthctl_el2, clr, set);
+ /*
+ * This only happens on VHE, so use the CNTHCTL_EL2 accessor, unless
+ * we are sure CNTKCTL_EL1 is completely stateful with FEAT_NV2p1.
+ */
+ if (!cpus_have_final_cap(ARM64_HAS_NV2P1))
+ sysreg_clear_set(cnthctl_el2, clr, set);
+ else
+ sysreg_clear_set(cntkctl_el1, clr, set);
}
void kvm_timer_vcpu_load(struct kvm_vcpu *vcpu)
diff --git a/arch/arm64/kvm/hyp/vhe/sysreg-sr.c b/arch/arm64/kvm/hyp/vhe/sysreg-sr.c
index 6f0f046e4ca4e..0c4ef1ce32ae7 100644
--- a/arch/arm64/kvm/hyp/vhe/sysreg-sr.c
+++ b/arch/arm64/kvm/hyp/vhe/sysreg-sr.c
@@ -69,11 +69,18 @@ static void __sysreg_save_vel2_state(struct kvm_vcpu *vcpu)
* The EL1 view of CNTKCTL_EL1 has a bunch of RES0 bits where
* the interesting CNTHCTL_EL2 bits live. So preserve these
* bits when reading back the guest-visible value.
+ *
+ * While NV2p1 fixes some of that, it makes CNTHCTL_EL2.ECV
+ * even more broken than it already was with NV2.
*/
val = read_sysreg_el1(SYS_CNTKCTL);
- val &= CNTKCTL_VALID_BITS;
- __vcpu_rmw_sys_reg(vcpu, CNTHCTL_EL2, &=, ~CNTKCTL_VALID_BITS);
- __vcpu_rmw_sys_reg(vcpu, CNTHCTL_EL2, |=, val);
+ if (!cpus_have_final_cap(ARM64_HAS_NV2P1)) {
+ val &= CNTKCTL_VALID_BITS;
+ __vcpu_rmw_sys_reg(vcpu, CNTHCTL_EL2, &=, ~CNTKCTL_VALID_BITS);
+ __vcpu_rmw_sys_reg(vcpu, CNTHCTL_EL2, |=, val);
+ } else {
+ __vcpu_assign_sys_reg(vcpu, CNTHCTL_EL2, val);
+ }
}
__vcpu_assign_sys_reg(vcpu, SP_EL2, read_sysreg(sp_el1));
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 1dfc1f88bec82..9439c5b2b1fe8 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -322,8 +322,10 @@ u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, enum vcpu_sysreg reg)
switch (reg) {
case CNTHCTL_EL2:
val = read_sysreg_el1(SYS_CNTKCTL);
- val &= CNTKCTL_VALID_BITS;
- val |= __vcpu_sys_reg(vcpu, reg) & ~CNTKCTL_VALID_BITS;
+ if (!cpus_have_final_cap(ARM64_HAS_NV2P1)) {
+ val &= CNTKCTL_VALID_BITS;
+ val |= __vcpu_sys_reg(vcpu, reg) & ~CNTKCTL_VALID_BITS;
+ }
return val;
case CPTR_EL2:
if (cpus_have_final_cap(ARM64_HAS_NV2P1))
--
2.47.3
^ permalink raw reply related
* Re: [PATCH v2 01/19] ARM: use CONFIG_AEABI by default everywhere
From: Aaro Koskinen @ 2026-07-02 16:10 UTC (permalink / raw)
To: Arnd Bergmann
Cc: linux-arm-kernel, soc, linux-kernel, Arnd Bergmann,
Alexander Sverdlin, Alexandre Belloni, Alexandre Torgue,
Andrew Lunn, Ard Biesheuvel, Claudiu Beznea, Daniel Mack,
Ethan Nelson-Moore, Frank Li, Gregory Clement, Haojian Zhuang,
Jeremy J. Peper, Kristoffer Ericson, Krzysztof Kozlowski,
Linus Walleij, Mark Brown, Marc Zyngier, Mike Rapoport,
Nicolas Ferre, Patrice Chotard, Ralph Siemsen, Robert Jarzmik,
Russell King, Sascha Hauer, Sebastian Hesselbarth, Stefan Agner,
Stefan Wiehler, Tony Lindgren, Vladimir Zapolskiy, Will Deacon,
Linus Walleij
In-Reply-To: <20260701212353.2196041-2-arnd@kernel.org>
Hi,
On Wed, Jul 01, 2026 at 11:23:35PM +0200, Arnd Bergmann wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> On ARMv4 and ARMv5, the default is still to build for OABI, with
> CONFIG_AEABI disabled, even though distros and toolchains no longer
> support OABI as a target.
>
> Change the default to EABI for all architecture levels and change
> the defconfig entries as follows:
>
> - All machines that used to explicitly enable EABI can drop that line now
> - Machines that are likely to actually use old distros and had NWFPE
> enabled in combination with OABI (rpc, footrbridge, netwinder,
> assabet, neponset) explicitly turn it on now.
> - Machines that already had both EABI and NWFPE disabled in defconfig
> (at91_dt, collie, ep93xx, gemini, h3600, imx_v4_v5, integrator, jornada,
> moxart, multi_v4t, omap1) were likely not usable with either OABI or
> EABI and now use EABI instead implicitly, making it more likely that
> they could work.
>
> Acked-by: Linus Walleij <linus.walleij@linaro.org>
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Aaro Koskinen <aaro.koskinen@iki.fi> # OMAP
> ---
> arch/arm/Kconfig | 15 ++++++---------
> arch/arm/configs/am200epdkit_defconfig | 1 -
> arch/arm/configs/aspeed_g4_defconfig | 1 -
> arch/arm/configs/assabet_defconfig | 1 +
> arch/arm/configs/at91_dt_defconfig | 1 -
> arch/arm/configs/axm55xx_defconfig | 1 -
> arch/arm/configs/bcm2835_defconfig | 1 -
> arch/arm/configs/clps711x_defconfig | 1 -
> arch/arm/configs/collie_defconfig | 1 -
> arch/arm/configs/davinci_all_defconfig | 1 -
> arch/arm/configs/dove_defconfig | 1 -
> arch/arm/configs/ep93xx_defconfig | 1 -
> arch/arm/configs/footbridge_defconfig | 1 +
> arch/arm/configs/gemini_defconfig | 1 -
> arch/arm/configs/h3600_defconfig | 1 -
> arch/arm/configs/hisi_defconfig | 1 -
> arch/arm/configs/imx_v4_v5_defconfig | 1 -
> arch/arm/configs/integrator_defconfig | 1 -
> arch/arm/configs/ixp4xx_defconfig | 1 -
> arch/arm/configs/jornada720_defconfig | 1 -
> arch/arm/configs/keystone_defconfig | 1 -
> arch/arm/configs/lpc32xx_defconfig | 1 -
> arch/arm/configs/mmp2_defconfig | 1 -
> arch/arm/configs/moxart_defconfig | 1 -
> arch/arm/configs/multi_v4t_defconfig | 1 -
> arch/arm/configs/multi_v5_defconfig | 1 -
> arch/arm/configs/mv78xx0_defconfig | 2 --
> arch/arm/configs/mvebu_v5_defconfig | 1 -
> arch/arm/configs/mxs_defconfig | 1 -
> arch/arm/configs/neponset_defconfig | 1 +
> arch/arm/configs/netwinder_defconfig | 1 +
> arch/arm/configs/nhk8815_defconfig | 1 -
> arch/arm/configs/omap1_defconfig | 2 --
> arch/arm/configs/orion5x_defconfig | 2 --
> arch/arm/configs/pxa168_defconfig | 2 --
> arch/arm/configs/pxa3xx_defconfig | 2 --
> arch/arm/configs/pxa910_defconfig | 2 --
> arch/arm/configs/pxa_defconfig | 1 -
> arch/arm/configs/rpc_defconfig | 1 +
> arch/arm/configs/spear13xx_defconfig | 1 -
> arch/arm/configs/spitz_defconfig | 1 -
> arch/arm/configs/versatile_defconfig | 1 -
> arch/arm/configs/vt8500_v6_v7_defconfig | 1 -
> arch/arm/configs/wpcm450_defconfig | 1 -
> 44 files changed, 11 insertions(+), 53 deletions(-)
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 9187240a02db..ccc0114d30de 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -1153,17 +1153,14 @@ config ARM_PATCH_IDIV
> config AEABI
> bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \
> !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG
> - default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG
> + default y
> help
> - This option allows for the kernel to be compiled using the latest
> - ARM ABI (aka EABI). This is only useful if you are using a user
> - space environment that is also compiled with EABI.
> + The Arm EABI is the default ABI on all modern Linux
> + distributions, replacing the obsolete and "OABI" that was
> + commonly used on ARMv4 distributions before ca. 2013.
>
> - Since there are major incompatibilities between the legacy ABI and
> - EABI, especially with regard to structure member alignment, this
> - option also changes the kernel syscall calling convention to
> - disambiguate both ABIs and allow for backward compatibility support
> - (selected with CONFIG_OABI_COMPAT).
> + Everyone should enable this, as support for OABI user space
> + was dropped in gcc-4.8 and most distributions after ca. 2013.
>
> config OABI_COMPAT
> bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
> diff --git a/arch/arm/configs/am200epdkit_defconfig b/arch/arm/configs/am200epdkit_defconfig
> index d8198592fe1b..b3f81237c6e1 100644
> --- a/arch/arm/configs/am200epdkit_defconfig
> +++ b/arch/arm/configs/am200epdkit_defconfig
> @@ -7,7 +7,6 @@ CONFIG_EXPERT=y
> # CONFIG_ARCH_MULTI_V7 is not set
> CONFIG_ARCH_PXA=y
> CONFIG_ARCH_GUMSTIX=y
> -CONFIG_AEABI=y
> # CONFIG_OABI_COMPAT is not set
> CONFIG_CMDLINE="console=ttyS0,115200n8 root=1f01 rootfstype=jffs2"
> CONFIG_MODULES=y
> diff --git a/arch/arm/configs/aspeed_g4_defconfig b/arch/arm/configs/aspeed_g4_defconfig
> index 45d8738abb75..3dcb80157f77 100644
> --- a/arch/arm/configs/aspeed_g4_defconfig
> +++ b/arch/arm/configs/aspeed_g4_defconfig
> @@ -22,7 +22,6 @@ CONFIG_KEXEC=y
> CONFIG_ARCH_ASPEED=y
> CONFIG_MACH_ASPEED_G4=y
> CONFIG_VMSPLIT_2G=y
> -CONFIG_AEABI=y
> CONFIG_UACCESS_WITH_MEMCPY=y
> # CONFIG_ATAGS is not set
> CONFIG_JUMP_LABEL=y
> diff --git a/arch/arm/configs/assabet_defconfig b/arch/arm/configs/assabet_defconfig
> index 07ab9eaac4af..df63889b0c4c 100644
> --- a/arch/arm/configs/assabet_defconfig
> +++ b/arch/arm/configs/assabet_defconfig
> @@ -5,6 +5,7 @@ CONFIG_ARCH_MULTI_V4=y
> # CONFIG_ARCH_MULTI_V7 is not set
> CONFIG_ARCH_SA1100=y
> CONFIG_SA1100_ASSABET=y
> +# CONFIG_AEABI is not set
> CONFIG_CMDLINE="mem=32M console=ttySA0,38400n8 initrd=0xc0800000,3M root=/dev/ram"
> CONFIG_FPE_NWFPE=y
> CONFIG_PM=y
> diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig
> index e331242dece7..320eb27a6a2e 100644
> --- a/arch/arm/configs/at91_dt_defconfig
> +++ b/arch/arm/configs/at91_dt_defconfig
> @@ -18,7 +18,6 @@ CONFIG_SOC_AT91SAM9=y
> CONFIG_SOC_SAM9X60=y
> CONFIG_SOC_SAM9X7=y
> # CONFIG_ATMEL_CLOCKSOURCE_PIT is not set
> -CONFIG_AEABI=y
> CONFIG_UACCESS_WITH_MEMCPY=y
> # CONFIG_ATAGS is not set
> CONFIG_ARM_APPENDED_DTB=y
> diff --git a/arch/arm/configs/axm55xx_defconfig b/arch/arm/configs/axm55xx_defconfig
> index 0952e5e94c5e..12c59a4ee504 100644
> --- a/arch/arm/configs/axm55xx_defconfig
> +++ b/arch/arm/configs/axm55xx_defconfig
> @@ -38,7 +38,6 @@ CONFIG_PCIE_AXXIA=y
> CONFIG_SMP=y
> CONFIG_NR_CPUS=16
> CONFIG_HOTPLUG_CPU=y
> -CONFIG_AEABI=y
> CONFIG_OABI_COMPAT=y
> CONFIG_HIGHMEM=y
> CONFIG_ARM_APPENDED_DTB=y
> diff --git a/arch/arm/configs/bcm2835_defconfig b/arch/arm/configs/bcm2835_defconfig
> index 4a8ac09843d7..b469ecc36cf5 100644
> --- a/arch/arm/configs/bcm2835_defconfig
> +++ b/arch/arm/configs/bcm2835_defconfig
> @@ -25,7 +25,6 @@ CONFIG_CRASH_DUMP=y
> CONFIG_ARCH_MULTI_V6=y
> CONFIG_ARCH_BCM=y
> CONFIG_ARCH_BCM2835=y
> -CONFIG_AEABI=y
> CONFIG_SECCOMP=y
> CONFIG_KEXEC=y
> CONFIG_CPU_FREQ=y
> diff --git a/arch/arm/configs/clps711x_defconfig b/arch/arm/configs/clps711x_defconfig
> index f66d502ce2ef..7ba344e84c62 100644
> --- a/arch/arm/configs/clps711x_defconfig
> +++ b/arch/arm/configs/clps711x_defconfig
> @@ -6,7 +6,6 @@ CONFIG_RD_LZMA=y
> CONFIG_EXPERT=y
> CONFIG_JUMP_LABEL=y
> CONFIG_PARTITION_ADVANCED=y
> -CONFIG_AEABI=y
> # CONFIG_COREDUMP is not set
> CONFIG_SLUB_TINY=y
> CONFIG_NET=y
> diff --git a/arch/arm/configs/collie_defconfig b/arch/arm/configs/collie_defconfig
> index 578c6a4af620..165202960438 100644
> --- a/arch/arm/configs/collie_defconfig
> +++ b/arch/arm/configs/collie_defconfig
> @@ -10,7 +10,6 @@ CONFIG_ARCH_MULTI_V4=y
> CONFIG_ARCH_SA1100=y
> CONFIG_SA1100_COLLIE=y
> CONFIG_CMDLINE="noinitrd root=/dev/mtdblock2 rootfstype=jffs2 fbcon=rotate:1"
> -CONFIG_FPE_NWFPE=y
> CONFIG_PM=y
> # CONFIG_SWAP is not set
> CONFIG_SLUB_TINY=y
> diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig
> index 72703ef0c51c..e6fbe1f03920 100644
> --- a/arch/arm/configs/davinci_all_defconfig
> +++ b/arch/arm/configs/davinci_all_defconfig
> @@ -17,7 +17,6 @@ CONFIG_ARCH_DAVINCI=y
> CONFIG_ARCH_DAVINCI_DA850=y
> CONFIG_DAVINCI_MUX_DEBUG=y
> CONFIG_DAVINCI_MUX_WARNINGS=y
> -CONFIG_AEABI=y
> CONFIG_SECCOMP=y
> CONFIG_ARM_APPENDED_DTB=y
> CONFIG_ARM_ATAG_DTB_COMPAT=y
> diff --git a/arch/arm/configs/dove_defconfig b/arch/arm/configs/dove_defconfig
> index b6ed01216a62..08271e6719d7 100644
> --- a/arch/arm/configs/dove_defconfig
> +++ b/arch/arm/configs/dove_defconfig
> @@ -7,7 +7,6 @@ CONFIG_EXPERT=y
> CONFIG_ARCH_MULTI_V7=y
> CONFIG_ARCH_DOVE=y
> CONFIG_MACH_CM_A510=y
> -CONFIG_AEABI=y
> CONFIG_HIGHMEM=y
> CONFIG_ARM_APPENDED_DTB=y
> CONFIG_ARM_ATAG_DTB_COMPAT=y
> diff --git a/arch/arm/configs/ep93xx_defconfig b/arch/arm/configs/ep93xx_defconfig
> index ce41dc8c435c..6863d8fd7713 100644
> --- a/arch/arm/configs/ep93xx_defconfig
> +++ b/arch/arm/configs/ep93xx_defconfig
> @@ -18,7 +18,6 @@ CONFIG_MACH_EDB9315=y
> CONFIG_MACH_EDB9315A=y
> CONFIG_MACH_TS72XX=y
> CONFIG_MACH_VISION_EP9307=y
> -CONFIG_AEABI=y
> CONFIG_CMDLINE="console=ttyAM0,115200 root=/dev/nfs ip=bootp"
> CONFIG_MODULES=y
> CONFIG_MODULE_UNLOAD=y
> diff --git a/arch/arm/configs/footbridge_defconfig b/arch/arm/configs/footbridge_defconfig
> index 5f6963687ee4..589b7b1df8c6 100644
> --- a/arch/arm/configs/footbridge_defconfig
> +++ b/arch/arm/configs/footbridge_defconfig
> @@ -11,6 +11,7 @@ CONFIG_ARCH_EBSA285_HOST=y
> CONFIG_ARCH_NETWINDER=y
> CONFIG_FPE_NWFPE=y
> CONFIG_FPE_NWFPE_XP=y
> +# CONFIG_AEABI is not set
> CONFIG_MODULES=y
> CONFIG_PARTITION_ADVANCED=y
> CONFIG_ACORN_PARTITION=y
> diff --git a/arch/arm/configs/gemini_defconfig b/arch/arm/configs/gemini_defconfig
> index 7b1daec630cb..5860b2fe7d1f 100644
> --- a/arch/arm/configs/gemini_defconfig
> +++ b/arch/arm/configs/gemini_defconfig
> @@ -11,7 +11,6 @@ CONFIG_KEXEC=y
> CONFIG_ARCH_MULTI_V4=y
> # CONFIG_ARCH_MULTI_V7 is not set
> CONFIG_ARCH_GEMINI=y
> -CONFIG_AEABI=y
> CONFIG_HIGHMEM=y
> CONFIG_CMDLINE="console=ttyS0,115200n8"
> CONFIG_PM=y
> diff --git a/arch/arm/configs/h3600_defconfig b/arch/arm/configs/h3600_defconfig
> index 4e272875c797..0923d331190a 100644
> --- a/arch/arm/configs/h3600_defconfig
> +++ b/arch/arm/configs/h3600_defconfig
> @@ -9,7 +9,6 @@ CONFIG_ARCH_MULTI_V4=y
> CONFIG_ARCH_SA1100=y
> CONFIG_SA1100_H3600=y
> # CONFIG_CPU_FREQ_STAT is not set
> -CONFIG_FPE_NWFPE=y
> CONFIG_MODULES=y
> CONFIG_NET=y
> CONFIG_UNIX=y
> diff --git a/arch/arm/configs/hisi_defconfig b/arch/arm/configs/hisi_defconfig
> index dde9cff951d4..c89b743784ca 100644
> --- a/arch/arm/configs/hisi_defconfig
> +++ b/arch/arm/configs/hisi_defconfig
> @@ -10,7 +10,6 @@ CONFIG_ARCH_HIP04=y
> CONFIG_ARCH_HIX5HD2=y
> CONFIG_SMP=y
> CONFIG_NR_CPUS=16
> -CONFIG_AEABI=y
> CONFIG_HIGHMEM=y
> CONFIG_ARM_APPENDED_DTB=y
> CONFIG_ARM_ATAG_DTB_COMPAT=y
> diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig
> index 9139d1784c70..871e93dd65b5 100644
> --- a/arch/arm/configs/imx_v4_v5_defconfig
> +++ b/arch/arm/configs/imx_v4_v5_defconfig
> @@ -15,7 +15,6 @@ CONFIG_ARCH_MXC=y
> CONFIG_SOC_IMX1=y
> CONFIG_SOC_IMX25=y
> CONFIG_SOC_IMX27=y
> -CONFIG_AEABI=y
> CONFIG_PM_DEBUG=y
> CONFIG_KPROBES=y
> CONFIG_MODULES=y
> diff --git a/arch/arm/configs/integrator_defconfig b/arch/arm/configs/integrator_defconfig
> index 61711d4bbf74..ba38ec810a61 100644
> --- a/arch/arm/configs/integrator_defconfig
> +++ b/arch/arm/configs/integrator_defconfig
> @@ -13,7 +13,6 @@ CONFIG_ARCH_INTEGRATOR=y
> CONFIG_ARCH_INTEGRATOR_AP=y
> CONFIG_INTEGRATOR_IMPD1=y
> CONFIG_ARCH_INTEGRATOR_CP=y
> -CONFIG_AEABI=y
> # CONFIG_ATAGS is not set
> CONFIG_CMDLINE="console=ttyAM0,38400n8 root=/dev/nfs ip=bootp"
> CONFIG_CPU_FREQ=y
> diff --git a/arch/arm/configs/ixp4xx_defconfig b/arch/arm/configs/ixp4xx_defconfig
> index 418ef909572b..122ca7354986 100644
> --- a/arch/arm/configs/ixp4xx_defconfig
> +++ b/arch/arm/configs/ixp4xx_defconfig
> @@ -9,7 +9,6 @@ CONFIG_EXPERT=y
> # CONFIG_ARCH_MULTI_V7 is not set
> CONFIG_ARCH_IXP4XX=y
> CONFIG_CPU_BIG_ENDIAN=y
> -CONFIG_AEABI=y
> CONFIG_CMDLINE="console=ttyS0,115200"
> CONFIG_STRICT_KERNEL_RWX=y
> CONFIG_STRICT_MODULE_RWX=y
> diff --git a/arch/arm/configs/jornada720_defconfig b/arch/arm/configs/jornada720_defconfig
> index d57285cfefb2..0ebddd083b36 100644
> --- a/arch/arm/configs/jornada720_defconfig
> +++ b/arch/arm/configs/jornada720_defconfig
> @@ -5,7 +5,6 @@ CONFIG_ARCH_MULTI_V4=y
> CONFIG_ARCH_SA1100=y
> CONFIG_SA1100_JORNADA720=y
> CONFIG_SA1100_JORNADA720_SSP=y
> -CONFIG_FPE_NWFPE=y
> CONFIG_PM=y
> CONFIG_MODULES=y
> CONFIG_NET=y
> diff --git a/arch/arm/configs/keystone_defconfig b/arch/arm/configs/keystone_defconfig
> index b0cadd878152..af91b9a420c9 100644
> --- a/arch/arm/configs/keystone_defconfig
> +++ b/arch/arm/configs/keystone_defconfig
> @@ -22,7 +22,6 @@ CONFIG_PCI_KEYSTONE=y
> CONFIG_SMP=y
> CONFIG_HOTPLUG_CPU=y
> CONFIG_ARM_PSCI=y
> -CONFIG_AEABI=y
> CONFIG_HIGHMEM=y
> CONFIG_VFP=y
> CONFIG_NEON=y
> diff --git a/arch/arm/configs/lpc32xx_defconfig b/arch/arm/configs/lpc32xx_defconfig
> index b9e2e603cd95..c0b45eea1b0f 100644
> --- a/arch/arm/configs/lpc32xx_defconfig
> +++ b/arch/arm/configs/lpc32xx_defconfig
> @@ -10,7 +10,6 @@ CONFIG_CC_OPTIMIZE_FOR_SIZE=y
> CONFIG_EXPERT=y
> # CONFIG_ARCH_MULTI_V7 is not set
> CONFIG_ARCH_LPC32XX=y
> -CONFIG_AEABI=y
> CONFIG_ARM_APPENDED_DTB=y
> CONFIG_ARM_ATAG_DTB_COMPAT=y
> CONFIG_CMDLINE="console=ttyS0,115200n81 root=/dev/ram0"
> diff --git a/arch/arm/configs/mmp2_defconfig b/arch/arm/configs/mmp2_defconfig
> index 0ea608c75f22..2ca166d4e78f 100644
> --- a/arch/arm/configs/mmp2_defconfig
> +++ b/arch/arm/configs/mmp2_defconfig
> @@ -4,7 +4,6 @@ CONFIG_PREEMPT=y
> CONFIG_LOG_BUF_SHIFT=14
> # CONFIG_BLK_DEV_BSG is not set
> CONFIG_ARCH_MMP=y
> -CONFIG_AEABI=y
> CONFIG_MACH_MMP2_DT=y
> CONFIG_CMDLINE="root=/dev/nfs rootfstype=nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on console=ttyS2,38400 mem=128M user_debug=255 earlyprintk"
> CONFIG_VFP=y
> diff --git a/arch/arm/configs/moxart_defconfig b/arch/arm/configs/moxart_defconfig
> index e2d9f3610063..d97d9ea5c34d 100644
> --- a/arch/arm/configs/moxart_defconfig
> +++ b/arch/arm/configs/moxart_defconfig
> @@ -16,7 +16,6 @@ CONFIG_ARCH_MULTI_V4=y
> # CONFIG_ARCH_MULTI_V7 is not set
> CONFIG_ARCH_MOXART=y
> CONFIG_MACH_UC7112LX=y
> -CONFIG_AEABI=y
> # CONFIG_ATAGS is not set
> CONFIG_ARM_APPENDED_DTB=y
> # CONFIG_SWAP is not set
> diff --git a/arch/arm/configs/multi_v4t_defconfig b/arch/arm/configs/multi_v4t_defconfig
> index 1a86dc305523..14c93bb59ad6 100644
> --- a/arch/arm/configs/multi_v4t_defconfig
> +++ b/arch/arm/configs/multi_v4t_defconfig
> @@ -17,7 +17,6 @@ CONFIG_INTEGRATOR_IMPD1=y
> CONFIG_INTEGRATOR_CM720T=y
> CONFIG_INTEGRATOR_CM920T=y
> CONFIG_INTEGRATOR_CM922T_XA10=y
> -CONFIG_AEABI=y
> # CONFIG_ATAGS is not set
> CONFIG_CPU_IDLE=y
> CONFIG_ARM_CPUIDLE=y
> diff --git a/arch/arm/configs/multi_v5_defconfig b/arch/arm/configs/multi_v5_defconfig
> index d237ea8ea327..7eab9fb9ffc4 100644
> --- a/arch/arm/configs/multi_v5_defconfig
> +++ b/arch/arm/configs/multi_v5_defconfig
> @@ -36,7 +36,6 @@ CONFIG_MACH_NET2BIG=y
> CONFIG_MACH_MSS2_DT=y
> CONFIG_ARCH_SUNXI=y
> CONFIG_ARCH_VERSATILE=y
> -CONFIG_AEABI=y
> CONFIG_HIGHMEM=y
> CONFIG_ARM_APPENDED_DTB=y
> CONFIG_ARM_ATAG_DTB_COMPAT=y
> diff --git a/arch/arm/configs/mv78xx0_defconfig b/arch/arm/configs/mv78xx0_defconfig
> index 1174893102bd..823f7963b8b3 100644
> --- a/arch/arm/configs/mv78xx0_defconfig
> +++ b/arch/arm/configs/mv78xx0_defconfig
> @@ -11,9 +11,7 @@ CONFIG_ARCH_MULTI_V5=y
> # CONFIG_ARCH_MULTI_V7 is not set
> CONFIG_ARCH_MV78XX0=y
> CONFIG_MACH_TERASTATION_WXL=y
> -CONFIG_AEABI=y
> CONFIG_HIGHMEM=y
> -CONFIG_FPE_NWFPE=y
> CONFIG_VFP=y
> CONFIG_KPROBES=y
> CONFIG_MODULES=y
> diff --git a/arch/arm/configs/mvebu_v5_defconfig b/arch/arm/configs/mvebu_v5_defconfig
> index 781f8f72df5f..0709a5e66bb5 100644
> --- a/arch/arm/configs/mvebu_v5_defconfig
> +++ b/arch/arm/configs/mvebu_v5_defconfig
> @@ -22,7 +22,6 @@ CONFIG_MACH_MV2120=y
> CONFIG_MACH_D2NET_DT=y
> CONFIG_MACH_NET2BIG=y
> CONFIG_MACH_MSS2_DT=y
> -CONFIG_AEABI=y
> CONFIG_HIGHMEM=y
> CONFIG_ARM_APPENDED_DTB=y
> CONFIG_ARM_ATAG_DTB_COMPAT=y
> diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
> index 603fb003b223..b0b5eb33d01e 100644
> --- a/arch/arm/configs/mxs_defconfig
> +++ b/arch/arm/configs/mxs_defconfig
> @@ -17,7 +17,6 @@ CONFIG_BLK_DEV_INITRD=y
> CONFIG_PERF_EVENTS=y
> # CONFIG_ARCH_MULTI_V7 is not set
> CONFIG_ARCH_MXS=y
> -CONFIG_AEABI=y
> CONFIG_MODULES=y
> CONFIG_MODULE_FORCE_LOAD=y
> CONFIG_MODULE_UNLOAD=y
> diff --git a/arch/arm/configs/neponset_defconfig b/arch/arm/configs/neponset_defconfig
> index 8a5dcca743fc..c3010a4d93a8 100644
> --- a/arch/arm/configs/neponset_defconfig
> +++ b/arch/arm/configs/neponset_defconfig
> @@ -11,6 +11,7 @@ CONFIG_ZBOOT_ROM_BSS=0xc1000000
> CONFIG_ZBOOT_ROM=y
> CONFIG_CMDLINE="console=ttySA0,38400n8 cpufreq=221200 rw root=/dev/mtdblock2 mtdparts=sa1100:512K(boot),1M(kernel),2560K(initrd),4M(root) mem=32M noinitrd initrd=0xc0800000,3M"
> CONFIG_FPE_NWFPE=y
> +# CONFIG_AEABI is not set
> CONFIG_PM=y
> CONFIG_MODULES=y
> CONFIG_MODULE_UNLOAD=y
> diff --git a/arch/arm/configs/netwinder_defconfig b/arch/arm/configs/netwinder_defconfig
> index e639e6ad02cb..7ff70439458d 100644
> --- a/arch/arm/configs/netwinder_defconfig
> +++ b/arch/arm/configs/netwinder_defconfig
> @@ -4,6 +4,7 @@ CONFIG_ARCH_MULTI_V4=y
> # CONFIG_ARCH_MULTI_V7 is not set
> CONFIG_ARCH_FOOTBRIDGE=y
> CONFIG_ARCH_NETWINDER=y
> +# CONFIG_AEABI is not set
> CONFIG_DEPRECATED_PARAM_STRUCT=y
> CONFIG_CMDLINE="root=0x801"
> CONFIG_FPE_NWFPE=y
> diff --git a/arch/arm/configs/nhk8815_defconfig b/arch/arm/configs/nhk8815_defconfig
> index 696b4fbc2412..7a307bd93730 100644
> --- a/arch/arm/configs/nhk8815_defconfig
> +++ b/arch/arm/configs/nhk8815_defconfig
> @@ -12,7 +12,6 @@ CONFIG_KALLSYMS_ALL=y
> # CONFIG_ARCH_MULTI_V7 is not set
> CONFIG_ARCH_NOMADIK=y
> CONFIG_MACH_NOMADIK_8815NHK=y
> -CONFIG_AEABI=y
> CONFIG_MODULES=y
> CONFIG_MODULE_UNLOAD=y
> # CONFIG_SWAP is not set
> diff --git a/arch/arm/configs/omap1_defconfig b/arch/arm/configs/omap1_defconfig
> index 7bf58e8a5ab5..8d11ba724204 100644
> --- a/arch/arm/configs/omap1_defconfig
> +++ b/arch/arm/configs/omap1_defconfig
> @@ -28,9 +28,7 @@ CONFIG_MACH_OMAP_PALMTE=y
> CONFIG_MACH_SX1=y
> CONFIG_MACH_NOKIA770=y
> CONFIG_MACH_AMS_DELTA=y
> -CONFIG_AEABI=y
> CONFIG_CMDLINE="root=1f03 rootfstype=jffs2"
> -CONFIG_FPE_NWFPE=y
> # CONFIG_SUSPEND is not set
> CONFIG_PM=y
> CONFIG_MODULES=y
> diff --git a/arch/arm/configs/orion5x_defconfig b/arch/arm/configs/orion5x_defconfig
> index f5be2e26d9ae..d658d5e04e2d 100644
> --- a/arch/arm/configs/orion5x_defconfig
> +++ b/arch/arm/configs/orion5x_defconfig
> @@ -20,10 +20,8 @@ CONFIG_MACH_TS409=y
> CONFIG_MACH_TS78XX=y
> CONFIG_MACH_MV2120=y
> CONFIG_MACH_NET2BIG=y
> -CONFIG_AEABI=y
> CONFIG_ARM_APPENDED_DTB=y
> CONFIG_ARM_ATAG_DTB_COMPAT=y
> -CONFIG_FPE_NWFPE=y
> CONFIG_VFP=y
> CONFIG_KPROBES=y
> CONFIG_MODULES=y
> diff --git a/arch/arm/configs/pxa168_defconfig b/arch/arm/configs/pxa168_defconfig
> index 8cbca84fe33a..d6af01434f04 100644
> --- a/arch/arm/configs/pxa168_defconfig
> +++ b/arch/arm/configs/pxa168_defconfig
> @@ -3,11 +3,9 @@ CONFIG_SYSVIPC=y
> CONFIG_NO_HZ_IDLE=y
> CONFIG_HIGH_RES_TIMERS=y
> CONFIG_PREEMPT=y
> -CONFIG_AEABI=y
> CONFIG_LOG_BUF_SHIFT=14
> CONFIG_ARCH_MMP=y
> CONFIG_CMDLINE="root=/dev/nfs rootfstype=nfs nfsroot=192.168.2.100:/nfsroot/ ip=192.168.2.101:192.168.2.100::255.255.255.0::eth0:on console=ttyS0,115200 mem=128M"
> -CONFIG_FPE_NWFPE=y
> CONFIG_MODULES=y
> CONFIG_MODULE_UNLOAD=y
> CONFIG_MODULE_FORCE_UNLOAD=y
> diff --git a/arch/arm/configs/pxa3xx_defconfig b/arch/arm/configs/pxa3xx_defconfig
> index fb272e3a2337..2a777698d06f 100644
> --- a/arch/arm/configs/pxa3xx_defconfig
> +++ b/arch/arm/configs/pxa3xx_defconfig
> @@ -7,9 +7,7 @@ CONFIG_KALLSYMS_ALL=y
> # CONFIG_ARCH_MULTI_V7 is not set
> CONFIG_ARCH_PXA=y
> CONFIG_MACH_PXA3XX_DT=y
> -CONFIG_AEABI=y
> CONFIG_CMDLINE="root=/dev/nfs rootfstype=nfs nfsroot=192.168.1.100:/nfsroot/ ip=192.168.1.101:192.168.1.100::255.255.255.0::eth0:on console=ttyS0,115200 mem=64M debug"
> -CONFIG_FPE_NWFPE=y
> CONFIG_MODULES=y
> CONFIG_NET=y
> CONFIG_PACKET=y
> diff --git a/arch/arm/configs/pxa910_defconfig b/arch/arm/configs/pxa910_defconfig
> index 71ed0d73f8a9..9e7b11d1e723 100644
> --- a/arch/arm/configs/pxa910_defconfig
> +++ b/arch/arm/configs/pxa910_defconfig
> @@ -10,8 +10,6 @@ CONFIG_MODULES=y
> CONFIG_MODULE_UNLOAD=y
> CONFIG_MODULE_FORCE_UNLOAD=y
> # CONFIG_BLK_DEV_BSG is not set
> -CONFIG_AEABI=y
> -CONFIG_FPE_NWFPE=y
> CONFIG_NET=y
> CONFIG_PACKET=y
> CONFIG_UNIX=y
> diff --git a/arch/arm/configs/pxa_defconfig b/arch/arm/configs/pxa_defconfig
> index 66cc149c5ca4..396680975506 100644
> --- a/arch/arm/configs/pxa_defconfig
> +++ b/arch/arm/configs/pxa_defconfig
> @@ -20,7 +20,6 @@ CONFIG_ARCH_GUMSTIX=y
> CONFIG_PXA_SHARPSL=y
> CONFIG_MACH_AKITA=y
> CONFIG_MACH_BORZOI=y
> -CONFIG_AEABI=y
> CONFIG_ARCH_FORCE_MAX_ORDER=8
> CONFIG_CMDLINE="root=/dev/ram0 ro"
> CONFIG_CPU_FREQ=y
> diff --git a/arch/arm/configs/rpc_defconfig b/arch/arm/configs/rpc_defconfig
> index 46df453e224e..8d73ec43cb41 100644
> --- a/arch/arm/configs/rpc_defconfig
> +++ b/arch/arm/configs/rpc_defconfig
> @@ -7,6 +7,7 @@ CONFIG_ARCH_MULTI_V4=y
> CONFIG_ARCH_RPC=y
> CONFIG_CPU_SA110=y
> CONFIG_FPE_NWFPE=y
> +# CONFIG_AEABI is not set
> CONFIG_MODULES=y
> CONFIG_MODULE_UNLOAD=y
> CONFIG_PARTITION_ADVANCED=y
> diff --git a/arch/arm/configs/spear13xx_defconfig b/arch/arm/configs/spear13xx_defconfig
> index 6712ae741c19..648260f536a1 100644
> --- a/arch/arm/configs/spear13xx_defconfig
> +++ b/arch/arm/configs/spear13xx_defconfig
> @@ -9,7 +9,6 @@ CONFIG_MACH_SPEAR1340=y
> CONFIG_SMP=y
> # CONFIG_SMP_ON_UP is not set
> # CONFIG_ARM_CPU_TOPOLOGY is not set
> -CONFIG_AEABI=y
> CONFIG_ARM_APPENDED_DTB=y
> CONFIG_ARM_ATAG_DTB_COMPAT=y
> CONFIG_VFP=y
> diff --git a/arch/arm/configs/spitz_defconfig b/arch/arm/configs/spitz_defconfig
> index 8f8a058294fb..d68a8f9cdad4 100644
> --- a/arch/arm/configs/spitz_defconfig
> +++ b/arch/arm/configs/spitz_defconfig
> @@ -11,7 +11,6 @@ CONFIG_PXA_SHARPSL=y
> CONFIG_MACH_AKITA=y
> CONFIG_MACH_BORZOI=y
> CONFIG_CMDLINE="console=ttyS0,115200n8 console=tty1 noinitrd root=/dev/mtdblock2 rootfstype=jffs2 debug"
> -CONFIG_FPE_NWFPE=y
> CONFIG_MODULES=y
> CONFIG_MODULE_UNLOAD=y
> CONFIG_MODULE_FORCE_UNLOAD=y
> diff --git a/arch/arm/configs/versatile_defconfig b/arch/arm/configs/versatile_defconfig
> index 849118cbbb44..8e89debb5a5b 100644
> --- a/arch/arm/configs/versatile_defconfig
> +++ b/arch/arm/configs/versatile_defconfig
> @@ -6,7 +6,6 @@ CONFIG_LOG_BUF_SHIFT=14
> CONFIG_BLK_DEV_INITRD=y
> # CONFIG_ARCH_MULTI_V7 is not set
> CONFIG_ARCH_VERSATILE=y
> -CONFIG_AEABI=y
> CONFIG_OABI_COMPAT=y
> CONFIG_CMDLINE="root=1f03 mem=32M"
> CONFIG_FPE_NWFPE=y
> diff --git a/arch/arm/configs/vt8500_v6_v7_defconfig b/arch/arm/configs/vt8500_v6_v7_defconfig
> index 41607a84abc8..2925a1f1dbb6 100644
> --- a/arch/arm/configs/vt8500_v6_v7_defconfig
> +++ b/arch/arm/configs/vt8500_v6_v7_defconfig
> @@ -8,7 +8,6 @@ CONFIG_ARM_ERRATA_720789=y
> CONFIG_ARM_ERRATA_754322=y
> CONFIG_ARM_ERRATA_775420=y
> CONFIG_HAVE_ARM_ARCH_TIMER=y
> -CONFIG_AEABI=y
> CONFIG_HIGHMEM=y
> CONFIG_HIGHPTE=y
> CONFIG_ARM_APPENDED_DTB=y
> diff --git a/arch/arm/configs/wpcm450_defconfig b/arch/arm/configs/wpcm450_defconfig
> index 67b64a378166..9cb379077d70 100644
> --- a/arch/arm/configs/wpcm450_defconfig
> +++ b/arch/arm/configs/wpcm450_defconfig
> @@ -13,7 +13,6 @@ CONFIG_PROFILING=y
> CONFIG_ARCH_NPCM=y
> CONFIG_ARCH_WPCM450=y
> CONFIG_CPU_DCACHE_WRITETHROUGH=y
> -CONFIG_AEABI=y
> CONFIG_UACCESS_WITH_MEMCPY=y
> # CONFIG_ATAGS is not set
> CONFIG_ARM_APPENDED_DTB=y
> --
> 2.39.5
>
^ permalink raw reply
* [PATCH v7 8/8] arm64: dts: imx8qxp-mek: add parallel ov5640 camera support
From: Frank.Li @ 2026-07-02 16:04 UTC (permalink / raw)
To: Sakari Ailus, Mauro Carvalho Chehab, Michael Riesch,
Laurent Pinchart, Frank Li, Martin Kepplinger-Novakovic,
Rui Miguel Silva, Purism Kernel Team, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam
Cc: linux-media, linux-kernel, imx, Guoniu Zhou, devicetree,
linux-arm-kernel
In-Reply-To: <20260702-imx8qxp_pcam-v7-0-b47d9e363400@nxp.com>
From: Frank Li <Frank.Li@nxp.com>
Add parallel ov5640 nodes in imx8qxp-mek and create overlay file to enable
it because it can work at two mode: MIPI CSI and parallel mode.
Reviewed-by: Guoniu Zhou <guoniu.zhou@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
Changes in v7
- none
changes in v6
- add Guoniu's reviewed-by tags
changes in v4
- add hsync-active = <1>
changes in v3
- replace csi with cpi.
- use imx8qxp-mek-ov5640-cpi.dtso since csi use imx8qxp-mek-ov5640-csi.dtso
change in v2
- move ov5640 part to overlay file
- rename to imx8qxp-mek-ov5640-parallel.dtso
- remove data-lanes
---
arch/arm64/boot/dts/freescale/Makefile | 3 +
.../boot/dts/freescale/imx8qxp-mek-ov5640-cpi.dtso | 83 ++++++++++++++++++++++
2 files changed, 86 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 001ca3a12c0ae..3b9e9844f11ef 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -554,6 +554,9 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek-pcie-ep.dtb
imx8qxp-mek-ov5640-csi-dtbs := imx8qxp-mek.dtb imx8qxp-mek-ov5640-csi.dtbo
dtb-${CONFIG_ARCH_MXC} += imx8qxp-mek-ov5640-csi.dtb
+imx8qxp-mek-ov5640-cpi-dtbs := imx8qxp-mek.dtb imx8qxp-mek-ov5640-cpi.dtbo
+dtb-${CONFIG_ARCH_MXC} += imx8qxp-mek-ov5640-cpi.dtb
+
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqp-mba8xx.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqps-mb-smarc-2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8ulp-9x9-evk.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640-cpi.dtso b/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640-cpi.dtso
new file mode 100644
index 0000000000000..9fbdd798f17d6
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640-cpi.dtso
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2025 NXP
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/imx8-lpcg.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/media/video-interfaces.h>
+#include <dt-bindings/pinctrl/pads-imx8qxp.h>
+
+&cm40_i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ov5640_pi: camera@3c {
+ compatible = "ovti,ov5640";
+ reg = <0x3c>;
+ clocks = <&pi0_misc_lpcg IMX_LPCG_CLK_0>;
+ clock-names = "xclk";
+ assigned-clocks = <&pi0_misc_lpcg IMX_LPCG_CLK_0>;
+ assigned-clock-rates = <24000000>;
+ AVDD-supply = <®_2v8>;
+ DOVDD-supply = <®_1v8>;
+ DVDD-supply = <®_1v5>;
+ pinctrl-0 = <&pinctrl_parallel_cpi>;
+ pinctrl-names = "default";
+ powerdown-gpios = <&lsio_gpio3 2 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&lsio_gpio3 3 GPIO_ACTIVE_LOW>;
+
+ port {
+ ov5640_pi_ep: endpoint {
+ bus-type = <MEDIA_BUS_TYPE_PARALLEL>;
+ bus-width = <8>;
+ hsync-active = <1>;
+ pclk-sample = <1>;
+ remote-endpoint = <¶llel_cpi_in>;
+ vsync-active = <0>;
+ };
+ };
+ };
+};
+
+&iomuxc {
+ pinctrl_parallel_cpi: parallelcpigrp {
+ fsl,pins = <
+ IMX8QXP_CSI_D00_CI_PI_D02 0xc0000041
+ IMX8QXP_CSI_D01_CI_PI_D03 0xc0000041
+ IMX8QXP_CSI_D02_CI_PI_D04 0xc0000041
+ IMX8QXP_CSI_D03_CI_PI_D05 0xc0000041
+ IMX8QXP_CSI_D04_CI_PI_D06 0xc0000041
+ IMX8QXP_CSI_D05_CI_PI_D07 0xc0000041
+ IMX8QXP_CSI_D06_CI_PI_D08 0xc0000041
+ IMX8QXP_CSI_D07_CI_PI_D09 0xc0000041
+
+ IMX8QXP_CSI_MCLK_CI_PI_MCLK 0xc0000041
+ IMX8QXP_CSI_PCLK_CI_PI_PCLK 0xc0000041
+ IMX8QXP_CSI_HSYNC_CI_PI_HSYNC 0xc0000041
+ IMX8QXP_CSI_VSYNC_CI_PI_VSYNC 0xc0000041
+ IMX8QXP_CSI_EN_LSIO_GPIO3_IO02 0xc0000041
+ IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 0xc0000041
+ >;
+ };
+};
+
+&isi {
+ status = "okay";
+};
+
+¶llel_cpi {
+ status = "okay";
+
+ ports {
+ port@0 {
+ parallel_cpi_in: endpoint {
+ hsync-active = <1>;
+ remote-endpoint = <&ov5640_pi_ep>;
+ };
+ };
+ };
+};
--
2.43.0
^ permalink raw reply related
* [PATCH v7 7/8] arm64: dts: imx8: add camera parallel interface (CPI) node
From: Frank.Li @ 2026-07-02 16:04 UTC (permalink / raw)
To: Sakari Ailus, Mauro Carvalho Chehab, Michael Riesch,
Laurent Pinchart, Frank Li, Martin Kepplinger-Novakovic,
Rui Miguel Silva, Purism Kernel Team, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam
Cc: linux-media, linux-kernel, imx, Guoniu Zhou, devicetree,
linux-arm-kernel
In-Reply-To: <20260702-imx8qxp_pcam-v7-0-b47d9e363400@nxp.com>
From: Frank Li <Frank.Li@nxp.com>
Add camera parallel interface (CPI) node.
Reviewed-by: Guoniu Zhou <guoniu.zhou@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
Chagnes in v7
- none
changes in v6
- add Guoniu Zhou's review by
changes in v4
- none
changes in v3
- replace csi with cpi.
changes in v2
- update compatible string to match binding's change
---
arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi | 13 +++++++++++
arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi | 27 +++++++++++++++++++++++
2 files changed, 40 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi
index a72b2f1c4a1b2..b504f99f6acdb 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi
@@ -222,6 +222,19 @@ irqsteer_parallel: irqsteer@58260000 {
status = "disabled";
};
+ parallel_cpi: cpi@58261000 {
+ compatible = "fsl,imx8qxp-pcif";
+ reg = <0x58261000 0x1000>;
+ clocks = <&pi0_pxl_lpcg IMX_LPCG_CLK_0>,
+ <&pi0_ipg_lpcg IMX_LPCG_CLK_4>;
+ clock-names = "pixel", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-parents = <&clk IMX_SC_R_PI_0_PLL IMX_SC_PM_CLK_PLL>;
+ assigned-clock-rates = <160000000>;
+ power-domains = <&pd IMX_SC_R_PI_0>;
+ status = "disabled";
+ };
+
pi0_ipg_lpcg: clock-controller@58263004 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x58263004 0x4>;
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi
index 232cf25dadfcd..5aae15540d6cb 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi
@@ -62,6 +62,14 @@ isi_in_2: endpoint {
remote-endpoint = <&mipi_csi0_out>;
};
};
+
+ port@4 {
+ reg = <4>;
+
+ isi_in_4: endpoint {
+ remote-endpoint = <¶llel_cpi_out>;
+ };
+ };
};
};
@@ -95,3 +103,22 @@ &jpegenc {
&mipi_csi_1 {
status = "disabled";
};
+
+¶llel_cpi {
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+
+ parallel_cpi_out: endpoint {
+ remote-endpoint = <&isi_in_4>;
+ };
+ };
+ };
+};
--
2.43.0
^ permalink raw reply related
* [PATCH v7 6/8] media: nxp: add V4L2 subdev driver for camera parallel interface (CPI)
From: Frank.Li @ 2026-07-02 16:04 UTC (permalink / raw)
To: Sakari Ailus, Mauro Carvalho Chehab, Michael Riesch,
Laurent Pinchart, Frank Li, Martin Kepplinger-Novakovic,
Rui Miguel Silva, Purism Kernel Team, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam
Cc: linux-media, linux-kernel, imx, Guoniu Zhou, devicetree,
linux-arm-kernel, Alice Yuan, Robert Chiras, Zhipeng Wang
In-Reply-To: <20260702-imx8qxp_pcam-v7-0-b47d9e363400@nxp.com>
From: Alice Yuan <alice.yuan@nxp.com>
Add a V4L2 sub-device driver for the CPI controller found on i.MX8QXP,
i.MX8QM, and i.MX93 SoCs. This controller supports parallel camera sensors
and enables image data capture through a parallel interface.
Signed-off-by: Alice Yuan <alice.yuan@nxp.com>
Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Signed-off-by: Zhipeng Wang <zhipeng.wang_1@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
Change in v7
- save vep flags to local driver data
- update according new API change.
Change in v6
- Don't use subdev_1to1
- use new api media_async_register_subdev()
- remove used switch -case
Change in v5
- Use subdev_1to1 register function
- Use v4l2_subdev_get_frame_desc_passthrough
- Use dwc csi2 similar logic enable/disable stream
- Add route settup at imx_cpi_init_state()
- Remove V2 register layout support, add it later
change in v4
- remove unnecesary header file.
- use devm_bulk_clk_get().
- update kConfig i.MX8/i.MX9
- Remove define IMX_CPI_DEF_PIX_WIDTH ..., which used once only
- drop get_interface_ctrl_reg1_param
- drop uv-swap
- drop imx_cpi_link_setup by use immutable link.
- use enable/disable_stream() replace depericated .s_stream.
- remove dbg print and reg dump functions.
- use goto/.remove() to do manual cleanup.
- remove imx93 support. Add it later.
change in v3
- replace csi with cpi
- use __free(fwnode_handle) to simpilfy code
- remove imx91 driver data, which is the same as imx93
change in v2
- remove MODULE_ALIAS
- use devm_pm_runtime_enable() and cleanup remove function
- change output format to 1x16. controller convert 2x8 to 1x16 format
---
MAINTAINERS | 1 +
drivers/media/platform/nxp/Kconfig | 12 +
drivers/media/platform/nxp/Makefile | 1 +
drivers/media/platform/nxp/imx-parallel-cpi.c | 629 ++++++++++++++++++++++++++
4 files changed, 643 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index f690826964369..22f60b6e89bf2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -16251,6 +16251,7 @@ F: Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml
F: Documentation/devicetree/bindings/media/nxp,imx7-csi.yaml
F: Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml
F: drivers/media/platform/nxp/imx-mipi-csis.c
+F: drivers/media/platform/nxp/imx-parallel-cpi.c
F: drivers/media/platform/nxp/imx7-media-csi.c
F: drivers/media/platform/nxp/imx8mq-mipi-csi2.c
diff --git a/drivers/media/platform/nxp/Kconfig b/drivers/media/platform/nxp/Kconfig
index 40e3436669e21..90f7c792003f2 100644
--- a/drivers/media/platform/nxp/Kconfig
+++ b/drivers/media/platform/nxp/Kconfig
@@ -39,6 +39,18 @@ config VIDEO_IMX_MIPI_CSIS
Video4Linux2 sub-device driver for the MIPI CSI-2 CSIS receiver
v3.3/v3.6.3 found on some i.MX7 and i.MX8 SoCs.
+config VIDEO_IMX_PARALLEL_CPI
+ tristate "NXP i.MX8/i.MX9 Parallel CPI Driver"
+ depends on ARCH_MXC || COMPILE_TEST
+ depends on VIDEO_DEV
+ select MEDIA_CONTROLLER
+ select V4L2_1TO1
+ select V4L2_FWNODE
+ select VIDEO_V4L2_SUBDEV_API
+ help
+ Video4Linux2 sub-device driver for PARALLEL CPI receiver found
+ on some iMX8 and iMX9 SoCs.
+
source "drivers/media/platform/nxp/imx8-isi/Kconfig"
# mem2mem drivers
diff --git a/drivers/media/platform/nxp/Makefile b/drivers/media/platform/nxp/Makefile
index 4d90eb7136525..5346919d2f108 100644
--- a/drivers/media/platform/nxp/Makefile
+++ b/drivers/media/platform/nxp/Makefile
@@ -7,5 +7,6 @@ obj-y += imx8-isi/
obj-$(CONFIG_VIDEO_IMX7_CSI) += imx7-media-csi.o
obj-$(CONFIG_VIDEO_IMX8MQ_MIPI_CSI2) += imx8mq-mipi-csi2.o
obj-$(CONFIG_VIDEO_IMX_MIPI_CSIS) += imx-mipi-csis.o
+obj-$(CONFIG_VIDEO_IMX_PARALLEL_CPI) += imx-parallel-cpi.o
obj-$(CONFIG_VIDEO_IMX_PXP) += imx-pxp.o
obj-$(CONFIG_VIDEO_MX2_EMMAPRP) += mx2_emmaprp.o
diff --git a/drivers/media/platform/nxp/imx-parallel-cpi.c b/drivers/media/platform/nxp/imx-parallel-cpi.c
new file mode 100644
index 0000000000000..735d4a89f7b30
--- /dev/null
+++ b/drivers/media/platform/nxp/imx-parallel-cpi.c
@@ -0,0 +1,629 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * i.MX Parallel CPI receiver driver.
+ *
+ * Copyright 2019-2025 NXP
+ *
+ */
+
+#include <linux/bits.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/limits.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+
+#include <media/v4l2-common.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-event.h>
+#include <media/v4l2-fwnode.h>
+#include <media/v4l2-mc.h>
+#include <media/v4l2-subdev.h>
+
+/* CI_PI INTERFACE CONTROL */
+#define IF_CTRL_REG_PL_ENABLE BIT(0)
+#define IF_CTRL_REG_PL_VALID BIT(1)
+#define IF_CTRL_REG_DATA_TYPE_SEL BIT(8)
+#define IF_CTRL_REG_DATA_TYPE(x) FIELD_PREP(GENMASK(13, 9), (x))
+
+#define DATA_TYPE_OUT_NULL 0x00
+#define DATA_TYPE_OUT_RGB 0x04
+#define DATA_TYPE_OUT_YUV444 0x08
+#define DATA_TYPE_OUT_YYU420_ODD 0x10
+#define DATA_TYPE_OUT_YYU420_EVEN 0x12
+#define DATA_TYPE_OUT_YYY_ODD 0x18
+#define DATA_TYPE_OUT_UYVY_EVEN 0x1a
+#define DATA_TYPE_OUT_RAW 0x1c
+
+#define IF_CTRL_REG_IF_FORCE_HSYNV_OVERRIDE 0x4
+#define IF_CTRL_REG_IF_FORCE_VSYNV_OVERRIDE 0x2
+#define IF_CTRL_REG_IF_FORCE_DATA_ENABLE_OVERRIDE 0x1
+
+/* CPI INTERFACE CONTROL REG */
+#define CPI_CTRL_REG_CPI_EN BIT(0)
+#define CPI_CTRL_REG_PIXEL_CLK_POL BIT(1)
+#define CPI_CTRL_REG_HSYNC_POL BIT(2)
+#define CPI_CTRL_REG_VSYNC_POL BIT(3)
+#define CPI_CTRL_REG_DE_POL BIT(4)
+#define CPI_CTRL_REG_PIXEL_DATA_POL BIT(5)
+#define CPI_CTRL_REG_CCIR_EXT_VSYNC_EN BIT(6)
+#define CPI_CTRL_REG_CCIR_EN BIT(7)
+#define CPI_CTRL_REG_CCIR_VIDEO_MODE BIT(8)
+#define CPI_CTRL_REG_CCIR_NTSC_EN BIT(9)
+#define CPI_CTRL_REG_CCIR_VSYNC_RESET_EN BIT(10)
+#define CPI_CTRL_REG_CCIR_ECC_ERR_CORRECT_EN BIT(11)
+#define CPI_CTRL_REG_HSYNC_FORCE_EN BIT(12)
+#define CPI_CTRL_REG_VSYNC_FORCE_EN BIT(13)
+#define CPI_CTRL_REG_GCLK_MODE_EN BIT(14)
+#define CPI_CTRL_REG_VALID_SEL BIT(15)
+#define CPI_CTRL_REG_RAW_OUT_SEL BIT(16)
+#define CPI_CTRL_REG_HSYNC_OUT_SEL BIT(17)
+#define CPI_CTRL_REG_HSYNC_PULSE(x) FIELD_PREP(GENMASK(21, 19), (x))
+#define CPI_CTRL_REG_UV_SWAP_EN BIT(22)
+#define CPI_CTRL_REG_DATA_TYPE_IN(x) FIELD_PREP(GENMASK(26, 23), (x))
+#define CPI_CTRL_REG_MASK_VSYNC_COUNTER(x) FIELD_PREP(GENMASK(28, 27), (x))
+#define CPI_CTRL_REG_SOFTRST BIT(31)
+
+/* CPI INTERFACE STATUS */
+#define CPI_STATUS_FIELD_TOGGLE BIT(0)
+#define CPI_STATUS_ECC_ERROR BIT(1)
+
+/* CPI INTERFACE CONTROL REG1 */
+#define CPI_CTRL_REG1_PIXEL_WIDTH(v) FIELD_PREP(GENMASK(15, 0), (v))
+#define CPI_CTRL_REG1_VSYNC_PULSE(v) FIELD_PREP(GENMASK(31, 16), (v))
+
+#define CPI_CTRL_V2_REG1_PIXEL_WIDTH(v) FIELD_PREP(GENMASK(16, 0), (v))
+#define CPI_CTRL_V2_REG1_VSYNC_PULSE(v) FIELD_PREP(GENMASK(31, 16), (v))
+
+/* Need match field DATA_TYPE_IN definition at CPI CTRL register */
+enum cpi_in_data_type {
+ CPI_IN_DT_UYVY_BT656_8 = 0x0,
+ CPI_IN_DT_UYVY_BT656_10,
+ CPI_IN_DT_RGB_8,
+ CPI_IN_DT_BGR_8,
+ CPI_IN_DT_YVYU_8 = 0x5,
+ CPI_IN_DT_YUV_8,
+ CPI_IN_DT_RAW_8 = 0x9,
+ CPI_IN_DT_RAW_10,
+};
+
+enum {
+ PI_GATE_CLOCK_MODE,
+ PI_CCIR_MODE,
+};
+
+enum {
+ PI_V1,
+};
+
+struct imx_cpi_plat_data {
+ u32 version;
+ u32 if_ctrl_reg;
+ u32 interface_status;
+ u32 interface_ctrl_reg;
+ u32 interface_ctrl_reg1;
+};
+
+struct imx_cpi_device {
+ struct device *dev;
+ void __iomem *regs;
+ struct clk_bulk_data *clks;
+ int num_clks;
+
+ struct v4l2_subdev sd;
+
+ const struct imx_cpi_plat_data *pdata;
+
+ u32 flags;
+ u32 enabled_streams;
+ u8 mode;
+};
+
+struct imx_cpi_pix_format {
+ u32 code;
+ u32 output;
+ u32 data_type;
+ u8 width;
+};
+
+static const struct imx_cpi_pix_format imx_cpi_formats[] = {
+ /* YUV formats. */
+ {
+ .code = MEDIA_BUS_FMT_UYVY8_2X8,
+ .output = MEDIA_BUS_FMT_UYVY8_1X16,
+ .data_type = CPI_IN_DT_UYVY_BT656_8,
+ .width = 16,
+ }, {
+ .code = MEDIA_BUS_FMT_YUYV8_2X8,
+ .output = MEDIA_BUS_FMT_YUYV8_1X16,
+ .data_type = CPI_IN_DT_YVYU_8,
+ .width = 16,
+ },
+};
+
+static const struct imx_cpi_plat_data imx8qxp_pdata = {
+ .version = PI_V1,
+ .if_ctrl_reg = 0x0,
+ .interface_status = 0x20,
+ .interface_ctrl_reg = 0x10,
+ .interface_ctrl_reg1 = 0x30,
+};
+
+static const struct imx_cpi_pix_format *find_imx_cpi_format(u32 code)
+{
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(imx_cpi_formats); i++)
+ if (code == imx_cpi_formats[i].code)
+ return &imx_cpi_formats[i];
+
+ return NULL;
+}
+
+static void imx_cpi_sw_reset(struct imx_cpi_device *pcpidev)
+{
+ const struct imx_cpi_plat_data *pdata = pcpidev->pdata;
+ u32 val;
+
+ /* Softwaret Reset */
+ val = readl(pcpidev->regs + pdata->interface_ctrl_reg);
+ val |= CPI_CTRL_REG_SOFTRST;
+ writel(val, pcpidev->regs + pdata->interface_ctrl_reg);
+
+ fsleep(500);
+ val = readl(pcpidev->regs + pdata->interface_ctrl_reg);
+ val &= ~CPI_CTRL_REG_SOFTRST;
+ writel(val, pcpidev->regs + pdata->interface_ctrl_reg);
+}
+
+static void imx_cpi_hw_config(struct imx_cpi_device *pcpidev,
+ const struct imx_cpi_pix_format *pcpidev_fmt)
+{
+ bool hsync_pol = pcpidev->flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH;
+ bool vsync_pol = pcpidev->flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH;
+ const struct imx_cpi_plat_data *pdata = pcpidev->pdata;
+ u32 val;
+
+ /* Software Reset */
+ imx_cpi_sw_reset(pcpidev);
+
+ /* Config PL Data Type */
+ val = IF_CTRL_REG_DATA_TYPE(DATA_TYPE_OUT_YUV444);
+ val |= IF_CTRL_REG_PL_ENABLE | IF_CTRL_REG_PL_VALID;
+ writel(val, pcpidev->regs + pdata->if_ctrl_reg);
+
+ /* Config CTRL REG */
+ val = CPI_CTRL_REG_HSYNC_FORCE_EN | CPI_CTRL_REG_VSYNC_FORCE_EN;
+
+ val |= CPI_CTRL_REG_DATA_TYPE_IN(pcpidev_fmt->data_type) |
+ FIELD_PREP(CPI_CTRL_REG_HSYNC_POL, hsync_pol) |
+ FIELD_PREP(CPI_CTRL_REG_VSYNC_POL, vsync_pol) |
+ FIELD_PREP(CPI_CTRL_REG_PIXEL_CLK_POL, 0) |
+ CPI_CTRL_REG_MASK_VSYNC_COUNTER(3) |
+ CPI_CTRL_REG_HSYNC_PULSE(2);
+
+ if (pcpidev_fmt->code == MEDIA_BUS_FMT_YUYV8_2X8 ||
+ pcpidev_fmt->code == MEDIA_BUS_FMT_UYVY8_2X8)
+ val |= CPI_CTRL_REG_UV_SWAP_EN;
+
+ if (pcpidev->mode == PI_GATE_CLOCK_MODE) {
+ val |= CPI_CTRL_REG_GCLK_MODE_EN;
+ } else if (pcpidev->mode == PI_CCIR_MODE) {
+ val |= (CPI_CTRL_REG_CCIR_EN |
+ CPI_CTRL_REG_CCIR_VSYNC_RESET_EN |
+ CPI_CTRL_REG_CCIR_EXT_VSYNC_EN |
+ CPI_CTRL_REG_CCIR_ECC_ERR_CORRECT_EN);
+ }
+
+ writel(val, pcpidev->regs + pdata->interface_ctrl_reg);
+}
+
+static void imx_cpi_config_ctrl_reg1(struct imx_cpi_device *pcpidev,
+ const struct v4l2_mbus_framefmt *format)
+{
+ const struct imx_cpi_plat_data *pdata = pcpidev->pdata;
+ u32 pixel_width;
+ u32 vsync_pulse;
+ u32 val;
+
+ pixel_width = format->width - 1;
+ vsync_pulse = format->width << 1;
+
+ val = CPI_CTRL_REG1_PIXEL_WIDTH(pixel_width) |
+ CPI_CTRL_REG1_VSYNC_PULSE(vsync_pulse);
+ writel(val, pcpidev->regs + pdata->interface_ctrl_reg1);
+}
+
+static void imx_cpi_enable(struct imx_cpi_device *pcpidev)
+{
+ const struct imx_cpi_plat_data *pdata = pcpidev->pdata;
+ u32 val;
+
+ /* Enable CPI */
+ val = readl(pcpidev->regs + pdata->interface_ctrl_reg);
+ val |= CPI_CTRL_REG_CPI_EN;
+ writel(val, pcpidev->regs + pdata->interface_ctrl_reg);
+
+ /* Disable SYNC Force */
+ val = readl(pcpidev->regs + pdata->interface_ctrl_reg);
+ val &= ~(CPI_CTRL_REG_HSYNC_FORCE_EN | CPI_CTRL_REG_VSYNC_FORCE_EN);
+ writel(val, pcpidev->regs + pdata->interface_ctrl_reg);
+}
+
+static void imx_cpi_disable(struct imx_cpi_device *pcpidev)
+{
+ const struct imx_cpi_plat_data *pdata = pcpidev->pdata;
+ u32 val;
+
+ /* Enable Sync Force */
+ val = readl(pcpidev->regs + pdata->interface_ctrl_reg);
+ val |= CPI_CTRL_REG_HSYNC_FORCE_EN | CPI_CTRL_REG_VSYNC_FORCE_EN;
+ writel(val, pcpidev->regs + pdata->interface_ctrl_reg);
+
+ /* Disable CPI */
+ val = readl(pcpidev->regs + pdata->interface_ctrl_reg);
+ val &= ~CPI_CTRL_REG_CPI_EN;
+ writel(val, pcpidev->regs + pdata->interface_ctrl_reg);
+
+ /* Disable Pixel Link */
+ val = readl(pcpidev->regs + pdata->if_ctrl_reg);
+ val &= ~(IF_CTRL_REG_PL_VALID | IF_CTRL_REG_PL_ENABLE);
+ writel(val, pcpidev->regs + pdata->if_ctrl_reg);
+}
+
+static struct imx_cpi_device *sd_to_imx_cpi_device(struct v4l2_subdev *sdev)
+{
+ return container_of(sdev, struct imx_cpi_device, sd);
+}
+
+static const struct media_entity_operations imx_cpi_entity_ops = {
+ .link_validate = v4l2_subdev_link_validate,
+ .get_fwnode_pad = v4l2_subdev_get_fwnode_pad_1_to_1,
+};
+
+static int imx_cpi_set_fmt(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *sd_state,
+ struct v4l2_subdev_format *sdformat)
+{
+ struct imx_cpi_pix_format const *pcpidev_fmt;
+ struct v4l2_mbus_framefmt *fmt;
+
+ /*
+ * The Parallel cpi can't transcode in any way, the source format
+ * can't be modified.
+ */
+ if (sdformat->pad == V4L2_SUBDEV_1TO1_PADS_SOURCE)
+ return v4l2_subdev_get_fmt(sd, sd_state, sdformat);
+
+ pcpidev_fmt = find_imx_cpi_format(sdformat->format.code);
+ if (!pcpidev_fmt)
+ pcpidev_fmt = &imx_cpi_formats[0];
+
+ fmt = v4l2_subdev_state_get_format(sd_state, sdformat->pad);
+
+ fmt->code = pcpidev_fmt->code;
+ fmt->width = sdformat->format.width;
+ fmt->height = sdformat->format.height;
+ fmt->field = V4L2_FIELD_NONE;
+ fmt->colorspace = sdformat->format.colorspace;
+ fmt->quantization = sdformat->format.quantization;
+ fmt->xfer_func = sdformat->format.xfer_func;
+ fmt->ycbcr_enc = sdformat->format.ycbcr_enc;
+
+ sdformat->format = *fmt;
+
+ /* Propagate the format from sink to source. */
+ fmt = v4l2_subdev_state_get_format(sd_state, V4L2_SUBDEV_1TO1_PADS_SOURCE);
+ *fmt = sdformat->format;
+
+ /* The format on the source pad might change due to unpacking. */
+ fmt->code = pcpidev_fmt->output;
+
+ return 0;
+}
+
+static int imx_cpi_init_state(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *state)
+{
+ struct v4l2_subdev_route routes[] = {
+ {
+ .sink_pad = V4L2_SUBDEV_1TO1_PADS_SINK,
+ .sink_stream = 0,
+ .source_pad = V4L2_SUBDEV_1TO1_PADS_SOURCE,
+ .source_stream = 0,
+ .flags = V4L2_SUBDEV_ROUTE_FL_ACTIVE,
+ },
+ };
+ struct v4l2_subdev_krouting routing = {
+ .len_routes = ARRAY_SIZE(routes),
+ .num_routes = ARRAY_SIZE(routes),
+ .routes = routes,
+ };
+ struct v4l2_mbus_framefmt *fmt;
+
+ fmt = v4l2_subdev_state_get_format(state, 0);
+
+ fmt->code = imx_cpi_formats[0].code;
+ fmt->width = 1920;
+ fmt->height = 1080;
+
+ fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
+ fmt->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt->colorspace);
+ fmt->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt->colorspace);
+ fmt->quantization = V4L2_MAP_QUANTIZATION_DEFAULT(false,
+ fmt->colorspace,
+ fmt->ycbcr_enc);
+
+ return v4l2_subdev_set_routing_with_fmt(sd, state, &routing, fmt);
+}
+
+static int imx_cpi_disable_streams(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *state, u32 pad,
+ u64 streams_mask)
+{
+ struct imx_cpi_device *pcpidev = sd_to_imx_cpi_device(sd);
+ struct media_pad *sink_pad, *remote_pad;
+ struct device *dev = pcpidev->dev;
+ struct v4l2_subdev *remote_sd;
+ u64 mask;
+ int ret;
+
+ sink_pad = &sd->entity.pads[V4L2_SUBDEV_1TO1_PADS_SINK];
+ remote_pad = media_pad_remote_pad_first(sink_pad);
+ remote_sd = media_entity_to_v4l2_subdev(remote_pad->entity);
+
+ mask = v4l2_subdev_state_xlate_streams(state, V4L2_SUBDEV_1TO1_PADS_SINK,
+ V4L2_SUBDEV_1TO1_PADS_SOURCE,
+ &streams_mask);
+
+ ret = v4l2_subdev_disable_streams(remote_sd, remote_pad->index, mask);
+ if (ret)
+ dev_err(dev, "failed to disable streams on remote subdev: %d\n", ret);
+
+ pcpidev->enabled_streams &= ~streams_mask;
+
+ if (!pcpidev->enabled_streams) {
+ imx_cpi_disable(pcpidev);
+ pm_runtime_put_autosuspend(dev);
+ }
+
+ return 0;
+}
+
+static int imx_cpi_enable_streams(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *state, u32 pad,
+ u64 streams_mask)
+{
+ struct imx_cpi_device *pcpidev = sd_to_imx_cpi_device(sd);
+ const struct imx_cpi_pix_format *pcpidev_fmt;
+ const struct v4l2_mbus_framefmt *format;
+ struct media_pad *sink_pad, *remote_pad;
+ struct device *dev = pcpidev->dev;
+ struct v4l2_subdev *remote_sd;
+ u64 mask;
+ int ret;
+
+ sink_pad = &sd->entity.pads[V4L2_SUBDEV_1TO1_PADS_SINK];
+ remote_pad = media_pad_remote_pad_first(sink_pad);
+ remote_sd = media_entity_to_v4l2_subdev(remote_pad->entity);
+
+ mask = v4l2_subdev_state_xlate_streams(state, V4L2_SUBDEV_1TO1_PADS_SINK,
+ V4L2_SUBDEV_1TO1_PADS_SOURCE,
+ &streams_mask);
+
+ format = v4l2_subdev_state_get_format(state, V4L2_SUBDEV_1TO1_PADS_SINK);
+ pcpidev_fmt = find_imx_cpi_format(format->code);
+
+ if (!pcpidev->enabled_streams) {
+ ret = pm_runtime_resume_and_get(dev);
+ if (ret)
+ return ret;
+
+ imx_cpi_hw_config(pcpidev, pcpidev_fmt);
+ imx_cpi_config_ctrl_reg1(pcpidev, format);
+ imx_cpi_enable(pcpidev);
+ }
+
+ ret = v4l2_subdev_enable_streams(remote_sd, remote_pad->index, mask);
+ if (ret)
+ goto err_cpi_stop;
+
+ pcpidev->enabled_streams |= streams_mask;
+
+ return 0;
+
+err_cpi_stop:
+ /* Stop CSI hardware if no streams are enabled */
+ if (!pcpidev->enabled_streams)
+ imx_cpi_disable(pcpidev);
+
+ pm_runtime_put_autosuspend(dev);
+
+ return ret;
+}
+
+static int imx_cpi_enum_mbus_code(struct v4l2_subdev *sd,
+ struct v4l2_subdev_state *sd_state,
+ struct v4l2_subdev_mbus_code_enum *code)
+{
+ /*
+ * The PARALLEL CPI can't transcode in any way, the source format
+ * is identical to the sink format.
+ */
+ if (code->pad == V4L2_SUBDEV_1TO1_PADS_SOURCE) {
+ struct v4l2_mbus_framefmt *fmt;
+
+ if (code->index > 0)
+ return -EINVAL;
+
+ fmt = v4l2_subdev_state_get_format(sd_state, code->pad);
+ code->code = fmt->code;
+ return 0;
+ }
+
+ if (code->pad != V4L2_SUBDEV_1TO1_PADS_SINK)
+ return -EINVAL;
+
+ if (code->index >= ARRAY_SIZE(imx_cpi_formats))
+ return -EINVAL;
+
+ code->code = imx_cpi_formats[code->index].code;
+
+ return 0;
+}
+
+static int imx_cpi_set_pad_by_ep(struct v4l2_subdev *sd, struct media_pad *pad,
+ struct v4l2_fwnode_endpoint *vep)
+{
+ if (vep->base.port == V4L2_SUBDEV_1TO1_PADS_SINK) {
+ struct imx_cpi_device *pcpidev = sd_to_imx_cpi_device(sd);
+
+ pcpidev->flags = vep->bus.parallel.flags;
+
+ if (vep->bus_type != V4L2_MBUS_PARALLEL)
+ return -EINVAL;
+
+ pad->flags = MEDIA_PAD_FL_SINK | MEDIA_PAD_FL_MUST_CONNECT;
+
+ return 0;
+ }
+
+ if (vep->base.port == V4L2_SUBDEV_1TO1_PADS_SOURCE) {
+ /* Source port */
+ pad->flags = MEDIA_PAD_FL_SOURCE | MEDIA_PAD_FL_MUST_CONNECT;
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+static const struct v4l2_subdev_video_ops imx_cpi_video_ops = {
+ .s_stream = v4l2_subdev_s_stream_helper,
+};
+
+static const struct v4l2_subdev_pad_ops imx_cpi_pad_ops = {
+ .enum_mbus_code = imx_cpi_enum_mbus_code,
+ .get_fmt = v4l2_subdev_get_fmt,
+ .set_fmt = imx_cpi_set_fmt,
+ .get_frame_desc = v4l2_subdev_get_frame_desc_passthrough,
+ .enable_streams = imx_cpi_enable_streams,
+ .disable_streams = imx_cpi_disable_streams,
+};
+
+static const struct v4l2_subdev_ops imx_cpi_subdev_ops = {
+ .pad = &imx_cpi_pad_ops,
+ .video = &imx_cpi_video_ops,
+};
+
+static const struct v4l2_subdev_internal_ops imx_cpi_internal_ops = {
+ .init_state = imx_cpi_init_state,
+ .set_pad_by_ep = imx_cpi_set_pad_by_ep,
+};
+
+/* ----------------------------------------------------------------------
+ * Suspend/resume
+ */
+
+static int imx_cpi_runtime_suspend(struct device *dev)
+{
+ struct imx_cpi_device *pcpidev = dev_get_drvdata(dev);
+
+ clk_bulk_disable_unprepare(pcpidev->num_clks, pcpidev->clks);
+
+ return 0;
+}
+
+static int imx_cpi_runtime_resume(struct device *dev)
+{
+ struct imx_cpi_device *pcpidev = dev_get_drvdata(dev);
+
+ return clk_bulk_prepare_enable(pcpidev->num_clks, pcpidev->clks);
+}
+
+static const struct dev_pm_ops imx_cpi_pm_ops = {
+ RUNTIME_PM_OPS(imx_cpi_runtime_suspend, imx_cpi_runtime_resume, NULL)
+};
+
+static void imx_cpi_remove(struct platform_device *pdev)
+{
+ struct imx_cpi_device *pcpidev = platform_get_drvdata(pdev);
+
+ media_async_subdev_cleanup(&pcpidev->sd);
+}
+
+static int imx_cpi_probe(struct platform_device *pdev)
+{
+ struct imx_cpi_device *pcpidev;
+ struct device *dev = &pdev->dev;
+ struct v4l2_subdev *sd;
+ int ret;
+
+ pcpidev = devm_kzalloc(dev, sizeof(*pcpidev), GFP_KERNEL);
+ if (!pcpidev)
+ return -ENOMEM;
+
+ pcpidev->dev = dev;
+ platform_set_drvdata(pdev, pcpidev);
+
+ pcpidev->pdata = of_device_get_match_data(dev);
+ pcpidev->mode = PI_GATE_CLOCK_MODE;
+
+ pcpidev->regs = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(pcpidev->regs))
+ return dev_err_probe(dev, PTR_ERR(pcpidev->regs),
+ "Failed to get regs\n");
+
+ pcpidev->num_clks = devm_clk_bulk_get_all(dev, &pcpidev->clks);
+ if (pcpidev->num_clks < 0)
+ return pcpidev->num_clks;
+
+ sd = &pcpidev->sd;
+
+ v4l2_subdev_init(sd, &imx_cpi_subdev_ops);
+
+ sd->internal_ops = &imx_cpi_internal_ops;
+ snprintf(sd->name, sizeof(sd->name), "parallel-%s",
+ dev_name(pcpidev->dev));
+
+ sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
+
+ sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
+ sd->entity.ops = &imx_cpi_entity_ops;
+
+ sd->dev = pcpidev->dev;
+
+ pm_runtime_use_autosuspend(dev);
+ ret = devm_pm_runtime_enable(dev);
+ if (ret)
+ return ret;
+
+ return media_async_register_subdev(sd);
+}
+
+static const struct of_device_id imx_cpi_of_match[] = {
+ { .compatible = "fsl,imx8qxp-pcif", .data = &imx8qxp_pdata },
+ { },
+};
+
+MODULE_DEVICE_TABLE(of, imx_cpi_of_match);
+
+static struct platform_driver imx_cpi_driver = {
+ .probe = imx_cpi_probe,
+ .remove = imx_cpi_remove,
+ .driver = {
+ .of_match_table = imx_cpi_of_match,
+ .name = "imx-parallel-cpi",
+ .pm = pm_ptr(&imx_cpi_pm_ops),
+ },
+};
+
+module_platform_driver(imx_cpi_driver);
+
+MODULE_DESCRIPTION("i.MX9 Parallel CPI receiver driver");
+MODULE_LICENSE("GPL");
--
2.43.0
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