* [PATCH v7 07/16] arm64: dts: st: add ltdc pins for stm32mp25
From: Dario Binacchi @ 2026-07-03 6:48 UTC (permalink / raw)
To: linux-kernel
Cc: michael, linux-amarula, francesco.utel, domenico.acri,
Dario Binacchi, Alexandre Torgue, Conor Dooley,
Krzysztof Kozlowski, Maxime Coquelin, Rob Herring, devicetree,
linux-arm-kernel, linux-stm32
In-Reply-To: <20260703065110.1433283-1-dario.binacchi@amarulasolutions.com>
Add the LTDC pins used on MicroGEA-STM32MP257-RMM board.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---
(no changes since v5)
Changes in v5:
- Increase slew-rate to <1> to support the 27 MHz pixel clock and
prevent timing violations. Suggested by Sashiko
arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 71 +++++++++++++++++++
1 file changed, 71 insertions(+)
diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
index db485b9ed904..50f454630cf2 100644
--- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
@@ -260,6 +260,77 @@ pins {
};
};
+ /omit-if-no-ref/
+ ltdc_pins_a: ltdc-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 6, AF14)>, /* LCD_CLK */
+ <STM32_PINMUX('G', 2, AF13)>, /* LCD_HSYNC */
+ <STM32_PINMUX('G', 1, AF13)>, /* LCD_VSYNC */
+ <STM32_PINMUX('C', 5, AF14)>, /* LCD_DE */
+ <STM32_PINMUX('H', 4, AF10)>, /* LCD_R0 */
+ <STM32_PINMUX('F', 7, AF13)>, /* LCD_R1 */
+ <STM32_PINMUX('C', 11, AF13)>, /* LCD_R2 */
+ <STM32_PINMUX('A', 1, AF11)>, /* LCD_R3 */
+ <STM32_PINMUX('B', 15, AF13)>, /* LCD_R4 */
+ <STM32_PINMUX('G', 3, AF13)>, /* LCD_R5 */
+ <STM32_PINMUX('A', 10, AF12)>, /* LCD_R6 */
+ <STM32_PINMUX('G', 7, AF13)>, /* LCD_R7 */
+ <STM32_PINMUX('F', 8, AF13)>, /* LCD_G0 */
+ <STM32_PINMUX('H', 5, AF10)>, /* LCD_G1 */
+ <STM32_PINMUX('C', 9, AF13)>, /* LCD_G2 */
+ <STM32_PINMUX('C', 10, AF13)>, /* LCD_G3 */
+ <STM32_PINMUX('A', 6, AF10)>, /* LCD_G4 */
+ <STM32_PINMUX('G', 11, AF13)>, /* LCD_G5 */
+ <STM32_PINMUX('G', 12, AF13)>, /* LCD_G6 */
+ <STM32_PINMUX('A', 9, AF12)>, /* LCD_G7 */
+ <STM32_PINMUX('F', 6, AF13)>, /* LCD_B0 */
+ <STM32_PINMUX('A', 3, AF11)>, /* LCD_B1 */
+ <STM32_PINMUX('G', 15, AF13)>, /* LCD_B2 */
+ <STM32_PINMUX('I', 0, AF13)>, /* LCD_B3 */
+ <STM32_PINMUX('I', 1, AF13)>, /* LCD_B4 */
+ <STM32_PINMUX('A', 7, AF10)>, /* LCD_B5 */
+ <STM32_PINMUX('F', 5, AF13)>, /* LCD_B6 */
+ <STM32_PINMUX('I', 4, AF13)>; /* LCD_B7 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ };
+
+ /omit-if-no-ref/
+ ltdc_sleep_pins_a: ltdc-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 6, ANALOG)>, /* LCD_CLK */
+ <STM32_PINMUX('G', 2, ANALOG)>, /* LCD_HSYNC */
+ <STM32_PINMUX('G', 1, ANALOG)>, /* LCD_VSYNC */
+ <STM32_PINMUX('C', 5, ANALOG)>, /* LCD_DE */
+ <STM32_PINMUX('H', 4, ANALOG)>, /* LCD_R0 */
+ <STM32_PINMUX('F', 7, ANALOG)>, /* LCD_R1 */
+ <STM32_PINMUX('C', 11, ANALOG)>, /* LCD_R2 */
+ <STM32_PINMUX('A', 1, ANALOG)>, /* LCD_R3 */
+ <STM32_PINMUX('B', 15, ANALOG)>, /* LCD_R4 */
+ <STM32_PINMUX('G', 3, ANALOG)>, /* LCD_R5 */
+ <STM32_PINMUX('A', 10, ANALOG)>, /* LCD_R6 */
+ <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_R7 */
+ <STM32_PINMUX('F', 8, ANALOG)>, /* LCD_G0 */
+ <STM32_PINMUX('H', 5, ANALOG)>, /* LCD_G1 */
+ <STM32_PINMUX('C', 9, ANALOG)>, /* LCD_G2 */
+ <STM32_PINMUX('C', 10, ANALOG)>, /* LCD_G3 */
+ <STM32_PINMUX('A', 6, ANALOG)>, /* LCD_G4 */
+ <STM32_PINMUX('G', 11, ANALOG)>, /* LCD_G5 */
+ <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_G6 */
+ <STM32_PINMUX('A', 9, ANALOG)>, /* LCD_G7 */
+ <STM32_PINMUX('F', 6, ANALOG)>, /* LCD_B0 */
+ <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B1 */
+ <STM32_PINMUX('G', 15, ANALOG)>, /* LCD_B2 */
+ <STM32_PINMUX('I', 0, ANALOG)>, /* LCD_B3 */
+ <STM32_PINMUX('I', 1, ANALOG)>, /* LCD_B4 */
+ <STM32_PINMUX('A', 7, ANALOG)>, /* LCD_B5 */
+ <STM32_PINMUX('F', 5, ANALOG)>, /* LCD_B6 */
+ <STM32_PINMUX('I', 4, ANALOG)>; /* LCD_B7 */
+ };
+ };
+
/omit-if-no-ref/
ospi_port1_clk_pins_a: ospi-port1-clk-0 {
pins {
--
2.43.0
^ permalink raw reply related
* [PATCH v7 08/16] arm64: dts: st: add can1 pins for stm32mp25
From: Dario Binacchi @ 2026-07-03 6:48 UTC (permalink / raw)
To: linux-kernel
Cc: michael, linux-amarula, francesco.utel, domenico.acri,
Dario Binacchi, Alexandre Torgue, Conor Dooley,
Krzysztof Kozlowski, Maxime Coquelin, Rob Herring, devicetree,
linux-arm-kernel, linux-stm32
In-Reply-To: <20260703065110.1433283-1-dario.binacchi@amarulasolutions.com>
Add the can1 pins used on MicroGEA-STM32MP257-RMM board.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---
(no changes since v1)
arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 22 +++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
index 50f454630cf2..6482dd47e977 100644
--- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
@@ -331,6 +331,28 @@ pins {
};
};
+ /omit-if-no-ref/
+ m_can1_pins_a: m-can1-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 9, AF7)>; /* CAN1_TX */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 11, AF7)>; /* CAN1_RX */
+ bias-disable;
+ };
+ };
+
+ /omit-if-no-ref/
+ m_can1_sleep_pins_a: m-can1-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 9, ANALOG)>, /* CAN1_TX */
+ <STM32_PINMUX('B', 11, ANALOG)>; /* CAN1_RX */
+ };
+ };
+
/omit-if-no-ref/
ospi_port1_clk_pins_a: ospi-port1-clk-0 {
pins {
--
2.43.0
^ permalink raw reply related
* [PATCH v7 09/16] arm64: dts: st: add pwm2/pwm4 pins for stm32mp25
From: Dario Binacchi @ 2026-07-03 6:48 UTC (permalink / raw)
To: linux-kernel
Cc: michael, linux-amarula, francesco.utel, domenico.acri,
Dario Binacchi, Alexandre Torgue, Conor Dooley,
Krzysztof Kozlowski, Maxime Coquelin, Rob Herring, devicetree,
linux-arm-kernel, linux-stm32
In-Reply-To: <20260703065110.1433283-1-dario.binacchi@amarulasolutions.com>
Add the pwm2 and pwm4 pins used on MicroGEA-STM32MP257-RMM board.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---
(no changes since v1)
arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 34 +++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
index 6482dd47e977..695c9d771853 100644
--- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
@@ -433,6 +433,23 @@ pins {
};
};
+ /omit-if-no-ref/
+ pwm2_pins_a: pwm2-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 7, AF7)>; /* TIM2_CH1 */
+ bias-pull-down;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ /omit-if-no-ref/
+ pwm2_sleep_pins_a: pwm2-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('I', 7, ANALOG)>; /* TIM2_CH1 */
+ };
+ };
+
/omit-if-no-ref/
pwm3_pins_a: pwm3-0 {
pins {
@@ -450,6 +467,23 @@ pins {
};
};
+ /omit-if-no-ref/
+ pwm4_pins_a: pwm4-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 12, AF7)>; /* TIM4_CH1 */
+ bias-pull-down;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ /omit-if-no-ref/
+ pwm4_sleep_pins_a: pwm4-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('A', 12, ANALOG)>; /* TIM4_CH1 */
+ };
+ };
+
/omit-if-no-ref/
pwm8_pins_a: pwm8-0 {
pins {
--
2.43.0
^ permalink raw reply related
* [PATCH v7 10/16] arm64: dts: st: add sai1 pins for stm32mp25
From: Dario Binacchi @ 2026-07-03 6:49 UTC (permalink / raw)
To: linux-kernel
Cc: michael, linux-amarula, francesco.utel, domenico.acri,
Dario Binacchi, Olivier Moysan, Alexandre Torgue, Conor Dooley,
Krzysztof Kozlowski, Maxime Coquelin, Rob Herring, devicetree,
linux-arm-kernel, linux-stm32
In-Reply-To: <20260703065110.1433283-1-dario.binacchi@amarulasolutions.com>
Add the sai1 pins used on MicroGEA-STM32MP257-RMM board.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Olivier Moysan <olivier.moysan@foss.st.com>
---
Changes in v7:
- Add Reviewed-by tag of Olivier Moysan
arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 45 +++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
index 695c9d771853..002fbc724b9d 100644
--- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
@@ -520,6 +520,51 @@ pins {
};
};
+ /omit-if-no-ref/
+ sai1a_pins_a: sai1a-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('D', 9, AF3)>, /* SAI1_SD_A */
+ <STM32_PINMUX('D', 8, AF3)>, /* SAI1_FS_A */
+ <STM32_PINMUX('D', 10, AF3)>; /* SAI1_SCK_A */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 11, AF3)>; /* SAI1_MCLK_A */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ /omit-if-no-ref/
+ sai1a_sleep_pins_a: sai1a-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 9, ANALOG)>, /* SAI1_SD_A */
+ <STM32_PINMUX('D', 8, ANALOG)>, /* SAI1_FS_A */
+ <STM32_PINMUX('D', 10, ANALOG)>, /* SAI1_SCK_A */
+ <STM32_PINMUX('D', 11, ANALOG)>; /* SAI1_MCLK_A */
+ };
+ };
+
+ /omit-if-no-ref/
+ sai1b_pins_a: sai1b-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 4, AF4)>; /* SAI1_SD_B */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ };
+
+ /omit-if-no-ref/
+ sai1b_sleep_pins_a: sai1b-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('D', 4, ANALOG)>; /* SAI1_SD_B */
+ };
+ };
+
/omit-if-no-ref/
sdmmc1_b4_pins_a: sdmmc1-b4-0 {
pins1 {
--
2.43.0
^ permalink raw reply related
* [PATCH v7 11/16] arm64: dts: st: add sdmmc2 pins for stm32mp25
From: Dario Binacchi @ 2026-07-03 6:49 UTC (permalink / raw)
To: linux-kernel
Cc: michael, linux-amarula, francesco.utel, domenico.acri,
Dario Binacchi, Alexandre Torgue, Conor Dooley,
Krzysztof Kozlowski, Maxime Coquelin, Rob Herring, devicetree,
linux-arm-kernel, linux-stm32
In-Reply-To: <20260703065110.1433283-1-dario.binacchi@amarulasolutions.com>
Add the sdmmc2 pins used on MicroGEA-STM32MP257-RMM board.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---
(no changes since v5)
Changes in v5:
- Change SDMMC2_CK pin bias from pull-up to bias-disable to
avoid signal integrity issues on the clock line. Suggested by Sashiko
arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 80 +++++++++++++++++++
1 file changed, 80 insertions(+)
diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
index 002fbc724b9d..c816a6aece47 100644
--- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
@@ -622,6 +622,86 @@ pins {
};
};
+ /omit-if-no-ref/
+ sdmmc2_b4_pins_a: sdmmc2-b4-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('E', 13, AF12)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('E', 11, AF12)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('E', 8, AF12)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('E', 12, AF12)>, /* SDMMC2_D3 */
+ <STM32_PINMUX('E', 15, AF12)>; /* SDMMC2_CMD */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('E', 14, AF12)>; /* SDMMC2_CK */
+ slew-rate = <2>;
+ drive-push-pull;
+ bias-disable;
+ };
+ };
+
+ /omit-if-no-ref/
+ sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('E', 13, AF12)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('E', 11, AF12)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('E', 8, AF12)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('E', 12, AF12)>; /* SDMMC2_D3 */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('E', 14, AF12)>; /* SDMMC2_CK */
+ slew-rate = <2>;
+ drive-push-pull;
+ bias-disable;
+ };
+ pins3 {
+ pinmux = <STM32_PINMUX('E', 15, AF12)>; /* SDMMC2_CMD */
+ slew-rate = <1>;
+ drive-open-drain;
+ bias-pull-up;
+ };
+ };
+
+ /omit-if-no-ref/
+ sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 13, ANALOG)>, /* SDMMC2_D0 */
+ <STM32_PINMUX('E', 11, ANALOG)>, /* SDMMC2_D1 */
+ <STM32_PINMUX('E', 8, ANALOG)>, /* SDMMC2_D2 */
+ <STM32_PINMUX('E', 12, ANALOG)>, /* SDMMC2_D3 */
+ <STM32_PINMUX('E', 14, ANALOG)>, /* SDMMC2_CK */
+ <STM32_PINMUX('E', 15, ANALOG)>; /* SDMMC2_CMD */
+ };
+ };
+
+ /omit-if-no-ref/
+ sdmmc2_d47_pins_a: sdmmc2-d47-0 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 10, AF12)>, /* SDMMC2_D4 */
+ <STM32_PINMUX('E', 9, AF12)>, /* SDMMC2_D5 */
+ <STM32_PINMUX('E', 6, AF12)>, /* SDMMC2_D6 */
+ <STM32_PINMUX('E', 7, AF12)>; /* SDMMC2_D7 */
+ slew-rate = <1>;
+ drive-push-pull;
+ bias-pull-up;
+ };
+ };
+
+ /omit-if-no-ref/
+ sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 {
+ pins {
+ pinmux = <STM32_PINMUX('E', 10, ANALOG)>, /* SDMMC2_D4 */
+ <STM32_PINMUX('E', 9, ANALOG)>, /* SDMMC2_D5 */
+ <STM32_PINMUX('E', 6, ANALOG)>, /* SDMMC2_D6 */
+ <STM32_PINMUX('E', 7, ANALOG)>; /* SDMMC2_D7 */
+ };
+ };
+
/omit-if-no-ref/
spi3_pins_a: spi3-0 {
pins1 {
--
2.43.0
^ permalink raw reply related
* [PATCH v7 12/16] arm64: dts: st: add spi1 pins for stm32mp25
From: Dario Binacchi @ 2026-07-03 6:49 UTC (permalink / raw)
To: linux-kernel
Cc: michael, linux-amarula, francesco.utel, domenico.acri,
Dario Binacchi, Alexandre Torgue, Conor Dooley,
Krzysztof Kozlowski, Maxime Coquelin, Rob Herring, devicetree,
linux-arm-kernel, linux-stm32
In-Reply-To: <20260703065110.1433283-1-dario.binacchi@amarulasolutions.com>
Add the spi1 pins used on MicroGEA-STM32MP257-RMM board.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---
(no changes since v1)
arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 24 +++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
index c816a6aece47..4e570e2e5157 100644
--- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
@@ -702,6 +702,30 @@ pins {
};
};
+ /omit-if-no-ref/
+ spi1_pins_a: spi1-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 6, AF3)>, /* SPI1_SCK */
+ <STM32_PINMUX('I', 5, AF3)>; /* SPI1_MOSI */
+ drive-push-pull;
+ bias-disable;
+ slew-rate = <1>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('F', 12, AF3)>; /* SPI1_MISO */
+ bias-disable;
+ };
+ };
+
+ /omit-if-no-ref/
+ spi1_sleep_pins_a: spi1-sleep-0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 6, ANALOG)>, /* SPI1_SCK */
+ <STM32_PINMUX('I', 5, ANALOG)>, /* SPI1_MOSI */
+ <STM32_PINMUX('F', 12, ANALOG)>; /* SPI1_MISO */
+ };
+ };
+
/omit-if-no-ref/
spi3_pins_a: spi3-0 {
pins1 {
--
2.43.0
^ permalink raw reply related
* [PATCH v7 13/16] arm64: dts: st: add usart1 pins for stm32mp25
From: Dario Binacchi @ 2026-07-03 6:49 UTC (permalink / raw)
To: linux-kernel
Cc: michael, linux-amarula, francesco.utel, domenico.acri,
Dario Binacchi, Alexandre Torgue, Conor Dooley,
Krzysztof Kozlowski, Maxime Coquelin, Rob Herring, devicetree,
linux-arm-kernel, linux-stm32
In-Reply-To: <20260703065110.1433283-1-dario.binacchi@amarulasolutions.com>
Add the usart1 pins used on MicroGEA-STM32MP257-RMM board.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---
(no changes since v1)
arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 33 +++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
index 4e570e2e5157..d515e44832d7 100644
--- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
@@ -766,6 +766,39 @@ pins {
};
};
+ /omit-if-no-ref/
+ usart1_pins_b: usart1-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 8, AF6)>; /* USART1_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 10, AF6)>; /* USART1_RX */
+ bias-disable;
+ };
+ };
+
+ /omit-if-no-ref/
+ usart1_idle_pins_b: usart1-idle-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('B', 8, ANALOG)>; /* USART1_TX */
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 10, AF6)>; /* USART1_RX */
+ bias-disable;
+ };
+ };
+
+ /omit-if-no-ref/
+ usart1_sleep_pins_b: usart1-sleep-1 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 8, ANALOG)>, /* USART1_TX */
+ <STM32_PINMUX('B', 10, ANALOG)>; /* USART1_RX */
+ };
+ };
+
/omit-if-no-ref/
usart2_pins_a: usart2-0 {
pins1 {
--
2.43.0
^ permalink raw reply related
* [PATCH v7 14/16] arm64: dts: st: support Engicam MicroGEA-STM32MP257 SoM
From: Dario Binacchi @ 2026-07-03 6:49 UTC (permalink / raw)
To: linux-kernel
Cc: michael, linux-amarula, francesco.utel, domenico.acri,
Dario Binacchi, Alexandre Torgue, Conor Dooley,
Krzysztof Kozlowski, Maxime Coquelin, Rob Herring, devicetree,
linux-arm-kernel, linux-stm32
In-Reply-To: <20260703065110.1433283-1-dario.binacchi@amarulasolutions.com>
Support Engicam MicroGEA-STM32MP257 SoM with:
- 8 GB eMMC Flash
- 2 GB LPDDR4 DRAM
The SoM also provides an Ethernet MAC, but Ethernet support is not
enabled at this stage due to a known silicon limitation documented in
[1].
This corresponds to section 2.21.2 ("ETH1 RMII mode could have CRC
errors"), where CRC errors may occur in ETH1 RMII direct mode when
directly connected to I/Os.
The workaround requires use of the Ethernet switch (ETHSW), which
introduces additional DT bindings and topology complexity. This is
intended to be addressed in a separate patch series.
[1] https://www.st.com/resource/en/errata_sheet/es0598-stm32mp23xx25xx-device-errata-stmicroelectronics.pdf
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---
(no changes since v4)
Changes in v4:
- Drop inclusion of stm32mp25xf.dtsi, we are using stm32mp257d.
Changes in v3:
- Fix a typo in the URL
.../dts/st/stm32mp257-engicam-microgea.dtsi | 63 +++++++++++++++++++
1 file changed, 63 insertions(+)
create mode 100644 arch/arm64/boot/dts/st/stm32mp257-engicam-microgea.dtsi
diff --git a/arch/arm64/boot/dts/st/stm32mp257-engicam-microgea.dtsi b/arch/arm64/boot/dts/st/stm32mp257-engicam-microgea.dtsi
new file mode 100644
index 000000000000..5b4287e86def
--- /dev/null
+++ b/arch/arm64/boot/dts/st/stm32mp257-engicam-microgea.dtsi
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2026 Amarula Solutions, Dario Binacchi <dario.binacchi@amarulasolutions.com>
+ * Copyright (C) 2026 Engicam srl
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/regulator/st,stm32mp25-regulator.h>
+#include "stm32mp257.dtsi"
+#include "stm32mp25-pinctrl.dtsi"
+#include "stm32mp25xxai-pinctrl.dtsi"
+
+/ {
+ model = "Engicam MicroGEA STM32MP257 SoM";
+ compatible = "engicam,microgea-stm32mp257", "st,stm32mp257";
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0x80000000>;
+ };
+};
+
+&scmi_regu {
+ scmi_vddio1: regulator@0 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+ scmi_vddcore: regulator@b {
+ reg = <VOLTD_SCMI_STPMIC2_BUCK2>;
+ regulator-name = "vddcore";
+ };
+ scmi_v1v8: regulator@e {
+ reg = <VOLTD_SCMI_STPMIC2_BUCK5>;
+ regulator-name = "v1v8";
+ };
+ scmi_v3v3: regulator@10 {
+ reg = <VOLTD_SCMI_STPMIC2_BUCK7>;
+ regulator-name = "v3v3";
+ };
+ scmi_vdd3v3_usb: regulator@14 {
+ reg = <VOLTD_SCMI_STPMIC2_LDO4>;
+ regulator-name = "vdd3v3_usb";
+ };
+};
+
+/* eMMC */
+&sdmmc2 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>;
+ pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a>;
+ pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>;
+ non-removable;
+ no-sd;
+ no-sdio;
+ st,neg-edge;
+ bus-width = <8>;
+ vmmc-supply = <&scmi_v3v3>;
+ vqmmc-supply = <&scmi_vddio2>;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ status = "okay";
+};
--
2.43.0
^ permalink raw reply related
* [PATCH v7 15/16] arm64: dts: st: support Engicam MicroGEA-STM32MP257-RMM board
From: Dario Binacchi @ 2026-07-03 6:49 UTC (permalink / raw)
To: linux-kernel
Cc: michael, linux-amarula, francesco.utel, domenico.acri,
Dario Binacchi, Alexandre Torgue, Conor Dooley,
Krzysztof Kozlowski, Maxime Coquelin, Rob Herring, devicetree,
linux-arm-kernel, linux-stm32
In-Reply-To: <20260703065110.1433283-1-dario.binacchi@amarulasolutions.com>
Support for Engicam MicroGEA-STM32MP257-RMM board with:
- 8 GB eMMC Flash
- 2 GB LPDDR4 DRAM
- CAN
- LEDs
- LCD panel with touchscreen
- Micro SD card connector
- Audio codec
- Buzzer
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---
(no changes since v5)
Changes in v5:
- Fix touchscreen resolution to 480x854
- Fix SPI1 CS0 polarity to GPIO_ACTIVE_LOW
Changes in v2:
- Drop the clocks property from the sai1 node in stm32mp257-engicam-microgea-rmm.dts
to avoid overriding the peripheral bus clock reference defined in the base
SoC device tree. Suggested by Sashiko.
- Reference the existing labeled nodes directly at the root level using
&sai1a and &sai1b in stm32mp257-engicam-microgea-rmm.dts instead of
redefining the entire node structure and redeclaring the labels. Suggested by Sashiko.
- Drop the #clock-cells property from sai1a and remove the reference to sai1a from
the clocks array in sai1b, relying strictly on the st,sync property to handle
internal synchronization.
arch/arm64/boot/dts/st/Makefile | 1 +
.../st/stm32mp257-engicam-microgea-rmm.dts | 319 ++++++++++++++++++
2 files changed, 320 insertions(+)
create mode 100644 arch/arm64/boot/dts/st/stm32mp257-engicam-microgea-rmm.dts
diff --git a/arch/arm64/boot/dts/st/Makefile b/arch/arm64/boot/dts/st/Makefile
index 63908113ae36..386eca593c54 100644
--- a/arch/arm64/boot/dts/st/Makefile
+++ b/arch/arm64/boot/dts/st/Makefile
@@ -2,5 +2,6 @@
dtb-$(CONFIG_ARCH_STM32) += \
stm32mp215f-dk.dtb \
stm32mp235f-dk.dtb \
+ stm32mp257-engicam-microgea-rmm.dtb \
stm32mp257f-dk.dtb \
stm32mp257f-ev1.dtb
diff --git a/arch/arm64/boot/dts/st/stm32mp257-engicam-microgea-rmm.dts b/arch/arm64/boot/dts/st/stm32mp257-engicam-microgea-rmm.dts
new file mode 100644
index 000000000000..3aea0c2f6651
--- /dev/null
+++ b/arch/arm64/boot/dts/st/stm32mp257-engicam-microgea-rmm.dts
@@ -0,0 +1,319 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2026 Amarula Solutions, Dario Binacchi <dario.binacchi@amarulasolutions.com>
+ * Copyright (C) 2026 Engicam srl
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+
+#include "stm32mp257-engicam-microgea.dtsi"
+
+/ {
+ model = "Engicam MicroGEA STM32MP257D RMM Board";
+ compatible = "engicam,microgea-stm32mp257-rmm",
+ "engicam,microgea-stm32mp257", "st,stm32mp257";
+
+ aliases {
+ mmc0 = &sdmmc1;
+ mmc1 = &sdmmc2;
+ serial0 = &usart2;
+ serial1 = &usart1;
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ brightness-levels = <0 100>;
+ num-interpolated-steps = <100>;
+ default-brightness-level = <85>;
+ pwms = <&pwm2 0 100000 0>;
+ };
+
+ buzzer {
+ compatible = "pwm-beeper";
+ pwms = <&pwm4 0 1000000 0>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ framebuffer {
+ compatible = "simple-framebuffer";
+ clocks = <&rcc CK_BUS_LTDC>, <&rcc CK_KER_LTDC>;
+ lcd-supply = <®_3v3>;
+ status = "disabled";
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-0 {
+ gpios = <&gpioh 2 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ status = "okay";
+ };
+
+ led-1 {
+ gpios = <&gpioh 6 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ status = "okay";
+ };
+ };
+
+ mclk: clock-mclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+
+ reg_1v8: regulator-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "1v8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_ext_pwr: regulator-ext-pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "ext-pwr";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpiog 0 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ regulator-always-on;
+ };
+
+ sound {
+ compatible = "audio-graph-card";
+ label = "STM32MP25-RMM";
+ widgets = "Headphone", "Headphone Jack",
+ "Microphone", "Microphone Jack";
+ routing = "Headphone Jack", "HP_OUT",
+ "MIC_IN", "Microphone Jack",
+ "Microphone Jack", "Mic Bias";
+ dais = <&sai1a_port &sai1b_port>;
+ status = "okay";
+ };
+};
+
+&arm_wdt {
+ timeout-sec = <32>;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c1_pins_a>;
+ pinctrl-1 = <&i2c1_sleep_pins_a>;
+ i2c-scl-rising-time-ns = <185>;
+ i2c-scl-falling-time-ns = <20>;
+ status = "okay";
+ /* spare dmas for other usage */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+
+ touchscreen@38 {
+ compatible = "edt,edt-ft5306";
+ reg = <0x38>;
+ interrupt-parent = <&gpiob>;
+ interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&gpiod 1 GPIO_ACTIVE_LOW>;
+ touchscreen-size-x = <480>;
+ touchscreen-size-y = <854>;
+ };
+};
+
+&i2c2 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c2_pins_a>;
+ pinctrl-1 = <&i2c2_sleep_pins_a>;
+ i2c-scl-rising-time-ns = <185>;
+ i2c-scl-falling-time-ns = <20>;
+ status = "okay";
+ /* spare dmas for other usage */
+ /delete-property/dmas;
+ /delete-property/dma-names;
+
+ sgtl5000: codec@a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ #sound-dai-cells = <0>;
+ clocks = <&mclk>;
+
+ VDDA-supply = <®_3v3>;
+ VDDIO-supply = <®_3v3>;
+ VDDD-supply = <®_1v8>;
+
+ sgtl5000_port: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sgtl5000_tx_endpoint: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&sai1a_endpoint>;
+ frame-master = <&sgtl5000_tx_endpoint>;
+ bitclock-master = <&sgtl5000_tx_endpoint>;
+ };
+
+ sgtl5000_rx_endpoint: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&sai1b_endpoint>;
+ frame-master = <&sgtl5000_rx_endpoint>;
+ bitclock-master = <&sgtl5000_rx_endpoint>;
+ };
+ };
+ };
+};
+
+<dc {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <<dc_pins_a>;
+ pinctrl-1 = <<dc_sleep_pins_a>;
+ status = "okay";
+
+ port {
+ ltdc_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+};
+
+&m_can1 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&m_can1_pins_a>;
+ pinctrl-1 = <&m_can1_sleep_pins_a>;
+ status = "okay";
+};
+
+&sai1 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&sai1a_pins_a>, <&sai1b_pins_a>;
+ pinctrl-1 = <&sai1a_sleep_pins_a>, <&sai1b_sleep_pins_a>;
+ status = "okay";
+};
+
+&sai1a {
+ dma-names = "tx";
+ status = "okay";
+
+ sai1a_port: port {
+ sai1a_endpoint: endpoint {
+ remote-endpoint = <&sgtl5000_tx_endpoint>;
+ dai-format = "i2s";
+ mclk-fs = <512>;
+ };
+ };
+};
+
+&sai1b {
+ dma-names = "rx";
+ st,sync = <&sai1a 2>;
+ clocks = <&rcc CK_KER_SAI1>;
+ clock-names = "sai_ck";
+ status = "okay";
+
+ sai1b_port: port {
+ sai1b_endpoint: endpoint {
+ remote-endpoint = <&sgtl5000_rx_endpoint>;
+ dai-format = "i2s";
+ mclk-fs = <512>;
+ };
+ };
+};
+
+/* MicroSD */
+&sdmmc1 {
+ pinctrl-names = "default", "opendrain", "sleep";
+ pinctrl-0 = <&sdmmc1_b4_pins_a>;
+ pinctrl-1 = <&sdmmc1_b4_od_pins_a>;
+ pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>;
+ broken-cd;
+ disable-wp;
+ st,neg-edge;
+ bus-width = <4>;
+ vmmc-supply = <&scmi_v3v3>;
+ vqmmc-supply = <&scmi_vddio1>;
+ no-1-8-v;
+ status = "okay";
+};
+
+&spi1 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&spi1_pins_a>;
+ pinctrl-1 = <&spi1_sleep_pins_a>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cs-gpios = <&gpioh 8 GPIO_ACTIVE_LOW>, <&gpioh 3 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ display: display@0 {
+ compatible = "rocktech,rk050hr345-ct106a", "ilitek,ili9806e";
+ reg = <0>;
+ vdd-supply = <®_3v3>;
+ spi-max-frequency = <10000000>;
+ reset-gpios = <&gpiob 6 GPIO_ACTIVE_LOW>;
+ backlight = <&backlight>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <<dc_out>;
+ };
+ };
+ };
+};
+
+&timers2 {
+ status = "okay";
+
+ pwm2: pwm {
+ pinctrl-0 = <&pwm2_pins_a>;
+ pinctrl-1 = <&pwm2_sleep_pins_a>;
+ pinctrl-names = "default", "sleep";
+ status = "okay";
+ };
+};
+
+&timers4 {
+ status = "okay";
+
+ pwm4: pwm {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pwm4_pins_a>;
+ pinctrl-1 = <&pwm4_sleep_pins_a>;
+ status = "okay";
+ };
+};
+
+&usart1 {
+ pinctrl-names = "default", "idle", "sleep";
+ pinctrl-0 = <&usart1_pins_b>;
+ pinctrl-1 = <&usart1_idle_pins_b>;
+ pinctrl-2 = <&usart1_sleep_pins_b>;
+ /delete-property/ dmas;
+ /delete-property/ dma-names;
+ status = "okay";
+};
+
+&usart2 {
+ pinctrl-names = "default", "idle", "sleep";
+ pinctrl-0 = <&usart2_pins_a>;
+ pinctrl-1 = <&usart2_idle_pins_a>;
+ pinctrl-2 = <&usart2_sleep_pins_a>;
+ /delete-property/ dmas;
+ /delete-property/ dma-names;
+ status = "okay";
+};
--
2.43.0
^ permalink raw reply related
* Re: [PATCH 2/3] arm64: dts: socfpga: agilex5: Add SoCDK TSN Config2 board
From: Nazle Asmade, Muhammad Nazim Amirul @ 2026-07-03 7:04 UTC (permalink / raw)
To: Andrew Lunn
Cc: dinguyen@kernel.org, maxime.chevallier@bootlin.com,
rmk+kernel@armlinux.org.uk, krzk+dt@kernel.org,
conor+dt@kernel.org, robh@kernel.org, davem@davemloft.net,
edumazet@google.com, kuba@kernel.org, pabeni@redhat.com,
andrew+netdev@lunn.ch, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org,
linux-kernel@vger.kernel.org
In-Reply-To: <d70a6795-e1a2-43e2-b523-0fc668324674@lunn.ch>
On 1/7/2026 8:47 pm, Andrew Lunn wrote:
>>> # There are a small number of cases where the MAC has hard coded
>>> # delays which cannot be disabled. The 'phy-mode' only describes the
>>> # PCB. The inability to disable the delays in the MAC does not change
>>> # the meaning of 'phy-mode'. It does however mean that a 'phy-mode' of
>>> # 'rgmii' is now invalid, it cannot be supported, since both the PCB
>>> # and the MAC and PHY adding delays cannot result in a functional
>>> # link. Thus the MAC should report a fatal error for any modes which
>>> # cannot be supported. When the MAC implements the delay, it must
>>> # ensure that the PHY does not also implement the same delay. So it
>>> # must modify the phy-mode it passes to the PHY, removing the delay it
>>> # has added. Failure to remove the delay will result in a
>>> # non-functioning link.
>>>
>>> Andrew
>>>
>>> ---
>>> pw-bot: cr
>> Hi Andrew,
>>
>> The delays are provided by the FPGA GMII-to-RGMII converter soft IP,
>> which is hardcoded in the FPGA bitstream and cannot be disabled or
>> modified from the driver side.
>>
>> Using phy-mode = "rgmii" is intentional here — it prevents the PHY from
>> adding its own internal delays on top, since the FPGA converter already
>> provides the full required delay. This is consistent with how all other
>> Agilex5 SoCDK board variants are described, as seen in commit
>> c5637e5ceb4b ("arm64: dts: socfpga: agilex5: Fix phy-mode to rgmii as HW
>> provides clock delay") already in Dinh Nguyen's tree, which applies the
>> same rationale across all Agilex5 boards.
>
> I've become more insistent that designs get this correct. So i don't
> care too much about past systems. Many vendors are having to fix up
> their drivers and DT in order to make new boards consistent.
>
> You can look at your system as the FPGA being the MAC, and the PHY is
> the PHY. The PCB is not providing the delay, the MAC is. This exactly
> fits the description above.
>
> Andrew
Hi Andrew,
Thank you for the clarification. We agree with your framework in
principle, but would like to explain why phy-mode = "rgmii" is the
appropriate description for this specific case.
After getting more information from hw team, for Agilex specific device,
the RGMII timing delays on this board are provided by an FPGA delay
chain (Input/Output Delay Chain primitives in the FPGA fabric). The
reason for using the FPGA rather than the PHY is that the Marvell PHY on
this board only supports 0ns or 2ns delay steps — too coarse to meet the
RGMII timing requirements. The FPGA delay chain provides up to 63 steps
of ~0.1ns precision, which the hardware team has tuned at design time to
achieve correct signal timing.
This delay is fixed in the FPGA bitstream and is invisible to the Linux
driver — the driver cannot read, modify, or even detect the delay value
that was programmed. The driver has no way to know "the MAC is providing
X nanoseconds of delay."
In this situation, the only meaningful action the driver can take is to
instruct the PHY not to add its own delays — which phy-mode = "rgmii"
already achieves correctly. Changing to phy-mode = "rgmii-id" and having
the driver strip the delay before passing to the PHY would produce the
same hardware behaviour (PHY adds zero delay), but would add driver
complexity with no practical benefit, and would misrepresent the FPGA
delay as a driver-managed MAC delay when it is actually a fixed,
board-level hardware calibration.
Could you advise if you still prefer the rgmii-id approach given this
constraint?
BR,
Nazim
^ permalink raw reply
* Re: [PATCH v2 2/6] mm/rmap: use huge_ptep_get() in try_to_unmap_one()
From: David Hildenbrand (Arm) @ 2026-07-03 7:06 UTC (permalink / raw)
To: Dev Jain, muchun.song, osalvador, akpm, ljs, liam
Cc: riel, vbabka, harry, jannh, lance.yang, kas, linux-mm,
linux-kernel, rcampbell, apopple, ziy, matthew.brost,
joshua.hahnjy, rakie.kim, byungchul, gourry, ying.huang, j-nomura,
nao.horiguchi, ak, mel, pfalcato, jpoimboe, dave.hansen, tglx,
catalin.marinas, will, linux-arm-kernel, ryan.roberts,
anshuman.khandual, stable
In-Reply-To: <1b1f6281-2a46-4811-bbea-24a666c0a772@arm.com>
>>> diff --git a/mm/rmap.c b/mm/rmap.c
>>> index 1c77d5dc06e9f..aa8a254efaecc 100644
>>> --- a/mm/rmap.c
>>> +++ b/mm/rmap.c
>>> @@ -2095,11 +2095,16 @@ static bool try_to_unmap_one(struct folio *folio, struct vm_area_struct *vma,
>>> /* Unexpected PMD-mapped THP? */
>>> VM_BUG_ON_FOLIO(!pvmw.pte, folio);
>>>
>>> - /*
>>> - * Handle PFN swap PTEs, such as device-exclusive ones, that
>>> - * actually map pages.
>>> - */
>>
>> That comment now actually belongs above the pte_present() check below.
>
> Oops I mindlessly just copied the comment.
>
> I will then rather put it in the else block which gets the pfn from the softleaf,
> that is the most appropriate.
Works for me, thanks
--
Cheers,
David
^ permalink raw reply
* Re: [PATCH v1 08/11] iommu/tegra241-cmdqv: Require exactly one Stream ID for a vSID
From: Nicolin Chen @ 2026-07-03 7:11 UTC (permalink / raw)
To: Will Deacon
Cc: Robin Murphy, Joerg Roedel (AMD), Jason Gunthorpe, linux-tegra,
linux-arm-kernel, iommu, linux-kernel
In-Reply-To: <3177c49c4d9f24b1dc001d54b5ac30e5061feb7c.1783054570.git.nicolinc@nvidia.com>
On Thu, Jul 02, 2026 at 10:31:34PM -0700, Nicolin Chen wrote:
> diff --git a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
> index 812cc500b4a1e..aa0568e328356 100644
> --- a/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
> +++ b/drivers/iommu/arm/arm-smmu-v3/tegra241-cmdqv.c
> @@ -1249,7 +1249,8 @@ static int tegra241_vintf_init_vsid(struct iommufd_vdevice *vdev)
> if (virt_sid > FIELD_MAX(VINTF_SID_MATCH_VIRT_SID))
> return -EINVAL;
>
> - WARN_ON_ONCE(master->num_streams != 1);
> + if (master->num_streams != 1)
> + return -EINVAL;
Kevin pointed out in the other smmu patch that this should return
-EOPNOTSUPP instead.
https://lore.kernel.org/linux-iommu/SA2PR11MB4844DD8A0367D8E909123F868CF42@SA2PR11MB4844.namprd11.prod.outlook.com/
So, it'd be better to return -EOPNOTSUPP in both places. I'll fix
this when doing a v2.
Nicolin
^ permalink raw reply
* [PATCH v2] mtd: rawnand: lpc32xx_mlc: fail DMA transfers on timeout
From: Pengpeng Hou @ 2026-07-03 7:37 UTC (permalink / raw)
To: Miquel Raynal
Cc: Richard Weinberger, Vignesh Raghavendra, Vladimir Zapolskiy,
Piotr Wojtaszczyk, linux-mtd, linux-arm-kernel, linux-kernel,
stable, Pengpeng Hou
lpc32xx_xmit_dma() starts a DMA transfer and waits up to one second
for its completion, but it ignores the wait result and returns success
after unmapping the buffer.
A timed out read can therefore return success with incomplete data, and
a timed out write can continue the NAND operation without proof that the
DMA payload reached the controller.
Terminate the DMA channel on timeout, unmap the scatterlist through the
existing cleanup path, and return -ETIMEDOUT to the NAND read/write
callers. Initialize the shared cleanup-path result before using it for
dmaengine_prep_slave_sg() failures.
Fixes: 70f7cb78ec53 ("mtd: add LPC32xx MLC NAND driver")
Cc: stable@vger.kernel.org
Reviewed-by: Vladimir Zapolskiy <vz@kernel.org>
Signed-off-by: Pengpeng Hou <pengpeng@iscas.ac.cn>
---
Changes since v1: https://lore.kernel.org/all/20260625003327.11060-1-pengpeng@iscas.ac.cn/
- add Fixes and Cc stable tags as requested by Miquel
- carry Vladimir's Reviewed-by tag
drivers/mtd/nand/raw/lpc32xx_mlc.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/raw/lpc32xx_mlc.c b/drivers/mtd/nand/raw/lpc32xx_mlc.c
index 19b13ae536d4..8f6a89d9ba83 100644
--- a/drivers/mtd/nand/raw/lpc32xx_mlc.c
+++ b/drivers/mtd/nand/raw/lpc32xx_mlc.c
@@ -396,6 +396,7 @@ static int lpc32xx_xmit_dma(struct mtd_info *mtd, void *mem, int len,
struct lpc32xx_nand_host *host = nand_get_controller_data(chip);
struct dma_async_tx_descriptor *desc;
int flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
+ unsigned long time_left;
int res;
sg_init_one(&host->sgl, mem, len);
@@ -410,6 +411,7 @@ static int lpc32xx_xmit_dma(struct mtd_info *mtd, void *mem, int len,
flags);
if (!desc) {
dev_err(mtd->dev.parent, "Failed to prepare slave sg\n");
+ res = -ENXIO;
goto out1;
}
@@ -420,7 +422,13 @@ static int lpc32xx_xmit_dma(struct mtd_info *mtd, void *mem, int len,
dmaengine_submit(desc);
dma_async_issue_pending(host->dma_chan);
- wait_for_completion_timeout(&host->comp_dma, msecs_to_jiffies(1000));
+ time_left = wait_for_completion_timeout(&host->comp_dma,
+ msecs_to_jiffies(1000));
+ if (!time_left) {
+ dmaengine_terminate_sync(host->dma_chan);
+ res = -ETIMEDOUT;
+ goto out1;
+ }
dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1,
DMA_BIDIRECTIONAL);
@@ -428,7 +436,7 @@ static int lpc32xx_xmit_dma(struct mtd_info *mtd, void *mem, int len,
out1:
dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1,
DMA_BIDIRECTIONAL);
- return -ENXIO;
+ return res;
}
static int lpc32xx_read_page(struct nand_chip *chip, uint8_t *buf,
--
2.53.0
^ permalink raw reply related
* [PATCH v2] mtd: rawnand: lpc32xx_slc: fail DMA transfer on completion timeout
From: Pengpeng Hou @ 2026-07-03 7:39 UTC (permalink / raw)
To: Miquel Raynal
Cc: Richard Weinberger, Vignesh Raghavendra, Vladimir Zapolskiy,
Piotr Wojtaszczyk, linux-mtd, linux-arm-kernel, linux-kernel,
stable, Pengpeng Hou
lpc32xx_xmit_dma() waits for the DMA completion callback but ignores
wait_for_completion_timeout(). A timed out DMA transfer is therefore
unmapped and reported as successful to the NAND read/write path.
Return -ETIMEDOUT when the completion wait expires. Terminate the DMA
channel before unmapping the scatterlist so the timed out transfer cannot
continue to access the buffer after the error is returned.
Fixes: 2944a44da09e ("mtd: add LPC32xx SLC NAND driver")
Cc: stable@vger.kernel.org
Reviewed-by: Vladimir Zapolskiy <vz@kernel.org>
Signed-off-by: Pengpeng Hou <pengpeng@iscas.ac.cn>
---
Changes since v1: https://lore.kernel.org/all/20260624144127.69075-1-pengpeng@iscas.ac.cn/
- add Fixes and Cc stable tags as requested by Miquel
- carry Vladimir's Reviewed-by tag
drivers/mtd/nand/raw/lpc32xx_slc.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/raw/lpc32xx_slc.c b/drivers/mtd/nand/raw/lpc32xx_slc.c
index 3ca30e7dce33..10c8080207f4 100644
--- a/drivers/mtd/nand/raw/lpc32xx_slc.c
+++ b/drivers/mtd/nand/raw/lpc32xx_slc.c
@@ -430,6 +430,7 @@ static int lpc32xx_xmit_dma(struct mtd_info *mtd, dma_addr_t dma,
struct dma_async_tx_descriptor *desc;
int flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
int res;
+ unsigned long time_left;
host->dma_slave_config.direction = dir;
host->dma_slave_config.src_addr = dma;
@@ -467,12 +468,19 @@ static int lpc32xx_xmit_dma(struct mtd_info *mtd, dma_addr_t dma,
dmaengine_submit(desc);
dma_async_issue_pending(host->dma_chan);
- wait_for_completion_timeout(&host->comp, msecs_to_jiffies(1000));
+ time_left = wait_for_completion_timeout(&host->comp,
+ msecs_to_jiffies(1000));
+ if (!time_left) {
+ dmaengine_terminate_sync(host->dma_chan);
+ res = -ETIMEDOUT;
+ } else {
+ res = 0;
+ }
dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1,
DMA_BIDIRECTIONAL);
- return 0;
+ return res;
out1:
dma_unmap_sg(host->dma_chan->device->dev, &host->sgl, 1,
DMA_BIDIRECTIONAL);
--
2.53.0
^ permalink raw reply related
* Re: [PATCH] mfd: stm32-timers: depopulate child devices on populate failure
From: Lee Jones @ 2026-07-03 7:47 UTC (permalink / raw)
To: Pengpeng Hou
Cc: Fabrice Gasnier, Maxime Coquelin, Alexandre Torgue, linux-stm32,
linux-arm-kernel, linux-kernel
In-Reply-To: <20260703065016.97181-1-pengpeng@iscas.ac.cn>
On Fri, 03 Jul 2026, Pengpeng Hou wrote:
> Hi Lee,
>
> Thanks for taking a look.
>
> I checked devm_of_platform_populate(), but I don't think it covers this
> particular failure path on its own.
>
> devm_of_platform_populate() only installs the devres cleanup after
> of_platform_populate() has returned success. If of_platform_populate()
> returns an error after creating some earlier children, the helper just
> frees its devres record and those partial children are not depopulated.
>
> For stm32-timers, I think we still need the explicit ordering used by
> remove: depopulate children before stm32_timers_dma_remove(). The child
> drivers get the parent drvdata, and the PWM child can call the parent
> stm32_timers_dma_burst_read() helper, so releasing the parent DMA
> channels while partially-created children remain would keep the same
> ordering problem the remove path avoids.
>
> I agree the inline unwind is not the clearest form. I can send a v2
> using a normal goto unwind label and a short comment explaining the
> partial-populate case, unless you prefer a different shape.
I'm not concerned about where in the file the call sits. Calls like
this that fail usually do so cleanly. I think this deserves a wider
piece of work that ensures that of_platform_populate() doesn't leave
dangling resources when it fails.
Also, why doesn't every call to of_platform_populate() have this?
--
Lee Jones
^ permalink raw reply
* [PATCH v3] dt-bindings: arm-smmu: qcom: Add compatible for Maili SoC
From: Jingyi Wang @ 2026-07-03 7:50 UTC (permalink / raw)
To: Will Deacon, Robin Murphy, Joerg Roedel (AMD), Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: aiqun.yu, tingwei.zhang, trilok.soni, yijie.yang,
linux-arm-kernel, iommu, devicetree, linux-kernel, Jingyi Wang
Qualcomm Maili SoC includes apps smmu that implements arm,mmu-500,
which is used to translate device-visible virtual addresses to
physical addresses. Add compatible for it.
Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
---
Changes in v3:
- add smmu binding to the block that disallows clocks
- Link to v2: https://lore.kernel.org/r/20260628-maili-smmu-v2-1-87448a7678ec@oss.qualcomm.com
Changes in v2:
- patch rebase
- Link to v1: https://lore.kernel.org/r/20260524-maili-smmu-v1-1-ec85b12fda83@oss.qualcomm.com
---
Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
index a701dec2fa0a..fd095161f6be 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
@@ -39,6 +39,7 @@ properties:
- qcom,glymur-smmu-500
- qcom,hawi-smmu-500
- qcom,kaanapali-smmu-500
+ - qcom,maili-smmu-500
- qcom,milos-smmu-500
- qcom,nord-smmu-500
- qcom,qcm2290-smmu-500
@@ -621,6 +622,7 @@ allOf:
- qcom,glymur-smmu-500
- qcom,hawi-smmu-500
- qcom,kaanapali-smmu-500
+ - qcom,maili-smmu-500
- qcom,milos-smmu-500
- qcom,nord-smmu-500
- qcom,qcs615-smmu-500
---
base-commit: 3d5670d672ae08b8c534b7beed6f57c8b44e7b43
change-id: 20260628-maili-smmu-9ed0f2c189ad
Best regards,
--
Jingyi Wang <jingyi.wang@oss.qualcomm.com>
^ permalink raw reply related
* Re: [PATCH 2/2] ASoC: meson: aiu-formatter: remove pipeline reset from prepare
From: Jerome Brunet @ 2026-07-03 7:58 UTC (permalink / raw)
To: Valerio Setti
Cc: Liam Girdwood, Mark Brown, Jaroslav Kysela, Takashi Iwai,
Neil Armstrong, Kevin Hilman, Martin Blumenstingl, linux-sound,
linux-arm-kernel, linux-amlogic, linux-kernel
In-Reply-To: <20260702-fix-24-bit-i2s-playback-v1-2-bcd3a43fe32a@baylibre.com>
On jeu. 02 juil. 2026 at 12:56, Valerio Setti <vsetti@baylibre.com> wrote:
> 'aiu-formatter-i2s' already performs the very same reset in
> 'aiu_fifo_i2s_trigger' for all relevant trigger scenarios. There is no
> need to duplicate the operation in the formatter.
>
> Signed-off-by: Valerio Setti <vsetti@baylibre.com>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
> ---
> sound/soc/meson/aiu-formatter-i2s.c | 9 ++++-----
> 1 file changed, 4 insertions(+), 5 deletions(-)
>
> diff --git a/sound/soc/meson/aiu-formatter-i2s.c b/sound/soc/meson/aiu-formatter-i2s.c
> index b4604734fe88..cb554c2e7ce4 100644
> --- a/sound/soc/meson/aiu-formatter-i2s.c
> +++ b/sound/soc/meson/aiu-formatter-i2s.c
> @@ -13,7 +13,6 @@
> #define AIU_I2S_SOURCE_DESC_MODE_8CH BIT(0)
> #define AIU_I2S_SOURCE_DESC_MODE_24BIT BIT(5)
> #define AIU_I2S_SOURCE_DESC_MODE_32BIT BIT(9)
> -#define AIU_RST_SOFT_I2S_FAST BIT(0)
>
> #define AIU_I2S_DAC_CFG_MSB_FIRST BIT(2)
>
> @@ -55,11 +54,11 @@ static int aiu_formatter_i2s_prepare(struct regmap *map,
> {
> /* Always operate in split (classic interleaved) mode */
> unsigned int desc = 0;
> - unsigned int tmp;
>
> - /* Reset required to update the pipeline */
> - regmap_write(map, AIU_RST_SOFT, AIU_RST_SOFT_I2S_FAST);
> - regmap_read(map, AIU_I2S_SYNC, &tmp);
> + /*
> + * Pipeline reset is already implemented in aiu_fifo_i2s_trigger() at
> + * trigger time.
> + */
>
> switch (ts->physical_width) {
> case 16: /* Nothing to do */
--
Jerome
^ permalink raw reply
* Re: [PATCH v1 1/5] iommu/arm-smmu-v3-iommufd: Reject unsupported bits in invalidation commands
From: Nicolin Chen @ 2026-07-03 8:00 UTC (permalink / raw)
To: Tian, Kevin
Cc: Will Deacon, Jason Gunthorpe, Lu Baolu, Robin Murphy,
joro@8bytes.org, David Woodhouse,
linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev,
linux-kernel@vger.kernel.org
In-Reply-To: <CO1PR11MB4835A412EADC0D56A8BDBBFC8CF42@CO1PR11MB4835.namprd11.prod.outlook.com>
On Fri, Jul 03, 2026 at 06:20:37AM +0000, Tian, Kevin wrote:
> > From: Nicolin Chen <nicolinc@nvidia.com>
> > + case CMDQ_OP_ATC_INV:
> > + /*
> > + * Exclude the Global bit: it makes the SMMU ignore the SID
> > and
> > + * invalidate the ATC of every device, not just the guest's.
> > + */
>
> I suppose the Global bit in vcmdq is guaranteed by HW to be contained within
> the vcmdq, then the SMMU will convert it into multiple INV cmds sent to
> devices associated with the vcmdq?
Actually, this piece is wrong. I double-checked the spec, the
Global bit isn't about SID but SSID (should be provided too).
So, the Global bit should be allowed. I need to fix it..
Similarly for VCMDQ, it is allowed. HW only validates whether
the given SID/BDF is programmed into the VINTF or not.
Thanks (for the question)!
Nicolin
^ permalink raw reply
* [PATCH v4 0/4] can: rockchip: add RK3588 CAN support
From: Cunhao Lu @ 2026-07-03 8:01 UTC (permalink / raw)
To: Marc Kleine-Budde, kernel, Vincent Mailhol, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner
Cc: linux-can, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel, Cunhao Lu, Krzysztof Kozlowski, Heiko Stuebner
Add support for the RK3588 CAN controller.
RK3588 integrates three CAN-FD controllers that are closely related to
the existing Rockchip CAN-FD IP already supported in the kernel. The
RK3588 variant is not fully compatible with RK3568v2 because the RX
FIFO count register field has a different layout.
This series therefore:
- extends the existing Rockchip CAN-FD binding with the
rockchip,rk3588-canfd compatible
- adds a dedicated RK3588 match entry and devtype in the driver
- describes the three CAN controller nodes in rk3588-base.dtsi
- enables CAN on the RK3588 Tiger Haikou board
RK3588 encodes RX_FIFO_CNT in bits 7:5 instead of 6:4. This
difference was found by comparing Rockchip's vendor kernel 6.1 CAN
support for RK3568 and RK3588, and was also confirmed by runtime
testing.
RK3588 uses the existing erratum 5 empty-FIFO workaround. Based on
Heiko's testing, v2 also enables the erratum 6 workaround for extended
frames being transmitted as standard frames.
CAN-FD is enabled for RK3588. The BRS bus-off issue seen in earlier
testing was caused by the transmit delay compensation setting. With
RKCANFD_REG_TRANSMIT_DELAY_COMPENSATION programmed to 0 on RK3588,
CAN-FD with BRS works in local testing.
Tested on an embedfire,rk3588-lubancat-5io board with can0/can1
directly connected, no other device on the bus, 60 Ohm bus
termination, and a 300 MHz CAN clock. The test used 500 kbit/s
arbitration bitrate and 1, 3 and 5 Mbit/s data bitrates. The 5 Mbit/s
data phase test ran for 15 minutes with:
ip link set can0 type can bitrate 500000 sample-point 0.8 dbitrate 5000000 dsample-point 0.8 fd on berr-reporting on
ip link set can1 type can bitrate 500000 sample-point 0.8 dbitrate 5000000 dsample-point 0.8 fd on berr-reporting on
cangen can0 -I 2 -Li -Di -p 10 -f -g 1 -c32 -b
cansequence -rv can1 -f
The receiver reported continuous sequence wrap-around messages up to
sequence wrap around (37219). Both interfaces reported 9528377 packets
and 150667356 bytes, with 0 bus-errors, 0 error-warn, 0 error-pass and
0 bus-off events.
Signed-off-by: Cunhao Lu <1579567540@qq.com>
---
v3 -> v4:
- disable TDC on RK3588 by programming
RKCANFD_REG_TRANSMIT_DELAY_COMPENSATION to 0
- drop RKCANFD_QUIRK_CANFD_BROKEN for RK3588 and enable CAN-FD support
- document successful RK3588 CAN-FD/BRS testing at 500 kbit/s
arbitration bitrate and 1, 3 and 5 Mbit/s data bitrates
- collect Krzysztof's Acked-by tag for the binding patch
- Link to v3: https://patch.msgid.link/20260703-master-v3-0-6d56de6fd2f3@qq.com
v2 -> v3:
- Move the Changelog below ---
- Collect Heiko's Reviewed-by and the driver patch Tested-by tag
- Use Co-developed-by for Heiko's RK3588 contributions and add his
Signed-off-by
v1 -> v2:
- use real author name
- fold the single-compatible entries into an enum, as suggested by Krzysztof
- enable the erratum 6 workaround for RK3588 based on Heiko's testing
- add Heiko's RK3588 Tiger Haikou CAN enablement patch
- keep RKCANFD_QUIRK_CANFD_BROKEN enabled for RK3588 so CAN-FD stays disabled
- document the RK3588 CAN-FD/BRS bus-off failure mode
---
Cunhao Lu (3):
dt-bindings: can: rockchip: add rk3588 CAN-FD compatible
can: rockchip: add RK3588 CAN support
arm64: dts: rockchip: add CAN-FD nodes for RK3588
Heiko Stuebner (1):
arm64: dts: rockchip: Enable CAN controller on RK3588-Tiger-Haikou
.../bindings/net/can/rockchip,rk3568v2-canfd.yaml | 4 ++-
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 39 ++++++++++++++++++++++
.../boot/dts/rockchip/rk3588-tiger-haikou.dts | 6 ++++
drivers/net/can/rockchip/rockchip_canfd-core.c | 17 ++++++++++
drivers/net/can/rockchip/rockchip_canfd-rx.c | 5 ++-
drivers/net/can/rockchip/rockchip_canfd.h | 14 +++++++-
6 files changed, 82 insertions(+), 3 deletions(-)
---
base-commit: dc59e4fea9d83f03bad6bddf3fa2e52491777482
change-id: 20260702-master-8c52be892a3f
Best regards,
--
Cunhao Lu <1579567540@qq.com>
^ permalink raw reply
* [PATCH v4 1/4] dt-bindings: can: rockchip: add rk3588 CAN-FD compatible
From: Cunhao Lu @ 2026-07-03 8:01 UTC (permalink / raw)
To: Marc Kleine-Budde, kernel, Vincent Mailhol, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner
Cc: linux-can, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel, Cunhao Lu, Krzysztof Kozlowski
In-Reply-To: <20260703-master-v4-0-47d40bbf5fda@qq.com>
RK3588 integrates a Rockchip CAN-FD controller variant that is not
fully compatible with RK3568v2. The RX FIFO count register field is
encoded in bits 7:5 on RK3588, while RK3568v2 uses bits 6:4.
Add a dedicated rockchip,rk3588-canfd compatible to describe this
variant. Do not use rockchip,rk3568v2-canfd as a fallback, because that
would describe a register layout that does not match the hardware.
Signed-off-by: Cunhao Lu <1579567540@qq.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
---
v3 -> v4:
- Collect Krzysztof's Acked-by tag.
v2 -> v3:
- Move the Changelog below ---
- Collect Heiko's Reviewed-by tag
v1 -> v2:
- Use enum for the single-compatible entries, as suggested by Krzysztof.
- Reword the commit message to explain the hardware difference instead
of referring to Linux driver match data.
---
.../devicetree/bindings/net/can/rockchip,rk3568v2-canfd.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/net/can/rockchip,rk3568v2-canfd.yaml b/Documentation/devicetree/bindings/net/can/rockchip,rk3568v2-canfd.yaml
index a077c0330013..81e2b6dfeb02 100644
--- a/Documentation/devicetree/bindings/net/can/rockchip,rk3568v2-canfd.yaml
+++ b/Documentation/devicetree/bindings/net/can/rockchip,rk3568v2-canfd.yaml
@@ -16,7 +16,9 @@ allOf:
properties:
compatible:
oneOf:
- - const: rockchip,rk3568v2-canfd
+ - enum:
+ - rockchip,rk3568v2-canfd
+ - rockchip,rk3588-canfd
- items:
- const: rockchip,rk3568v3-canfd
- const: rockchip,rk3568v2-canfd
--
2.34.1
^ permalink raw reply related
* [PATCH v4 2/4] can: rockchip: add RK3588 CAN support
From: Cunhao Lu @ 2026-07-03 8:01 UTC (permalink / raw)
To: Marc Kleine-Budde, kernel, Vincent Mailhol, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner
Cc: linux-can, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel, Cunhao Lu, Heiko Stuebner
In-Reply-To: <20260703-master-v4-0-47d40bbf5fda@qq.com>
Add support for the RK3588 CAN controller by introducing a dedicated
model ID and OF match entry.
The block is closely related to the existing RK3568 variants, but it
cannot reuse their match data unchanged. In particular, RK3588
encodes RX_FIFO_CNT in bits 7:5 instead of 6:4, so the RX path needs
SoC-specific handling.
The RX FIFO count bitfield difference was found by comparing Rockchip's
vendor kernel 6.1 CAN support for RK3568 and RK3588. Runtime testing on
RK3588 also confirms that bits 7:5 are needed.
Enable the existing erratum 5 empty-FIFO workaround for RK3588.
Heiko reproduced erratum 6 on RK3588, so enable that workaround as
well.
CAN-FD is enabled for RK3588. The BRS bus-off issue seen in earlier
testing was caused by the transmit delay compensation setting. With
RKCANFD_REG_TRANSMIT_DELAY_COMPENSATION programmed to 0 on RK3588,
CAN-FD with BRS works in local testing.
Tested on an embedfire,rk3588-lubancat-5io board with can0/can1
directly connected, no other device on the bus, 60 Ohm bus
termination, and a 300 MHz CAN clock. Runtime testing used 500 kbit/s
arbitration bitrate and 1, 3 and 5 Mbit/s data bitrates. The 5 Mbit/s
data phase test ran for 15 minutes with cangen using BRS and
cansequence on the receiver. Both interfaces reported 9528377 packets
and 150667356 bytes, with 0 bus-errors, 0 error-warn, 0 error-pass and
0 bus-off events.
Co-developed-by: Heiko Stuebner <heiko.stuebner@cherry.de>
Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
Signed-off-by: Cunhao Lu <1579567540@qq.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
---
v3 -> v4:
- Disable TDC on RK3588 by programming
RKCANFD_REG_TRANSMIT_DELAY_COMPENSATION to 0.
- Drop RKCANFD_QUIRK_CANFD_BROKEN for RK3588 and enable CAN-FD support.
- Document successful RK3588 CAN-FD/BRS testing.
v2 -> v3:
- Use Co-developed-by for Heiko's RK3588 contributions and add his
Signed-off-by
- Collect Heiko's Reviewed-by and Tested-by tags
---
drivers/net/can/rockchip/rockchip_canfd-core.c | 17 +++++++++++++++++
drivers/net/can/rockchip/rockchip_canfd-rx.c | 5 ++++-
drivers/net/can/rockchip/rockchip_canfd.h | 14 +++++++++++++-
3 files changed, 34 insertions(+), 2 deletions(-)
diff --git a/drivers/net/can/rockchip/rockchip_canfd-core.c b/drivers/net/can/rockchip/rockchip_canfd-core.c
index 29de0c01e4ed..37c1c22c40c9 100644
--- a/drivers/net/can/rockchip/rockchip_canfd-core.c
+++ b/drivers/net/can/rockchip/rockchip_canfd-core.c
@@ -50,6 +50,12 @@ static const struct rkcanfd_devtype_data rkcanfd_devtype_data_rk3568v3 = {
RKCANFD_QUIRK_CANFD_BROKEN,
};
+static const struct rkcanfd_devtype_data rkcanfd_devtype_data_rk3588 = {
+ .model = RKCANFD_MODEL_RK3588,
+ .quirks = RKCANFD_QUIRK_RK3568_ERRATUM_5 |
+ RKCANFD_QUIRK_RK3568_ERRATUM_6,
+};
+
static const char *__rkcanfd_get_model_str(enum rkcanfd_model model)
{
switch (model) {
@@ -57,6 +63,8 @@ static const char *__rkcanfd_get_model_str(enum rkcanfd_model model)
return "rk3568v2";
case RKCANFD_MODEL_RK3568V3:
return "rk3568v3";
+ case RKCANFD_MODEL_RK3588:
+ return "rk3588";
}
return "<unknown>";
@@ -148,6 +156,12 @@ static int rkcanfd_set_bittiming(struct rkcanfd_priv *priv)
rkcanfd_write(priv, RKCANFD_REG_FD_DATA_BITTIMING, reg_dbt);
+ /* RK3588 CAN-FD BRS works with TDC disabled. */
+ if (priv->devtype_data.model == RKCANFD_MODEL_RK3588) {
+ rkcanfd_write(priv, RKCANFD_REG_TRANSMIT_DELAY_COMPENSATION, 0);
+ return 0;
+ }
+
tdco = (priv->can.clock.freq / dbt->bitrate) * 2 / 3;
tdco = min(tdco, FIELD_MAX(RKCANFD_REG_TRANSMIT_DELAY_COMPENSATION_TDC_OFFSET));
@@ -846,6 +860,9 @@ static const struct of_device_id rkcanfd_of_match[] = {
}, {
.compatible = "rockchip,rk3568v3-canfd",
.data = &rkcanfd_devtype_data_rk3568v3,
+ }, {
+ .compatible = "rockchip,rk3588-canfd",
+ .data = &rkcanfd_devtype_data_rk3588,
}, {
/* sentinel */
},
diff --git a/drivers/net/can/rockchip/rockchip_canfd-rx.c b/drivers/net/can/rockchip/rockchip_canfd-rx.c
index 475c0409e215..24e87daa1df0 100644
--- a/drivers/net/can/rockchip/rockchip_canfd-rx.c
+++ b/drivers/net/can/rockchip/rockchip_canfd-rx.c
@@ -281,7 +281,10 @@ rkcanfd_rx_fifo_get_len(const struct rkcanfd_priv *priv)
{
const u32 reg = rkcanfd_read(priv, RKCANFD_REG_RX_FIFO_CTRL);
- return FIELD_GET(RKCANFD_REG_RX_FIFO_CTRL_RX_FIFO_CNT, reg);
+ if (priv->devtype_data.model == RKCANFD_MODEL_RK3588)
+ return FIELD_GET(RKCANFD_REG_RX_FIFO_CTRL_RX_FIFO_CNT_RK3588, reg);
+
+ return FIELD_GET(RKCANFD_REG_RX_FIFO_CTRL_RX_FIFO_CNT_RK3568, reg);
}
int rkcanfd_handle_rx_int(struct rkcanfd_priv *priv)
diff --git a/drivers/net/can/rockchip/rockchip_canfd.h b/drivers/net/can/rockchip/rockchip_canfd.h
index 93131c7d7f54..95bea9bfd8a2 100644
--- a/drivers/net/can/rockchip/rockchip_canfd.h
+++ b/drivers/net/can/rockchip/rockchip_canfd.h
@@ -214,7 +214,8 @@
#define RKCANFD_REG_TXEVENT_FIFO_CTRL_TXE_FIFO_ENABLE BIT(0)
#define RKCANFD_REG_RX_FIFO_CTRL 0x118
-#define RKCANFD_REG_RX_FIFO_CTRL_RX_FIFO_CNT GENMASK(6, 4)
+#define RKCANFD_REG_RX_FIFO_CTRL_RX_FIFO_CNT_RK3568 GENMASK(6, 4)
+#define RKCANFD_REG_RX_FIFO_CTRL_RX_FIFO_CNT_RK3588 GENMASK(7, 5)
#define RKCANFD_REG_RX_FIFO_CTRL_RX_FIFO_FULL_WATERMARK GENMASK(3, 1)
#define RKCANFD_REG_RX_FIFO_CTRL_RX_FIFO_ENABLE BIT(0)
@@ -331,6 +332,11 @@
* rarely with the standard clock of 300 MHz, but almost immediately
* at 80 MHz.
*
+ * Tests on the rk3588 show the same empty FIFO condition.
+ * In that setup rx_fifo_empty_errors increments when the bus
+ * transitions from idle to high CAN-FD load and stops growing once
+ * the bus reaches a steady state.
+ *
* To workaround this problem, check for empty FIFO with
* rkcanfd_fifo_header_empty() in rkcanfd_handle_rx_int_one() and exit
* early.
@@ -344,6 +350,8 @@
/* Erratum 6: The CAN controller's transmission of extended frames may
* intermittently change into standard frames
*
+ * Tests on the rk3588 show the same problem.
+ *
* Work around this issue by activating self reception (RXSTX). If we
* have pending TX CAN frames, check all RX'ed CAN frames in
* rkcanfd_rxstx_filter().
@@ -424,6 +432,9 @@
* cansequence -rv -i 1
*
* - TX starvation after repeated Bus-Off
+ * Tests on the rk3588 show the same problem. In a
+ * 10-cycle Bus-Off recovery test, 9 cycles failed to send after the
+ * controller restarted.
* To reproduce:
* host:
* sleep 3 && cangen can0 -I2 -Li -Di -p10 -g 0.0
@@ -434,6 +445,7 @@
enum rkcanfd_model {
RKCANFD_MODEL_RK3568V2 = 0x35682,
RKCANFD_MODEL_RK3568V3 = 0x35683,
+ RKCANFD_MODEL_RK3588 = 0x3588,
};
struct rkcanfd_devtype_data {
--
2.34.1
^ permalink raw reply related
* [PATCH v4 4/4] arm64: dts: rockchip: Enable CAN controller on RK3588-Tiger-Haikou
From: Cunhao Lu @ 2026-07-03 8:01 UTC (permalink / raw)
To: Marc Kleine-Budde, kernel, Vincent Mailhol, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner
Cc: linux-can, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel, Cunhao Lu, Heiko Stuebner
In-Reply-To: <20260703-master-v4-0-47d40bbf5fda@qq.com>
From: Heiko Stuebner <heiko.stuebner@cherry.de>
CAN0 is piped through the Q7-connector to the CAN-Header on the Haikou
base-board, so enable support for it there.
At least on RK3588-Tiger, the CAN clocks default to 99MHz, limiting
usable CAN bitrates without skew. Errata documentation mentions
300MHz as the default frequency on RK3568, so replicate this here
to allow more bitrates.
Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
Signed-off-by: Cunhao Lu <1579567540@qq.com>
---
arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts b/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts
index 873fbeb8daa1..6273e695b039 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger-haikou.dts
@@ -155,6 +155,12 @@ vddd_audio_1v6: regulator-vddd-audio-1v6 {
};
};
+&can0 {
+ assigned-clocks = <&cru CLK_CAN0>;
+ assigned-clock-rates = <300000000>;
+ status = "okay";
+};
+
&combphy2_psu {
status = "okay";
};
--
2.34.1
^ permalink raw reply related
* [PATCH v4 3/4] arm64: dts: rockchip: add CAN-FD nodes for RK3588
From: Cunhao Lu @ 2026-07-03 8:01 UTC (permalink / raw)
To: Marc Kleine-Budde, kernel, Vincent Mailhol, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Heiko Stuebner
Cc: linux-can, devicetree, linux-arm-kernel, linux-rockchip,
linux-kernel, Cunhao Lu, Heiko Stuebner
In-Reply-To: <20260703-master-v4-0-47d40bbf5fda@qq.com>
Describe the three CAN-FD controllers integrated in RK3588 in the base
SoC .dtsi.
Add CAN0, CAN1 and CAN2 nodes with their register ranges, interrupts,
clocks and resets, and keep them disabled by default so board DTS files
can enable them as needed.
Co-developed-by: Heiko Stuebner <heiko.stuebner@cherry.de>
Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
Signed-off-by: Cunhao Lu <1579567540@qq.com>
---
v2 -> v3:
- Use Co-developed-by for Heiko's RK3588 contributions and add his
Signed-off-by
---
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 39 +++++++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
index fc1fdbfd3162..b340973775c5 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -2648,6 +2648,45 @@ dmac1: dma-controller@fea30000 {
#dma-cells = <1>;
};
+ can0: can@fea50000 {
+ compatible = "rockchip,rk3588-canfd";
+ reg = <0x0 0xfea50000 0x0 0x1000>;
+ interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru CLK_CAN0>, <&cru PCLK_CAN0>;
+ clock-names = "baud", "pclk";
+ resets = <&cru SRST_CAN0>, <&cru SRST_P_CAN0>;
+ reset-names = "core", "apb";
+ pinctrl-names = "default";
+ pinctrl-0 = <&can0m0_pins>;
+ status = "disabled";
+ };
+
+ can1: can@fea60000 {
+ compatible = "rockchip,rk3588-canfd";
+ reg = <0x0 0xfea60000 0x0 0x1000>;
+ interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru CLK_CAN1>, <&cru PCLK_CAN1>;
+ clock-names = "baud", "pclk";
+ resets = <&cru SRST_CAN1>, <&cru SRST_P_CAN1>;
+ reset-names = "core", "apb";
+ pinctrl-names = "default";
+ pinctrl-0 = <&can1m0_pins>;
+ status = "disabled";
+ };
+
+ can2: can@fea70000 {
+ compatible = "rockchip,rk3588-canfd";
+ reg = <0x0 0xfea70000 0x0 0x1000>;
+ interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&cru CLK_CAN2>, <&cru PCLK_CAN2>;
+ clock-names = "baud", "pclk";
+ resets = <&cru SRST_CAN2>, <&cru SRST_P_CAN2>;
+ reset-names = "core", "apb";
+ pinctrl-names = "default";
+ pinctrl-0 = <&can2m0_pins>;
+ status = "disabled";
+ };
+
i2c1: i2c@fea90000 {
compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
reg = <0x0 0xfea90000 0x0 0x1000>;
--
2.34.1
^ permalink raw reply related
* Re: [PATCH 3/3] net: stmmac: dwmac-socfpga: Add mac-mode DT property support
From: Nazle Asmade, Muhammad Nazim Amirul @ 2026-07-03 8:10 UTC (permalink / raw)
To: Andrew Lunn
Cc: dinguyen@kernel.org, maxime.chevallier@bootlin.com,
rmk+kernel@armlinux.org.uk, krzk+dt@kernel.org,
conor+dt@kernel.org, robh@kernel.org, davem@davemloft.net,
edumazet@google.com, kuba@kernel.org, pabeni@redhat.com,
andrew+netdev@lunn.ch, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, netdev@vger.kernel.org,
linux-kernel@vger.kernel.org
In-Reply-To: <e489be4a-5940-46e5-ae06-b78f1c919352@lunn.ch>
On 1/7/2026 10:43 pm, Andrew Lunn wrote:
> On Tue, Jun 30, 2026 at 06:31:08AM -0700, muhammad.nazim.amirul.nazle.asmade@altera.com wrote:
>> From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
>>
>> Russell King's commit de696c63c1dc ("net: stmmac: socfpga: convert to
>> use phy_interface") replaced mac_interface with phy_interface in
>> socfpga_get_plat_phymode(), noting that no upstream DTS files set the
>> "mac-mode" property, making the two values identical.
>>
>> The Agilex5 SoCDK TSN Config2 board is an exception: its gmac1 TSN
>> port uses GMII internally in the MAC while the PHY-side interface is
>> RGMII, so mac-mode and phy-mode differ. Without restoring mac_interface
>> support, the MAC is configured with RGMII instead of GMII, causing
>> connectivity failures on this board.
>>
>> Add socfpga_of_get_mac_mode() to read the optional "mac-mode" DT
>> property and store it in a new mac_interface field. When the property
>> is absent, mac_interface falls back to phy_interface, preserving
>> the existing behaviour for all other boards.
>
> I don't actually see a need for mac-mode. From what you are saying,
> there is no choice. The MAC is hard wired to the converter block. So
> you can just look at the compatible. You are going to need to use the
> compatible anyway, to mask the phy-mode to handle the "MAC" doing the
> RGMII delays.
>
> Andrew
>
Hi Maxime, Andrew
Thanks for the reviews!
Hi Andrew,
The challenge with using compatible is that the TSN Config2 board has
two ports — only gmac1 uses the GMII-to-RGMII converter, while gmac2
connects directly to its PHY. A board-level compatible check would need
additional logic to know which port to apply the GMII override to.
With mac-mode, the configuration is per-port in the DTS — consistent
with how altr,emac-splitter works today. I also addressing Maxime's
feedback in v2 by unifying the splitter and mac-mode code paths.
BR,
Nazim
^ permalink raw reply
* Re: [PATCH v6 02/12] dt-bindings: soc: zte: Add zx297520v3 matrix clock and reset bindings
From: Krzysztof Kozlowski @ 2026-07-03 6:07 UTC (permalink / raw)
To: Stefan Dösinger
Cc: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Philipp Zabel, Brian Masney, linux-clk, devicetree,
linux-kernel, linux-arm-kernel
In-Reply-To: <20260702-zx29clk-v6-2-377b704f80c4@gmail.com>
On Thu, Jul 02, 2026 at 11:27:57PM +0300, Stefan Dösinger wrote:
> This controller contains clocks and resets for high speed devices on the
> zx297520v3 board and hardware spinlocks that I expect will be necessary
> to communicate correctly with the LTE DSP firmware blob.
>
> A simple MFD driver will instantiate independent clock, reset and hwlock
> drivers.
>
> Signed-off-by: Stefan Dösinger <stefandoesinger@gmail.com>
>
> ---
>
> Changes
> v5->v6:
> Add syscon compatible - Conor suggested this after v4 and I forgot it in v5.
Please explain why. syscon has meaning in bindings, so if this is not
accessed outside, then it is not a syscon.
Best regards,
Krzysztof
^ permalink raw reply
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